* [PATCH 5/8] OMAP4: hwmod data: Add mailbox
From: Benoit Cousson @ 2011-02-17 10:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297938289-8678-1-git-send-email-b-cousson@ti.com>
Mailbox hwmod data for omap4.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
[b-cousson at ti.com: Re-order the structures
and remove the irq line name]
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 68 +++++++++++++++++++++++++++-
1 files changed, 67 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index aafe60d..efdf266 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -530,7 +530,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
* ipu
* iss
* kbd
- * mailbox
* mcasp
* mcbsp1
* mcbsp2
@@ -2006,6 +2005,70 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
};
/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &omap44xx_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap44xx_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
+ { .irq = 26 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x4a0f4000,
+ .pa_end = 0x4a0f41ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_cfg -> mailbox */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_mailbox_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
+ &omap44xx_l4_cfg__mailbox,
+};
+
+static struct omap_hwmod omap44xx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap44xx_mailbox_hwmod_class,
+ .mpu_irqs = omap44xx_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
@@ -3539,6 +3602,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
&omap44xx_iva_seq0_hwmod,
&omap44xx_iva_seq1_hwmod,
+ /* mailbox class */
+ &omap44xx_mailbox_hwmod,
+
/* mcspi class */
&omap44xx_mcspi1_hwmod,
&omap44xx_mcspi2_hwmod,
--
1.7.0.4
^ permalink raw reply related
* [PATCH 4/8] OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
From: Benoit Cousson @ 2011-02-17 10:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297938289-8678-1-git-send-email-b-cousson@ti.com>
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
interconnect paths depending of the access initiator (MPU vs. SDMA).
In the case of the DSS, both L3 direct path and L4 CFG path can be
used to access all the DSS IPs. The two ocp_ip already exists to support
the two address spaces.
+------------+-- L3_MAIN --+ MPU
IP | |
+-- L4_CFG --+
L3 main address range is specified first, since it is used by default.
dss is also considered as an IP as dispc, rfbi, and named as dss_core.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
[b-cousson at ti.com: Re-organize structures to match file
convention and remove irq entry from dss_hwmod]
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 612 +++++++++++++++++++++++++++-
1 files changed, 604 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 37b3024..aafe60d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1,7 +1,7 @@
/*
* Hardware modules present on the OMAP44xx chips
*
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation
*
* Paul Walmsley
@@ -43,6 +43,7 @@
static struct omap_hwmod omap44xx_dma_system_hwmod;
static struct omap_hwmod omap44xx_dmm_hwmod;
static struct omap_hwmod omap44xx_dsp_hwmod;
+static struct omap_hwmod omap44xx_dss_hwmod;
static struct omap_hwmod omap44xx_emif_fw_hwmod;
static struct omap_hwmod omap44xx_iva_hwmod;
static struct omap_hwmod omap44xx_l3_instr_hwmod;
@@ -213,6 +214,14 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* dss -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
+ .master = &omap44xx_dss_hwmod,
+ .slave = &omap44xx_l3_main_1_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l3_main_2 -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
.master = &omap44xx_l3_main_2_hwmod,
@@ -240,6 +249,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
/* l3_main_1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
&omap44xx_dsp__l3_main_1,
+ &omap44xx_dss__l3_main_1,
&omap44xx_l3_main_2__l3_main_1,
&omap44xx_l4_cfg__l3_main_1,
&omap44xx_mpu__l3_main_1,
@@ -507,13 +517,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
* ctrl_module_wkup
* debugss
* dmic
- * dss
- * dss_dispc
- * dss_dsi1
- * dss_dsi2
- * dss_hdmi
- * dss_rfbi
- * dss_venc
* efuse_ctrl_cust
* efuse_ctrl_std
* elm
@@ -731,6 +734,590 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
};
/*
+ * 'dss' class
+ * display sub-system
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
+ .rev_offs = 0x0000,
+ .syss_offs = 0x0014,
+ .sysc_flags = SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
+ .name = "dss",
+ .sysc = &omap44xx_dss_sysc,
+};
+
+/* dss */
+/* dss master ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
+ &omap44xx_dss__l3_main_1,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
+ {
+ .pa_start = 0x58000000,
+ .pa_end = 0x5800007f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l3_main_2 -> dss */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
+ {
+ .pa_start = 0x48040000,
+ .pa_end = 0x4804007f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> dss */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
+ .user = OCP_USER_MPU,
+};
+
+/* dss slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
+ &omap44xx_l3_main_2__dss,
+ &omap44xx_l4_per__dss,
+};
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+ { .role = "sys_clk", .clk = "dss_sys_clk" },
+ { .role = "tv_clk", .clk = "dss_tv_clk" },
+ { .role = "dss_clk", .clk = "dss_dss_clk" },
+ { .role = "video_clk", .clk = "dss_48mhz_clk" },
+};
+
+static struct omap_hwmod omap44xx_dss_hwmod = {
+ .name = "dss_core",
+ .class = &omap44xx_dss_hwmod_class,
+ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ },
+ },
+ .opt_clks = dss_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+ .slaves = omap44xx_dss_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
+ .masters = omap44xx_dss_masters,
+ .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
+ .name = "dispc",
+ .sysc = &omap44xx_dispc_sysc,
+};
+
+/* dss_dispc */
+static struct omap_hwmod omap44xx_dss_dispc_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
+ { .irq = 25 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
+ { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
+ {
+ .pa_start = 0x58001000,
+ .pa_end = 0x58001fff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l3_main_2 -> dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_dispc_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_dispc_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
+ {
+ .pa_start = 0x48041000,
+ .pa_end = 0x48041fff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_dispc_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_dispc_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
+ .user = OCP_USER_MPU,
+};
+
+/* dss_dispc slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
+ &omap44xx_l3_main_2__dss_dispc,
+ &omap44xx_l4_per__dss_dispc,
+};
+
+static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &omap44xx_dispc_hwmod_class,
+ .mpu_irqs = omap44xx_dss_dispc_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
+ .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
+ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_dss_dispc_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'dsi' class
+ * display serial interface controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
+ .name = "dsi",
+ .sysc = &omap44xx_dsi_sysc,
+};
+
+/* dss_dsi1 */
+static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
+ { .irq = 53 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
+ { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
+ {
+ .pa_start = 0x58004000,
+ .pa_end = 0x580041ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l3_main_2 -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_dsi1_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_dsi1_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
+ {
+ .pa_start = 0x48044000,
+ .pa_end = 0x480441ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_dsi1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_dsi1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
+ .user = OCP_USER_MPU,
+};
+
+/* dss_dsi1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
+ &omap44xx_l3_main_2__dss_dsi1,
+ &omap44xx_l4_per__dss_dsi1,
+};
+
+static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
+ .name = "dss_dsi1",
+ .class = &omap44xx_dsi_hwmod_class,
+ .mpu_irqs = omap44xx_dss_dsi1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
+ .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
+ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_dss_dsi1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* dss_dsi2 */
+static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
+ { .irq = 84 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
+ { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
+ {
+ .pa_start = 0x58005000,
+ .pa_end = 0x580051ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l3_main_2 -> dss_dsi2 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_dsi2_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_dsi2_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
+ {
+ .pa_start = 0x48045000,
+ .pa_end = 0x480451ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> dss_dsi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_dsi2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_dsi2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
+ .user = OCP_USER_MPU,
+};
+
+/* dss_dsi2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
+ &omap44xx_l3_main_2__dss_dsi2,
+ &omap44xx_l4_per__dss_dsi2,
+};
+
+static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
+ .name = "dss_dsi2",
+ .class = &omap44xx_dsi_hwmod_class,
+ .mpu_irqs = omap44xx_dss_dsi2_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
+ .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
+ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_dss_dsi2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'hdmi' class
+ * hdmi controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
+ .name = "hdmi",
+ .sysc = &omap44xx_hdmi_sysc,
+};
+
+/* dss_hdmi */
+static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
+ { .irq = 101 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
+ { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
+ {
+ .pa_start = 0x58006000,
+ .pa_end = 0x58006fff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l3_main_2 -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_hdmi_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_hdmi_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
+ {
+ .pa_start = 0x48046000,
+ .pa_end = 0x48046fff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_hdmi_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_hdmi_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
+ .user = OCP_USER_MPU,
+};
+
+/* dss_hdmi slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
+ &omap44xx_l3_main_2__dss_hdmi,
+ &omap44xx_l4_per__dss_hdmi,
+};
+
+static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
+ .name = "dss_hdmi",
+ .class = &omap44xx_hdmi_hwmod_class,
+ .mpu_irqs = omap44xx_dss_hdmi_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
+ .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
+ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_dss_hdmi_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
+ .name = "rfbi",
+ .sysc = &omap44xx_rfbi_sysc,
+};
+
+/* dss_rfbi */
+static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
+static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
+ { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
+ {
+ .pa_start = 0x58002000,
+ .pa_end = 0x580020ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l3_main_2 -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_rfbi_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_rfbi_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
+ {
+ .pa_start = 0x48042000,
+ .pa_end = 0x480420ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_rfbi_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_rfbi_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
+ .user = OCP_USER_MPU,
+};
+
+/* dss_rfbi slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
+ &omap44xx_l3_main_2__dss_rfbi,
+ &omap44xx_l4_per__dss_rfbi,
+};
+
+static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
+ .name = "dss_rfbi",
+ .class = &omap44xx_rfbi_hwmod_class,
+ .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
+ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_dss_rfbi_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'venc' class
+ * video encoder
+ */
+
+static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
+ .name = "venc",
+};
+
+/* dss_venc */
+static struct omap_hwmod omap44xx_dss_venc_hwmod;
+static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
+ {
+ .pa_start = 0x58003000,
+ .pa_end = 0x580030ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l3_main_2 -> dss_venc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_dss_venc_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_dss_venc_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
+ {
+ .pa_start = 0x48043000,
+ .pa_end = 0x480430ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> dss_venc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_dss_venc_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_dss_venc_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
+ .user = OCP_USER_MPU,
+};
+
+/* dss_venc slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
+ &omap44xx_l3_main_2__dss_venc,
+ &omap44xx_l4_per__dss_venc,
+};
+
+static struct omap_hwmod omap44xx_dss_venc_hwmod = {
+ .name = "dss_venc",
+ .class = &omap44xx_venc_hwmod_class,
+ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_dss_venc_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
* 'gpio' class
* general purpose io module
*/
@@ -2924,6 +3511,15 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
&omap44xx_dsp_hwmod,
&omap44xx_dsp_c0_hwmod,
+ /* dss class */
+ &omap44xx_dss_hwmod,
+ &omap44xx_dss_dispc_hwmod,
+ &omap44xx_dss_dsi1_hwmod,
+ &omap44xx_dss_dsi2_hwmod,
+ &omap44xx_dss_hdmi_hwmod,
+ &omap44xx_dss_rfbi_hwmod,
+ &omap44xx_dss_venc_hwmod,
+
/* gpio class */
&omap44xx_gpio1_hwmod,
&omap44xx_gpio2_hwmod,
--
1.7.0.4
^ permalink raw reply related
* [PATCH 3/8] OMAP4: hwmod data: Add timer
From: Benoit Cousson @ 2011-02-17 10:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297938289-8678-1-git-send-email-b-cousson@ti.com>
Add the data for the 11 timers IPs.
OMAP4 contains two differents IP variants for the timers:
- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
- 3 x 1ms timer (1, 2 & 10)
The regular timers registers programming model was changed due to the
adaptation to the new IP interface. Unfortunately the 1ms version
still use the previous programming model. The driver will have
to take care of theses differences.
Please note that the capability and the partitioning is also
different depending of the instance.
- timer 1 is inside the wakeup domain
- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
The timer was previously named gptimerX or dmtimerX, it is
now simply named timerX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
[b-cousson at ti.com: Fix alignement in class attribute,
re-order flags and update the changelog]
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 633 +++++++++++++++++++++++++++-
1 files changed, 622 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 8199eb2..37b3024 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -551,17 +551,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
* sl2if
* slimbus1
* slimbus2
- * timer1
- * timer10
- * timer11
- * timer2
- * timer3
- * timer4
- * timer5
- * timer6
- * timer7
- * timer8
- * timer9
* usb_host_fs
* usb_host_hs
* usb_otg_hs
@@ -1934,6 +1923,615 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
};
/*
+ * 'timer' class
+ * general purpose timer module with accurate 1ms tick
+ * This class contains several variants: ['timer_1ms', 'timer']
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap44xx_timer_1ms_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap44xx_timer_sysc,
+};
+
+/* timer1 */
+static struct omap_hwmod omap44xx_timer1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
+ { .irq = 37 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
+ {
+ .pa_start = 0x4a318000,
+ .pa_end = 0x4a31807f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
+ .master = &omap44xx_l4_wkup_hwmod,
+ .slave = &omap44xx_timer1_hwmod,
+ .clk = "l4_wkup_clk_mux_ck",
+ .addr = omap44xx_timer1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
+ &omap44xx_l4_wkup__timer1,
+};
+
+static struct omap_hwmod omap44xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
+ .main_clk = "timer1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer2 */
+static struct omap_hwmod omap44xx_timer2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
+ { .irq = 38 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
+ {
+ .pa_start = 0x48032000,
+ .pa_end = 0x4803207f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
+ &omap44xx_l4_per__timer2,
+};
+
+static struct omap_hwmod omap44xx_timer2_hwmod = {
+ .name = "timer2",
+ .class = &omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer2_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
+ .main_clk = "timer2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer3 */
+static struct omap_hwmod omap44xx_timer3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
+ { .irq = 39 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
+ {
+ .pa_start = 0x48034000,
+ .pa_end = 0x4803407f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer3_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
+ &omap44xx_l4_per__timer3,
+};
+
+static struct omap_hwmod omap44xx_timer3_hwmod = {
+ .name = "timer3",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer3_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
+ .main_clk = "timer3_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer4 */
+static struct omap_hwmod omap44xx_timer4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
+ { .irq = 40 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
+ {
+ .pa_start = 0x48036000,
+ .pa_end = 0x4803607f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer4_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
+ &omap44xx_l4_per__timer4,
+};
+
+static struct omap_hwmod omap44xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer4_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
+ .main_clk = "timer4_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer5 */
+static struct omap_hwmod omap44xx_timer5_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
+ { .irq = 41 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
+ {
+ .pa_start = 0x40138000,
+ .pa_end = 0x4013807f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer5_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer5_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
+ {
+ .pa_start = 0x49038000,
+ .pa_end = 0x4903807f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer5 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer5_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer5_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+/* timer5 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
+ &omap44xx_l4_abe__timer5,
+ &omap44xx_l4_abe__timer5_dma,
+};
+
+static struct omap_hwmod omap44xx_timer5_hwmod = {
+ .name = "timer5",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer5_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
+ .main_clk = "timer5_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer5_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer6 */
+static struct omap_hwmod omap44xx_timer6_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
+ { .irq = 42 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
+ {
+ .pa_start = 0x4013a000,
+ .pa_end = 0x4013a07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer6_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer6_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
+ {
+ .pa_start = 0x4903a000,
+ .pa_end = 0x4903a07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer6 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer6_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer6_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+/* timer6 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
+ &omap44xx_l4_abe__timer6,
+ &omap44xx_l4_abe__timer6_dma,
+};
+
+static struct omap_hwmod omap44xx_timer6_hwmod = {
+ .name = "timer6",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer6_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
+ .main_clk = "timer6_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer6_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer7 */
+static struct omap_hwmod omap44xx_timer7_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
+ { .irq = 43 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
+ {
+ .pa_start = 0x4013c000,
+ .pa_end = 0x4013c07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer7 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer7_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer7_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
+ {
+ .pa_start = 0x4903c000,
+ .pa_end = 0x4903c07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer7 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer7_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer7_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+/* timer7 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
+ &omap44xx_l4_abe__timer7,
+ &omap44xx_l4_abe__timer7_dma,
+};
+
+static struct omap_hwmod omap44xx_timer7_hwmod = {
+ .name = "timer7",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer7_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
+ .main_clk = "timer7_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer7_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer8 */
+static struct omap_hwmod omap44xx_timer8_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
+ { .irq = 44 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
+ {
+ .pa_start = 0x4013e000,
+ .pa_end = 0x4013e07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer8 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer8_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer8_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
+ {
+ .pa_start = 0x4903e000,
+ .pa_end = 0x4903e07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_abe -> timer8 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
+ .master = &omap44xx_l4_abe_hwmod,
+ .slave = &omap44xx_timer8_hwmod,
+ .clk = "ocp_abe_iclk",
+ .addr = omap44xx_timer8_dma_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
+/* timer8 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
+ &omap44xx_l4_abe__timer8,
+ &omap44xx_l4_abe__timer8_dma,
+};
+
+static struct omap_hwmod omap44xx_timer8_hwmod = {
+ .name = "timer8",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer8_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
+ .main_clk = "timer8_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer8_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer9 */
+static struct omap_hwmod omap44xx_timer9_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
+ { .irq = 45 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
+ {
+ .pa_start = 0x4803e000,
+ .pa_end = 0x4803e07f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer9_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer9_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
+ &omap44xx_l4_per__timer9,
+};
+
+static struct omap_hwmod omap44xx_timer9_hwmod = {
+ .name = "timer9",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer9_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
+ .main_clk = "timer9_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer9_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer10 */
+static struct omap_hwmod omap44xx_timer10_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
+ { .irq = 46 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
+ {
+ .pa_start = 0x48086000,
+ .pa_end = 0x4808607f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer10 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer10_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer10_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
+ &omap44xx_l4_per__timer10,
+};
+
+static struct omap_hwmod omap44xx_timer10_hwmod = {
+ .name = "timer10",
+ .class = &omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer10_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
+ .main_clk = "timer10_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer10_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer11 */
+static struct omap_hwmod omap44xx_timer11_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
+ { .irq = 47 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
+ {
+ .pa_start = 0x48088000,
+ .pa_end = 0x4808807f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> timer11 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_timer11_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_timer11_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
+ &omap44xx_l4_per__timer11,
+};
+
+static struct omap_hwmod omap44xx_timer11_hwmod = {
+ .name = "timer11",
+ .class = &omap44xx_timer_hwmod_class,
+ .mpu_irqs = omap44xx_timer11_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
+ .main_clk = "timer11_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer11_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
* 'uart' class
* universal asynchronous receiver/transmitter (uart)
*/
@@ -2362,6 +2960,19 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* spinlock class */
&omap44xx_spinlock_hwmod,
+ /* timer class */
+ &omap44xx_timer1_hwmod,
+ &omap44xx_timer2_hwmod,
+ &omap44xx_timer3_hwmod,
+ &omap44xx_timer4_hwmod,
+ &omap44xx_timer5_hwmod,
+ &omap44xx_timer6_hwmod,
+ &omap44xx_timer7_hwmod,
+ &omap44xx_timer8_hwmod,
+ &omap44xx_timer9_hwmod,
+ &omap44xx_timer10_hwmod,
+ &omap44xx_timer11_hwmod,
+
/* uart class */
&omap44xx_uart1_hwmod,
&omap44xx_uart2_hwmod,
--
1.7.0.4
^ permalink raw reply related
* [PATCH 2/8] OMAP4: hwmod data: Add McSPI
From: Benoit Cousson @ 2011-02-17 10:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297938289-8678-1-git-send-email-b-cousson@ti.com>
Update omap4 hwmod file with McSPI info.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Charulatha V <charu@ti.com>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Reviewed-by: Kevin Hilman <khilman@ti.com>
---
[b-cousson at ti.com: Remove dev_attr to prevent dependency
with device code. It will have to be re-added along with
the original series]
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 249 +++++++++++++++++++++++++++-
1 files changed, 245 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 46da576..8199eb2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -534,10 +534,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
* mcbsp3
* mcbsp4
* mcpdm
- * mcspi1
- * mcspi2
- * mcspi3
- * mcspi4
* mmc1
* mmc2
* mmc3
@@ -1434,6 +1430,245 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
};
/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
+ .name = "mcspi",
+ .sysc = &omap44xx_mcspi_sysc,
+};
+
+/* mcspi1 */
+static struct omap_hwmod omap44xx_mcspi1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
+ { .irq = 65 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+ {
+ .pa_start = 0x48098000,
+ .pa_end = 0x480981ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mcspi1_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcspi1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
+ &omap44xx_l4_per__mcspi1,
+};
+
+static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+ .name = "mcspi1",
+ .class = &omap44xx_mcspi_hwmod_class,
+ .mpu_irqs = omap44xx_mcspi1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
+ .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
+ .main_clk = "mcspi1_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_mcspi1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi2 */
+static struct omap_hwmod omap44xx_mcspi2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
+ { .irq = 66 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+ {
+ .pa_start = 0x4809a000,
+ .pa_end = 0x4809a1ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mcspi2_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcspi2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
+ &omap44xx_l4_per__mcspi2,
+};
+
+static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+ .name = "mcspi2",
+ .class = &omap44xx_mcspi_hwmod_class,
+ .mpu_irqs = omap44xx_mcspi2_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
+ .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
+ .main_clk = "mcspi2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_mcspi2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi3 */
+static struct omap_hwmod omap44xx_mcspi3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
+ { .irq = 91 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
+ { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+ {
+ .pa_start = 0x480b8000,
+ .pa_end = 0x480b81ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mcspi3_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcspi3_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
+ &omap44xx_l4_per__mcspi3,
+};
+
+static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+ .name = "mcspi3",
+ .class = &omap44xx_mcspi_hwmod_class,
+ .mpu_irqs = omap44xx_mcspi3_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
+ .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
+ .main_clk = "mcspi3_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_mcspi3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi4 */
+static struct omap_hwmod omap44xx_mcspi4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
+ { .irq = 48 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
+ { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+ {
+ .pa_start = 0x480ba000,
+ .pa_end = 0x480ba1ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
+ .master = &omap44xx_l4_per_hwmod,
+ .slave = &omap44xx_mcspi4_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mcspi4_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
+ &omap44xx_l4_per__mcspi4,
+};
+
+static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+ .name = "mcspi4",
+ .class = &omap44xx_mcspi_hwmod_class,
+ .mpu_irqs = omap44xx_mcspi4_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
+ .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
+ .main_clk = "mcspi4_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_mcspi4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
* 'mpu' class
* mpu sub-system
*/
@@ -2110,6 +2345,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
&omap44xx_iva_seq0_hwmod,
&omap44xx_iva_seq1_hwmod,
+ /* mcspi class */
+ &omap44xx_mcspi1_hwmod,
+ &omap44xx_mcspi2_hwmod,
+ &omap44xx_mcspi3_hwmod,
+ &omap44xx_mcspi4_hwmod,
+
/* mpu class */
&omap44xx_mpu_hwmod,
--
1.7.0.4
^ permalink raw reply related
* [PATCH 1/8] OMAP4: hwmod data: Add hwspinlock
From: Benoit Cousson @ 2011-02-17 10:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297938289-8678-1-git-send-email-b-cousson@ti.com>
Add hwspinlock hwmod data for OMAP4 chip
Signed-off-by: Cousson, Benoit <b-cousson@ti.com>
Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Paul Walmsley <paul@pwsan.com>
[b-cousson at ti.com: Move the data to keep the original
order and add missing SIDLE_SMART_WKUP flag]
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 65 +++++++++++++++++++++++++++-
1 files changed, 64 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c2806bd..46da576 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -555,7 +555,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
* sl2if
* slimbus1
* slimbus2
- * spinlock
* timer1
* timer10
* timer11
@@ -1639,6 +1638,67 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
};
/*
+ * 'spinlock' class
+ * spinlock provides hardware assistance for synchronizing the processes
+ * running on multiple processors
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
+ .name = "spinlock",
+ .sysc = &omap44xx_spinlock_sysc,
+};
+
+/* spinlock */
+static struct omap_hwmod omap44xx_spinlock_hwmod;
+static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
+ {
+ .pa_start = 0x4a0f6000,
+ .pa_end = 0x4a0f6fff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_cfg -> spinlock */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_spinlock_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_spinlock_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* spinlock slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
+ &omap44xx_l4_cfg__spinlock,
+};
+
+static struct omap_hwmod omap44xx_spinlock_hwmod = {
+ .name = "spinlock",
+ .class = &omap44xx_spinlock_hwmod_class,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_spinlock_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
* 'uart' class
* universal asynchronous receiver/transmitter (uart)
*/
@@ -2058,6 +2118,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
&omap44xx_smartreflex_iva_hwmod,
&omap44xx_smartreflex_mpu_hwmod,
+ /* spinlock class */
+ &omap44xx_spinlock_hwmod,
+
/* uart class */
&omap44xx_uart1_hwmod,
&omap44xx_uart2_hwmod,
--
1.7.0.4
^ permalink raw reply related
* [PATCH 0/8] OMAP4: hwmod data: Add a bunch of IPs
From: Benoit Cousson @ 2011-02-17 10:24 UTC (permalink / raw)
To: linux-arm-kernel
All,
Due to the important number of modifications recently done on the
OMAP4 data compared to the original and the total absence of explanation
in the changelog, I re-submit the data before the driver series in order
to maintain the integrity of the original file and to avoid a huge pain
during the merge.
Govind, Tarun and Kishon,
Please note that I cannot include here the dev_attr or rev field for
McSPI, McBSP and timer since it requires some modification in the device
header.
You will have to update your series accordingly.
A couple of extra hwmod are added as well to avoid the future drivers
series to include them.
The various USB OMAP4 hwmods data will be send soon.
Regards,
Benoit
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Cc: Govindraj.R <govindraj.raja@ti.com>
Cc: Charulatha V <charu@ti.com>
Cc: David Lambert <dlambert@ti.com>
Cc: Omar Ramirez Luna <omar.ramirez@ti.com>
Cc: Sumit Semwal <sumit.semwal@ti.com>
Cc: Ohad Ben-Cohen <ohad@wizery.com>
The following changes since commit 85e2efbb1db9a18d218006706d6e4fbeb0216213:
Linus Torvalds (1):
Linux 2.6.38-rc5
are available in the git repository at:
git://gitorious.org/omap-pm/linux.git for_2.6.39/omap4_hwmod_data
Benoit Cousson (8):
OMAP4: hwmod data: Add hwspinlock
OMAP4: hwmod data: Add McSPI
OMAP4: hwmod data: Add timer
OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
OMAP4: hwmod data: Add mailbox
OMAP4: hwmod data: Add DMIC
OMAP4: hwmod data: Add McBSP
OMAP4: hwmod data: Add AESS, McPDM, bandgap, counter_32k, MMC, KBD, ISS & IPU
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 3023 +++++++++++++++++++++++++++-
1 files changed, 2977 insertions(+), 46 deletions(-)
^ permalink raw reply
* [PATCH v2] OMAP: PM: DMA: Enable runtime pm
From: G, Manjunath Kondaiah @ 2011-02-17 10:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87zkpvn4mi.fsf@ti.com>
On Wed, Feb 16, 2011 at 11:47:33AM -0800, Kevin Hilman wrote:
> "G, Manjunath Kondaiah" <manjugk@ti.com> writes:
>
> > Hi Kevin,
> >
> > On Mon, Feb 14, 2011 at 02:06:53PM -0800, Kevin Hilman wrote:
> >> "G, Manjunath Kondaiah" <manjugk@ti.com> writes:
> >>
> >> > From: Manjunath G Kondaiah <manjugk@ti.com>
> >> >
> >> > Enable runtime pm and use pm_runtime_get_sync and pm_runtime_put_autosuspend
> >> > for OMAP DMA driver.
> >> >
> >> > The DMA driver uses auto suspend feature of runtime pm framework through
> >> > which the clock gets disabled automatically if there is no activity for
> >> > more than one second.
> >> >
> >> > Testing:
> >> > Compile: omap1_defconfig and omap2plus_defconfig
> >> > Boot: OMAP1710(H3), OMAP2420(H4), OMAP3630(Zoom3), OMAP4(Blaze)
> >>
> >> The normal DMA tests should also be run on these platforms. Based on
> >> the above, I can't tell any DMA tests were run. Based on my tests,
> >> this isn't working for chained xfers.
> >>
> >> Using the runtime PM sysfs interface, you can check the runtime status
> >> of the device:
> >>
> >> # cat /sys/devices/platform/omap/omap_dma_system.0/power/runtime_status
> >>
> >> It should show 'active' during transfer, and after timeout expires it
> >> will show 'suspended'.
> >>
> >> Doing some tests using my dmatest module:
> >>
> >> git://gitorious.org/omap-test/dmatest.git
> >>
> >> I noticed that it gets stuck in 'active' and never gets suspended when I
> >> used DMA channel linking (load module using 'linking=1' as load-time option)
> >>
> >> I'm not sure exactly why, but I will guess that the reason is that there
> >> is an imbalance in get/put calls when using chaining, since 'get' is
> >> only called once upon omap_start_dma() but 'put' is called for every
> >> channel in the callback.
> >
> > Even I noticed this after running chaining test case and checking
> > runtime status. But, I am wondering even with 'active' runtime status,
> > the core hits off and retention.
>
> Probably because system DMA is auto-idle and clocked by the core_l3_iclk
>
> > The complete log which has all the sequences of running chaining tests,
> > enabling off mode and checking runtime status is available at:
> > http://pastebin.com/YEHMEXUP
> >
> > Though I agree on the point that, it is mismatch with get/put calls with
> > DMA chaining, I still need to analyze this in detail.
>
> Yes. The mismatch highlights an underlying problem.
>
> > The other thing which is not considered here is, the get_sync is called
> > inside start_dma only(request_dma will call get_sync and put after the
> > getting requested channel). After request_dma and start_dma, there are
> > API's called by user(dma_set_params, priority etc) which also require
> > get_sync since those API's will access configuration registers. I am
> > wondering if have get_sync and put in all the API's, this might result
> > in over loading.
>
> I'm not sure what you mean by over loading.
>
> You need to have all register accesses inside get/put calls. As long as
> they are balanced, this should not leed to problems.
I mean, almost all the api's will have get_sync and put_autosuspend
calls. If it is acceptable, let me check the same with implementation.
I feel this is equivalent to placing get_sync and put_autosuspend with
low level read/write api's.
-Manjunath
^ permalink raw reply
* [PATCH] ARM: gic: use handle_fasteoi_irq for SPIs
From: Russell King - ARM Linux @ 2011-02-17 10:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1102171032580.2701@localhost6.localdomain6>
On Thu, Feb 17, 2011 at 10:38:08AM +0100, Thomas Gleixner wrote:
> On Thu, 17 Feb 2011, Russell King - ARM Linux wrote:
> > That's a result of genirq. With the ARM non-genirq implementation
> > where we had just ack, mask and unmask, it all turned out much easier.
> > In fact, we hardly ever called any of these functions in chained
> > handlers (except ack) - the only time when mask and unmask were called
> > was when we had an IRQ multiplexer which didn't allow us to mask the
> > individual interrupts.
> >
> > With the advent of genirq and its expansion of the irq chip methods it's
> > become much more complicated. That's one of the faults of trying to
> > generalize this across different architectures.
> >
> > You can't do without chained handlers on ARM - we used to do it without
> > them and it was proven to be a complete disaster. Dropped interrupts
> > and various drivers just didn't work with chained interrupt controllers.
>
> I really have a hard time to see the difference between doing:
>
> chained_handler()
> fiddle_with_primary_chip()
> demux()
> fiddle_with_primary_chip()
>
> and
>
> handle_xxxx_irq()
> fiddle_with_primary_chip()
>
> chained_handler()
> demux()
>
> fiddle_with_primary_chip()
>
> Why should that drop more interrupt? The only difference is that you
> make the demux handler oblivious of the underlying primary chip and
> let the chip chose the appropriate flow handler which issues the right
> chip methods.
The difference is that properly implemented chained handlers do *not*
mask the interrupt on the parent IRQ controller, thereby allowing
other interrupts to be serviced as appropriate.
The issue that this whole implementation was designed in the first place
to fix was lost IDE interrupts for CF cards connected to the PCMCIA/CF
interfaces of SA1111 devices. These were lost because the CF interrupt
output is a level-based output, but the SA11xx interrupt inputs are all
edge based.
When the CF interrupt is connected to a SA1111 GPIO, and using the old
interrupt system, edge transitions were _often_ missed resulting in
frequent 'lost interrupt' complaints from the IDE layer. Exactly why
this was could never be ascertained (probably because the hardware
combination I had at the time did not allow me to setup this scenario.)
With the chained interrupt handler implementation, things were setup to
ensure that as much of the interrupt levels were left enabled so that
there was symetrical handling across the entire interrupt tree, and the
result of that was no more lost interrupts.
There is a lot of difference between using a conventional 'flow' handler
which does masking/unmasking of the parent interrupt and a properly
written chained handler which avoids that masking.
^ permalink raw reply
* [PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros
From: Jamie Iles @ 2011-02-17 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e58673f5-2881-4820-b5cd-99e8ef294ed5@VA3EHSMHS024.ehs.local>
Hi John,
A few more nitpicks, but looking good now!
Jamie
On Wed, Feb 16, 2011 at 09:11:55AM -0700, John Linn wrote:
> These are the minimum needed to build the kernel for the new platform.
>
> Signed-off-by: John Linn <john.linn@xilinx.com>
> ---
>
> V3 Changes
>
> Updates based on Russell Kings' comments
> Changed headers to update the license info and remove
> the address
>
> Updated the constant to use UL in vmalloc.h
>
> V2 Changes
>
> Updates based on Russell King's comments
> moved to using entry-macro-gic.S
> moved stuff from hardware.h to xilinx_soc.h
> added IOMEM() in io.h to help with typing
> Minor updates to IO_SPACE_LIMIT and __io()
> Updated addresses to be clear with seperate virtual
> and physical addresses
>
> arch/arm/mach-xilinx/include/mach/clkdev.h | 33 ++++++++++++++++
> arch/arm/mach-xilinx/include/mach/debug-macro.S | 36 +++++++++++++++++
> arch/arm/mach-xilinx/include/mach/entry-macro.S | 30 ++++++++++++++
> arch/arm/mach-xilinx/include/mach/hardware.h | 18 +++++++++
> arch/arm/mach-xilinx/include/mach/io.h | 33 ++++++++++++++++
> arch/arm/mach-xilinx/include/mach/irqs.h | 29 ++++++++++++++
> arch/arm/mach-xilinx/include/mach/memory.h | 23 +++++++++++
> arch/arm/mach-xilinx/include/mach/system.h | 28 +++++++++++++
> arch/arm/mach-xilinx/include/mach/timex.h | 24 ++++++++++++
> arch/arm/mach-xilinx/include/mach/uart.h | 31 +++++++++++++++
> arch/arm/mach-xilinx/include/mach/uncompress.h | 47 +++++++++++++++++++++++
> arch/arm/mach-xilinx/include/mach/vmalloc.h | 20 ++++++++++
> arch/arm/mach-xilinx/include/mach/xilinx_soc.h | 46 ++++++++++++++++++++++
> 13 files changed, 398 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h
> create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S
> create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S
> create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h
> create mode 100644 arch/arm/mach-xilinx/include/mach/io.h
> create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h
> create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h
> create mode 100644 arch/arm/mach-xilinx/include/mach/system.h
> create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h
> create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h
> create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h
> create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h
> create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h
>
> diff --git a/arch/arm/mach-xilinx/include/mach/clkdev.h b/arch/arm/mach-xilinx/include/mach/clkdev.h
> new file mode 100644
> index 0000000..5dd1453
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/clkdev.h
> @@ -0,0 +1,33 @@
> +/*
> + * arch/arm/mach-xilinx/include/mach/clkdev.h
> + *
> + * Copyright (C) 2011 Xilinx, Inc.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __MACH_CLKDEV_H__
> +#define __MACH_CLKDEV_H__
> +
> +struct clk {
> + unsigned long rate;
> +};
> +
> +static inline int __clk_get(struct clk *clk)
> +{
> + return 1;
> +}
> +
> +static inline void __clk_put(struct clk *clk)
> +{
> +}
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/debug-macro.S b/arch/arm/mach-xilinx/include/mach/debug-macro.S
> new file mode 100644
> index 0000000..30d3d3d
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/debug-macro.S
> @@ -0,0 +1,36 @@
> +/* arch/arm/mach-xilinx/include/mach/debug-macro.S
> + *
> + * Debugging macro include header
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <mach/xilinx_soc.h>
> +#include <mach/uart.h>
> +
> + .macro addruart, rp, rv
> + ldr \rp, =LL_UART_PADDR @ physical
> + ldr \rv, =LL_UART_VADDR @ virtual
> + .endm
> +
> + .macro senduart,rd,rx
> + str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
> + .endm
> +
> + .macro waituart,rd,rx
> + .endm
> +
> + .macro busyuart,rd,rx
> +1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
> + tst \rd, #UART_SR_TXFULL @
> + bne 1002b @ wait if FIFO is full
> + .endm
> diff --git a/arch/arm/mach-xilinx/include/mach/entry-macro.S b/arch/arm/mach-xilinx/include/mach/entry-macro.S
> new file mode 100644
> index 0000000..11a2866
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/entry-macro.S
> @@ -0,0 +1,30 @@
> +/*
> + * arch/arm/mach-xilinx/include/mach/entry-macro.S
> + *
> + * Low-level IRQ helper macros
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * based on arch/plat-mxc/include/mach/entry-macro.S
> + *
> + * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
> + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <mach/hardware.h>
> +#include <asm/hardware/entry-macro-gic.S>
> +
> + .macro disable_fiq
> + .endm
> +
> + .macro arch_ret_to_user, tmp1, tmp2
> + .endm
> diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h b/arch/arm/mach-xilinx/include/mach/hardware.h
> new file mode 100644
> index 0000000..f9685c4
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/hardware.h
> @@ -0,0 +1,18 @@
> +/* arch/arm/mach-xilinx/include/mach/hardware.h
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_HARDWARE_H__
> +#define __MACH_HARDWARE_H__
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/io.h b/arch/arm/mach-xilinx/include/mach/io.h
> new file mode 100644
> index 0000000..ef69e65
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/io.h
> @@ -0,0 +1,33 @@
> +/* arch/arm/mach-xilinx/include/mach/io.h
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_IO_H__
> +#define __MACH_IO_H__
> +
> +/* Allow IO space to be anywhere in the memory */
> +
> +#define IO_SPACE_LIMIT 0xffff
> +
> +/* IO address mapping macros, nothing special at this time but required */
> +
> +#ifdef __ASSEMBLER__
> +#define IOMEM(x) (x)
> +#else
> +#define IOMEM(x) ((void __force __iomem *)(x))
> +#endif
> +
> +#define __io(a) __typesafe_io(a)
> +#define __mem_pci(a) (a)
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/irqs.h b/arch/arm/mach-xilinx/include/mach/irqs.h
> new file mode 100644
> index 0000000..47a8162
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/irqs.h
> @@ -0,0 +1,29 @@
> +/* arch/arm/mach-xilinx/include/mach/irqs.h
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_IRQS_H
> +#define __MACH_IRQS_H
> +
> +#define ARCH_NR_GPIOS 118
> +#define NR_IRQS (128 + ARCH_NR_GPIOS)
> +
> +/*
> + * GIC Interrupts
> + */
> +
> +#define IRQ_GIC_SPI_START 32
> +#define IRQ_TIMERCOUNTER0 42
> +#define IRQ_UART0 59
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/memory.h b/arch/arm/mach-xilinx/include/mach/memory.h
> new file mode 100644
> index 0000000..c200486
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/memory.h
> @@ -0,0 +1,23 @@
> +/* arch/arm/mach-xilinx/include/mach/memory.h
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_MEMORY_H__
> +#define __MACH_MEMORY_H__
> +
> +#include <mach/hardware.h>
> +
> +#define PHYS_OFFSET 0x0
This should be PLAT_PHYS_OFFSET and could do with being surrounded with
UL() e.g.
#define PLAT_PHYS_OFFSET UL(0x00000000)
> +#define MEM_SIZE SZ_256M
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/system.h b/arch/arm/mach-xilinx/include/mach/system.h
> new file mode 100644
> index 0000000..e8514a0
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/system.h
> @@ -0,0 +1,28 @@
> +/* arch/arm/mach-xilinx/include/mach/system.h
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_SYSTEM_H__
> +#define __MACH_SYSTEM_H__
> +
> +static inline void arch_idle(void)
> +{
> + cpu_do_idle();
> +}
> +
> +static inline void arch_reset(char mode, const char *cmd)
> +{
> + /* Add architecture specific reset processing here */
I think you can add cpu_reset(0) in here to try a soft reset by jumping
to the reset vector. This should give you some reset functionality.
> +}
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/timex.h b/arch/arm/mach-xilinx/include/mach/timex.h
> new file mode 100644
> index 0000000..6765e15
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/timex.h
> @@ -0,0 +1,24 @@
> +/* arch/arm/mach-xilinx/include/mach/timex.h
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_TIMEX_H__
> +#define __MACH_TIMEX_H__
> +
> +#include <mach/hardware.h>
I don't think you need mach/hardware.h included in here.
> +
> +#define PERIPHERAL_CLOCK_RATE 2500000
> +
> +#define CLOCK_TICK_RATE (PERIPHERAL_CLOCK_RATE / 32)
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/uart.h b/arch/arm/mach-xilinx/include/mach/uart.h
> new file mode 100644
> index 0000000..20a10d7
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/uart.h
> @@ -0,0 +1,31 @@
> +/* arch/arm/mach-xilinx/include/mach/uart.h
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_UART_H__
> +#define __MACH_UART_H__
> +
> +#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
> +#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
> +#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
> +
> +#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
> +#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
> +
> +#define UART_FIFO_WRITE(base, value) \
> + (*(volatile unsigned int *)((base) + UART_FIFO_OFFSET) = (value))
> +
> +#define UART_STATUS(base) \
> + (*(volatile unsigned int *)((base) + UART_SR_OFFSET))
You could probably make these static inline functions in the header and
use __raw_{readl,writel}() to make this a little cleaner.
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h b/arch/arm/mach-xilinx/include/mach/uncompress.h
> new file mode 100644
> index 0000000..b7a5110
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/uncompress.h
> @@ -0,0 +1,47 @@
> +/* arch/arm/mach-xilinx/include/mach/uncompress.h
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_UNCOMPRESS_H__
> +#define __MACH_UNCOMPRESS_H__
> +
> +#include <mach/xilinx_soc.h>
> +#include <mach/uart.h>
> +
> +void arch_decomp_setup(void)
> +{
> +}
> +
> +static inline void flush(void)
> +{
> + /*
> + * Wait while the FIFO is not empty
> + */
> + while (!(UART_STATUS(LL_UART_PADDR) & UART_SR_TXEMPTY))
> + ;
> +}
> +
> +#define arch_decomp_wdog()
> +
> +static void putc(char ch)
> +{
> + /*
> + * Wait for room in the FIFO, then write the char into the FIFO
> + */
> + while (UART_STATUS(LL_UART_PADDR) & UART_SR_TXFULL)
> + ;
It might be worth adding a barrier() call to these loops to be explicit
about the volatility.
> +
> + UART_FIFO_WRITE(LL_UART_PADDR, ch);
> +}
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/vmalloc.h b/arch/arm/mach-xilinx/include/mach/vmalloc.h
> new file mode 100644
> index 0000000..aba20a3
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/vmalloc.h
> @@ -0,0 +1,20 @@
> +/* arch/arm/mach-xilinx/include/mach/vmalloc.h
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_VMALLOC_H__
> +#define __MACH_VMALLOC_H__
> +
> +#define VMALLOC_END 0xE0000000UL
> +
> +#endif
> diff --git a/arch/arm/mach-xilinx/include/mach/xilinx_soc.h b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> new file mode 100644
> index 0000000..d01cde1
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> @@ -0,0 +1,46 @@
> +/* arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_XILINX_SOC_H__
> +#define __MACH_XILINX_SOC_H__
> +
> +/* For now, all mappings are flat (physical = virtual)
> + */
> +#define UART0_PHYS 0xE0000000
> +#define UART0_VIRT UART0_PHYS
> +
> +#define TTC0_PHYS 0xF8001000
> +#define TTC0_VIRT TTC0_PHYS
> +
> +#define PL310_L2CC_PHYS 0xF8F02000
> +#define PL310_L2CC_VIRT PL310_L2CC_PHYS
> +
> +#define SCU_PERIPH_PHYS 0xF8F00000
> +#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS
> +
> +/* The following are intended for the devices that are mapped early */
> +
> +#define TTC0_BASE IOMEM(TTC0_VIRT)
> +#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
> +#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100)
> +#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000)
> +#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT)
> +
> +/*
> + * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
> + */
> +#define LL_UART_PADDR UART0_PHYS
> +#define LL_UART_VADDR UART0_VIRT
> +
> +#endif
> --
> 1.6.2.1
>
>
>
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>
>
> --
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^ permalink raw reply
* [PATCH V3 2/4] ARM: Xilinx: Adding timer support to the platform
From: Jamie Iles @ 2011-02-17 9:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <28346a1e-ec89-4c09-8fda-f020b58d1fa4@VA3EHSMHS024.ehs.local>
Hi John,
A couple more nitpicks.
Jamie
On Wed, Feb 16, 2011 at 09:11:54AM -0700, John Linn wrote:
> The timer driver supports the Xilinx PS Timer Counter IP.
>
> Signed-off-by: Kiran Sutariya <kiran.sutariya@einfochips.com>
> Signed-off-by: John Linn <john.linn@xilinx.com>
> ---
>
> V3 Changes
>
> Updates based on Russell Kings' comments
> Changed headers to update the license info and remove
> the address
>
> V2 Changes
>
> The timer code was changed quite a bit based on review inputs. It
> got much smaller and cleaner I think.
>
> Updates based on Russell King's comments
> minor cleanups for documentation comments
> removed the name from the timer structure
> removed interrupt for clock source
> moved to using clock functions provided in the kernel
> for calculating shift/mult values
> removed PM code as generic handles it
>
> Updated based on Jamie Iles's comment
> cleaned up ENABLE_MASK which was confusing
> now using platform_add_devices() from platform code
> moved base_addr to void __iomem pointer
> removed stop of the event timer in one shot mode
>
> arch/arm/mach-xilinx/Makefile | 2 +-
> arch/arm/mach-xilinx/timer.c | 301 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 302 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/mach-xilinx/timer.c
>
> diff --git a/arch/arm/mach-xilinx/Makefile b/arch/arm/mach-xilinx/Makefile
> index 76e9e55..660fb19 100644
> --- a/arch/arm/mach-xilinx/Makefile
> +++ b/arch/arm/mach-xilinx/Makefile
> @@ -3,5 +3,5 @@
> #
>
> # Common support
> -obj-y := common.o
> +obj-y := common.o timer.o
> obj-$(CONFIG_MACH_XILINX) += board_ep107.o
> diff --git a/arch/arm/mach-xilinx/timer.c b/arch/arm/mach-xilinx/timer.c
> new file mode 100644
> index 0000000..f08a2f1
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/timer.c
> @@ -0,0 +1,301 @@
> +/* arch/arm/mach-xilinx/timer.c
> + *
> + * This file contains driver for the Xilinx PS Timer Counter IP.
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * based on arch/mips/kernel/time.c timer driver
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/types.h>
> +#include <linux/clocksource.h>
> +#include <linux/clockchips.h>
> +#include <linux/io.h>
> +
> +#include <asm/mach/time.h>
> +#include <mach/xilinx_soc.h>
> +
> +/*
> + * This driver configures the 2 16-bit count-up timers as follows:
> + *
> + * T1: Timer 1, clocksource for generic timekeeping
> + * T2: Timer 2, clockevent source for hrtimers
> + * T3: Timer 3, <unused>
> + *
> + * The input frequency to the timer module for emulation is 2.5MHz which is
> + * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
> + * the timers are clocked at 78.125KHz (12.8 us resolution).
> + *
> + * The input frequency to the timer module in silicon will be 200MHz. With the
> + * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
> + */
> +#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */
> +#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */
> +
> +#define XTTCPSS_TIMER_BASE TTC0_BASE
> +#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1)
> +/*
> + * Timer Register Offset Definitions of Timer 1, Increment base address by 4
> + * and use same offsets for Timer 2
> + */
> +#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
> +#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
> +#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
> +#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
> +#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */
> +#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */
> +#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */
> +#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
> +#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
> +
> +#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1
> +
> +/**
> + * struct xttcpss_timer - This definition defines local timer structure
> + *
> + * @base_addr: Base address of timer
> + * @timer_irq: irqaction structure for the timer device
> + * @mode: only valid for an clock event, periodic or one-shot
> + **/
> +struct xttcpss_timer {
> + void __iomem *base_addr;
> + enum clock_event_mode mode;
I can't see .mode being used anywhere in this file so this could
probably be simplified a bit to just two base address pointers.
> +};
> +
> +static struct xttcpss_timer timers[2];
> +static struct clock_event_device xttcpss_clockevent;
> +
> +/**
> + * xttcpss_set_interval - Set the timer interval value
> + *
> + * @timer: Pointer to the timer instance
> + * @cycles: Timer interval ticks
> + **/
> +static void xttcpss_set_interval(struct xttcpss_timer *timer,
> + unsigned long cycles)
> +{
> + u32 ctrl_reg;
> +
> + /* Disable the counter, set the counter value and re-enable counter */
> + ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
> + ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> + __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
> +
> + __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
> +
> + /* Reset the counter (0x10) so that it starts from 0, one-shot
> + mode makes this needed for timing to be right. */
> + ctrl_reg |= 0x10;
> + ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> + __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
> +}
> +
> +/**
> + * xttcpss_clock_event_interrupt - Clock event timer interrupt handler
> + *
> + * @irq: IRQ number of the Timer
> + * @dev_id: void pointer to the xttcpss_timer instance
> + *
> + * returns: Always IRQ_HANDLED - success
> + **/
> +static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
> +{
> + struct clock_event_device *evt = &xttcpss_clockevent;
> + struct xttcpss_timer *timer = dev_id;
> +
> + /* Acknowledge the interrupt and call event handler */
> + __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
> + timer->base_addr + XTTCPSS_ISR_OFFSET);
> +
> + evt->event_handler(evt);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static struct irqaction event_timer_irq = {
> + .name = "xttcpss clockevent",
> + .flags = IRQF_DISABLED | IRQF_TIMER,
> + .handler = xttcpss_clock_event_interrupt,
> +};
> +
> +/**
> + * xttcpss_timer_hardware_init - Initialize the timer hardware
> + *
> + * Initialize the hardware to start the clock source, get the clock
> + * event timer ready to use, and hook up the interrupt.
> + **/
> +static void __init xttcpss_timer_hardware_init(void)
> +{
> + /* Setup the clock source counter to be an incrementing counter
> + * with no interrupt and it rolls over at 0xFFFF. Pre-scale
> + it by 32 also. Let it start running now.
> + */
> + timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
> +
> + __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
> + XTTCPSS_IER_OFFSET);
> + __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
> + XTTCPSS_CLK_CNTRL_OFFSET);
> + __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
> + XTTCPSS_CNT_CNTRL_OFFSET);
> +
> + /* Setup the clock event timer to be an interval timer which
> + * is prescaled by 32 using the interval interrupt. Leave it
> + * disabled for now.
> + */
> +
> + timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
> +
> + __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
> + XTTCPSS_CNT_CNTRL_OFFSET);
> + __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
> + XTTCPSS_CLK_CNTRL_OFFSET);
> + __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
> + XTTCPSS_IER_OFFSET);
> +
> + /* Setup IRQ the clock event timer */
> + event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
> +
> + if (event_timer_irq.handler != NULL)
> + setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
You've explicitly initialized event_timer_irq.handler above so I don't
think you need to check against NULL, and just always call setup_irq().
> +}
> +
> +/**
> + * __raw_readl_cycles - Reads the timer counter register
> + *
> + * returns: Current timer counter register value
> + **/
> +static cycle_t __raw_readl_cycles(struct clocksource *cs)
> +{
> + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
> +
> + return (cycle_t)__raw_readl(timer->base_addr +
> + XTTCPSS_COUNT_VAL_OFFSET);
> +}
> +
> +
> +/*
> + * Instantiate and initialize the clock source structure
> + */
> +static struct clocksource clocksource_xttcpss = {
> + .name = "xttcpss_timer1",
> + .rating = 200, /* Reasonable clock source */
> + .read = __raw_readl_cycles,
> + .mask = CLOCKSOURCE_MASK(16),
> + .shift = 0, /* Initialized to zero */
This is static data so you don't need to explicitly initialize shift to
0. It doesn't hurt anything though.
> + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> +};
> +
> +
> +/**
> + * xttcpss_set_next_event - Sets the time interval for next event
> + *
> + * @cycles: Timer interval ticks
> + * @evt: Address of clock event instance
> + *
> + * returns: Always 0 - success
> + **/
> +static int xttcpss_set_next_event(unsigned long cycles,
> + struct clock_event_device *evt)
> +{
> + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
> +
> + xttcpss_set_interval(timer, cycles);
> + return 0;
> +}
> +
> +/**
> + * xttcpss_set_mode - Sets the mode of timer
> + *
> + * @mode: Mode to be set
> + * @evt: Address of clock event instance
> + **/
> +static void xttcpss_set_mode(enum clock_event_mode mode,
> + struct clock_event_device *evt)
> +{
> + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
> + u32 ctrl_reg;
> +
> + timer->mode = mode;
> +
> + switch (mode) {
> + case CLOCK_EVT_MODE_PERIODIC:
> + xttcpss_set_interval(timer, CLOCK_TICK_RATE / HZ);
> + break;
> + case CLOCK_EVT_MODE_ONESHOT:
> + case CLOCK_EVT_MODE_UNUSED:
> + case CLOCK_EVT_MODE_SHUTDOWN:
> + ctrl_reg = __raw_readl(timer->base_addr +
> + XTTCPSS_CNT_CNTRL_OFFSET);
> + ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> + __raw_writel(ctrl_reg,
> + timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
> + break;
> + case CLOCK_EVT_MODE_RESUME:
> + ctrl_reg = __raw_readl(timer->base_addr +
> + XTTCPSS_CNT_CNTRL_OFFSET);
> + ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> + __raw_writel(ctrl_reg,
> + timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
> + break;
> + }
> +}
> +
> +/*
> + * Instantiate and initialize the clock event structure
> + */
> +static struct clock_event_device xttcpss_clockevent = {
> + .name = "xttcpss_timer2",
> + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> + .shift = 0, /* Initialized to zero */
Same here, that .shift = 0 isn't really needed (but doesn't hurt).
> + .set_next_event = xttcpss_set_next_event,
> + .set_mode = xttcpss_set_mode,
> + .rating = 200,
> +};
> +
> +/**
> + * xttcpss_timer_init - Initialize the timer
> + *
> + * Initializes the timer hardware and register the clock source and clock event
> + * timers with Linux kernal timer framework
> + **/
> +static void __init xttcpss_timer_init(void)
> +{
> + xttcpss_timer_hardware_init();
> + clocksource_register_hz(&clocksource_xttcpss, CLOCK_TICK_RATE);
> +
> + /* Calculate the parameters to allow the clockevent to operate using
> + integer math
> + */
> + clockevents_calc_mult_shift(&xttcpss_clockevent, CLOCK_TICK_RATE, 4);
> +
> + xttcpss_clockevent.max_delta_ns =
> + clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
> + xttcpss_clockevent.min_delta_ns =
> + clockevent_delta2ns(1, &xttcpss_clockevent);
> +
> + /* Indicate that clock event can be used on any of the CPUs */
> +
> + xttcpss_clockevent.cpumask = cpu_all_mask;
> + clockevents_register_device(&xttcpss_clockevent);
> +}
> +
> +/*
> + * Instantiate and initialize the system timer structure
> + */
> +struct sys_timer xttcpss_sys_timer = {
> + .init = xttcpss_timer_init,
> +};
> --
> 1.6.2.1
>
>
>
> This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [klibc] fwd: fix up ARM assembly to use 'bx lr' in place of 'mov pc, lr'.
From: Dave Martin @ 2011-02-17 9:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216235019.GA17674@shutemov.name>
On Wed, Feb 16, 2011 at 11:50 PM, Kirill A. Shutemov
<kirill@shutemov.name> wrote:
> On Thu, Feb 17, 2011 at 12:06:48AM +0100, maximilian attems wrote:
>> hello vorlon,
>>
>> got notified of your patch,
>> will apply next days upstream unless some critiques are voiced on ml.
>> thanks.
>>
>> --
>> maks
>>
>>
>> ----- Forwarded message from Steve Langasek <steve.langasek@canonical.com> -----
>>
>> Date: Wed, 16 Feb 2011 22:05:42 -0000
>> From: Steve Langasek <steve.langasek@canonical.com>
>> Subject: [Bug 527720] Re: thumb2 porting issues identified: klibc uses mov.*pc
>>
>>
>> I've also touched it up to be mergeable with Debian (support v4t builds
>> with #ifdef).
>>
>> Confirmed that installing the resulting klibc packages on my beagleboard
>> gives me a successfully-booting initramfs with klibc; and the
>> vfork/setjmptest test cases all pass in the klibc package tree.
>>
>> Fixes: https://bugs.launchpad.net/ubuntu/+source/klibc/+bug/527720
>>
>> --- klibc-1.5.20.orig/usr/klibc/arch/arm/vfork.S
>> +++ klibc-1.5.20/usr/klibc/arch/arm/vfork.S
>> @@ -25,7 +25,11 @@ vfork:
>> ? ? ? ? ?ldrcs ? ? ? ?r3, 1f
>> ? ? ? ? ?mvncs ? ? ? ?r0, #0
>> ? ? ? ? ?strcs ? ? ? ?r2, [r3]
>> +#if defined (___ARM_ARCH_4T__) || defined (__ARM_ARCH_4__)
>
> NAK. ARMv4T supports bx intruction. ARMv4 doesn't.
>
You're strictly correct. My original rationale was to ensure there is
no disruption for people building for v4/v4T -- since the more
restricted functionality of Thumb-1 means people tend not to use it to
build the whole distro anyway.
If people using <v5 are prepared to accept the change, I've got no
problem with changing the #ifs to #ifdef __ARM_ARCH_4__
We can't get rid of the #ifdef though, unless we can persuade everyone
targeting v4 to build with gcc/as -march=armv4t + ld --fix-v4bx
(unlikely).
Cheers
---Dave
^ permalink raw reply
* [PATCH] ARM: gic: use handle_fasteoi_irq for SPIs
From: Thomas Gleixner @ 2011-02-17 9:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217091741.GA24627@n2100.arm.linux.org.uk>
On Thu, 17 Feb 2011, Russell King - ARM Linux wrote:
> On Wed, Feb 16, 2011 at 08:20:17PM +0100, Thomas Gleixner wrote:
> > On Wed, 16 Feb 2011, Rabin Vincent wrote:
> > > On Wed, Feb 16, 2011 at 21:47, Will Deacon <will.deacon@arm.com> wrote:
> > > > Ah yes, thanks for the explanation. After looking at the plat-omap code
> > > > I finally understand what's going on and I can't help but feel that the
> > > > chained GPIO handlers are terminally broken! The generic irq chip high-level
> > > > handlers (handle_{edge,level}_irq for example) at least check to see if
> > > > the irq_chip functions are non-NULL before calling them.
> > > >
> > > > Ideally, the chained handler would be able to query the irq_chip to find
> > > > out what types of IRQ flow-control it supports and then assume that behaviour.
> > >
> > > Thomas, suggestions on how best to handle this? (Some of these chained
> > > handlers are the ones in plat-omap/gpio.c, plat-nomadik/gpio.c, and
> > > mach-s5pv310/irq-combiner.c.)
> >
> > I'm not much of a fan of those chained handlers. They work fine, when
> > they are tied into the irq_chip implementation of a SoC where the
> > chained handler code is 1:1 related to that irq_chip.
> >
> > Once you start assigning those handlers somewhere else or even using
> > the same handler for different underlying primary irq chips, then it's
> > a lost case and wreckage like this is just lurking around the corner.
>
> That's a result of genirq. With the ARM non-genirq implementation
> where we had just ack, mask and unmask, it all turned out much easier.
> In fact, we hardly ever called any of these functions in chained
> handlers (except ack) - the only time when mask and unmask were called
> was when we had an IRQ multiplexer which didn't allow us to mask the
> individual interrupts.
>
> With the advent of genirq and its expansion of the irq chip methods it's
> become much more complicated. That's one of the faults of trying to
> generalize this across different architectures.
>
> You can't do without chained handlers on ARM - we used to do it without
> them and it was proven to be a complete disaster. Dropped interrupts
> and various drivers just didn't work with chained interrupt controllers.
I really have a hard time to see the difference between doing:
chained_handler()
fiddle_with_primary_chip()
demux()
fiddle_with_primary_chip()
and
handle_xxxx_irq()
fiddle_with_primary_chip()
chained_handler()
demux()
fiddle_with_primary_chip()
Why should that drop more interrupt? The only difference is that you
make the demux handler oblivious of the underlying primary chip and
let the chip chose the appropriate flow handler which issues the right
chip methods.
> So getting rid of it is also a 'lost cause'.
I didn't say that we need to get rid of chained handlers. You just
have to be very careful about them. Nothing new - with or without
genirq.
Thanks,
tglx
^ permalink raw reply
* [PATCH V3 1/4] ARM: Xilinx: Adding Xilinx board support
From: Jamie Iles @ 2011-02-17 9:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ad969bd6-87bb-4910-a04a-d680e90d69af@VA3EHSMHS009.ehs.local>
Hi John,
One nitpick, otherwise looks nice.
Jamie
On Wed, Feb 16, 2011 at 09:11:53AM -0700, John Linn wrote:
> diff --git a/arch/arm/mach-xilinx/common.h b/arch/arm/mach-xilinx/common.h
> new file mode 100644
> index 0000000..9a7cf65
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/common.h
> @@ -0,0 +1,30 @@
> +/* arch/arm/mach-xilinx/common.h
> + *
> + * This file contains common function prototypes to avoid externs
> + * in the c files.
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_XILINX_COMMON_H__
> +#define __MACH_XILINX_COMMON_H__
> +
> +#include <linux/init.h>
> +#include <linux/platform_device.h>
You don't appear to use the contents of platform_device.h in here so you
could probably drop this include.
^ permalink raw reply
* compiling 2.6.37 kernel in THUMB2 mode
From: Dave Martin @ 2011-02-17 9:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTi=_=jzs+MrvGbwF3L0c_eSq4nnbqE-xZ_+Z5fgH@mail.gmail.com>
Hi,
On Thu, Feb 17, 2011 at 2:02 AM, <vb@vsbe.com> wrote:
> On Wed, Feb 16, 2011 at 1:19 AM, Dave Martin <dave.martin@linaro.org> wrote:
>>>
>>> Note that while the bulk of the kernel is Thumb-2 safe, there are
>>> occasional regressions, and individual platforms and drivers could
>>> still have problems. ?For now, I've been focusing on omap--- see
>>>
>>> git://git.linaro.org/people/dmart/linux-2.6-arm.git dirty/arm/omap-thumb2+merged
>>>
>>> ARM: Add local symbols in relocate_kernel.S to work around gas bugs
>>
>> ^ Oops, forgot to explain that line: this is the patch required to
>> work around a specific bug in the assembler. ?I'm not currently
>> proposing to merge this upstream, since I prefer the assembler to get
>> fixed...
>> You can grab this patch from the branch.
>>
>
> Dave, thank you for this information. I checked out this branch and
> would like to build a kernel. I don't know what omap is though, can
> you please share a config file one could use to build the thumb
> enabled kernel for it?
OMAP is one of TI's applications processor families.
^ permalink raw reply
* [PATCH 2/2] ARM: remove the 4x expansion presumption while decompressing the kernel
From: Russell King - ARM Linux @ 2011-02-17 9:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217000923.GF2364@angua.secretlab.ca>
On Wed, Feb 16, 2011 at 05:09:23PM -0700, Grant Likely wrote:
> Patch looks good to me, but on a related note, I'm looking for a way
> to also find the end of .bss.
>
> When John looks at adding support for appending an initrd and/or dtb
> to the zimage, it will be important to make sure the start of the
> initrd/dtb does not overlap the ram the kernel is expecting to be
> empty and available.
Appending data to the zImage has already been solved with the 'bootp'
stuff - and I'm afraid to say that merely catting a zImage with something
else just isn't going to work. There's no way for the zImage decompressor
to know that there's anything on the end of the image, and there's no way
for it to know where it can relocate itself to or where in memory it can
safely decompress to in such scenarios.
While such stuff may be possible with architectures where you know memory
always starts at zero and extends contiguously for N MB where N is some
number larger than 16, we don't have that luxury on ARM. Sometimes it
might be in 4MB chunks scattered throughout the physical address space
at maybe 256MB offset from zero. Or maybe 32MB chunks starting at 3GB.
etc.
And that's why the 'bootp' stuff takes a fixed address for where to
locate the initrd - the only person who knows where its safe to do so is
the person building the image for the platform.
^ permalink raw reply
* [PATCH] ARM: gic: use handle_fasteoi_irq for SPIs
From: Russell King - ARM Linux @ 2011-02-17 9:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1102162008490.2701@localhost6.localdomain6>
On Wed, Feb 16, 2011 at 08:20:17PM +0100, Thomas Gleixner wrote:
> On Wed, 16 Feb 2011, Rabin Vincent wrote:
> > On Wed, Feb 16, 2011 at 21:47, Will Deacon <will.deacon@arm.com> wrote:
> > > Ah yes, thanks for the explanation. After looking at the plat-omap code
> > > I finally understand what's going on and I can't help but feel that the
> > > chained GPIO handlers are terminally broken! The generic irq chip high-level
> > > handlers (handle_{edge,level}_irq for example) at least check to see if
> > > the irq_chip functions are non-NULL before calling them.
> > >
> > > Ideally, the chained handler would be able to query the irq_chip to find
> > > out what types of IRQ flow-control it supports and then assume that behaviour.
> >
> > Thomas, suggestions on how best to handle this? (Some of these chained
> > handlers are the ones in plat-omap/gpio.c, plat-nomadik/gpio.c, and
> > mach-s5pv310/irq-combiner.c.)
>
> I'm not much of a fan of those chained handlers. They work fine, when
> they are tied into the irq_chip implementation of a SoC where the
> chained handler code is 1:1 related to that irq_chip.
>
> Once you start assigning those handlers somewhere else or even using
> the same handler for different underlying primary irq chips, then it's
> a lost case and wreckage like this is just lurking around the corner.
That's a result of genirq. With the ARM non-genirq implementation
where we had just ack, mask and unmask, it all turned out much easier.
In fact, we hardly ever called any of these functions in chained
handlers (except ack) - the only time when mask and unmask were called
was when we had an IRQ multiplexer which didn't allow us to mask the
individual interrupts.
With the advent of genirq and its expansion of the irq chip methods it's
become much more complicated. That's one of the faults of trying to
generalize this across different architectures.
You can't do without chained handlers on ARM - we used to do it without
them and it was proven to be a complete disaster. Dropped interrupts
and various drivers just didn't work with chained interrupt controllers.
So getting rid of it is also a 'lost cause'.
^ permalink raw reply
* [PATCH V4 resend] rtc: Adding support for spear rtc
From: viresh kumar @ 2011-02-17 9:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6bd0f375a2f9475172a3ea968b0662b7c73da421.1297247552.git.viresh.kumar@st.com>
On 02/09/2011 04:06 PM, Viresh KUMAR wrote:
> From: Rajeev Kumar <rajeev-dlh.kumar@st.com>
>
> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
> Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
> ---
> drivers/rtc/Kconfig | 8 +
> drivers/rtc/Makefile | 1 +
> drivers/rtc/rtc-spear.c | 534 +++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 543 insertions(+), 0 deletions(-)
> create mode 100644 drivers/rtc/rtc-spear.c
Guys,
Am i posting this patch to incorrect lists?
We have been awaiting review/inclusion for this patch since 2-3 months now.
Can somebody please help?
--
viresh
^ permalink raw reply
* [PATCH v3 3/3] ARM: IMX5 bbg: add cpuidle parameters
From: yong.shen at linaro.org @ 2011-02-17 9:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297933299-30367-1-git-send-email-yong.shen@linaro.org>
From: Yong Shen <yong.shen@freescale.com>
This parameters are workable, but need further tuning.
Signed-off-by: Yong Shen <yong.shen@freescale.com>
---
arch/arm/mach-mx5/board-mx51_babbage.c | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index d9d402e..bb6fda0 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -37,6 +37,7 @@
#include "devices-imx51.h"
#include "devices.h"
#include "cpu_op-mx51.h"
+#include "cpuidle.h"
#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
@@ -333,6 +334,11 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
.num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
};
+static struct mx5_cpuidle_params babbage_cpuidle_params[] = {
+ {100,},
+ {150,},
+ {1000,},
+};
/*
* Board specific initialization.
*/
@@ -383,6 +389,8 @@ static void __init mxc_board_init(void)
ARRAY_SIZE(mx51_babbage_spi_board_info));
imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
imx51_add_imx2_wdt(0, NULL);
+
+ mx5_cpuidle_board_params(babbage_cpuidle_params);
}
static void __init mx51_babbage_timer_init(void)
--
1.7.1
^ permalink raw reply related
* [PATCH v3 2/3] ARM: IMX5: cpuidle driver
From: yong.shen at linaro.org @ 2011-02-17 9:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297933299-30367-1-git-send-email-yong.shen@linaro.org>
From: Yong Shen <yong.shen@freescale.com>
implement cpuidle driver for iMX5 SOCs, leave cpuidle params to board
related code.
Signed-off-by: Yong Shen <yong.shen@freescale.com>
---
arch/arm/mach-mx5/Makefile | 1 +
arch/arm/mach-mx5/cpuidle.c | 112 +++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-mx5/cpuidle.h | 25 ++++++++++
3 files changed, 138 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-mx5/cpuidle.c
create mode 100644 arch/arm/mach-mx5/cpuidle.h
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 0d43be9..12239e0 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -7,6 +7,7 @@ obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o
obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
+obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
diff --git a/arch/arm/mach-mx5/cpuidle.c b/arch/arm/mach-mx5/cpuidle.c
new file mode 100644
index 0000000..64bfb6f
--- /dev/null
+++ b/arch/arm/mach-mx5/cpuidle.c
@@ -0,0 +1,112 @@
+/*
+ * arch/arm/mach-mx5/cpuidle.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/cpuidle.h>
+#include <asm/proc-fns.h>
+#include <mach/hardware.h>
+#include "cpuidle.h"
+#include "crm_regs.h"
+
+static struct mx5_cpuidle_params *mx5_cpuidle_params;
+void mx5_cpuidle_board_params(struct mx5_cpuidle_params *cpuidle_params)
+{
+ mx5_cpuidle_params = cpuidle_params;
+}
+
+static int mx5_enter_idle(struct cpuidle_device *dev,
+ struct cpuidle_state *state)
+{
+ struct timeval before, after;
+ int idle_time;
+ u32 plat_lpc, arm_srpgcr, ccm_clpcr;
+ u32 empgc0, empgc1;
+
+ local_irq_disable();
+ do_gettimeofday(&before);
+
+ plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
+ ~(MXC_CORTEXA8_PLAT_LPC_DSM);
+ ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
+ arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
+ empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
+ empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
+
+ /* for WAIT_CLK_ON, we do nothing but cpu_do_idle() */
+ if (state == &dev->states[WAIT_CLK_OFF])
+ ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET);
+ else if (state == &dev->states[WAIT_CLK_OFF_POWER_OFF]) {
+ /* Wait unclocked, power off */
+ plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
+ | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
+ arm_srpgcr |= MXC_SRPGCR_PCR;
+ ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET);
+ ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
+ ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
+ if (tzic_enable_wake(1) != 0) {
+ local_irq_enable();
+ return 0;
+ }
+ }
+
+ __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
+ __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
+ __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
+
+ cpu_do_idle();
+
+ do_gettimeofday(&after);
+ local_irq_enable();
+ idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+ (after.tv_usec - before.tv_usec);
+ return idle_time;
+}
+
+static struct cpuidle_driver mx5_cpuidle_driver = {
+ .name = "mx5_idle",
+ .owner = THIS_MODULE,
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, mx5_cpuidle_device);
+
+static int __init mx5_cpuidle_init(void)
+{
+ struct cpuidle_device *device;
+ int i;
+
+ if (mx5_cpuidle_params == NULL) {
+ printk(KERN_ERR "mx5_cpuidle_init: no cpuidle params\n");
+ return -ENODEV;
+ }
+
+ cpuidle_register_driver(&mx5_cpuidle_driver);
+
+ device = &per_cpu(mx5_cpuidle_device, smp_processor_id());
+ device->state_count = MX5_MAX_CPUIDLE_STATE;
+
+ for (i = 0; i < MX5_MAX_CPUIDLE_STATE && i < CPUIDLE_STATE_MAX; i++) {
+ device->states[i].enter = mx5_enter_idle;
+ device->states[i].exit_latency = mx5_cpuidle_params[i].latency;
+ device->states[i].flags = CPUIDLE_FLAG_TIME_VALID;
+ }
+
+ strcpy(device->states[WAIT_CLK_ON].name, "WFI 0");
+ strcpy(device->states[WAIT_CLK_ON].desc, "Wait with clock on");
+ strcpy(device->states[WAIT_CLK_OFF].name, "WFI 1");
+ strcpy(device->states[WAIT_CLK_OFF].desc, "Wait with clock off");
+ strcpy(device->states[WAIT_CLK_OFF_POWER_OFF].name, "WFI 2");
+ strcpy(device->states[WAIT_CLK_OFF_POWER_OFF].desc,
+ "Wait with clock off and power gating");
+
+ if (cpuidle_register_device(device)) {
+ printk(KERN_ERR "mx5_cpuidle_init: Failed registering\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+late_initcall(mx5_cpuidle_init);
diff --git a/arch/arm/mach-mx5/cpuidle.h b/arch/arm/mach-mx5/cpuidle.h
new file mode 100644
index 0000000..ffd7314
--- /dev/null
+++ b/arch/arm/mach-mx5/cpuidle.h
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-mx5/cpuidle.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+enum {
+ WAIT_CLK_ON, /* c1 */
+ WAIT_CLK_OFF, /* c2 */
+ WAIT_CLK_OFF_POWER_OFF, /* c3 */
+ MX5_MAX_CPUIDLE_STATE,
+};
+
+struct mx5_cpuidle_params {
+ unsigned int latency;
+};
+
+#ifdef CONFIG_CPU_IDLE
+extern void mx5_cpuidle_board_params(struct mx5_cpuidle_params *cpuidle_params);
+#else
+inline void mx5_cpuidle_board_params(struct mx5_cpuidle_params *cpuidle_params)
+{}
+#endif
--
1.7.1
^ permalink raw reply related
* [PATCH v3 1/3] ARM: IMX: add tzic_enable_wake in the head file
From: yong.shen at linaro.org @ 2011-02-17 9:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297933299-30367-1-git-send-email-yong.shen@linaro.org>
From: Yong Shen <yong.shen@freescale.com>
Add tzic_enable_wake in the head file, so other code can call it.
Signed-off-by: Yong Shen <yong.shen@freescale.com>
---
arch/arm/plat-mxc/include/mach/mxc.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 04c7a26..962d742 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -182,6 +182,7 @@ struct cpu_op {
};
extern struct cpu_op *(*get_cpu_op)(int *op);
+extern int tzic_enable_wake(int is_idle);
#endif
#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
--
1.7.1
^ permalink raw reply related
* [PATCH v3 0/3] ARM: IMX5: cpuidle driver
From: yong.shen at linaro.org @ 2011-02-17 9:01 UTC (permalink / raw)
To: linux-arm-kernel
change log:
addressed some comments in previous cycle.
^ permalink raw reply
* [PATCH 2/2] plat-nomadik: fix compilation warning
From: Linus Walleij @ 2011-02-17 8:54 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
The compiler warns that [rf]wimsc may be used uninitialized in
this function - the warning is actually false since the uses are
in identical if()-clauses, but it can't hurt very much to read
out the values to be modified early anyway and rid the warning.
Cc: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/plat-nomadik/gpio.c | 7 ++-----
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 5e6653f..45b1cf9 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -134,15 +134,12 @@ static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
unsigned offset, int gpio_mode,
bool glitch)
{
- u32 rwimsc;
- u32 fwimsc;
+ u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
+ u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
if (glitch && nmk_chip->set_ioforce) {
u32 bit = BIT(offset);
- rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
- fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
-
/* Prevent spurious wakeups */
writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
--
1.7.3.2
^ permalink raw reply related
* [PATCH 1/2] plat-nomadik: get rid of unused GPIO PM code
From: Linus Walleij @ 2011-02-17 8:54 UTC (permalink / raw)
To: linux-arm-kernel
From: Rabin Vincent <rabin.vincent@stericsson.com>
The NOMADIK_GPIO_PM config option is disabled by default, not user visible,
and never selected by any other option: the code is therefore unused. The
GPIO registers need not be saved and restored since their values are
preserved when vAPE (on DB8500) is powered down.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Reviewed-by: Jonas Aberg <jonas.aberg@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/plat-nomadik/Kconfig | 6 ---
arch/arm/plat-nomadik/gpio.c | 76 ++---------------------------------------
2 files changed, 3 insertions(+), 79 deletions(-)
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig
index ad25c96..187f4e8 100644
--- a/arch/arm/plat-nomadik/Kconfig
+++ b/arch/arm/plat-nomadik/Kconfig
@@ -25,10 +25,4 @@ config NOMADIK_GPIO
help
Support for the Nomadik GPIO controller.
-config NOMADIK_GPIO_PM
- bool
- depends on NOMADIK_GPIO && PM
- help
- Support PM for the Nomadik GPIO controller.
-
endif
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index acc9de2..5e6653f 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -35,18 +35,6 @@
* Symbols in this file are called "nmk_gpio" for "nomadik gpio"
*/
-static const u32 backup_regs[] = {
- NMK_GPIO_PDIS,
- NMK_GPIO_DIR,
- NMK_GPIO_AFSLA,
- NMK_GPIO_AFSLB,
- NMK_GPIO_SLPC,
- NMK_GPIO_RIMSC,
- NMK_GPIO_FIMSC,
- NMK_GPIO_RWIMSC,
- NMK_GPIO_FWIMSC,
-};
-
#define NMK_GPIO_PER_CHIP 32
struct nmk_gpio_chip {
@@ -62,9 +50,6 @@ struct nmk_gpio_chip {
/* Keep track of configured edges */
u32 edge_rising;
u32 edge_falling;
- u32 backup[ARRAY_SIZE(backup_regs)];
- /* Bitmap, 1 = pull up, 0 = pull down */
- u32 pull;
};
static struct nmk_gpio_chip *
@@ -117,13 +102,10 @@ static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
pdis &= ~bit;
writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
- if (pull == NMK_GPIO_PULL_UP) {
- nmk_chip->pull |= bit;
+ if (pull == NMK_GPIO_PULL_UP)
writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
- } else if (pull == NMK_GPIO_PULL_DOWN) {
- nmk_chip->pull &= ~bit;
+ else if (pull == NMK_GPIO_PULL_DOWN)
writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
- }
}
static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
@@ -991,64 +973,12 @@ out:
return ret;
}
-#ifdef CONFIG_NOMADIK_GPIO_PM
-static int nmk_gpio_pm(struct platform_device *dev, bool suspend)
-{
- struct nmk_gpio_chip *nmk_chip = platform_get_drvdata(dev);
- int i;
- u32 dir;
- u32 dat;
-
- for (i = 0; i < ARRAY_SIZE(backup_regs); i++) {
- if (suspend)
- nmk_chip->backup[i] = readl(nmk_chip->addr +
- backup_regs[i]);
- else
- writel(nmk_chip->backup[i],
- nmk_chip->addr + backup_regs[i]);
- }
-
- if (!suspend) {
- /*
- * Restore pull-up and pull-down on inputs and
- * outputs.
- */
- dir = readl(nmk_chip->addr + NMK_GPIO_DIR);
- dat = readl(nmk_chip->addr + NMK_GPIO_DAT);
-
- writel((nmk_chip->pull & ~dir) |
- (dat & dir),
- nmk_chip->addr + NMK_GPIO_DATS);
-
- writel((~nmk_chip->pull & ~dir) |
- (~dat & dir),
- nmk_chip->addr + NMK_GPIO_DATC);
- }
- return 0;
-}
-
-static int nmk_gpio_suspend(struct platform_device *dev, pm_message_t state)
-{
- return nmk_gpio_pm(dev, true);
-}
-
-static int nmk_gpio_resume(struct platform_device *dev)
-{
- return nmk_gpio_pm(dev, false);
-}
-#else
-#define nmk_gpio_suspend NULL
-#define nmk_gpio_resume NULL
-#endif
-
static struct platform_driver nmk_gpio_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "gpio",
- },
+ },
.probe = nmk_gpio_probe,
- .suspend = nmk_gpio_suspend,
- .resume = nmk_gpio_resume,
};
static int __init nmk_gpio_init(void)
--
1.7.3.2
^ permalink raw reply related
* [PATCH v2 1/2] ARM: IMX5: cpuidle driver
From: Yong Shen @ 2011-02-17 8:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215182752.GD2027@pengutronix.de>
>
>
> > + return 0;
> > +}
> > +
> > +late_initcall(imx_cpuidle_init);
>
> We have a late_initcall here which needs to be protected from other
> cpus. On the other hand we depend on board code calling
> imx_cpuidle_board_params() before this initcall. I think the board code
> should call a imx_cpuidle_init(struct imx_cpuidle_params
> *cpuidle_params) instead which makes the flow of execution more clear.
>
> imx_cpuidle_init can not be called directly in board code, since it is too
early to register cpuidle driver and device which depend on some other
system resource.
Yong
-------------- next part --------------
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^ permalink raw reply
* [PATCH] amba: move to pm ops
From: Rabin Vincent @ 2011-02-17 7:49 UTC (permalink / raw)
To: linux-arm-kernel
Support pm_ops in the AMBA bus instead of the legacy ops. pm_ops is needed
for runtime pm, and there is also a general move to convert drivers to
dev_pm_ops rather than bus specific PM ops in order to facilitate core
development.
Since there are only 6 AMBA drivers using suspend/resume, convert them all in
one go and directly use the GENERIC_SUBSYS_PM_OPS in the bus.
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Chris Ball <cjb@laptop.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
---
drivers/amba/bus.c | 25 ++-----------------------
drivers/input/serio/ambakmi.c | 13 ++++++++++---
drivers/mmc/host/mmci.c | 17 ++++++++++-------
drivers/spi/amba-pl022.c | 15 +++++++++------
drivers/tty/serial/amba-pl010.c | 20 ++++++++++++++------
drivers/tty/serial/amba-pl011.c | 22 +++++++++++++---------
include/linux/amba/bus.h | 4 ++--
sound/arm/aaci.c | 18 ++++++++++--------
8 files changed, 70 insertions(+), 64 deletions(-)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index ca96b0a..402b07e 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -13,12 +13,12 @@
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/io.h>
+#include <linux/pm.h>
#include <linux/amba/bus.h>
#include <asm/irq.h>
#include <asm/sizes.h>
-#define to_amba_device(d) container_of(d, struct amba_device, dev)
#define to_amba_driver(d) container_of(d, struct amba_driver, drv)
static struct amba_id *
@@ -57,26 +57,6 @@ static int amba_uevent(struct device *dev, struct kobj_uevent_env *env)
#define amba_uevent NULL
#endif
-static int amba_suspend(struct device *dev, pm_message_t state)
-{
- struct amba_driver *drv = to_amba_driver(dev->driver);
- int ret = 0;
-
- if (dev->driver && drv->suspend)
- ret = drv->suspend(to_amba_device(dev), state);
- return ret;
-}
-
-static int amba_resume(struct device *dev)
-{
- struct amba_driver *drv = to_amba_driver(dev->driver);
- int ret = 0;
-
- if (dev->driver && drv->resume)
- ret = drv->resume(to_amba_device(dev));
- return ret;
-}
-
#define amba_attr_func(name,fmt,arg...) \
static ssize_t name##_show(struct device *_dev, \
struct device_attribute *attr, char *buf) \
@@ -111,8 +91,7 @@ struct bus_type amba_bustype = {
.dev_attrs = amba_dev_attrs,
.match = amba_match,
.uevent = amba_uevent,
- .suspend = amba_suspend,
- .resume = amba_resume,
+ .pm = GENERIC_SUBSYS_PM_OPS,
};
static int __init amba_init(void)
diff --git a/drivers/input/serio/ambakmi.c b/drivers/input/serio/ambakmi.c
index 92563a6..c710437 100644
--- a/drivers/input/serio/ambakmi.c
+++ b/drivers/input/serio/ambakmi.c
@@ -176,15 +176,22 @@ static int __devexit amba_kmi_remove(struct amba_device *dev)
return 0;
}
-static int amba_kmi_resume(struct amba_device *dev)
+#ifdef CONFIG_PM_SLEEP
+static int amba_kmi_resume(struct device *dev)
{
- struct amba_kmi_port *kmi = amba_get_drvdata(dev);
+ struct amba_device *adev = to_amba_device(dev);
+ struct amba_kmi_port *kmi = amba_get_drvdata(adev);
/* kick the serio layer to rescan this port */
serio_reconnect(kmi->io);
return 0;
}
+#else
+#define amba_kmi_resume NULL
+#endif
+
+static SIMPLE_DEV_PM_OPS(amba_kmi_pm, NULL, amba_kmi_resume);
static struct amba_id amba_kmi_idtable[] = {
{
@@ -198,11 +205,11 @@ static struct amba_driver ambakmi_driver = {
.drv = {
.name = "kmi-pl050",
.owner = THIS_MODULE,
+ .pm = &amba_kmi_pm,
},
.id_table = amba_kmi_idtable,
.probe = amba_kmi_probe,
.remove = __devexit_p(amba_kmi_remove),
- .resume = amba_kmi_resume,
};
static int __init amba_kmi_init(void)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 8a29c9f..18e142b 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -1236,10 +1236,11 @@ static int __devexit mmci_remove(struct amba_device *dev)
return 0;
}
-#ifdef CONFIG_PM
-static int mmci_suspend(struct amba_device *dev, pm_message_t state)
+#ifdef CONFIG_PM_SLEEP
+static int mmci_suspend(struct device *dev)
{
- struct mmc_host *mmc = amba_get_drvdata(dev);
+ struct amba_device *adev = to_amba_device(dev);
+ struct mmc_host *mmc = amba_get_drvdata(adev);
int ret = 0;
if (mmc) {
@@ -1253,9 +1254,10 @@ static int mmci_suspend(struct amba_device *dev, pm_message_t state)
return ret;
}
-static int mmci_resume(struct amba_device *dev)
+static int mmci_resume(struct device *dev)
{
- struct mmc_host *mmc = amba_get_drvdata(dev);
+ struct amba_device *adev = to_amba_device(dev);
+ struct mmc_host *mmc = amba_get_drvdata(adev);
int ret = 0;
if (mmc) {
@@ -1273,6 +1275,8 @@ static int mmci_resume(struct amba_device *dev)
#define mmci_resume NULL
#endif
+static SIMPLE_DEV_PM_OPS(mmci_pm, mmci_suspend, mmci_resume);
+
static struct amba_id mmci_ids[] = {
{
.id = 0x00041180,
@@ -1306,11 +1310,10 @@ static struct amba_id mmci_ids[] = {
static struct amba_driver mmci_driver = {
.drv = {
.name = DRIVER_NAME,
+ .pm = &mmci_pm,
},
.probe = mmci_probe,
.remove = __devexit_p(mmci_remove),
- .suspend = mmci_suspend,
- .resume = mmci_resume,
.id_table = mmci_ids,
};
diff --git a/drivers/spi/amba-pl022.c b/drivers/spi/amba-pl022.c
index 71a1219..eb16ea5 100644
--- a/drivers/spi/amba-pl022.c
+++ b/drivers/spi/amba-pl022.c
@@ -2184,9 +2184,10 @@ pl022_remove(struct amba_device *adev)
return 0;
}
-#ifdef CONFIG_PM
-static int pl022_suspend(struct amba_device *adev, pm_message_t state)
+#ifdef CONFIG_PM_SLEEP
+static int pl022_suspend(struct device *dev)
{
+ struct amba_device *adev = to_amba_device(dev);
struct pl022 *pl022 = amba_get_drvdata(adev);
int status = 0;
@@ -2203,8 +2204,9 @@ static int pl022_suspend(struct amba_device *adev, pm_message_t state)
return 0;
}
-static int pl022_resume(struct amba_device *adev)
+static int pl022_resume(struct device *dev)
{
+ struct amba_device *adev = to_amba_device(dev);
struct pl022 *pl022 = amba_get_drvdata(adev);
int status = 0;
@@ -2220,7 +2222,9 @@ static int pl022_resume(struct amba_device *adev)
#else
#define pl022_suspend NULL
#define pl022_resume NULL
-#endif /* CONFIG_PM */
+#endif
+
+static SIMPLE_DEV_PM_OPS(pl022_pm, pl022_suspend, pl022_resume);
static struct vendor_data vendor_arm = {
.fifodepth = 8,
@@ -2284,12 +2288,11 @@ static struct amba_id pl022_ids[] = {
static struct amba_driver pl022_driver = {
.drv = {
.name = "ssp-pl022",
+ .pm = &pl022_pm,
},
.id_table = pl022_ids,
.probe = pl022_probe,
.remove = __devexit_p(pl022_remove),
- .suspend = pl022_suspend,
- .resume = pl022_resume,
};
diff --git a/drivers/tty/serial/amba-pl010.c b/drivers/tty/serial/amba-pl010.c
index 2904aa0..5e0e62f 100644
--- a/drivers/tty/serial/amba-pl010.c
+++ b/drivers/tty/serial/amba-pl010.c
@@ -757,9 +757,11 @@ static int pl010_remove(struct amba_device *dev)
return 0;
}
-static int pl010_suspend(struct amba_device *dev, pm_message_t state)
+#ifdef CONFIG_PM_SLEEP
+static int pl010_suspend(struct device *dev)
{
- struct uart_amba_port *uap = amba_get_drvdata(dev);
+ struct amba_device *adev = to_amba_device(dev);
+ struct uart_amba_port *uap = amba_get_drvdata(adev);
if (uap)
uart_suspend_port(&amba_reg, &uap->port);
@@ -767,15 +769,22 @@ static int pl010_suspend(struct amba_device *dev, pm_message_t state)
return 0;
}
-static int pl010_resume(struct amba_device *dev)
+static int pl010_resume(struct device *dev)
{
- struct uart_amba_port *uap = amba_get_drvdata(dev);
+ struct amba_device *adev = to_amba_device(dev);
+ struct uart_amba_port *uap = amba_get_drvdata(adev);
if (uap)
uart_resume_port(&amba_reg, &uap->port);
return 0;
}
+#else
+#define pl010_suspend NULL
+#define pl010_resume NULL
+#endif
+
+static SIMPLE_DEV_PM_OPS(pl010_pm, pl010_suspend, pl010_resume);
static struct amba_id pl010_ids[] = {
{
@@ -788,12 +797,11 @@ static struct amba_id pl010_ids[] = {
static struct amba_driver pl010_driver = {
.drv = {
.name = "uart-pl010",
+ .pm = &pl010_pm,
},
.id_table = pl010_ids,
.probe = pl010_probe,
.remove = pl010_remove,
- .suspend = pl010_suspend,
- .resume = pl010_resume,
};
static int __init pl010_init(void)
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index e76d7d0..52a5e18 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1438,10 +1438,11 @@ static int pl011_remove(struct amba_device *dev)
return 0;
}
-#ifdef CONFIG_PM
-static int pl011_suspend(struct amba_device *dev, pm_message_t state)
+#ifdef CONFIG_PM_SLEEP
+static int pl011_suspend(struct device *dev)
{
- struct uart_amba_port *uap = amba_get_drvdata(dev);
+ struct amba_device *adev = to_amba_device(dev);
+ struct uart_amba_port *uap = amba_get_drvdata(adev);
if (!uap)
return -EINVAL;
@@ -1449,17 +1450,23 @@ static int pl011_suspend(struct amba_device *dev, pm_message_t state)
return uart_suspend_port(&amba_reg, &uap->port);
}
-static int pl011_resume(struct amba_device *dev)
+static int pl011_resume(struct device *dev)
{
- struct uart_amba_port *uap = amba_get_drvdata(dev);
+ struct amba_device *adev = to_amba_device(dev);
+ struct uart_amba_port *uap = amba_get_drvdata(adev);
if (!uap)
return -EINVAL;
return uart_resume_port(&amba_reg, &uap->port);
}
+#else
+#define pl011_suspend NULL
+#define pl011_resume NULL
#endif
+static SIMPLE_DEV_PM_OPS(pl011_pm, pl011_suspend, pl011_resume);
+
static struct amba_id pl011_ids[] = {
{
.id = 0x00041011,
@@ -1477,14 +1484,11 @@ static struct amba_id pl011_ids[] = {
static struct amba_driver pl011_driver = {
.drv = {
.name = "uart-pl011",
+ .pm = &pl011_pm,
},
.id_table = pl011_ids,
.probe = pl011_probe,
.remove = pl011_remove,
-#ifdef CONFIG_PM
- .suspend = pl011_suspend,
- .resume = pl011_resume,
-#endif
};
static int __init pl011_init(void)
diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h
index a0ccf28..2f48827 100644
--- a/include/linux/amba/bus.h
+++ b/include/linux/amba/bus.h
@@ -46,8 +46,6 @@ struct amba_driver {
int (*probe)(struct amba_device *, struct amba_id *);
int (*remove)(struct amba_device *);
void (*shutdown)(struct amba_device *);
- int (*suspend)(struct amba_device *, pm_message_t);
- int (*resume)(struct amba_device *);
struct amba_id *id_table;
};
@@ -58,6 +56,8 @@ enum amba_vendor {
extern struct bus_type amba_bustype;
+#define to_amba_device(d) container_of(d, struct amba_device, dev)
+
#define amba_get_drvdata(d) dev_get_drvdata(&d->dev)
#define amba_set_drvdata(d,p) dev_set_drvdata(&d->dev, p)
diff --git a/sound/arm/aaci.c b/sound/arm/aaci.c
index af5a152..040c5f0 100644
--- a/sound/arm/aaci.c
+++ b/sound/arm/aaci.c
@@ -35,7 +35,7 @@
/*
* PM support is not complete. Turn it off.
*/
-#undef CONFIG_PM
+#undef CONFIG_PM_SLEEP
static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
{
@@ -752,7 +752,7 @@ static struct snd_pcm_ops aaci_capture_ops = {
/*
* Power Management.
*/
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
static int aaci_do_suspend(struct snd_card *card, unsigned int state)
{
struct aaci *aaci = card->private_data;
@@ -767,15 +767,17 @@ static int aaci_do_resume(struct snd_card *card, unsigned int state)
return 0;
}
-static int aaci_suspend(struct amba_device *dev, pm_message_t state)
+static int aaci_suspend(struct device *dev)
{
- struct snd_card *card = amba_get_drvdata(dev);
+ struct amba_device *adev = to_amba_device(dev);
+ struct snd_card *card = amba_get_drvdata(adev);
return card ? aaci_do_suspend(card) : 0;
}
-static int aaci_resume(struct amba_device *dev)
+static int aaci_resume(struct device *dev)
{
- struct snd_card *card = amba_get_drvdata(dev);
+ struct amba_device *adev = to_amba_device(dev);
+ struct snd_card *card = amba_get_drvdata(adev);
return card ? aaci_do_resume(card) : 0;
}
#else
@@ -785,6 +787,7 @@ static int aaci_resume(struct amba_device *dev)
#define aaci_resume NULL
#endif
+static SIMPLE_DEV_PM_OPS(aaci_pm, aaci_suspend, aaci_resume);
static struct ac97_pcm ac97_defs[] __devinitdata = {
[0] = { /* Front PCM */
@@ -1099,11 +1102,10 @@ static struct amba_id aaci_ids[] = {
static struct amba_driver aaci_driver = {
.drv = {
.name = DRIVER_NAME,
+ .pm = &aaci_pm,
},
.probe = aaci_probe,
.remove = __devexit_p(aaci_remove),
- .suspend = aaci_suspend,
- .resume = aaci_resume,
.id_table = aaci_ids,
};
--
1.7.2.dirty
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