* [patch v2 4/5] efika: enable cpufreq
From: Arnaud Patard (Rtp) @ 2011-02-17 14:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217143127.307109680@rtp-net.org>
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* [patch v2 3/5] efikamx: add mc13892 support / implement power off
From: Arnaud Patard (Rtp) @ 2011-02-17 14:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217143127.307109680@rtp-net.org>
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* [patch v2 2/5] efikamx: add usb h1 support
From: Arnaud Patard (Rtp) @ 2011-02-17 14:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217143127.307109680@rtp-net.org>
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* [patch v2 1/5] Introduce EFIKA_COMMON
From: Arnaud Patard (Rtp) @ 2011-02-17 14:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217143127.307109680@rtp-net.org>
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* [patch v2 0/5] Genesi Efika MX/SB support improvements
From: Arnaud Patard (Rtp) @ 2011-02-17 14:31 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This patch series aims at improving current efika mx support and adds support
for efika smartbook. Given the similarities between the two systems, the first
patch moves mx some code into a new file which will contain code shared by both
systems and the last patch adds support for efika smartbook.
Change since v1:
- rebased on ehci cleanup patches (which seems to be now merged in
Sascha's imx for-next tree)
- use machine_is_* in initcalls
- drop dead uart-related code
Arnaud
^ permalink raw reply
* [PATCH V3 2/4] ARM: Xilinx: Adding timer support to the platform
From: John Linn @ 2011-02-17 14:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217094801.GC22961@pulham.picochip.com>
> -----Original Message-----
> From: Jamie Iles [mailto:jamie at jamieiles.com]
> Sent: Thursday, February 17, 2011 2:48 AM
> To: John Linn
> Cc: linux-arm-kernel at lists.infradead.org;
linux-kernel at vger.kernel.org; linux at arm.linux.org.uk;
> catalin.marinas at arm.com; glikely at secretlab.ca; arnd at arndb.de; Kiran
Sutariya
> Subject: Re: [PATCH V3 2/4] ARM: Xilinx: Adding timer support to the
platform
>
> Hi John,
>
> A couple more nitpicks.
>
> Jamie
>
> On Wed, Feb 16, 2011 at 09:11:54AM -0700, John Linn wrote:
> > The timer driver supports the Xilinx PS Timer Counter IP.
> >
> > Signed-off-by: Kiran Sutariya <kiran.sutariya@einfochips.com>
> > Signed-off-by: John Linn <john.linn@xilinx.com>
> > ---
> >
> > V3 Changes
> >
> > Updates based on Russell Kings' comments
> > Changed headers to update the license info and remove
> > the address
> >
> > V2 Changes
> >
> > The timer code was changed quite a bit based on review inputs. It
> > got much smaller and cleaner I think.
> >
> > Updates based on Russell King's comments
> > minor cleanups for documentation comments
> > removed the name from the timer structure
> > removed interrupt for clock source
> > moved to using clock functions provided in the kernel
> > for calculating shift/mult values
> > removed PM code as generic handles it
> >
> > Updated based on Jamie Iles's comment
> > cleaned up ENABLE_MASK which was confusing
> > now using platform_add_devices() from platform code
> > moved base_addr to void __iomem pointer
> > removed stop of the event timer in one shot mode
> >
> > arch/arm/mach-xilinx/Makefile | 2 +-
> > arch/arm/mach-xilinx/timer.c | 301
+++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 302 insertions(+), 1 deletions(-)
> > create mode 100644 arch/arm/mach-xilinx/timer.c
> >
> > diff --git a/arch/arm/mach-xilinx/Makefile
b/arch/arm/mach-xilinx/Makefile
> > index 76e9e55..660fb19 100644
> > --- a/arch/arm/mach-xilinx/Makefile
> > +++ b/arch/arm/mach-xilinx/Makefile
> > @@ -3,5 +3,5 @@
> > #
> >
> > # Common support
> > -obj-y := common.o
> > +obj-y := common.o timer.o
> > obj-$(CONFIG_MACH_XILINX) += board_ep107.o
> > diff --git a/arch/arm/mach-xilinx/timer.c
b/arch/arm/mach-xilinx/timer.c
> > new file mode 100644
> > index 0000000..f08a2f1
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/timer.c
> > @@ -0,0 +1,301 @@
> > +/* arch/arm/mach-xilinx/timer.c
> > + *
> > + * This file contains driver for the Xilinx PS Timer Counter IP.
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * based on arch/mips/kernel/time.c timer driver
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/init.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/irq.h>
> > +#include <linux/types.h>
> > +#include <linux/clocksource.h>
> > +#include <linux/clockchips.h>
> > +#include <linux/io.h>
> > +
> > +#include <asm/mach/time.h>
> > +#include <mach/xilinx_soc.h>
> > +
> > +/*
> > + * This driver configures the 2 16-bit count-up timers as follows:
> > + *
> > + * T1: Timer 1, clocksource for generic timekeeping
> > + * T2: Timer 2, clockevent source for hrtimers
> > + * T3: Timer 3, <unused>
> > + *
> > + * The input frequency to the timer module for emulation is 2.5MHz
which is
> > + * common to all the timer channels (T1, T2, and T3). With a
pre-scaler of 32,
> > + * the timers are clocked at 78.125KHz (12.8 us resolution).
> > + *
> > + * The input frequency to the timer module in silicon will be
200MHz. With the
> > + * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns
resolution).
> > + */
> > +#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic
timekeeping */
> > +#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */
> > +
> > +#define XTTCPSS_TIMER_BASE TTC0_BASE
> > +#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1)
> > +/*
> > + * Timer Register Offset Definitions of Timer 1, Increment base
address by 4
> > + * and use same offsets for Timer 2
> > + */
> > +#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
> > +#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW
*/
> > +#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
> > +#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count
Reg, RW */
> > +#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value
Reg, RW */
> > +#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value
Reg, RW */
> > +#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value
Reg, RW */
> > +#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO
*/
> > +#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW
*/
> > +
> > +#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1
> > +
> > +/**
> > + * struct xttcpss_timer - This definition defines local timer
structure
> > + *
> > + * @base_addr: Base address of timer
> > + * @timer_irq: irqaction structure for the timer device
> > + * @mode: only valid for an clock event, periodic or one-shot
> > + **/
> > +struct xttcpss_timer {
> > + void __iomem *base_addr;
> > + enum clock_event_mode mode;
>
> I can't see .mode being used anywhere in this file so this could
> probably be simplified a bit to just two base address pointers.
Yep, got removed in the cleanup. Obviously the cleanup didn't get quite
everything.
Will do.
>
> > +};
> > +
> > +static struct xttcpss_timer timers[2];
> > +static struct clock_event_device xttcpss_clockevent;
> > +
> > +/**
> > + * xttcpss_set_interval - Set the timer interval value
> > + *
> > + * @timer: Pointer to the timer instance
> > + * @cycles: Timer interval ticks
> > + **/
> > +static void xttcpss_set_interval(struct xttcpss_timer *timer,
> > + unsigned long cycles)
> > +{
> > + u32 ctrl_reg;
> > +
> > + /* Disable the counter, set the counter value and re-enable
counter */
> > + ctrl_reg = __raw_readl(timer->base_addr +
XTTCPSS_CNT_CNTRL_OFFSET);
> > + ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> > + __raw_writel(ctrl_reg, timer->base_addr +
XTTCPSS_CNT_CNTRL_OFFSET);
> > +
> > + __raw_writel(cycles, timer->base_addr +
XTTCPSS_INTR_VAL_OFFSET);
> > +
> > + /* Reset the counter (0x10) so that it starts from 0, one-shot
> > + mode makes this needed for timing to be right. */
> > + ctrl_reg |= 0x10;
> > + ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> > + __raw_writel(ctrl_reg, timer->base_addr +
XTTCPSS_CNT_CNTRL_OFFSET);
> > +}
> > +
> > +/**
> > + * xttcpss_clock_event_interrupt - Clock event timer interrupt
handler
> > + *
> > + * @irq: IRQ number of the Timer
> > + * @dev_id: void pointer to the xttcpss_timer instance
> > + *
> > + * returns: Always IRQ_HANDLED - success
> > + **/
> > +static irqreturn_t xttcpss_clock_event_interrupt(int irq, void
*dev_id)
> > +{
> > + struct clock_event_device *evt = &xttcpss_clockevent;
> > + struct xttcpss_timer *timer = dev_id;
> > +
> > + /* Acknowledge the interrupt and call event handler */
> > + __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
> > + timer->base_addr + XTTCPSS_ISR_OFFSET);
> > +
> > + evt->event_handler(evt);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static struct irqaction event_timer_irq = {
> > + .name = "xttcpss clockevent",
> > + .flags = IRQF_DISABLED | IRQF_TIMER,
> > + .handler = xttcpss_clock_event_interrupt,
> > +};
> > +
> > +/**
> > + * xttcpss_timer_hardware_init - Initialize the timer hardware
> > + *
> > + * Initialize the hardware to start the clock source, get the clock
> > + * event timer ready to use, and hook up the interrupt.
> > + **/
> > +static void __init xttcpss_timer_hardware_init(void)
> > +{
> > + /* Setup the clock source counter to be an incrementing counter
> > + * with no interrupt and it rolls over at 0xFFFF. Pre-scale
> > + it by 32 also. Let it start running now.
> > + */
> > + timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
> > +
> > + __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
> > + XTTCPSS_IER_OFFSET);
> > + __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
> > + XTTCPSS_CLK_CNTRL_OFFSET);
> > + __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
> > + XTTCPSS_CNT_CNTRL_OFFSET);
> > +
> > + /* Setup the clock event timer to be an interval timer which
> > + * is prescaled by 32 using the interval interrupt. Leave it
> > + * disabled for now.
> > + */
> > +
> > + timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
> > +
> > + __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
> > + XTTCPSS_CNT_CNTRL_OFFSET);
> > + __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
> > + XTTCPSS_CLK_CNTRL_OFFSET);
> > + __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
> > + XTTCPSS_IER_OFFSET);
> > +
> > + /* Setup IRQ the clock event timer */
> > + event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
> > +
> > + if (event_timer_irq.handler != NULL)
> > + setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
>
> You've explicitly initialized event_timer_irq.handler above so I don't
> think you need to check against NULL, and just always call
setup_irq().
Makes sense.
>
> > +}
> > +
> > +/**
> > + * __raw_readl_cycles - Reads the timer counter register
> > + *
> > + * returns: Current timer counter register value
> > + **/
> > +static cycle_t __raw_readl_cycles(struct clocksource *cs)
> > +{
> > + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
> > +
> > + return (cycle_t)__raw_readl(timer->base_addr +
> > + XTTCPSS_COUNT_VAL_OFFSET);
> > +}
> > +
> > +
> > +/*
> > + * Instantiate and initialize the clock source structure
> > + */
> > +static struct clocksource clocksource_xttcpss = {
> > + .name = "xttcpss_timer1",
> > + .rating = 200, /* Reasonable clock
source */
> > + .read = __raw_readl_cycles,
> > + .mask = CLOCKSOURCE_MASK(16),
> > + .shift = 0, /* Initialized to zero
*/
>
> This is static data so you don't need to explicitly initialize shift
to
> 0. It doesn't hurt anything though.
>
Yes, agreed.
> > + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> > +};
> > +
> > +
> > +/**
> > + * xttcpss_set_next_event - Sets the time interval for next event
> > + *
> > + * @cycles: Timer interval ticks
> > + * @evt: Address of clock event instance
> > + *
> > + * returns: Always 0 - success
> > + **/
> > +static int xttcpss_set_next_event(unsigned long cycles,
> > + struct clock_event_device *evt)
> > +{
> > + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
> > +
> > + xttcpss_set_interval(timer, cycles);
> > + return 0;
> > +}
> > +
> > +/**
> > + * xttcpss_set_mode - Sets the mode of timer
> > + *
> > + * @mode: Mode to be set
> > + * @evt: Address of clock event instance
> > + **/
> > +static void xttcpss_set_mode(enum clock_event_mode mode,
> > + struct clock_event_device *evt)
> > +{
> > + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
> > + u32 ctrl_reg;
> > +
> > + timer->mode = mode;
> > +
> > + switch (mode) {
> > + case CLOCK_EVT_MODE_PERIODIC:
> > + xttcpss_set_interval(timer, CLOCK_TICK_RATE / HZ);
> > + break;
> > + case CLOCK_EVT_MODE_ONESHOT:
> > + case CLOCK_EVT_MODE_UNUSED:
> > + case CLOCK_EVT_MODE_SHUTDOWN:
> > + ctrl_reg = __raw_readl(timer->base_addr +
> > + XTTCPSS_CNT_CNTRL_OFFSET);
> > + ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> > + __raw_writel(ctrl_reg,
> > + timer->base_addr +
XTTCPSS_CNT_CNTRL_OFFSET);
> > + break;
> > + case CLOCK_EVT_MODE_RESUME:
> > + ctrl_reg = __raw_readl(timer->base_addr +
> > + XTTCPSS_CNT_CNTRL_OFFSET);
> > + ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
> > + __raw_writel(ctrl_reg,
> > + timer->base_addr +
XTTCPSS_CNT_CNTRL_OFFSET);
> > + break;
> > + }
> > +}
> > +
> > +/*
> > + * Instantiate and initialize the clock event structure
> > + */
> > +static struct clock_event_device xttcpss_clockevent = {
> > + .name = "xttcpss_timer2",
> > + .features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
> > + .shift = 0, /* Initialized to zero */
>
> Same here, that .shift = 0 isn't really needed (but doesn't hurt).
OK.
Thanks,
John
>
> > + .set_next_event = xttcpss_set_next_event,
> > + .set_mode = xttcpss_set_mode,
> > + .rating = 200,
> > +};
> > +
> > +/**
> > + * xttcpss_timer_init - Initialize the timer
> > + *
> > + * Initializes the timer hardware and register the clock source and
clock event
> > + * timers with Linux kernal timer framework
> > + **/
> > +static void __init xttcpss_timer_init(void)
> > +{
> > + xttcpss_timer_hardware_init();
> > + clocksource_register_hz(&clocksource_xttcpss, CLOCK_TICK_RATE);
> > +
> > + /* Calculate the parameters to allow the clockevent to operate
using
> > + integer math
> > + */
> > + clockevents_calc_mult_shift(&xttcpss_clockevent,
CLOCK_TICK_RATE, 4);
> > +
> > + xttcpss_clockevent.max_delta_ns =
> > + clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
> > + xttcpss_clockevent.min_delta_ns =
> > + clockevent_delta2ns(1, &xttcpss_clockevent);
> > +
> > + /* Indicate that clock event can be used on any of the CPUs */
> > +
> > + xttcpss_clockevent.cpumask = cpu_all_mask;
> > + clockevents_register_device(&xttcpss_clockevent);
> > +}
> > +
> > +/*
> > + * Instantiate and initialize the system timer structure
> > + */
> > +struct sys_timer xttcpss_sys_timer = {
> > + .init = xttcpss_timer_init,
> > +};
> > --
> > 1.6.2.1
> >
> >
> >
> > This email and any attachments are intended for the sole use of the
named recipient(s) and
> contain(s) confidential information that may be proprietary,
privileged or copyrighted under
> applicable law. If you are not the intended recipient, do not read,
copy, or forward this email
> message or any attachments. Delete this email message and any
attachments immediately.
> >
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
^ permalink raw reply
* [PATCH V3 1/4] ARM: Xilinx: Adding Xilinx board support
From: John Linn @ 2011-02-17 14:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217093433.GB22961@pulham.picochip.com>
> -----Original Message-----
> From: Jamie Iles [mailto:jamie at jamieiles.com]
> Sent: Thursday, February 17, 2011 2:35 AM
> To: John Linn
> Cc: linux-arm-kernel at lists.infradead.org;
linux-kernel at vger.kernel.org; linux at arm.linux.org.uk;
> catalin.marinas at arm.com; glikely at secretlab.ca; arnd at arndb.de
> Subject: Re: [PATCH V3 1/4] ARM: Xilinx: Adding Xilinx board support
>
> Hi John,
>
> One nitpick, otherwise looks nice.
>
> Jamie
>
> On Wed, Feb 16, 2011 at 09:11:53AM -0700, John Linn wrote:
> > diff --git a/arch/arm/mach-xilinx/common.h
b/arch/arm/mach-xilinx/common.h
> > new file mode 100644
> > index 0000000..9a7cf65
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/common.h
> > @@ -0,0 +1,30 @@
> > +/* arch/arm/mach-xilinx/common.h
> > + *
> > + * This file contains common function prototypes to avoid externs
> > + * in the c files.
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_XILINX_COMMON_H__
> > +#define __MACH_XILINX_COMMON_H__
> > +
> > +#include <linux/init.h>
> > +#include <linux/platform_device.h>
>
> You don't appear to use the contents of platform_device.h in here so
you
> could probably drop this include.
Good point. Easy enough.
Thanks,
John
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
^ permalink raw reply
* [RFC 0/5] runtime P2V translations
From: Russell King - ARM Linux @ 2011-02-17 14:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110104202052.GE24935@n2100.arm.linux.org.uk>
On Tue, Jan 04, 2011 at 08:20:52PM +0000, Russell King - ARM Linux wrote:
> Here's my solution to this, which should allow it to be used on almost
> all platforms, including MSM, with the exception of Realview when
> SPARSEMEM is enabled.
It is my intention to freeze the p2v branch against further changes to
existing commits this evening. That means any further acks/tested-bys
or whatever else will be ignored. Please ensure that you get any acks
etc or further comments to me by this evening, thanks.
^ permalink raw reply
* ep93xx: Failed to open eth0
From: 余谨智 @ 2011-02-17 14:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi, everyone. I am a newbie here. I come from China.
I have a board based on ep9315. I am trying to port embeded linux to that
board.
I used 'make zImage' to generate a zImage, and u-boot command 'dhcp' to
download zImage into board sdram at address 0x1000000, then 'go 0x1000000'.
Thank God! The kernel ran!
But I get this message in my minicom:
Uncompressing Linux... done, booting the kernel.
Linux version 2.6.37 (root at myhost) (gcc version 4.1.2) #4 Wed Feb 16
20:23:04 CST 2011
CPU: ARM920T [41129200] revision 0 (ARMv4T), cr=c0007177
CPU: VIVT data cache, VIVT instruction cache
Machine: Cirrus Logic EDB9315 Evaluation Board
Memory policy: ECC disabled, Data cache writeback
Built 1 zonelists in Zone order, mobility grouping off. Total pages: 4064
Kernel command line: console=ttyAM0,115200 root=/dev/nfs ip=dhcp
PID hash table entries: 64 (order: -4, 256 bytes)
Dentry cache hash table entries: 2048 (order: 1, 8192 bytes)
Inode-cache hash table entries: 1024 (order: 0, 4096 bytes)
Memory: 16MB = 16MB total
Memory: 12584k/12584k available, 3800k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
DMA : 0xffc00000 - 0xffe00000 ( 2 MB)
vmalloc : 0xc1800000 - 0xfe800000 ( 976 MB)
lowmem : 0xc0000000 - 0xc1000000 ( 16 MB)
modules : 0xbf000000 - 0xc0000000 ( 16 MB)
.init : 0xc0008000 - 0xc0023000 ( 108 kB)
.text : 0xc0023000 - 0xc0352090 (3261 kB)
.data : 0xc0354000 - 0xc0374400 ( 129 kB)
NR_IRQS:120
VIC @fefb0000: id 0x00041190, vendor 0x41
VIC @fefc0000: id 0x00041190, vendor 0x41
Calibrating delay loop... 99.73 BogoMIPS (lpj=498688)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
NET: Registered protocol family 16
ep93xx clock: PLL1 running at 199 MHz, PLL2 at 192 MHz
ep93xx clock: FCLK 199 MHz, HCLK 99 MHz, PCLK 49 MHz
ep93xx dma_m2p: M2P DMA subsystem initialized
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 512 (order: 0, 4096 bytes)
TCP bind hash table entries: 512 (order: 1, 10240 bytes)
TCP: Hash tables configured (established 512 bind 512)
TCP reno registered
UDP hash table entries: 128 (order: 0, 6144 bytes)
UDP-Lite hash table entries: 128 (order: 0, 6144 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
NetWinder Floating Point Emulator V0.97 (extended precision)
JFFS2 version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc.
msgmni has been set to 24
io scheduler noop registered
io scheduler deadline registered (default)
Serial: AMBA driver
apb:uart1: ttyAM0 at MMIO 0x808c0000 (irq = 52) is a AMBA
console [ttyAM0] enabled
apb:uart2: ttyAM1 at MMIO 0x808d0000 (irq = 54) is a AMBA
apb:uart3: ttyAM2 at MMIO 0x808e0000 (irq = 55) is a AMBA
nbd: registered device at major 43
physmap platform flash device: 02000000 at 60000000
physmap-flash.0: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID
0x000089 Chip ID 0x000018
Intel/Sharp Extended Query Table at 0x0031
Intel/Sharp Extended Query Table at 0x0031
Using buffer write method
cfi_cmdset_0001: Erase suspend on write enabled
Searching for RedBoot partition table in physmap-flash.0 at offset 0x1fc0000
No RedBoot partition table detected in physmap-flash.0
ep93xx-eth version 0.1 loading
eth0: ep93xx on-chip ethernet, IRQ 39, 01:02:93:12:15:07
rtl8150: v0.6.2 (2004/08/27):rtl8150 based usb-ethernet driver
usbcore: registered new interface driver rtl8150
ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
ep93xx-ohci ep93xx-ohci: EP93xx OHCI
ep93xx-ohci ep93xx-ohci: new USB bus registered, assigned bus number 1
ep93xx-ohci ep93xx-ohci: irq 56, io mem 0x80020000
usb usb1: New USB device found, idVendor=1d6b, idProduct=0001
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: EP93xx OHCI
usb usb1: Manufacturer: Linux 2.6.37 ohci_hcd
usb usb1: SerialNumber: ep93xx
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 3 ports detected
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
usbcore: registered new interface driver usbserial
usbserial: USB Serial Driver core
USB Serial support registered for pl2303
usbcore: registered new interface driver pl2303
pl2303: Prolific PL2303 USB to serial adaptor driver
ep93xx-rtc ep93xx-rtc: rtc core: registered ep93xx-rtc as rtc0
i2c /dev entries driver
ep93xx_wdt: EP93XX watchdog, driver version 0.3
TCP cubic registered
NET: Registered protocol family 10
NET: Registered protocol family 17
NET: Registered protocol family 15
ep93xx-rtc ep93xx-rtc: setting system clock to 1970-01-01 00:57:09 UTC
(3429)
IP-Config: Failed to open eth0
IP-Config: No network devices available.
Root-NFS: no NFS server address
VFS: Unable to mount root fs via NFS, trying floppy.
VFS: Cannot open root device "nfs" or unknown-block(2,0)
Please append a correct "root=" boot option; here are the available
partitions:
1f00 32768 mtdblock0 (driver?)
Kernel panic - not syncing: VFS: Unable to mount root fs on
unknown-block(2,0)
After analyzing, I think the main problem is IP-Config: Failed to open eth0,
so that the kernel can not mount the nfs root.
Is there some problem in the network driver ep93xx-eth or in some code
generate "IP-Config: Failed to open eth"
Any reply will be appreciated!
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^ permalink raw reply
* [RFC 2/5] ARM: P2V: avoid initializers and assembly using PHYS_OFFSET
From: Russell King - ARM Linux @ 2011-02-17 14:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1PaDOv-00023d-Gi@rmk-PC.arm.linux.org.uk>
On Tue, Jan 04, 2011 at 08:22:37PM +0000, Russell King - ARM Linux wrote:
> As PHYS_OFFSET will be becoming a variable, we can't have it used in
> initializers nor assembly code. Replace those in generic code with
> a run-time initialization. Replace those in platform code using the
> individual platform specific PLAT_PHYS_OFFSET.
I'm still missing acks for MSM, PXA and TCC8k stuff for this change.
^ permalink raw reply
* [patch-v2.6.39 6/7] OMAP4430: hwmod data: Adding USBOTG
From: Hema Kalliguddi @ 2011-02-17 14:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D5D25F9.8030907@ti.com>
Benoit,
>-----Original Message-----
>From: Cousson, Benoit [mailto:b-cousson at ti.com]
>Sent: Thursday, February 17, 2011 7:13 PM
>To: Balbi, Felipe
>Cc: Tony Lindgren; Linux OMAP Mailing List; Linux ARM Kernel
>Mailing List; Kalliguddi, Hema; Kevin Hilman; Paul Walmsley
>Subject: Re: [patch-v2.6.39 6/7] OMAP4430: hwmod data: Adding USBOTG
>
>Hi Felipe and Hema,
>
>Sorry for this late review, but I have a couple of comments on
>this one.
:-)....
>
>Since I was planning to send usb hwmod data file to Tony
>directly like I
>did for the other drivers, I can handle the update myself if you want.
>
I was not aware that you are sending the Hwmod patches for OMAP4
for all the drivers. Anyway I am OK with you sending the patch or
required I can also send it.
>
>On 2/17/2011 1:41 PM, Balbi, Felipe wrote:
>> From: Hema HK<hemahk@ti.com>
>
>The authorship is not correct. It should be me.
>
Yes. I agree. It is a mistake.
>[...]
>
>> +static struct omap_hwmod_class_sysconfig
>omap44xx_usb_otg_hs_sysc = {
>> + .rev_offs = 0x0400,
>> + .sysc_offs = 0x0404,
>> + .syss_offs = 0x0408,
>> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
>> + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
>> + SYSC_HAS_AUTOIDLE),
>
>These flags does not contains the latest reset flag
>(SYSS_HAS_RESET_STATUS) introduced in 2.6.37.
OK.
>
>[...]
>
>> +static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
>> + {
>> + .pa_start = OMAP44XX_HSUSB_OTG_BASE,
>> + .pa_end = OMAP44XX_HSUSB_OTG_BASE + SZ_4K - 1,
>
>You should not use the defines anymore, since the only user of the
>physical address should be this file.
Then we shlould be removing these defines right?
>
>[...]
>
>> +static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
>> + { .role = "xclk", .clk = "otg_60m_gfclk_ck" },
>
>That optional clock does not exist anymore, it should be
>"usb_otg_hs_xclk".
>
Since this clock is not enabled for musb as 60Mhz clock is external,
I did not notice this.
In your updated patch below still the optional clock name is not changed.
>[...]
>
>> @@ -2068,6 +2159,8 @@ static __initdata struct omap_hwmod
>*omap44xx_hwmods[] = {
>> &omap44xx_wd_timer2_hwmod,
>> &omap44xx_wd_timer3_hwmod,
>>
>> + /* hsusb otg class */
>> + &omap44xx_usb_otg_hs_hwmod,
>
>"usb_otb_hs" should be before "wd_timer2".
Is this because of the automated scripts which generates the hwmod?
>
>For information, the updated version is below. It is based on rc5 +
>for_2.6.39/omap4_hwmod_data series I've just sent.
Regards,
Hema
>
>Regards,
>Benoit
>
>
>---
> From 5c2017f9405588127bf0b41f718409411d01abf8 Mon Sep 17 00:00:00 2001
>From: Benoit Cousson <b-cousson@ti.com>
>Date: Thu, 17 Feb 2011 12:41:05 +0000
>Subject: [PATCH] OMAP4430: hwmod data: Add USBOTG
>
>OMAP4 hwmod data structures are populated with base address, L3 and L4
>interface clocks, IRQs and sysconfig register details.
>
>As per OMAP USBOTG specification, need to configure the USBOTG
>to smart idle/standby or no idle/standby during data transfer and
>force idle/standby when not in use to support retention and offmode.
>By setting HWMOD_SWSUP_SIDLE and HWMOD_SWSUP_MSTANDBY flags,framework
>will take care of configuring to no idle/standby when module is enabled
>and force idle/standby when idled.
>
>Signed-off-by: Cousson, Benoit <b-cousson@ti.com>
>Signed-off-by: Hema HK <hemahk@ti.com>
>Cc: Tony Lindgren <tony@atomide.com>
>Cc: Kevin Hilman <khilman@deeprootsystems.com>
>Cc: Paul Walmsley <paul@pwsan.com>
>Signed-off-by: Felipe Balbi <balbi@ti.com>
>[b-cousson at ti.com: Fix position, opt_clk, and author]
>---
> arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 95
>++++++++++++++++++++++++++++
> 1 files changed, 95 insertions(+), 0 deletions(-)
>
>diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>index 989bc96..b27e1e3 100644
>--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>@@ -62,6 +62,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod;
> static struct omap_hwmod omap44xx_mmc2_hwmod;
> static struct omap_hwmod omap44xx_mpu_hwmod;
> static struct omap_hwmod omap44xx_mpu_private_hwmod;
>+static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
>
> /*
> * Interconnects omap_hwmod structures
>@@ -344,6 +345,14 @@ static struct omap_hwmod_ocp_if
>omap44xx_l4_cfg__l3_main_2 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
>+/* usb_otg_hs -> l3_main_2 */
>+static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
>+ .master = &omap44xx_usb_otg_hs_hwmod,
>+ .slave = &omap44xx_l3_main_2_hwmod,
>+ .clk = "l3_div_ck",
>+ .user = OCP_USER_MPU | OCP_USER_SDMA,
>+};
>+
> /* l3_main_2 slave ports */
> static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
> &omap44xx_dma_system__l3_main_2,
>@@ -353,6 +362,7 @@ static struct omap_hwmod_ocp_if
>*omap44xx_l3_main_2_slaves[] = {
> &omap44xx_iva__l3_main_2,
> &omap44xx_l3_main_1__l3_main_2,
> &omap44xx_l4_cfg__l3_main_2,
>+ &omap44xx_usb_otg_hs__l3_main_2,
> };
>
> static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
>@@ -4725,6 +4735,88 @@ static struct omap_hwmod
>omap44xx_uart4_hwmod = {
> };
>
> /*
>+ * 'usb_otg_hs' class
>+ * high-speed on-the-go universal serial bus (usb_otg_hs) controller
>+ */
>+
>+static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
>+ .rev_offs = 0x0400,
>+ .sysc_offs = 0x0404,
>+ .syss_offs = 0x0408,
>+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
>+ SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
>+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
>+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
>+ SIDLE_SMART_WKUP | MSTANDBY_FORCE |
>MSTANDBY_NO |
>+ MSTANDBY_SMART),
>+ .sysc_fields = &omap_hwmod_sysc_type1,
>+};
>+
>+static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
>+ .name = "usb_otg_hs",
>+ .sysc = &omap44xx_usb_otg_hs_sysc,
>+};
>+
>+/* usb_otg_hs */
>+static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
>+ { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
>+ { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
>+};
>+
>+/* usb_otg_hs master ports */
>+static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
>+ &omap44xx_usb_otg_hs__l3_main_2,
>+};
>+
>+static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
>+ {
>+ .pa_start = 0x4a0ab000,
>+ .pa_end = 0x4a0ab003,
>+ .flags = ADDR_TYPE_RT
>+ },
>+};
>+
>+/* l4_cfg -> usb_otg_hs */
>+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
>+ .master = &omap44xx_l4_cfg_hwmod,
>+ .slave = &omap44xx_usb_otg_hs_hwmod,
>+ .clk = "l4_div_ck",
>+ .addr = omap44xx_usb_otg_hs_addrs,
>+ .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
>+ .user = OCP_USER_MPU | OCP_USER_SDMA,
>+};
>+
>+/* usb_otg_hs slave ports */
>+static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
>+ &omap44xx_l4_cfg__usb_otg_hs,
>+};
>+
>+static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
>+ { .role = "xclk", .clk = "otg_60m_gfclk_ck" },
>+};
>+
>+static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
>+ .name = "usb_otg_hs",
>+ .class = &omap44xx_usb_otg_hs_hwmod_class,
>+ .mpu_irqs = omap44xx_usb_otg_hs_irqs,
>+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
>+ .main_clk = "usb_otg_hs_ick",
>+ .prcm = {
>+ .omap4 = {
>+ .clkctrl_reg =
>OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
>+ },
>+ },
>+ .opt_clks = usb_otg_hs_opt_clks,
>+ .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
>+ .slaves = omap44xx_usb_otg_hs_slaves,
>+ .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
>+ .masters = omap44xx_usb_otg_hs_masters,
>+ .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
>+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
>+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
>+};
>+
>+/*
> * 'wd_timer' class
> * 32-bit watchdog upward counter that generates a pulse on
>the reset
>pin on
> * overflow condition
>@@ -4995,6 +5087,9 @@ static __initdata struct omap_hwmod
>*omap44xx_hwmods[] = {
> &omap44xx_uart3_hwmod,
> &omap44xx_uart4_hwmod,
>
>+ /* usb_otg_hs class */
>+ &omap44xx_usb_otg_hs_hwmod,
>+
> /* wd_timer class */
> &omap44xx_wd_timer2_hwmod,
> &omap44xx_wd_timer3_hwmod,
>--
>1.7.0.4
>
>
^ permalink raw reply
* [PATCH 5/6] ARM: pm: convert samsung platforms to generic suspend/resume support
From: Russell King - ARM Linux @ 2011-02-17 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <017901cbce9b$7b405ee0$71c11ca0$%kim@samsung.com>
On Thu, Feb 17, 2011 at 09:09:02PM +0900, Kukjin Kim wrote:
> Hi Russell,
>
> I tested on SMDKV210(S5PV210) and SMDKC110(S5PC110).
Thanks for testing. It looks like I'm missing a load for r3 in the
s5pv210 code. The replacement patch below should resolve this.
arch/arm/mach-s3c64xx/sleep.S | 63 +-----------------
arch/arm/mach-s5pv210/sleep.S | 105 +-----------------------------
arch/arm/plat-s3c24xx/sleep.S | 57 +----------------
arch/arm/plat-samsung/include/plat/pm.h | 12 +---
arch/arm/plat-samsung/pm.c | 16 +-----
5 files changed, 14 insertions(+), 239 deletions(-)
diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S
index b2ef443..afe5a76 100644
--- a/arch/arm/mach-s3c64xx/sleep.S
+++ b/arch/arm/mach-s3c64xx/sleep.S
@@ -32,25 +32,13 @@
* code after resume.
*
* entry:
- * r0 = pointer to the save block
+ * r1 = v:p offset
*/
ENTRY(s3c_cpu_save)
stmfd sp!, { r4 - r12, lr }
-
- mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
- mrc p15, 0, r5, c3, c0, 0 @ Domain ID
- mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
- mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
- mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
- mrc p15, 0, r9, c1, c0, 0 @ Control register
- mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
- mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
-
- stmia r0, { r4 - r13 } @ Save CP registers and SP
-
- @@ save our state to ram
- bl s3c_pm_cb_flushcache
+ ldr r3, =resume_with_mmu
+ bl cpu_suspend
@@ call final suspend code
ldr r0, =pm_cpu_sleep
@@ -61,18 +49,6 @@ ENTRY(s3c_cpu_save)
resume_with_mmu:
ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save
- .data
-
- /* the next bit is code, but it requires easy access to the
- * s3c_sleep_save_phys data before the MMU is switched on, so
- * we store the code that needs this variable in the .data where
- * the value can be written to (the .text segment is RO).
- */
-
- .global s3c_sleep_save_phys
-s3c_sleep_save_phys:
- .word 0
-
/* Sleep magic, the word before the resume entry point so that the
* bootloader can check for a resumeable image. */
@@ -110,35 +86,4 @@ ENTRY(s3c_cpu_resume)
orr r0, r0, #1 << 15 @ GPN15
str r0, [ r3, #S3C64XX_GPNDAT ]
#endif
-
- /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches
- * are thoroughly cleaned just in case the bootloader didn't do it
- * for us. */
- mov r0, #0
- mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
- mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
- mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
- mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
- @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
- @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches
-
- ldr r0, s3c_sleep_save_phys
- ldmia r0, { r4 - r13 }
-
- mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
- mcr p15, 0, r5, c3, c0, 0 @ Domain ID
- mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
- mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
- mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
- mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
-
- mov r0, #0 @ restore copro access controls
- mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls
- mcr p15, 0, r0, c7, c5, 4
-
- ldr r2, =resume_with_mmu
- mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */
- nop
- mov pc, r2 /* jump back */
-
- .end
+ b cpu_resume
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
index d4d222b..a3d6494 100644
--- a/arch/arm/mach-s5pv210/sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -35,50 +35,24 @@
/* s3c_cpu_save
*
* entry:
- * r0 = save address (virtual addr of s3c_sleep_save_phys)
+ * r1 = v:p offset
*/
ENTRY(s3c_cpu_save)
stmfd sp!, { r3 - r12, lr }
-
- mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
- mrc p15, 0, r5, c3, c0, 0 @ Domain ID
- mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
- mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
- mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
- mrc p15, 0, r9, c1, c0, 0 @ Control register
- mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
- mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
- mrc p15, 0, r12, c10, c2, 0 @ Read PRRR
- mrc p15, 0, r3, c10, c2, 1 @ READ NMRR
-
- stmia r0, { r3 - r13 }
-
- bl s3c_pm_cb_flushcache
+ ldr r3, =resume_with_mmu
+ bl cpu_suspend
ldr r0, =pm_cpu_sleep
ldr r0, [ r0 ]
mov pc, r0
resume_with_mmu:
- /*
- * After MMU is turned on, restore the previous MMU table.
- */
- ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET)
- add r4, r4, r9
- str r12, [r4]
-
ldmfd sp!, { r3 - r12, pc }
.ltorg
- .data
-
- .global s3c_sleep_save_phys
-s3c_sleep_save_phys:
- .word 0
-
/* sleep magic, to allow the bootloader to check for an valid
* image to resume to. Must be the first word before the
* s3c_cpu_resume entry.
@@ -96,75 +70,4 @@ s3c_sleep_save_phys:
*/
ENTRY(s3c_cpu_resume)
- mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
- msr cpsr_c, r0
-
- mov r1, #0
- mcr p15, 0, r1, c8, c7, 0 @ invalidate TLBs
- mcr p15, 0, r1, c7, c5, 0 @ invalidate I Cache
-
- ldr r0, s3c_sleep_save_phys @ address of restore block
- ldmia r0, { r3 - r13 }
-
- mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
- mcr p15, 0, r5, c3, c0, 0 @ Domain ID
-
- mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
- mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
- mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
-
- mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
-
- mov r0, #0
- mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB
-
- mov r0, #0 @ restore copro access
- mcr p15, 0, r11, c1, c0, 2 @ Co-processor access
- mcr p15, 0, r0, c7, c5, 4
-
- mcr p15, 0, r12, c10, c2, 0 @ write PRRR
- mcr p15, 0, r3, c10, c2, 1 @ write NMRR
-
- /*
- * In Cortex-A8, when MMU is turned on, the pipeline is flushed.
- * And there are no valid entries in the MMU table@this point.
- * So before turning on the MMU, the MMU entry for the DRAM address
- * range is added. After the MMU is turned on, the other entries
- * in the MMU table will be restored.
- */
-
- /* r6 = Translation Table BASE0 */
- mov r4, r6
- mov r4, r4, LSR #14
- mov r4, r4, LSL #14
-
- /* Load address for adding to MMU table list */
- ldr r11, =0xE010F000 @ INFORM0 reg.
- ldr r10, [r11, #0]
- mov r10, r10, LSR #18
- bic r10, r10, #0x3
- orr r4, r4, r10
-
- /* Calculate MMU table entry */
- mov r10, r10, LSL #18
- ldr r5, =0x40E
- orr r10, r10, r5
-
- /* Back up originally data */
- ldr r12, [r4]
-
- /* Add calculated MMU table entry into MMU table list */
- str r10, [r4]
-
- ldr r2, =resume_with_mmu
- mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc
-
- nop
- nop
- nop
- nop
- nop @ second-to-last before mmu
-
- mov pc, r2 @ go back to virtual address
-
- .ltorg
+ b cpu_resume
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index e73e3b6..fd7032f 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -44,23 +44,13 @@
/* s3c_cpu_save
*
* entry:
- * r0 = save address (virtual addr of s3c_sleep_save_phys)
+ * r1 = v:p offset
*/
ENTRY(s3c_cpu_save)
stmfd sp!, { r4 - r12, lr }
-
- @@ store co-processor registers
-
- mrc p15, 0, r4, c13, c0, 0 @ PID
- mrc p15, 0, r5, c3, c0, 0 @ Domain ID
- mrc p15, 0, r6, c2, c0, 0 @ translation table base address
- mrc p15, 0, r7, c1, c0, 0 @ control register
-
- stmia r0, { r4 - r13 }
-
- @@ write our state back to RAM
- bl s3c_pm_cb_flushcache
+ ldr r3, =resume_with_mmu
+ bl cpu_suspend
@@ jump to final code to send system to sleep
ldr r0, =pm_cpu_sleep
@@ -76,20 +66,6 @@ resume_with_mmu:
.ltorg
- @@ the next bits sit in the .data segment, even though they
- @@ happen to be code... the s3c_sleep_save_phys needs to be
- @@ accessed by the resume code before it can restore the MMU.
- @@ This means that the variable has to be close enough for the
- @@ code to read it... since the .text segment needs to be RO,
- @@ the data segment can be the only place to put this code.
-
- .data
-
- .global s3c_sleep_save_phys
-s3c_sleep_save_phys:
- .word 0
-
-
/* sleep magic, to allow the bootloader to check for an valid
* image to resume to. Must be the first word before the
* s3c_cpu_resume entry.
@@ -100,10 +76,6 @@ s3c_sleep_save_phys:
/* s3c_cpu_resume
*
* resume code entry for bootloader to call
- *
- * we must put this code here in the data segment as we have no
- * other way of restoring the stack pointer after sleep, and we
- * must not write to the code segment (code is read-only)
*/
ENTRY(s3c_cpu_resume)
@@ -134,25 +106,4 @@ ENTRY(s3c_cpu_resume)
beq 1001b
#endif /* CONFIG_DEBUG_RESUME */
- mov r1, #0
- mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs
- mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches
-
- ldr r0, s3c_sleep_save_phys @ address of restore block
- ldmia r0, { r4 - r13 }
-
- mcr p15, 0, r4, c13, c0, 0 @ PID
- mcr p15, 0, r5, c3, c0, 0 @ Domain ID
- mcr p15, 0, r6, c2, c0, 0 @ translation table base
-
-#ifdef CONFIG_DEBUG_RESUME
- mov r3, #'R'
- strb r3, [ r2, #S3C2410_UTXH ]
-#endif
-
- ldr r2, =resume_with_mmu
- mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, etc
- nop @ second-to-last before mmu
- mov pc, r2 @ go back to virtual address
-
- .ltorg
+ b cpu_resume
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index d9025e3..4aa697d 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -50,13 +50,11 @@ extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */
/* from sleep.S */
-extern int s3c_cpu_save(unsigned long *saveblk);
+extern int s3c_cpu_save(unsigned long *saveblk, long);
extern void s3c_cpu_resume(void);
extern void s3c2410_cpu_suspend(void);
-extern unsigned long s3c_sleep_save_phys;
-
/* sleep save info */
/**
@@ -179,13 +177,5 @@ extern void s3c_pm_restore_gpios(void);
*/
extern void s3c_pm_save_gpios(void);
-/**
- * s3c_pm_cb_flushcache - callback for assembly code
- *
- * Callback to issue flush_cache_all() as this call is
- * not a directly callable object.
- */
-extern void s3c_pm_cb_flushcache(void);
-
extern void s3c_pm_save_core(void);
extern void s3c_pm_restore_core(void);
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 02d531f..d5b58d3 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -241,8 +241,6 @@ void (*pm_cpu_sleep)(void);
static int s3c_pm_enter(suspend_state_t state)
{
- static unsigned long regs_save[16];
-
/* ensure the debug is initialised (if enabled) */
s3c_pm_debug_init();
@@ -266,12 +264,6 @@ static int s3c_pm_enter(suspend_state_t state)
return -EINVAL;
}
- /* store the physical address of the register recovery block */
-
- s3c_sleep_save_phys = virt_to_phys(regs_save);
-
- S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
-
/* save all necessary core registers not covered by the drivers */
s3c_pm_save_gpios();
@@ -305,7 +297,7 @@ static int s3c_pm_enter(suspend_state_t state)
* we resume as it saves its own register state and restores it
* during the resume. */
- s3c_cpu_save(regs_save);
+ s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET);
/* restore the cpu state using the kernel's cpu init code. */
@@ -336,12 +328,6 @@ static int s3c_pm_enter(suspend_state_t state)
return 0;
}
-/* callback from assembly code */
-void s3c_pm_cb_flushcache(void)
-{
- flush_cache_all();
-}
-
static int s3c_pm_prepare(void)
{
/* prepare check area if configured */
^ permalink raw reply related
* [PATCH 1/2] omap4: 4430sdp: drop ehci support
From: Anand Gadiyar @ 2011-02-17 14:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217114916.GA24989@n2100.arm.linux.org.uk>
Russell King - ARM Linux wrote:
> On Wed, Feb 16, 2011 at 04:47:19PM +0530, Anand Gadiyar wrote:
> > Most revisions of the OMAP4 Blaze/SDP platform do not have
> > the EHCI signals routed by default. The pads are routed
> > for the alternate HSI functionality instead, and explicit
> > board modifications are needed to route the signals to
> > the USB PHY on the board.
> >
> > Also, turning on the PHY connected to the EHCI port causes
> > a board reboot during bootup due to an unintended short
> > on the rails - this affects many initial revisions of the
> > board, and needs a minor board mod to fix (or as a
> > workaround, one should not attempt to power on the
> > USB PHY).
>
> It's probably a good idea to put some comment in the code to that
> effect - people don't generally look at the history when adding new
> features.
I did part of this in patch 2/2.
I've muxed the pad in "safe mode" which turns off the output drivers
for the pad - so it can no longer drive a 1.
I've also placed a big warning above that line explaining why.
> It's probably also a good idea to claim the GPIO for the
> PHY power control and ensure that it's set to 'off' mode - that code
> can then be a placeholder for the comment.
This is a good idea too. Tony, if you concur, I'll go
respin this series.
- Anand
^ permalink raw reply
* [PATCH 2/6] ARM: pm: add generic CPU suspend/resume support
From: Russell King - ARM Linux @ 2011-02-17 13:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297939312.7096.32.camel@e102568-lin.cambridge.arm.com>
On Thu, Feb 17, 2011 at 10:41:52AM +0000, Lorenzo Pieralisi wrote:
> When calling suspend from cpuidle, do you flush the stack (ie CPU
> context) from L2 using outer_cache functions ? This has to be done when
> one CPU is shut down with L2 enabled for the MMU off resume path to work
> properly.
> I think that on resume you invalidate L1 in the reset vector before
> jumping to cpu_resume, correct ?
Let's forget cpuidle using this code for the time being - the issues
there appear to be more complex than the suspend-to-ram which this code
is currently being used for. What I'm saying is that cpuidle using
this is an enhancement over and above its current use.
Once we have the S2R stuff working and tested, then we can go back to
cpuidle stuff.
I fear that trying to get this to work for cpuidle will result in the
entire thing being thrown away.
^ permalink raw reply
* [patch-v2.6.39 6/7] OMAP4430: hwmod data: Adding USBOTG
From: Cousson, Benoit @ 2011-02-17 13:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297946466-9565-7-git-send-email-balbi@ti.com>
Hi Felipe and Hema,
Sorry for this late review, but I have a couple of comments on this one.
Since I was planning to send usb hwmod data file to Tony directly like I
did for the other drivers, I can handle the update myself if you want.
On 2/17/2011 1:41 PM, Balbi, Felipe wrote:
> From: Hema HK<hemahk@ti.com>
The authorship is not correct. It should be me.
[...]
> +static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
> + .rev_offs = 0x0400,
> + .sysc_offs = 0x0404,
> + .syss_offs = 0x0408,
> + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
> + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
> + SYSC_HAS_AUTOIDLE),
These flags does not contains the latest reset flag
(SYSS_HAS_RESET_STATUS) introduced in 2.6.37.
[...]
> +static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
> + {
> + .pa_start = OMAP44XX_HSUSB_OTG_BASE,
> + .pa_end = OMAP44XX_HSUSB_OTG_BASE + SZ_4K - 1,
You should not use the defines anymore, since the only user of the
physical address should be this file.
[...]
> +static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
> + { .role = "xclk", .clk = "otg_60m_gfclk_ck" },
That optional clock does not exist anymore, it should be "usb_otg_hs_xclk".
[...]
> @@ -2068,6 +2159,8 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
> &omap44xx_wd_timer2_hwmod,
> &omap44xx_wd_timer3_hwmod,
>
> + /* hsusb otg class */
> + &omap44xx_usb_otg_hs_hwmod,
"usb_otb_hs" should be before "wd_timer2".
For information, the updated version is below. It is based on rc5 +
for_2.6.39/omap4_hwmod_data series I've just sent.
Regards,
Benoit
---
From 5c2017f9405588127bf0b41f718409411d01abf8 Mon Sep 17 00:00:00 2001
From: Benoit Cousson <b-cousson@ti.com>
Date: Thu, 17 Feb 2011 12:41:05 +0000
Subject: [PATCH] OMAP4430: hwmod data: Add USBOTG
OMAP4 hwmod data structures are populated with base address, L3 and L4
interface clocks, IRQs and sysconfig register details.
As per OMAP USBOTG specification, need to configure the USBOTG
to smart idle/standby or no idle/standby during data transfer and
force idle/standby when not in use to support retention and offmode.
By setting HWMOD_SWSUP_SIDLE and HWMOD_SWSUP_MSTANDBY flags,framework
will take care of configuring to no idle/standby when module is enabled
and force idle/standby when idled.
Signed-off-by: Cousson, Benoit <b-cousson@ti.com>
Signed-off-by: Hema HK <hemahk@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
[b-cousson at ti.com: Fix position, opt_clk, and author]
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 95
++++++++++++++++++++++++++++
1 files changed, 95 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 989bc96..b27e1e3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -62,6 +62,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod;
static struct omap_hwmod omap44xx_mmc2_hwmod;
static struct omap_hwmod omap44xx_mpu_hwmod;
static struct omap_hwmod omap44xx_mpu_private_hwmod;
+static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
/*
* Interconnects omap_hwmod structures
@@ -344,6 +345,14 @@ static struct omap_hwmod_ocp_if
omap44xx_l4_cfg__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* usb_otg_hs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
+ .master = &omap44xx_usb_otg_hs_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l3_main_2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
&omap44xx_dma_system__l3_main_2,
@@ -353,6 +362,7 @@ static struct omap_hwmod_ocp_if
*omap44xx_l3_main_2_slaves[] = {
&omap44xx_iva__l3_main_2,
&omap44xx_l3_main_1__l3_main_2,
&omap44xx_l4_cfg__l3_main_2,
+ &omap44xx_usb_otg_hs__l3_main_2,
};
static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
@@ -4725,6 +4735,88 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
};
/*
+ * 'usb_otg_hs' class
+ * high-speed on-the-go universal serial bus (usb_otg_hs) controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
+ .rev_offs = 0x0400,
+ .sysc_offs = 0x0404,
+ .syss_offs = 0x0408,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
+ .name = "usb_otg_hs",
+ .sysc = &omap44xx_usb_otg_hs_sysc,
+};
+
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
+ { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
+ { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
+};
+
+/* usb_otg_hs master ports */
+static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
+ &omap44xx_usb_otg_hs__l3_main_2,
+};
+
+static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
+ {
+ .pa_start = 0x4a0ab000,
+ .pa_end = 0x4a0ab003,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_cfg -> usb_otg_hs */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_usb_otg_hs_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_usb_otg_hs_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* usb_otg_hs slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
+ &omap44xx_l4_cfg__usb_otg_hs,
+};
+
+static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
+ { .role = "xclk", .clk = "otg_60m_gfclk_ck" },
+};
+
+static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
+ .name = "usb_otg_hs",
+ .class = &omap44xx_usb_otg_hs_hwmod_class,
+ .mpu_irqs = omap44xx_usb_otg_hs_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
+ .main_clk = "usb_otg_hs_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+ },
+ },
+ .opt_clks = usb_otg_hs_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
+ .slaves = omap44xx_usb_otg_hs_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
+ .masters = omap44xx_usb_otg_hs_masters,
+ .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset
pin on
* overflow condition
@@ -4995,6 +5087,9 @@ static __initdata struct omap_hwmod
*omap44xx_hwmods[] = {
&omap44xx_uart3_hwmod,
&omap44xx_uart4_hwmod,
+ /* usb_otg_hs class */
+ &omap44xx_usb_otg_hs_hwmod,
+
/* wd_timer class */
&omap44xx_wd_timer2_hwmod,
&omap44xx_wd_timer3_hwmod,
--
1.7.0.4
^ permalink raw reply related
* [PATCH 16/17] mc13xxx: mfd_cell is now implicitly available to drivers
From: Uwe Kleine-König @ 2011-02-17 13:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTimhXR=AWT6wV-MXhtW7dvs6OYW7OqaV5RPhFP5V@mail.gmail.com>
On Thu, Feb 17, 2011 at 09:53:56AM -0200, Fabio Estevam wrote:
> Hi Uwe,
>
> 2011/2/16 Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>:
> > On Wed, Feb 16, 2011 at 10:31:10AM -0200, Fabio Estevam wrote:
> >> Hi Uwe,
> >>
> >> On 2/16/2011 7:41 AM, Uwe Kleine-K?nig wrote:
> >> ...
> >> >> ?/* MC13783 */
> >> >> -static struct mc13783_platform_data mc13783_pdata __initdata = {
> >> > isn't using __initdata here broken already before your patch? ?Was
> >> > introduced in c67a3e09. ?Fabio?
> >>
> >> I followed the same approach as in mx31_3ds.c file.
> >>
> >> > But in general I'd prefer to keep as much __initdata as possible because
> >> > this occupies less memory when using a multi-machine kernel.
> >>
> >> Ok, is the __initdata usage correct then? If not, I can change it. Just let me know.
> > I guess that if you compile mc13xxx support as module it won't work.
> >
> > Try that, and if it breaks, send a patch fixing mx31_3ds.c, too.
>
> I built it as module and the build went fine.
And you did a runtime test, too?
If you did and that went smooth, I'll take a look again, because I
expected it to barf.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH v5 5/5] ARM: omap3: Thumb-2 compatibility for sleep34xx.S
From: Dave Martin @ 2011-02-17 12:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297946558-13436-1-git-send-email-dave.martin@linaro.org>
* Build unconditionally as ARM for correct interoperation with
OMAP firmware.
* Fix an out-of-range ADR when building for ARM.
* Remove deprecated PC-relative stores.
* Add the required ENDPROC() directive for each ENTRY().
* .align before data words.
* Handle non-interworking return from v7_flush_dcache_all.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
arch/arm/mach-omap2/sleep34xx.S | 48 ++++++++++++++++++++++++++++++++++----
1 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index a05c348..f377724 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -64,6 +64,11 @@
#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
+/*
+ * This file needs be built unconditionally as ARM to interoperate correctly
+ * with non-Thumb-2-capable firmware.
+ */
+ .arm
/*
* API functions
@@ -82,6 +87,8 @@ ENTRY(get_restore_pointer)
stmfd sp!, {lr} @ save registers on stack
adr r0, restore
ldmfd sp!, {pc} @ restore regs and return
+ENDPROC(get_restore_pointer)
+ .align
ENTRY(get_restore_pointer_sz)
.word . - get_restore_pointer
@@ -91,6 +98,8 @@ ENTRY(get_omap3630_restore_pointer)
stmfd sp!, {lr} @ save registers on stack
adr r0, restore_3630
ldmfd sp!, {pc} @ restore regs and return
+ENDPROC(get_omap3630_restore_pointer)
+ .align
ENTRY(get_omap3630_restore_pointer_sz)
.word . - get_omap3630_restore_pointer
@@ -100,6 +109,8 @@ ENTRY(get_es3_restore_pointer)
stmfd sp!, {lr} @ save registers on stack
adr r0, restore_es3
ldmfd sp!, {pc} @ restore regs and return
+ENDPROC(get_es3_restore_pointer)
+ .align
ENTRY(get_es3_restore_pointer_sz)
.word . - get_es3_restore_pointer
@@ -113,8 +124,10 @@ ENTRY(enable_omap3630_toggle_l2_on_restore)
stmfd sp!, {lr} @ save registers on stack
/* Setup so that we will disable and enable l2 */
mov r1, #0x1
- str r1, l2dis_3630
+ adrl r2, l2dis_3630 @ may be too distant for plain adr
+ str r1, [r2]
ldmfd sp!, {pc} @ restore regs and return
+ENDPROC(enable_omap3630_toggle_l2_on_restore)
.text
/* Function to call rom code to save secure ram context */
@@ -139,12 +152,14 @@ ENTRY(save_secure_ram_context)
nop
nop
ldmfd sp!, {r1-r12, pc}
+ .align
sram_phy_addr_mask:
.word SRAM_BASE_P
high_mask:
.word 0xffff
api_params:
.word 0x4, 0x0, 0x0, 0x1, 0x1
+ENDPROC(save_secure_ram_context)
ENTRY(save_secure_ram_context_sz)
.word . - save_secure_ram_context
@@ -279,8 +294,18 @@ clean_l2:
* - 'might' have to copy address, load and jump to it
*/
ldr r1, kernel_flush
- mov lr, pc
- bx r1
+ blx r1
+ /*
+ * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
+ * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
+ * This sequence switches back to ARM. Note that .align may insert a
+ * nop: bx pc needs to be word-aligned in order to work.
+ */
+ THUMB( .thumb )
+ THUMB( .align )
+ THUMB( bx pc )
+ THUMB( nop )
+ .arm
omap3_do_wfi:
ldr r4, sdrc_power @ read the SDRC_POWER register
@@ -438,6 +463,7 @@ skipl2dis:
#endif
b logic_l1_restore
+ .align
l2_inv_api_params:
.word 0x1, 0x00
l2_inv_gp:
@@ -607,6 +633,7 @@ usettbr0:
/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
.text
+ .align 3
ENTRY(es3_sdrc_fix)
ldr r4, sdrc_syscfg @ get config addr
ldr r5, [r4] @ get value
@@ -634,6 +661,7 @@ ENTRY(es3_sdrc_fix)
str r5, [r4] @ kick off refreshes
bx lr
+ .align
sdrc_syscfg:
.word SDRC_SYSCONFIG_P
sdrc_mr_0:
@@ -648,6 +676,7 @@ sdrc_emr2_1:
.word SDRC_EMR2_1_P
sdrc_manual_1:
.word SDRC_MANUAL_1_P
+ENDPROC(es3_sdrc_fix)
ENTRY(es3_sdrc_fix_sz)
.word . - es3_sdrc_fix
@@ -682,6 +711,12 @@ wait_sdrc_ready:
bic r5, r5, #0x40
str r5, [r4]
+/*
+ * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a
+ * base instead.
+ * Be careful not to clobber r7 when maintaing this code.
+ */
+
is_dll_in_lock_mode:
/* Is dll in lock mode? */
ldr r4, sdrc_dlla_ctrl
@@ -689,10 +724,11 @@ is_dll_in_lock_mode:
tst r5, #0x4
bxne lr @ Return if locked
/* wait till dll locks */
+ adr r7, kick_counter
wait_dll_lock_timed:
ldr r4, wait_dll_lock_counter
add r4, r4, #1
- str r4, wait_dll_lock_counter
+ str r4, [r7, #wait_dll_lock_counter - kick_counter]
ldr r4, sdrc_dlla_status
/* Wait 20uS for lock */
mov r6, #8
@@ -718,9 +754,10 @@ kick_dll:
dsb
ldr r4, kick_counter
add r4, r4, #1
- str r4, kick_counter
+ str r4, [r7] @ kick_counter
b wait_dll_lock_timed
+ .align
cm_idlest1_core:
.word CM_IDLEST1_CORE_V
cm_idlest_ckgen:
@@ -763,6 +800,7 @@ kick_counter:
.word 0
wait_dll_lock_counter:
.word 0
+ENDPROC(omap34xx_cpu_suspend)
ENTRY(omap34xx_cpu_suspend_sz)
.word . - omap34xx_cpu_suspend
--
1.7.1
^ permalink raw reply related
* [PATCH v5 4/5] ARM: omap3: Thumb-2 compatibility for sram34xx.S
From: Dave Martin @ 2011-02-17 12:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297946558-13436-1-git-send-email-dave.martin@linaro.org>
* Build unconditionally as ARM for correct interoperation with
OMAP firmware.
* Remove deprecated PC-relative stores
* Add the required ENDPROC() directive for each ENTRY().
* .align before data words
Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
arch/arm/mach-omap2/sram34xx.S | 36 ++++++++++++++++++++++++++++--------
1 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 7f893a2..fd1531c 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -34,6 +34,12 @@
#include "sdrc.h"
#include "cm2xxx_3xxx.h"
+/*
+ * This file needs be built unconditionally as ARM to interoperate correctly
+ * with non-Thumb-2-capable firmware.
+ */
+ .arm
+
.text
/* r1 parameters */
@@ -116,24 +122,36 @@ ENTRY(omap3_sram_configure_core_dpll)
@ pull the extra args off the stack
@ and store them in SRAM
+
+/*
+ * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
+ * in Thumb-2: use a r7 as a base instead.
+ * Be careful not to clobber r7 when maintaing this file.
+ */
+ THUMB( adr r7, omap3_sram_configure_core_dpll )
+ .macro strtext Rt:req, label:req
+ ARM( str \Rt, \label )
+ THUMB( str \Rt, [r7, \label - omap3_sram_configure_core_dpll] )
+ .endm
+
ldr r4, [sp, #52]
- str r4, omap_sdrc_rfr_ctrl_0_val
+ strtext r4, omap_sdrc_rfr_ctrl_0_val
ldr r4, [sp, #56]
- str r4, omap_sdrc_actim_ctrl_a_0_val
+ strtext r4, omap_sdrc_actim_ctrl_a_0_val
ldr r4, [sp, #60]
- str r4, omap_sdrc_actim_ctrl_b_0_val
+ strtext r4, omap_sdrc_actim_ctrl_b_0_val
ldr r4, [sp, #64]
- str r4, omap_sdrc_mr_0_val
+ strtext r4, omap_sdrc_mr_0_val
ldr r4, [sp, #68]
- str r4, omap_sdrc_rfr_ctrl_1_val
+ strtext r4, omap_sdrc_rfr_ctrl_1_val
cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
beq skip_cs1_params @ do not use cs1 params
ldr r4, [sp, #72]
- str r4, omap_sdrc_actim_ctrl_a_1_val
+ strtext r4, omap_sdrc_actim_ctrl_a_1_val
ldr r4, [sp, #76]
- str r4, omap_sdrc_actim_ctrl_b_1_val
+ strtext r4, omap_sdrc_actim_ctrl_b_1_val
ldr r4, [sp, #80]
- str r4, omap_sdrc_mr_1_val
+ strtext r4, omap_sdrc_mr_1_val
skip_cs1_params:
mrc p15, 0, r8, c1, c0, 0 @ read ctrl register
bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction
@@ -271,6 +289,7 @@ skip_cs1_prog:
ldr r12, [r11] @ posted-write barrier for SDRC
bx lr
+ .align
omap3_sdrc_power:
.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
omap3_cm_clksel1_pll:
@@ -319,6 +338,7 @@ omap3_sdrc_dlla_ctrl:
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
core_m2_mask_val:
.word 0x07FFFFFF
+ENDPROC(omap3_sram_configure_core_dpll)
ENTRY(omap3_sram_configure_core_dpll_sz)
.word . - omap3_sram_configure_core_dpll
--
1.7.1
^ permalink raw reply related
* [PATCH v5 3/5] ARM: omap3: Remove hand-encoded SMC instructions
From: Dave Martin @ 2011-02-17 12:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297946558-13436-1-git-send-email-dave.martin@linaro.org>
For various reasons, Linux now only officially supports being built
with tools which are new enough to understand the SMC instruction.
Replacing the hand-encoded instructions when the mnemonic also
allows for correct assembly in Thumb-2 (otherwise, the result is
random data in the middle of the code).
The Makefile already ensures that this file is built with a high
enough gcc -march= flag (armv7-a).
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/sleep34xx.S | 14 +++++++-------
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 98d8232..a05c348 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -133,7 +133,7 @@ ENTRY(save_secure_ram_context)
mov r6, #0xff
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
- .word 0xE1600071 @ call SMI monitor (smi #1)
+ smc #1 @ call SMI monitor (smi #1)
nop
nop
nop
@@ -408,7 +408,7 @@ skipl2dis:
adr r3, l2_inv_api_params @ r3 points to dummy parameters
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
- .word 0xE1600071 @ call SMI monitor (smi #1)
+ smc #1 @ call SMI monitor (smi #1)
/* Write to Aux control register to set some bits */
mov r0, #42 @ set service ID for PPA
mov r12, r0 @ copy secure Service ID in r12
@@ -419,7 +419,7 @@ skipl2dis:
ldr r3, [r4, #0xBC] @ r3 points to parameters
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
- .word 0xE1600071 @ call SMI monitor (smi #1)
+ smc #1 @ call SMI monitor (smi #1)
#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
/* Restore L2 aux control register */
@@ -434,7 +434,7 @@ skipl2dis:
adds r3, r3, #8 @ r3 points to parameters
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
- .word 0xE1600071 @ call SMI monitor (smi #1)
+ smc #1 @ call SMI monitor (smi #1)
#endif
b logic_l1_restore
@@ -443,18 +443,18 @@ l2_inv_api_params:
l2_inv_gp:
/* Execute smi to invalidate L2 cache */
mov r12, #0x1 @ set up to invalidate L2
- .word 0xE1600070 @ Call SMI monitor (smieq)
+ smc #0 @ Call SMI monitor (smieq)
/* Write to Aux control register to set some bits */
ldr r4, scratchpad_base
ldr r3, [r4,#0xBC]
ldr r0, [r3,#4]
mov r12, #0x3
- .word 0xE1600070 @ Call SMI monitor (smieq)
+ smc #0 @ Call SMI monitor (smieq)
ldr r4, scratchpad_base
ldr r3, [r4,#0xBC]
ldr r0, [r3,#12]
mov r12, #0x2
- .word 0xE1600070 @ Call SMI monitor (smieq)
+ smc #0 @ Call SMI monitor (smieq)
logic_l1_restore:
ldr r1, l2dis_3630
cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
--
1.7.1
^ permalink raw reply related
* [PATCH v5 2/5] ARM: omap4: Convert END() to ENDPROC() for correct linkage with CONFIG_THUMB2_KERNEL
From: Dave Martin @ 2011-02-17 12:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297946558-13436-1-git-send-email-dave.martin@linaro.org>
Code marked with ENTRY() also needs a matching ENDPROC() directive,
in order to ensure that the type and instruction set of the
symbol are correctly annotated.
ENDPROC() tags the affected symbol as a function symbol, which will
ensure that link-time fixups don't accidentally switch to the
wrong instruction set.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/omap-headsmp.S | 2 +-
arch/arm/mach-omap2/omap44xx-smc.S | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 6ae937a..4ee6aec 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -45,5 +45,5 @@ hold: ldr r12,=0x103
* should now contain the SVC stack for this core
*/
b secondary_startup
-END(omap_secondary_startup)
+ENDPROC(omap_secondary_startup)
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
index 1980dc3..e69d37d 100644
--- a/arch/arm/mach-omap2/omap44xx-smc.S
+++ b/arch/arm/mach-omap2/omap44xx-smc.S
@@ -29,7 +29,7 @@ ENTRY(omap_smc1)
dsb
smc #0
ldmfd sp!, {r2-r12, pc}
-END(omap_smc1)
+ENDPROC(omap_smc1)
ENTRY(omap_modify_auxcoreboot0)
stmfd sp!, {r1-r12, lr}
@@ -37,7 +37,7 @@ ENTRY(omap_modify_auxcoreboot0)
dsb
smc #0
ldmfd sp!, {r1-r12, pc}
-END(omap_modify_auxcoreboot0)
+ENDPROC(omap_modify_auxcoreboot0)
ENTRY(omap_auxcoreboot_addr)
stmfd sp!, {r2-r12, lr}
@@ -45,7 +45,7 @@ ENTRY(omap_auxcoreboot_addr)
dsb
smc #0
ldmfd sp!, {r2-r12, pc}
-END(omap_auxcoreboot_addr)
+ENDPROC(omap_auxcoreboot_addr)
ENTRY(omap_read_auxcoreboot0)
stmfd sp!, {r2-r12, lr}
@@ -54,4 +54,4 @@ ENTRY(omap_read_auxcoreboot0)
smc #0
mov r0, r0, lsr #9
ldmfd sp!, {r2-r12, pc}
-END(omap_read_auxcoreboot0)
+ENDPROC(omap_read_auxcoreboot0)
--
1.7.1
^ permalink raw reply related
* [PATCH v5 1/5] ARM: omap4: Provide do_wfi() for Thumb-2
From: Dave Martin @ 2011-02-17 12:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297946558-13436-1-git-send-email-dave.martin@linaro.org>
For CONFIG_THUMB2_KERNEL, the existing definition of do_wfi() will
insert invalid code into the instruction stream.
Any assembler which can assemble Thumb-2 is guaranteed to accept
the "wfi" mnemonic, so for the Thumb-2 case, just use the mnemonic.
The ARM case is left as-is.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
arch/arm/mach-omap2/include/mach/omap4-common.h | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index 5b0270b..de441c0 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -17,8 +17,12 @@
* wfi used in low power code. Directly opcode is used instead
* of instruction to avoid mulit-omap build break
*/
+#ifdef CONFIG_THUMB2_KERNEL
+#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
+#else
#define do_wfi() \
__asm__ __volatile__ (".word 0xe320f003" : : : "memory")
+#endif
#ifdef CONFIG_CACHE_L2X0
extern void __iomem *l2cache_base;
--
1.7.1
^ permalink raw reply related
* [PATCH v5 0/5] ARM: omap[34]: Thumb-2 compatibility fixes
From: Dave Martin @ 2011-02-17 12:42 UTC (permalink / raw)
To: linux-arm-kernel
This set of patches, along with some other patches under
discussion on alkml, should enable omap3 and omap4 kernels to be
built with CONFIG_THUMB2_KERNEL.
This patch set builds on recent cleanup done by the omap
maintainers.
At least some of this code definitely works, most features have
been tested successfully. Further testing, especially of Thumb-2
behaviour, is still welcome.
Seems to work with CONFIG_SMP_ON_UP and CONFIG_THUMB2_KERNEL
enabled on Beagle xM A2 and Panda A1.
Thanks also to Santosh Shilimkar and Kevin Hilman for their help
with testing.
v3:
* make SMC instruction syntax more consistent
* remove do_wfi() in favour of the generic wfi() macro
v4:
* revert to the OMAP-specific do_wfi() implementation, pending
discussion of how generic macros can/should be provided
v5:
* use ARM for low-level code in mach-omap2/*34xx.S, for
correct interoperation with non-Thumb-capable firmware.
I've stripped the Acked/Tested-bys from the major patches to
mach-omap2/*34xx.S, since the reversion to ARM constitutes a
significant change -- I would be grateful if people could re-
test / re-review if they have the chance.
For best future compatibility, I've left the changes which
avoid architecturally deprecated features.
Details below.
Cheers,
Dave
The patches can be found, along with a buildable working tree,
in the following repo:
git://git.linaro.org/people/dmart/linux-2.6-arm.git
* arm/omap-thumb2: has the patches proposed here
* arm/omap-thumb2+merged: additionally has some patches cherry-
picked from other trees which are needed in order for the
patches on arm/omap-thumb2 to work usefully.
* dirty/arm/omap-thumb2+merged: buildable test tree, which adds
2 local patches to work around a toolchain bug.
A working kernel config for this tree is here:
http://people.linaro.org/~dmart/arm_omap-thumb2+v2_config :
CONFIG_SMP_ON_UP=y
CONFIG_THUMB2_KERNEL=y
CONFIG_SERIAL_OMAP=y (to avoid garbage on xM; for Panda use console=ttyS2)
(The config is derived from the linaro omap config and so turns on
loads of modules -- don't feel you have to build them all...)
Cherry-picked patches originated from Russell's devel tree
and Tony Lindgren's omap-testing tree:
http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm.git devel
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git omap-testing
This series also depends on one un-merged patch to generic-ise
the wfi() macro:
git://git.linaro.org/people/dmart/linux-2.6-arm.git arm/wfi-macro
Dave Martin (5):
ARM: omap4: Provide do_wfi() for Thumb-2
ARM: omap4: Convert END() to ENDPROC() for correct linkage with
CONFIG_THUMB2_KERNEL
ARM: omap3: Remove hand-encoded SMC instructions
ARM: omap3: Thumb-2 compatibility for sram34xx.S
ARM: omap3: Thumb-2 compatibility for sleep34xx.S
arch/arm/mach-omap2/include/mach/omap4-common.h | 4 ++
arch/arm/mach-omap2/omap-headsmp.S | 2 +-
arch/arm/mach-omap2/omap44xx-smc.S | 8 ++--
arch/arm/mach-omap2/sleep34xx.S | 62 ++++++++++++++++++----
arch/arm/mach-omap2/sram34xx.S | 36 ++++++++++---
5 files changed, 87 insertions(+), 25 deletions(-)
^ permalink raw reply
* [patch-v2.6.39 7/7] OMAP2+: musb: hwmod adaptation for musb registration
From: Felipe Balbi @ 2011-02-17 12:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297946466-9565-1-git-send-email-balbi@ti.com>
From: Hema HK <hemahk@ti.com>
Using omap_device_build API instead of platform_device_register for
OMAP2430,OMAP3xxx, OMAP4430 and AM35x musb device registration.
The device specific resources defined in centralized
database will be used.
Signed-off-by: Hema HK <hemahk@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Cousson, Benoit <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
---
arch/arm/mach-omap2/usb-musb.c | 84 +++++++++++++++++++++-------------------
1 files changed, 44 insertions(+), 40 deletions(-)
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 5a82b43..b089ea4 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -30,6 +30,7 @@
#include <mach/irqs.h>
#include <mach/am35xx.h>
#include <plat/usb.h>
+#include <plat/omap_device.h>
#include "control.h"
#include "mux.h"
@@ -127,22 +128,6 @@ static void am35x_musb_set_mode(u8 musb_mode)
omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
}
-static struct resource musb_resources[] = {
- [0] = { /* start and end set dynamically */
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = INT_243X_HS_USB_MC,
- .flags = IORESOURCE_IRQ,
- .name = "mc",
- },
- [2] = { /* DMA IRQ */
- .start = INT_243X_HS_USB_DMA,
- .flags = IORESOURCE_IRQ,
- .name = "dma",
- },
-};
-
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
.dyn_fifo = 1,
@@ -170,16 +155,12 @@ static struct musb_hdrc_platform_data musb_plat = {
static u64 musb_dmamask = DMA_BIT_MASK(32);
-static struct platform_device musb_device = {
- .name = "musb-omap2430",
- .id = -1,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &musb_plat,
+static struct omap_device_pm_latency omap_musb_latency[] = {
+ {
+ .deactivate_func = omap_device_idle_hwmods,
+ .activate_func = omap_device_enable_hwmods,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
},
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
};
static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
@@ -219,28 +200,24 @@ static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
break;
}
}
+
void __init usb_musb_init(struct omap_musb_board_data *board_data)
{
- if (cpu_is_omap243x()) {
- musb_resources[0].start = OMAP243X_HS_BASE;
- } else if (cpu_is_omap3517() || cpu_is_omap3505()) {
- musb_device.name = "musb-am35x";
- musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE;
- musb_resources[1].start = INT_35XX_USBOTG_IRQ;
+ struct omap_hwmod *oh;
+ struct omap_device *od;
+ struct platform_device *pdev;
+ struct device *dev;
+ int bus_id = -1;
+ const char *oh_name, *name;
+
+ if (cpu_is_omap3517() || cpu_is_omap3505()) {
board_data->set_phy_power = am35x_musb_phy_power;
board_data->clear_irq = am35x_musb_clear_irq;
board_data->set_mode = am35x_musb_set_mode;
board_data->reset = am35x_musb_reset;
- } else if (cpu_is_omap34xx()) {
- musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
} else if (cpu_is_omap44xx()) {
- musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE;
- musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N;
- musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N;
-
usb_musb_mux_init(board_data);
}
- musb_resources[0].end = musb_resources[0].start + SZ_4K - 1;
/*
* REVISIT: This line can be removed once all the platforms using
@@ -252,8 +229,35 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
musb_plat.mode = board_data->mode;
musb_plat.extvbus = board_data->extvbus;
- if (platform_device_register(&musb_device) < 0)
- printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
+ if (cpu_is_omap3517() || cpu_is_omap3505()) {
+ oh_name = "am35x_otg_hs";
+ name = "musb-am35x";
+ } else {
+ oh_name = "usb_otg_hs";
+ name = "musb-omap2430";
+ }
+
+ oh = omap_hwmod_lookup(oh_name);
+ if (!oh) {
+ pr_err("Could not look up %s\n", oh_name);
+ return;
+ }
+
+ od = omap_device_build(name, bus_id, oh, &musb_plat,
+ sizeof(musb_plat), omap_musb_latency,
+ ARRAY_SIZE(omap_musb_latency), false);
+ if (IS_ERR(od)) {
+ pr_err("Could not build omap_device for %s %s\n",
+ name, oh_name);
+ return;
+ }
+
+ pdev = &od->pdev;
+ dev = &pdev->dev;
+ get_device(dev);
+ dev->dma_mask = &musb_dmamask;
+ dev->coherent_dma_mask = musb_dmamask;
+ put_device(dev);
}
#else
--
1.7.4.rc2
^ permalink raw reply related
* [patch-v2.6.39 6/7] OMAP4430: hwmod data: Adding USBOTG
From: Felipe Balbi @ 2011-02-17 12:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297946466-9565-1-git-send-email-balbi@ti.com>
From: Hema HK <hemahk@ti.com>
OMAP4 hwmod data structures are populated with base address, L3 and L4
interface clocks, IRQs and sysconfig register details.
As per OMAP USBOTG specification, need to configure the USBOTG
to smart idle/standby or no idle/standby during data transfer and
force idle/standby when not in use to support retention and offmode.
By setting HWMOD_SWSUP_SIDLE and HWMOD_SWSUP_MSTANDBY flags,framework
will take care of configuring to no idle/standby when module is enabled
and force idle/standby when idled.
Signed-off-by: Cousson, Benoit <b-cousson@ti.com>
Signed-off-by: Hema HK <hemahk@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Cousson, Benoit <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 93 ++++++++++++++++++++++++++++
1 files changed, 93 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c2806bd..a78e6d7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -55,6 +55,7 @@ static struct omap_hwmod omap44xx_l4_per_hwmod;
static struct omap_hwmod omap44xx_l4_wkup_hwmod;
static struct omap_hwmod omap44xx_mpu_hwmod;
static struct omap_hwmod omap44xx_mpu_private_hwmod;
+static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
/*
* Interconnects omap_hwmod structures
@@ -286,12 +287,21 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* usb_otg_hs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
+ .master = &omap44xx_usb_otg_hs_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l3_main_2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
&omap44xx_dma_system__l3_main_2,
&omap44xx_iva__l3_main_2,
&omap44xx_l3_main_1__l3_main_2,
&omap44xx_l4_cfg__l3_main_2,
+ &omap44xx_usb_otg_hs__l3_main_2,
};
static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
@@ -2001,6 +2011,87 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+/*
+ * 'usb_otg_hs' class
+ * high-speed on-the-go universal serial bus (usb_otg_hs) controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
+ .rev_offs = 0x0400,
+ .sysc_offs = 0x0404,
+ .syss_offs = 0x0408,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
+ .name = "usb_otg_hs",
+ .sysc = &omap44xx_usb_otg_hs_sysc,
+};
+
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
+ { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
+ { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
+};
+
+/* usb_otg_hs master ports */
+static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
+ &omap44xx_usb_otg_hs__l3_main_2,
+};
+
+static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
+ {
+ .pa_start = OMAP44XX_HSUSB_OTG_BASE,
+ .pa_end = OMAP44XX_HSUSB_OTG_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_cfg -> usb_otg_hs */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_usb_otg_hs_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_usb_otg_hs_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* usb_otg_hs slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
+ &omap44xx_l4_cfg__usb_otg_hs,
+};
+
+static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
+ { .role = "xclk", .clk = "otg_60m_gfclk_ck" },
+};
+
+static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
+ .name = "usb_otg_hs",
+ .class = &omap44xx_usb_otg_hs_hwmod_class,
+ .mpu_irqs = omap44xx_usb_otg_hs_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
+ .main_clk = "usb_otg_hs_ick",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+ },
+ },
+ .opt_clks = usb_otg_hs_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
+ .slaves = omap44xx_usb_otg_hs_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
+ .masters = omap44xx_usb_otg_hs_masters,
+ .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* dmm class */
@@ -2068,6 +2159,8 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
&omap44xx_wd_timer2_hwmod,
&omap44xx_wd_timer3_hwmod,
+ /* hsusb otg class */
+ &omap44xx_usb_otg_hs_hwmod,
NULL,
};
--
1.7.4.rc2
^ permalink raw reply related
* [patch-v2.6.39 5/7] AM35xx: hwmod data: Add USBOTG
From: Felipe Balbi @ 2011-02-17 12:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297946466-9565-1-git-send-email-balbi@ti.com>
From: Hema HK <hemahk@ti.com>
AM35xx hwmod data structures are populated for USBOTG with base address,
L3 and L4 interface clocks and IRQ.
Signed-off-by: Hema HK <hemahk@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Cousson, Benoit <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 65 ++++++++++++++++++++++++++++
1 files changed, 65 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index cce09fd..b4cd8dd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -28,6 +28,7 @@
#include "prm-regbits-34xx.h"
#include "cm-regbits-34xx.h"
#include "wd_timer.h"
+#include <mach/am35xx.h>
/*
* OMAP3xxx hardware module integration data
@@ -55,6 +56,8 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod;
static struct omap_hwmod omap3xxx_gpio6_hwmod;
static struct omap_hwmod omap34xx_sr1_hwmod;
static struct omap_hwmod omap34xx_sr2_hwmod;
+static struct omap_hwmod am35xx_usbhsotg_hwmod;
+
static struct omap_hwmod omap3xxx_dma_system_hwmod;
@@ -117,6 +120,13 @@ static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
.user = OCP_USER_MPU,
};
+/* l3_core -> am35xx_usbhsotg interface */
+static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
+ .master = &am35xx_usbhsotg_hwmod,
+ .slave = &omap3xxx_l3_main_hwmod,
+ .clk = "core_l3_ick",
+ .user = OCP_USER_MPU,
+};
/* L4_CORE -> L4_WKUP interface */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
.master = &omap3xxx_l4_core_hwmod,
@@ -340,6 +350,31 @@ static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
&omap3xxx_l4_core__usbhsotg,
};
+static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
+ {
+ .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
+ .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_core -> usbhsotg */
+static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &am35xx_usbhsotg_hwmod,
+ .clk = "l4_ick",
+ .addr = am35xx_usbhsotg_addrs,
+ .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
+ &am35xx_usbhsotg__l3,
+};
+
+static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
+ &am35xx_l4_core__usbhsotg,
+};
/* Slave interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
&omap3xxx_l3_main__l4_core,
@@ -1452,6 +1487,33 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
| HWMOD_SWSUP_MSTANDBY,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
+/* usb_otg_hs */
+static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
+
+ { .name = "mc", .irq = 71 },
+};
+
+static struct omap_hwmod_class am35xx_usbotg_class = {
+ .name = "am35xx_usbotg",
+ .sysc = NULL,
+};
+
+static struct omap_hwmod am35xx_usbhsotg_hwmod = {
+ .name = "am35x_otg_hs",
+ .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
+ .main_clk = NULL,
+ .prcm = {
+ .omap2 = {
+ },
+ },
+ .masters = am35xx_usbhsotg_masters,
+ .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
+ .slaves = am35xx_usbhsotg_slaves,
+ .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
+ .class = &am35xx_usbotg_class,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
+};
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_l3_main_hwmod,
@@ -1488,6 +1550,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
/* usbotg class */
&omap3xxx_usbhsotg_hwmod,
+ /* usbotg for am35x */
+ &am35xx_usbhsotg_hwmod,
+
NULL,
};
--
1.7.4.rc2
^ permalink raw reply related
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