* [PATCH] msm: add single-wire serial bus interface (SSBI) driver
From: Daniel Walker @ 2011-02-18 0:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297989299-27320-1-git-send-email-kheitke@codeaurora.org>
On Thu, 2011-02-17 at 17:34 -0700, Kenneth Heitke wrote:
> SSBI is the Qualcomm single-wire serial bus interface used to connect
> the MSM devices to the PMIC and other devices.
>
> Since SSBI only supports a single slave, the driver gets the name of the
> slave device passed in from the board file through the master device's
> platform data.
>
> SSBI registers pretty early (postcore), so that the PMIC can come up
> before the board init. This is useful if the board init requires the
> use of gpios that are connected through the PMIC.
>
> Based on a patch by Dima Zavin <dima@android.com> that can be found at:
> http://android.git.kernel.org/?p=kernel/msm.git;a=commitdiff;h=eb060bac4
>
> This patch adds PMIC Arbiter support for the MSM8660. The PMIC Arbiter
> is a hardware wrapper around the SSBI 2.0 controller that is designed to
> overcome concurrency issues and security limitations. A controller_type
> field is added to the platform data to specify the type of the SSBI
> controller (1.0, 2.0, or PMIC Arbiter).
>
> Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
> ---
> arch/arm/mach-msm/Kconfig | 16 ++
> arch/arm/mach-msm/Makefile | 1 +
> arch/arm/mach-msm/include/mach/msm_ssbi.h | 38 +++
> arch/arm/mach-msm/ssbi.c | 376 +++++++++++++++++++++++++++++
> 4 files changed, 431 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/mach-msm/include/mach/msm_ssbi.h
> create mode 100644 arch/arm/mach-msm/ssbi.c
>
> diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
> index 997c5bd..f35c3d9 100644
> --- a/arch/arm/mach-msm/Kconfig
> +++ b/arch/arm/mach-msm/Kconfig
> @@ -24,6 +24,7 @@ config ARCH_MSM7X30
> select MSM_GPIOMUX
> select MSM_PROC_COMM
> select HAS_MSM_DEBUG_UART_PHYS
> + select HAS_MSM_SSBI
>
> config ARCH_QSD8X50
> bool "QSD8X50"
> @@ -46,6 +47,7 @@ config ARCH_MSM8X60
> select MSM_V2_TLMM
> select MSM_GPIOMUX
> select MSM_SCM if SMP
> + select HAS_MSM_SSBI
>
> config ARCH_MSM8960
> bool "MSM8960"
> @@ -56,6 +58,7 @@ config ARCH_MSM8960
> select MSM_V2_TLMM
> select MSM_GPIOMUX
> select MSM_SCM if SMP
> + select HAS_MSM_SSBI
>
> endchoice
>
> @@ -190,6 +193,16 @@ choice
> endchoice
> endif
>
> +config MSM_SSBI
> + bool "Qualcomm Single-wire Serial Bus Interface (SSBI)"
> + depends on HAS_MSM_SSBI
> + help
> + If you say yes to this option, support will be included for the
> + built-in SSBI interface on Qualcomm MSM family processors.
> +
> + This is required for communicating with Qualcomm PMICs and
> + other devices that have the SSBI interface.
> +
Can you put this in drivers/ this doesn't looks like it need to be here.
Daniel
--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros
From: John Linn @ 2011-02-18 0:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217100126.GD22961@pulham.picochip.com>
> -----Original Message-----
> From: Jamie Iles [mailto:jamie at jamieiles.com]
> Sent: Thursday, February 17, 2011 3:01 AM
> To: John Linn
> Cc: linux-arm-kernel at lists.infradead.org;
linux-kernel at vger.kernel.org; linux at arm.linux.org.uk;
> catalin.marinas at arm.com; glikely at secretlab.ca; arnd at arndb.de
> Subject: Re: [PATCH V3 3/4] ARM: Xilinx: base header files and
assembly macros
>
> Hi John,
>
> A few more nitpicks, but looking good now!
>
> Jamie
>
> On Wed, Feb 16, 2011 at 09:11:55AM -0700, John Linn wrote:
> > These are the minimum needed to build the kernel for the new
platform.
> >
> > Signed-off-by: John Linn <john.linn@xilinx.com>
> > ---
> >
> > V3 Changes
> >
> > Updates based on Russell Kings' comments
> > Changed headers to update the license info and remove
> > the address
> >
> > Updated the constant to use UL in vmalloc.h
> >
> > V2 Changes
> >
> > Updates based on Russell King's comments
> > moved to using entry-macro-gic.S
> > moved stuff from hardware.h to xilinx_soc.h
> > added IOMEM() in io.h to help with typing
> > Minor updates to IO_SPACE_LIMIT and __io()
> > Updated addresses to be clear with seperate virtual
> > and physical addresses
> >
> > arch/arm/mach-xilinx/include/mach/clkdev.h | 33
++++++++++++++++
> > arch/arm/mach-xilinx/include/mach/debug-macro.S | 36
+++++++++++++++++
> > arch/arm/mach-xilinx/include/mach/entry-macro.S | 30
++++++++++++++
> > arch/arm/mach-xilinx/include/mach/hardware.h | 18 +++++++++
> > arch/arm/mach-xilinx/include/mach/io.h | 33
++++++++++++++++
> > arch/arm/mach-xilinx/include/mach/irqs.h | 29
++++++++++++++
> > arch/arm/mach-xilinx/include/mach/memory.h | 23 +++++++++++
> > arch/arm/mach-xilinx/include/mach/system.h | 28
+++++++++++++
> > arch/arm/mach-xilinx/include/mach/timex.h | 24 ++++++++++++
> > arch/arm/mach-xilinx/include/mach/uart.h | 31
+++++++++++++++
> > arch/arm/mach-xilinx/include/mach/uncompress.h | 47
+++++++++++++++++++++++
> > arch/arm/mach-xilinx/include/mach/vmalloc.h | 20 ++++++++++
> > arch/arm/mach-xilinx/include/mach/xilinx_soc.h | 46
++++++++++++++++++++++
> > 13 files changed, 398 insertions(+), 0 deletions(-)
> > create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S
> > create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S
> > create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/io.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/system.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> >
> > diff --git a/arch/arm/mach-xilinx/include/mach/clkdev.h
b/arch/arm/mach-xilinx/include/mach/clkdev.h
> > new file mode 100644
> > index 0000000..5dd1453
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/clkdev.h
> > @@ -0,0 +1,33 @@
> > +/*
> > + * arch/arm/mach-xilinx/include/mach/clkdev.h
> > + *
> > + * Copyright (C) 2011 Xilinx, Inc.
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + */
> > +
> > +#ifndef __MACH_CLKDEV_H__
> > +#define __MACH_CLKDEV_H__
> > +
> > +struct clk {
> > + unsigned long rate;
> > +};
> > +
> > +static inline int __clk_get(struct clk *clk)
> > +{
> > + return 1;
> > +}
> > +
> > +static inline void __clk_put(struct clk *clk)
> > +{
> > +}
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/debug-macro.S
b/arch/arm/mach-
> xilinx/include/mach/debug-macro.S
> > new file mode 100644
> > index 0000000..30d3d3d
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/debug-macro.S
> > @@ -0,0 +1,36 @@
> > +/* arch/arm/mach-xilinx/include/mach/debug-macro.S
> > + *
> > + * Debugging macro include header
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <mach/xilinx_soc.h>
> > +#include <mach/uart.h>
> > +
> > + .macro addruart, rp, rv
> > + ldr \rp, =LL_UART_PADDR @ physical
> > + ldr \rv, =LL_UART_VADDR @ virtual
> > + .endm
> > +
> > + .macro senduart,rd,rx
> > + str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
> > + .endm
> > +
> > + .macro waituart,rd,rx
> > + .endm
> > +
> > + .macro busyuart,rd,rx
> > +1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get
status register
> > + tst \rd, #UART_SR_TXFULL @
> > + bne 1002b @ wait if FIFO is full
> > + .endm
> > diff --git a/arch/arm/mach-xilinx/include/mach/entry-macro.S
b/arch/arm/mach-
> xilinx/include/mach/entry-macro.S
> > new file mode 100644
> > index 0000000..11a2866
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/entry-macro.S
> > @@ -0,0 +1,30 @@
> > +/*
> > + * arch/arm/mach-xilinx/include/mach/entry-macro.S
> > + *
> > + * Low-level IRQ helper macros
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * based on arch/plat-mxc/include/mach/entry-macro.S
> > + *
> > + * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
> > + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights
Reserved.
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <mach/hardware.h>
> > +#include <asm/hardware/entry-macro-gic.S>
> > +
> > + .macro disable_fiq
> > + .endm
> > +
> > + .macro arch_ret_to_user, tmp1, tmp2
> > + .endm
> > diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h
b/arch/arm/mach-
> xilinx/include/mach/hardware.h
> > new file mode 100644
> > index 0000000..f9685c4
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/hardware.h
> > @@ -0,0 +1,18 @@
> > +/* arch/arm/mach-xilinx/include/mach/hardware.h
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_HARDWARE_H__
> > +#define __MACH_HARDWARE_H__
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/io.h
b/arch/arm/mach-xilinx/include/mach/io.h
> > new file mode 100644
> > index 0000000..ef69e65
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/io.h
> > @@ -0,0 +1,33 @@
> > +/* arch/arm/mach-xilinx/include/mach/io.h
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_IO_H__
> > +#define __MACH_IO_H__
> > +
> > +/* Allow IO space to be anywhere in the memory */
> > +
> > +#define IO_SPACE_LIMIT 0xffff
> > +
> > +/* IO address mapping macros, nothing special at this time but
required */
> > +
> > +#ifdef __ASSEMBLER__
> > +#define IOMEM(x) (x)
> > +#else
> > +#define IOMEM(x) ((void __force __iomem *)(x))
> > +#endif
> > +
> > +#define __io(a) __typesafe_io(a)
> > +#define __mem_pci(a) (a)
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/irqs.h
b/arch/arm/mach-xilinx/include/mach/irqs.h
> > new file mode 100644
> > index 0000000..47a8162
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/irqs.h
> > @@ -0,0 +1,29 @@
> > +/* arch/arm/mach-xilinx/include/mach/irqs.h
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_IRQS_H
> > +#define __MACH_IRQS_H
> > +
> > +#define ARCH_NR_GPIOS 118
> > +#define NR_IRQS (128 + ARCH_NR_GPIOS)
> > +
> > +/*
> > + * GIC Interrupts
> > + */
> > +
> > +#define IRQ_GIC_SPI_START 32
> > +#define IRQ_TIMERCOUNTER0 42
> > +#define IRQ_UART0 59
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/memory.h
b/arch/arm/mach-xilinx/include/mach/memory.h
> > new file mode 100644
> > index 0000000..c200486
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/memory.h
> > @@ -0,0 +1,23 @@
> > +/* arch/arm/mach-xilinx/include/mach/memory.h
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_MEMORY_H__
> > +#define __MACH_MEMORY_H__
> > +
> > +#include <mach/hardware.h>
> > +
> > +#define PHYS_OFFSET 0x0
>
> This should be PLAT_PHYS_OFFSET and could do with being surrounded
with
> UL() e.g.
>
> #define PLAT_PHYS_OFFSET UL(0x00000000)
>
> > +#define MEM_SIZE SZ_256M
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/system.h
b/arch/arm/mach-xilinx/include/mach/system.h
> > new file mode 100644
> > index 0000000..e8514a0
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/system.h
> > @@ -0,0 +1,28 @@
> > +/* arch/arm/mach-xilinx/include/mach/system.h
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_SYSTEM_H__
> > +#define __MACH_SYSTEM_H__
> > +
> > +static inline void arch_idle(void)
> > +{
> > + cpu_do_idle();
> > +}
> > +
> > +static inline void arch_reset(char mode, const char *cmd)
> > +{
> > + /* Add architecture specific reset processing here */
>
> I think you can add cpu_reset(0) in here to try a soft reset by
jumping
> to the reset vector. This should give you some reset functionality.
Hi Jamie,
How strongly do you feel that this has to be in on this initial patch
set?
There will be many more coming later and I'd like to postpone that one
as it's really additional
functionality vs a bug (to me anyway).
Thanks,
John
>
> > +}
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/timex.h
b/arch/arm/mach-xilinx/include/mach/timex.h
> > new file mode 100644
> > index 0000000..6765e15
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/timex.h
> > @@ -0,0 +1,24 @@
> > +/* arch/arm/mach-xilinx/include/mach/timex.h
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_TIMEX_H__
> > +#define __MACH_TIMEX_H__
> > +
> > +#include <mach/hardware.h>
>
> I don't think you need mach/hardware.h included in here.
>
> > +
> > +#define PERIPHERAL_CLOCK_RATE 2500000
> > +
> > +#define CLOCK_TICK_RATE (PERIPHERAL_CLOCK_RATE / 32)
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/uart.h
b/arch/arm/mach-xilinx/include/mach/uart.h
> > new file mode 100644
> > index 0000000..20a10d7
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/uart.h
> > @@ -0,0 +1,31 @@
> > +/* arch/arm/mach-xilinx/include/mach/uart.h
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_UART_H__
> > +#define __MACH_UART_H__
> > +
> > +#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
> > +#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
> > +#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
> > +
> > +#define UART_SR_TXFULL 0x00000010 /* TX FIFO full
*/
> > +#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty
*/
> > +
> > +#define UART_FIFO_WRITE(base, value) \
> > + (*(volatile unsigned int *)((base) + UART_FIFO_OFFSET) =
(value))
> > +
> > +#define UART_STATUS(base) \
> > + (*(volatile unsigned int *)((base) + UART_SR_OFFSET))
>
> You could probably make these static inline functions in the header
and
> use __raw_{readl,writel}() to make this a little cleaner.
>
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h
b/arch/arm/mach-
> xilinx/include/mach/uncompress.h
> > new file mode 100644
> > index 0000000..b7a5110
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/uncompress.h
> > @@ -0,0 +1,47 @@
> > +/* arch/arm/mach-xilinx/include/mach/uncompress.h
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_UNCOMPRESS_H__
> > +#define __MACH_UNCOMPRESS_H__
> > +
> > +#include <mach/xilinx_soc.h>
> > +#include <mach/uart.h>
> > +
> > +void arch_decomp_setup(void)
> > +{
> > +}
> > +
> > +static inline void flush(void)
> > +{
> > + /*
> > + * Wait while the FIFO is not empty
> > + */
> > + while (!(UART_STATUS(LL_UART_PADDR) & UART_SR_TXEMPTY))
> > + ;
> > +}
> > +
> > +#define arch_decomp_wdog()
> > +
> > +static void putc(char ch)
> > +{
> > + /*
> > + * Wait for room in the FIFO, then write the char into the FIFO
> > + */
> > + while (UART_STATUS(LL_UART_PADDR) & UART_SR_TXFULL)
> > + ;
>
> It might be worth adding a barrier() call to these loops to be
explicit
> about the volatility.
>
> > +
> > + UART_FIFO_WRITE(LL_UART_PADDR, ch);
> > +}
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/vmalloc.h
b/arch/arm/mach-
> xilinx/include/mach/vmalloc.h
> > new file mode 100644
> > index 0000000..aba20a3
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/vmalloc.h
> > @@ -0,0 +1,20 @@
> > +/* arch/arm/mach-xilinx/include/mach/vmalloc.h
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_VMALLOC_H__
> > +#define __MACH_VMALLOC_H__
> > +
> > +#define VMALLOC_END 0xE0000000UL
> > +
> > +#endif
> > diff --git a/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
b/arch/arm/mach-
> xilinx/include/mach/xilinx_soc.h
> > new file mode 100644
> > index 0000000..d01cde1
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> > @@ -0,0 +1,46 @@
> > +/* arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_XILINX_SOC_H__
> > +#define __MACH_XILINX_SOC_H__
> > +
> > +/* For now, all mappings are flat (physical = virtual)
> > + */
> > +#define UART0_PHYS 0xE0000000
> > +#define UART0_VIRT UART0_PHYS
> > +
> > +#define TTC0_PHYS 0xF8001000
> > +#define TTC0_VIRT TTC0_PHYS
> > +
> > +#define PL310_L2CC_PHYS 0xF8F02000
> > +#define PL310_L2CC_VIRT PL310_L2CC_PHYS
> > +
> > +#define SCU_PERIPH_PHYS 0xF8F00000
> > +#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS
> > +
> > +/* The following are intended for the devices that are mapped early
*/
> > +
> > +#define TTC0_BASE IOMEM(TTC0_VIRT)
> > +#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
> > +#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100)
> > +#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000)
> > +#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT)
> > +
> > +/*
> > + * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
> > + */
> > +#define LL_UART_PADDR UART0_PHYS
> > +#define LL_UART_VADDR UART0_VIRT
> > +
> > +#endif
> > --
> > 1.6.2.1
> >
> >
> >
> > This email and any attachments are intended for the sole use of the
named recipient(s) and
> contain(s) confidential information that may be proprietary,
privileged or copyrighted under
> applicable law. If you are not the intended recipient, do not read,
copy, or forward this email
> message or any attachments. Delete this email message and any
attachments immediately.
> >
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe
linux-kernel" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
> > Please read the FAQ at http://www.tux.org/lkml/
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
^ permalink raw reply
* [PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros
From: Jamie Iles @ 2011-02-18 0:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cb015a68-c46f-400b-97ba-e1bf32e8dc2c@VA3EHSMHS019.ehs.local>
On Thu, Feb 17, 2011 at 05:37:47PM -0700, John Linn wrote:
> > > +static inline void arch_reset(char mode, const char *cmd)
> > > +{
> > > + /* Add architecture specific reset processing here */
> >
> > I think you can add cpu_reset(0) in here to try a soft reset by
> jumping
> > to the reset vector. This should give you some reset functionality.
>
> Hi Jamie,
>
> How strongly do you feel that this has to be in on this initial patch
> set?
>
> There will be many more coming later and I'd like to postpone that one
> as it's really additional
> functionality vs a bug (to me anyway).
I don't have a strong opinion on it. If you leave it as it is so that
arch_reset() will return then the generic ARM code will issue a printk
to tell the user that it failed then drop into an infinite loop so it
should be obvious that reset isn't implemented!
If reset is nontrivial then you're probably right to leave it out of
this patch and put it into another later on.
Jamie
^ permalink raw reply
* [PATCH] msm: add single-wire serial bus interface (SSBI) driver
From: Bryan Huntsman @ 2011-02-18 0:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297989432.9680.50.camel@c-dwalke-linux.qualcomm.com>
On 02/17/2011 04:37 PM, Daniel Walker wrote:
> Can you put this in drivers/ this doesn't looks like it need to be here.
Where would you suggest? The initial attempt to model SSBI as an I2C
bus didn't go anywhere. See http://lkml.org/lkml/2010/7/21/400. This
functionality is specific to MSM. Plus, we're trying to maintain
similarity to the Android MSM tree. That may not matter to people who
don't use MSM, but is matters to us. Given these considerations, the
current location seems as good a place as any.
- Bryan
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [RFC PATCH 2/3] ARM: gic: Use cpu pm notifiers to save gic state
From: Colin Cross @ 2011-02-18 0:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297373487-23902-3-git-send-email-ccross@android.com>
On Thu, Feb 10, 2011 at 1:31 PM, Colin Cross <ccross@android.com> wrote:
<snip>
> +#ifdef CONFIG_PM
> + ? ? ? u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
> + ? ? ? u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
> + ? ? ? u32 saved_spi_pri[DIV_ROUND_UP(1020, 4)];
> + ? ? ? u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
> + ? ? ? u32 __percpu *saved_ppi_enable;
> + ? ? ? u32 __percpu *saved_ppi_conf;
> + ? ? ? u32 __percpu *saved_ppi_pri;
> +#endif
The #ifdef CONFIG_PM breaks building !CONFIG_PM, and this should
depend on CONFIG_CPU_IDLE, not CONFIG_PM.
> +static void gic_cpu_save(unsigned int gic_nr)
> +{
> + ? ? ? int i;
> + ? ? ? u32 *ptr;
> + ? ? ? void __iomem *dist_base;
> + ? ? ? void __iomem *cpu_base;
> +
> + ? ? ? if (gic_nr >= MAX_GIC_NR)
> + ? ? ? ? ? ? ? BUG();
> +
> + ? ? ? dist_base = gic_data[gic_nr].dist_base;
> + ? ? ? cpu_base = gic_data[gic_nr].cpu_base;
> +
> + ? ? ? if (!dist_base || !cpu_base)
> + ? ? ? ? ? ? ? return;
> +
> + ? ? ? ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
> + ? ? ? for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
> + ? ? ? ? ? ? ? ptr[i] = readl(dist_base + GIC_DIST_ENABLE_SET + i * 4);
> +
> + ? ? ? ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
> + ? ? ? for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
> + ? ? ? ? ? ? ? ptr[i] = readl(dist_base + GIC_DIST_CONFIG + i * 4);
> +
> + ? ? ? ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_pri);
> + ? ? ? for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
> + ? ? ? ? ? ? ? ptr[i] = readl(dist_base + GIC_DIST_PRI + i * 4);
> +
> + ? ? ? writel(0, cpu_base + GIC_CPU_CTRL);
> +}
Disabling the GIC cpu interface here prevents SGIs from waking the CPU
from WFI. On Tegra2, it is useful to be able to go to WFI, and then
either back to normal or into reset depending on the state of the
other CPU. Is it safe to leave the GIC CPU control on when going to
reset?
^ permalink raw reply
* MMC quirks relating to performance/lifetime.
From: Andrei Warkentin @ 2011-02-18 1:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTinaY2RM86tX4ex+zsMwFKUdBNVpdZ8fFrt-e12_@mail.gmail.com>
On Fri, Feb 11, 2011 at 4:33 PM, Andrei Warkentin <andreiw@motorola.com> wrote:
> Arnd,
>
> Yes, this is a Toshiba card. I've sent the patch as a reply to Linus' email.
>
> cid - 02010053454d3332479070cc51451d00
> csd - d00f00320f5903ffffffffff92404000
> erase_size - 524288
> fwrev - 0x0
> hwrev - 0x0
> manfid - 0x000002
> name - SEM32G
> oemid - 0x0100
> preferred_erase_size - 2097152
>
Ok. Big mistake. Sorry about that. This card is Sandisk card. I got
confused over all the manfids changing.
Here is the Toshiba card:
cid - 1101004d4d4333324703101a17746d00
csd - 900e00320f5903ffffffffe796400000
erase_size - 524288
fwrev - 0x0
hwrev - 0x0
manfid - 0x000011
name - MMC32G
oemid - 0x0100
preferred_erase_size - 4194304
I'll get you the flashbench timings for both.
^ permalink raw reply
* [PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros
From: John Linn @ 2011-02-18 1:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217100126.GD22961@pulham.picochip.com>
> -----Original Message-----
> From: Jamie Iles [mailto:jamie at jamieiles.com]
> Sent: Thursday, February 17, 2011 3:01 AM
> To: John Linn
> Cc: linux-arm-kernel at lists.infradead.org;
linux-kernel at vger.kernel.org; linux at arm.linux.org.uk;
> catalin.marinas at arm.com; glikely at secretlab.ca; arnd at arndb.de
> Subject: Re: [PATCH V3 3/4] ARM: Xilinx: base header files and
assembly macros
>
> Hi John,
>
> A few more nitpicks, but looking good now!
>
> Jamie
>
> On Wed, Feb 16, 2011 at 09:11:55AM -0700, John Linn wrote:
> > These are the minimum needed to build the kernel for the new
platform.
> >
> > Signed-off-by: John Linn <john.linn@xilinx.com>
> > ---
> >
> > V3 Changes
> >
> > Updates based on Russell Kings' comments
> > Changed headers to update the license info and remove
> > the address
> >
> > Updated the constant to use UL in vmalloc.h
> >
> > V2 Changes
> >
> > Updates based on Russell King's comments
> > moved to using entry-macro-gic.S
> > moved stuff from hardware.h to xilinx_soc.h
> > added IOMEM() in io.h to help with typing
> > Minor updates to IO_SPACE_LIMIT and __io()
> > Updated addresses to be clear with seperate virtual
> > and physical addresses
> >
> > arch/arm/mach-xilinx/include/mach/clkdev.h | 33
++++++++++++++++
> > arch/arm/mach-xilinx/include/mach/debug-macro.S | 36
+++++++++++++++++
> > arch/arm/mach-xilinx/include/mach/entry-macro.S | 30
++++++++++++++
> > arch/arm/mach-xilinx/include/mach/hardware.h | 18 +++++++++
> > arch/arm/mach-xilinx/include/mach/io.h | 33
++++++++++++++++
> > arch/arm/mach-xilinx/include/mach/irqs.h | 29
++++++++++++++
> > arch/arm/mach-xilinx/include/mach/memory.h | 23 +++++++++++
> > arch/arm/mach-xilinx/include/mach/system.h | 28
+++++++++++++
> > arch/arm/mach-xilinx/include/mach/timex.h | 24 ++++++++++++
> > arch/arm/mach-xilinx/include/mach/uart.h | 31
+++++++++++++++
> > arch/arm/mach-xilinx/include/mach/uncompress.h | 47
+++++++++++++++++++++++
> > arch/arm/mach-xilinx/include/mach/vmalloc.h | 20 ++++++++++
> > arch/arm/mach-xilinx/include/mach/xilinx_soc.h | 46
++++++++++++++++++++++
> > 13 files changed, 398 insertions(+), 0 deletions(-)
> > create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S
> > create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S
> > create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/io.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/system.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h
> > create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h
> >
<snip>
> > diff --git a/arch/arm/mach-xilinx/include/mach/memory.h
b/arch/arm/mach-xilinx/include/mach/memory.h
> > new file mode 100644
> > index 0000000..c200486
> > --- /dev/null
> > +++ b/arch/arm/mach-xilinx/include/mach/memory.h
> > @@ -0,0 +1,23 @@
> > +/* arch/arm/mach-xilinx/include/mach/memory.h
> > + *
> > + * Copyright (C) 2011 Xilinx
> > + *
> > + * This software is licensed under the terms of the GNU General
Public
> > + * License version 2, as published by the Free Software Foundation,
and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __MACH_MEMORY_H__
> > +#define __MACH_MEMORY_H__
> > +
> > +#include <mach/hardware.h>
> > +
> > +#define PHYS_OFFSET 0x0
>
> This should be PLAT_PHYS_OFFSET and could do with being surrounded
with
> UL() e.g.
>
> #define PLAT_PHYS_OFFSET UL(0x00000000)
This doesn't build with 2.6.38-rc5, am I missing something?
PHYS_OFFSET is still needed from what I can tell, but maybe I overlooked
something.
Thanks,
John
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
^ permalink raw reply
* [PATCH] ARM: fold lookup_machine_type() into setup_machine()
From: Nicolas Pitre @ 2011-02-18 1:26 UTC (permalink / raw)
To: linux-arm-kernel
Since commit 6fc31d54 there is no callers for lookup_machine_type()
other than setup_machine(). And if the former fails it won't return,
therefore the error path in the later is dead code. Let's clean
things up by merging them together.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
---
This is meant for the p2v-stable branch.
arch/arm/kernel/setup.c | 48 ++++++++++++++++------------------------------
1 files changed, 17 insertions(+), 31 deletions(-)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 773b5cd..f43f041 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -325,28 +325,6 @@ static void __init early_print(const char *str, ...)
printk("%s", buf);
}
-static struct machine_desc * __init lookup_machine_type(unsigned int type)
-{
- extern struct machine_desc __arch_info_begin[], __arch_info_end[];
- struct machine_desc *p;
-
- for (p = __arch_info_begin; p < __arch_info_end; p++)
- if (type == p->nr)
- return p;
-
- early_print("\n"
- "Error: unrecognized/unsupported machine ID (r1 = 0x%08x).\n\n"
- "Available machine support:\n\nID (hex)\tNAME\n", type);
-
- for (p = __arch_info_begin; p < __arch_info_end; p++)
- early_print("%08x\t%s\n", p->nr, p->name);
-
- early_print("\nPlease check your kernel config and/or bootloader.\n");
-
- while (true)
- /* can't use cpu_relax() here as it may require MMU setup */;
-}
-
static void __init feat_v6_fixup(void)
{
int id = read_cpuid_id();
@@ -463,21 +441,29 @@ void cpu_init(void)
static struct machine_desc * __init setup_machine(unsigned int nr)
{
- struct machine_desc *list;
+ extern struct machine_desc __arch_info_begin[], __arch_info_end[];
+ struct machine_desc *p;
/*
* locate machine in the list of supported machines.
*/
- list = lookup_machine_type(nr);
- if (!list) {
- printk("Machine configuration botched (nr %d), unable "
- "to continue.\n", nr);
- while (1);
- }
+ for (p = __arch_info_begin; p < __arch_info_end; p++)
+ if (nr == p->nr) {
+ printk("Machine: %s\n", p->name);
+ return p;
+ }
- printk("Machine: %s\n", list->name);
+ early_print("\n"
+ "Error: unrecognized/unsupported machine ID (r1 = 0x%08x).\n\n"
+ "Available machine support:\n\nID (hex)\tNAME\n", nr);
+
+ for (p = __arch_info_begin; p < __arch_info_end; p++)
+ early_print("%08x\t%s\n", p->nr, p->name);
- return list;
+ early_print("\nPlease check your kernel config and/or bootloader.\n");
+
+ while (true)
+ /* can't use cpu_relax() here as it may require MMU setup */;
}
static int __init arm_add_memory(unsigned long start, unsigned long size)
^ permalink raw reply related
* [PATCH 0/11] ARM: EXYNOS4: Change ARCH name, ARCH_EXYNOS4 from ARCH_S5PV310
From: Kukjin Kim @ 2011-02-18 1:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297671787-10571-1-git-send-email-kgene.kim@samsung.com>
Kukjin Kim wrote:
>
> This patch set changes to ARCH_EXYNOS4 from ARCH_S5PV310 for supporting
> Samsung's
> new brand name EXYNOS. Samsung officially announced about the brand name
of
> EXYNOS
> at MWC 2011 and The EXYNOS4 integrates a ARM Cortex A9 microporcessor with
> several
> other peripherals to support features such as multimedai, storage,
graphics
> and gaming.
> Especially, the EXYNOS4210 CPU which is one of EXYNOS4 SoC series can be
used
> in
> products such as Mobile devices.
>
Hi all,
If there are no more comments for this, will merge this into for-next this
weekend.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros
From: John Linn @ 2011-02-18 1:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D5D9A00.7060609@codeaurora.org>
> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd at codeaurora.org]
> Sent: Thursday, February 17, 2011 2:58 PM
> To: Jamie Iles
> Cc: John Linn; linux at arm.linux.org.uk; arnd at arndb.de;
catalin.marinas at arm.com; linux-
> kernel at vger.kernel.org; glikely at secretlab.ca;
linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH V3 3/4] ARM: Xilinx: base header files and
assembly macros
>
> On 02/17/2011 02:01 AM, Jamie Iles wrote:
> >> +
> >> +static void putc(char ch)
> >> +{
> >> + /*
> >> + * Wait for room in the FIFO, then write the char into the FIFO
> >> + */
> >> + while (UART_STATUS(LL_UART_PADDR) & UART_SR_TXFULL)
> >> + ;
> >
> > It might be worth adding a barrier() call to these loops to be
explicit
> > about the volatility.
>
> I think you want cpu_relax() then.
Thanks Stephen.
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum.
>
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
^ permalink raw reply
* [PATCH v6 0/4] omap: mailbox: hwmod support
From: Omar Ramirez Luna @ 2011-02-18 1:42 UTC (permalink / raw)
To: linux-arm-kernel
Mailbox hwmod support for OMAP 2,3,4.
This was tested on OMAP3 (3430, 3630) by using
tidspbridge and OMAP4 (blaze). Also using Kevin's
mailbox test: http://bit.ly/fdk8Au
No testing on OMAP2 since I don't have the hardware.
Changes on v6 include:
- Dropping OMAP4 hwmod patch, as Benoit already sent it.
- Removing irq names in hwmod data for single irq, changed
mailbox to use platform_request_irq in these cases.
- Moved ick to be the main_clk so it can be disabled on
pm_runtime_put_sync.
Highlights from v5 include the comments received from
previous version v4 (http://bit.ly/gfLaIs)
Felipe Contreras (2):
OMAP3: hwmod data: add mailbox data
OMAP: mailbox: build device using omap_device/omap_hwmod
Omar Ramirez Luna (2):
OMAP2: hwmod data: add mailbox data
OMAP: mailbox: use runtime pm for clk and sysc handling
arch/arm/mach-omap2/devices.c | 98 +++++-----------------------
arch/arm/mach-omap2/mailbox.c | 72 ++------------------
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 73 +++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 72 ++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 71 ++++++++++++++++++++
5 files changed, 240 insertions(+), 146 deletions(-)
^ permalink raw reply
* [PATCH v6 1/4] OMAP2: hwmod data: add mailbox data
From: Omar Ramirez Luna @ 2011-02-18 1:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297993347-5654-1-git-send-email-omar.ramirez@ti.com>
Mailbox hwmod data for omap2430 and 2420.
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 73 ++++++++++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 72 +++++++++++++++++++++++++++
2 files changed, 145 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 7fffd34..bd7f982 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -904,6 +904,76 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
};
/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &omap2420_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2420_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+ { .name = "dsp", .irq = 26 },
+ { .name = "iva", .irq = 34 },
+};
+
+static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
+ {
+ .pa_start = 0x48094000,
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
+ .master = &omap2420_l4_core_hwmod,
+ .slave = &omap2420_mailbox_hwmod,
+ .addr = omap2420_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
+ &omap2420_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap2420_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap2420_mailbox_hwmod_class,
+ .mpu_irqs = omap2420_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
+ .main_clk = "mailboxes_ick",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+ },
+ },
+ .slaves = omap2420_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
@@ -1038,6 +1108,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
/* dma_system class*/
&omap2420_dma_system_hwmod,
+ /* mailbox class */
+ &omap2420_mailbox_hwmod,
+
/* mcspi class */
&omap2420_mcspi1_hwmod,
&omap2420_mcspi2_hwmod,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 60fe4aa..2bd1d1e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -978,6 +978,75 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
};
/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &omap2430_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2430_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
+ { .irq = 26 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
+ {
+ .pa_start = 0x48094000,
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
+ .master = &omap2430_l4_core_hwmod,
+ .slave = &omap2430_mailbox_hwmod,
+ .addr = omap2430_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
+ &omap2430_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap2430_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap2430_mailbox_hwmod_class,
+ .mpu_irqs = omap2430_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs),
+ .main_clk = "mailboxes_ick",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+ },
+ },
+ .slaves = omap2430_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
@@ -1156,6 +1225,9 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
/* dma_system class*/
&omap2430_dma_system_hwmod,
+ /* mailbox class */
+ &omap2430_mailbox_hwmod,
+
/* mcspi class */
&omap2430_mcspi1_hwmod,
&omap2430_mcspi2_hwmod,
--
1.7.1
^ permalink raw reply related
* [PATCH v6 2/4] OMAP3: hwmod data: add mailbox data
From: Omar Ramirez Luna @ 2011-02-18 1:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297993347-5654-1-git-send-email-omar.ramirez@ti.com>
From: Felipe Contreras <felipe.contreras@gmail.com>
Mailbox hwmod data for omap3.
Signed-off-by: Felipe Contreras <felipe.contreras@gmail.com>
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 71 ++++++++++++++++++++++++++++
1 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 800eda4..b697c98 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1361,6 +1361,74 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &omap3xxx_mailbox_sysc,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
+ { .irq = 26 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x48094000,
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_mailbox_hwmod,
+ .addr = omap3xxx_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
+ &omap3xxx_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &omap3xxx_mailbox_hwmod_class,
+ .mpu_irqs = omap3xxx_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
+ .main_clk = "mailboxes_ick",
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
/* l4 core -> mcspi1 interface */
static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
{
@@ -1662,6 +1730,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
/* dma_system class*/
&omap3xxx_dma_system_hwmod,
+ /* mailbox class */
+ &omap3xxx_mailbox_hwmod,
+
/* mcspi class */
&omap34xx_mcspi1,
&omap34xx_mcspi2,
--
1.7.1
^ permalink raw reply related
* [PATCH v6 3/4] OMAP: mailbox: build device using omap_device/omap_hwmod
From: Omar Ramirez Luna @ 2011-02-18 1:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297993347-5654-1-git-send-email-omar.ramirez@ti.com>
From: Felipe Contreras <felipe.contreras@gmail.com>
Remove static platform_device and resource data within
omap mailbox driver; use the one defined in the hwmod
database along with omap_device framework for device
build and registration.
Add device latency functions to be used, so clock can be
enabled and sysconfig is configured.
Signed-off-by: Felipe Contreras <felipe.contreras@gmail.com>
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
arch/arm/mach-omap2/devices.c | 98 +++++++----------------------------------
arch/arm/mach-omap2/mailbox.c | 7 +--
2 files changed, 19 insertions(+), 86 deletions(-)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 71f099b..44962eb 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -143,95 +143,29 @@ static inline void omap_init_camera(void)
#endif
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
-
-#define MBOX_REG_SIZE 0x120
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_mbox_resources[] = {
- {
- .start = OMAP24XX_MAILBOX_BASE,
- .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_24XX_MAIL_U0_MPU,
- .flags = IORESOURCE_IRQ,
- .name = "dsp",
- },
- {
- .start = INT_24XX_MAIL_U3_MPU,
- .flags = IORESOURCE_IRQ,
- .name = "iva",
- },
-};
-static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
-#else
-#define omap2_mbox_resources NULL
-#define omap2_mbox_resources_sz 0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_mbox_resources[] = {
- {
- .start = OMAP34XX_MAILBOX_BASE,
- .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_24XX_MAIL_U0_MPU,
- .flags = IORESOURCE_IRQ,
- .name = "dsp",
- },
-};
-static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
-#else
-#define omap3_mbox_resources NULL
-#define omap3_mbox_resources_sz 0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-
-#define OMAP4_MBOX_REG_SIZE 0x130
-static struct resource omap4_mbox_resources[] = {
- {
- .start = OMAP44XX_MAILBOX_BASE,
- .end = OMAP44XX_MAILBOX_BASE +
- OMAP4_MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = OMAP44XX_IRQ_MAIL_U0,
- .flags = IORESOURCE_IRQ,
- .name = "mbox",
+static struct omap_device_pm_latency mbox_latencies[] = {
+ [0] = {
+ .activate_func = omap_device_enable_hwmods,
+ .deactivate_func = omap_device_idle_hwmods,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
},
};
-static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
-#else
-#define omap4_mbox_resources NULL
-#define omap4_mbox_resources_sz 0
-#endif
-
-static struct platform_device mbox_device = {
- .name = "omap-mailbox",
- .id = -1,
-};
static inline void omap_init_mbox(void)
{
- if (cpu_is_omap24xx()) {
- mbox_device.resource = omap2_mbox_resources;
- mbox_device.num_resources = omap2_mbox_resources_sz;
- } else if (cpu_is_omap34xx()) {
- mbox_device.resource = omap3_mbox_resources;
- mbox_device.num_resources = omap3_mbox_resources_sz;
- } else if (cpu_is_omap44xx()) {
- mbox_device.resource = omap4_mbox_resources;
- mbox_device.num_resources = omap4_mbox_resources_sz;
- } else {
- pr_err("%s: platform not supported\n", __func__);
+ struct omap_hwmod *oh;
+ struct omap_device *od;
+
+ oh = omap_hwmod_lookup("mailbox");
+ if (!oh) {
+ pr_err("%s: unable to find hwmod\n", __func__);
return;
}
- platform_device_register(&mbox_device);
+
+ od = omap_device_build("omap-mailbox", -1, oh, NULL, 0,
+ mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
+ WARN(IS_ERR(od), "%s: could not build device, err %ld\n",
+ __func__, PTR_ERR(od));
}
#else
static inline void omap_init_mbox(void) { }
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 29b9dc3..de352bd 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -398,14 +398,14 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
else if (cpu_is_omap34xx()) {
list = omap3_mboxes;
- list[0]->irq = platform_get_irq_byname(pdev, "dsp");
+ list[0]->irq = platform_get_irq(pdev, 0);
}
#endif
#if defined(CONFIG_ARCH_OMAP2)
else if (cpu_is_omap2430()) {
list = omap2_mboxes;
- list[0]->irq = platform_get_irq_byname(pdev, "dsp");
+ list[0]->irq = platform_get_irq(pdev, 0);
} else if (cpu_is_omap2420()) {
list = omap2_mboxes;
@@ -417,8 +417,7 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
else if (cpu_is_omap44xx()) {
list = omap4_mboxes;
- list[0]->irq = list[1]->irq =
- platform_get_irq_byname(pdev, "mbox");
+ list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
}
#endif
else {
--
1.7.1
^ permalink raw reply related
* [PATCH v6 4/4] OMAP: mailbox: use runtime pm for clk and sysc handling
From: Omar Ramirez Luna @ 2011-02-18 1:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297993347-5654-1-git-send-email-omar.ramirez@ti.com>
Use runtime pm APIs to enable/disable mailbox clocks and
to configure SYSC register.
Based on the patch sent by Felipe Contreras:
https://patchwork.kernel.org/patch/101662/
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
arch/arm/mach-omap2/mailbox.c | 67 ++++-------------------------------------
1 files changed, 6 insertions(+), 61 deletions(-)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index de352bd..9a61e1f 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -14,12 +14,11 @@
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
+#include <linux/pm_runtime.h>
#include <plat/mailbox.h>
#include <mach/irqs.h>
#define MAILBOX_REVISION 0x000
-#define MAILBOX_SYSCONFIG 0x010
-#define MAILBOX_SYSSTATUS 0x014
#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
@@ -33,17 +32,6 @@
#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
-/* SYSCONFIG: register bit definition */
-#define AUTOIDLE (1 << 0)
-#define SOFTRESET (1 << 1)
-#define SMARTIDLE (2 << 3)
-#define OMAP4_SOFTRESET (1 << 0)
-#define OMAP4_NOIDLE (1 << 2)
-#define OMAP4_SMARTIDLE (2 << 2)
-
-/* SYSSTATUS: register bit definition */
-#define RESETDONE (1 << 0)
-
#define MBOX_REG_SIZE 0x120
#define OMAP4_MBOX_REG_SIZE 0x130
@@ -70,8 +58,6 @@ struct omap_mbox2_priv {
unsigned long irqdisable;
};
-static struct clk *mbox_ick_handle;
-
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq);
@@ -89,53 +75,13 @@ static inline void mbox_write_reg(u32 val, size_t ofs)
static int omap2_mbox_startup(struct omap_mbox *mbox)
{
u32 l;
- unsigned long timeout;
- mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
- if (IS_ERR(mbox_ick_handle)) {
- printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
- PTR_ERR(mbox_ick_handle));
- return PTR_ERR(mbox_ick_handle);
- }
- clk_enable(mbox_ick_handle);
-
- if (cpu_is_omap44xx()) {
- mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
- timeout = jiffies + msecs_to_jiffies(20);
- do {
- l = mbox_read_reg(MAILBOX_SYSCONFIG);
- if (!(l & OMAP4_SOFTRESET))
- break;
- } while (!time_after(jiffies, timeout));
-
- if (l & OMAP4_SOFTRESET) {
- pr_err("Can't take mailbox out of reset\n");
- return -ENODEV;
- }
- } else {
- mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
- timeout = jiffies + msecs_to_jiffies(20);
- do {
- l = mbox_read_reg(MAILBOX_SYSSTATUS);
- if (l & RESETDONE)
- break;
- } while (!time_after(jiffies, timeout));
-
- if (!(l & RESETDONE)) {
- pr_err("Can't take mailbox out of reset\n");
- return -ENODEV;
- }
- }
+ pm_runtime_enable(mbox->dev->parent);
+ pm_runtime_get_sync(mbox->dev->parent);
l = mbox_read_reg(MAILBOX_REVISION);
pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
- if (cpu_is_omap44xx())
- l = OMAP4_SMARTIDLE;
- else
- l = SMARTIDLE | AUTOIDLE;
- mbox_write_reg(l, MAILBOX_SYSCONFIG);
-
omap2_mbox_enable_irq(mbox, IRQ_RX);
return 0;
@@ -143,9 +89,8 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
- clk_disable(mbox_ick_handle);
- clk_put(mbox_ick_handle);
- mbox_ick_handle = NULL;
+ pm_runtime_put_sync(mbox->dev->parent);
+ pm_runtime_disable(mbox->dev->parent);
}
/* Mailbox FIFO handle functions */
--
1.7.1
^ permalink raw reply related
* [PATCH 0/2] ARM: Update number of VIC for S5P SoCs
From: Kukjin Kim @ 2011-02-18 2:05 UTC (permalink / raw)
To: linux-arm-kernel
The S5PV210 has 4 VICs and S5P6442 and S5PC100 have 3 VICs.
However, default VIC number is defined 2 in arch/arm/common.
So can be happened some problem on above SoCs.
I know, another better patch which has been submitted for it,
but I couldn't find any its progress, right now, need this
for esp., PM and so on.
And if required, can be improved for it later.
[PATCH RE-SEND 1/2] ARM: Update number of VIC for S5PV210
[PATCH RE-SEND 2/2] ARM: Update number of VIC for S5P6442 and S5PC100
^ permalink raw reply
* [PATCH RE-SEND 1/2] ARM: Update number of VIC for S5PV210
From: Kukjin Kim @ 2011-02-18 2:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297994753-22246-1-git-send-email-kgene.kim@samsung.com>
From: Kyungmin Park <kyungmin.park@samsung.com>
S5PV210 SoC have 4 VICs. It requires for suspend and resume.
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/common/Kconfig | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 778655f..9099604 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -6,6 +6,7 @@ config ARM_VIC
config ARM_VIC_NR
int
+ default 4 if ARCH_S5PV210
default 2
depends on ARM_VIC
help
--
1.7.1
^ permalink raw reply related
* [PATCH RE-SEND 2/2] ARM: Update number of VIC for S5P6442 and S5PC100
From: Kukjin Kim @ 2011-02-18 2:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297994753-22246-1-git-send-email-kgene.kim@samsung.com>
Update the number of VIC to handle the 3 VICs of the
S5P6442 and S5PC100.
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/common/Kconfig | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 9099604..ea5ee4d 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -7,6 +7,7 @@ config ARM_VIC
config ARM_VIC_NR
int
default 4 if ARCH_S5PV210
+ default 3 if ARCH_S5P6442 || ARCH_S5PC100
default 2
depends on ARM_VIC
help
--
1.7.1
^ permalink raw reply related
* [PATCH] i.MX23/28 framebuffer driver
From: Jammy Zhou @ 2011-02-18 2:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1102171545470.21278@casper.infradead.org>
To accommodate the fact of independent display controller and GPU components
in ARM SOC, it will be better if we can separate KMS from DRM both in kernel
space and user space (i.e, create a new drivers/video/kms directory for
kernel side, move KMS related code in libdrm to libkms in user space). Then
we can build xrandr1.2+ support based on KMS for ARM platforms, even if DRM
is still not supported. Besides, for buffer management part (GEM) in DRM, if
possible, we can also make it an independent module leaving DRM just a
wrapper, so that the GEM stuff can be used more flexibly.
Regards,
Jammy
On Fri, Feb 18, 2011 at 12:14 AM, James Simmons <jsimmons@infradead.org>wrote:
>
> > I'm still in the learning-as-I-go phase here, so definitely not ready
> > to propose a solution, but it does seem to me like there is room for
> > some sort of kms-helper library here to handle more of the boilerplate
> > xf86-video-* stuff.. I guess I'll have a better picture once I have a
> > chance to add support for the various multi-monitor configurations.
> > But certainly would be interested if anyone already has some ideas.
>
> I have been thinking about this as well. One of the short coming for DRM
> on embedded platforms is the lack of a small well defined library that one
> could use. Right now libkms only handles buffer allocation. The mode
> setting is currently tied to the libdrm library. It would be nice to
> seperate the two out more. Move the mode setting code to libkms and then
> have libdrm be a wrapper around this. This way libdrm can both support
> the legacy drm drivers and the new kms drivers at the same time. It also
> makes a clear seperation. Jakob if you are willing to take this work I
> will gladly seen you patches.
>
> _______________________________________________
> linaro-dev mailing list
> linaro-dev at lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-dev
>
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^ permalink raw reply
* [PATCH 1/2] ARM: PXA: PXAFB: Fix double-free issue.
From: Eric Miao @ 2011-02-18 2:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217185609.GB30606@n2100.arm.linux.org.uk>
On Fri, Feb 18, 2011 at 2:56 AM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Thu, Feb 17, 2011 at 07:17:41PM +0100, Marek Vasut wrote:
>> Why are you getting rid of the atomic operations ?
>
> Because they're idiotic. ?Just because something is called "atomic"
> doesn't make it so, and this is one instance where it's absolutely
> useless.
Yep, I completely agree that's useless here.
^ permalink raw reply
* [PATCH] i.MX23/28 framebuffer driver
From: Jammy Zhou @ 2011-02-18 2:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTim4rsuDLnyLtetMpn_i+x0e8FmyzLvy1Bm0JEAG@mail.gmail.com>
I also noticed that default XRandR1.2+ implementation is missing in X side.
If we can implement one, it would be beneficial for all ARM platforms. By
the way, does X driver of TI support XRandR1.2+?
Regards,
Jammy
On Thu, Feb 17, 2011 at 11:25 PM, Clark, Rob <rob@ti.com> wrote:
> Hmm, I was thinking more on the xf86 side of things.. ie. to provide
> default implementations of xf86CrtcFuncsRec and xf86OutputFuncsRec
> functions..
>
> BR,
> -R
>
> On Wed, Feb 16, 2011 at 7:24 PM, Jammy Zhou <jammy.zhou@linaro.org> wrote:
> >
> > There is already one KMS abstraction layer (libkms.so) in libdrm, maybe
> it can serve as what we needed.
> >
> > Regards,
> > Jammy
> >
> > On Thu, Feb 17, 2011 at 9:08 AM, Clark, Rob <rob@ti.com> wrote:
> >>
> >> I'm still in the learning-as-I-go phase here, so definitely not ready
> >> to propose a solution, but it does seem to me like there is room for
> >> some sort of kms-helper library here to handle more of the boilerplate
> >> xf86-video-* stuff.. I guess I'll have a better picture once I have a
> >> chance to add support for the various multi-monitor configurations.
> >> But certainly would be interested if anyone already has some ideas.
> >>
> >> BR,
> >> -R
> >>
> >> On Wed, Feb 16, 2011 at 8:42 AM, Jesse Barker <jesse.barker@linaro.org>
> wrote:
> >> > Speaking for the Linaro graphics working group, I think it's great.
> And, I
> >> > think you're right, that if enough of the KMS support in xf86-video-*
> is
> >> > similar enough (I was only aware of intel and nouveau supporting it
> properly
> >> > at current), pulling it out into a common layer would make it easier
> to
> >> > support in new drivers (including fbdev).
> >> >
> >> > cheers,
> >> > Jesse
> >> >
> >> > On Wed, Feb 16, 2011 at 4:22 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> >> >>
> >> >> On Tuesday 15 February 2011, Clark, Rob wrote:
> >> >> > I'd been experimenting a bit on the side w/ the DRM driver
> framework (
> >> >> >
> >> >> >
> http://gitorious.com/~robclark/pandaboard/robclarks-kernel-omap4/commits/omap_gpu
> >> >> > ), but had to add a good chunk of mostly boilerplate code to our
> xorg
> >> >> > driver in order just to test it. Maybe some generic support for
> KMS
> >> >> > in xf86-video-fbdev would have made this easier to develop the
> kernel
> >> >> > part without in parallel having to implement the userspace part.
> I'm
> >> >> > not sure if this is the sort of thing the linaro-wg has in mind?
> >> >>
> >> >> I'm not sure what the the linaro multimedia wg thinks of this, but
> the
> >> >> kernel code you linked looks like it's doing exactly the right thing.
> >> >>
> >> >> Arnd
> >> >>
> >> >> _______________________________________________
> >> >> linaro-dev mailing list
> >> >> linaro-dev at lists.linaro.org
> >> >> http://lists.linaro.org/mailman/listinfo/linaro-dev
> >> >
> >> >
> >>
> >> _______________________________________________
> >> linaro-dev mailing list
> >> linaro-dev at lists.linaro.org
> >> http://lists.linaro.org/mailman/listinfo/linaro-dev
> >
>
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^ permalink raw reply
* The p2v branch
From: Nicolas Pitre @ 2011-02-18 2:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1102130915120.14920@xanadu.home>
On Sun, 13 Feb 2011, Nicolas Pitre wrote:
> On Sun, 13 Feb 2011, Russell King - ARM Linux wrote:
>
> > On Sat, Feb 12, 2011 at 04:01:14PM -0500, Nicolas Pitre wrote:
> > > I've rebased my 2 patches on top of your latest p2v branch. You may
> > > pull them from:
> > >
> > > git://git.linaro.org/people/nico/linux p2v
> > >
> > > Or if you prefer I can put them in the patch system.
> >
> > I'd like to wait for Catalin to respond on the phys_addr_t patch - which
> > allows 64-bit phys addresses. Obviously that's going to have an impact
> > on the p2v code and I'd rather someone else had the job of working out
> > what to do about the T2 code.
>
> OK.
Now rebased on top of p2v-stable, and includes the lookup_machine_type()
cleanup patch.
Nicolas Pitre (3):
ARM: P2V: Thumb2 support
ARM: ignore mdesc->boot_params if out of range
ARM: fold lookup_machine_type() into setup_machine()
arch/arm/Kconfig | 4 +-
arch/arm/kernel/head.S | 49 ++++++++++++++++++++++++++++-
arch/arm/kernel/setup.c | 69 +++++++++++++++++++++-------------------
3 files changed, 86 insertions(+), 36 deletions(-)
Nicolas
^ permalink raw reply
* platform/i2c busses: pm runtime and system sleep
From: Rabin Vincent @ 2011-02-18 2:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTikRUZRh0YnP8nYTKFnFeUiJbK5xKvHHjn_S+gZE@mail.gmail.com>
On Thu, Feb 17, 2011 at 20:55, Rabin Vincent <rabin@rab.in> wrote:
> This will solve the platform vs AMBA bus, but shouldn't we really be
> aiming for consistent behaviour between these and the other busses such
> as I2C and SPI, which are also usually commonly used on the same
> platforms and are using GENERIC_PM_OPS?
>
> Should we be auditing all platform drivers and then switch platform to
> the GENERIC_PM_OPS?
>
> Or should the two points (1) and (2) be not handled in the bus at all
> and be left to individual drivers (in which case we should audit i2c and
> spi and change GENERIC_PM_OPS)?
How about something like the below? If we have something like this, we
can just switch platform to GENERIC_PM_OPS and add the
pm_runtime_want_interaction() (or something better named) call to the
i2c and spi drivers using runtime PM.
diff --git a/drivers/base/power/generic_ops.c b/drivers/base/power/generic_ops.c
index 42f97f9..c2a3b63 100644
--- a/drivers/base/power/generic_ops.c
+++ b/drivers/base/power/generic_ops.c
@@ -87,7 +87,10 @@ static int __pm_generic_call(struct device *dev, int event)
const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
int (*callback)(struct device *);
- if (!pm || pm_runtime_suspended(dev))
+ if (!pm)
+ return 0;
+
+ if (device_want_interaction(dev) && pm_runtime_suspended(dev))
return 0;
switch (event) {
@@ -185,7 +188,7 @@ static int __pm_generic_resume(struct device *dev,
int event)
return 0;
ret = callback(dev);
- if (!ret && pm_runtime_enabled(dev)) {
+ if (!ret && device_want_interaction(dev) && pm_runtime_enabled(dev)) {
pm_runtime_disable(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c
index 42615b4..2b8a099 100644
--- a/drivers/base/power/runtime.c
+++ b/drivers/base/power/runtime.c
@@ -1069,6 +1069,30 @@ void pm_runtime_allow(struct device *dev)
EXPORT_SYMBOL_GPL(pm_runtime_allow);
/**
+ * pm_runtime_want_interaction - Enable interaction between system sleep
+ * and runtime PM callbacks at the bus/subsystem
+ * level.
+ * @dev: Device to handle
+ *
+ * Set the power.want_interaction flage, which tells the generic PM subsystem
+ * ops that the following actions should be done during system suspend/resume:
+ *
+ * - If the device has been runtime suspended, the driver's
+ * suspend() handler will not be invoked.
+ *
+ * - If the device has a resume() pm callback, and the resume()
+ * callback returns success on system resume, the device's
+ * runtime PM status will be set to active.
+ */
+void pm_runtime_want_interaction(struct device *dev)
+{
+ spin_lock_irq(&dev->power.lock);
+ dev->power.want_interaction = 1;
+ spin_unlock_irq(&dev->power.lock);
+}
+EXPORT_SYMBOL_GPL(pm_runtime_want_interaction);
+
+/**
* pm_runtime_no_callbacks - Ignore run-time PM callbacks for a device.
* @dev: Device to handle.
*
diff --git a/include/linux/pm.h b/include/linux/pm.h
index dd9c7ab..b9bcfb9 100644
--- a/include/linux/pm.h
+++ b/include/linux/pm.h
@@ -450,6 +450,7 @@ struct dev_pm_info {
unsigned int irq_safe:1;
unsigned int use_autosuspend:1;
unsigned int timer_autosuspends:1;
+ unsigned int want_interaction:1;
enum rpm_request request;
enum rpm_status runtime_status;
int runtime_error;
diff --git a/include/linux/pm_runtime.h b/include/linux/pm_runtime.h
index d34f067..a0e081b 100644
--- a/include/linux/pm_runtime.h
+++ b/include/linux/pm_runtime.h
@@ -44,6 +44,7 @@ extern void pm_runtime_irq_safe(struct device *dev);
extern void __pm_runtime_use_autosuspend(struct device *dev, bool use);
extern void pm_runtime_set_autosuspend_delay(struct device *dev, int delay);
extern unsigned long pm_runtime_autosuspend_expiration(struct device *dev);
+static void pm_runtime_want_system_sleep_interaction(struct device *dev);
static inline bool pm_children_suspended(struct device *dev)
{
@@ -66,6 +67,11 @@ static inline void pm_runtime_put_noidle(struct device *dev)
atomic_add_unless(&dev->power.usage_count, -1, 0);
}
+static inline bool device_want_interaction(struct device *dev)
+{
+ return dev->power.want_interaction;
+}
+
static inline bool device_run_wake(struct device *dev)
{
return dev->power.run_wake;
@@ -122,6 +128,7 @@ static inline bool pm_children_suspended(struct
device *dev) { return false; }
static inline void pm_suspend_ignore_children(struct device *dev, bool en) {}
static inline void pm_runtime_get_noresume(struct device *dev) {}
static inline void pm_runtime_put_noidle(struct device *dev) {}
+static inline bool device_want_interaction(struct device *dev) {
return false; }
static inline bool device_run_wake(struct device *dev) { return false; }
static inline void device_set_run_wake(struct device *dev, bool enable) {}
static inline bool pm_runtime_suspended(struct device *dev) { return false; }
@@ -132,6 +139,7 @@ static inline int
pm_generic_runtime_suspend(struct device *dev) { return 0; }
static inline int pm_generic_runtime_resume(struct device *dev) { return 0; }
static inline void pm_runtime_no_callbacks(struct device *dev) {}
static inline void pm_runtime_irq_safe(struct device *dev) {}
+static inline void pm_runtime_want_system_sleep_interaction(struct
device *dev) {}
static inline void pm_runtime_mark_last_busy(struct device *dev) {}
static inline void __pm_runtime_use_autosuspend(struct device *dev,
^ permalink raw reply related
* [PATCH 04/29] ab3550: mfd_cell is now implicitly available to drivers
From: Andres Salomon @ 2011-02-18 3:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297998456-7615-1-git-send-email-dilinger@queued.net>
No clients (in mainline kernel, I'm told that drivers exist in external
trees that are planned for mainline inclusion) make use of this, nor
do they make use of platform_data, so nothing really had to change here.
The .data_size field is unused, so its usage gets removed.
Signed-off-by: Andres Salomon <dilinger@queued.net>
---
drivers/mfd/ab3550-core.c | 4 +---
include/linux/mfd/abx500.h | 1 -
2 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/drivers/mfd/ab3550-core.c b/drivers/mfd/ab3550-core.c
index 5fbca34..d849087 100644
--- a/drivers/mfd/ab3550-core.c
+++ b/drivers/mfd/ab3550-core.c
@@ -1320,10 +1320,8 @@ static int __init ab3550_probe(struct i2c_client *client,
goto exit_no_ops;
/* Set up and register the platform devices. */
- for (i = 0; i < AB3550_NUM_DEVICES; i++) {
+ for (i = 0; i < AB3550_NUM_DEVICES; i++)
ab3550_devs[i].platform_data = ab3550_plf_data->dev_data[i];
- ab3550_devs[i].data_size = ab3550_plf_data->dev_data_sz[i];
- }
err = mfd_add_devices(&client->dev, 0, ab3550_devs,
ARRAY_SIZE(ab3550_devs), NULL,
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index 67bd6f7..7d9b6ae 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -186,7 +186,6 @@ struct abx500_init_settings {
struct ab3550_platform_data {
struct {unsigned int base; unsigned int count; } irq;
void *dev_data[AB3550_NUM_DEVICES];
- size_t dev_data_sz[AB3550_NUM_DEVICES];
struct abx500_init_settings *init_settings;
unsigned int init_settings_sz;
};
--
1.7.2.3
^ permalink raw reply related
* [PATCH 05/29] ab3100: mfd_cell is now implicitly available to drivers (v2)
From: Andres Salomon @ 2011-02-18 3:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297998456-7615-1-git-send-email-dilinger@queued.net>
The cell's platform_data is now accessed with a helper function;
change clients to use that, and remove the now-unused data_size.
v2: add some missing mfd/core.h includes.
Signed-off-by: Andres Salomon <dilinger@queued.net>
---
drivers/mfd/ab3100-core.c | 4 +---
drivers/regulator/ab3100.c | 3 ++-
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/mfd/ab3100-core.c b/drivers/mfd/ab3100-core.c
index 4193af5..b44c3d9 100644
--- a/drivers/mfd/ab3100-core.c
+++ b/drivers/mfd/ab3100-core.c
@@ -949,10 +949,8 @@ static int __devinit ab3100_probe(struct i2c_client *client,
goto exit_no_ops;
/* Set up and register the platform devices. */
- for (i = 0; i < ARRAY_SIZE(ab3100_devs); i++) {
+ for (i = 0; i < ARRAY_SIZE(ab3100_devs); i++)
ab3100_devs[i].platform_data = ab3100_plf_data;
- ab3100_devs[i].data_size = sizeof(struct ab3100_platform_data);
- }
err = mfd_add_devices(&client->dev, 0, ab3100_devs,
ARRAY_SIZE(ab3100_devs), NULL, 0);
diff --git a/drivers/regulator/ab3100.c b/drivers/regulator/ab3100.c
index ed6feaf..2dec589 100644
--- a/drivers/regulator/ab3100.c
+++ b/drivers/regulator/ab3100.c
@@ -17,6 +17,7 @@
#include <linux/platform_device.h>
#include <linux/regulator/driver.h>
#include <linux/mfd/abx500.h>
+#include <linux/mfd/core.h>
/* LDO registers and some handy masking definitions for AB3100 */
#define AB3100_LDO_A 0x40
@@ -576,7 +577,7 @@ ab3100_regulator_desc[AB3100_NUM_REGULATORS] = {
static int __devinit ab3100_regulators_probe(struct platform_device *pdev)
{
- struct ab3100_platform_data *plfdata = pdev->dev.platform_data;
+ struct ab3100_platform_data *plfdata = mfd_get_data(pdev);
int err = 0;
u8 data;
int i;
--
1.7.2.3
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