* [PATCH for 2.6.38] ARM: S5PC110: fix regulator names
From: Kukjin Kim @ 2011-02-18 9:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297760487-7930-1-git-send-email-m.szyprowski@samsung.com>
Marek Szyprowski wrote:
>
> Since commit 1130e5b3ff4 regulators are exported to debugfs. The names
> of the regulators that contains slash ('/') causes an ops during kernel
> boot. This patch fixes this issue.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
> arch/arm/mach-s5pv210/mach-aquila.c | 6 +++---
> arch/arm/mach-s5pv210/mach-goni.c | 6 +++---
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-
> s5pv210/mach-aquila.c
> index 1236e19..557add4 100644
> --- a/arch/arm/mach-s5pv210/mach-aquila.c
> +++ b/arch/arm/mach-s5pv210/mach-aquila.c
> @@ -149,7 +149,7 @@ static struct regulator_init_data aquila_ldo2_data = {
>
> static struct regulator_init_data aquila_ldo3_data = {
> .constraints = {
> - .name = "VUSB/MIPI_1.1V",
> + .name = "VUSB+MIPI_1.1V",
> .min_uV = 1100000,
> .max_uV = 1100000,
> .apply_uV = 1,
> @@ -197,7 +197,7 @@ static struct regulator_init_data aquila_ldo7_data = {
>
> static struct regulator_init_data aquila_ldo8_data = {
> .constraints = {
> - .name = "VUSB/VADC_3.3V",
> + .name = "VUSB+VADC_3.3V",
> .min_uV = 3300000,
> .max_uV = 3300000,
> .apply_uV = 1,
> @@ -207,7 +207,7 @@ static struct regulator_init_data aquila_ldo8_data = {
>
> static struct regulator_init_data aquila_ldo9_data = {
> .constraints = {
> - .name = "VCC/VCAM_2.8V",
> + .name = "VCC+VCAM_2.8V",
> .min_uV = 2800000,
> .max_uV = 2800000,
> .apply_uV = 1,
> diff --git a/arch/arm/mach-s5pv210/mach-goni.c
b/arch/arm/mach-s5pv210/mach-
> goni.c
> index 2beeb66..056f5c7 100644
> --- a/arch/arm/mach-s5pv210/mach-goni.c
> +++ b/arch/arm/mach-s5pv210/mach-goni.c
> @@ -288,7 +288,7 @@ static struct regulator_init_data goni_ldo2_data = {
>
> static struct regulator_init_data goni_ldo3_data = {
> .constraints = {
> - .name = "VUSB/MIPI_1.1V",
> + .name = "VUSB+MIPI_1.1V",
> .min_uV = 1100000,
> .max_uV = 1100000,
> .apply_uV = 1,
> @@ -337,7 +337,7 @@ static struct regulator_init_data goni_ldo7_data = {
>
> static struct regulator_init_data goni_ldo8_data = {
> .constraints = {
> - .name = "VUSB/VADC_3.3V",
> + .name = "VUSB+VADC_3.3V",
> .min_uV = 3300000,
> .max_uV = 3300000,
> .apply_uV = 1,
> @@ -347,7 +347,7 @@ static struct regulator_init_data goni_ldo8_data = {
>
> static struct regulator_init_data goni_ldo9_data = {
> .constraints = {
> - .name = "VCC/VCAM_2.8V",
> + .name = "VCC+VCAM_2.8V",
> .min_uV = 2800000,
> .max_uV = 2800000,
> .apply_uV = 1,
> --
Ok, applied into s5p-fixes-for-linus for 38.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [PATCH for 2.6.38] ARM: S5PC110: update max8998_platform_data
From: Kukjin Kim @ 2011-02-18 9:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297760464-7639-1-git-send-email-m.szyprowski@samsung.com>
Marek Szyprowski wrote:
>
> Max8998 PMIC driver's platform data has been changed once again in
> commit 735a3d9efdc. This patch fixes build break caused by that commit.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
> arch/arm/mach-s5pv210/mach-aquila.c | 9 ++++++---
> arch/arm/mach-s5pv210/mach-goni.c | 9 ++++++---
> 2 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-
> s5pv210/mach-aquila.c
> index 461aa035..1236e19 100644
> --- a/arch/arm/mach-s5pv210/mach-aquila.c
> +++ b/arch/arm/mach-s5pv210/mach-aquila.c
> @@ -381,9 +381,12 @@ static struct max8998_platform_data
aquila_max8998_pdata
> = {
> .buck1_set1 = S5PV210_GPH0(3),
> .buck1_set2 = S5PV210_GPH0(4),
> .buck2_set3 = S5PV210_GPH0(5),
> - .buck1_max_voltage1 = 1200000,
> - .buck1_max_voltage2 = 1200000,
> - .buck2_max_voltage = 1200000,
> + .buck1_voltage1 = 1200000,
> + .buck1_voltage2 = 1200000,
> + .buck1_voltage3 = 1200000,
> + .buck1_voltage4 = 1200000,
> + .buck2_voltage1 = 1200000,
> + .buck2_voltage2 = 1200000,
> };
> #endif
>
> diff --git a/arch/arm/mach-s5pv210/mach-goni.c
b/arch/arm/mach-s5pv210/mach-
> goni.c
> index e22d511..2beeb66 100644
> --- a/arch/arm/mach-s5pv210/mach-goni.c
> +++ b/arch/arm/mach-s5pv210/mach-goni.c
> @@ -521,9 +521,12 @@ static struct max8998_platform_data
goni_max8998_pdata =
> {
> .buck1_set1 = S5PV210_GPH0(3),
> .buck1_set2 = S5PV210_GPH0(4),
> .buck2_set3 = S5PV210_GPH0(5),
> - .buck1_max_voltage1 = 1200000,
> - .buck1_max_voltage2 = 1200000,
> - .buck2_max_voltage = 1200000,
> + .buck1_voltage1 = 1200000,
> + .buck1_voltage2 = 1200000,
> + .buck1_voltage3 = 1200000,
> + .buck1_voltage4 = 1200000,
> + .buck2_voltage1 = 1200000,
> + .buck2_voltage2 = 1200000,
> };
> #endif
>
> --
Ok, applied into s5p-fixes-for-linus for 38.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [PATCH v2] mxcmmc: use dmaengine API
From: Sascha Hauer @ 2011-02-18 9:21 UTC (permalink / raw)
To: linux-arm-kernel
This switches the mxcmmc driver to use the dmaengine API. Unlike
the old one this one is always present in the tree, even if no DMA
is implemented, hence we can remove all the #ifdefs in from the driver.
The driver automatically switches to PIO mode if no DMA support or no
suitable channel is available.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Arnd recognized that it's not a good idea that the driver has to
know about the dmaengine implementation (the struct imx_dma_data field).
I have a patch in my queue fixing this, but as this has to be
synchronized with the platform code, I'd like to address this in a later
patch.
drivers/mmc/host/mxcmmc.c | 183 ++++++++++++++++++++++++++-------------------
1 files changed, 105 insertions(+), 78 deletions(-)
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index 4428594..cc20e02 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -32,16 +32,14 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
+#include <linux/dmaengine.h>
#include <asm/dma.h>
#include <asm/irq.h>
#include <asm/sizes.h>
#include <mach/mmc.h>
-#ifdef CONFIG_ARCH_MX2
-#include <mach/dma-mx1-mx2.h>
-#define HAS_DMA
-#endif
+#include <mach/dma.h>
#define DRIVER_NAME "mxc-mmc"
@@ -118,7 +116,8 @@ struct mxcmci_host {
void __iomem *base;
int irq;
int detect_irq;
- int dma;
+ struct dma_chan *dma;
+ struct dma_async_tx_descriptor *desc;
int do_dma;
int default_irq_mask;
int use_sdio;
@@ -129,7 +128,6 @@ struct mxcmci_host {
struct mmc_command *cmd;
struct mmc_data *data;
- unsigned int dma_nents;
unsigned int datasize;
unsigned int dma_dir;
@@ -144,6 +142,11 @@ struct mxcmci_host {
spinlock_t lock;
struct regulator *vcc;
+
+ int burstlen;
+ int dmareq;
+ struct dma_slave_config dma_slave_config;
+ struct imx_dma_data dma_data;
};
static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
@@ -206,17 +209,16 @@ static void mxcmci_softreset(struct mxcmci_host *host)
writew(0xff, host->base + MMC_REG_RES_TO);
}
+static int mxcmci_setup_dma(struct mmc_host *mmc);
static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
{
unsigned int nob = data->blocks;
unsigned int blksz = data->blksz;
unsigned int datasize = nob * blksz;
-#ifdef HAS_DMA
struct scatterlist *sg;
- int i;
- int ret;
-#endif
+ int i, nents;
+
if (data->flags & MMC_DATA_STREAM)
nob = 0xffff;
@@ -227,7 +229,9 @@ static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
writew(blksz, host->base + MMC_REG_BLK_LEN);
host->datasize = datasize;
-#ifdef HAS_DMA
+ if (!mxcmci_use_dma(host))
+ return 0;
+
for_each_sg(data->sg, sg, data->sg_len, i) {
if (sg->offset & 3 || sg->length & 3) {
host->do_dma = 0;
@@ -235,34 +239,30 @@ static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
}
}
- if (data->flags & MMC_DATA_READ) {
+ if (data->flags & MMC_DATA_READ)
host->dma_dir = DMA_FROM_DEVICE;
- host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
- data->sg_len, host->dma_dir);
-
- ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents,
- datasize,
- host->res->start + MMC_REG_BUFFER_ACCESS,
- DMA_MODE_READ);
- } else {
+ else
host->dma_dir = DMA_TO_DEVICE;
- host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
- data->sg_len, host->dma_dir);
- ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents,
- datasize,
- host->res->start + MMC_REG_BUFFER_ACCESS,
- DMA_MODE_WRITE);
- }
+ nents = dma_map_sg(host->dma->device->dev, data->sg,
+ data->sg_len, host->dma_dir);
+ if (nents != data->sg_len)
+ return -EINVAL;
+
+ host->desc = host->dma->device->device_prep_slave_sg(host->dma,
+ data->sg, data->sg_len, host->dma_dir,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
- if (ret) {
- dev_err(mmc_dev(host->mmc), "failed to setup DMA : %d\n", ret);
- return ret;
+ if (!host->desc) {
+ dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
+ host->dma_dir);
+ host->do_dma = 0;
+ return 0; /* Fall back to PIO */
}
wmb();
- imx_dma_enable(host->dma);
-#endif /* HAS_DMA */
+ dmaengine_submit(host->desc);
+
return 0;
}
@@ -337,13 +337,11 @@ static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
struct mmc_data *data = host->data;
int data_error;
-#ifdef HAS_DMA
if (mxcmci_use_dma(host)) {
- imx_dma_disable(host->dma);
- dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
+ dmaengine_terminate_all(host->dma);
+ dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
host->dma_dir);
}
-#endif
if (stat & STATUS_ERR_MASK) {
dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
@@ -545,7 +543,6 @@ static void mxcmci_datawork(struct work_struct *work)
}
}
-#ifdef HAS_DMA
static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
{
struct mmc_data *data = host->data;
@@ -568,7 +565,6 @@ static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
mxcmci_finish_request(host, host->req);
}
}
-#endif /* HAS_DMA */
static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
{
@@ -606,12 +602,10 @@ static irqreturn_t mxcmci_irq(int irq, void *devid)
sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
spin_unlock_irqrestore(&host->lock, flags);
-#ifdef HAS_DMA
if (mxcmci_use_dma(host) &&
(stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE)))
writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
host->base + MMC_REG_STATUS);
-#endif
if (sdio_irq) {
writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS);
@@ -621,14 +615,14 @@ static irqreturn_t mxcmci_irq(int irq, void *devid)
if (stat & STATUS_END_CMD_RESP)
mxcmci_cmd_done(host, stat);
-#ifdef HAS_DMA
if (mxcmci_use_dma(host) &&
(stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
mxcmci_data_done(host, stat);
-#endif
+
if (host->default_irq_mask &&
(stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
mmc_detect_change(host->mmc, msecs_to_jiffies(200));
+
return IRQ_HANDLED;
}
@@ -642,9 +636,10 @@ static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
host->req = req;
host->cmdat &= ~CMD_DAT_CONT_INIT;
-#ifdef HAS_DMA
- host->do_dma = 1;
-#endif
+
+ if (host->dma)
+ host->do_dma = 1;
+
if (req->data) {
error = mxcmci_setup_data(host, req->data);
if (error) {
@@ -660,6 +655,7 @@ static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
}
error = mxcmci_start_cmd(host, req->cmd, cmdat);
+
out:
if (error)
mxcmci_finish_request(host, req);
@@ -698,22 +694,46 @@ static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
prescaler, divider, clk_in, clk_ios);
}
+static int mxcmci_setup_dma(struct mmc_host *mmc)
+{
+ struct mxcmci_host *host = mmc_priv(mmc);
+ struct dma_slave_config *config = &host->dma_slave_config;
+
+ config->dst_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
+ config->src_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
+ config->dst_addr_width = 4;
+ config->src_addr_width = 4;
+ config->dst_maxburst = host->burstlen;
+ config->src_maxburst = host->burstlen;
+
+ return dmaengine_slave_config(host->dma, config);
+}
+
static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct mxcmci_host *host = mmc_priv(mmc);
-#ifdef HAS_DMA
- unsigned int blen;
+ int burstlen, ret;
+
/*
* use burstlen of 64 in 4 bit mode (--> reg value 0)
* use burstlen of 16 in 1 bit mode (--> reg value 16)
*/
if (ios->bus_width == MMC_BUS_WIDTH_4)
- blen = 0;
+ burstlen = 64;
else
- blen = 16;
+ burstlen = 16;
+
+ if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
+ host->burstlen = burstlen;
+ ret = mxcmci_setup_dma(mmc);
+ if (ret) {
+ dev_err(mmc_dev(host->mmc),
+ "failed to config DMA channel. Falling back to PIO\n");
+ dma_release_channel(host->dma);
+ host->do_dma = 0;
+ }
+ }
- imx_dma_config_burstlen(host->dma, blen);
-#endif
if (ios->bus_width == MMC_BUS_WIDTH_4)
host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
else
@@ -794,6 +814,18 @@ static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
host->caps |= MMC_CAP_4_BIT_DATA;
}
+static bool filter(struct dma_chan *chan, void *param)
+{
+ struct mxcmci_host *host = param;
+
+ if (!imx_dma_is_general_purpose(chan))
+ return false;
+
+ chan->private = &host->dma_data;
+
+ return true;
+}
+
static const struct mmc_host_ops mxcmci_ops = {
.request = mxcmci_request,
.set_ios = mxcmci_set_ios,
@@ -808,6 +840,7 @@ static int mxcmci_probe(struct platform_device *pdev)
struct mxcmci_host *host = NULL;
struct resource *iores, *r;
int ret = 0, irq;
+ dma_cap_mask_t mask;
printk(KERN_INFO "i.MX SDHC driver\n");
@@ -883,29 +916,23 @@ static int mxcmci_probe(struct platform_device *pdev)
writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR);
-#ifdef HAS_DMA
- host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
- if (host->dma < 0) {
- dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
- ret = -EBUSY;
- goto out_clk_put;
- }
-
r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
- if (!r) {
- ret = -EINVAL;
- goto out_free_dma;
+ if (r) {
+ host->dmareq = r->start;
+ host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
+ host->dma_data.priority = DMA_PRIO_LOW;
+ host->dma_data.dma_request = host->dmareq;
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+ host->dma = dma_request_channel(mask, filter, host);
+ if (host->dma)
+ mmc->max_seg_size = dma_get_max_seg_size(
+ host->dma->device->dev);
}
- ret = imx_dma_config_channel(host->dma,
- IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
- IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
- r->start, 0);
- if (ret) {
- dev_err(mmc_dev(host->mmc), "failed to config DMA channel\n");
- goto out_free_dma;
- }
-#endif
+ if (!host->dma)
+ dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
+
INIT_WORK(&host->datawork, mxcmci_datawork);
ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
@@ -928,9 +955,8 @@ static int mxcmci_probe(struct platform_device *pdev)
out_free_irq:
free_irq(host->irq, host);
out_free_dma:
-#ifdef HAS_DMA
- imx_dma_free(host->dma);
-#endif
+ if (host->dma)
+ dma_release_channel(host->dma);
out_clk_put:
clk_disable(host->clk);
clk_put(host->clk);
@@ -960,9 +986,10 @@ static int mxcmci_remove(struct platform_device *pdev)
free_irq(host->irq, host);
iounmap(host->base);
-#ifdef HAS_DMA
- imx_dma_free(host->dma);
-#endif
+
+ if (host->dma)
+ dma_release_channel(host->dma);
+
clk_disable(host->clk);
clk_put(host->clk);
--
1.7.2.3
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply related
* [PATCH 3/7] Add i.MX5 framebuffer driver
From: Jason Chen @ 2011-02-18 9:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297865452-32181-4-git-send-email-s.hauer@pengutronix.de>
hi, Sasha,
> + if (var->vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */
> + sig_cfg.odd_field_first = 1;
> + if (var->sync & FB_SYNC_EXT)
> + sig_cfg.ext_clk = 1;
> + if (var->sync & FB_SYNC_HOR_HIGH_ACT)
> + sig_cfg.Hsync_pol = 1;
Please remove FB_SYNC_EXT support.
+static void imx_ipu_fb_disable_overlay(struct fb_info *ovl)
+{
+ struct imx_ipu_fb_info *mxc_ovl = ovl->par;
+
+ if (!mxc_ovl->enabled)
+ return;
+
+ ipu_dp_disable_fg(mxc_ovl->dp);
+ ipu_wait_for_interrupt(451, 100);
+ ipu_idmac_disable_channel(mxc_ovl->ipu_ch);
+ ipu_dmfc_disable_channel(mxc_ovl->dmfc);
+ mxc_ovl->enabled = 0;
+}
Had better has a definition of ipu irq 451.
Jason Chen
BRs
^ permalink raw reply
* compiling 2.6.37 kernel in THUMB2 mode
From: Dave Martin @ 2011-02-18 9:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTik1FY=K1Wuo=vnh5xuq6aS1x2d2Km=ByrCSufJC@mail.gmail.com>
On Thu, Feb 17, 2011 at 5:30 PM, <vb@vsbe.com> wrote:
[...]
>
> Hi Dave,
>
> thank you again for the hints.
>
> I am trying to build an image for a Tegra2 based platform, it s a
> 2.6.37 based tree with a fair amount of private additions (to be
> upstreamed at some point), which does now come up and run in ARM mode.
> I am trying to see if it can run in Thumb mode.
>
> It looks like certain files need to be compiled in ARM mode even when
> THUMB2_KERNEL is enabled, but I don't see this happening in 2.6.37, I
> was wondering how this is done in your tree.
Generally, this can be kept to a minimum.
On OMAP, the low-level PM code calls into firmware which cannot cope
with interworking between ARM and Thumb. The PM code on the ARM side
could be made to work with this even if it is mostly built in Thumb,
but that would be complex and not really worth the pain.
You may have this problem if you're trying to communicate with
firmware, but it's best if you port everything else to be buildable in
Thumb-2: the primary reason is that for backwards compatibility
reasons, much of the assembler code in the kernel doesn't support
ARM/Thumb interworking either. This means that mixing ARM and Thumb
code in the kernel will lead to problems unless you're careful.
>
> I tried building an OMAP image, but it does not build in Thumb mode,
> and Thumb can't even be enabled for it because CPU_V6 configured in.
> So I was wondering if this tree has some other working config which
> does use Thumb mode. I'll look at the config files you mentioned, but
> any suggestions/warnings about converting a kernel to work in Thumb
> mode are welcome,
Assuming you started with omap2plus_defconfig, you need to remove
CONFIG_ARCH_OMAP2 from the config. It's not possible to incorporate
support for omap2 with CONFIG_THUMB2_KERNEL enabled because ARMv6
doesn't support Thumb-2.
Here's the config I was using:
http://people.linaro.org/~dmart/arm_omap-thumb2+v2_config (based on
the linaro config-- note: you don't need to build all the modules!
Just make zImage or uImage)
Hope that helps!
---Dave
^ permalink raw reply
* [PATCH 2/2] ARM i.MX23/28: Add framebuffer device support
From: Sascha Hauer @ 2011-02-18 9:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110218091717.GD18085@S2100-06.ap.freescale.net>
On Fri, Feb 18, 2011 at 05:17:18PM +0800, Shawn Guo wrote:
> Hi Sascha,
>
> On Fri, Feb 18, 2011 at 09:46:25AM +0100, Sascha Hauer wrote:
> > On Fri, Feb 18, 2011 at 02:14:41PM +0800, Shawn Guo wrote:
> > > On Wed, Feb 16, 2011 at 10:56:39AM +0100, Sascha Hauer wrote:
> > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > > Cc: Shawn Guo <shawn.guo@freescale.com>
> > > > ---
> > > > arch/arm/mach-mxs/clock-mx23.c | 2 +-
> > > > arch/arm/mach-mxs/clock-mx28.c | 1 +
> > > > arch/arm/mach-mxs/devices-mx23.h | 4 ++
> > > > arch/arm/mach-mxs/devices-mx28.h | 4 ++
> > > > arch/arm/mach-mxs/devices/Kconfig | 4 ++
> > > > arch/arm/mach-mxs/devices/Makefile | 1 +
> > > > arch/arm/mach-mxs/devices/platform-mxsfb.c | 46 ++++++++++++++++++++++++++++
> > > > 7 files changed, 61 insertions(+), 1 deletions(-)
> > > > create mode 100644 arch/arm/mach-mxs/devices/platform-mxsfb.c
> > > >
> > > > diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
> > > > index ca72a05..bfc7f27 100644
> > > > --- a/arch/arm/mach-mxs/clock-mx23.c
> > > > +++ b/arch/arm/mach-mxs/clock-mx23.c
> > > > @@ -446,7 +446,7 @@ static struct clk_lookup lookups[] = {
> > > > _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
> > > > _REGISTER_CLOCK(NULL, "usb", usb_clk)
> > > > _REGISTER_CLOCK(NULL, "audio", audio_clk)
> > > > - _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
> > > Introducing the warning below ...
> > >
> > > arch/arm/mach-mxs/clock-mx23.c:430: warning: ?pwm_clk? defined but not used
> >
> > Right, it was not intended to remove the pwm here. Will fix.
> >
> > >
> > > > + _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
> > > > };
> > > >
> > > > static int clk_misc_init(void)
> > > > diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
> > > > index fd1c4c5..6a7ebcb 100644
> > > > --- a/arch/arm/mach-mxs/clock-mx28.c
> > > > +++ b/arch/arm/mach-mxs/clock-mx28.c
> > > > @@ -620,6 +620,7 @@ static struct clk_lookup lookups[] = {
> > > > _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
> > > > _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
> > > > _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
> > > > + _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
> > > > };
> > > >
> > > > static int clk_misc_init(void)
> > > > diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
> > > > index 1256788..b9745a2 100644
> > > > --- a/arch/arm/mach-mxs/devices-mx23.h
> > > > +++ b/arch/arm/mach-mxs/devices-mx23.h
> > > > @@ -10,7 +10,11 @@
> > > > */
> > > > #include <mach/mx23.h>
> > > > #include <mach/devices-common.h>
> > > > +#include <mach/fb.h>
> > > >
> > > Why do we have mxsfb platform device code breaking the consistency
> > > that we are maintaining well so far?
> >
> > The rule is that we include header files where we need them.
> > devices-common.h is not touched in this patch and it does not need
> > mach/fb.h, hence it is not include there.
> >
> > >
> > > Generally, we have this header included in devices-common.h
> > >
> > > > extern const struct amba_device mx23_duart_device __initconst;
> > > > #define mx23_add_duart() \
> > > > mxs_add_duart(&mx23_duart_device)
> > > > +
> > > > +struct platform_device *__init mx23_add_mxsfb(
> > > > + const struct mxsfb_platform_data *pdata);
> > >
> > > Generally, this goes to devices-common.h
> >
> > No, devices-common.h only declares the mxs_* functions. There is no
> > mxs_add_mxsfb in this patch which indeed would go to devices-common.h
> >
> Well, if you break the consistency in one place, you break the
> consistency every. If you follow the convention to add mxs_add_fb
> in platform_fb.c, declare it in devices-common.h, ..., everything
> gets consistent. We will not have the particular and noticeable fb
> device code everywhere.
>
> > >
> > > I understand that "mxsfb" was picked up for the device name to
> > > reflect the driver name. But since this is the device under mach- mxs
> > > folder, can we simply call it "fb" just like the way you name fb.h?
> > >
> > > In this way, we have all mxs platform device naming schema aligned,
> > > auart, duart, dma, fb, fec, flexcan, mmc ...
> >
> > I see it the other way round. mach/fb.h is too generic, I would prefer
> > mach/mxsfb.h to be able to add support for a different framebuffer
> > later. So I better change fb.h to mxsfb.h.
> >
> I'm fine with either way, but just wondering what kind of fb later
> it is and its naming, relatively to mxsfs.
IPU...?
>
> > >
> > >
> > > Generally, we have macro mxs_fb_data_entry and function mxs_add_fb
> > > in this file. It's nothing but all about consistency. We do not
> > > want some later coming platform device looking at this as example,
> > > and bring more inconsistency into mach-mxs platform device codes.
> >
> > My opinion on this is that we should not use complex ## macro constructs
> > where not necessary. With a device which is only present once on the SoC
> > it is not necessary, so I skippped it. And yes, if someone is in the
> > same situation with a single device on a system, he actually should take
> > this as an example. So no, I don't agree with you.
> >
> With a device presents on more than one SoC, it's also not necessary?
The mxsfb is present on more than one SoC. I was talking about multiple
instances of the same device on one SoC.
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 2/2] ARM i.MX23/28: Add framebuffer device support
From: Shawn Guo @ 2011-02-18 9:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110218092650.GH24426@pengutronix.de>
On Fri, Feb 18, 2011 at 10:26:50AM +0100, Sascha Hauer wrote:
> On Fri, Feb 18, 2011 at 05:17:18PM +0800, Shawn Guo wrote:
> > > > I understand that "mxsfb" was picked up for the device name to
> > > > reflect the driver name. But since this is the device under mach- mxs
> > > > folder, can we simply call it "fb" just like the way you name fb.h?
> > > >
> > > > In this way, we have all mxs platform device naming schema aligned,
> > > > auart, duart, dma, fb, fec, flexcan, mmc ...
> > >
> > > I see it the other way round. mach/fb.h is too generic, I would prefer
> > > mach/mxsfb.h to be able to add support for a different framebuffer
> > > later. So I better change fb.h to mxsfb.h.
> > >
> > I'm fine with either way, but just wondering what kind of fb later
> > it is and its naming, relatively to mxsfs.
>
> IPU...?
>
AFAICT, this is something that never going to happen.
--
Regards,
Shawn
^ permalink raw reply
* [PATCH 7/7] ARM i.MX51 babbage: Add framebuffer support
From: Sascha Hauer @ 2011-02-18 9:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87wrkyo7it.fsf@lechat.rtp-net.org>
On Thu, Feb 17, 2011 at 07:11:54PM +0100, Arnaud Patard wrote:
> Sascha Hauer <s.hauer@pengutronix.de> writes:
>
> Hi,
>
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > arch/arm/mach-mx5/Kconfig | 1 +
> > arch/arm/mach-mx5/board-mx51_babbage.c | 74 ++++++++++++++++++++++++++++++++
> > 2 files changed, 75 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
> > index de4fa992f..89e71da 100644
> > --- a/arch/arm/mach-mx5/Kconfig
> > +++ b/arch/arm/mach-mx5/Kconfig
> > @@ -42,6 +42,7 @@ config MACH_MX51_BABBAGE
> > select IMX_HAVE_PLATFORM_IMX_UART
> > select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
> > select IMX_HAVE_PLATFORM_SPI_IMX
> > + select IMX_HAVE_PLATFORM_IMX_IPUV3
> > help
> > Include support for MX51 Babbage platform, also known as MX51EVK in
> > u-boot. This includes specific configurations for the board and its
> > diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
> > index 1d231e8..c5170e8 100644
> > --- a/arch/arm/mach-mx5/board-mx51_babbage.c
> > +++ b/arch/arm/mach-mx5/board-mx51_babbage.c
> > @@ -22,11 +22,13 @@
> > #include <linux/input.h>
> > #include <linux/spi/flash.h>
> > #include <linux/spi/spi.h>
> > +#include <linux/mfd/imx-ipu-v3.h>
> >
> > #include <mach/common.h>
> > #include <mach/hardware.h>
> > #include <mach/iomux-mx51.h>
> > #include <mach/mxc_ehci.h>
> > +#include <mach/ipu-v3.h>
> >
> > #include <asm/irq.h>
> > #include <asm/setup.h>
> > @@ -158,6 +160,41 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
> > MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
> > MX51_PAD_CSPI1_SS0__GPIO4_24,
> > MX51_PAD_CSPI1_SS1__GPIO4_25,
> > +
> > + /* Display */
> > + MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
> > + MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
> > + MX51_PAD_NANDF_D12__GPIO3_28,
> > +
> > + MX51_PAD_DISP1_DAT0__DISP1_DAT0,
> > + MX51_PAD_DISP1_DAT1__DISP1_DAT1,
> > + MX51_PAD_DISP1_DAT2__DISP1_DAT2,
> > + MX51_PAD_DISP1_DAT3__DISP1_DAT3,
> > + MX51_PAD_DISP1_DAT4__DISP1_DAT4,
> > + MX51_PAD_DISP1_DAT5__DISP1_DAT5,
> > + MX51_PAD_DISP1_DAT6__DISP1_DAT6,
> > + MX51_PAD_DISP1_DAT7__DISP1_DAT7,
> > + MX51_PAD_DISP1_DAT8__DISP1_DAT8,
> > + MX51_PAD_DISP1_DAT9__DISP1_DAT9,
> > + MX51_PAD_DISP1_DAT10__DISP1_DAT10,
> > + MX51_PAD_DISP1_DAT11__DISP1_DAT11,
> > + MX51_PAD_DISP1_DAT12__DISP1_DAT12,
> > + MX51_PAD_DISP1_DAT13__DISP1_DAT13,
> > + MX51_PAD_DISP1_DAT14__DISP1_DAT14,
> > + MX51_PAD_DISP1_DAT15__DISP1_DAT15,
> > + MX51_PAD_DISP1_DAT16__DISP1_DAT16,
> > + MX51_PAD_DISP1_DAT17__DISP1_DAT17,
> > + MX51_PAD_DISP1_DAT18__DISP1_DAT18,
> > + MX51_PAD_DISP1_DAT19__DISP1_DAT19,
> > + MX51_PAD_DISP1_DAT20__DISP1_DAT20,
> > + MX51_PAD_DISP1_DAT21__DISP1_DAT21,
> > + MX51_PAD_DISP1_DAT22__DISP1_DAT22,
> > + MX51_PAD_DISP1_DAT23__DISP1_DAT23,
> > +#define MX51_PAD_DI_GP4__IPU_DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0, 0, NO_PAD_CTRL)
> > + MX51_PAD_DI_GP4__IPU_DI2_PIN15,
> > +
> > + /* I2C DVI enable */
> > + MX51_PAD_CSI2_HSYNC__GPIO4_14,
> > };
> >
> > /* Serial ports */
> > @@ -346,6 +383,23 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
> > .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
> > };
> >
> > +static struct ipuv3_fb_platform_data babbage_fb0_data = {
> > + .interface_pix_fmt = IPU_PIX_FMT_RGB24,
> > + .flags = IMX_IPU_FB_USE_MODEDB | IMX_IPU_FB_USE_OVERLAY,
> > + .display = 0,
> > +};
> > +
> > +static struct ipuv3_fb_platform_data babbage_fb1_data = {
> > + .interface_pix_fmt = IPU_PIX_FMT_RGB565,
> > + .flags = IMX_IPU_FB_USE_MODEDB,
> > + .display = 1,
> > +};
> > +
> > +static struct imx_ipuv3_platform_data ipu_data = {
> > + .fb_head0_platform_data = &babbage_fb0_data,
> > + .fb_head1_platform_data = &babbage_fb1_data,
> > +};
> > +
> > /*
> > * Board specific initialization.
> > */
> > @@ -392,6 +446,26 @@ static void __init mxc_board_init(void)
> > ARRAY_SIZE(mx51_babbage_spi_board_info));
> > imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
> > imx51_add_imx2_wdt(0, NULL);
> > +
> > +#define GPIO_DVI_DETECT (2 * 32 + 28)
> > +#define GPIO_DVI_RESET (2 * 32 + 5)
> > +#define GPIO_DVI_PWRDN (2 * 32 + 6)
> > +#define GPIO_DVI_I2C (3 * 32 + 14)
>
> What about using IMX_GPIO_NR() ?
Yes, changed. Also I'll use gpio_request_array which simplfifies the
code a bit and adds proper error checking.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 1/7] Add a mfd IPUv3 driver
From: Sascha Hauer @ 2011-02-18 9:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <871v36pm5r.fsf@lechat.rtp-net.org>
On Thu, Feb 17, 2011 at 07:10:24PM +0100, Arnaud Patard wrote:
> > diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> > index 6bafb51b..ffdb37a 100644
> > --- a/drivers/video/Kconfig
> > +++ b/drivers/video/Kconfig
> > @@ -26,6 +26,8 @@ source "drivers/gpu/drm/Kconfig"
> >
> > source "drivers/gpu/stub/Kconfig"
> >
> > +source "drivers/video/imx-ipu-v3/Kconfig"
> > +
>
> I don't see such a Kconfig file in this patch. Got lost while moving
> from mfd to video ?
Oops, yes still untracked in my repository. Will add in the next series.
>
>
> > config VGASTATE
> > tristate
> > default n
> > diff --git a/drivers/video/Makefile b/drivers/video/Makefile
> > index 8c8fabd..f4921ab 100644
> > --- a/drivers/video/Makefile
> > +++ b/drivers/video/Makefile
> > @@ -153,6 +153,7 @@ obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o
> > obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o
> > obj-$(CONFIG_FB_MX3) += mx3fb.o
> > obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o
> > +obj-$(CONFIG_MFD_IMX_IPU_V3) += imx-ipu-v3/
>
> Now that files are in drivers/video, do we want to keep MFD in the name ?
I asked myself the same question and had no clear answer. Probably
better to remove the MFD.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 3/7] Add i.MX5 framebuffer driver
From: Sascha Hauer @ 2011-02-18 9:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTina46_CMvB_9cqc4=PvcPxaV_BQ_H_ghJZFFxg8@mail.gmail.com>
Hi Jason,
On Fri, Feb 18, 2011 at 05:22:09PM +0800, Jason Chen wrote:
> hi, Sasha,
>
> > + if (var->vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */
> > + sig_cfg.odd_field_first = 1;
> > + if (var->sync & FB_SYNC_EXT)
> > + sig_cfg.ext_clk = 1;
> > + if (var->sync & FB_SYNC_HOR_HIGH_ACT)
> > + sig_cfg.Hsync_pol = 1;
> Please remove FB_SYNC_EXT support.
No problem, can do. But why? Is it nonfunctional in the hardware
or is it that the current code just misses more pieces to support
this?
>
> +static void imx_ipu_fb_disable_overlay(struct fb_info *ovl)
> +{
> + struct imx_ipu_fb_info *mxc_ovl = ovl->par;
> +
> + if (!mxc_ovl->enabled)
> + return;
> +
> + ipu_dp_disable_fg(mxc_ovl->dp);
> + ipu_wait_for_interrupt(451, 100);
> + ipu_idmac_disable_channel(mxc_ovl->ipu_ch);
> + ipu_dmfc_disable_channel(mxc_ovl->dmfc);
> + mxc_ovl->enabled = 0;
> +}
> Had better has a definition of ipu irq 451.
Ok.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCHv5 0/4] ARM: add initial support for Picochip picoXcell SoC
From: Jamie Iles @ 2011-02-18 10:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This patch series adds support for the Picochip picoXcell series of
femtocell SoC's. There are currently two device families - PC3X2 and
PC3X3. Both include an ARM1176JZ-S, 100Mb Ethernet controller, 2xDMA
controllers, eFuses, crypto offload engines and Picochip's array
processor the picoArray.
I've reduced this patch series down pretty much to the bare minimum to
boot on all device families with serial access but not much more.
Hopefully this will make this series a little easier to review and we
can add the GPIO, muxing, clock gating and PM etc once these have been
merged.
Any feedback would be much appreciated!
Jamie
Note: we also need this patch for the CONFIG_DEBUG_LL:
- debug-8250: add a 32 bit mode:
http://marc.info/?l=linux-arm-kernel&m=129044061221371&w=2
Jamie Iles (4):
picoxcell: add support for picoXcell
picoxcell: add support for the system timers
picoxcell: add common SoC devices
picoxcell: add support for the PC7302 development board
arch/arm/Kconfig | 13 ++
arch/arm/Makefile | 1 +
arch/arm/mach-picoxcell/Kconfig | 12 +
arch/arm/mach-picoxcell/Makefile | 4 +
arch/arm/mach-picoxcell/Makefile.boot | 3 +
arch/arm/mach-picoxcell/axi2cfg.c | 36 ++++
arch/arm/mach-picoxcell/board_pc7302.c | 109 ++++++++++
arch/arm/mach-picoxcell/devices.c | 122 +++++++++++
arch/arm/mach-picoxcell/include/mach/debug-macro.S | 18 ++
arch/arm/mach-picoxcell/include/mach/entry-macro.S | 19 ++
arch/arm/mach-picoxcell/include/mach/hardware.h | 29 +++
arch/arm/mach-picoxcell/include/mach/io.h | 38 ++++
arch/arm/mach-picoxcell/include/mach/irqs.h | 89 ++++++++
arch/arm/mach-picoxcell/include/mach/memory.h | 27 +++
.../include/mach/picoxcell/axi2cfg.h | 122 +++++++++++
.../mach-picoxcell/include/mach/picoxcell/gpio.h | 48 +++++
.../include/mach/picoxcell/picoxcell.h | 62 ++++++
.../mach-picoxcell/include/mach/picoxcell/timer.h | 37 ++++
.../mach-picoxcell/include/mach/picoxcell/wdog.h | 43 ++++
arch/arm/mach-picoxcell/include/mach/platform.h | 27 +++
arch/arm/mach-picoxcell/include/mach/system.h | 51 +++++
arch/arm/mach-picoxcell/include/mach/timex.h | 26 +++
arch/arm/mach-picoxcell/include/mach/uncompress.h | 60 ++++++
arch/arm/mach-picoxcell/include/mach/vmalloc.h | 18 ++
arch/arm/mach-picoxcell/io.c | 49 +++++
arch/arm/mach-picoxcell/picoxcell_core.c | 106 ++++++++++
arch/arm/mach-picoxcell/picoxcell_core.h | 25 +++
arch/arm/mach-picoxcell/soc.h | 32 +++
arch/arm/mach-picoxcell/time.c | 222 ++++++++++++++++++++
29 files changed, 1448 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-picoxcell/Kconfig
create mode 100644 arch/arm/mach-picoxcell/Makefile
create mode 100644 arch/arm/mach-picoxcell/Makefile.boot
create mode 100644 arch/arm/mach-picoxcell/axi2cfg.c
create mode 100644 arch/arm/mach-picoxcell/board_pc7302.c
create mode 100644 arch/arm/mach-picoxcell/devices.c
create mode 100644 arch/arm/mach-picoxcell/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-picoxcell/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-picoxcell/include/mach/hardware.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/io.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/irqs.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/memory.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/axi2cfg.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/gpio.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/picoxcell.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/timer.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/wdog.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/platform.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/system.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/timex.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/uncompress.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-picoxcell/io.c
create mode 100644 arch/arm/mach-picoxcell/picoxcell_core.c
create mode 100644 arch/arm/mach-picoxcell/picoxcell_core.h
create mode 100644 arch/arm/mach-picoxcell/soc.h
create mode 100644 arch/arm/mach-picoxcell/time.c
--
1.7.4
^ permalink raw reply
* [PATCHv5 1/4] picoxcell: add support for picoXcell
From: Jamie Iles @ 2011-02-18 10:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298023231-2747-1-git-send-email-jamie@jamieiles.com>
picoXcell is a family of femtocell SoC devices from Picochip [1] with an
ARM subsystem. The devices have an ARM1176JZ-S core and a DSP processor
array. Currently there are two sub families - PC3X2 and PC3X3. The
latter includes extra power and performance control along with extra
peripherals.
This initial patch adds the hardware definitions and a framework for
adding device variants.
v2:
- Define VMALLOC_END as a fixed address rather than relative to
PAGE_OFFSET
- Reduce the number of static IO mappings
- Put the picoXcell entry in the correct place in
arch/arm/Kconfig
v3:
- Incorporate feedback from RMK
- Refactor static IO mappings into io.c and include arch
specific ioremap and iounmap to reuse static mappings.
- Tell Linux about the TCMs and the onchip SRAM.
- Switch to __raw_ io accessors where possible. Note the AXI2CFG
requires a strongly ordered protocol so retains ordered
accessors.
v4:
- Remove redundant __init declarations and add a cpu_relax() to
the AXI2CFG read polling
- Allow soc variants to register variant specific devices
v5:
- Remove all of the sysdev and AXI2Cfg configuration stuff to
reduce it to the bare minimum to boot on all devices.
1. http://www.picochip.com
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
---
arch/arm/Kconfig | 13 ++
arch/arm/Makefile | 1 +
arch/arm/mach-picoxcell/Kconfig | 4 +
arch/arm/mach-picoxcell/Makefile | 1 +
arch/arm/mach-picoxcell/Makefile.boot | 3 +
arch/arm/mach-picoxcell/axi2cfg.c | 36 ++++++
arch/arm/mach-picoxcell/include/mach/debug-macro.S | 18 +++
arch/arm/mach-picoxcell/include/mach/entry-macro.S | 19 +++
arch/arm/mach-picoxcell/include/mach/hardware.h | 29 +++++
arch/arm/mach-picoxcell/include/mach/io.h | 38 ++++++
arch/arm/mach-picoxcell/include/mach/irqs.h | 89 ++++++++++++++
arch/arm/mach-picoxcell/include/mach/memory.h | 27 +++++
.../include/mach/picoxcell/axi2cfg.h | 122 ++++++++++++++++++++
.../mach-picoxcell/include/mach/picoxcell/gpio.h | 48 ++++++++
.../include/mach/picoxcell/picoxcell.h | 62 ++++++++++
.../mach-picoxcell/include/mach/picoxcell/timer.h | 37 ++++++
.../mach-picoxcell/include/mach/picoxcell/wdog.h | 43 +++++++
arch/arm/mach-picoxcell/include/mach/platform.h | 27 +++++
arch/arm/mach-picoxcell/include/mach/system.h | 51 ++++++++
arch/arm/mach-picoxcell/include/mach/timex.h | 26 ++++
arch/arm/mach-picoxcell/include/mach/uncompress.h | 60 ++++++++++
arch/arm/mach-picoxcell/include/mach/vmalloc.h | 18 +++
arch/arm/mach-picoxcell/io.c | 49 ++++++++
arch/arm/mach-picoxcell/picoxcell_core.c | 105 +++++++++++++++++
arch/arm/mach-picoxcell/picoxcell_core.h | 22 ++++
arch/arm/mach-picoxcell/soc.h | 32 +++++
26 files changed, 980 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-picoxcell/Kconfig
create mode 100644 arch/arm/mach-picoxcell/Makefile
create mode 100644 arch/arm/mach-picoxcell/Makefile.boot
create mode 100644 arch/arm/mach-picoxcell/axi2cfg.c
create mode 100644 arch/arm/mach-picoxcell/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-picoxcell/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-picoxcell/include/mach/hardware.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/io.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/irqs.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/memory.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/axi2cfg.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/gpio.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/picoxcell.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/timer.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/wdog.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/platform.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/system.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/timex.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/uncompress.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-picoxcell/io.c
create mode 100644 arch/arm/mach-picoxcell/picoxcell_core.c
create mode 100644 arch/arm/mach-picoxcell/picoxcell_core.h
create mode 100644 arch/arm/mach-picoxcell/soc.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 08799af..d6f4714 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -605,6 +605,17 @@ config ARCH_PNX4008
help
This enables support for Philips PNX4008 mobile platform.
+config ARCH_PICOXCELL
+ bool "Picochip picoXcell"
+ select ARM_VIC
+ select GENERIC_CLOCKEVENTS
+ select HAVE_SCHED_CLOCK
+ select CPU_V6K
+ select HAVE_TCM
+ help
+ This enables support for systems based on the Picochip picoXcell
+ family of Femtocell devices.
+
config ARCH_PXA
bool "PXA2xx/PXA3xx-based"
depends on MMU
@@ -954,6 +965,8 @@ source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
+source "arch/arm/mach-picoxcell/Kconfig"
+
source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/plat-pxa/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 9a0f6a3..6403eef 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -166,6 +166,7 @@ machine-$(CONFIG_ARCH_OMAP2) := omap2
machine-$(CONFIG_ARCH_OMAP3) := omap2
machine-$(CONFIG_ARCH_OMAP4) := omap2
machine-$(CONFIG_ARCH_ORION5X) := orion5x
+machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell
machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_REALVIEW) := realview
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
new file mode 100644
index 0000000..3daba53
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -0,0 +1,4 @@
+menu "PICOXCELL platform type"
+ depends on ARCH_PICOXCELL
+
+endmenu
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
new file mode 100644
index 0000000..6afe388
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -0,0 +1 @@
+obj-y := picoxcell_core.o io.o axi2cfg.o
diff --git a/arch/arm/mach-picoxcell/Makefile.boot b/arch/arm/mach-picoxcell/Makefile.boot
new file mode 100644
index 0000000..67039c3
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Makefile.boot
@@ -0,0 +1,3 @@
+ zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-picoxcell/axi2cfg.c b/arch/arm/mach-picoxcell/axi2cfg.c
new file mode 100644
index 0000000..6bb4014
--- /dev/null
+++ b/arch/arm/mach-picoxcell/axi2cfg.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support at picochip.com
+ *
+ * This file implements functions for using the axi2cfg to configure and debug
+ * picoArray systems providing configuration bus access over the axi2cfg.
+ */
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+#include <mach/hardware.h>
+
+static void __iomem *axi2cfg;
+
+unsigned long axi2cfg_readl(unsigned long offs)
+{
+ return readl(axi2cfg + offs);
+}
+
+void axi2cfg_writel(unsigned long val, unsigned long offs)
+{
+ writel(val, axi2cfg + offs);
+}
+
+void __init axi2cfg_init(void)
+{
+ axi2cfg = ioremap(PICOXCELL_AXI2CFG_BASE, 0x300);
+ BUG_ON(!axi2cfg);
+}
diff --git a/arch/arm/mach-picoxcell/include/mach/debug-macro.S b/arch/arm/mach-picoxcell/include/mach/debug-macro.S
new file mode 100644
index 0000000..5cbab63
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/debug-macro.S
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+ .macro addruart, rp, rv
+ mov \rv, #0x00230000
+ orr \rp, \rv, #0x80000000
+ orr \rv, \rv, #0xFE000000
+ .endm
+
+#define UART_SHIFT 2
+#define DEBUG_8250_ACCESS_32
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-picoxcell/include/mach/entry-macro.S b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
new file mode 100644
index 0000000..4dcda96
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
@@ -0,0 +1,19 @@
+/*
+ * entry-macro.S
+ *
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * Low-level IRQ helper macros for picoXcell platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <mach/io.h>
+#include <mach/irqs.h>
+
+#define VA_VIC0 IO_ADDRESS(PICOXCELL_VIC0_BASE)
+#define VA_VIC1 IO_ADDRESS(PICOXCELL_VIC1_BASE)
+
+#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-picoxcell/include/mach/hardware.h b/arch/arm/mach-picoxcell/include/mach/hardware.h
new file mode 100644
index 0000000..7c203d3
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/hardware.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This file contains the hardware definitions of the picoXcell SoC devices.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <mach/picoxcell/axi2cfg.h>
+#include <mach/picoxcell/gpio.h>
+#include <mach/picoxcell/picoxcell.h>
+#include <mach/picoxcell/timer.h>
+#include <mach/picoxcell/wdog.h>
+
+#endif
diff --git a/arch/arm/mach-picoxcell/include/mach/io.h b/arch/arm/mach-picoxcell/include/mach/io.h
new file mode 100644
index 0000000..cb11040
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/io.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define PHYS_TO_IO(x) (((x) & 0x00ffffff) | 0xfe000000)
+#ifdef __ASSEMBLY__
+# define IO_ADDRESS(x) PHYS_TO_IO((x))
+#else /* __ASSEMBLY__ */
+# define IO_ADDRESS(x) (void __iomem __force *)(PHYS_TO_IO((x)))
+# define IO_SPACE_LIMIT 0xffffffff
+# define __io(a) __typesafe_io(a)
+# define __mem_pci(a) (a)
+
+#define __arch_ioremap(p, s, t) picoxcell_ioremap(p, s, t)
+#define __arch_iounmap(v) picoxcell_iounmap(v)
+
+void __iomem *picoxcell_ioremap(unsigned long phys, size_t size,
+ unsigned int type);
+void picoxcell_iounmap(volatile void __iomem *addr);
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/irqs.h b/arch/arm/mach-picoxcell/include/mach/irqs.h
new file mode 100644
index 0000000..0fe84ff
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/irqs.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __IRQS_H__
+#define __IRQS_H__
+
+/* VIC0 IRQ Indexes */
+#define IRQ_VIC0_BASE 32
+#define IRQ_EMAC (31 + IRQ_VIC0_BASE)
+#define IRQ_NPMUIRQ (30 + IRQ_VIC0_BASE)
+#define IRQ_NDMAEXTERRIRQ (29 + IRQ_VIC0_BASE)
+#define IRQ_NDMASIRQ (28 + IRQ_VIC0_BASE)
+#define IRQ_NDMAIRQ (27 + IRQ_VIC0_BASE)
+#define IRQ_DMAC2 (26 + IRQ_VIC0_BASE)
+#define IRQ_DMAC1 (25 + IRQ_VIC0_BASE)
+#define IRQ_IPSEC (24 + IRQ_VIC0_BASE)
+#define IRQ_SRTP (23 + IRQ_VIC0_BASE)
+#define IRQ_AES (22 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO8 (21 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO7 (20 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO6 (19 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO5 (18 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO4 (17 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO3 (16 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO2 (15 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO1 (14 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO0 (13 + IRQ_VIC0_BASE)
+#define IRQ_AXI2CFG (12 + IRQ_VIC0_BASE)
+#define IRQ_WDG (11 + IRQ_VIC0_BASE)
+#define IRQ_SSI (10 + IRQ_VIC0_BASE)
+#define IRQ_AXI_RD_ERR (9 + IRQ_VIC0_BASE)
+#define IRQ_AXI_WR_ERR (8 + IRQ_VIC0_BASE)
+#define IRQ_TIMER3 (7 + IRQ_VIC0_BASE)
+#define IRQ_TIMER2 (6 + IRQ_VIC0_BASE)
+#define IRQ_TIMER1 (5 + IRQ_VIC0_BASE)
+#define IRQ_TIMER0 (4 + IRQ_VIC0_BASE)
+#define IRQ_COMMTX (3 + IRQ_VIC0_BASE)
+#define IRQ_COMMRX (2 + IRQ_VIC0_BASE)
+#define IRQ_SWI (1 + IRQ_VIC0_BASE)
+
+/* VIC1 IRQ Indexes */
+#define IRQ_VIC1_BASE 0
+#define IRQ_UART1 (10 + IRQ_VIC1_BASE)
+#define IRQ_UART2 (9 + IRQ_VIC1_BASE)
+#define IRQ_RTC (8 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO7 (7 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO6 (6 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO5 (5 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO4 (4 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO3 (3 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO2 (2 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO1 (1 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO0 (0 + IRQ_VIC1_BASE)
+
+/*
+ * Virtual GPIO interrupts.
+ *
+ * We want to enable/disable interrupts for the GPIO pins through the GPIO
+ * block itself. To do this we install a chained handler. If a user requests
+ * one of the __IRQ_GPIOn interrupts then the GPIO block won't get configured.
+ * We provide these interrupts below as virtual ones that will configure the
+ * GPIO block and enable the source in the VIC.
+ */
+#define IRQ_GPIO7 71
+#define IRQ_GPIO6 70
+#define IRQ_GPIO5 69
+#define IRQ_GPIO4 68
+#define IRQ_GPIO3 67
+#define IRQ_GPIO2 66
+#define IRQ_GPIO1 65
+#define IRQ_GPIO0 64
+
+#define NR_IRQS 72
+
+#endif /* __IRQS_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/memory.h b/arch/arm/mach-picoxcell/include/mach/memory.h
new file mode 100644
index 0000000..c0f6077
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/memory.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PLAT_PHYS_OFFSET UL(0x00000000)
+
+#endif
+
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell/axi2cfg.h b/arch/arm/mach-picoxcell/include/mach/picoxcell/axi2cfg.h
new file mode 100644
index 0000000..94c9800
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell/axi2cfg.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef PICOXCELL_AXI2CFG_H
+#define PICOXCELL_AXI2CFG_H
+
+#define AXI2CFG_SYSCFG_REG_OFFSET 0x0000
+#define AXI2CFG_JTAG_ISC_REG_OFFSET 0x0004
+#define AXI2CFG_IRQ_REG_OFFSET 0x0008
+#define AXI2CFG_PURGE_CFG_PORT_REG_OFFSET 0x000C
+#define AXI2CFG_DMA_CFG_REG_OFFSET 0x0010
+#define AXI2CFG_DEVICE_ID_REG_OFFSET 0x0014
+#define AXI2CFG_REVISION_ID_REG_OFFSET 0x0018
+#define AXI2CFG_AXI_ERR_ENABLE_REG_OFFSET 0x001C
+#define AXI2CFG_AXI_ERR_CLEAR_REG_OFFSET 0x0020
+#define AXI2CFG_AXI_ERR_MASK_REG_OFFSET 0x0024
+#define AXI2CFG_AXI_ERR_TEST_REG_OFFSET 0x0028
+#define AXI2CFG_AXI_ERR_RAW_REG_OFFSET 0x002C
+#define AXI2CFG_AXI_ERR_STATE_REG_OFFSET 0x0030
+#define AXI2CFG_CLOCK_GATING_REG_OFFSET 0x0048
+#define AXI2CFG_CONFIG_WRITE_REG_OFFSET 0x0100
+#define AXI2CFG_CONFIG_READ_REG_OFFSET 0x0200
+#define AXI2CFG_DMAC1_CONFIG_REG_OFFSET 0x0300
+
+#define AXI2CFG_SYSCFG_PA_RST_IDX 30
+#define AXI2CFG_SYSCFG_SD_ARM_GPIO_SEL_SZ 8
+#define AXI2CFG_SYSCFG_SD_ARM_GPIO_SEL_HI 23
+#define AXI2CFG_SYSCFG_SD_ARM_GPIO_SEL_LO 16
+#define AXI2CFG_SYSCFG_RW_EBI_CLK_DISABLE_IDX 15
+#define AXI2CFG_SYSCFG_RW_EXCVEC_EN_IDX 14
+#define AXI2CFG_SYSCFG_RW_RMII_EN_IDX 13
+#define AXI2CFG_SYSCFG_RW_REVMII_EN_IDX 12
+#define AXI2CFG_SYSCFG_SSI_EBI_SEL_SZ 4
+#define AXI2CFG_SYSCFG_SSI_EBI_SEL_HI 11
+#define AXI2CFG_SYSCFG_SSI_EBI_SEL_LO 8
+#define AXI2CFG_SYSCFG_FREQ_SYNTH_MUX_IDX 7
+#define AXI2CFG_SYSCFG_MASK_AXI_ERR_IDX 6
+#define AXI2CFG_SYSCFG_RW_REMAP_IDX 5
+#define AXI2CFG_SYSCFG_WDG_PAUSE_IDX 4
+#define AXI2CFG_SYSCFG_CP15DISABLE_IDX 3
+#define AXI2CFG_SYSCFG_DMAC1_CH7_IDX 2
+#define AXI2CFG_SYSCFG_BOOT_MODE_SZ 2
+#define AXI2CFG_SYSCFG_BOOT_MODE_HI 1
+#define AXI2CFG_SYSCFG_BOOT_MODE_LO 0
+
+#define AXI2CFG_SYSCFG_PA_RST_MASK \
+ (1 << AXI2CFG_SYSCFG_PA_RST_IDX)
+#define AXI2CFG_SYSCFG_SD_ARM_GPIO_MASK \
+ (((1 << AXI2CFG_SYSCFG_SD_ARM_GPIO_SEL_SZ) - 1) << \
+ AXI2CFG_SYSCFG_SD_ARM_GPIO_SEL_LO)
+#define AXI2CFG_SYSCFG_RW_EXCVEC_EN_MASK \
+ (1 << AXI2CFG_SYSCFG_RW_EXCVEC_EN_IDX)
+#define AXI2CFG_SYSCFG_RW_RMII_EN_MASK \
+ (1 << AXI2CFG_SYSCFG_RW_RMII_EN_IDX)
+#define AXI2CFG_SYSCFG_RW_REVMII_EN_MASK \
+ (1 << AXI2CFG_SYSCFG_RW_REVMII_EN_IDX)
+#define AXI2CFG_SYSCFG_SSI_EBI_SEL_MASK \
+ (((1 << AXI2CFG_SYSCFG_SSI_EBI_SEL_SZ) - 1) << \
+ AXI2CFG_SYSCFG_SSI_EBI_SEL_LO)
+#define AXI2CFG_SYSCFG_FREQ_SYNTH_MUX_MASK \
+ (1 << AXI2CFG_SYSCFG_FREQ_SYNTH_MUX_IDX)
+#define AXI2CFG_SYSCFG_MASK_AXI_ERR_MASK \
+ (1 << AXI2CFG_SYSCFG_MASK_AXI_ERR_IDX)
+#define AXI2CFG_SYSCFG_RW_REMAP_MASK \
+ (1 << AXI2CFG_SYSCFG_RW_REMAP_IDX)
+#define AXI2CFG_SYSCFG_WDG_PAUSE_MASK \
+ (1 << AXI2CFG_SYSCFG_WDG_PAUSE_IDX)
+#define AXI2CFG_SYSCFG_CP15DISABLE_MASK \
+ (1 << AXI2CFG_SYSCFG_CP15DISABLE_IDX)
+#define AXI2CFG_SYSCFG_DMAC1_CH7_MASK \
+ (1 << AXI2CFG_SYSCFG_DMAC1_CH7_IDX)
+#define AXI2CFG_SYSCFG_BOOT_MODE_MASK \
+ (((1 << AXI2CFG_SYSCFG_BOOT_MODE_SZ) - 1) << \
+ AXI2CFG_SYSCFG_BOOT_MODE_LO)
+
+#define AXI2CFG_AXI_RD_ERR_MASK 0x00000FFF
+#define AXI2CFG_AXI_WR_ERR_MASK 0x00FFF000
+#define AXI2CFG_AXI_ERR_MASK_NONE 0
+#define AXI2CFG_AXI_ERR_ENABLE_ALL 0x00FFFFFF
+
+#ifndef __ASSEMBLY__
+
+/*
+ * axi2cfg_init - initialize the AXI2CFG hardware.
+ */
+extern void axi2cfg_init(void);
+
+/*
+ * axi2cfg_readl - read a register in the axi2cfg.
+ *
+ * Returns the value of the register.
+ *
+ * @offs: the byte offset to read from.
+ */
+extern unsigned long axi2cfg_readl(unsigned long offs);
+
+/*
+ * axi2cfg_writel - write an axi2cfg AXI domain register.
+ *
+ * @val: the value to write.
+ * @offs: the byte offset to write to.
+ */
+extern void axi2cfg_writel(unsigned long val, unsigned long offs);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* PICOXCELL_AXI2CFG_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell/gpio.h b/arch/arm/mach-picoxcell/include/mach/picoxcell/gpio.h
new file mode 100644
index 0000000..f526271
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell/gpio.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef PICOXCELL_GPIO_H
+#define PICOXCELL_GPIO_H
+
+#define GPIO_SW_PORT_A_DR_REG_OFFSET 0x00
+#define GPIO_SW_PORT_A_DDR_REG_OFFSET 0x04
+#define GPIO_SW_PORT_A_CTL_REG_OFFSET 0x08
+#define GPIO_SW_PORT_B_DR_REG_OFFSET 0x0C
+#define GPIO_SW_PORT_B_DDR_REG_OFFSET 0x10
+#define GPIO_SW_PORT_B_CTL_REG_OFFSET 0x14
+#define GPIO_SW_PORT_C_DR_REG_OFFSET 0x18
+#define GPIO_SW_PORT_C_DDR_REG_OFFSET 0x1C
+#define GPIO_SW_PORT_C_CTL_REG_OFFSET 0x20
+#define GPIO_SW_PORT_D_DR_REG_OFFSET 0x24
+#define GPIO_SW_PORT_D_DDR_REG_OFFSET 0x28
+#define GPIO_SW_PORT_D_CTL_REG_OFFSET 0x2C
+
+#define GPIO_INT_EN_REG_OFFSET 0x30
+#define GPIO_INT_MASK_REG_OFFSET 0x34
+#define GPIO_INT_TYPE_LEVEL_REG_OFFSET 0x38
+#define GPIO_INT_POLARITY_REG_OFFSET 0x3c
+
+#define GPIO_INT_STATUS_REG_OFFSET 0x40
+
+#define GPIO_PORT_A_EOI_REG_OFFSET 0x4c
+#define GPIO_EXT_PORT_A_REG_OFFSET 0x50
+#define GPIO_EXT_PORT_B_REG_OFFSET 0x54
+#define GPIO_EXT_PORT_C_REG_OFFSET 0x58
+#define GPIO_EXT_PORT_D_REG_OFFSET 0x5C
+
+#endif /* PICOXCELL_GPIO_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell/picoxcell.h b/arch/arm/mach-picoxcell/include/mach/picoxcell/picoxcell.h
new file mode 100644
index 0000000..9691ec0
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell/picoxcell.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __PICOXCELL_H__
+#define __PICOXCELL_H__
+
+#define BOOT_ROM_BASE 0xFFFF0000
+#define BOOT_ROM_SIZE 0x400
+#define AXI2PICO_BUFFERS_BASE 0xC0000000
+#define AXI2PICO_BUFFERS_SIZE 0x00010000
+#define PICOXCELL_PERIPH_BASE 0x80000000
+#define PICOXCELL_PERIPH_LENGTH 0x00400000
+#define PICOXCELL_MEMIF_BASE 0x80000000
+#define PICOXCELL_EBI_BASE 0x80010000
+#define PICOXCELL_EMAC_BASE 0x80030000
+#define PICOXCELL_DMAC1_BASE 0x80040000
+#define PICOXCELL_DMAC2_BASE 0x80050000
+#define PICOXCELL_VIC0_BASE 0x80060000
+#define PICOXCELL_VIC1_BASE 0x80064000
+#define PICOXCELL_TZIC_BASE 0x80068000
+#define PICOXCELL_TZPC_BASE 0x80070000
+#define PICOXCELL_FUSE_BASE 0x80080000
+#define PICOXCELL_SSI_BASE 0x80090000
+#define PICOXCELL_AXI2CFG_BASE 0x800A0000
+#define PICOXCELL_IPSEC_BASE 0x80100000
+#define PICOXCELL_SRTP_BASE 0x80140000
+#define PICOXCELL_CIPHER_BASE 0x80180000
+#define PICOXCELL_RTCLK_BASE 0x80200000
+#define PICOXCELL_TIMER_BASE 0x80210000
+#define PICOXCELL_GPIO_BASE 0x80220000
+#define PICOXCELL_UART1_BASE 0x80230000
+#define PICOXCELL_UART2_BASE 0x80240000
+#define PICOXCELL_WDOG_BASE 0x80250000
+#define PC3X3_RNG_BASE 0x800B0000
+#define PC3X3_TIMER2_BASE 0x80260000
+#define PC3X3_OTP_BASE 0xFFFF8000
+
+#define EBI_CS0_BASE 0x40000000
+#define EBI_CS1_BASE 0x48000000
+#define EBI_CS2_BASE 0x50000000
+#define EBI_CS3_BASE 0x58000000
+
+#define SRAM_BASE 0x20000000
+#define SRAM_START 0x20000000
+#define SRAM_SIZE 0x00020000
+#define SRAM_VIRT 0xFE400000
+
+#endif /* __PICOXCELL_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell/timer.h b/arch/arm/mach-picoxcell/include/mach/picoxcell/timer.h
new file mode 100644
index 0000000..8d67c42
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell/timer.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef PICOXCELL_TIMER_H
+#define PICOXCELL_TIMER_H
+
+/* The spacing between individual timers. */
+#define TIMER_SPACING 0x14
+
+#define TIMER_LOAD_COUNT_REG_OFFSET 0x00
+#define TIMER_CONTROL_REG_OFFSET 0x08
+#define TIMER_EOI_REG_OFFSET 0x0c
+
+#define TIMERS_EOI_REG_OFFSET 0xa4
+
+#define TIMER_ENABLE 0x00000001
+#define TIMER_MODE 0x00000002
+#define TIMER_INTERRUPT_MASK 0x00000004
+
+#define RTCLK_CCV_REG_OFFSET 0x00
+#define RTCLK_SET_REG_OFFSET 0x08
+
+#endif /* PICOXCELL_TIMER_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell/wdog.h b/arch/arm/mach-picoxcell/include/mach/picoxcell/wdog.h
new file mode 100644
index 0000000..727780c
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell/wdog.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef PICOXCELL_WDOG_H
+#define PICOXCELL_WDOG_H
+
+#define WDOG_CONTROL_REG_OFFSET 0x00
+#define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
+#define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
+#define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
+#define WDOG_INT_STATUS_REG_OFFSET 0x10
+#define WDOG_CLEAR_REG_OFFSET 0x14
+
+#define WDOG_CONTROL_REG_RESET 0x00000016
+#define WDOG_TIMEOUT_RANGE_REG_RESET 0x0000000c
+#define WDOG_CURRENT_COUNT_REG_RESET 0x0fffffff
+#define WDOG_COUNTER_RESTART_REG_RESET 0x00000000
+#define WDOG_INT_STATUS_REG_RESET 0x00000000
+#define WDOG_CLEAR_REG_RESET 0x00000000
+
+#define WDOGCONTROLREGWDT_ENIDX 0
+#define WDOGCONTROLREGRMODIDX 1
+#define WDOGCONTROLREGRPLIDX 2
+
+#define WDOG_CONTROL_REG_WDT_EN_MASK (1 << WDOGCONTROLREGWDT_ENIDX)
+#define WDOG_CONTROL_REG_RMOD_MASK (1 << WDOGCONTROLREGRMODIDX)
+#define WDOG_CONTROL_REG_RPL_MASK (0x7 << WDOGCONTROLREGRPLIDX)
+
+#endif /* PICOXCELL_WDOG_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/platform.h b/arch/arm/mach-picoxcell/include/mach/platform.h
new file mode 100644
index 0000000..97697c0
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/platform.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ARCH_PICOXCELL_PLATFORM_H
+#define __ARCH_PICOXCELL_PLATFORM_H
+
+/* Physical address of the Flash in the ARM sub-system memory map */
+#define PICOXCELL_FLASH_BASE 0x40000000
+
+/* The clock frequency for the UARTs */
+#define PICOXCELL_BASE_BAUD 3686400 /* 3.6864 MHz */
+
+#endif /* __ARCH_PICOXCELL_PLATFORM_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/system.h b/arch/arm/mach-picoxcell/include/mach/system.h
new file mode 100644
index 0000000..b74cb7b
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/system.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/io.h>
+#include <mach/picoxcell/picoxcell.h>
+#include <mach/picoxcell/wdog.h>
+
+static inline void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks
+ */
+ cpu_do_idle();
+}
+
+static inline void arch_reset(int mode, const char *cmd)
+{
+ /*
+ * Set the watchdog to expire as soon as possible and reset the
+ * system.
+ */
+ __raw_writel(WDOG_CONTROL_REG_WDT_EN_MASK,
+ IO_ADDRESS(PICOXCELL_WDOG_BASE + WDOG_CONTROL_REG_OFFSET));
+ __raw_writel(0, IO_ADDRESS(PICOXCELL_WDOG_BASE +
+ WDOG_TIMEOUT_RANGE_REG_OFFSET));
+
+ /* Give it chance to reset. */
+ mdelay(500);
+
+ pr_crit("watchdog reset failed - entering infinite loop\n");
+}
+
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/timex.h b/arch/arm/mach-picoxcell/include/mach/timex.h
new file mode 100644
index 0000000..bf0fee6
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/timex.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __TIMEX_H__
+#define __TIMEX_H__
+
+#include <mach/platform.h>
+
+#define CLOCK_TICK_RATE 200000000 /* 200MHz */
+
+#endif /* __TIMEX_H__ */
+
diff --git a/arch/arm/mach-picoxcell/include/mach/uncompress.h b/arch/arm/mach-picoxcell/include/mach/uncompress.h
new file mode 100644
index 0000000..3b6c4a5a
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/uncompress.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/io.h>
+#include <linux/serial_reg.h>
+
+#include <asm/processor.h>
+
+#include <mach/hardware.h>
+
+#define UART_SHIFT 2
+
+static inline void putc(int c)
+{
+ void __iomem *uart = (void __iomem *)(PICOXCELL_UART1_BASE);
+
+ while (!(__raw_readl(uart + (UART_LSR << UART_SHIFT)) & UART_LSR_THRE))
+ barrier();
+ __raw_writel(c & 0xFF, uart + (UART_TX << UART_SHIFT));
+}
+
+static inline void flush(void)
+{
+}
+
+static inline void arch_decomp_setup(void)
+{
+ void __iomem *uart = (void __iomem *)(PICOXCELL_UART1_BASE);
+
+ /* Reset and enable the FIFO's. */
+ __raw_writel(UART_FCR_ENABLE_FIFO, uart + (UART_FCR << UART_SHIFT));
+
+ /* Wait for the FIFO's to be enabled. */
+ while (!(__raw_readl(uart + (UART_FCR << UART_SHIFT)) &
+ UART_FCR_TRIGGER_14))
+ cpu_relax();
+ /* Enable divisor access, set length to 8 bits. */
+ __raw_writel(UART_LCR_DLAB | UART_LCR_WLEN8,
+ uart + (UART_LCR << UART_SHIFT));
+ /* Set for 115200 baud. */
+ __raw_writel(0x2, uart + (UART_DLL << UART_SHIFT));
+ __raw_writel(0x0, uart + (UART_DLM << UART_SHIFT));
+ __raw_writel(UART_LCR_WLEN8, uart + (UART_LCR << UART_SHIFT));
+}
+
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-picoxcell/include/mach/vmalloc.h b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
new file mode 100644
index 0000000..09a7f75
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define VMALLOC_END 0xFE000000UL
diff --git a/arch/arm/mach-picoxcell/io.c b/arch/arm/mach-picoxcell/io.c
new file mode 100644
index 0000000..5c61dbe
--- /dev/null
+++ b/arch/arm/mach-picoxcell/io.c
@@ -0,0 +1,49 @@
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+
+static struct map_desc __initdata picoxcell_io_desc[] = {
+ {
+ .virtual = PHYS_TO_IO(PICOXCELL_PERIPH_BASE),
+ .pfn = __phys_to_pfn(PICOXCELL_PERIPH_BASE),
+ .length = PICOXCELL_PERIPH_LENGTH,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = SRAM_VIRT,
+ .pfn = __phys_to_pfn(SRAM_BASE),
+ .length = SRAM_SIZE,
+ .type = MT_MEMORY,
+ },
+};
+
+void __init picoxcell_map_io(void)
+{
+ iotable_init(picoxcell_io_desc, ARRAY_SIZE(picoxcell_io_desc));
+}
+
+/*
+ * Intercept ioremap() requests for addresses in our fixed mapping regions.
+ */
+void __iomem *picoxcell_ioremap(unsigned long p, size_t size, unsigned int type)
+{
+ if (p >= PICOXCELL_PERIPH_BASE &&
+ p < PICOXCELL_PERIPH_BASE + PICOXCELL_PERIPH_LENGTH)
+ return IO_ADDRESS(p);
+
+ return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
+}
+EXPORT_SYMBOL(picoxcell_ioremap);
+
+void picoxcell_iounmap(volatile void __iomem *addr)
+{
+ unsigned long virt = (unsigned long)addr;
+
+ if (virt >= VMALLOC_START && virt < VMALLOC_END)
+ __iounmap(addr);
+}
+EXPORT_SYMBOL(picoxcell_iounmap);
diff --git a/arch/arm/mach-picoxcell/picoxcell_core.c b/arch/arm/mach-picoxcell/picoxcell_core.c
new file mode 100644
index 0000000..a0db3fd
--- /dev/null
+++ b/arch/arm/mach-picoxcell/picoxcell_core.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support@picochip.com
+ */
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/hardware/vic.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+
+#include "picoxcell_core.h"
+#include "soc.h"
+
+static const struct picoxcell_timer picoxcell_timers[] = {
+ {
+ .name = "timer0",
+ .type = TIMER_TYPE_TIMER,
+ .base = PICOXCELL_TIMER_BASE + 0 * TIMER_SPACING,
+ .irq = IRQ_TIMER0,
+ },
+ {
+ .name = "timer1",
+ .type = TIMER_TYPE_TIMER,
+ .base = PICOXCELL_TIMER_BASE + 1 * TIMER_SPACING,
+ .irq = IRQ_TIMER1,
+ },
+ {
+ .name = "rtc",
+ .type = TIMER_TYPE_RTC,
+ .base = PICOXCELL_RTCLK_BASE,
+ .irq = IRQ_RTC,
+ },
+};
+
+static struct picoxcell_soc generic_soc = {
+ .timers = picoxcell_timers,
+ .nr_timers = ARRAY_SIZE(picoxcell_timers),
+};
+
+struct picoxcell_soc *picoxcell_get_soc(void)
+{
+ return &generic_soc;
+}
+
+void __init picoxcell_init_irq(void)
+{
+ u32 vic0_resume_sources =
+ (1 << (IRQ_AXI2PICO8 & 31)) |
+ (1 << (IRQ_EMAC & 31)) |
+ (1 << (IRQ_WDG & 31));
+
+ vic_init(IO_ADDRESS(PICOXCELL_VIC0_BASE), 32, 0xFFFFFFFE,
+ vic0_resume_sources);
+ vic_init(IO_ADDRESS(PICOXCELL_VIC1_BASE), 0, 0x7FF, 0);
+}
+
+static const char *picoxcell_get_partname(void)
+{
+ unsigned long dev_id = axi2cfg_readl(AXI2CFG_DEVICE_ID_REG_OFFSET);
+ const char *part = "<unknown>";
+
+ if (dev_id == 0x8003)
+ part = "pc302";
+ else if (dev_id == 0x8007)
+ part = "pc312";
+ else if (dev_id == 0x20)
+ part = "pc313";
+ else if (dev_id == 0x21)
+ part = "pc323";
+ else if (dev_id == 0x22)
+ part = "pc333";
+
+ return part;
+}
+
+static inline unsigned long picoxcell_get_revision(void)
+{
+ return axi2cfg_readl(AXI2CFG_REVISION_ID_REG_OFFSET);
+}
+
+static void report_chipinfo(void)
+{
+ const char *part = picoxcell_get_partname();
+ unsigned long revision = picoxcell_get_revision();
+
+ pr_info("Picochip picoXcell device: %s revision %lu\n", part, revision);
+}
+
+void __init picoxcell_init_early(void)
+{
+ axi2cfg_init();
+}
+
+void __init picoxcell_core_init(void)
+{
+ report_chipinfo();
+}
diff --git a/arch/arm/mach-picoxcell/picoxcell_core.h b/arch/arm/mach-picoxcell/picoxcell_core.h
new file mode 100644
index 0000000..299c512
--- /dev/null
+++ b/arch/arm/mach-picoxcell/picoxcell_core.h
@@ -0,0 +1,22 @@
+/*
+ * linux/arch/arm/mach-picoxcell/picoxcell_core.h
+ *
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support at picochip.com
+ */
+#ifndef __ASM_ARCH_PICOXCELL_CORE_H__
+#define __ASM_ARCH_PICOXCELL_CORE_H__
+
+struct picoxcell_soc;
+
+extern void picoxcell_init_early(void);
+extern void picoxcell_core_init(void);
+extern void picoxcell_init_irq(void);
+extern void picoxcell_map_io(void);
+
+#endif /* __ASM_ARCH_PICOXCELL_CORE_H__ */
diff --git a/arch/arm/mach-picoxcell/soc.h b/arch/arm/mach-picoxcell/soc.h
new file mode 100644
index 0000000..1422216
--- /dev/null
+++ b/arch/arm/mach-picoxcell/soc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support at picochip.com
+ */
+#ifndef __PICOXCELL_SOC_H__
+#define __PICOXCELL_SOC_H__
+
+enum timer_type {
+ TIMER_TYPE_RTC,
+ TIMER_TYPE_TIMER,
+};
+
+struct picoxcell_timer {
+ const char *name;
+ enum timer_type type;
+ unsigned long base;
+ int irq;
+};
+
+struct picoxcell_soc {
+ const struct picoxcell_timer *timers;
+ int nr_timers;
+};
+
+extern struct picoxcell_soc *picoxcell_get_soc(void);
+
+#endif /* __PICOXCELL_SOC_H__ */
--
1.7.4
^ permalink raw reply related
* [PATCHv5 2/4] picoxcell: add support for the system timers
From: Jamie Iles @ 2011-02-18 10:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298023231-2747-1-git-send-email-jamie@jamieiles.com>
The picoXcell devices have 4 timers capable of generating interrupts
when they reach a predefined value and restarting and a freerunning RTC.
Use one of the interrupt capable timers as the clockevent_device and the
RTC for the clocksource and sched_clock().
v2:
- use clocksource_register_hz() and
clockevents_calc_mult_shift() rather than specifying .mult and
.shift.
v3:
- Incorporate feedback from RMK.
- Don't emulate oneshot mode in the timers, let the generic
clockevents layer do it.
- Provide a better sched_clock() based on plat-nomadik's.
- Convert to __raw_ io accessors.
v4:
- Use the fixed_sched_clock helpers for sched_clock()
implementation as provided by RMK and remove redunant use of
__init.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
---
arch/arm/mach-picoxcell/Makefile | 3 +-
arch/arm/mach-picoxcell/picoxcell_core.c | 1 +
arch/arm/mach-picoxcell/picoxcell_core.h | 3 +
arch/arm/mach-picoxcell/time.c | 222 ++++++++++++++++++++++++++++++
4 files changed, 228 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-picoxcell/time.c
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
index 6afe388..493ec0e 100644
--- a/arch/arm/mach-picoxcell/Makefile
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -1 +1,2 @@
-obj-y := picoxcell_core.o io.o axi2cfg.o
+obj-y := picoxcell_core.o io.o axi2cfg.o \
+ time.o
diff --git a/arch/arm/mach-picoxcell/picoxcell_core.c b/arch/arm/mach-picoxcell/picoxcell_core.c
index a0db3fd..a54d981 100644
--- a/arch/arm/mach-picoxcell/picoxcell_core.c
+++ b/arch/arm/mach-picoxcell/picoxcell_core.c
@@ -97,6 +97,7 @@ static void report_chipinfo(void)
void __init picoxcell_init_early(void)
{
axi2cfg_init();
+ picoxcell_sched_clock_init();
}
void __init picoxcell_core_init(void)
diff --git a/arch/arm/mach-picoxcell/picoxcell_core.h b/arch/arm/mach-picoxcell/picoxcell_core.h
index 299c512..50cf842 100644
--- a/arch/arm/mach-picoxcell/picoxcell_core.h
+++ b/arch/arm/mach-picoxcell/picoxcell_core.h
@@ -13,10 +13,13 @@
#define __ASM_ARCH_PICOXCELL_CORE_H__
struct picoxcell_soc;
+struct sys_timer;
extern void picoxcell_init_early(void);
extern void picoxcell_core_init(void);
extern void picoxcell_init_irq(void);
extern void picoxcell_map_io(void);
+extern struct sys_timer picoxcell_sys_timer;
+extern void picoxcell_sched_clock_init(void);
#endif /* __ASM_ARCH_PICOXCELL_CORE_H__ */
diff --git a/arch/arm/mach-picoxcell/time.c b/arch/arm/mach-picoxcell/time.c
new file mode 100644
index 0000000..66fe86d
--- /dev/null
+++ b/arch/arm/mach-picoxcell/time.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support at picochip.com
+ */
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/cnt32_to_63.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+
+#include <asm/mach/time.h>
+#include <asm/sched_clock.h>
+
+#include <mach/hardware.h>
+
+#include "picoxcell_core.h"
+#include "soc.h"
+
+enum timer_id {
+ TIMER_ID_CLOCKEVENT,
+ TIMER_ID_CLOCKSOURCE,
+ NR_TIMERS,
+};
+
+struct timer_instance {
+ void __iomem *base;
+ struct irqaction irqaction;
+};
+
+/*
+ * We expect to have 2 timers - a freerunning one for the clock source and a
+ * periodic/oneshot one for the clock_event_device.
+ */
+static struct timer_instance timers[NR_TIMERS];
+
+static void timer_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *clk)
+{
+ struct timer_instance *timer = &timers[TIMER_ID_CLOCKEVENT];
+ unsigned long load_count = DIV_ROUND_UP(CLOCK_TICK_RATE, HZ);
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ /*
+ * By default, use the kernel tick rate. The reload value can
+ * be changed with the timer_set_next_event() function.
+ */
+ __raw_writel(load_count,
+ timer->base + TIMER_LOAD_COUNT_REG_OFFSET);
+ __raw_writel(TIMER_ENABLE | TIMER_MODE,
+ timer->base + TIMER_CONTROL_REG_OFFSET);
+ break;
+
+ case CLOCK_EVT_MODE_ONESHOT:
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ default:
+ __raw_writel(0, timer->base + TIMER_CONTROL_REG_OFFSET);
+ break;
+ }
+}
+
+static int timer_set_next_event(unsigned long evt,
+ struct clock_event_device *clk)
+{
+ struct timer_instance *timer = &timers[TIMER_ID_CLOCKEVENT];
+
+ /* Disable the timer, write the new event then enable it. */
+ __raw_writel(0, timer->base + TIMER_CONTROL_REG_OFFSET);
+ __raw_writel(evt, timer->base + TIMER_LOAD_COUNT_REG_OFFSET);
+ __raw_writel(TIMER_ENABLE | TIMER_MODE,
+ timer->base + TIMER_CONTROL_REG_OFFSET);
+
+ return 0;
+}
+
+static struct clock_event_device clockevent_picoxcell = {
+ .features = CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_ONESHOT,
+ .set_next_event = timer_set_next_event,
+ .set_mode = timer_set_mode,
+};
+
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
+{
+ struct timer_instance *timer = &timers[TIMER_ID_CLOCKEVENT];
+
+ /* Clear the interrupt. */
+ __raw_readl(timer->base + TIMER_EOI_REG_OFFSET);
+
+ clockevent_picoxcell.event_handler(&clockevent_picoxcell);
+
+ return IRQ_HANDLED;
+}
+
+#define PICOXCELL_MIN_RANGE 4
+
+static void picoxcell_clockevent_init(struct picoxcell_soc *soc)
+{
+ struct timer_instance *inst = &timers[TIMER_ID_CLOCKEVENT];
+ const struct picoxcell_timer *timer = NULL;
+ int i;
+
+ for (i = 0; i < soc->nr_timers; ++i)
+ if (soc->timers[i].type == TIMER_TYPE_TIMER) {
+ timer = &soc->timers[i];
+ break;
+ }
+
+ BUG_ON(!timer);
+
+ /* Configure the interrupt for this timer. */
+ inst->irqaction.name = timer->name;
+ inst->irqaction.handler = timer_interrupt;
+ inst->irqaction.flags = IRQF_DISABLED | IRQF_TIMER;
+ inst->base = ioremap(timer->base, TIMER_SPACING);
+
+ clockevent_picoxcell.name = timer->name;
+ clockevents_calc_mult_shift(&clockevent_picoxcell, CLOCK_TICK_RATE,
+ PICOXCELL_MIN_RANGE);
+ clockevent_picoxcell.max_delta_ns =
+ clockevent_delta2ns(0xfffffffe, &clockevent_picoxcell);
+ clockevent_picoxcell.min_delta_ns = 50000;
+ clockevent_picoxcell.cpumask = cpumask_of(0);
+
+ /* Start with the timer disabled and the interrupt enabled. */
+ __raw_writel(0, inst->base + TIMER_CONTROL_REG_OFFSET);
+ setup_irq(timer->irq, &inst->irqaction);
+
+ clockevents_register_device(&clockevent_picoxcell);
+}
+
+static cycle_t picoxcell_rtc_get_cycles(struct clocksource *cs)
+{
+ struct timer_instance *inst = &timers[TIMER_ID_CLOCKSOURCE];
+
+ return __raw_readl(inst->base + RTCLK_CCV_REG_OFFSET);
+}
+
+static struct clocksource clocksource_picoxcell = {
+ .name = "rtc",
+ .rating = 300,
+ .read = picoxcell_rtc_get_cycles,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void picoxcell_clocksource_init(struct picoxcell_soc *soc)
+{
+ const struct picoxcell_timer *timer = NULL;
+ int i;
+
+ for (i = 0; i < soc->nr_timers; ++i)
+ if (soc->timers[i].type == TIMER_TYPE_RTC) {
+ timer = &soc->timers[i];
+ break;
+ }
+
+ BUG_ON(!timer);
+
+ timers[TIMER_ID_CLOCKSOURCE].base = ioremap(timer->base, SZ_4K);
+
+ /* The RTC is always running. We don't need to do any initialization. */
+ clocksource_picoxcell.read = picoxcell_rtc_get_cycles;
+ clocksource_register_hz(&clocksource_picoxcell, CLOCK_TICK_RATE);
+}
+
+static void __init picoxcell_timer_init(void)
+{
+ struct picoxcell_soc *soc = picoxcell_get_soc();
+
+ picoxcell_clocksource_init(soc);
+ picoxcell_clockevent_init(soc);
+}
+
+struct sys_timer picoxcell_sys_timer = {
+ .init = picoxcell_timer_init,
+};
+
+/*
+ * picoxcell's sched_clock implementation. It has a resolution of 5ns
+ * (200MHz).
+ */
+static DEFINE_CLOCK_DATA(cd);
+
+/*
+ * Constants generated by:
+ * clocks_calc_mult_shift(m, s, 200000000, NSEC_PER_SEC, 0);
+ */
+#define SC_MULT 2684354560LU
+#define SC_SHIFT 29
+
+unsigned long long notrace sched_clock(void)
+{
+ u32 cyc = __raw_readl(IO_ADDRESS(PICOXCELL_RTCLK_BASE) +
+ RTCLK_CCV_REG_OFFSET);
+ return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
+}
+
+static void notrace picoxcell_update_sched_clock(void)
+{
+ u32 cyc = __raw_readl(IO_ADDRESS(PICOXCELL_RTCLK_BASE) +
+ RTCLK_CCV_REG_OFFSET);
+ update_sched_clock(&cd, cyc, (u32)~0);
+}
+
+void __init picoxcell_sched_clock_init(void)
+{
+ /*
+ * Reset the RTC. We don't know how long the RTC has been running for
+ * in the bootloader.
+ */
+ __raw_writel(0, IO_ADDRESS(PICOXCELL_RTCLK_BASE +
+ RTCLK_SET_REG_OFFSET));
+ init_fixed_sched_clock(&cd, picoxcell_update_sched_clock, 32,
+ CLOCK_TICK_RATE, SC_MULT, SC_SHIFT);
+}
--
1.7.4
^ permalink raw reply related
* [PATCHv5 3/4] picoxcell: add common SoC devices
From: Jamie Iles @ 2011-02-18 10:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298023231-2747-1-git-send-email-jamie@jamieiles.com>
Add the devices common to all picoXcell variants (UART and PMU). Other
peripherals such as DMA, SPI, fuses and EMAC will be added later
with driver support.
v3:
- move device registration to an arch_initcall
- mark common_devices with __initdata
v2: - split the UARTs into two separate platform devices and use
PLAT8250_* as the IDs
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
---
arch/arm/mach-picoxcell/Makefile | 3 +-
arch/arm/mach-picoxcell/devices.c | 122 +++++++++++++++++++++++++++++++++++++
2 files changed, 124 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-picoxcell/devices.c
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
index 493ec0e..3cace37 100644
--- a/arch/arm/mach-picoxcell/Makefile
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -1,2 +1,3 @@
obj-y := picoxcell_core.o io.o axi2cfg.o \
- time.o
+ time.o \
+ devices.o
diff --git a/arch/arm/mach-picoxcell/devices.c b/arch/arm/mach-picoxcell/devices.c
new file mode 100644
index 0000000..505de91
--- /dev/null
+++ b/arch/arm/mach-picoxcell/devices.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support at picochip.com
+ */
+#include <linux/serial_8250.h>
+#include <linux/serial_reg.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+#include <asm/pmu.h>
+
+#include "picoxcell_core.h"
+#include "soc.h"
+
+#define UART_USR_REG_OFFSET 0x7C
+static struct plat_serial8250_port serial1_platform_data[] = {
+ {
+ .membase = IO_ADDRESS(PICOXCELL_UART1_BASE),
+ .mapbase = PICOXCELL_UART1_BASE,
+ .irq = IRQ_UART1,
+ .flags = UPF_BOOT_AUTOCONF,
+ .iotype = UPIO_DWAPB32,
+ .regshift = 2,
+ .uartclk = PICOXCELL_BASE_BAUD,
+ .private_data = (void *)(PHYS_TO_IO(PICOXCELL_UART1_BASE +
+ UART_USR_REG_OFFSET)),
+ },
+ {},
+};
+
+static struct resource serial1_resources[] = {
+ {
+ .start = PICOXCELL_UART1_BASE,
+ .end = PICOXCELL_UART1_BASE + 0xFFFF,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_UART1,
+ .end = IRQ_UART2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device serial1_device = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM1,
+ .dev.platform_data = serial1_platform_data,
+ .resource = serial1_resources,
+ .num_resources = ARRAY_SIZE(serial1_resources),
+};
+
+static struct plat_serial8250_port serial2_platform_data[] = {
+ {
+ .membase = IO_ADDRESS(PICOXCELL_UART2_BASE),
+ .mapbase = PICOXCELL_UART2_BASE,
+ .irq = IRQ_UART2,
+ .flags = UPF_BOOT_AUTOCONF,
+ .iotype = UPIO_DWAPB32,
+ .regshift = 2,
+ .uartclk = PICOXCELL_BASE_BAUD,
+ .private_data = (void *)(PHYS_TO_IO(PICOXCELL_UART2_BASE +
+ UART_USR_REG_OFFSET)),
+ },
+ {},
+};
+
+static struct resource serial2_resources[] = {
+ {
+ .start = PICOXCELL_UART2_BASE,
+ .end = PICOXCELL_UART2_BASE + 0xFFFF,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_UART2,
+ .end = IRQ_UART2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device serial2_device = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM2,
+ .dev.platform_data = serial2_platform_data,
+ .resource = serial2_resources,
+ .num_resources = ARRAY_SIZE(serial2_resources),
+};
+
+static struct resource pmu_resource = {
+ .start = IRQ_NPMUIRQ,
+ .end = IRQ_NPMUIRQ,
+ .flags = IORESOURCE_IRQ,
+};
+
+static struct platform_device pmu_device = {
+ .name = "arm-pmu",
+ .id = ARM_PMU_DEVICE_CPU,
+ .num_resources = 1,
+ .resource = &pmu_resource,
+};
+
+static struct __initdata platform_device *common_devices[] __initdata = {
+ &serial1_device,
+ &serial2_device,
+ &pmu_device,
+};
+
+static int __init picoxcell_add_devices(void)
+{
+ platform_add_devices(common_devices, ARRAY_SIZE(common_devices));
+
+ return 0;
+}
+arch_initcall(picoxcell_add_devices);
--
1.7.4
^ permalink raw reply related
* [PATCHv5 4/4] picoxcell: add support for the PC7302 development board
From: Jamie Iles @ 2011-02-18 10:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298023231-2747-1-git-send-email-jamie@jamieiles.com>
The PC7302 development board is capable of taking both PC3X2 and PC3X3
devices and features NOR flash, NAND flash, SPI NOR flash a serial
console, 100Mb Ethernet and a number of picoArray peripherals.
This patch provides initial support for running on the PC7302 board.
v4:
- reduce to the bare minimum for NOR flash booting.
v3:
- remove redundant __init declarations.
v2:
- multiplex the NAND CLE pin by pad name.
- convert to __raw_ io accessors.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
---
arch/arm/mach-picoxcell/Kconfig | 8 +++
arch/arm/mach-picoxcell/Makefile | 1 +
arch/arm/mach-picoxcell/board_pc7302.c | 109 ++++++++++++++++++++++++++++++++
3 files changed, 118 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-picoxcell/board_pc7302.c
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
index 3daba53..0c1f78d 100644
--- a/arch/arm/mach-picoxcell/Kconfig
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -1,4 +1,12 @@
menu "PICOXCELL platform type"
depends on ARCH_PICOXCELL
+config BOARD_PC7302
+ bool "Support PC7302 Board"
+ default y
+ help
+ Include support for the picoChip PC7302 platform. This platform is
+ can take any of the PC3X2 or PC3X3 devices and includes SPI NOR
+ flash, parallel NOR flash and NAND flash.
+
endmenu
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
index 3cace37..fc4e735 100644
--- a/arch/arm/mach-picoxcell/Makefile
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -1,3 +1,4 @@
obj-y := picoxcell_core.o io.o axi2cfg.o \
time.o \
devices.o
+obj-$(CONFIG_BOARD_PC7302) += board_pc7302.o
diff --git a/arch/arm/mach-picoxcell/board_pc7302.c b/arch/arm/mach-picoxcell/board_pc7302.c
new file mode 100644
index 0000000..6d2b5e0
--- /dev/null
+++ b/arch/arm/mach-picoxcell/board_pc7302.c
@@ -0,0 +1,109 @@
+/*
+ * linux/arch/arm/mach-picoxcell/board_pc7302.c
+ *
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support at picochip.com
+ */
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+
+#include <mach/hardware.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include "picoxcell_core.h"
+
+static long pc7302_panic_blink(int state)
+{
+ __raw_writel(state ? 0xFF : 0, IO_ADDRESS(PICOXCELL_GPIO_BASE +
+ GPIO_SW_PORT_C_DR_REG_OFFSET));
+ return 0;
+}
+
+static void pc7302_panic_init(void)
+{
+ /*
+ * We have a BOOT_ERROR pin on PC7302. Reuse that for signalling when
+ * the kernel panics. There is only 1 bit wired up to port C but it
+ * won't hurt to configure all of them.
+ */
+ __raw_writel(0xF, IO_ADDRESS(PICOXCELL_GPIO_BASE +
+ GPIO_SW_PORT_C_DDR_REG_OFFSET));
+ __raw_writel(0x0, IO_ADDRESS(PICOXCELL_GPIO_BASE +
+ GPIO_SW_PORT_C_CTL_REG_OFFSET));
+
+ panic_blink = pc7302_panic_blink;
+}
+
+static struct mtd_partition pc7302_nor_partitions[] = {
+ {
+ .name = "Boot",
+ .size = SZ_128K,
+ .offset = 0,
+ },
+ {
+ .name = "Boot Environment",
+ .size = SZ_128K,
+ .offset = MTDPART_OFS_APPEND,
+ },
+ {
+ .name = "Kernel",
+ .size = SZ_4M,
+ .offset = MTDPART_OFS_APPEND,
+ },
+ {
+ .name = "Application",
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND,
+ },
+};
+
+static struct physmap_flash_data pc7302_nor_flash_data = {
+ .width = 1,
+ .parts = pc7302_nor_partitions,
+ .nr_parts = ARRAY_SIZE(pc7302_nor_partitions)
+};
+
+static struct resource pc7302_nor_resource = {
+ .start = PICOXCELL_FLASH_BASE,
+ .end = PICOXCELL_FLASH_BASE + SZ_128M - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device pc7302_nor = {
+ .name = "physmap-flash",
+ .id = -1,
+ .dev.platform_data = &pc7302_nor_flash_data,
+ .resource = &pc7302_nor_resource,
+ .num_resources = 1,
+};
+
+static void pc7302_init_nor(void)
+{
+ platform_device_register(&pc7302_nor);
+}
+
+static void __init pc7302_init(void)
+{
+ picoxcell_core_init();
+ pc7302_init_nor();
+ pc7302_panic_init();
+}
+
+MACHINE_START(PC7302, "PC7302")
+ .map_io = picoxcell_map_io,
+ .init_irq = picoxcell_init_irq,
+ .init_early = picoxcell_init_early,
+ .timer = &picoxcell_sys_timer,
+ .init_machine = pc7302_init,
+MACHINE_END
--
1.7.4
^ permalink raw reply related
* [PATCH RESEND 3/4] ARM: imx53_loco: add i2c device support
From: Sascha Hauer @ 2011-02-18 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110218085940.GA2086@b20223-02.ap.freescale.net>
On Fri, Feb 18, 2011 at 04:59:41PM +0800, Richard Zhao wrote:
> Hi Uwe,
>
> On Fri, Feb 18, 2011 at 09:45:33AM +0100, Uwe Kleine-K?nig wrote:
> > On Fri, Feb 18, 2011 at 12:36:16PM +0800, Richard Zhao wrote:
> > > Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
> > >
> > > diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
> > > index 10b6008..abea297 100644
> > > --- a/arch/arm/mach-mx5/Kconfig
> > > +++ b/arch/arm/mach-mx5/Kconfig
> > > @@ -146,6 +146,7 @@ config MACH_MX53_LOCO
> > > bool "Support MX53 LOCO platforms"
> > > select SOC_IMX53
> > > select IMX_HAVE_PLATFORM_IMX_UART
> > > + select IMX_HAVE_PLATFORM_IMX_I2C
> > please keep these sorted alphabetically
> ok. I will move it up by one line.
Fixed while applying.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH RESEND 2.6.39 0/3] ARM: simpad: Add support for GPIO attached hardware
From: Jochen Friedrich @ 2011-02-18 10:02 UTC (permalink / raw)
To: linux-arm-kernel
This series enables GPIO API on UCB1x00 and implements the GPIO
API on the CS3 latch. The third patch finally registers platform
devices for the GPIO attached LED, buttons and I2C bus.
ARM: simpad: Add ucb1x00 GPIO definitions and register GPIO
ARM: simpad: Cleanup CS3 accessors and add GPIO API
ARM: simpad: add GPIO based device definitions
^ permalink raw reply
* [PATCH RESEND 2.6.39 1/3] ARM: simpad: Add ucb1x00 GPIO definitions and register GPIO
From: Jochen Friedrich @ 2011-02-18 10:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298023368-27090-1-git-send-email-jochen@scram.de>
Add ucb1x00 GPIO definitions to simpad.h and add gpio_base
to ucb1x00 platform device so the pins are available using
the GPIO API.
Signed-off-by: Jochen Friedrich <jochen@scram.de>
---
arch/arm/mach-sa1100/include/mach/simpad.h | 13 +++++++++++++
arch/arm/mach-sa1100/simpad.c | 1 +
2 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h
index 9296c45..231550d 100644
--- a/arch/arm/mach-sa1100/include/mach/simpad.h
+++ b/arch/arm/mach-sa1100/include/mach/simpad.h
@@ -48,6 +48,19 @@
#define GPIO_SMART_CARD GPIO_GPIO10
#define IRQ_GPIO_SMARD_CARD IRQ_GPIO10
+/*--- ucb1x00 GPIO ---*/
+#define SIMPAD_UCB1X00_GPIO_BASE (GPIO_MAX + 1)
+#define SIMPAD_UCB1X00_GPIO_PROG1 (SIMPAD_UCB1X00_GPIO_BASE)
+#define SIMPAD_UCB1X00_GPIO_PROG2 (SIMPAD_UCB1X00_GPIO_BASE + 1)
+#define SIMPAD_UCB1X00_GPIO_UP (SIMPAD_UCB1X00_GPIO_BASE + 2)
+#define SIMPAD_UCB1X00_GPIO_DOWN (SIMPAD_UCB1X00_GPIO_BASE + 3)
+#define SIMPAD_UCB1X00_GPIO_LEFT (SIMPAD_UCB1X00_GPIO_BASE + 4)
+#define SIMPAD_UCB1X00_GPIO_RIGHT (SIMPAD_UCB1X00_GPIO_BASE + 5)
+#define SIMPAD_UCB1X00_GPIO_6 (SIMPAD_UCB1X00_GPIO_BASE + 6)
+#define SIMPAD_UCB1X00_GPIO_7 (SIMPAD_UCB1X00_GPIO_BASE + 7)
+#define SIMPAD_UCB1X00_GPIO_HEADSET (SIMPAD_UCB1X00_GPIO_BASE + 8)
+#define SIMPAD_UCB1X00_GPIO_SPEAKER (SIMPAD_UCB1X00_GPIO_BASE + 9)
+
// CS3 Latch is write only, a shadow is necessary
#define CS3BUSTYPE unsigned volatile long
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index cfb7607..718b802 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -132,6 +132,7 @@ static struct resource simpad_flash_resources [] = {
static struct mcp_plat_data simpad_mcp_data = {
.mccr0 = MCCR0_ADM,
.sclk_rate = 11981000,
+ .gpio_base = SIMPAD_UCB1X00_GPIO_BASE,
};
--
1.7.2.3
^ permalink raw reply related
* [PATCH RESEND 2.6.39 2/3] ARM: simpad: Cleanup CS3 accessors and add GPIO API
From: Jochen Friedrich @ 2011-02-18 10:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298023368-27090-1-git-send-email-jochen@scram.de>
- prepend CS3 accessors by simpad_ to indicate they
are specific to simpad devices.
- use spinlock to protect shadow register.
- implement 8 read-only pins.
- use readl/writel macros so barriers are used where
necessary.
- register CS3 as GPIO controller with 24 pins
(16 output only and 8 input only).
Signed-off-by: Jochen Friedrich <jochen@scram.de>
---
arch/arm/mach-sa1100/include/mach/simpad.h | 81 ++++++++++++++------
arch/arm/mach-sa1100/leds-simpad.c | 7 +-
arch/arm/mach-sa1100/simpad.c | 115 ++++++++++++++++++++++------
drivers/pcmcia/sa1100_simpad.c | 30 +++----
4 files changed, 165 insertions(+), 68 deletions(-)
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h
index 231550d..db28118 100644
--- a/arch/arm/mach-sa1100/include/mach/simpad.h
+++ b/arch/arm/mach-sa1100/include/mach/simpad.h
@@ -61,32 +61,67 @@
#define SIMPAD_UCB1X00_GPIO_HEADSET (SIMPAD_UCB1X00_GPIO_BASE + 8)
#define SIMPAD_UCB1X00_GPIO_SPEAKER (SIMPAD_UCB1X00_GPIO_BASE + 9)
-// CS3 Latch is write only, a shadow is necessary
+/*--- CS3 Latch ---*/
+#define SIMPAD_CS3_GPIO_BASE (GPIO_MAX + 11)
+#define SIMPAD_CS3_VCC_5V_EN (SIMPAD_CS3_GPIO_BASE)
+#define SIMPAD_CS3_VCC_3V_EN (SIMPAD_CS3_GPIO_BASE + 1)
+#define SIMPAD_CS3_EN1 (SIMPAD_CS3_GPIO_BASE + 2)
+#define SIMPAD_CS3_EN0 (SIMPAD_CS3_GPIO_BASE + 3)
+#define SIMPAD_CS3_DISPLAY_ON (SIMPAD_CS3_GPIO_BASE + 4)
+#define SIMPAD_CS3_PCMCIA_BUFF_DIS (SIMPAD_CS3_GPIO_BASE + 5)
+#define SIMPAD_CS3_MQ_RESET (SIMPAD_CS3_GPIO_BASE + 6)
+#define SIMPAD_CS3_PCMCIA_RESET (SIMPAD_CS3_GPIO_BASE + 7)
+#define SIMPAD_CS3_DECT_POWER_ON (SIMPAD_CS3_GPIO_BASE + 8)
+#define SIMPAD_CS3_IRDA_SD (SIMPAD_CS3_GPIO_BASE + 9)
+#define SIMPAD_CS3_RS232_ON (SIMPAD_CS3_GPIO_BASE + 10)
+#define SIMPAD_CS3_SD_MEDIAQ (SIMPAD_CS3_GPIO_BASE + 11)
+#define SIMPAD_CS3_LED2_ON (SIMPAD_CS3_GPIO_BASE + 12)
+#define SIMPAD_CS3_IRDA_MODE (SIMPAD_CS3_GPIO_BASE + 13)
+#define SIMPAD_CS3_ENABLE_5V (SIMPAD_CS3_GPIO_BASE + 14)
+#define SIMPAD_CS3_RESET_SIMCARD (SIMPAD_CS3_GPIO_BASE + 15)
+
+#define SIMPAD_CS3_PCMCIA_BVD1 (SIMPAD_CS3_GPIO_BASE + 16)
+#define SIMPAD_CS3_PCMCIA_BVD2 (SIMPAD_CS3_GPIO_BASE + 17)
+#define SIMPAD_CS3_PCMCIA_VS1 (SIMPAD_CS3_GPIO_BASE + 18)
+#define SIMPAD_CS3_PCMCIA_VS2 (SIMPAD_CS3_GPIO_BASE + 19)
+#define SIMPAD_CS3_LOCK_IND (SIMPAD_CS3_GPIO_BASE + 20)
+#define SIMPAD_CS3_CHARGING_STATE (SIMPAD_CS3_GPIO_BASE + 21)
+#define SIMPAD_CS3_PCMCIA_SHORT (SIMPAD_CS3_GPIO_BASE + 22)
+#define SIMPAD_CS3_GPIO_23 (SIMPAD_CS3_GPIO_BASE + 23)
-#define CS3BUSTYPE unsigned volatile long
#define CS3_BASE 0xf1000000
-#define VCC_5V_EN 0x0001 // For 5V PCMCIA
-#define VCC_3V_EN 0x0002 // FOR 3.3V PCMCIA
-#define EN1 0x0004 // This is only for EPROM's
-#define EN0 0x0008 // Both should be enable for 3.3V or 5V
-#define DISPLAY_ON 0x0010
-#define PCMCIA_BUFF_DIS 0x0020
-#define MQ_RESET 0x0040
-#define PCMCIA_RESET 0x0080
-#define DECT_POWER_ON 0x0100
-#define IRDA_SD 0x0200 // Shutdown for powersave
-#define RS232_ON 0x0400
-#define SD_MEDIAQ 0x0800 // Shutdown for powersave
-#define LED2_ON 0x1000
-#define IRDA_MODE 0x2000 // Fast/Slow IrDA mode
-#define ENABLE_5V 0x4000 // Enable 5V circuit
-#define RESET_SIMCARD 0x8000
-
-#define RS232_ENABLE 0x0440
-#define PCMCIAMASK 0x402f
-
-
+long simpad_get_cs3_ro(void);
+long simpad_get_cs3_shadow(void);
+void simpad_set_cs3_bit(int value);
+void simpad_clear_cs3_bit(int value);
+
+#define VCC_5V_EN 0x0001 /* For 5V PCMCIA */
+#define VCC_3V_EN 0x0002 /* FOR 3.3V PCMCIA */
+#define EN1 0x0004 /* This is only for EPROM's */
+#define EN0 0x0008 /* Both should be enable for 3.3V or 5V */
+#define DISPLAY_ON 0x0010
+#define PCMCIA_BUFF_DIS 0x0020
+#define MQ_RESET 0x0040
+#define PCMCIA_RESET 0x0080
+#define DECT_POWER_ON 0x0100
+#define IRDA_SD 0x0200 /* Shutdown for powersave */
+#define RS232_ON 0x0400
+#define SD_MEDIAQ 0x0800 /* Shutdown for powersave */
+#define LED2_ON 0x1000
+#define IRDA_MODE 0x2000 /* Fast/Slow IrDA mode */
+#define ENABLE_5V 0x4000 /* Enable 5V circuit */
+#define RESET_SIMCARD 0x8000
+
+#define PCMCIA_BVD1 0x01
+#define PCMCIA_BVD2 0x02
+#define PCMCIA_VS1 0x04
+#define PCMCIA_VS2 0x08
+#define LOCK_IND 0x10
+#define CHARGING_STATE 0x20
+#define PCMCIA_SHORT 0x40
+
+/*--- Battery ---*/
struct simpad_battery {
unsigned char ac_status; /* line connected yes/no */
unsigned char status; /* battery loading yes/no */
diff --git a/arch/arm/mach-sa1100/leds-simpad.c b/arch/arm/mach-sa1100/leds-simpad.c
index d50f4ee..d25784c 100644
--- a/arch/arm/mach-sa1100/leds-simpad.c
+++ b/arch/arm/mach-sa1100/leds-simpad.c
@@ -22,9 +22,6 @@ static unsigned int hw_led_state;
#define LED_GREEN (1)
#define LED_MASK (1)
-extern void set_cs3_bit(int value);
-extern void clear_cs3_bit(int value);
-
void simpad_leds_event(led_event_t evt)
{
switch (evt)
@@ -93,8 +90,8 @@ void simpad_leds_event(led_event_t evt)
}
if (led_state & LED_STATE_ENABLED)
- set_cs3_bit(LED2_ON);
+ simpad_set_cs3_bit(LED2_ON);
else
- clear_cs3_bit(LED2_ON);
+ simpad_clear_cs3_bit(LED2_ON);
}
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 718b802..ec6e381 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -13,6 +13,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/io.h>
+#include <linux/gpio.h>
#include <asm/irq.h>
#include <mach/hardware.h>
@@ -31,32 +32,85 @@
#include "generic.h"
-long cs3_shadow;
+/*
+ * CS3 support
+ */
+
+static long cs3_shadow;
+static spinlock_t cs3_lock;
+static struct gpio_chip cs3_gpio;
+
+long simpad_get_cs3_ro(void)
+{
+ return readl(CS3_BASE);
+}
+EXPORT_SYMBOL(simpad_get_cs3_ro);
-long get_cs3_shadow(void)
+long simpad_get_cs3_shadow(void)
{
return cs3_shadow;
}
+EXPORT_SYMBOL(simpad_get_cs3_shadow);
-void set_cs3(long value)
+static void __simpad_write_cs3(void)
{
- *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow = value;
+ writel(cs3_shadow, CS3_BASE);
}
-void set_cs3_bit(int value)
+void simpad_set_cs3_bit(int value)
{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cs3_lock, flags);
cs3_shadow |= value;
- *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
+ __simpad_write_cs3();
+ spin_unlock_irqrestore(&cs3_lock, flags);
}
+EXPORT_SYMBOL(simpad_set_cs3_bit);
-void clear_cs3_bit(int value)
+void simpad_clear_cs3_bit(int value)
{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cs3_lock, flags);
cs3_shadow &= ~value;
- *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
+ __simpad_write_cs3();
+ spin_unlock_irqrestore(&cs3_lock, flags);
}
+EXPORT_SYMBOL(simpad_clear_cs3_bit);
+
+static void cs3_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ if (offset > 15)
+ return;
+ if (value)
+ simpad_set_cs3_bit(1 << offset);
+ else
+ simpad_clear_cs3_bit(1 << offset);
+};
-EXPORT_SYMBOL(set_cs3_bit);
-EXPORT_SYMBOL(clear_cs3_bit);
+static int cs3_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ if (offset > 15)
+ return simpad_get_cs3_ro() & (1 << (offset - 16));
+ return simpad_get_cs3_shadow() & (1 << offset);
+};
+
+static int cs3_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ if (offset > 15)
+ return 0;
+ return -EINVAL;
+};
+
+static int cs3_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ if (offset > 15)
+ return -EINVAL;
+ cs3_gpio_set(chip, offset, value);
+ return 0;
+};
static struct map_desc simpad_io_desc[] __initdata = {
{ /* MQ200 */
@@ -64,9 +118,9 @@ static struct map_desc simpad_io_desc[] __initdata = {
.pfn = __phys_to_pfn(0x4b800000),
.length = 0x00800000,
.type = MT_DEVICE
- }, { /* Paules CS3, write only */
- .virtual = 0xf1000000,
- .pfn = __phys_to_pfn(0x18000000),
+ }, { /* Simpad CS3 */
+ .virtual = CS3_BASE,
+ .pfn = __phys_to_pfn(SA1100_CS3_PHYS),
.length = 0x00100000,
.type = MT_DEVICE
},
@@ -78,12 +132,12 @@ static void simpad_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
if (port->mapbase == (u_int)&Ser1UTCR0) {
if (state)
{
- clear_cs3_bit(RS232_ON);
- clear_cs3_bit(DECT_POWER_ON);
+ simpad_clear_cs3_bit(RS232_ON);
+ simpad_clear_cs3_bit(DECT_POWER_ON);
}else
{
- set_cs3_bit(RS232_ON);
- set_cs3_bit(DECT_POWER_ON);
+ simpad_set_cs3_bit(RS232_ON);
+ simpad_set_cs3_bit(DECT_POWER_ON);
}
}
}
@@ -143,9 +197,10 @@ static void __init simpad_map_io(void)
iotable_init(simpad_io_desc, ARRAY_SIZE(simpad_io_desc));
- set_cs3_bit (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON |
- ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON);
-
+ /* Initialize CS3 */
+ cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON |
+ RS232_ON | ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON);
+ __simpad_write_cs3(); /* Spinlocks not yet initialized */
sa1100_register_uart_fns(&simpad_port_fns);
sa1100_register_uart(0, 3); /* serial interface */
@@ -171,12 +226,13 @@ static void __init simpad_map_io(void)
static void simpad_power_off(void)
{
- local_irq_disable(); // was cli
- set_cs3(0x800); /* only SD_MEDIAQ */
+ local_irq_disable(); /* was cli */
+ cs3_shadow = SD_MEDIAQ;
+ __simpad_write_cs3(); /* Bypass spinlock here */
/* disable internal oscillator, float CS lines */
PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
- /* enable wake-up on GPIO0 (Assabet...) */
+ /* enable wake-up on GPIO0 */
PWER = GFER = GRER = 1;
/*
* set scratchpad to zero, just in case it is used as a
@@ -212,6 +268,19 @@ static int __init simpad_init(void)
{
int ret;
+ spin_lock_init(&cs3_lock);
+
+ cs3_gpio.label = "simpad_cs3";
+ cs3_gpio.base = SIMPAD_CS3_GPIO_BASE;
+ cs3_gpio.ngpio = 24;
+ cs3_gpio.set = cs3_gpio_set;
+ cs3_gpio.get = cs3_gpio_get;
+ cs3_gpio.direction_input = cs3_gpio_direction_input;
+ cs3_gpio.direction_output = cs3_gpio_direction_output;
+ ret = gpiochip_add(&cs3_gpio);
+ if (ret)
+ printk(KERN_WARNING "simpad: Unable to register cs3 GPIO device");
+
pm_power_off = simpad_power_off;
sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
diff --git a/drivers/pcmcia/sa1100_simpad.c b/drivers/pcmcia/sa1100_simpad.c
index c998f7a..540320d 100644
--- a/drivers/pcmcia/sa1100_simpad.c
+++ b/drivers/pcmcia/sa1100_simpad.c
@@ -15,10 +15,6 @@
#include <mach/simpad.h>
#include "sa1100_generic.h"
-extern long get_cs3_shadow(void);
-extern void set_cs3_bit(int value);
-extern void clear_cs3_bit(int value);
-
static struct pcmcia_irqs irqs[] = {
{ 1, IRQ_GPIO_CF_CD, "CF_CD" },
};
@@ -26,7 +22,7 @@ static struct pcmcia_irqs irqs[] = {
static int simpad_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
{
- clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1);
+ simpad_clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1);
skt->socket.pci_irq = IRQ_GPIO_CF_IRQ;
@@ -38,8 +34,8 @@ static void simpad_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs));
/* Disable CF bus: */
- //set_cs3_bit(PCMCIA_BUFF_DIS);
- clear_cs3_bit(PCMCIA_RESET);
+ /*simpad_set_cs3_bit(PCMCIA_BUFF_DIS);*/
+ simpad_clear_cs3_bit(PCMCIA_RESET);
}
static void
@@ -47,15 +43,15 @@ simpad_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
struct pcmcia_state *state)
{
unsigned long levels = GPLR;
- long cs3reg = get_cs3_shadow();
+ long cs3reg = simpad_get_cs3_shadow();
state->detect=((levels & GPIO_CF_CD)==0)?1:0;
state->ready=(levels & GPIO_CF_IRQ)?1:0;
state->bvd1=1; /* Not available on Simpad. */
state->bvd2=1; /* Not available on Simpad. */
state->wrprot=0; /* Not available on Simpad. */
-
- if((cs3reg & 0x0c) == 0x0c) {
+
+ if ((cs3reg & 0x0c) == 0x0c) {
state->vs_3v=0;
state->vs_Xv=0;
} else {
@@ -75,23 +71,23 @@ simpad_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
/* Murphy: see table of MIC2562a-1 */
switch (state->Vcc) {
case 0:
- clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1);
+ simpad_clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1);
break;
case 33:
- clear_cs3_bit(VCC_3V_EN|EN1);
- set_cs3_bit(VCC_5V_EN|EN0);
+ simpad_clear_cs3_bit(VCC_3V_EN|EN1);
+ simpad_set_cs3_bit(VCC_5V_EN|EN0);
break;
case 50:
- clear_cs3_bit(VCC_5V_EN|EN1);
- set_cs3_bit(VCC_3V_EN|EN0);
+ simpad_clear_cs3_bit(VCC_5V_EN|EN1);
+ simpad_set_cs3_bit(VCC_3V_EN|EN0);
break;
default:
printk(KERN_ERR "%s(): unrecognized Vcc %u\n",
__func__, state->Vcc);
- clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1);
+ simpad_clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1);
local_irq_restore(flags);
return -1;
}
@@ -110,7 +106,7 @@ static void simpad_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
static void simpad_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
{
soc_pcmcia_disable_irqs(skt, irqs, ARRAY_SIZE(irqs));
- set_cs3_bit(PCMCIA_RESET);
+ simpad_set_cs3_bit(PCMCIA_RESET);
}
static struct pcmcia_low_level simpad_pcmcia_ops = {
--
1.7.2.3
^ permalink raw reply related
* [PATCH RESEND 2.6.39 3/3] ARM: simpad: add GPIO based device definitions
From: Jochen Friedrich @ 2011-02-18 10:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298023368-27090-1-git-send-email-jochen@scram.de>
Register LED, keyboard, polled keyboard and I2C platform
devices based on GPIOs.
Make LED resources conditional to CONFIG_LEDS to avoid
using the legacy ARM LED code and generic GPIO LED code
concurrently on the same GPIO pin.
Signed-off-by: Jochen Friedrich <jochen@scram.de>
---
arch/arm/mach-sa1100/simpad.c | 99 ++++++++++++++++++++++++++++++++++++++++-
1 files changed, 98 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index ec6e381..058a3ee 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -29,6 +29,10 @@
#include <linux/serial_core.h>
#include <linux/ioport.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/leds.h>
+#include <linux/i2c-gpio.h>
#include "generic.h"
@@ -249,6 +253,93 @@ static void simpad_power_off(void)
}
+/*
+ * gpio_keys
+ */
+
+static struct gpio_keys_button simpad_button_table[] = {
+ { KEY_POWER, IRQ_GPIO_POWER_BUTTON, 1, "power button" },
+};
+
+static struct gpio_keys_platform_data simpad_keys_data = {
+ .buttons = simpad_button_table,
+ .nbuttons = ARRAY_SIZE(simpad_button_table),
+};
+
+static struct platform_device simpad_keys = {
+ .name = "gpio-keys",
+ .dev = {
+ .platform_data = &simpad_keys_data,
+ },
+};
+
+static struct gpio_keys_button simpad_polled_button_table[] = {
+ { KEY_PROG1, SIMPAD_UCB1X00_GPIO_PROG1, 1, "prog1 button" },
+ { KEY_PROG2, SIMPAD_UCB1X00_GPIO_PROG2, 1, "prog2 button" },
+ { KEY_UP, SIMPAD_UCB1X00_GPIO_UP, 1, "up button" },
+ { KEY_DOWN, SIMPAD_UCB1X00_GPIO_DOWN, 1, "down button" },
+ { KEY_LEFT, SIMPAD_UCB1X00_GPIO_LEFT, 1, "left button" },
+ { KEY_RIGHT, SIMPAD_UCB1X00_GPIO_RIGHT, 1, "right button" },
+};
+
+static struct gpio_keys_platform_data simpad_polled_keys_data = {
+ .buttons = simpad_polled_button_table,
+ .nbuttons = ARRAY_SIZE(simpad_polled_button_table),
+ .poll_interval = 50,
+};
+
+static struct platform_device simpad_polled_keys = {
+ .name = "gpio-keys-polled",
+ .dev = {
+ .platform_data = &simpad_polled_keys_data,
+ },
+};
+
+/*
+ * GPIO LEDs
+ */
+
+#ifndef CONFIG_LEDS
+static struct gpio_led simpad_leds[] = {
+ {
+ .name = "power",
+ .gpio = SIMPAD_CS3_LED2_ON,
+ .active_low = 0,
+ .default_trigger = "default-on",
+ },
+};
+
+static struct gpio_led_platform_data simpad_led_data = {
+ .num_leds = 1,
+ .leds = simpad_leds,
+};
+
+static struct platform_device simpad_gpio_leds = {
+ .name = "leds-gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &simpad_led_data,
+ },
+};
+#endif
+
+/*
+ * i2c
+ */
+static struct i2c_gpio_platform_data simpad_i2c_data = {
+ .sda_pin = GPIO_GPIO21,
+ .scl_pin = GPIO_GPIO25,
+ .udelay = 10,
+ .timeout = HZ,
+};
+
+static struct platform_device simpad_i2c = {
+ .name = "i2c-gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &simpad_i2c_data,
+ },
+};
/*
* MediaQ Video Device
@@ -259,7 +350,13 @@ static struct platform_device simpad_mq200fb = {
};
static struct platform_device *devices[] __initdata = {
- &simpad_mq200fb
+ &simpad_keys,
+ &simpad_polled_keys,
+ &simpad_mq200fb,
+#ifndef CONFIG_LEDS
+ &simpad_gpio_leds,
+#endif
+ &simpad_i2c,
};
--
1.7.2.3
^ permalink raw reply related
* [PATCH] ARM: PXA: Make PXA27x/PXA3xx overlay actually work
From: Sascha Hauer @ 2011-02-18 10:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1296679619-32666-1-git-send-email-anarsoul@gmail.com>
Hi Vasily,
On Wed, Feb 02, 2011 at 10:46:59PM +0200, Vasily Khoruzhick wrote:
> From: "Russell King - ARM Linux" <linux@arm.linux.org.uk>
>
> Release callback tries to free memory even if it was not allocated in
> map_video_memory. Fix PXA27x/3xx overlay memory management and make overlay
> actually work.
While at pxa overlay support you also might to fix that the xpos field
in var->nonstd is also used for ypos in two places:
ypos = NONSTD_TO_XPOS(var->nonstd);
^^^
I stumbled upon this but was not interested enough that moment to create
a patch.
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 01/09] ARM: s3c2442: gta02: Fix usage gpio bank j pin definitions
From: Lars-Peter Clausen @ 2011-02-18 10:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297043521-21903-1-git-send-email-lars@metafoo.de>
On 02/07/2011 02:51 AM, Lars-Peter Clausen wrote:
> The gta02 header file still uses the old S3C2410_GPJx defines instead of the
> S3C2410_GPJ(x) macro. Since the S3C2410_GPJx defines have already been removed
> this causes the following build failure:
>
> sound/soc/samsung/neo1973_wm8753.c: In function 'lm4853_set_spk':
> sound/soc/samsung/neo1973_wm8753.c:259: error: 'S3C2440_GPJ2' undeclared (first use in this function)
> sound/soc/samsung/neo1973_wm8753.c:259: error: (Each undeclared identifier is reported only once
> sound/soc/samsung/neo1973_wm8753.c:259: error: for each function it appears in.)
> sound/soc/samsung/neo1973_wm8753.c: In function 'lm4853_get_spk':
> sound/soc/samsung/neo1973_wm8753.c:267: error: 'S3C2440_GPJ2' undeclared (first use in this function)
> sound/soc/samsung/neo1973_wm8753.c: In function 'lm4853_event':
> sound/soc/samsung/neo1973_wm8753.c:276: error: 'S3C2440_GPJ1' undeclared (first use in this function)
> sound/soc/samsung/neo1973_wm8753.c: At top level:
> sound/soc/samsung/neo1973_wm8753.c:439: error: 'S3C2440_GPJ2' undeclared here (not in a function)
> sound/soc/samsung/neo1973_wm8753.c:440: error: 'S3C2440_GPJ1' undeclared here (not in a function)
>
> This patches fixes the issue by doing a s,S3C2410_GPJ([\d]+),S3C2410_GPJ(\1),g
> on the file.
>
> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Hi
Ben or Kukjin could you take a look at this series and merge it, if it is ok?
- Lars
> ---
> arch/arm/mach-s3c2440/include/mach/gta02.h | 26 +++++++++++++-------------
> 1 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/mach-s3c2440/include/mach/gta02.h b/arch/arm/mach-s3c2440/include/mach/gta02.h
> index 953331d..3a56a22 100644
> --- a/arch/arm/mach-s3c2440/include/mach/gta02.h
> +++ b/arch/arm/mach-s3c2440/include/mach/gta02.h
> @@ -44,19 +44,19 @@
> #define GTA02v3_GPIO_nUSB_FLT S3C2410_GPG(10) /* v3 + v4 only */
> #define GTA02v3_GPIO_nGSM_OC S3C2410_GPG(11) /* v3 + v4 only */
>
> -#define GTA02_GPIO_AMP_SHUT S3C2440_GPJ1 /* v2 + v3 + v4 only */
> -#define GTA02v1_GPIO_WLAN_GPIO10 S3C2440_GPJ2
> -#define GTA02_GPIO_HP_IN S3C2440_GPJ2 /* v2 + v3 + v4 only */
> -#define GTA02_GPIO_INT0 S3C2440_GPJ3 /* v2 + v3 + v4 only */
> -#define GTA02_GPIO_nGSM_EN S3C2440_GPJ4
> -#define GTA02_GPIO_3D_RESET S3C2440_GPJ5
> -#define GTA02_GPIO_nDL_GSM S3C2440_GPJ6 /* v4 + v5 only */
> -#define GTA02_GPIO_WLAN_GPIO0 S3C2440_GPJ7
> -#define GTA02v1_GPIO_BAT_ID S3C2440_GPJ8
> -#define GTA02_GPIO_KEEPACT S3C2440_GPJ8
> -#define GTA02v1_GPIO_HP_IN S3C2440_GPJ10
> -#define GTA02_CHIP_PWD S3C2440_GPJ11 /* v2 + v3 + v4 only */
> -#define GTA02_GPIO_nWLAN_RESET S3C2440_GPJ12 /* v2 + v3 + v4 only */
> +#define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */
> +#define GTA02v1_GPIO_WLAN_GPIO10 S3C2410_GPJ(2)
> +#define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */
> +#define GTA02_GPIO_INT0 S3C2410_GPJ(3) /* v2 + v3 + v4 only */
> +#define GTA02_GPIO_nGSM_EN S3C2410_GPJ(4)
> +#define GTA02_GPIO_3D_RESET S3C2410_GPJ(5)
> +#define GTA02_GPIO_nDL_GSM S3C2410_GPJ(6) /* v4 + v5 only */
> +#define GTA02_GPIO_WLAN_GPIO0 S3C2410_GPJ(7)
> +#define GTA02v1_GPIO_BAT_ID S3C2410_GPJ(8)
> +#define GTA02_GPIO_KEEPACT S3C2410_GPJ(8)
> +#define GTA02v1_GPIO_HP_IN S3C2410_GPJ(10)
> +#define GTA02_CHIP_PWD S3C2410_GPJ(11) /* v2 + v3 + v4 only */
> +#define GTA02_GPIO_nWLAN_RESET S3C2410_GPJ(12) /* v2 + v3 + v4 only */
>
> #define GTA02_IRQ_GSENSOR_1 IRQ_EINT0
> #define GTA02_IRQ_MODEM IRQ_EINT1
^ permalink raw reply
* [PATCH 00/10] Fix CLCD framebuffer formats and consolidate ARM platform CLCD support
From: Catalin Marinas @ 2011-02-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110127125714.GD25968@n2100.arm.linux.org.uk>
On Thu, 2011-01-27 at 12:57 +0000, Russell King - ARM Linux wrote:
> This patch series fixes the framebuffer formatting for the various
> CLCD colour modes - including those which the CLCD doesn't actually
> support.
I reviewed the patches and they look fine (ack if you want).
What I can't tell for sure is whether the capabilities supported by the
displays are correct (platforms people here in ARM should know better
but I don't think we have all those available to try).
--
Catalin
^ permalink raw reply
* Good Day
From: Barrister Chong Kim Wong @ 2011-02-18 11:16 UTC (permalink / raw)
To: linux-arm-kernel
I am Chong Kim Wong, Attorney at law.I have contacted you to assist in
distributing the money left behind by my Late client , that shares the same
name as yours,who lost his life alongside his wife and only child in
(Beirut-bound charter jet) plane crash on the Monday, 9 January 2006,Prior to
the Death of my Late Client.Get back to me via email for more detils:barrchongkim1 at hotmail.com
Regards And hope to hear from you soon.
Barr Chong Kim Wong
^ permalink raw reply
* [patch-v2.6.39 5/7] AM35xx: hwmod data: Add USBOTG
From: Premi, Sanjeev @ 2011-02-18 11:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297946466-9565-6-git-send-email-balbi@ti.com>
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Balbi, Felipe
> Sent: Thursday, February 17, 2011 6:11 PM
> To: Tony Lindgren
> Cc: Linux OMAP Mailing List; Linux ARM Kernel Mailing List; Kalliguddi,
> Hema; Kevin Hilman; Cousson, Benoit; Paul Walmsley; Balbi, Felipe
> Subject: [patch-v2.6.39 5/7] AM35xx: hwmod data: Add USBOTG
>
> From: Hema HK <hemahk@ti.com>
>
> AM35xx hwmod data structures are populated for USBOTG with base address,
> L3 and L4 interface clocks and IRQ.
>
> Signed-off-by: Hema HK <hemahk@ti.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Cousson, Benoit <b-cousson@ti.com>
> Cc: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Felipe Balbi <balbi@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 65
> ++++++++++++++++++++++++++++
> 1 files changed, 65 insertions(+), 0 deletions(-)
>
[snip]
>
> + /* usbotg for am35x */
> + &am35xx_usbhsotg_hwmod,
> +
> NULL,
Felipe, Hema,
This patch will break all existing OMAP35x (and I believe
OMAP3430 - since there is no difference - unless there is
some trick in the USB driver code).
I have seen similar problems with smart reflex included in
the AM35x hwmod data.
In this case accessing "unknown" registers corresponding to
SmartReflex in _setup() causes crash.
(http://marc.info/?l=linux-omap&m=129777408503329&w=2)
I expect similar to be happening on OMAP35x with inclusion
of am35xx_usbhsotg_hwmod. If you don't see any crash, there
would be side-effects - and _setup() would be initializing
non-existent OTG registers on OMAP35x.
Did you see any problems while testing?
~sanjeev
PS: Sending mail via webmailer. Formatting may break
> };
>
> --
> 1.7.4.rc2
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
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