* MMC quirks relating to performance/lifetime.
From: Andrei Warkentin @ 2011-02-18 19:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201102181444.24476.arnd@arndb.de>
On Fri, Feb 18, 2011 at 7:44 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> I'm curious. Neither the manfid nor the oemid fields of either card
> match what I have seen on SD cards, I would expect them to be
>
> Sandisk: manfid 0x000003, oemid 0x5344
> Toshiba: manfid 0x000002, oemid 0x544d
>
> I have not actually seen any Toshiba SD cards, but I assume that they
> use the same controllers as Kingston.
>
> Does anyone know if the IDs have any correlation between MMC and SD
> controllers?
>
> ? ? ? ?Arnd
>
I'm unsure about the older scheme (assigned by MMCA), but ever since
MMC is now JEDEC-controlled, the IDs have changed. Sandisk's new id
will be 0x45, and Toshiba I guess will be 0x11.
^ permalink raw reply
* platform/i2c busses: pm runtime and system sleep
From: Rabin Vincent @ 2011-02-18 19:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201102181928.05911.rjw@sisk.pl>
On Fri, Feb 18, 2011 at 23:58, Rafael J. Wysocki <rjw@sisk.pl> wrote:
> On Friday, February 18, 2011, Rabin Vincent wrote:
>> On Thu, Feb 17, 2011 at 20:55, Rabin Vincent <rabin@rab.in> wrote:
>> > This will solve the platform vs AMBA bus, but shouldn't we really be
>> > aiming for consistent behaviour between these and the other busses such
>> > as I2C and SPI, which are also usually commonly used on the same
>> > platforms and are using GENERIC_PM_OPS?
>> >
>> > Should we be auditing all platform drivers and then switch platform to
>> > the GENERIC_PM_OPS?
>> >
>> > Or should the two points (1) and (2) be not handled in the bus at all
>> > and be left to individual drivers (in which case we should audit i2c and
>> > spi and change GENERIC_PM_OPS)?
>>
>> How about something like the below? ?If we have something like this, we
>> can just switch platform to GENERIC_PM_OPS and add the
>> pm_runtime_want_interaction() (or something better named) call to the
>> i2c and spi drivers using runtime PM.
>
> Why don't we make platform_bus_type behave along the lines of generic ops
> instead?
At least drivers/spi/omap2_mcspi.c, drivers/video/sh_mobile_lcdcfb.c and
drivers/watchdog/omap_wdt.c are some pm_runtime-using drivers which seem
to do different things in their runtime vs normal suspend/resume
routines, so forcing platform into the active-on-resume behaviour of the
generic ops may make some use cases impossible. Conversion of more OMAP
drivers to runtime pm appears to be ongoing so I'd imagine we'd be
seeing more of this. Perhaps Kevin or Magnus will have a comment here.
The same thing applies to AMBA drivers.
Looking at the i2c drivers using runtime pm in comparison, they all seem
to be using straightforward UNIVERSAL_PM_OPS-style code with the runtime
and the system sleep doing the same things. So maybe we do need to
treat platform/AMBA different from the I2C/SPI group?
^ permalink raw reply
* [PATCH] ARM: gic: use handle_fasteoi_irq for SPIs
From: Will Deacon @ 2011-02-18 18:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTikRXgT76Pzv8yiVLN8gRAxvrYu1CWqDjt7V-GH=@mail.gmail.com>
> > Well, grepping for set_chained_irq_handler yields a whole bunch of platforms
> > but the set of these which appear to use the gic is only:
> >
> > mach-msm
> > mach-s5pv310
> > mach-shmobile
> > mach-tegra
> >
> > I'll have a look through the code there and post some patches next week.
> > Hopefully if I've missed anybody, they'll shout then.
>
> omap4 uses the gic, and uses chained handlers in plat-omap/gpio.c.
> plat-omap/gpio.c seems to handle similar gpio hardware connected to
> different IRQ controllers on different SoCs - non-gic on omap2-3, and
> gic on omap4.
Thanks for spotting this Colin. My grep-fu failed me because the gic
initialisation for omap is under a different directory to the GPIO cascaded
IRQ stuff (plat- vs mach-).
I'll add OMAP to the list.
Will
^ permalink raw reply
* [PATCH v2 13/13] tty: pruss SUART driver
From: Arnd Bergmann @ 2011-02-18 18:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1102181917520.2701@localhost6.localdomain6>
On Friday 18 February 2011 19:23:49 Thomas Gleixner wrote:
> On Fri, 18 Feb 2011, Alan Cox wrote:
>
> > On Fri, 18 Feb 2011 19:17:38 +0530
> > "Subhasish Ghosh" <subhasish@mistralsolutions.com> wrote:
> >
> > > Hello,
> > >
> > > Regarding the semaphore to mutex migration.
> > > We are using down_trylock in interrupt context,
> > > mutex_trylock cannot be used in interrupt context, so we cannot use mutex in
> > > our driver.
> >
> > Then you probably need to rework your locking. Best bet might be to fix
> > all the other stuff and report the driver, and people can think about the
> > locking problem.
>
> That semaphore is utterly useless to begin with. There are more
> serious locking problems than this one. Non serialized calls to
> suart_intr_clrmask/suart_intr_setmask are the most obvious ones.
>
> Aside of that the code is complete unreadable.
I think it mostly suffers from the same problem as the CAN driver
I commented on earlier: One of the files (pruss_suart_api.c) was
clearly not written with Linux as the target, and the other files
try to work around this by wrapping a Linux driver around it.
The suart_api HAL stuff clearly needs to go away, so that the rest
can be rewritten into a proper device driver.
Arnd
^ permalink raw reply
* [PATCH] msm: add single-wire serial bus interface (SSBI) driver
From: Daniel Walker @ 2011-02-18 18:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D5DC289.1090004@codeaurora.org>
On Thu, 2011-02-17 at 16:51 -0800, Bryan Huntsman wrote:
> On 02/17/2011 04:37 PM, Daniel Walker wrote:
> > Can you put this in drivers/ this doesn't looks like it need to be here.
>
> Where would you suggest? The initial attempt to model SSBI as an I2C
> bus didn't go anywhere. See http://lkml.org/lkml/2010/7/21/400. This
> functionality is specific to MSM. Plus, we're trying to maintain
> similarity to the Android MSM tree. That may not matter to people who
> don't use MSM, but is matters to us. Given these considerations, the
> current location seems as good a place as any.
I don't know the driver well enough to be more detailed than suggesting
drivers/ . In the thread you quoted Pavel (who I added to the CC line)
suggested drivers/ssbi/ .
Daniel
--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [PATCH] ARM: gic: use handle_fasteoi_irq for SPIs
From: Santosh Shilimkar @ 2011-02-18 18:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTikRXgT76Pzv8yiVLN8gRAxvrYu1CWqDjt7V-GH=@mail.gmail.com>
> -----Original Message-----
> From: Colin Cross [mailto:ccross at google.com]
> Sent: Saturday, February 19, 2011 12:01 AM
> To: Will Deacon
> Cc: Thomas Gleixner; Rabin Vincent; Abhijeet Dharmapurikar; Russell
> King - ARM Linux; linux-arm-kernel at lists.infradead.org; Santosh
> Shilimkar
> Subject: Re: [PATCH] ARM: gic: use handle_fasteoi_irq for SPIs
>
> On Fri, Feb 18, 2011 at 4:09 AM, Will Deacon <will.deacon@arm.com>
> wrote:
> >> > I don't think the cascaded handlers would have assumed that
> because ack
> >> > just sends EOI - it doesn't do any masking. We do have a
> problem with
> >> > the percpu_irq flow though (the GIC reference manual says that
> EOIing a
> >> > non-active interrupt is UNPREDICTABLE).
> >> >
> >> > Another easy hack is to set IRQ_PER_CPU in the irq_desc->status
> for PPI
> >> > interrupts and then check this in the ack routine. It's pretty
> ugly, but
> >> > it doesn't affect the common case and it at least postpones the
> platform
> >> > changes.
> >>
> >> Conditionals in irq_chip callbacks are almost always a sign of
> >> doom. Don't do that.
> >
> > Ok, that was a hack too far! Let's fix this properly.
> >
> >> How many chained handlers need to be fixed, when the whole gic
> stuff
> >> switches to eoi ?
> >
> > Well, grepping for set_chained_irq_handler yields a whole bunch of
> platforms
> > but the set of these which appear to use the gic is only:
> >
> > mach-msm
> > mach-s5pv310
> > mach-shmobile
> > mach-tegra
> >
> > I'll have a look through the code there and post some patches next
> week.
> > Hopefully if I've missed anybody, they'll shout then.
>
> omap4 uses the gic, and uses chained handlers in plat-omap/gpio.c.
> plat-omap/gpio.c seems to handle similar gpio hardware connected to
> different IRQ controllers on different SoCs - non-gic on omap2-3,
> and gic on omap4.
That's right.
Thanks Colin for pointing it. I almost missed this
thread.
Regards,
Santosh
^ permalink raw reply
* [PATCH] ARM: gic: use handle_fasteoi_irq for SPIs
From: Colin Cross @ 2011-02-18 18:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <-8083923411736601789@unknownmsgid>
On Fri, Feb 18, 2011 at 4:09 AM, Will Deacon <will.deacon@arm.com> wrote:
>> > I don't think the cascaded handlers would have assumed that because ack
>> > just sends EOI - it doesn't do any masking. We do have a problem with
>> > the percpu_irq flow though (the GIC reference manual says that EOIing a
>> > non-active interrupt is UNPREDICTABLE).
>> >
>> > Another easy hack is to set IRQ_PER_CPU in the irq_desc->status for PPI
>> > interrupts and then check this in the ack routine. It's pretty ugly, but
>> > it doesn't affect the common case and it at least postpones the platform
>> > changes.
>>
>> Conditionals in irq_chip callbacks are almost always a sign of
>> doom. Don't do that.
>
> Ok, that was a hack too far! Let's fix this properly.
>
>> How many chained handlers need to be fixed, when the whole gic stuff
>> switches to eoi ?
>
> Well, grepping for set_chained_irq_handler yields a whole bunch of platforms
> but the set of these which appear to use the gic is only:
>
> mach-msm
> mach-s5pv310
> mach-shmobile
> mach-tegra
>
> I'll have a look through the code there and post some patches next week.
> Hopefully if I've missed anybody, they'll shout then.
omap4 uses the gic, and uses chained handlers in plat-omap/gpio.c.
plat-omap/gpio.c seems to handle similar gpio hardware connected to
different IRQ controllers on different SoCs - non-gic on omap2-3, and
gic on omap4.
^ permalink raw reply
* platform/i2c busses: pm runtime and system sleep
From: Rafael J. Wysocki @ 2011-02-18 18:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTinsPqFcodH0w7LQeFEY+amodNH4CneRCRhhbKaz@mail.gmail.com>
On Friday, February 18, 2011, Rabin Vincent wrote:
> On Thu, Feb 17, 2011 at 20:55, Rabin Vincent <rabin@rab.in> wrote:
> > This will solve the platform vs AMBA bus, but shouldn't we really be
> > aiming for consistent behaviour between these and the other busses such
> > as I2C and SPI, which are also usually commonly used on the same
> > platforms and are using GENERIC_PM_OPS?
> >
> > Should we be auditing all platform drivers and then switch platform to
> > the GENERIC_PM_OPS?
> >
> > Or should the two points (1) and (2) be not handled in the bus at all
> > and be left to individual drivers (in which case we should audit i2c and
> > spi and change GENERIC_PM_OPS)?
>
> How about something like the below? If we have something like this, we
> can just switch platform to GENERIC_PM_OPS and add the
> pm_runtime_want_interaction() (or something better named) call to the
> i2c and spi drivers using runtime PM.
Why don't we make platform_bus_type behave along the lines of generic ops
instead?
Rafael
^ permalink raw reply
* [PATCH v2 13/13] tty: pruss SUART driver
From: Thomas Gleixner @ 2011-02-18 18:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110218143500.23b3044b@lxorguk.ukuu.org.uk>
On Fri, 18 Feb 2011, Alan Cox wrote:
> On Fri, 18 Feb 2011 19:17:38 +0530
> "Subhasish Ghosh" <subhasish@mistralsolutions.com> wrote:
>
> > Hello,
> >
> > Regarding the semaphore to mutex migration.
> > We are using down_trylock in interrupt context,
> > mutex_trylock cannot be used in interrupt context, so we cannot use mutex in
> > our driver.
>
> Then you probably need to rework your locking. Best bet might be to fix
> all the other stuff and report the driver, and people can think about the
> locking problem.
That semaphore is utterly useless to begin with. There are more
serious locking problems than this one. Non serialized calls to
suart_intr_clrmask/suart_intr_setmask are the most obvious ones.
Aside of that the code is complete unreadable.
Thanks,
tglx
^ permalink raw reply
* [PATCH] perf: add OMAP support for the new power events
From: Santosh Shilimkar @ 2011-02-18 18:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298052645-4164-1-git-send-email-j-pihet@ti.com>
Jean,
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of jean.pihet at newoldbits.com
> Sent: Friday, February 18, 2011 11:41 PM
> To: Kevin Hilman; Thomas Renninger; linux-omap at vger.kernel.org;
> linux-arm-kernel at lists.infradead.org
> Cc: Jean Pihet
> Subject: [PATCH] perf: add OMAP support for the new power events
>
> From: Jean Pihet <j-pihet@ti.com>
>
> The patch adds the new power management trace points for
> the OMAP architecture.
>
> The trace points are for:
> - default idle handler. Since the cpuidle framework is
> instrumented in the generic way there is no need to
> add trace points in the OMAP specific cpuidle handler;
> - cpufreq (DVFS),
> - SoC clocks changes (enable, disable, set_rate),
> - power domain states: the desired target state and -if different-
> the actually hit state.
>
> Because of the generic nature of the changes, OMAP3 and OMAP4 are
> supported.
>
> Tested on OMAP3 with suspend/resume, cpuidle, basic DVFS.
>
> Signed-off-by: Jean Pihet <j-pihet@ti.com>
Thanks for additional power domain trace point as per
discussion.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/mach-omap2/clock.c | 8 +++++++-
> arch/arm/mach-omap2/pm34xx.c | 7 +++++++
> arch/arm/mach-omap2/powerdomain.c | 26 +++++++++++++++++++++++---
> 3 files changed, 37 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-
> omap2/clock.c
> index 2a2f152..72af75d 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -22,7 +22,9 @@
> #include <linux/clk.h>
> #include <linux/io.h>
> #include <linux/bitops.h>
> +#include <trace/events/power.h>
>
> +#include <asm/cpu.h>
> #include <plat/clock.h>
> #include "clockdomain.h"
> #include <plat/cpu.h>
> @@ -261,6 +263,7 @@ void omap2_clk_disable(struct clk *clk)
>
> pr_debug("clock: %s: disabling in hardware\n", clk->name);
>
> + trace_clock_disable(clk->name, 0, smp_processor_id());
> clk->ops->disable(clk);
>
> if (clk->clkdm)
> @@ -312,6 +315,7 @@ int omap2_clk_enable(struct clk *clk)
> }
> }
>
> + trace_clock_enable(clk->name, 1, smp_processor_id());
> ret = clk->ops->enable(clk);
> if (ret) {
> WARN(1, "clock: %s: could not enable: %d\n", clk->name,
> ret);
> @@ -349,8 +353,10 @@ int omap2_clk_set_rate(struct clk *clk,
> unsigned long rate)
> pr_debug("clock: set_rate for clock %s to rate %ld\n", clk-
> >name, rate);
>
> /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
> - if (clk->set_rate)
> + if (clk->set_rate) {
> + trace_clock_set_rate(clk->name, rate,
> smp_processor_id());
> ret = clk->set_rate(clk, rate);
> + }
>
> return ret;
> }
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-
> omap2/pm34xx.c
> index 2f864e4..d1cc3f4 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -29,6 +29,7 @@
> #include <linux/delay.h>
> #include <linux/slab.h>
> #include <linux/console.h>
> +#include <trace/events/power.h>
>
> #include <plat/sram.h>
> #include "clockdomain.h"
> @@ -519,8 +520,14 @@ static void omap3_pm_idle(void)
> if (omap_irq_pending() || need_resched())
> goto out;
>
> + trace_power_start(POWER_CSTATE, 1, smp_processor_id());
> + trace_cpu_idle(1, smp_processor_id());
> +
> omap_sram_idle();
>
> + trace_power_end(smp_processor_id());
> + trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
> +
> out:
> local_fiq_enable();
> local_irq_enable();
> diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-
> omap2/powerdomain.c
> index eaed0df..1495eed 100644
> --- a/arch/arm/mach-omap2/powerdomain.c
> +++ b/arch/arm/mach-omap2/powerdomain.c
> @@ -19,12 +19,15 @@
> #include <linux/list.h>
> #include <linux/errno.h>
> #include <linux/string.h>
> +#include <trace/events/power.h>
> +
> #include "cm2xxx_3xxx.h"
> #include "prcm44xx.h"
> #include "cm44xx.h"
> #include "prm2xxx_3xxx.h"
> #include "prm44xx.h"
>
> +#include <asm/cpu.h>
> #include <plat/cpu.h>
> #include "powerdomain.h"
> #include "clockdomain.h"
> @@ -32,6 +35,8 @@
>
> #include "pm.h"
>
> +#define PWRDM_TRACE_STATES_FLAG (1<<31)
> +
> enum {
> PWRDM_STATE_NOW = 0,
> PWRDM_STATE_PREV,
> @@ -130,8 +135,7 @@ static void
> _update_logic_membank_counters(struct powerdomain *pwrdm)
> static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
> {
>
> - int prev;
> - int state;
> + int prev, state, trace_state = 0;
>
> if (pwrdm == NULL)
> return -EINVAL;
> @@ -148,6 +152,17 @@ static int _pwrdm_state_switch(struct
> powerdomain *pwrdm, int flag)
> pwrdm->state_counter[prev]++;
> if (prev == PWRDM_POWER_RET)
> _update_logic_membank_counters(pwrdm);
> + /*
> + * If the power domain did not hit the desired state,
> + * generate a trace event with both the desired and hit
> states
> + */
> + if (state != prev) {
> + trace_state = (PWRDM_TRACE_STATES_FLAG |
> + ((state & OMAP_POWERSTATE_MASK) <<
8)
> |
> + ((prev & OMAP_POWERSTATE_MASK) <<
> 0));
> + trace_power_domain_target(pwrdm->name,
> trace_state,
> + smp_processor_id());
> + }
> break;
> default:
> return -EINVAL;
> @@ -406,8 +421,13 @@ int pwrdm_set_next_pwrst(struct powerdomain
> *pwrdm, u8 pwrst)
> pr_debug("powerdomain: setting next powerstate for %s to
> %0x\n",
> pwrdm->name, pwrst);
>
> - if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst)
> + if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
> + /* Trace the pwrdm desired target state */
> + trace_power_domain_target(pwrdm->name, pwrst,
> + smp_processor_id());
> + /* Program the pwrdm desired target state */
> ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
> + }
>
> return ret;
> }
> --
> 1.7.2.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-
> omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH V4 4/4] ARM: Xilinx: Adding Xilinx platform infrastructure support
From: John Linn @ 2011-02-18 18:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298052881-14591-4-git-send-email-john.linn@xilinx.com>
Minimum infrastructure to add the Xilinx machine and allow it to
be selected in the build.
Signed-off-by: John Linn <john.linn@xilinx.com>
---
V4
Updated to apply against linux-next branch.
No updates for V3
V2 Changes
Updates based on Russell King's comments
Cleanup of the Kconfig
Moved this patch to be last in the patch series
arch/arm/Kconfig | 14 ++++++++++++++
arch/arm/Makefile | 1 +
arch/arm/mm/Kconfig | 2 +-
3 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 08799af..326f1b5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -880,6 +880,18 @@ config ARCH_VT8500
select HAVE_PWM
help
Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
+
+config ARCH_XILINX
+ bool "Xilinx ARM Cortex A9 Platform"
+ select CPU_V7
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select CLKDEV_LOOKUP
+ select ARM_GIC
+ select ARM_AMBA
+ help
+ Support for Xilinx ARM Cortex A9 Platform
+
endchoice
#
@@ -1013,6 +1025,8 @@ source "arch/arm/mach-vt8500/Kconfig"
source "arch/arm/mach-w90x900/Kconfig"
+source "arch/arm/mach-xilinx/Kconfig"
+
# Definitions to make life easier
config ARCH_ACORN
bool
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 9a0f6a3..bb5fa87 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -197,6 +197,7 @@ machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
machine-$(CONFIG_MACH_SPEAR600) := spear6xx
+machine-$(CONFIG_ARCH_XILINX) := xilinx
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 8926638..34fa4af 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -821,7 +821,7 @@ config CACHE_L2X0
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
+ ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_XILINX
default y
select OUTER_CACHE
select OUTER_CACHE_SYNC
--
1.6.2.1
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* [PATCH V4 3/4] ARM: Xilinx: base header files and assembly macros
From: John Linn @ 2011-02-18 18:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298052881-14591-3-git-send-email-john.linn@xilinx.com>
These are the minimum needed to build the kernel for the new platform.
Signed-off-by: John Linn <john.linn@xilinx.com>
---
V4 Changes
Cleanup based on input from Jamie Iles.
Moved to PLAT_PHYS_OFFSET.
Remove headers file inclusions that weren't needed.
Added use of raw_readl/raw_writel in uncompressor uart code.
Added cpu_relax() in the uncompressor uart code.
V3 Changes
Updates based on Russell Kings' comments
Changed headers to update the license info and remove
the address
Updated the constant to use UL in vmalloc.h
V2 Changes
Updates based on Russell King's comments
moved to using entry-macro-gic.S
moved stuff from hardware.h to xilinx_soc.h
added IOMEM() in io.h to help with typing
Minor updates to IO_SPACE_LIMIT and __io()
Updated addresses to be clear with seperate virtual
and physical addresses
arch/arm/mach-xilinx/include/mach/clkdev.h | 33 ++++++++++++
arch/arm/mach-xilinx/include/mach/debug-macro.S | 36 +++++++++++++
arch/arm/mach-xilinx/include/mach/entry-macro.S | 30 +++++++++++
arch/arm/mach-xilinx/include/mach/hardware.h | 18 +++++++
arch/arm/mach-xilinx/include/mach/io.h | 33 ++++++++++++
arch/arm/mach-xilinx/include/mach/irqs.h | 29 +++++++++++
arch/arm/mach-xilinx/include/mach/memory.h | 23 +++++++++
arch/arm/mach-xilinx/include/mach/system.h | 28 ++++++++++
arch/arm/mach-xilinx/include/mach/timex.h | 22 ++++++++
arch/arm/mach-xilinx/include/mach/uart.h | 25 +++++++++
arch/arm/mach-xilinx/include/mach/uncompress.h | 61 +++++++++++++++++++++++
arch/arm/mach-xilinx/include/mach/vmalloc.h | 20 +++++++
arch/arm/mach-xilinx/include/mach/xilinx_soc.h | 46 +++++++++++++++++
13 files changed, 404 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h
create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h
create mode 100644 arch/arm/mach-xilinx/include/mach/io.h
create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h
create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h
create mode 100644 arch/arm/mach-xilinx/include/mach/system.h
create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h
create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h
create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h
create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h
diff --git a/arch/arm/mach-xilinx/include/mach/clkdev.h b/arch/arm/mach-xilinx/include/mach/clkdev.h
new file mode 100644
index 0000000..5dd1453
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/clkdev.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-xilinx/include/mach/clkdev.h
+ *
+ * Copyright (C) 2011 Xilinx, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_CLKDEV_H__
+#define __MACH_CLKDEV_H__
+
+struct clk {
+ unsigned long rate;
+};
+
+static inline int __clk_get(struct clk *clk)
+{
+ return 1;
+}
+
+static inline void __clk_put(struct clk *clk)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/debug-macro.S b/arch/arm/mach-xilinx/include/mach/debug-macro.S
new file mode 100644
index 0000000..30d3d3d
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/debug-macro.S
@@ -0,0 +1,36 @@
+/* arch/arm/mach-xilinx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/xilinx_soc.h>
+#include <mach/uart.h>
+
+ .macro addruart, rp, rv
+ ldr \rp, =LL_UART_PADDR @ physical
+ ldr \rv, =LL_UART_VADDR @ virtual
+ .endm
+
+ .macro senduart,rd,rx
+ str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
+ .endm
+
+ .macro waituart,rd,rx
+ .endm
+
+ .macro busyuart,rd,rx
+1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
+ tst \rd, #UART_SR_TXFULL @
+ bne 1002b @ wait if FIFO is full
+ .endm
diff --git a/arch/arm/mach-xilinx/include/mach/entry-macro.S b/arch/arm/mach-xilinx/include/mach/entry-macro.S
new file mode 100644
index 0000000..11a2866
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/entry-macro.S
@@ -0,0 +1,30 @@
+/*
+ * arch/arm/mach-xilinx/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * based on arch/plat-mxc/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/hardware.h>
+#include <asm/hardware/entry-macro-gic.S>
+
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h b/arch/arm/mach-xilinx/include/mach/hardware.h
new file mode 100644
index 0000000..f9685c4
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/hardware.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-xilinx/include/mach/hardware.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_HARDWARE_H__
+#define __MACH_HARDWARE_H__
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/io.h b/arch/arm/mach-xilinx/include/mach/io.h
new file mode 100644
index 0000000..ef69e65
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/io.h
@@ -0,0 +1,33 @@
+/* arch/arm/mach-xilinx/include/mach/io.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_IO_H__
+#define __MACH_IO_H__
+
+/* Allow IO space to be anywhere in the memory */
+
+#define IO_SPACE_LIMIT 0xffff
+
+/* IO address mapping macros, nothing special at this time but required */
+
+#ifdef __ASSEMBLER__
+#define IOMEM(x) (x)
+#else
+#define IOMEM(x) ((void __force __iomem *)(x))
+#endif
+
+#define __io(a) __typesafe_io(a)
+#define __mem_pci(a) (a)
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/irqs.h b/arch/arm/mach-xilinx/include/mach/irqs.h
new file mode 100644
index 0000000..47a8162
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/irqs.h
@@ -0,0 +1,29 @@
+/* arch/arm/mach-xilinx/include/mach/irqs.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define ARCH_NR_GPIOS 118
+#define NR_IRQS (128 + ARCH_NR_GPIOS)
+
+/*
+ * GIC Interrupts
+ */
+
+#define IRQ_GIC_SPI_START 32
+#define IRQ_TIMERCOUNTER0 42
+#define IRQ_UART0 59
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/memory.h b/arch/arm/mach-xilinx/include/mach/memory.h
new file mode 100644
index 0000000..3efde15
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/memory.h
@@ -0,0 +1,23 @@
+/* arch/arm/mach-xilinx/include/mach/memory.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_MEMORY_H__
+#define __MACH_MEMORY_H__
+
+#include <asm/sizes.h>
+
+#define PHYS_OFFSET UL(0x0)
+#define MEM_SIZE SZ_256M
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/system.h b/arch/arm/mach-xilinx/include/mach/system.h
new file mode 100644
index 0000000..e8514a0
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/system.h
@@ -0,0 +1,28 @@
+/* arch/arm/mach-xilinx/include/mach/system.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_SYSTEM_H__
+#define __MACH_SYSTEM_H__
+
+static inline void arch_idle(void)
+{
+ cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+ /* Add architecture specific reset processing here */
+}
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/timex.h b/arch/arm/mach-xilinx/include/mach/timex.h
new file mode 100644
index 0000000..4ebc0a6
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/timex.h
@@ -0,0 +1,22 @@
+/* arch/arm/mach-xilinx/include/mach/timex.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_TIMEX_H__
+#define __MACH_TIMEX_H__
+
+#define PERIPHERAL_CLOCK_RATE 2500000
+
+#define CLOCK_TICK_RATE (PERIPHERAL_CLOCK_RATE / 32)
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/uart.h b/arch/arm/mach-xilinx/include/mach/uart.h
new file mode 100644
index 0000000..7fca361
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/uart.h
@@ -0,0 +1,25 @@
+/* arch/arm/mach-xilinx/include/mach/uart.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_UART_H__
+#define __MACH_UART_H__
+
+#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
+#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
+#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
+
+#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
+#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h b/arch/arm/mach-xilinx/include/mach/uncompress.h
new file mode 100644
index 0000000..ff3754c
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/uncompress.h
@@ -0,0 +1,61 @@
+/* arch/arm/mach-xilinx/include/mach/uncompress.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H__
+#define __MACH_UNCOMPRESS_H__
+
+#include <mach/xilinx_soc.h>
+#include <mach/uart.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <mach/io.h>
+
+void arch_decomp_setup(void)
+{
+}
+
+static inline void flush(void)
+{
+ u32 status;
+ /*
+ * Wait while the FIFO is not empty
+ */
+ while (1) {
+ status = __raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET));
+ if (status & UART_SR_TXEMPTY)
+ break;
+ cpu_relax();
+ }
+}
+
+#define arch_decomp_wdog()
+
+static void putc(char ch)
+{
+ u32 status;
+
+ /*
+ * Wait for room in the FIFO, then write the char into the FIFO
+ */
+ while (1) {
+ status = __raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET));
+ if (!(status & UART_SR_TXFULL))
+ break;
+ cpu_relax();
+ }
+
+ __raw_writel(ch, IOMEM(LL_UART_PADDR + UART_FIFO_OFFSET));
+}
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/vmalloc.h b/arch/arm/mach-xilinx/include/mach/vmalloc.h
new file mode 100644
index 0000000..aba20a3
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/* arch/arm/mach-xilinx/include/mach/vmalloc.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_VMALLOC_H__
+#define __MACH_VMALLOC_H__
+
+#define VMALLOC_END 0xE0000000UL
+
+#endif
diff --git a/arch/arm/mach-xilinx/include/mach/xilinx_soc.h b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
new file mode 100644
index 0000000..d01cde1
--- /dev/null
+++ b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h
@@ -0,0 +1,46 @@
+/* arch/arm/mach-xilinx/include/mach/xilinx_soc.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_XILINX_SOC_H__
+#define __MACH_XILINX_SOC_H__
+
+/* For now, all mappings are flat (physical = virtual)
+ */
+#define UART0_PHYS 0xE0000000
+#define UART0_VIRT UART0_PHYS
+
+#define TTC0_PHYS 0xF8001000
+#define TTC0_VIRT TTC0_PHYS
+
+#define PL310_L2CC_PHYS 0xF8F02000
+#define PL310_L2CC_VIRT PL310_L2CC_PHYS
+
+#define SCU_PERIPH_PHYS 0xF8F00000
+#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS
+
+/* The following are intended for the devices that are mapped early */
+
+#define TTC0_BASE IOMEM(TTC0_VIRT)
+#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
+#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100)
+#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000)
+#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT)
+
+/*
+ * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
+ */
+#define LL_UART_PADDR UART0_PHYS
+#define LL_UART_VADDR UART0_VIRT
+
+#endif
--
1.6.2.1
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
^ permalink raw reply related
* [PATCH V4 2/4] ARM: Xilinx: Adding timer support to the platform
From: John Linn @ 2011-02-18 18:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298052881-14591-2-git-send-email-john.linn@xilinx.com>
The timer driver supports the Xilinx PS Timer Counter IP.
Signed-off-by: Kiran Sutariya <kiran.sutariya@einfochips.com>
Signed-off-by: John Linn <john.linn@xilinx.com>
---
V4 Changes
Minor cleanup based on input from Jamie Iles.
Got rid of unused mode.
Removed un-needed initialization.
Made interrupt handler setup unconditional.
V3 Changes
Updates based on Russell Kings' comments
Changed headers to update the license info and remove
the address
V2 Changes
The timer code was changed quite a bit based on review inputs. It
got much smaller and cleaner I think.
Updates based on Russell King's comments
minor cleanups for documentation comments
removed the name from the timer structure
removed interrupt for clock source
moved to using clock functions provided in the kernel
for calculating shift/mult values
removed PM code as generic handles it
Updated based on Jamie Iles's comment
cleaned up ENABLE_MASK which was confusing
now using platform_add_devices() from platform code
moved base_addr to void __iomem pointer
removed stop of the event timer in one shot mode
arch/arm/mach-xilinx/Makefile | 2 +-
arch/arm/mach-xilinx/timer.c | 292 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 293 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-xilinx/timer.c
diff --git a/arch/arm/mach-xilinx/Makefile b/arch/arm/mach-xilinx/Makefile
index 76e9e55..660fb19 100644
--- a/arch/arm/mach-xilinx/Makefile
+++ b/arch/arm/mach-xilinx/Makefile
@@ -3,5 +3,5 @@
#
# Common support
-obj-y := common.o
+obj-y := common.o timer.o
obj-$(CONFIG_MACH_XILINX) += board_ep107.o
diff --git a/arch/arm/mach-xilinx/timer.c b/arch/arm/mach-xilinx/timer.c
new file mode 100644
index 0000000..539a558
--- /dev/null
+++ b/arch/arm/mach-xilinx/timer.c
@@ -0,0 +1,292 @@
+/* arch/arm/mach-xilinx/timer.c
+ *
+ * This file contains driver for the Xilinx PS Timer Counter IP.
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * based on arch/mips/kernel/time.c timer driver
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/types.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/io.h>
+
+#include <asm/mach/time.h>
+#include <mach/xilinx_soc.h>
+
+/*
+ * This driver configures the 2 16-bit count-up timers as follows:
+ *
+ * T1: Timer 1, clocksource for generic timekeeping
+ * T2: Timer 2, clockevent source for hrtimers
+ * T3: Timer 3, <unused>
+ *
+ * The input frequency to the timer module for emulation is 2.5MHz which is
+ * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
+ * the timers are clocked at 78.125KHz (12.8 us resolution).
+ *
+ * The input frequency to the timer module in silicon will be 200MHz. With the
+ * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
+ */
+#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */
+#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */
+
+#define XTTCPSS_TIMER_BASE TTC0_BASE
+#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1)
+/*
+ * Timer Register Offset Definitions of Timer 1, Increment base address by 4
+ * and use same offsets for Timer 2
+ */
+#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
+#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
+#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
+#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
+#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */
+#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */
+#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */
+#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
+#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
+
+#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1
+
+/**
+ * struct xttcpss_timer - This definition defines local timer structure
+ *
+ * @base_addr: Base address of timer
+ **/
+struct xttcpss_timer {
+ void __iomem *base_addr;
+};
+
+static struct xttcpss_timer timers[2];
+static struct clock_event_device xttcpss_clockevent;
+
+/**
+ * xttcpss_set_interval - Set the timer interval value
+ *
+ * @timer: Pointer to the timer instance
+ * @cycles: Timer interval ticks
+ **/
+static void xttcpss_set_interval(struct xttcpss_timer *timer,
+ unsigned long cycles)
+{
+ u32 ctrl_reg;
+
+ /* Disable the counter, set the counter value and re-enable counter */
+ ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+ ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+ __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+
+ __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
+
+ /* Reset the counter (0x10) so that it starts from 0, one-shot
+ mode makes this needed for timing to be right. */
+ ctrl_reg |= 0x10;
+ ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+ __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+}
+
+/**
+ * xttcpss_clock_event_interrupt - Clock event timer interrupt handler
+ *
+ * @irq: IRQ number of the Timer
+ * @dev_id: void pointer to the xttcpss_timer instance
+ *
+ * returns: Always IRQ_HANDLED - success
+ **/
+static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = &xttcpss_clockevent;
+ struct xttcpss_timer *timer = dev_id;
+
+ /* Acknowledge the interrupt and call event handler */
+ __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
+ timer->base_addr + XTTCPSS_ISR_OFFSET);
+
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction event_timer_irq = {
+ .name = "xttcpss clockevent",
+ .flags = IRQF_DISABLED | IRQF_TIMER,
+ .handler = xttcpss_clock_event_interrupt,
+};
+
+/**
+ * xttcpss_timer_hardware_init - Initialize the timer hardware
+ *
+ * Initialize the hardware to start the clock source, get the clock
+ * event timer ready to use, and hook up the interrupt.
+ **/
+static void __init xttcpss_timer_hardware_init(void)
+{
+ /* Setup the clock source counter to be an incrementing counter
+ * with no interrupt and it rolls over at 0xFFFF. Pre-scale
+ it by 32 also. Let it start running now.
+ */
+ timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
+
+ __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
+ XTTCPSS_IER_OFFSET);
+ __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
+ XTTCPSS_CLK_CNTRL_OFFSET);
+ __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
+ XTTCPSS_CNT_CNTRL_OFFSET);
+
+ /* Setup the clock event timer to be an interval timer which
+ * is prescaled by 32 using the interval interrupt. Leave it
+ * disabled for now.
+ */
+
+ timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
+
+ __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
+ XTTCPSS_CNT_CNTRL_OFFSET);
+ __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
+ XTTCPSS_CLK_CNTRL_OFFSET);
+ __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
+ XTTCPSS_IER_OFFSET);
+
+ /* Setup IRQ the clock event timer */
+ event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
+ setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
+}
+
+/**
+ * __raw_readl_cycles - Reads the timer counter register
+ *
+ * returns: Current timer counter register value
+ **/
+static cycle_t __raw_readl_cycles(struct clocksource *cs)
+{
+ struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
+
+ return (cycle_t)__raw_readl(timer->base_addr +
+ XTTCPSS_COUNT_VAL_OFFSET);
+}
+
+
+/*
+ * Instantiate and initialize the clock source structure
+ */
+static struct clocksource clocksource_xttcpss = {
+ .name = "xttcpss_timer1",
+ .rating = 200, /* Reasonable clock source */
+ .read = __raw_readl_cycles,
+ .mask = CLOCKSOURCE_MASK(16),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+
+/**
+ * xttcpss_set_next_event - Sets the time interval for next event
+ *
+ * @cycles: Timer interval ticks
+ * @evt: Address of clock event instance
+ *
+ * returns: Always 0 - success
+ **/
+static int xttcpss_set_next_event(unsigned long cycles,
+ struct clock_event_device *evt)
+{
+ struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
+
+ xttcpss_set_interval(timer, cycles);
+ return 0;
+}
+
+/**
+ * xttcpss_set_mode - Sets the mode of timer
+ *
+ * @mode: Mode to be set
+ * @evt: Address of clock event instance
+ **/
+static void xttcpss_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+{
+ struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
+ u32 ctrl_reg;
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ xttcpss_set_interval(timer, CLOCK_TICK_RATE / HZ);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ ctrl_reg = __raw_readl(timer->base_addr +
+ XTTCPSS_CNT_CNTRL_OFFSET);
+ ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+ __raw_writel(ctrl_reg,
+ timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+ break;
+ case CLOCK_EVT_MODE_RESUME:
+ ctrl_reg = __raw_readl(timer->base_addr +
+ XTTCPSS_CNT_CNTRL_OFFSET);
+ ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+ __raw_writel(ctrl_reg,
+ timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+ break;
+ }
+}
+
+/*
+ * Instantiate and initialize the clock event structure
+ */
+static struct clock_event_device xttcpss_clockevent = {
+ .name = "xttcpss_timer2",
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .set_next_event = xttcpss_set_next_event,
+ .set_mode = xttcpss_set_mode,
+ .rating = 200,
+};
+
+/**
+ * xttcpss_timer_init - Initialize the timer
+ *
+ * Initializes the timer hardware and register the clock source and clock event
+ * timers with Linux kernal timer framework
+ **/
+static void __init xttcpss_timer_init(void)
+{
+ xttcpss_timer_hardware_init();
+ clocksource_register_hz(&clocksource_xttcpss, CLOCK_TICK_RATE);
+
+ /* Calculate the parameters to allow the clockevent to operate using
+ integer math
+ */
+ clockevents_calc_mult_shift(&xttcpss_clockevent, CLOCK_TICK_RATE, 4);
+
+ xttcpss_clockevent.max_delta_ns =
+ clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
+ xttcpss_clockevent.min_delta_ns =
+ clockevent_delta2ns(1, &xttcpss_clockevent);
+
+ /* Indicate that clock event can be used on any of the CPUs */
+
+ xttcpss_clockevent.cpumask = cpu_all_mask;
+ clockevents_register_device(&xttcpss_clockevent);
+}
+
+/*
+ * Instantiate and initialize the system timer structure
+ */
+struct sys_timer xttcpss_sys_timer = {
+ .init = xttcpss_timer_init,
+};
--
1.6.2.1
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* [PATCH V4 1/4] ARM: Xilinx: Adding Xilinx board support
From: John Linn @ 2011-02-18 18:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298052881-14591-1-git-send-email-john.linn@xilinx.com>
The 1st board support is minimal to get a system up and running
on the Xilinx platform.
Signed-off-by: John Linn <john.linn@xilinx.com>
---
V4 Changes
Minor cleanup based on input from Jamie Iles.
V3 Changes
Updates based on Russell Kings' comments
Changed headers to update the license info and remove
the address
Changed the name of functions to include "xilinx" in
common.c and common.h
Changed the Kconfig and Makefile to use MACH_XILINX which
matches the machine registered.
V2 Changes
Updates based on Russell King's comments
minor cleanups
cleaned up physical/virtual addresses in early i/o table
arch/arm/mach-xilinx/Kconfig | 14 +++++
arch/arm/mach-xilinx/Makefile | 7 ++
arch/arm/mach-xilinx/Makefile.boot | 3 +
arch/arm/mach-xilinx/board_ep107.c | 82 ++++++++++++++++++++++++++
arch/arm/mach-xilinx/common.c | 113 ++++++++++++++++++++++++++++++++++++
arch/arm/mach-xilinx/common.h | 30 ++++++++++
6 files changed, 249 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-xilinx/Kconfig
create mode 100644 arch/arm/mach-xilinx/Makefile
create mode 100644 arch/arm/mach-xilinx/Makefile.boot
create mode 100644 arch/arm/mach-xilinx/board_ep107.c
create mode 100644 arch/arm/mach-xilinx/common.c
create mode 100644 arch/arm/mach-xilinx/common.h
diff --git a/arch/arm/mach-xilinx/Kconfig b/arch/arm/mach-xilinx/Kconfig
new file mode 100644
index 0000000..61532af
--- /dev/null
+++ b/arch/arm/mach-xilinx/Kconfig
@@ -0,0 +1,14 @@
+if ARCH_XILINX
+
+choice
+ prompt "Board Selection"
+ default MACH_XILINX
+
+config MACH_XILINX
+ bool "Xilinx EP107 Board"
+ help
+ Select if you are using a Xilinx EP107 board.
+
+endchoice
+
+endif
diff --git a/arch/arm/mach-xilinx/Makefile b/arch/arm/mach-xilinx/Makefile
new file mode 100644
index 0000000..76e9e55
--- /dev/null
+++ b/arch/arm/mach-xilinx/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common support
+obj-y := common.o
+obj-$(CONFIG_MACH_XILINX) += board_ep107.o
diff --git a/arch/arm/mach-xilinx/Makefile.boot b/arch/arm/mach-xilinx/Makefile.boot
new file mode 100644
index 0000000..67039c3
--- /dev/null
+++ b/arch/arm/mach-xilinx/Makefile.boot
@@ -0,0 +1,3 @@
+ zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-xilinx/board_ep107.c b/arch/arm/mach-xilinx/board_ep107.c
new file mode 100644
index 0000000..a1635b5
--- /dev/null
+++ b/arch/arm/mach-xilinx/board_ep107.c
@@ -0,0 +1,82 @@
+/* arch/arm/mach-xilinx/board_ep107.c
+ *
+ * This file contains code specific to the Xilinx EP107 board.
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * based on /arch/arm/mach-realview/core.c
+ *
+ * Copyright (C) 1999 - 2003 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/xilinx_soc.h>
+#include <mach/irqs.h>
+#include <linux/clkdev.h>
+#include "common.h"
+
+/*
+ * Fixed clocks for now
+ */
+
+static struct clk ref50_clk = {
+ .rate = 50000000,
+};
+
+/* Create all the platform devices for the board */
+
+static struct resource uart0[] = {
+ {
+ .start = UART0_PHYS,
+ .end = UART0_PHYS + 0xFFF,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_UART0,
+ .end = IRQ_UART0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device uart_device0 = {
+ .name = "xuartpss",
+ .id = 0,
+ .dev = {
+ .platform_data = &ref50_clk.rate,
+ },
+ .resource = uart0,
+ .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct platform_device *xilinx_pdevices[] __initdata = {
+ &uart_device0,
+};
+
+/**
+ * board_ep107_init - Board specific initialization for the Xilinx EP107 board.
+ *
+ **/
+static void __init board_ep107_init(void)
+{
+ xilinx_system_init();
+ platform_add_devices(&xilinx_pdevices[0], ARRAY_SIZE(xilinx_pdevices));
+}
+
+MACHINE_START(XILINX_EP107, "Xilinx EP107")
+ .boot_params = PHYS_OFFSET + 0x00000100,
+ .map_io = xilinx_map_io,
+ .init_irq = xilinx_irq_init,
+ .init_machine = board_ep107_init,
+ .timer = &xttcpss_sys_timer,
+MACHINE_END
diff --git a/arch/arm/mach-xilinx/common.c b/arch/arm/mach-xilinx/common.c
new file mode 100644
index 0000000..564b707
--- /dev/null
+++ b/arch/arm/mach-xilinx/common.c
@@ -0,0 +1,113 @@
+/* arch/arm/mach-xilinx/common.c
+ *
+ * This file contains common code that is intended to be used across
+ * boards so that it's not replicated.
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/cpumask.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+#include <asm/mach/map.h>
+#include <asm/page.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/xilinx_soc.h>
+#include <mach/clkdev.h>
+
+/*
+ * Clock function infrastructure.
+ */
+int clk_enable(struct clk *clk)
+{
+ return 0;
+}
+
+void clk_disable(struct clk *clk)
+{
+}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+
+/**
+ * system_init - System specific initialization, intended to be called from
+ * board specific initialization.
+ *
+ **/
+void __init xilinx_system_init(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+ /*
+ * 64KB way size, 8-way associativity, parity disabled
+ */
+ l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF);
+#endif
+}
+
+/**
+ * irq_init - Interrupt controller initialization for the GIC.
+ *
+ **/
+void __init xilinx_irq_init(void)
+{
+ gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE);
+}
+
+/* The minimum devices needed to be mapped before the VM system is up and
+ * running include the GIC, UART and Timer Counter.
+ */
+
+static struct map_desc io_desc[] __initdata = {
+ {
+ .virtual = TTC0_VIRT,
+ .pfn = __phys_to_pfn(TTC0_PHYS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = SCU_PERIPH_VIRT,
+ .pfn = __phys_to_pfn(SCU_PERIPH_PHYS),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = PL310_L2CC_VIRT,
+ .pfn = __phys_to_pfn(PL310_L2CC_PHYS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+
+#ifdef CONFIG_DEBUG_LL
+ {
+ .virtual = UART0_VIRT,
+ .pfn = __phys_to_pfn(UART0_PHYS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+#endif
+
+};
+
+/**
+ * map_io - Create memory mappings needed for early I/O.
+ *
+ **/
+void __init xilinx_map_io(void)
+{
+ iotable_init(io_desc, ARRAY_SIZE(io_desc));
+}
diff --git a/arch/arm/mach-xilinx/common.h b/arch/arm/mach-xilinx/common.h
new file mode 100644
index 0000000..71f4ebc
--- /dev/null
+++ b/arch/arm/mach-xilinx/common.h
@@ -0,0 +1,30 @@
+/* arch/arm/mach-xilinx/common.h
+ *
+ * This file contains common function prototypes to avoid externs
+ * in the c files.
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_XILINX_COMMON_H__
+#define __MACH_XILINX_COMMON_H__
+
+#include <linux/init.h>
+#include <asm/mach/time.h>
+
+void __init xilinx_system_init(void);
+void __init xilinx_irq_init(void);
+void __init xilinx_map_io(void);
+
+extern struct sys_timer xttcpss_sys_timer;
+
+#endif
--
1.6.2.1
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
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* [PATCH V4 0/4] ARM: Basic Xilinx Support
From: John Linn @ 2011-02-18 18:14 UTC (permalink / raw)
To: linux-arm-kernel
V4
I incorporated more feedback from Jamie Iles. It was
primariy cleanup with the only significant change
being a move to using raw_read/write in the uncompressor
uart code.
The other changes were minor updates so that the patch
set applies to linux-next.
This patch set is now tested against the linux-next branch
from pub/scm/linux/kernel/git/sfr/linux-next.git.
V3
I incorporated more feedback from Russell King.
Primarily clean up of the license header to remove
the address.
Also minor cleanup of the Kconfig and Makefile for the board
to match the MACH_XILINX entry in the machine ID database.
These changes were tested on 2.6.38-rc4 and rc5.
V2
I incorporated review comments from Russell King and Jamie Iles.
Each patch has V2 comments describing the details. The order of
each patch in the series did change.
Thanks a lot to them for the detailed review as this patch set
is much cleaner and improved (I think anyway).
Thanks for comments from Arnd and Grant also.
This was tested against 2.6.38-rc4.
----
This patch series adds very basic support for the Xilinx ARM platform.
The entire patch set must be used, I only broke it up into logical
pieces to make the review easier (I hope).
I would like to get the review feedback and make any changes, but after
that I need to change mach-xilinx to the real product name. The real
product name is expected to be released by marketing very soon.
There's always the option of keeping mach-xilinx and then only
documenting the product name in the Kconfig. I'm less in favor of that
but it could be ok.
This code has been tested against 2.6.38-rc2, r3, and against head. The
only checkpatch warnings are about volatile in the uncompress.h file
and this method I used seems normal.
Thanks,
John
arch/arm/Kconfig | 14 +
arch/arm/Makefile | 1
arch/arm/mach-xilinx/Kconfig | 14 +
arch/arm/mach-xilinx/Makefile | 9
arch/arm/mach-xilinx/Makefile.boot | 3
arch/arm/mach-xilinx/board_ep107.c | 82 ++++++
arch/arm/mach-xilinx/common.c | 113 +++++++++
arch/arm/mach-xilinx/common.h | 31 ++
arch/arm/mach-xilinx/include/mach/clkdev.h | 33 ++
arch/arm/mach-xilinx/include/mach/debug-macro.S | 36 ++
arch/arm/mach-xilinx/include/mach/entry-macro.S | 30 ++
arch/arm/mach-xilinx/include/mach/hardware.h | 18 +
arch/arm/mach-xilinx/include/mach/io.h | 33 ++
arch/arm/mach-xilinx/include/mach/irqs.h | 29 ++
arch/arm/mach-xilinx/include/mach/memory.h | 23 +
arch/arm/mach-xilinx/include/mach/system.h | 28 ++
arch/arm/mach-xilinx/include/mach/timex.h | 22 +
arch/arm/mach-xilinx/include/mach/uart.h | 25 ++
arch/arm/mach-xilinx/include/mach/uncompress.h | 61 ++++
arch/arm/mach-xilinx/include/mach/vmalloc.h | 20 +
arch/arm/mach-xilinx/include/mach/xilinx_soc.h | 47 +++
arch/arm/mach-xilinx/timer.c | 293 +++++++++++++++++++++++-
arch/arm/mm/Kconfig | 3
23 files changed, 962 insertions(+), 6 deletions(-)
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^ permalink raw reply
* [PATCH 2/5] omap4: Enable ARM local timers with OMAP4430 es1.0 exception
From: Santosh Shilimkar @ 2011-02-18 18:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297510187-31547-3-git-send-email-santosh.shilimkar@ti.com>
> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
> Sent: Saturday, February 12, 2011 5:00 PM
> To: linux-omap at vger.kernel.org
> Cc: khilman at ti.com; linux-arm-kernel at lists.infradead.org;
> tony at atomide.com; Santosh Shilimkar
> Subject: [PATCH 2/5] omap4: Enable ARM local timers with OMAP4430
> es1.0 exception
>
[....]
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-
> omap2/Kconfig
> index 1a2cf62..f285dd7 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -44,6 +44,7 @@ config ARCH_OMAP4
> depends on ARCH_OMAP2PLUS
> select CPU_V7
> select ARM_GIC
> + select LOCAL_TIMERS
This change should be 'select LOCAL_TIMERS if SMP'
Otherwise, with !SMP, the build will break.
Here is the updated version with Tony's ack added.
--------
^ permalink raw reply
* [PATCH] perf: add OMAP support for the new power events
From: jean.pihet at newoldbits.com @ 2011-02-18 18:10 UTC (permalink / raw)
To: linux-arm-kernel
From: Jean Pihet <j-pihet@ti.com>
The patch adds the new power management trace points for
the OMAP architecture.
The trace points are for:
- default idle handler. Since the cpuidle framework is
instrumented in the generic way there is no need to
add trace points in the OMAP specific cpuidle handler;
- cpufreq (DVFS),
- SoC clocks changes (enable, disable, set_rate),
- power domain states: the desired target state and -if different-
the actually hit state.
Because of the generic nature of the changes, OMAP3 and OMAP4 are supported.
Tested on OMAP3 with suspend/resume, cpuidle, basic DVFS.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
---
arch/arm/mach-omap2/clock.c | 8 +++++++-
arch/arm/mach-omap2/pm34xx.c | 7 +++++++
arch/arm/mach-omap2/powerdomain.c | 26 +++++++++++++++++++++++---
3 files changed, 37 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 2a2f152..72af75d 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -22,7 +22,9 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/bitops.h>
+#include <trace/events/power.h>
+#include <asm/cpu.h>
#include <plat/clock.h>
#include "clockdomain.h"
#include <plat/cpu.h>
@@ -261,6 +263,7 @@ void omap2_clk_disable(struct clk *clk)
pr_debug("clock: %s: disabling in hardware\n", clk->name);
+ trace_clock_disable(clk->name, 0, smp_processor_id());
clk->ops->disable(clk);
if (clk->clkdm)
@@ -312,6 +315,7 @@ int omap2_clk_enable(struct clk *clk)
}
}
+ trace_clock_enable(clk->name, 1, smp_processor_id());
ret = clk->ops->enable(clk);
if (ret) {
WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret);
@@ -349,8 +353,10 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
- if (clk->set_rate)
+ if (clk->set_rate) {
+ trace_clock_set_rate(clk->name, rate, smp_processor_id());
ret = clk->set_rate(clk, rate);
+ }
return ret;
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2f864e4..d1cc3f4 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -29,6 +29,7 @@
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/console.h>
+#include <trace/events/power.h>
#include <plat/sram.h>
#include "clockdomain.h"
@@ -519,8 +520,14 @@ static void omap3_pm_idle(void)
if (omap_irq_pending() || need_resched())
goto out;
+ trace_power_start(POWER_CSTATE, 1, smp_processor_id());
+ trace_cpu_idle(1, smp_processor_id());
+
omap_sram_idle();
+ trace_power_end(smp_processor_id());
+ trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
+
out:
local_fiq_enable();
local_irq_enable();
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index eaed0df..1495eed 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -19,12 +19,15 @@
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/string.h>
+#include <trace/events/power.h>
+
#include "cm2xxx_3xxx.h"
#include "prcm44xx.h"
#include "cm44xx.h"
#include "prm2xxx_3xxx.h"
#include "prm44xx.h"
+#include <asm/cpu.h>
#include <plat/cpu.h>
#include "powerdomain.h"
#include "clockdomain.h"
@@ -32,6 +35,8 @@
#include "pm.h"
+#define PWRDM_TRACE_STATES_FLAG (1<<31)
+
enum {
PWRDM_STATE_NOW = 0,
PWRDM_STATE_PREV,
@@ -130,8 +135,7 @@ static void _update_logic_membank_counters(struct powerdomain *pwrdm)
static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
{
- int prev;
- int state;
+ int prev, state, trace_state = 0;
if (pwrdm == NULL)
return -EINVAL;
@@ -148,6 +152,17 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
pwrdm->state_counter[prev]++;
if (prev == PWRDM_POWER_RET)
_update_logic_membank_counters(pwrdm);
+ /*
+ * If the power domain did not hit the desired state,
+ * generate a trace event with both the desired and hit states
+ */
+ if (state != prev) {
+ trace_state = (PWRDM_TRACE_STATES_FLAG |
+ ((state & OMAP_POWERSTATE_MASK) << 8) |
+ ((prev & OMAP_POWERSTATE_MASK) << 0));
+ trace_power_domain_target(pwrdm->name, trace_state,
+ smp_processor_id());
+ }
break;
default:
return -EINVAL;
@@ -406,8 +421,13 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
pwrdm->name, pwrst);
- if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst)
+ if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
+ /* Trace the pwrdm desired target state */
+ trace_power_domain_target(pwrdm->name, pwrst,
+ smp_processor_id());
+ /* Program the pwrdm desired target state */
ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
+ }
return ret;
}
--
1.7.2.3
^ permalink raw reply related
* [PATCH] ARM: Avoid discarding sections that might have SMP_ON_UP fixups
From: Dave Martin @ 2011-02-18 17:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216163543.GA27480@arm.com>
Hi Russell,
On Wed, Feb 16, 2011 at 4:35 PM, Dave Martin <dave.martin@linaro.org> wrote:
> Hi,
>
> On Fri, Feb 11, 2011 at 04:32:47PM +0000, Russell King - ARM Linux wrote:
>
> [...]
>
>> diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
>> index 45b5651..343d29f 100644
>> --- a/arch/arm/kernel/vmlinux.lds.S
>> +++ b/arch/arm/kernel/vmlinux.lds.S
>> @@ -21,6 +21,12 @@
>> ?#define ARM_CPU_KEEP(x)
>> ?#endif
>>
>> +#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
>> +#define ARM_EXIT_KEEP(x) ? ? x
>> +#else
>> +#define ARM_EXIT_KEEP(x)
>> +#endif
>> +
>> ?OUTPUT_ARCH(arm)
>> ?ENTRY(stext)
>>
>> @@ -43,6 +49,7 @@ SECTIONS
>> ? ? ? ? ? ? ? _sinittext = .;
>> ? ? ? ? ? ? ? ? ? ? ? HEAD_TEXT
>> ? ? ? ? ? ? ? ? ? ? ? INIT_TEXT
>> + ? ? ? ? ? ? ? ? ? ? ARM_EXIT_KEEP(EXIT_TEXT)
>> ? ? ? ? ? ? ? _einittext = .;
>> ? ? ? ? ? ? ? ARM_CPU_DISCARD(PROC_INFO)
>> ? ? ? ? ? ? ? __arch_info_begin = .;
>> @@ -71,6 +78,7 @@ SECTIONS
>> ?#ifndef CONFIG_XIP_KERNEL
>> ? ? ? ? ? ? ? __init_begin = _stext;
>> ? ? ? ? ? ? ? INIT_DATA
>> + ? ? ? ? ? ? ARM_EXIT_KEEP(EXIT_DATA)
>> ?#endif
>> ? ? ? }
>>
>> @@ -166,6 +174,7 @@ SECTIONS
>> ? ? ? ? ? ? ? . = ALIGN(PAGE_SIZE);
>> ? ? ? ? ? ? ? __init_begin = .;
>> ? ? ? ? ? ? ? INIT_DATA
>> + ? ? ? ? ? ? ARM_EXIT_KEEP(EXIT_DATA)
>> ? ? ? ? ? ? ? . = ALIGN(PAGE_SIZE);
>> ? ? ? ? ? ? ? __init_end = .;
>> ?#endif
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> This works for me in a case known to fail without the patch.
>
> Tested-by: Dave Martin <dave.martin@linaro.org>
>
> I still don't quite understand the intricacies of how vmlinux
> is laid out, but the patch looks sensible.
>
> Do you need anything more from me on this? ?If not, I will
> throw away my patch and replace it with yours.
Are you still intending to merge your patch here? I don't see it
anywhere yet, but I would like to get rid of my hack (which is rather
messy).
Cheers
---Dave
^ permalink raw reply
* [PATCH 16/17] mc13xxx: mfd_cell is now implicitly available to drivers
From: Andres Salomon @ 2011-02-18 17:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110218083928.GU22310@pengutronix.de>
On Fri, 18 Feb 2011 09:39:28 +0100
Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de> wrote:
> On Wed, Feb 16, 2011 at 09:00:36AM -0800, Andres Salomon wrote:
> > On Wed, 16 Feb 2011 10:41:54 +0100
> > Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de> wrote:
> >
> > > On Fri, Feb 11, 2011 at 06:19:21PM -0800, Andres Salomon wrote:
> > > >
> > > > The cell's platform_data is now accessed with a helper function;
> > > > change clients to use that, and remove the now-unused data_size.
> > > >
> > > > Note that mfd-core no longer makes a copy of platform_data, but
> > > > the
> > > why was this changed and where? I'm not able to find your
> > > complete series via gmane.
> >
> > http://permalink.gmane.org/gmane.linux.kernel/1099164
> I still don't get the motivation of your patch set. For drivers that
> don't need the mfd_cells you introduce another level of indirection.
> And drivers that want to use mfd_cells as platform_data, they can
> already now.
>
> Best regards
> Uwe
>
The main motivation for making mfd_cell available to all was to be able
to provide functions within mfd-core (introduced in later
patches/patchsets) that accept platform devices and operate on their
mfd_cells. The mfd_cell used to be automatically carried by the pdevs,
and I'm not entirely sure the reason for getting rid of that. It also
(imo) cleans up a lot of things. For example, the mfd_cell API
platform_data/driver_data stuff was unclear when I first
encountered it, as various drivers were doing things completely
differently (some incorrectly, as witnessed by some of the drivers
that I modified that were using driver_data and had clients later
calling set_drvdata on the same pdev). This is clearer, and provides
a uniform way to do things that, afaict, sacrifices absolutely no
flexibility or functionality. Yes, it adds some overhead by having a
copy of the mfd_cell around in memory, but if that's really an issue it
could be optimized further by not making a full copy of the mfd_cell.
With the new wrappers (mfd_get_data/mfd_get_cell), this could be done
without having to mess with drivers.
^ permalink raw reply
* [PATCH 4/4] mtd: OneNAND: OMAP2: increase multiblock erase verify timeout
From: Tony Lindgren @ 2011-02-18 17:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298003498.2735.4.camel@localhost>
* Artem Bityutskiy <dedekind1@gmail.com> [110217 20:31]:
> Hi,
>
> On Thu, 2011-02-17 at 15:46 -0800, Tony Lindgren wrote:
> > * Adrian Hunter <adrian.hunter@nokia.com> [110207 00:45]:
> > > From: Roman Tereshonkov <roman.tereshonkov@nokia.com>
> > >
> > > The current multiblock erase verify read timeout 100us is the maximum
> > > for none-error case. If errors happen during multibock erase then
> > > the specification recommends to run multiblock erase verify command
> > > with maximum timeout 10ms (see specs. for KFM4G16Q2A and KFN8G16Q2A).
> > >
> > > For the most common non-error case we wait 100us in udelay polling
> > > loop. In case of timeout the interrupt mode is used to wait for the
> > > command end.
> > >
> > > Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com>
> >
> > I'll queue this series. Anybody from MTD list care to ack this patch?
>
> Acked-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Thanks!
Tony
^ permalink raw reply
* [PATCH 1/3] OMAP2+: hwmod: Avoid setup if clock lookup failed
From: Cousson, Benoit @ 2011-02-18 17:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297858285-7056-2-git-send-email-rnayak@ti.com>
On 2/16/2011 1:11 PM, Nayak, Rajendra wrote:
> Add a hwmod state check in the _setup function
> to avoid setting up hwmods' for which clock
> lookup has failed.
>
> Signed-off-by: Rajendra Nayak<rnayak@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod.c | 6 ++++++
> 1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index e282e35..cd9dcde 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -1362,6 +1362,12 @@ static int _setup(struct omap_hwmod *oh, void *data)
> int i, r;
> u8 postsetup_state;
>
> + if (oh->_state != _HWMOD_STATE_CLKS_INITED) {
> + WARN(1, "omap_hwmod: %s: _setup failed as one or more"
> + "clock lookups' have failed\n", oh->name);
Maybe a pr_warning will be enough for that?
> + return -EINVAL;
As discussed previously I'd prefer to return 0 here since we do not want
to break the iteration.
> + }
> +
> /* Set iclk autoidle mode */
> if (oh->slaves_cnt> 0) {
> for (i = 0; i< oh->slaves_cnt; i++) {
Otherwise it is fine for me.
Thanks,
Benoit
^ permalink raw reply
* [PATCH 2/2] arm: mxs: add i2c-devices
From: Wolfram Sang @ 2011-02-18 17:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298049507-6987-1-git-send-email-w.sang@pengutronix.de>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-mxs/devices-mx28.h | 3 +
arch/arm/mach-mxs/devices/Kconfig | 3 +
arch/arm/mach-mxs/devices/Makefile | 1 +
arch/arm/mach-mxs/devices/platform-i2c.c | 56 +++++++++++++++++++++++
arch/arm/mach-mxs/include/mach/devices-common.h | 9 ++++
5 files changed, 72 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-mxs/devices/platform-i2c.c
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 3b18304..c581b26 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -32,3 +32,6 @@ extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
mxs_add_flexcan(&mx28_flexcan_data[id], pdata)
#define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata)
#define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata)
+
+extern const struct mxs_i2c_data mx28_i2c_data[] __initconst;
+#define mx28_add_i2c(id) mxs_add_i2c(&mx28_i2c_data[id])
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index 6c65b67..c9f80e1 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -11,3 +11,6 @@ config MXS_HAVE_PLATFORM_FEC
config MXS_HAVE_PLATFORM_FLEXCAN
select HAVE_CAN_FLEXCAN if CAN
bool
+
+config MXS_HAVE_PLATFORM_I2C
+ bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index a8dc8d5..4fb4d9a 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_I2C) += platform-i2c.o
diff --git a/arch/arm/mach-mxs/devices/platform-i2c.c b/arch/arm/mach-mxs/devices/platform-i2c.c
new file mode 100644
index 0000000..22236b2
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-i2c.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2011 Pengutronix
+ * Wolfram Sang <w.sang@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+
+/* helper defines to fix MX23 naming anomaly */
+#define MX23_I2C0_BASE_ADDR MX23_I2C_BASE_ADDR
+#define MX23_INT_I2C0_ERROR MX23_INT_I2C_ERROR
+#define MX23_INT_I2C0_DMA MX23_INT_I2C_DMA
+
+#define mxs_i2c_data_entry_single(soc, _id) \
+ { \
+ .id = _id, \
+ .iobase = soc ## _I2C ## _id ## _BASE_ADDR, \
+ .errirq = soc ## _INT_I2C ## _id ## _ERROR, \
+ .dmairq = soc ## _INT_I2C ## _id ## _DMA, \
+ }
+
+#define mxs_i2c_data_entry(soc, _id) \
+ [_id] = mxs_i2c_data_entry_single(soc, _id)
+
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_i2c_data mx28_i2c_data[] __initconst = {
+ mxs_i2c_data_entry(MX28, 0),
+ mxs_i2c_data_entry(MX28, 1),
+};
+#endif
+
+struct platform_device *__init mxs_add_i2c(const struct mxs_i2c_data *data)
+{
+ struct resource res[] = {
+ {
+ .start = data->iobase,
+ .end = data->iobase + SZ_8K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = data->errirq,
+ .end = data->errirq,
+ .flags = IORESOURCE_IRQ,
+ }, {
+ .start = data->dmairq,
+ .end = data->dmairq,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ return mxs_add_platform_device("mxs-i2c", data->id, res,
+ ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index e7aefb4..e385ece 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -63,3 +63,12 @@ struct mxs_flexcan_data {
struct platform_device *__init mxs_add_flexcan(
const struct mxs_flexcan_data *data,
const struct flexcan_platform_data *pdata);
+
+/* i2c */
+struct mxs_i2c_data {
+ int id;
+ resource_size_t iobase;
+ resource_size_t errirq;
+ resource_size_t dmairq;
+};
+struct platform_device * __init mxs_add_i2c(const struct mxs_i2c_data *data);
--
1.7.2.3
^ permalink raw reply related
* [PATCH 1/2] arm: mx23: names of interrupts and base address should match for I2C
From: Wolfram Sang @ 2011-02-18 17:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298049507-6987-1-git-send-email-w.sang@pengutronix.de>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-mxs/include/mach/mx23.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
index 4768402..9b610b1 100644
--- a/arch/arm/mach-mxs/include/mach/mx23.h
+++ b/arch/arm/mach-mxs/include/mach/mx23.h
@@ -57,7 +57,7 @@
#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000)
#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000)
#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000)
-#define MX23_I2C0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000)
+#define MX23_I2C_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000)
#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000)
#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000)
#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000)
--
1.7.2.3
^ permalink raw reply related
* [PATCH 0/2] mach-mxs: dynamic device creation for i.MX28-i2c
From: Wolfram Sang @ 2011-02-18 17:18 UTC (permalink / raw)
To: linux-arm-kernel
Currently for mx28 only, because the driver submitted for mainline does only
PIOQUEUE which is only available on that cpu. mx23 can be added if support is
available.
Patches are based on imx-for-2.6.39.
Wolfram Sang (2):
arm: mx23: names of interrupts and base address should match for I2C
arm: mxs: add i2c-devices
arch/arm/mach-mxs/devices-mx28.h | 3 +
arch/arm/mach-mxs/devices/Kconfig | 3 +
arch/arm/mach-mxs/devices/Makefile | 1 +
arch/arm/mach-mxs/devices/platform-i2c.c | 56 +++++++++++++++++++++++
arch/arm/mach-mxs/include/mach/devices-common.h | 9 ++++
arch/arm/mach-mxs/include/mach/mx23.h | 2 +-
6 files changed, 73 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-mxs/devices/platform-i2c.c
--
1.7.2.3
^ permalink raw reply
* [PATCH 1/2] PRUSS UIO driver support
From: Greg KH @ 2011-02-18 17:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110218163147.GD4684@local>
On Fri, Feb 18, 2011 at 05:31:47PM +0100, Hans J. Koch wrote:
> On Fri, Feb 18, 2011 at 08:35:29PM +0530, Pratheesh Gangadhar wrote:
> > Signed-off-by: Pratheesh Gangadhar <pratheesh@ti.com>
As noted by others, this needs to go at the end of the changelog
comment.
Also, always run your patches through the scripts/checkpatch.pl script
and fix the warnings and errors it finds. To not do so is just rude as
you are asking us to do the basic review work that you yourself did not
do in the first place.
> > +static irqreturn_t pruss_handler(int irq, struct uio_info *dev_info)
> > +{
> > + return IRQ_HANDLED;
> > +}
>
> ROTFL. That reminds me of an old story. The last time I wrote this, and
> Greg dared to post it, we received this reply:
>
> http://marc.info/?l=linux-kernel&m=116604101232144&w=2
>
> So, if you really have a _very_ good reason why this _always_ works on
> _any_ DA850 board, add a comment that explains why. Otherwise the whole
> patch set will be doomed.
Nope, this whole patch set is doomed if this isn't fixed, I'm not going
to accept it no matter how much you want to try to say this is ok on
this hardware.
thanks,
greg k-h
^ permalink raw reply
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