* [PATCH V4 0/4] ARM: Basic Xilinx Support
From: Jamie Iles @ 2011-02-28 11:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0d410c20-32b4-46d6-9639-249a2816cbe9@VA3EHSMHS005.ehs.local>
On Fri, Feb 18, 2011 at 11:14:37AM -0700, John Linn wrote:
>
> V4
>
> I incorporated more feedback from Jamie Iles. It was
> primariy cleanup with the only significant change
> being a move to using raw_read/write in the uncompressor
> uart code.
>
> The other changes were minor updates so that the patch
> set applies to linux-next.
>
> This patch set is now tested against the linux-next branch
> from pub/scm/linux/kernel/git/sfr/linux-next.git.
Hi John,
I've just tried a quick dummy build of this series (with a fudge in
mach-types to get it building) and I see a couple of minor sparse
warnings:
arch/arm/mach-xilinx/common.c:54:13: warning: symbol
'xilinx_system_init' was not declared. Should it be static?
arch/arm/mach-xilinx/common.c:68:13: warning: symbol 'xilinx_irq_init'
was not declared. Should it be static?
arch/arm/mach-xilinx/common.c:110:13: warning: symbol 'xilinx_map_io'
was not declared. Should it be static?
arch/arm/mach-xilinx/timer.c:290:18: warning: symbol 'xttcpss_sys_timer'
was not declared. Should it be static?
I think all of these can be resolved by including "common.h" in both
timer.c and common.c.
I've put a couple of nitpicks for the individual patches, sorry I didn't
spot them before. Otherwise,
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Jamie
^ permalink raw reply
* [PATCH] ARM: EXYNOS4: Adds Samsung NURI board support
From: Kukjin Kim @ 2011-02-28 11:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <002801cbd721$42e4bad0$c8ae3070$%kim@samsung.com>
Kukjin Kim wrote:
>
> Minkyu Kang wrote:
> >
> > Dear Kukjin Kim,
> >
> > 2011-02-28 ?? 4:42, Kukjin Kim ? ?:
> > > Minkyu Kang wrote:
> > >>
> > >> This patch adds Samsung NURI board support.
> > >>
> > >> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
> > >> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > >> ---
> > >> This patch is base on next-exynos4 branch at kgene tree.
> > >>
> > >> arch/arm/configs/exynos4_defconfig | 1 +
> > >> arch/arm/mach-exynos4/Kconfig | 15 +++
> > >> arch/arm/mach-exynos4/Makefile | 1 +
> > >> arch/arm/mach-exynos4/mach-nuri.c | 233
> > >> ++++++++++++++++++++++++++++++++++++
> > >> 4 files changed, 250 insertions(+), 0 deletions(-)
> > >> create mode 100644 arch/arm/mach-exynos4/mach-nuri.c
> > >>
> > >
> > >> +enum fixed_regulator_id {
> > >> + FIXED_REG_ID_MMC = 0,
> > >
> > > FIXED_REG_ID_MMC,
> > >
> > > (snip)
> > >
> > >> +static struct platform_device emmc_fixed_voltage = {
> > >> + .name = "reg-fixed-voltage",
> > >> + .id = FIXED_REG_ID_MMC,
> > >
> > > Is there any reason to use FIXED_REG_ID_MMC instead directly id 0?
> > >
> >
> > I'm going to add more IDs of fixed regulator that are LCD and Backlight,
> and
> > so on.
> > So use enum values for avoid the hard coding.
> >
>
> Ok, applied this after removing "ifdef WATCHDOG".
Oops, NURI board is not registered yet :(
So can't merge this before updating it now.
Or should drop update defconfig from this...
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [PATCH V4 3/4] ARM: Xilinx: base header files and assembly macros
From: Russell King - ARM Linux @ 2011-02-28 11:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <42efee69-aca1-446b-a997-f0063e113877@VA3EHSMHS009.ehs.local>
On Fri, Feb 18, 2011 at 11:14:40AM -0700, John Linn wrote:
> diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h b/arch/arm/mach-xilinx/include/mach/uncompress.h
> new file mode 100644
> index 0000000..ff3754c
> --- /dev/null
> +++ b/arch/arm/mach-xilinx/include/mach/uncompress.h
> @@ -0,0 +1,61 @@
> +/* arch/arm/mach-xilinx/include/mach/uncompress.h
> + *
> + * Copyright (C) 2011 Xilinx
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __MACH_UNCOMPRESS_H__
> +#define __MACH_UNCOMPRESS_H__
> +
> +#include <mach/xilinx_soc.h>
> +#include <mach/uart.h>
> +#include <asm/processor.h>
> +#include <asm/io.h>
> +#include <mach/io.h>
You don't need mach/io.h here - it's already included by asm/io.h.
It's probably also worth trying linux/io.h instead of asm/io.h too.
^ permalink raw reply
* [PATCH V3 1/4] ARM: imx53_loco: add esdhc device support
From: Richard Zhu @ 2011-02-28 11:25 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
---
arch/arm/mach-mx5/Kconfig | 1 +
arch/arm/mach-mx5/board-mx53_loco.c | 2 ++
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index f065a0d..a72c833 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -162,6 +162,7 @@ config MACH_MX53_LOCO
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX53 LOCO platform. This includes specific
configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 160899e..0a18f8d 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -213,6 +213,8 @@ static void __init mx53_loco_board_init(void)
imx53_add_imx2_wdt(0, NULL);
imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
+ imx53_add_sdhci_esdhc_imx(0, NULL);
+ imx53_add_sdhci_esdhc_imx(2, NULL);
}
static void __init mx53_loco_timer_init(void)
--
1.7.1
^ permalink raw reply related
* [PATCH V3 2/4] ARM: imx51/53: add sdhc3/4 clock
From: Richard Zhu @ 2011-02-28 11:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298892315-23386-1-git-send-email-Hong-Xing.Zhu@freescale.com>
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
---
arch/arm/mach-mx5/clock-mx51-mx53.c | 140 ++++++++++++++++++++++++++++++++++-
arch/arm/mach-mx5/crm_regs.h | 7 ++
2 files changed, 146 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 8164b1d..652ace4 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -42,6 +42,9 @@ static struct clk usboh3_clk;
static struct clk emi_fast_clk;
static struct clk ipu_clk;
static struct clk mipi_hsc1_clk;
+static struct clk esdhc1_clk;
+static struct clk esdhc2_clk;
+static struct clk esdhc3_mx53_clk;
#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
@@ -1143,10 +1146,80 @@ CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
+/* mx51 specific */
CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
+static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &esdhc1_clk)
+ reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+ else if (parent == &esdhc2_clk)
+ reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+ else
+ return -EINVAL;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &esdhc1_clk)
+ reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ else if (parent == &esdhc2_clk)
+ reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ else
+ return -EINVAL;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+/* mx53 specific */
+static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &esdhc1_clk)
+ reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+ else if (parent == &esdhc3_mx53_clk)
+ reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+ else
+ return -EINVAL;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+
+static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &esdhc1_clk)
+ reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ else if (parent == &esdhc3_mx53_clk)
+ reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ else
+ return -EINVAL;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
static struct clk name = { \
.id = i, \
@@ -1251,9 +1324,62 @@ DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
+ NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
+ NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+
+/* mx51 specific */
DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
+static struct clk esdhc3_clk = {
+ .id = 2,
+ .parent = &esdhc1_clk,
+ .set_parent = clk_esdhc3_set_parent,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+ .enable = _clk_max_enable,
+ .disable = _clk_max_disable,
+ .secondary = &esdhc3_ipg_clk,
+};
+static struct clk esdhc4_clk = {
+ .id = 3,
+ .parent = &esdhc1_clk,
+ .set_parent = clk_esdhc4_set_parent,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+ .enable = _clk_max_enable,
+ .disable = _clk_max_disable,
+ .secondary = &esdhc4_ipg_clk,
+};
+
+/* mx53 specific */
+static struct clk esdhc2_mx53_clk = {
+ .id = 2,
+ .parent = &esdhc1_clk,
+ .set_parent = clk_esdhc2_mx53_set_parent,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+ .enable = _clk_max_enable,
+ .disable = _clk_max_disable,
+ .secondary = &esdhc3_ipg_clk,
+};
+
+DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
+ clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
+
+static struct clk esdhc4_mx53_clk = {
+ .id = 3,
+ .parent = &esdhc1_clk,
+ .set_parent = clk_esdhc4_mx53_set_parent,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+ .enable = _clk_max_enable,
+ .disable = _clk_max_disable,
+ .secondary = &esdhc4_ipg_clk,
+};
+
DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
@@ -1312,6 +1438,8 @@ static struct clk_lookup mx51_lookups[] = {
_REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_clk)
_REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
_REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
@@ -1332,7 +1460,9 @@ static struct clk_lookup mx53_lookups[] = {
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_mx53_clk)
_REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
_REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
_REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
@@ -1425,6 +1555,14 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
mx53_revision();
clk_disable(&iim_clk);
+ /* Set SDHC parents to be PLL2 */
+ clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
+ clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
+
+ /* set SDHC root clock as 200MHZ*/
+ clk_set_rate(&esdhc1_clk, 200000000);
+ clk_set_rate(&esdhc3_mx53_clk, 200000000);
+
/* System timer */
mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
MX53_INT_GPT);
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index b462c22..87c0c58 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -217,9 +217,12 @@
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
@@ -271,6 +274,10 @@
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
--
1.7.1
^ permalink raw reply related
* [PATCH V3 3/4] mmc: sdhci-esdhc: remove SDHCI_QUIRK_NO_CARD_NO_RESET from ESDHC_DEFAULT_QUIRKS
From: Richard Zhu @ 2011-02-28 11:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298892315-23386-1-git-send-email-Hong-Xing.Zhu@freescale.com>
sdhci-esdhc-imx does not need SDHCI_QUIRK_NO_CARD_NO_RESET. Make it OF-specific.
Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com>
---
drivers/mmc/host/sdhci-esdhc.h | 3 +--
drivers/mmc/host/sdhci-of-esdhc.c | 2 +-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h
index afaf1bc..303cde0 100644
--- a/drivers/mmc/host/sdhci-esdhc.h
+++ b/drivers/mmc/host/sdhci-esdhc.h
@@ -24,8 +24,7 @@
SDHCI_QUIRK_NONSTANDARD_CLOCK | \
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
SDHCI_QUIRK_PIO_NEEDS_DELAY | \
- SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET | \
- SDHCI_QUIRK_NO_CARD_NO_RESET)
+ SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
#define ESDHC_SYSTEM_CONTROL 0x2c
#define ESDHC_CLOCK_MASK 0x0000fff0
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index fcd0e1f..6337607 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -73,7 +73,7 @@ static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
}
struct sdhci_of_data sdhci_esdhc = {
- .quirks = ESDHC_DEFAULT_QUIRKS,
+ .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_CARD_NO_RESET,
.ops = {
.read_l = sdhci_be32bs_readl,
.read_w = esdhc_readw,
--
1.7.1
^ permalink raw reply related
* [PATCH V3 4/4] mmc: sdhci-esdhc: enable esdhc on imx53
From: Richard Zhu @ 2011-02-28 11:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298892315-23386-1-git-send-email-Hong-Xing.Zhu@freescale.com>
Fix the NO INT in the Multi-BLK IO in SD/MMC, and
Multi-BLK read in SDIO
The CMDTYPE of the CMD register(offset 0xE) should be set to
"11" when the STOP CMD12 is issued on imx53 to abort one
open ended multi-blk IO. Otherwise one the TC INT wouldn't
be generated.
In exact block transfer, the controller doesn't complete the
operations automatically as required at the end of the
transfer and remains on hold if the abort command is not sent.
As a result, the TC flag is not asserted and SW received timeout
exeception. set bit1 of Vendor Spec registor to fix it
Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com>
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
---
drivers/mmc/host/sdhci-esdhc-imx.c | 77 ++++++++++++++++++++++++++++++++++-
drivers/mmc/host/sdhci-pltfm.h | 2 +-
2 files changed, 75 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 9b82910..32af7c4 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -15,13 +15,41 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
+#include <linux/slab.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sdhci-pltfm.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/sdio.h>
#include <mach/hardware.h>
#include "sdhci.h"
#include "sdhci-pltfm.h"
#include "sdhci-esdhc.h"
+/* Abort type definition in the command register */
+#define SDHCI_CMD_ABORTCMD 0xC0
+/* VENDOR SPEC register */
+#define SDHCI_VENDOR_SPEC 0xC0
+
+/*
+ * The CMDTYPE of the CMD register(offset 0xE) should be set to
+ * "11" when the STOP CMD12 is issued on imx53 to abort one
+ * open ended multi-blk IO. Otherwise one the TC INT wouldn't
+ * be generated.
+ * In exact block transfer, the controller doesn't complete the
+ * operations automatically as required at the end of the
+ * transfer and remains on hold if the abort command is not sent.
+ * As a result, the TC flag is not asserted and SW received timeout
+ * exeception. Bit1 of Vendor Spec registor is used to fix it.
+ */
+#define IMX_MULTIBLK_NO_INT (1 << 0)
+
+struct pltfm_imx_data {
+ int flags;
+ u32 mod_val;
+};
+
+static struct sdhci_ops sdhci_esdhc_ops;
+
static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
{
void __iomem *base = host->ioaddr + (reg & ~0x3);
@@ -38,20 +66,51 @@ static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
return readw(host->ioaddr + reg);
}
+static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
+{
+ switch (reg) {
+ case SDHCI_INT_STATUS:
+ if (val & SDHCI_INT_DATA_END) {
+ u32 v;
+ v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
+ if (v & 0x2) {
+ v &= ~0x2;
+ writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
+ }
+ }
+ break;
+ }
+ writel(val, host->ioaddr + reg);
+}
+
static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct pltfm_imx_data *imx_data =
+ (struct pltfm_imx_data *)pltfm_host->priv;
switch (reg) {
case SDHCI_TRANSFER_MODE:
+ if ((host->cmd->opcode == SD_IO_RW_EXTENDED)
+ && (host->cmd->data->blocks > 1)
+ && (host->cmd->data->flags & MMC_DATA_READ)
+ && (imx_data->flags & IMX_MULTIBLK_NO_INT)) {
+ u32 v;
+ v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
+ v |= 0x2;
+ writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
+ }
/*
* Postpone this write, we must do it together with a
* command write that is down below.
*/
- pltfm_host->scratchpad = val;
+ imx_data->mod_val = val;
return;
case SDHCI_COMMAND:
- writel(val << 16 | pltfm_host->scratchpad,
+ if ((host->cmd->opcode == MMC_STOP_TRANSMISSION)
+ && (imx_data->flags & IMX_MULTIBLK_NO_INT))
+ val |= SDHCI_CMD_ABORTCMD;
+ writel(val << 16 | imx_data->mod_val,
host->ioaddr + SDHCI_TRANSFER_MODE);
return;
case SDHCI_BLOCK_SIZE:
@@ -104,6 +163,10 @@ static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pd
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct clk *clk;
+ struct pltfm_imx_data *imx_data;
+
+ imx_data = kzalloc(sizeof(struct pltfm_imx_data), GFP_KERNEL);
+ pltfm_host->priv = (void *)imx_data;
clk = clk_get(mmc_dev(host->mmc), NULL);
if (IS_ERR(clk)) {
@@ -113,22 +176,30 @@ static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pd
clk_enable(clk);
pltfm_host->clk = clk;
- if (cpu_is_mx35() || cpu_is_mx51())
+ if (!cpu_is_mx25())
host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
/* Fix errata ENGcm07207 which is present on i.MX25 and i.MX35 */
if (cpu_is_mx25() || cpu_is_mx35())
host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
+ if (!(cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51())) {
+ imx_data->flags |= IMX_MULTIBLK_NO_INT;
+ sdhci_esdhc_ops.write_l = esdhc_writel_le;
+ }
+
return 0;
}
static void esdhc_pltfm_exit(struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct pltfm_imx_data *imx_data =
+ (struct pltfm_imx_data *)pltfm_host->priv;
clk_disable(pltfm_host->clk);
clk_put(pltfm_host->clk);
+ kfree(imx_data);
}
static struct sdhci_ops sdhci_esdhc_ops = {
diff --git a/drivers/mmc/host/sdhci-pltfm.h b/drivers/mmc/host/sdhci-pltfm.h
index ea2e44d..2b37016 100644
--- a/drivers/mmc/host/sdhci-pltfm.h
+++ b/drivers/mmc/host/sdhci-pltfm.h
@@ -17,7 +17,7 @@
struct sdhci_pltfm_host {
struct clk *clk;
- u32 scratchpad; /* to handle quirks across io-accessor calls */
+ void *priv; /* to handle quirks across io-accessor calls */
};
extern struct sdhci_pltfm_data sdhci_cns3xxx_pdata;
--
1.7.1
^ permalink raw reply related
* [PATCH V3 1/4] ARM: imx53_loco: add esdhc device support
From: Richard Zhu @ 2011-02-28 11:32 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
---
arch/arm/mach-mx5/Kconfig | 1 +
arch/arm/mach-mx5/board-mx53_loco.c | 2 ++
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index f065a0d..a72c833 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -162,6 +162,7 @@ config MACH_MX53_LOCO
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX53 LOCO platform. This includes specific
configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 160899e..0a18f8d 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -213,6 +213,8 @@ static void __init mx53_loco_board_init(void)
imx53_add_imx2_wdt(0, NULL);
imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
+ imx53_add_sdhci_esdhc_imx(0, NULL);
+ imx53_add_sdhci_esdhc_imx(2, NULL);
}
static void __init mx53_loco_timer_init(void)
--
1.7.1
^ permalink raw reply related
* [PATCH V3 2/4] ARM: imx51/53: add sdhc3/4 clock
From: Richard Zhu @ 2011-02-28 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298892725-23672-1-git-send-email-Hong-Xing.Zhu@freescale.com>
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
---
arch/arm/mach-mx5/clock-mx51-mx53.c | 140 ++++++++++++++++++++++++++++++++++-
arch/arm/mach-mx5/crm_regs.h | 7 ++
2 files changed, 146 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 8164b1d..652ace4 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -42,6 +42,9 @@ static struct clk usboh3_clk;
static struct clk emi_fast_clk;
static struct clk ipu_clk;
static struct clk mipi_hsc1_clk;
+static struct clk esdhc1_clk;
+static struct clk esdhc2_clk;
+static struct clk esdhc3_mx53_clk;
#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
@@ -1143,10 +1146,80 @@ CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
+/* mx51 specific */
CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
+static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &esdhc1_clk)
+ reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+ else if (parent == &esdhc2_clk)
+ reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+ else
+ return -EINVAL;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &esdhc1_clk)
+ reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ else if (parent == &esdhc2_clk)
+ reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ else
+ return -EINVAL;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+/* mx53 specific */
+static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &esdhc1_clk)
+ reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+ else if (parent == &esdhc3_mx53_clk)
+ reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+ else
+ return -EINVAL;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+
+static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &esdhc1_clk)
+ reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ else if (parent == &esdhc3_mx53_clk)
+ reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ else
+ return -EINVAL;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
static struct clk name = { \
.id = i, \
@@ -1251,9 +1324,62 @@ DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
+ NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
+ NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+
+/* mx51 specific */
DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
+static struct clk esdhc3_clk = {
+ .id = 2,
+ .parent = &esdhc1_clk,
+ .set_parent = clk_esdhc3_set_parent,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+ .enable = _clk_max_enable,
+ .disable = _clk_max_disable,
+ .secondary = &esdhc3_ipg_clk,
+};
+static struct clk esdhc4_clk = {
+ .id = 3,
+ .parent = &esdhc1_clk,
+ .set_parent = clk_esdhc4_set_parent,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+ .enable = _clk_max_enable,
+ .disable = _clk_max_disable,
+ .secondary = &esdhc4_ipg_clk,
+};
+
+/* mx53 specific */
+static struct clk esdhc2_mx53_clk = {
+ .id = 2,
+ .parent = &esdhc1_clk,
+ .set_parent = clk_esdhc2_mx53_set_parent,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+ .enable = _clk_max_enable,
+ .disable = _clk_max_disable,
+ .secondary = &esdhc3_ipg_clk,
+};
+
+DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
+ clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
+
+static struct clk esdhc4_mx53_clk = {
+ .id = 3,
+ .parent = &esdhc1_clk,
+ .set_parent = clk_esdhc4_mx53_set_parent,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+ .enable = _clk_max_enable,
+ .disable = _clk_max_disable,
+ .secondary = &esdhc4_ipg_clk,
+};
+
DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
@@ -1312,6 +1438,8 @@ static struct clk_lookup mx51_lookups[] = {
_REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_clk)
_REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
_REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
@@ -1332,7 +1460,9 @@ static struct clk_lookup mx53_lookups[] = {
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_mx53_clk)
_REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
_REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
_REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
@@ -1425,6 +1555,14 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
mx53_revision();
clk_disable(&iim_clk);
+ /* Set SDHC parents to be PLL2 */
+ clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
+ clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
+
+ /* set SDHC root clock as 200MHZ*/
+ clk_set_rate(&esdhc1_clk, 200000000);
+ clk_set_rate(&esdhc3_mx53_clk, 200000000);
+
/* System timer */
mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
MX53_INT_GPT);
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index b462c22..87c0c58 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -217,9 +217,12 @@
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
@@ -271,6 +274,10 @@
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
--
1.7.1
^ permalink raw reply related
* [PATCH V3 3/4] mmc: sdhci-esdhc: remove SDHCI_QUIRK_NO_CARD_NO_RESET from ESDHC_DEFAULT_QUIRKS
From: Richard Zhu @ 2011-02-28 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298892725-23672-1-git-send-email-Hong-Xing.Zhu@freescale.com>
sdhci-esdhc-imx does not need SDHCI_QUIRK_NO_CARD_NO_RESET. Make it OF-specific.
Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com>
---
drivers/mmc/host/sdhci-esdhc.h | 3 +--
drivers/mmc/host/sdhci-of-esdhc.c | 2 +-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h
index afaf1bc..303cde0 100644
--- a/drivers/mmc/host/sdhci-esdhc.h
+++ b/drivers/mmc/host/sdhci-esdhc.h
@@ -24,8 +24,7 @@
SDHCI_QUIRK_NONSTANDARD_CLOCK | \
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
SDHCI_QUIRK_PIO_NEEDS_DELAY | \
- SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET | \
- SDHCI_QUIRK_NO_CARD_NO_RESET)
+ SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
#define ESDHC_SYSTEM_CONTROL 0x2c
#define ESDHC_CLOCK_MASK 0x0000fff0
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index fcd0e1f..6337607 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -73,7 +73,7 @@ static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
}
struct sdhci_of_data sdhci_esdhc = {
- .quirks = ESDHC_DEFAULT_QUIRKS,
+ .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_CARD_NO_RESET,
.ops = {
.read_l = sdhci_be32bs_readl,
.read_w = esdhc_readw,
--
1.7.1
^ permalink raw reply related
* [PATCH V3 4/4] mmc: sdhci-esdhc: enable esdhc on imx53
From: Richard Zhu @ 2011-02-28 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298892725-23672-1-git-send-email-Hong-Xing.Zhu@freescale.com>
Fix the NO INT in the Multi-BLK IO in SD/MMC, and
Multi-BLK read in SDIO
The CMDTYPE of the CMD register(offset 0xE) should be set to
"11" when the STOP CMD12 is issued on imx53 to abort one
open ended multi-blk IO. Otherwise one the TC INT wouldn't
be generated.
In exact block transfer, the controller doesn't complete the
operations automatically as required at the end of the
transfer and remains on hold if the abort command is not sent.
As a result, the TC flag is not asserted and SW received timeout
exeception. set bit1 of Vendor Spec registor to fix it
Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com>
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
---
drivers/mmc/host/sdhci-esdhc-imx.c | 77 ++++++++++++++++++++++++++++++++++-
drivers/mmc/host/sdhci-pltfm.h | 2 +-
2 files changed, 75 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 9b82910..32af7c4 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -15,13 +15,41 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
+#include <linux/slab.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sdhci-pltfm.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/sdio.h>
#include <mach/hardware.h>
#include "sdhci.h"
#include "sdhci-pltfm.h"
#include "sdhci-esdhc.h"
+/* Abort type definition in the command register */
+#define SDHCI_CMD_ABORTCMD 0xC0
+/* VENDOR SPEC register */
+#define SDHCI_VENDOR_SPEC 0xC0
+
+/*
+ * The CMDTYPE of the CMD register(offset 0xE) should be set to
+ * "11" when the STOP CMD12 is issued on imx53 to abort one
+ * open ended multi-blk IO. Otherwise one the TC INT wouldn't
+ * be generated.
+ * In exact block transfer, the controller doesn't complete the
+ * operations automatically as required at the end of the
+ * transfer and remains on hold if the abort command is not sent.
+ * As a result, the TC flag is not asserted and SW received timeout
+ * exeception. Bit1 of Vendor Spec registor is used to fix it.
+ */
+#define IMX_MULTIBLK_NO_INT (1 << 0)
+
+struct pltfm_imx_data {
+ int flags;
+ u32 mod_val;
+};
+
+static struct sdhci_ops sdhci_esdhc_ops;
+
static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
{
void __iomem *base = host->ioaddr + (reg & ~0x3);
@@ -38,20 +66,51 @@ static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
return readw(host->ioaddr + reg);
}
+static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
+{
+ switch (reg) {
+ case SDHCI_INT_STATUS:
+ if (val & SDHCI_INT_DATA_END) {
+ u32 v;
+ v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
+ if (v & 0x2) {
+ v &= ~0x2;
+ writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
+ }
+ }
+ break;
+ }
+ writel(val, host->ioaddr + reg);
+}
+
static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct pltfm_imx_data *imx_data =
+ (struct pltfm_imx_data *)pltfm_host->priv;
switch (reg) {
case SDHCI_TRANSFER_MODE:
+ if ((host->cmd->opcode == SD_IO_RW_EXTENDED)
+ && (host->cmd->data->blocks > 1)
+ && (host->cmd->data->flags & MMC_DATA_READ)
+ && (imx_data->flags & IMX_MULTIBLK_NO_INT)) {
+ u32 v;
+ v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
+ v |= 0x2;
+ writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
+ }
/*
* Postpone this write, we must do it together with a
* command write that is down below.
*/
- pltfm_host->scratchpad = val;
+ imx_data->mod_val = val;
return;
case SDHCI_COMMAND:
- writel(val << 16 | pltfm_host->scratchpad,
+ if ((host->cmd->opcode == MMC_STOP_TRANSMISSION)
+ && (imx_data->flags & IMX_MULTIBLK_NO_INT))
+ val |= SDHCI_CMD_ABORTCMD;
+ writel(val << 16 | imx_data->mod_val,
host->ioaddr + SDHCI_TRANSFER_MODE);
return;
case SDHCI_BLOCK_SIZE:
@@ -104,6 +163,10 @@ static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pd
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct clk *clk;
+ struct pltfm_imx_data *imx_data;
+
+ imx_data = kzalloc(sizeof(struct pltfm_imx_data), GFP_KERNEL);
+ pltfm_host->priv = (void *)imx_data;
clk = clk_get(mmc_dev(host->mmc), NULL);
if (IS_ERR(clk)) {
@@ -113,22 +176,30 @@ static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pd
clk_enable(clk);
pltfm_host->clk = clk;
- if (cpu_is_mx35() || cpu_is_mx51())
+ if (!cpu_is_mx25())
host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
/* Fix errata ENGcm07207 which is present on i.MX25 and i.MX35 */
if (cpu_is_mx25() || cpu_is_mx35())
host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
+ if (!(cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51())) {
+ imx_data->flags |= IMX_MULTIBLK_NO_INT;
+ sdhci_esdhc_ops.write_l = esdhc_writel_le;
+ }
+
return 0;
}
static void esdhc_pltfm_exit(struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct pltfm_imx_data *imx_data =
+ (struct pltfm_imx_data *)pltfm_host->priv;
clk_disable(pltfm_host->clk);
clk_put(pltfm_host->clk);
+ kfree(imx_data);
}
static struct sdhci_ops sdhci_esdhc_ops = {
diff --git a/drivers/mmc/host/sdhci-pltfm.h b/drivers/mmc/host/sdhci-pltfm.h
index ea2e44d..2b37016 100644
--- a/drivers/mmc/host/sdhci-pltfm.h
+++ b/drivers/mmc/host/sdhci-pltfm.h
@@ -17,7 +17,7 @@
struct sdhci_pltfm_host {
struct clk *clk;
- u32 scratchpad; /* to handle quirks across io-accessor calls */
+ void *priv; /* to handle quirks across io-accessor calls */
};
extern struct sdhci_pltfm_data sdhci_cns3xxx_pdata;
--
1.7.1
^ permalink raw reply related
* [PATCH v10 05/18] OMAP2, 3 DSS2 Change driver name to omap_display
From: Cousson, Benoit @ 2011-02-28 11:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298877549.2096.47.camel@deskari>
Hi Tomi,
On 2/28/2011 8:19 AM, Valkeinen, Tomi wrote:
> On Mon, 2011-02-28 at 01:09 -0600, Taneja, Archit wrote:
>> Hi,
>>
>> On Monday 28 February 2011 12:23 PM, Valkeinen, Tomi wrote:
>>> On Thu, 2011-02-24 at 03:27 -0600, Tomi Valkeinen wrote:
>>>> Hi,
>>>>
>>>> On Mon, 2011-01-24 at 11:51 +0530, ext Sumit Semwal wrote:
>>>>> From: Senthilvadivu Guruswamy<svadivu@ti.com>
>>>>>
>>>>> Change the driver name from omapdss to omap_display as the driver takes care of
>>>>> the display devices ie number of panels, type of panels available in the
>>>>> platform. Change the device name in the board files and 2420,2430,3xxx clock
>>>>> files from omapdss to omap_display to match the driver name.
>>>>
>>>> I just realized that changing the driver name will break all scripts and
>>>> applications using omapdss sysfs files.
>>>>
>>>> How does this sound:
>>>>
>>>> Let's leave the omapdss device name as it is. It represents a "super"
>>>> device, containing the dss sysfs files and upper level dss management.
This is the case for all the drivers migrated to omap_device anyway due
to the change in the top level hierarchy. Everything is below
platform/omap now.
That's why we are using that opportunity to clean and provide a
consistent naming for all devices.
>>>> Name the HW module platform drivers as: omapdss_dss, omapdss_venc,
>>>> omapdss_dispc, etc. This would indicate them to be clearly parts of DSS,
>>>> and would also prevent any possible name conflict if there would happen
>>>> to be a, say, "dsi" block in some other HW component.
Cannot you use a device hierarchy then to do that?
omap_dss/core
omap_dss/dsi
omap_dss/venc
This is moreover the way the HW is done.
>>> Any comments on this?
>>
>> I also think we need to stick to the older name, "omapdss_dss" sounds a
>> bit confusing, and I think one of the previous versions had something
>> like "dss_dss" in it and it wasn't approved. Does something like
>> "omapdss_core" or "omapdss_dss_core" make sense, or is it more misleading?
>
> It is confusing, but so is the hardware naming =). There is a DSS module
> inside the omap display subsystem. That's why I would like to name it
> "dss", not "core", so it's clear it refers to this DSS module.
>
> "dss_dss" looks a bit silly, but I think "omapdss_dss" is slightly
> better in the sense that it doesn't repeat the same "dss", and there is
> an "omapdss" device, which acts like "manager" for these module devices.
> But yes, I wouldn't call it perfect either.
>
> "omapdss_dss_core" is one option. But then again, TRM doesn't speak of
> "core".
We should not maintain silly names just because they are in the TRM, we
should just fix the TRM. This is exactly what we are going to do for
most HW names we introduced in OMAP4.
So if we all agree that this name will avoid confusion and is much
better than the current one, we can change it right now with a comment
to explain the change and give the pointer to the current TRM naming.
Regards,
Benoit
^ permalink raw reply
* [PATCH V3 1/4] ARM: imx53_loco: add esdhc device support
From: Zhu Richard-R65037 @ 2011-02-28 11:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298892725-23672-1-git-send-email-Hong-Xing.Zhu@freescale.com>
Cc the patchs to linaro guys.
Best Regards
Richard Zhu
> -----Original Message-----
> From: Zhu Richard-R65037
> Sent: Monday, February 28, 2011 7:32 PM
> To: linux-arm-kernel at lists.infradead.org
> Cc: kernel at pengutronix.de; linux-mmc at vger.kernel.org; cjb at laptop.org;
> avorontsov at ru.mvista.com; eric at eukrea.com; w.sang at pengutronix.de;
> linuxzsc at gmail.com; Zhao Richard-B20223; Freescale at lists.linaro.org;
> eric.miao at linaro.org; Zhu Richard-R65037
> Subject: [PATCH V3 1/4] ARM: imx53_loco: add esdhc device support
>
> Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
> ---
> arch/arm/mach-mx5/Kconfig | 1 +
> arch/arm/mach-mx5/board-mx53_loco.c | 2 ++
> 2 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index
> f065a0d..a72c833 100644
> --- a/arch/arm/mach-mx5/Kconfig
> +++ b/arch/arm/mach-mx5/Kconfig
> @@ -162,6 +162,7 @@ config MACH_MX53_LOCO
> select IMX_HAVE_PLATFORM_IMX2_WDT
> select IMX_HAVE_PLATFORM_IMX_I2C
> select IMX_HAVE_PLATFORM_IMX_UART
> + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
> help
> Include support for MX53 LOCO platform. This includes specific
> configurations for the board and its peripherals.
> diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-
> mx5/board-mx53_loco.c
> index 160899e..0a18f8d 100644
> --- a/arch/arm/mach-mx5/board-mx53_loco.c
> +++ b/arch/arm/mach-mx5/board-mx53_loco.c
> @@ -213,6 +213,8 @@ static void __init mx53_loco_board_init(void)
> imx53_add_imx2_wdt(0, NULL);
> imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
> imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
> + imx53_add_sdhci_esdhc_imx(0, NULL);
> + imx53_add_sdhci_esdhc_imx(2, NULL);
> }
>
> static void __init mx53_loco_timer_init(void)
> --
> 1.7.1
^ permalink raw reply
* [PATCH] OMAP2+: sdrc: fix compile break on OMAP4-only config on current omap-for-linus
From: Sergei Shtylyov @ 2011-02-28 11:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1102271701450.4608@utopia.booyaka.com>
Hello.
On 28-02-2011 3:03, Paul Walmsley wrote:
>> How about empty inline instead?
> Thanks for the review; that is indeed a better approach. Following is the
> updated patch.
> Tony, do you want to take this one?
> - Paul
> From: Paul Walmsley<paul@pwsan.com>
> Date: Fri, 25 Feb 2011 17:38:25 -0700
> Subject: [PATCH] OMAP2+: sdrc: fix compile break on OMAP4-only config on current omap-for-linus
> On non-OMAP2 and non-OMAP3 kernel configs, turn omap2_sdrc_init() into
> a no-op. Otherwise, compilation breaks on an OMAP4-only config with
> the current omap-for-linus branch:
> arch/arm/mach-omap2/built-in.o: In function `omap2_init_common_devices':
> ../mach-omap2/io.c:421: undefined reference to `omap2_sdrc_init'
> Thanks to Sergei Shtylyov <sshtylyov@mvista.com> for suggesting the use
> of a empty static inline function rather than a macro.
Not at all. :-)
> Signed-off-by: Paul Walmsley<paul@pwsan.com>
> Cc: Tony Lindgren<tony@atomide.com>
> Cc: Sergei Shtylyov<sshtylyov@mvista.com>
> ---
> arch/arm/plat-omap/include/plat/sdrc.h | 6 ++++++
> 1 files changed, 6 insertions(+), 0 deletions(-)
> diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
> index efd87c8..2a34a65 100644
> --- a/arch/arm/plat-omap/include/plat/sdrc.h
> +++ b/arch/arm/plat-omap/include/plat/sdrc.h
> @@ -124,8 +124,14 @@ struct omap_sdrc_params {
> u32 mr;
> };
>
> +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
> void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
> struct omap_sdrc_params *sdrc_cs1);
> +#else
> +static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
No need to annotate it as __init.
> + struct omap_sdrc_params *sdrc_cs1) {};
> +#endif
> +
WBR, Sergei
^ permalink raw reply
* [PATCH v2 09/09] ARM: s3c2440: gta02: Add touchscreen support
From: Kukjin Kim @ 2011-02-28 11:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298891846-7487-1-git-send-email-lars@metafoo.de>
Lars-Peter Clausen wrote:
>
> This patch adds registers the s3c touchscreen and adc devices to add
> touchscreen
> support for the gta02.
>
> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
> ---
> arch/arm/mach-s3c2440/mach-gta02.c | 12 ++++++++++++
> 1 files changed, 12 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-s3c2440/mach-gta02.c
b/arch/arm/mach-s3c2440/mach-
> gta02.c
> index 640ca68..12193ad 100644
> --- a/arch/arm/mach-s3c2440/mach-gta02.c
> +++ b/arch/arm/mach-s3c2440/mach-gta02.c
> @@ -89,6 +89,8 @@
> #include <plat/udc.h>
> #include <plat/gpio-cfg.h>
> #include <plat/iic.h>
> +#include <plat/ts.h>
> +
>
> static struct pcf50633 *gta02_pcf;
>
> @@ -480,6 +482,13 @@ static struct s3c2410_hcd_info gta02_usb_info
__initdata
> = {
> },
> };
>
> +/* Touchscreen */
> +static struct s3c2410_ts_mach_info gta02_ts_info = {
> + .delay = 10000,
> + .presc = 0xff, /* slow as we can go */
> + .oversampling_shift = 2,
> +};
> +
> /* Buttons */
> static struct gpio_keys_button gta02_buttons[] = {
> {
> @@ -533,6 +542,8 @@ static struct platform_device *gta02_devices[]
__initdata
> = {
> &samsung_asoc_dma,
> &s3c_device_i2c0,
> >a02_buttons_device,
> + &s3c_device_adc,
> + &s3c_device_ts,
> };
>
> /* These guys DO need to be children of PMU. */
> @@ -595,6 +606,7 @@ static void __init gta02_machine_init(void)
> #endif
>
> s3c24xx_udc_set_platdata(>a02_udc_cfg);
> + s3c24xx_ts_set_platdata(>a02_ts_info);
> s3c_ohci_set_platdata(>a02_usb_info);
> s3c_nand_set_platdata(>a02_nand_info);
> s3c_i2c0_set_platdata(NULL);
> --
> 1.7.2.3
Ok, applied.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [PATCH 6/8 resend] dw_dmac: Mark all tx_descriptors with DMA_CRTL_ACK after xfer finish
From: Sergei Shtylyov @ 2011-02-28 12:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <82027aa0c6446df3f7fb8e3c5fbdc28f60ea33b7.1298889267.git.viresh.kumar@st.com>
Hello.
On 28-02-2011 13:41, Viresh Kumar wrote:
> dwc_desc_get checks all descriptors for DMA_CTRL_ACK before allocating them for
> transfers. And descriptors are not marked with DMA_CRTL_ACK after transfer
> finishes. Thus descriptor once used is not usable again. This patch marks
> descriptors with DMA_CRTL_ACK after dma xfer finishes
> Signed-off-by: Viresh Kumar<viresh.kumar@st.com>
> ---
> drivers/dma/dw_dmac.c | 7 +++++++
> 1 files changed, 7 insertions(+), 0 deletions(-)
> diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
> index c40b89f..01f783d 100644
> --- a/drivers/dma/dw_dmac.c
> +++ b/drivers/dma/dw_dmac.c
> @@ -196,6 +196,7 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc)
> dma_async_tx_callback callback;
> void *param;
> struct dma_async_tx_descriptor *txd =&desc->txd;
> + struct dw_desc *child;
Shouldn't this varaible name be aligned with the above variable names?
WBR, Sergei
^ permalink raw reply
* [PATCH v10 05/18] OMAP2,3 DSS2 Change driver name to omap_display
From: Tomi Valkeinen @ 2011-02-28 12:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D6B88BB.5010200@ti.com>
On Mon, 2011-02-28 at 05:36 -0600, Cousson, Benoit wrote:
> Hi Tomi,
>
> On 2/28/2011 8:19 AM, Valkeinen, Tomi wrote:
> > On Mon, 2011-02-28 at 01:09 -0600, Taneja, Archit wrote:
> >> Hi,
> >>
> >> On Monday 28 February 2011 12:23 PM, Valkeinen, Tomi wrote:
> >>> On Thu, 2011-02-24 at 03:27 -0600, Tomi Valkeinen wrote:
> >>>> Hi,
> >>>>
> >>>> On Mon, 2011-01-24 at 11:51 +0530, ext Sumit Semwal wrote:
> >>>>> From: Senthilvadivu Guruswamy<svadivu@ti.com>
> >>>>>
> >>>>> Change the driver name from omapdss to omap_display as the driver takes care of
> >>>>> the display devices ie number of panels, type of panels available in the
> >>>>> platform. Change the device name in the board files and 2420,2430,3xxx clock
> >>>>> files from omapdss to omap_display to match the driver name.
> >>>>
> >>>> I just realized that changing the driver name will break all scripts and
> >>>> applications using omapdss sysfs files.
> >>>>
> >>>> How does this sound:
> >>>>
> >>>> Let's leave the omapdss device name as it is. It represents a "super"
> >>>> device, containing the dss sysfs files and upper level dss management.
>
> This is the case for all the drivers migrated to omap_device anyway due
> to the change in the top level hierarchy. Everything is below
> platform/omap now.
The HW module drivers are under platform/omap/, but omapdss is in
platform/. Do you mean that omapdss should also be under platform/omap/?
The reason I'm unwilling to change omapdss name, or location, is that
omapdss directory contains lots of DSS configuration files, used by
scripts and programs.
> That's why we are using that opportunity to clean and provide a
> consistent naming for all devices.
>
> >>>> Name the HW module platform drivers as: omapdss_dss, omapdss_venc,
> >>>> omapdss_dispc, etc. This would indicate them to be clearly parts of DSS,
> >>>> and would also prevent any possible name conflict if there would happen
> >>>> to be a, say, "dsi" block in some other HW component.
>
> Cannot you use a device hierarchy then to do that?
> omap_dss/core
> omap_dss/dsi
> omap_dss/venc
>
> This is moreover the way the HW is done.
Hmm, how would that work? The devices are platform devices, and they
have a unique global name, which is used to match the driver for the
device.
>
> >>> Any comments on this?
> >>
> >> I also think we need to stick to the older name, "omapdss_dss" sounds a
> >> bit confusing, and I think one of the previous versions had something
> >> like "dss_dss" in it and it wasn't approved. Does something like
> >> "omapdss_core" or "omapdss_dss_core" make sense, or is it more misleading?
> >
> > It is confusing, but so is the hardware naming =). There is a DSS module
> > inside the omap display subsystem. That's why I would like to name it
> > "dss", not "core", so it's clear it refers to this DSS module.
> >
> > "dss_dss" looks a bit silly, but I think "omapdss_dss" is slightly
> > better in the sense that it doesn't repeat the same "dss", and there is
> > an "omapdss" device, which acts like "manager" for these module devices.
> > But yes, I wouldn't call it perfect either.
> >
> > "omapdss_dss_core" is one option. But then again, TRM doesn't speak of
> > "core".
>
> We should not maintain silly names just because they are in the TRM, we
> should just fix the TRM. This is exactly what we are going to do for
> most HW names we introduced in OMAP4.
>
> So if we all agree that this name will avoid confusion and is much
> better than the current one, we can change it right now with a comment
> to explain the change and give the pointer to the current TRM naming.
True. But I don't think there's a huge difference with omapdss_dss or
omapdss_core.
The name is used in only a few places inside the kernel, and never from
userspace, so we can change that also later.
The main issue I had was changing the omapdss device name, which would
break the userspace.
Tomi
^ permalink raw reply
* [PATCH v10 05/18] OMAP2,3 DSS2 Change driver name to omap_display
From: Russell King - ARM Linux @ 2011-02-28 12:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298895026.9809.27.camel@deskari>
On Mon, Feb 28, 2011 at 02:10:26PM +0200, Tomi Valkeinen wrote:
> On Mon, 2011-02-28 at 05:36 -0600, Cousson, Benoit wrote:
> > Cannot you use a device hierarchy then to do that?
> > omap_dss/core
> > omap_dss/dsi
> > omap_dss/venc
> >
> > This is moreover the way the HW is done.
>
> Hmm, how would that work? The devices are platform devices, and they
> have a unique global name, which is used to match the driver for the
> device.
And not forgetting that '/' is not permitted in device or driver names.
^ permalink raw reply
* [PATCH 2/4] msm: iommu: Rework clock logic and add IOMMU bus clock control
From: Trilok Soni @ 2011-02-28 12:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D6828B5.6050608@codeaurora.org>
Hi Steve,
On 2/26/2011 3:39 AM, Stepan Moskovchenko wrote:
> On 2/24/2011 11:29 PM, Trilok Soni wrote:
>> Hi Steve,
>
> Hello
>
>>> @@ -130,117 +131,134 @@ static int msm_iommu_probe(struct platform_device *pdev)
>>> {
>>> struct resource *r, *r2;
>>> struct clk *iommu_clk;
>>> + struct clk *iommu_pclk;
>>> struct msm_iommu_drvdata *drvdata;
>>> struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data;
>> const please.
>>
>
> I am not clear on what you mean. Please be more specific here.
I mean
const struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data;
Now I see that this change is not part of this patch so you can ignore my comment.
>
>>> + iommu_pclk = clk_get(NULL, "smmu_pclk");
>>> + if (IS_ERR(iommu_pclk)) {
>>> + ret = -ENODEV;
>>> + goto fail;
>>> + }
>> I am not a big fan of this when you have the "device" around. You should just do
>>
>> iommu_pclk = clk_get(&pdev->dev, NULL);
>>
>> ...error logic...
>>
>> iommu_clk = clk_get(&pdev->dev, "iommu_clk");
>>
>> ...error logic...
>>
>
> The pclk is a "special" bus clock and does not have a specific device instance associated with it, so passing a device would not be appropriate in this case. I pass the device for other clocks that are indeed associated with devices, but this is not one of them. I suppose we could create 11 or 12 aliases for the pclk and associate it with all the IOMMU devices, but I would prefer to avoid doing that as I believe the current approach is cleaner.
ok.
>
>>> - ret = -EBUSY;
>>> - goto fail;
>>> - }
>>> + len = r->end - r->start + 1;
>>
>> resource_size please.
>>
>
> Ok
Thanks.
---Trilok Soni
--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [PATCH RESEND 2.6.39 0/3] ARM: simpad: Add support for GPIO attached hardware
From: Jochen Friedrich @ 2011-02-28 12:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110226183322.GB1951@Boggieman>
Hi Kristoffer,
> You gotten any feedback on those patches?
>
>> ARM: simpad: Add ucb1x00 GPIO definitions and register GPIO
>> ARM: simpad: Cleanup CS3 accessors and add GPIO API
>> ARM: simpad: add GPIO based device definitions
Unfortunately, no.
Thanks,
Jochen
^ permalink raw reply
* [PATCH] ARM: 6770/1: l2x0: Errata fix for flush by Way operation
From: Santosh Shilimkar @ 2011-02-28 12:31 UTC (permalink / raw)
To: linux-arm-kernel
can cause data corruption
PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean & Invalidate
by Way operation.
Workaround:
Disable Write-Back and Cache Linefill (Debug Control Register)
Clean & Invalidate by Way (0x7FC)
Re-enable Write-Back and Cache Linefill (Debug Control Register)
This patch also removes any OMAP dependency on PL310 Errata's
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/Kconfig | 15 ++++++++++++---
arch/arm/include/asm/outercache.h | 1 +
arch/arm/mm/cache-l2x0.c | 32 ++++++++++++++++++--------------
3 files changed, 31 insertions(+), 17 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 65ea7bb..ef41f7e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1135,7 +1135,7 @@ config ARM_ERRATA_742231
config PL310_ERRATA_588369
bool "Clean & Invalidate maintenance operations do not invalidate
clean lines"
- depends on CACHE_L2X0 && ARCH_OMAP4
+ depends on CACHE_L2X0
help
The PL310 L2 cache controller implements three types of Clean &
Invalidate maintenance operations: by Physical Address
@@ -1144,8 +1144,7 @@ config PL310_ERRATA_588369
clean operation followed immediately by an invalidate
operation,
both performing to the same memory location. This functionality
is not correctly implemented in PL310 as clean lines are not
- invalidated as a result of these operations. Note that this
errata
- uses Texas Instrument's secure monitor api.
+ invalidated as a result of these operations.
config ARM_ERRATA_720789
bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can
broadcast a faulty ASID"
@@ -1172,6 +1171,16 @@ config ARM_ERRATA_743622
visible impact on the overall performance or power consumption
of the
processor.
+config PL310_ERRATA_727915
+ bool "Background Clean & Invalidate by Way operation can cause
data corruption"
+ depends on CACHE_L2X0
+ help
+ PL310 implements the Clean & Invalidate by Way L2 cache
maintenance
+ operation (offset 0x7FC). This operation runs in background so
that
+ PL310 can handle normal accesses while it is in progress. Under
very
+ rare circumstances, due to this erratum, write data can be lost
when
+ PL310 treats a cacheable write transaction during a Clean &
+ Invalidate by Way operation.
endmenu
source "arch/arm/common/Kconfig"
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index fc19009..348d513 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -31,6 +31,7 @@ struct outer_cache_fns {
#ifdef CONFIG_OUTER_CACHE_SYNC
void (*sync)(void);
#endif
+ void (*set_debug)(unsigned long);
};
#ifdef CONFIG_OUTER_CACHE
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb..0986cce 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -67,18 +67,24 @@ static inline void l2x0_inv_line(unsigned long addr)
writel_relaxed(addr, base + L2X0_INV_LINE_PA);
}
-#ifdef CONFIG_PL310_ERRATA_588369
-static void debug_writel(unsigned long val)
-{
- extern void omap_smc1(u32 fn, u32 arg);
+#if defined(CONFIG_PL310_ERRATA_588369) ||
defined(CONFIG_PL310_ERRATA_727915)
- /*
- * Texas Instrument secure monitor api to modify the
- * PL310 Debug Control Register.
- */
- omap_smc1(0x100, val);
+#define debug_writel(val) outer_cache.set_debug(val)
+
+static void l2x0_set_debug(unsigned long val)
+{
+ writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
}
+#else
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
+}
+
+#define l2x0_set_debug NULL
+#endif
+#ifdef CONFIG_PL310_ERRATA_588369
static inline void l2x0_flush_line(unsigned long addr)
{
void __iomem *base = l2x0_base;
@@ -91,11 +97,6 @@ static inline void l2x0_flush_line(unsigned long addr)
}
#else
-/* Optimised out for non-errata case */
-static inline void debug_writel(unsigned long val)
-{
-}
-
static inline void l2x0_flush_line(unsigned long addr)
{
void __iomem *base = l2x0_base;
@@ -119,9 +120,11 @@ static void l2x0_flush_all(void)
/* clean all ways */
spin_lock_irqsave(&l2x0_lock, flags);
+ debug_writel(0x03);
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
cache_sync();
+ debug_writel(0x00);
spin_unlock_irqrestore(&l2x0_lock, flags);
}
@@ -329,6 +332,7 @@ void __init l2x0_init(void __iomem *base, __u32
aux_val, __u32 aux_mask)
outer_cache.flush_all = l2x0_flush_all;
outer_cache.inv_all = l2x0_inv_all;
outer_cache.disable = l2x0_disable;
+ outer_cache.set_debug = l2x0_set_debug;
printk(KERN_INFO "%s cache controller enabled\n", type);
printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x,
Cache size: %d B\n",
--
1.6.0.4
--0015175ca8ee102c3d049de3979f
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Cgo=
--0015175ca8ee102c3d049de3979f--
^ permalink raw reply related
* [PATCH V3 1/4] ARM: imx53_loco: add esdhc device support
From: Fabio Estevam @ 2011-02-28 12:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298892315-23386-1-git-send-email-Hong-Xing.Zhu@freescale.com>
Hi Richard,
On Mon, Feb 28, 2011 at 8:25 AM, Richard Zhu
<Hong-Xing.Zhu@freescale.com> wrote:
> Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
> ---
> ?arch/arm/mach-mx5/Kconfig ? ? ? ? ? | ? ?1 +
> ?arch/arm/mach-mx5/board-mx53_loco.c | ? ?2 ++
> ?2 files changed, 3 insertions(+), 0 deletions(-)
I think this patch should be the last one of the series.
Regards,
Fabio Estevam
^ permalink raw reply
* [PATCH 1/2] ARM: l2x0: Errata fix for flush by Way operationcan cause data corruption
From: Santosh Shilimkar @ 2011-02-28 12:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110228101351.GA30781@n2100.arm.linux.org.uk>
> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> Sent: Monday, February 28, 2011 3:44 PM
> To: Santosh Shilimkar
> Cc: tony at atomide.com; catalin.marinas at arm.com; linux-
> omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 1/2] ARM: l2x0: Errata fix for flush by Way
> operationcan cause data corruption
>
> On Sun, Feb 27, 2011 at 12:00:21PM +0000, Russell King - ARM Linux
> wrote:
> > > +#else
> > > +/* Optimised out for non-errata case */
> > > +static inline void debug_writel(unsigned long val)
> > > +{
> > > }
> >
> > #define l2x0_set_debug NULL
> >
> > > +#endif
>
> I notice you got rid of the inline function. Have you tried
> building this without the errata enabled?
I accidently dropped the inline function while
incorporating the comment from you. :(
Fixed it. Updated version # 6770/1
Regards,
Santosh
^ permalink raw reply
* [PATCH v2 02/13] da850: pruss platform specific additions.
From: TK, Pratheesh Gangadhar @ 2011-02-28 13:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297435892-28278-3-git-send-email-subhasish@mistralsolutions.com>
Hi,
> -----Original Message-----
> From: davinci-linux-open-source-bounces at linux.davincidsp.com
> [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf
> Of Subhasish Ghosh
> Sent: Friday, February 11, 2011 8:21 PM
> To: davinci-linux-open-source at linux.davincidsp.com
> Cc: sachi at mistralsolutions.com; Russell King; Kevin Hilman; Subhasish
> Ghosh; open list; Watkins, Melissa; linux-arm-kernel at lists.infradead.org
> Subject: [PATCH v2 02/13] da850: pruss platform specific additions.
>
> This patch adds the platform device and assignes the platform resources
> for the PRUSS mfd driver.
>
> Signed-off-by: Subhasish Ghosh <subhasish@mistralsolutions.com>
> ---
> +struct platform_device da8xx_pruss_dev = {
Can you please rename this to da8xx_pruss_mfddev?
> + .name = "da8xx_pruss",
Can you please rename name string as pruss_mfd? This will help to
base my UIO patches on top of yours.
> + .id = -1,
> + .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
> + .resource = da8xx_pruss_resources,
> +};
> +
> +int __init da8xx_register_pruss(struct da8xx_pruss_devices *pruss_device)
Please rename this to da8xx_register_pruss_mfd
Thanks,
Pratheesh
^ permalink raw reply
* One quick question about SMP on ARM
From: rocky @ 2011-02-28 13:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi, all
I am puzzled these day on three issues for SMP ARM in terms of hardware:
1: Is MMU global or per cpu ?
2: Is MicroTLB/MainTLB global or per cpu ?
I read the code, each cpu has to set its own pgd base addr into TBBR0,so I draw the conclusion MMU is per cpu;
ASID is shared between each cpu, while when ASID rollover from 0xff back to 0x0, each cpu has to call local_flush_tlb_all to invalidate I/D tlb; Does that mean MicroTLB/MainTLB is also per cpu; then why all cpu shared ASID from 0x0~0xff ?
I am really confused about this ? any tips
Thanks
rocky
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