* [PATCH V6 04/11] ST SPEAr3xx: Make local shirq structures static
From: Viresh Kumar @ 2011-03-01 11:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977709.git.viresh.kumar@st.com>
From: Ryan Mallon <ryan@bluewatersys.com>
Several structures in arch/arm/mach-spear3xx are not marked static
like they should be. Fix this.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/spear300.c | 4 ++--
arch/arm/mach-spear3xx/spear310.c | 16 ++++++++--------
arch/arm/mach-spear3xx/spear320.c | 12 ++++++------
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 2e856d8..a1280ba 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -523,7 +523,7 @@ struct pmx_driver pmx_driver = {
};
/* spear3xx shared irq */
-struct shirq_dev_config shirq_ras1_config[] = {
+static struct shirq_dev_config shirq_ras1_config[] = {
{
.virq = VIRQ_IT_PERS_S,
.enb_mask = IT_PERS_S_IRQ_MASK,
@@ -563,7 +563,7 @@ struct shirq_dev_config shirq_ras1_config[] = {
},
};
-struct spear_shirq shirq_ras1 = {
+static struct spear_shirq shirq_ras1 = {
.irq = IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 20182d2..3a2c4b2 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -192,7 +192,7 @@ struct pmx_dev pmx_tdm0 = {
struct pmx_driver pmx_driver;
/* spear3xx shared irq */
-struct shirq_dev_config shirq_ras1_config[] = {
+static struct shirq_dev_config shirq_ras1_config[] = {
{
.virq = VIRQ_SMII0,
.status_mask = SMII0_IRQ_MASK,
@@ -220,7 +220,7 @@ struct shirq_dev_config shirq_ras1_config[] = {
},
};
-struct spear_shirq shirq_ras1 = {
+static struct spear_shirq shirq_ras1 = {
.irq = IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
@@ -232,7 +232,7 @@ struct spear_shirq shirq_ras1 = {
},
};
-struct shirq_dev_config shirq_ras2_config[] = {
+static struct shirq_dev_config shirq_ras2_config[] = {
{
.virq = VIRQ_UART1,
.status_mask = UART1_IRQ_MASK,
@@ -251,7 +251,7 @@ struct shirq_dev_config shirq_ras2_config[] = {
},
};
-struct spear_shirq shirq_ras2 = {
+static struct spear_shirq shirq_ras2 = {
.irq = IRQ_GEN_RAS_2,
.dev_config = shirq_ras2_config,
.dev_count = ARRAY_SIZE(shirq_ras2_config),
@@ -263,14 +263,14 @@ struct spear_shirq shirq_ras2 = {
},
};
-struct shirq_dev_config shirq_ras3_config[] = {
+static struct shirq_dev_config shirq_ras3_config[] = {
{
.virq = VIRQ_EMI,
.status_mask = EMI_IRQ_MASK,
},
};
-struct spear_shirq shirq_ras3 = {
+static struct spear_shirq shirq_ras3 = {
.irq = IRQ_GEN_RAS_3,
.dev_config = shirq_ras3_config,
.dev_count = ARRAY_SIZE(shirq_ras3_config),
@@ -282,7 +282,7 @@ struct spear_shirq shirq_ras3 = {
},
};
-struct shirq_dev_config shirq_intrcomm_ras_config[] = {
+static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
{
.virq = VIRQ_TDM_HDLC,
.status_mask = TDM_HDLC_IRQ_MASK,
@@ -295,7 +295,7 @@ struct shirq_dev_config shirq_intrcomm_ras_config[] = {
},
};
-struct spear_shirq shirq_intrcomm_ras = {
+static struct spear_shirq shirq_intrcomm_ras = {
.irq = IRQ_INTRCOMM_RAS_ARM,
.dev_config = shirq_intrcomm_ras_config,
.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 249798b3..fee265b 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -587,7 +587,7 @@ struct pmx_driver pmx_driver = {
};
/* spear3xx shared irq */
-struct shirq_dev_config shirq_ras1_config[] = {
+static struct shirq_dev_config shirq_ras1_config[] = {
{
.virq = VIRQ_EMI,
.status_mask = EMI_IRQ_MASK,
@@ -603,7 +603,7 @@ struct shirq_dev_config shirq_ras1_config[] = {
},
};
-struct spear_shirq shirq_ras1 = {
+static struct spear_shirq shirq_ras1 = {
.irq = IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
@@ -616,7 +616,7 @@ struct spear_shirq shirq_ras1 = {
},
};
-struct shirq_dev_config shirq_ras3_config[] = {
+static struct shirq_dev_config shirq_ras3_config[] = {
{
.virq = VIRQ_PLGPIO,
.enb_mask = GPIO_IRQ_MASK,
@@ -635,7 +635,7 @@ struct shirq_dev_config shirq_ras3_config[] = {
},
};
-struct spear_shirq shirq_ras3 = {
+static struct spear_shirq shirq_ras3 = {
.irq = IRQ_GEN_RAS_3,
.dev_config = shirq_ras3_config,
.dev_count = ARRAY_SIZE(shirq_ras3_config),
@@ -649,7 +649,7 @@ struct spear_shirq shirq_ras3 = {
},
};
-struct shirq_dev_config shirq_intrcomm_ras_config[] = {
+static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
{
.virq = VIRQ_CANU,
.status_mask = CAN_U_IRQ_MASK,
@@ -697,7 +697,7 @@ struct shirq_dev_config shirq_intrcomm_ras_config[] = {
},
};
-struct spear_shirq shirq_intrcomm_ras = {
+static struct spear_shirq shirq_intrcomm_ras = {
.irq = IRQ_INTRCOMM_RAS_ARM,
.dev_config = shirq_intrcomm_ras_config,
.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 05/11] ST SPEAR3xx: Rename register/irq defines to remove naming conflicts
From: Viresh Kumar @ 2011-03-01 11:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977709.git.viresh.kumar@st.com>
From: Ryan Mallon <ryan@bluewatersys.com>
Prefix register and irq defintions to remove naming conflicts between
the three SPEAr3xx platforms.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 4 +-
arch/arm/mach-spear3xx/include/mach/irqs.h | 206 ++++++++++++------------
arch/arm/mach-spear3xx/include/mach/spear300.h | 26 ++--
arch/arm/mach-spear3xx/include/mach/spear310.h | 44 +++---
arch/arm/mach-spear3xx/include/mach/spear320.h | 48 +++---
arch/arm/mach-spear3xx/spear300.c | 66 ++++----
arch/arm/mach-spear3xx/spear310.c | 92 ++++++------
arch/arm/mach-spear3xx/spear320.c | 134 ++++++++--------
arch/arm/mach-spear3xx/spear3xx.c | 6 +-
9 files changed, 314 insertions(+), 312 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 4772507..c2b15b1 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -27,8 +27,8 @@
* Following GPT channels will be used as clock source and clockevent
*/
#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
+#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
+#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
/* Add spear3xx family device structure declarations here */
extern struct amba_device gpio_device;
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index a1a7f48..6e26544 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -15,138 +15,140 @@
#define __MACH_IRQS_H
/* SPEAr3xx IRQ definitions */
-#define IRQ_HW_ACCEL_MOD_0 0
-#define IRQ_INTRCOMM_RAS_ARM 1
-#define IRQ_CPU_GPT1_1 2
-#define IRQ_CPU_GPT1_2 3
-#define IRQ_BASIC_GPT1_1 4
-#define IRQ_BASIC_GPT1_2 5
-#define IRQ_BASIC_GPT2_1 6
-#define IRQ_BASIC_GPT2_2 7
-#define IRQ_BASIC_DMA 8
-#define IRQ_BASIC_SMI 9
-#define IRQ_BASIC_RTC 10
-#define IRQ_BASIC_GPIO 11
-#define IRQ_BASIC_WDT 12
-#define IRQ_DDR_CONTROLLER 13
-#define IRQ_SYS_ERROR 14
-#define IRQ_WAKEUP_RCV 15
-#define IRQ_JPEG 16
-#define IRQ_IRDA 17
-#define IRQ_ADC 18
-#define IRQ_UART 19
-#define IRQ_SSP 20
-#define IRQ_I2C 21
-#define IRQ_MAC_1 22
-#define IRQ_MAC_2 23
-#define IRQ_USB_DEV 24
-#define IRQ_USB_H_OHCI_0 25
-#define IRQ_USB_H_EHCI_0 26
-#define IRQ_USB_H_EHCI_1 IRQ_USB_H_EHCI_0
-#define IRQ_USB_H_OHCI_1 27
-#define IRQ_GEN_RAS_1 28
-#define IRQ_GEN_RAS_2 29
-#define IRQ_GEN_RAS_3 30
-#define IRQ_HW_ACCEL_MOD_1 31
-#define IRQ_VIC_END 32
-
-#define VIRQ_START IRQ_VIC_END
+#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
+#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
+#define SPEAR3XX_IRQ_CPU_GPT1_1 2
+#define SPEAR3XX_IRQ_CPU_GPT1_2 3
+#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
+#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
+#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
+#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
+#define SPEAR3XX_IRQ_BASIC_DMA 8
+#define SPEAR3XX_IRQ_BASIC_SMI 9
+#define SPEAR3XX_IRQ_BASIC_RTC 10
+#define SPEAR3XX_IRQ_BASIC_GPIO 11
+#define SPEAR3XX_IRQ_BASIC_WDT 12
+#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
+#define SPEAR3XX_IRQ_SYS_ERROR 14
+#define SPEAR3XX_IRQ_WAKEUP_RCV 15
+#define SPEAR3XX_IRQ_JPEG 16
+#define SPEAR3XX_IRQ_IRDA 17
+#define SPEAR3XX_IRQ_ADC 18
+#define SPEAR3XX_IRQ_UART 19
+#define SPEAR3XX_IRQ_SSP 20
+#define SPEAR3XX_IRQ_I2C 21
+#define SPEAR3XX_IRQ_MAC_1 22
+#define SPEAR3XX_IRQ_MAC_2 23
+#define SPEAR3XX_IRQ_USB_DEV 24
+#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
+#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
+#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
+#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
+#define SPEAR3XX_IRQ_GEN_RAS_1 28
+#define SPEAR3XX_IRQ_GEN_RAS_2 29
+#define SPEAR3XX_IRQ_GEN_RAS_3 30
+#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
+#define SPEAR3XX_IRQ_VIC_END 32
+
+#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
/* SPEAr300 Virtual irq definitions */
-#ifdef CONFIG_MACH_SPEAR300
/* IRQs sharing IRQ_GEN_RAS_1 */
-#define VIRQ_IT_PERS_S (VIRQ_START + 0)
-#define VIRQ_IT_CHANGE_S (VIRQ_START + 1)
-#define VIRQ_I2S (VIRQ_START + 2)
-#define VIRQ_TDM (VIRQ_START + 3)
-#define VIRQ_CAMERA_L (VIRQ_START + 4)
-#define VIRQ_CAMERA_F (VIRQ_START + 5)
-#define VIRQ_CAMERA_V (VIRQ_START + 6)
-#define VIRQ_KEYBOARD (VIRQ_START + 7)
-#define VIRQ_GPIO1 (VIRQ_START + 8)
+#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
/* IRQs sharing IRQ_GEN_RAS_3 */
-#define IRQ_CLCD IRQ_GEN_RAS_3
+#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define IRQ_SDHCI IRQ_INTRCOMM_RAS_ARM
-
-/* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE (VIRQ_START + 9)
-#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8)
+#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
/* SPEAr310 Virtual irq definitions */
-#elif defined(CONFIG_MACH_SPEAR310)
/* IRQs sharing IRQ_GEN_RAS_1 */
-#define VIRQ_SMII0 (VIRQ_START + 0)
-#define VIRQ_SMII1 (VIRQ_START + 1)
-#define VIRQ_SMII2 (VIRQ_START + 2)
-#define VIRQ_SMII3 (VIRQ_START + 3)
-#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 4)
-#define VIRQ_WAKEUP_SMII1 (VIRQ_START + 5)
-#define VIRQ_WAKEUP_SMII2 (VIRQ_START + 6)
-#define VIRQ_WAKEUP_SMII3 (VIRQ_START + 7)
+#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
/* IRQs sharing IRQ_GEN_RAS_2 */
-#define VIRQ_UART1 (VIRQ_START + 8)
-#define VIRQ_UART2 (VIRQ_START + 9)
-#define VIRQ_UART3 (VIRQ_START + 10)
-#define VIRQ_UART4 (VIRQ_START + 11)
-#define VIRQ_UART5 (VIRQ_START + 12)
+#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
/* IRQs sharing IRQ_GEN_RAS_3 */
-#define VIRQ_EMI (VIRQ_START + 13)
-#define VIRQ_PLGPIO (VIRQ_START + 14)
+#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define VIRQ_TDM_HDLC (VIRQ_START + 15)
-#define VIRQ_RS485_0 (VIRQ_START + 16)
-#define VIRQ_RS485_1 (VIRQ_START + 17)
-
-/* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE (VIRQ_START + 18)
+#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
+#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
/* SPEAr320 Virtual irq definitions */
-#else
/* IRQs sharing IRQ_GEN_RAS_1 */
-#define VIRQ_EMI (VIRQ_START + 0)
-#define VIRQ_CLCD (VIRQ_START + 1)
-#define VIRQ_SPP (VIRQ_START + 2)
+#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
/* IRQs sharing IRQ_GEN_RAS_2 */
-#define IRQ_SDHCI IRQ_GEN_RAS_2
+#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
/* IRQs sharing IRQ_GEN_RAS_3 */
-#define VIRQ_PLGPIO (VIRQ_START + 3)
-#define VIRQ_I2S_PLAY (VIRQ_START + 4)
-#define VIRQ_I2S_REC (VIRQ_START + 5)
+#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define VIRQ_CANU (VIRQ_START + 6)
-#define VIRQ_CANL (VIRQ_START + 7)
-#define VIRQ_UART1 (VIRQ_START + 8)
-#define VIRQ_UART2 (VIRQ_START + 9)
-#define VIRQ_SSP1 (VIRQ_START + 10)
-#define VIRQ_SSP2 (VIRQ_START + 11)
-#define VIRQ_SMII0 (VIRQ_START + 12)
-#define VIRQ_MII1_SMII1 (VIRQ_START + 13)
-#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 14)
-#define VIRQ_WAKEUP_MII1_SMII1 (VIRQ_START + 15)
-#define VIRQ_I2C (VIRQ_START + 16)
-
-/* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE (VIRQ_START + 17)
+#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
+#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
+#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
+/*
+ * GPIO pins virtual irqs
+ * Use the lowest number for the GPIO virtual IRQs base on which subarchs
+ * we have compiled in
+ */
+#if defined(CONFIG_MACH_SPEAR310)
+#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
+#elif defined(CONFIG_MACH_SPEAR320)
+#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
+#else
+#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
#endif
-/* PLGPIO Virtual IRQs */
+#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
+#define SPEAR3XX_PLGPIO_COUNT 102
+
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-#define SPEAR_PLGPIO_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END (SPEAR_PLGPIO_INT_BASE + 102)
+#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
+#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
+ SPEAR3XX_PLGPIO_COUNT)
+#else
+#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
#endif
-#define VIRQ_END SPEAR_GPIO_INT_END
-#define NR_IRQS VIRQ_END
+#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
+#define NR_IRQS SPEAR3XX_VIRQ_END
#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index 4fd2d22..7d5db76 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -20,19 +20,19 @@
#define SPEAR300_TELECOM_BASE UL(0x50000000)
/* Interrupt registers offsets and masks */
-#define INT_ENB_MASK_REG 0x54
-#define INT_STS_MASK_REG 0x58
-#define IT_PERS_S_IRQ_MASK (1 << 0)
-#define IT_CHANGE_S_IRQ_MASK (1 << 1)
-#define I2S_IRQ_MASK (1 << 2)
-#define TDM_IRQ_MASK (1 << 3)
-#define CAMERA_L_IRQ_MASK (1 << 4)
-#define CAMERA_F_IRQ_MASK (1 << 5)
-#define CAMERA_V_IRQ_MASK (1 << 6)
-#define KEYBOARD_IRQ_MASK (1 << 7)
-#define GPIO1_IRQ_MASK (1 << 8)
-
-#define SHIRQ_RAS1_MASK 0x1FF
+#define SPEAR300_INT_ENB_MASK_REG 0x54
+#define SPEAR300_INT_STS_MASK_REG 0x58
+#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
+#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
+#define SPEAR300_I2S_IRQ_MASK (1 << 2)
+#define SPEAR300_TDM_IRQ_MASK (1 << 3)
+#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
+#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
+#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
+#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
+#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
+
+#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
#define SPEAR300_CLCD_BASE UL(0x60000000)
#define SPEAR300_SDHCI_BASE UL(0x70000000)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index 1e85347..1567d0da 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -29,29 +29,29 @@
#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
/* Interrupt registers offsets and masks */
-#define INT_STS_MASK_REG 0x04
-#define SMII0_IRQ_MASK (1 << 0)
-#define SMII1_IRQ_MASK (1 << 1)
-#define SMII2_IRQ_MASK (1 << 2)
-#define SMII3_IRQ_MASK (1 << 3)
-#define WAKEUP_SMII0_IRQ_MASK (1 << 4)
-#define WAKEUP_SMII1_IRQ_MASK (1 << 5)
-#define WAKEUP_SMII2_IRQ_MASK (1 << 6)
-#define WAKEUP_SMII3_IRQ_MASK (1 << 7)
-#define UART1_IRQ_MASK (1 << 8)
-#define UART2_IRQ_MASK (1 << 9)
-#define UART3_IRQ_MASK (1 << 10)
-#define UART4_IRQ_MASK (1 << 11)
-#define UART5_IRQ_MASK (1 << 12)
-#define EMI_IRQ_MASK (1 << 13)
-#define TDM_HDLC_IRQ_MASK (1 << 14)
-#define RS485_0_IRQ_MASK (1 << 15)
-#define RS485_1_IRQ_MASK (1 << 16)
+#define SPEAR310_INT_STS_MASK_REG 0x04
+#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
+#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
+#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
+#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
+#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
+#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
+#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
+#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
+#define SPEAR310_UART1_IRQ_MASK (1 << 8)
+#define SPEAR310_UART2_IRQ_MASK (1 << 9)
+#define SPEAR310_UART3_IRQ_MASK (1 << 10)
+#define SPEAR310_UART4_IRQ_MASK (1 << 11)
+#define SPEAR310_UART5_IRQ_MASK (1 << 12)
+#define SPEAR310_EMI_IRQ_MASK (1 << 13)
+#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
+#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
+#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
-#define SHIRQ_RAS1_MASK 0x000FF
-#define SHIRQ_RAS2_MASK 0x01F00
-#define SHIRQ_RAS3_MASK 0x02000
-#define SHIRQ_INTRCOMM_RAS_MASK 0x1C000
+#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
+#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
+#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
+#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
#endif /* __MACH_SPEAR310_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 940f0d8..8cfa83f 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -36,31 +36,31 @@
#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
/* Interrupt registers offsets and masks */
-#define INT_STS_MASK_REG 0x04
-#define INT_CLR_MASK_REG 0x04
-#define INT_ENB_MASK_REG 0x08
-#define GPIO_IRQ_MASK (1 << 0)
-#define I2S_PLAY_IRQ_MASK (1 << 1)
-#define I2S_REC_IRQ_MASK (1 << 2)
-#define EMI_IRQ_MASK (1 << 7)
-#define CLCD_IRQ_MASK (1 << 8)
-#define SPP_IRQ_MASK (1 << 9)
-#define SDHCI_IRQ_MASK (1 << 10)
-#define CAN_U_IRQ_MASK (1 << 11)
-#define CAN_L_IRQ_MASK (1 << 12)
-#define UART1_IRQ_MASK (1 << 13)
-#define UART2_IRQ_MASK (1 << 14)
-#define SSP1_IRQ_MASK (1 << 15)
-#define SSP2_IRQ_MASK (1 << 16)
-#define SMII0_IRQ_MASK (1 << 17)
-#define MII1_SMII1_IRQ_MASK (1 << 18)
-#define WAKEUP_SMII0_IRQ_MASK (1 << 19)
-#define WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
-#define I2C1_IRQ_MASK (1 << 21)
+#define SPEAR320_INT_STS_MASK_REG 0x04
+#define SPEAR320_INT_CLR_MASK_REG 0x04
+#define SPEAR320_INT_ENB_MASK_REG 0x08
+#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
+#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
+#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
+#define SPEAR320_EMI_IRQ_MASK (1 << 7)
+#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
+#define SPEAR320_SPP_IRQ_MASK (1 << 9)
+#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
+#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
+#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
+#define SPEAR320_UART1_IRQ_MASK (1 << 13)
+#define SPEAR320_UART2_IRQ_MASK (1 << 14)
+#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
+#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
+#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
+#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
+#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
+#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
+#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
-#define SHIRQ_RAS1_MASK 0x000380
-#define SHIRQ_RAS3_MASK 0x000007
-#define SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
+#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
+#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
+#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
#endif /* __MACH_SPEAR320_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index a1280ba..e1b2580 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -525,52 +525,52 @@ struct pmx_driver pmx_driver = {
/* spear3xx shared irq */
static struct shirq_dev_config shirq_ras1_config[] = {
{
- .virq = VIRQ_IT_PERS_S,
- .enb_mask = IT_PERS_S_IRQ_MASK,
- .status_mask = IT_PERS_S_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_IT_PERS_S,
+ .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
+ .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
}, {
- .virq = VIRQ_IT_CHANGE_S,
- .enb_mask = IT_CHANGE_S_IRQ_MASK,
- .status_mask = IT_CHANGE_S_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_IT_CHANGE_S,
+ .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
+ .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
}, {
- .virq = VIRQ_I2S,
- .enb_mask = I2S_IRQ_MASK,
- .status_mask = I2S_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_I2S,
+ .enb_mask = SPEAR300_I2S_IRQ_MASK,
+ .status_mask = SPEAR300_I2S_IRQ_MASK,
}, {
- .virq = VIRQ_TDM,
- .enb_mask = TDM_IRQ_MASK,
- .status_mask = TDM_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_TDM,
+ .enb_mask = SPEAR300_TDM_IRQ_MASK,
+ .status_mask = SPEAR300_TDM_IRQ_MASK,
}, {
- .virq = VIRQ_CAMERA_L,
- .enb_mask = CAMERA_L_IRQ_MASK,
- .status_mask = CAMERA_L_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_CAMERA_L,
+ .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
+ .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
}, {
- .virq = VIRQ_CAMERA_F,
- .enb_mask = CAMERA_F_IRQ_MASK,
- .status_mask = CAMERA_F_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_CAMERA_F,
+ .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
+ .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
}, {
- .virq = VIRQ_CAMERA_V,
- .enb_mask = CAMERA_V_IRQ_MASK,
- .status_mask = CAMERA_V_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_CAMERA_V,
+ .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
+ .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
}, {
- .virq = VIRQ_KEYBOARD,
- .enb_mask = KEYBOARD_IRQ_MASK,
- .status_mask = KEYBOARD_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_KEYBOARD,
+ .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
+ .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
}, {
- .virq = VIRQ_GPIO1,
- .enb_mask = GPIO1_IRQ_MASK,
- .status_mask = GPIO1_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_GPIO1,
+ .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
+ .status_mask = SPEAR300_GPIO1_IRQ_MASK,
},
};
static struct spear_shirq shirq_ras1 = {
- .irq = IRQ_GEN_RAS_1,
+ .irq = SPEAR3XX_IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
.regs = {
- .enb_reg = INT_ENB_MASK_REG,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS1_MASK,
+ .enb_reg = SPEAR300_INT_ENB_MASK_REG,
+ .status_reg = SPEAR300_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
.clear_reg = -1,
},
};
@@ -579,7 +579,7 @@ static struct spear_shirq shirq_ras1 = {
/* arm gpio1 device registration */
static struct pl061_platform_data gpio1_plat_data = {
.gpio_base = 8,
- .irq_base = SPEAR_GPIO1_INT_BASE,
+ .irq_base = SPEAR300_GPIO1_INT_BASE,
};
struct amba_device gpio1_device = {
@@ -592,7 +592,7 @@ struct amba_device gpio1_device = {
.end = SPEAR300_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {VIRQ_GPIO1, NO_IRQ},
+ .irq = {SPEAR300_VIRQ_GPIO1, NO_IRQ},
};
/* spear300 routines */
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 3a2c4b2..9f18d28 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -194,115 +194,115 @@ struct pmx_driver pmx_driver;
/* spear3xx shared irq */
static struct shirq_dev_config shirq_ras1_config[] = {
{
- .virq = VIRQ_SMII0,
- .status_mask = SMII0_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_SMII0,
+ .status_mask = SPEAR310_SMII0_IRQ_MASK,
}, {
- .virq = VIRQ_SMII1,
- .status_mask = SMII1_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_SMII1,
+ .status_mask = SPEAR310_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_SMII2,
- .status_mask = SMII2_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_SMII2,
+ .status_mask = SPEAR310_SMII2_IRQ_MASK,
}, {
- .virq = VIRQ_SMII3,
- .status_mask = SMII3_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_SMII3,
+ .status_mask = SPEAR310_SMII3_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII0,
- .status_mask = WAKEUP_SMII0_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
+ .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII1,
- .status_mask = WAKEUP_SMII1_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
+ .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII2,
- .status_mask = WAKEUP_SMII2_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
+ .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII3,
- .status_mask = WAKEUP_SMII3_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
+ .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
},
};
static struct spear_shirq shirq_ras1 = {
- .irq = IRQ_GEN_RAS_1,
+ .irq = SPEAR3XX_IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS1_MASK,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
.clear_reg = -1,
},
};
static struct shirq_dev_config shirq_ras2_config[] = {
{
- .virq = VIRQ_UART1,
- .status_mask = UART1_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART1,
+ .status_mask = SPEAR310_UART1_IRQ_MASK,
}, {
- .virq = VIRQ_UART2,
- .status_mask = UART2_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART2,
+ .status_mask = SPEAR310_UART2_IRQ_MASK,
}, {
- .virq = VIRQ_UART3,
- .status_mask = UART3_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART3,
+ .status_mask = SPEAR310_UART3_IRQ_MASK,
}, {
- .virq = VIRQ_UART4,
- .status_mask = UART4_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART4,
+ .status_mask = SPEAR310_UART4_IRQ_MASK,
}, {
- .virq = VIRQ_UART5,
- .status_mask = UART5_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART5,
+ .status_mask = SPEAR310_UART5_IRQ_MASK,
},
};
static struct spear_shirq shirq_ras2 = {
- .irq = IRQ_GEN_RAS_2,
+ .irq = SPEAR3XX_IRQ_GEN_RAS_2,
.dev_config = shirq_ras2_config,
.dev_count = ARRAY_SIZE(shirq_ras2_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS2_MASK,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
.clear_reg = -1,
},
};
static struct shirq_dev_config shirq_ras3_config[] = {
{
- .virq = VIRQ_EMI,
- .status_mask = EMI_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_EMI,
+ .status_mask = SPEAR310_EMI_IRQ_MASK,
},
};
static struct spear_shirq shirq_ras3 = {
- .irq = IRQ_GEN_RAS_3,
+ .irq = SPEAR3XX_IRQ_GEN_RAS_3,
.dev_config = shirq_ras3_config,
.dev_count = ARRAY_SIZE(shirq_ras3_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS3_MASK,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
.clear_reg = -1,
},
};
static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
{
- .virq = VIRQ_TDM_HDLC,
- .status_mask = TDM_HDLC_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_TDM_HDLC,
+ .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
}, {
- .virq = VIRQ_RS485_0,
- .status_mask = RS485_0_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_RS485_0,
+ .status_mask = SPEAR310_RS485_0_IRQ_MASK,
}, {
- .virq = VIRQ_RS485_1,
- .status_mask = RS485_1_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_RS485_1,
+ .status_mask = SPEAR310_RS485_1_IRQ_MASK,
},
};
static struct spear_shirq shirq_intrcomm_ras = {
- .irq = IRQ_INTRCOMM_RAS_ARM,
+ .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
.dev_config = shirq_intrcomm_ras_config,
.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
.clear_reg = -1,
},
};
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index fee265b..69b9549 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -589,123 +589,123 @@ struct pmx_driver pmx_driver = {
/* spear3xx shared irq */
static struct shirq_dev_config shirq_ras1_config[] = {
{
- .virq = VIRQ_EMI,
- .status_mask = EMI_IRQ_MASK,
- .clear_mask = EMI_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_EMI,
+ .status_mask = SPEAR320_EMI_IRQ_MASK,
+ .clear_mask = SPEAR320_EMI_IRQ_MASK,
}, {
- .virq = VIRQ_CLCD,
- .status_mask = CLCD_IRQ_MASK,
- .clear_mask = CLCD_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_CLCD,
+ .status_mask = SPEAR320_CLCD_IRQ_MASK,
+ .clear_mask = SPEAR320_CLCD_IRQ_MASK,
}, {
- .virq = VIRQ_SPP,
- .status_mask = SPP_IRQ_MASK,
- .clear_mask = SPP_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_SPP,
+ .status_mask = SPEAR320_SPP_IRQ_MASK,
+ .clear_mask = SPEAR320_SPP_IRQ_MASK,
},
};
static struct spear_shirq shirq_ras1 = {
- .irq = IRQ_GEN_RAS_1,
+ .irq = SPEAR3XX_IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS1_MASK,
- .clear_reg = INT_CLR_MASK_REG,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,
},
};
static struct shirq_dev_config shirq_ras3_config[] = {
{
- .virq = VIRQ_PLGPIO,
- .enb_mask = GPIO_IRQ_MASK,
- .status_mask = GPIO_IRQ_MASK,
- .clear_mask = GPIO_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_PLGPIO,
+ .enb_mask = SPEAR320_GPIO_IRQ_MASK,
+ .status_mask = SPEAR320_GPIO_IRQ_MASK,
+ .clear_mask = SPEAR320_GPIO_IRQ_MASK,
}, {
- .virq = VIRQ_I2S_PLAY,
- .enb_mask = I2S_PLAY_IRQ_MASK,
- .status_mask = I2S_PLAY_IRQ_MASK,
- .clear_mask = I2S_PLAY_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_I2S_PLAY,
+ .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
+ .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
+ .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
}, {
- .virq = VIRQ_I2S_REC,
- .enb_mask = I2S_REC_IRQ_MASK,
- .status_mask = I2S_REC_IRQ_MASK,
- .clear_mask = I2S_REC_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_I2S_REC,
+ .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
+ .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
+ .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
},
};
static struct spear_shirq shirq_ras3 = {
- .irq = IRQ_GEN_RAS_3,
+ .irq = SPEAR3XX_IRQ_GEN_RAS_3,
.dev_config = shirq_ras3_config,
.dev_count = ARRAY_SIZE(shirq_ras3_config),
.regs = {
- .enb_reg = INT_ENB_MASK_REG,
+ .enb_reg = SPEAR320_INT_ENB_MASK_REG,
.reset_to_enb = 1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS3_MASK,
- .clear_reg = INT_CLR_MASK_REG,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,
},
};
static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
{
- .virq = VIRQ_CANU,
- .status_mask = CAN_U_IRQ_MASK,
- .clear_mask = CAN_U_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_CANU,
+ .status_mask = SPEAR320_CAN_U_IRQ_MASK,
+ .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
}, {
- .virq = VIRQ_CANL,
- .status_mask = CAN_L_IRQ_MASK,
- .clear_mask = CAN_L_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_CANL,
+ .status_mask = SPEAR320_CAN_L_IRQ_MASK,
+ .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
}, {
- .virq = VIRQ_UART1,
- .status_mask = UART1_IRQ_MASK,
- .clear_mask = UART1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_UART1,
+ .status_mask = SPEAR320_UART1_IRQ_MASK,
+ .clear_mask = SPEAR320_UART1_IRQ_MASK,
}, {
- .virq = VIRQ_UART2,
- .status_mask = UART2_IRQ_MASK,
- .clear_mask = UART2_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_UART2,
+ .status_mask = SPEAR320_UART2_IRQ_MASK,
+ .clear_mask = SPEAR320_UART2_IRQ_MASK,
}, {
- .virq = VIRQ_SSP1,
- .status_mask = SSP1_IRQ_MASK,
- .clear_mask = SSP1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_SSP1,
+ .status_mask = SPEAR320_SSP1_IRQ_MASK,
+ .clear_mask = SPEAR320_SSP1_IRQ_MASK,
}, {
- .virq = VIRQ_SSP2,
- .status_mask = SSP2_IRQ_MASK,
- .clear_mask = SSP2_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_SSP2,
+ .status_mask = SPEAR320_SSP2_IRQ_MASK,
+ .clear_mask = SPEAR320_SSP2_IRQ_MASK,
}, {
- .virq = VIRQ_SMII0,
- .status_mask = SMII0_IRQ_MASK,
- .clear_mask = SMII0_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_SMII0,
+ .status_mask = SPEAR320_SMII0_IRQ_MASK,
+ .clear_mask = SPEAR320_SMII0_IRQ_MASK,
}, {
- .virq = VIRQ_MII1_SMII1,
- .status_mask = MII1_SMII1_IRQ_MASK,
- .clear_mask = MII1_SMII1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_MII1_SMII1,
+ .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
+ .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII0,
- .status_mask = WAKEUP_SMII0_IRQ_MASK,
- .clear_mask = WAKEUP_SMII0_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
+ .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
+ .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_MII1_SMII1,
- .status_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
- .clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
+ .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
+ .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_I2C,
- .status_mask = I2C1_IRQ_MASK,
- .clear_mask = I2C1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_I2C1,
+ .status_mask = SPEAR320_I2C1_IRQ_MASK,
+ .clear_mask = SPEAR320_I2C1_IRQ_MASK,
},
};
static struct spear_shirq shirq_intrcomm_ras = {
- .irq = IRQ_INTRCOMM_RAS_ARM,
+ .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
.dev_config = shirq_intrcomm_ras_config,
.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
- .clear_reg = INT_CLR_MASK_REG,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,
},
};
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 9a9e92b..9ae7009 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -25,7 +25,7 @@
/* gpio device registration */
static struct pl061_platform_data gpio_plat_data = {
.gpio_base = 0,
- .irq_base = SPEAR_GPIO_INT_BASE,
+ .irq_base = SPEAR3XX_GPIO_INT_BASE,
};
struct amba_device gpio_device = {
@@ -38,7 +38,7 @@ struct amba_device gpio_device = {
.end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {IRQ_BASIC_GPIO, NO_IRQ},
+ .irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ},
};
/* uart device registration */
@@ -51,7 +51,7 @@ struct amba_device uart_device = {
.end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {IRQ_UART, NO_IRQ},
+ .irq = {SPEAR3XX_IRQ_UART, NO_IRQ},
};
/* Do spear3xx familiy common initialization part here */
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 06/11] ST SPEAr3xx: Rework pmx_dev code to remove conflicts
From: Viresh Kumar @ 2011-03-01 11:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977709.git.viresh.kumar@st.com>
From: Ryan Mallon <ryan@bluewatersys.com>
Prefix the pmx_devs to remove naming conflicts between the three
SPEAr3xx platforms. Also make pmx_driver static to each platform and
rework the init code to pass the devices rather than export the
pmx_driver structure.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 193 +++++++++++++------------
arch/arm/mach-spear3xx/spear300.c | 66 +++++----
arch/arm/mach-spear3xx/spear300_evb.c | 26 ++--
arch/arm/mach-spear3xx/spear310.c | 28 ++--
arch/arm/mach-spear3xx/spear310_evb.c | 41 +++---
arch/arm/mach-spear3xx/spear320.c | 64 +++++----
arch/arm/mach-spear3xx/spear320_evb.c | 36 ++---
arch/arm/mach-spear3xx/spear3xx.c | 60 ++++----
8 files changed, 257 insertions(+), 257 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index c2b15b1..9186e5a 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -61,85 +61,84 @@ void spear3xx_pmx_init_addr(struct pmx_driver *driver, unsigned int addr);
#define PMX_TIMER_1_2_MASK (1 << 0)
/* pad mux devices */
-extern struct pmx_dev pmx_firda;
-extern struct pmx_dev pmx_i2c;
-extern struct pmx_dev pmx_ssp_cs;
-extern struct pmx_dev pmx_ssp;
-extern struct pmx_dev pmx_mii;
-extern struct pmx_dev pmx_gpio_pin0;
-extern struct pmx_dev pmx_gpio_pin1;
-extern struct pmx_dev pmx_gpio_pin2;
-extern struct pmx_dev pmx_gpio_pin3;
-extern struct pmx_dev pmx_gpio_pin4;
-extern struct pmx_dev pmx_gpio_pin5;
-extern struct pmx_dev pmx_uart0_modem;
-extern struct pmx_dev pmx_uart0;
-extern struct pmx_dev pmx_timer_3_4;
-extern struct pmx_dev pmx_timer_1_2;
+extern struct pmx_dev spear3xx_pmx_firda;
+extern struct pmx_dev spear3xx_pmx_i2c;
+extern struct pmx_dev spear3xx_pmx_ssp_cs;
+extern struct pmx_dev spear3xx_pmx_ssp;
+extern struct pmx_dev spear3xx_pmx_mii;
+extern struct pmx_dev spear3xx_pmx_gpio_pin0;
+extern struct pmx_dev spear3xx_pmx_gpio_pin1;
+extern struct pmx_dev spear3xx_pmx_gpio_pin2;
+extern struct pmx_dev spear3xx_pmx_gpio_pin3;
+extern struct pmx_dev spear3xx_pmx_gpio_pin4;
+extern struct pmx_dev spear3xx_pmx_gpio_pin5;
+extern struct pmx_dev spear3xx_pmx_uart0_modem;
+extern struct pmx_dev spear3xx_pmx_uart0;
+extern struct pmx_dev spear3xx_pmx_timer_3_4;
+extern struct pmx_dev spear3xx_pmx_timer_1_2;
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
/* padmux plgpio devices */
-extern struct pmx_dev pmx_plgpio_0_1;
-extern struct pmx_dev pmx_plgpio_2_3;
-extern struct pmx_dev pmx_plgpio_4_5;
-extern struct pmx_dev pmx_plgpio_6_9;
-extern struct pmx_dev pmx_plgpio_10_27;
-extern struct pmx_dev pmx_plgpio_28;
-extern struct pmx_dev pmx_plgpio_29;
-extern struct pmx_dev pmx_plgpio_30;
-extern struct pmx_dev pmx_plgpio_31;
-extern struct pmx_dev pmx_plgpio_32;
-extern struct pmx_dev pmx_plgpio_33;
-extern struct pmx_dev pmx_plgpio_34_36;
-extern struct pmx_dev pmx_plgpio_37_42;
-extern struct pmx_dev pmx_plgpio_43_44_47_48;
-extern struct pmx_dev pmx_plgpio_45_46_49_50;
+extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
+extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
+extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
+extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
+extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
+extern struct pmx_dev spear3xx_pmx_plgpio_28;
+extern struct pmx_dev spear3xx_pmx_plgpio_29;
+extern struct pmx_dev spear3xx_pmx_plgpio_30;
+extern struct pmx_dev spear3xx_pmx_plgpio_31;
+extern struct pmx_dev spear3xx_pmx_plgpio_32;
+extern struct pmx_dev spear3xx_pmx_plgpio_33;
+extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
+extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
+extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
+extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
#endif
-extern struct pmx_driver pmx_driver;
-
/* spear300 declarations */
#ifdef CONFIG_MACH_SPEAR300
/* Add spear300 machine device structure declarations here */
extern struct amba_device gpio1_device;
/* pad mux modes */
-extern struct pmx_mode nand_mode;
-extern struct pmx_mode nor_mode;
-extern struct pmx_mode photo_frame_mode;
-extern struct pmx_mode lend_ip_phone_mode;
-extern struct pmx_mode hend_ip_phone_mode;
-extern struct pmx_mode lend_wifi_phone_mode;
-extern struct pmx_mode hend_wifi_phone_mode;
-extern struct pmx_mode ata_pabx_wi2s_mode;
-extern struct pmx_mode ata_pabx_i2s_mode;
-extern struct pmx_mode caml_lcdw_mode;
-extern struct pmx_mode camu_lcd_mode;
-extern struct pmx_mode camu_wlcd_mode;
-extern struct pmx_mode caml_lcd_mode;
+extern struct pmx_mode spear300_nand_mode;
+extern struct pmx_mode spear300_nor_mode;
+extern struct pmx_mode spear300_photo_frame_mode;
+extern struct pmx_mode spear300_lend_ip_phone_mode;
+extern struct pmx_mode spear300_hend_ip_phone_mode;
+extern struct pmx_mode spear300_lend_wifi_phone_mode;
+extern struct pmx_mode spear300_hend_wifi_phone_mode;
+extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
+extern struct pmx_mode spear300_ata_pabx_i2s_mode;
+extern struct pmx_mode spear300_caml_lcdw_mode;
+extern struct pmx_mode spear300_camu_lcd_mode;
+extern struct pmx_mode spear300_camu_wlcd_mode;
+extern struct pmx_mode spear300_caml_lcd_mode;
/* pad mux devices */
-extern struct pmx_dev pmx_fsmc_2_chips;
-extern struct pmx_dev pmx_fsmc_4_chips;
-extern struct pmx_dev pmx_keyboard;
-extern struct pmx_dev pmx_clcd;
-extern struct pmx_dev pmx_telecom_gpio;
-extern struct pmx_dev pmx_telecom_tdm;
-extern struct pmx_dev pmx_telecom_spi_cs_i2c_clk;
-extern struct pmx_dev pmx_telecom_camera;
-extern struct pmx_dev pmx_telecom_dac;
-extern struct pmx_dev pmx_telecom_i2s;
-extern struct pmx_dev pmx_telecom_boot_pins;
-extern struct pmx_dev pmx_telecom_sdhci_4bit;
-extern struct pmx_dev pmx_telecom_sdhci_8bit;
-extern struct pmx_dev pmx_gpio1;
+extern struct pmx_dev spear300_pmx_fsmc_2_chips;
+extern struct pmx_dev spear300_pmx_fsmc_4_chips;
+extern struct pmx_dev spear300_pmx_keyboard;
+extern struct pmx_dev spear300_pmx_clcd;
+extern struct pmx_dev spear300_pmx_telecom_gpio;
+extern struct pmx_dev spear300_pmx_telecom_tdm;
+extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
+extern struct pmx_dev spear300_pmx_telecom_camera;
+extern struct pmx_dev spear300_pmx_telecom_dac;
+extern struct pmx_dev spear300_pmx_telecom_i2s;
+extern struct pmx_dev spear300_pmx_telecom_boot_pins;
+extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
+extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
+extern struct pmx_dev spear300_pmx_gpio1;
/* pad multiplexing support */
#define SPEAR300_PAD_MUX_CONFIG_REG 0x99000000
#define SPEAR300_MODE_CONFIG_REG 0x99000004
/* Add spear300 machine function declarations here */
-void __init spear300_init(void);
+void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
#endif /* CONFIG_MACH_SPEAR300 */
@@ -148,18 +147,19 @@ void __init spear300_init(void);
/* Add spear310 machine device structure declarations here */
/* pad mux devices */
-extern struct pmx_dev pmx_emi_cs_0_1_4_5;
-extern struct pmx_dev pmx_emi_cs_2_3;
-extern struct pmx_dev pmx_uart1;
-extern struct pmx_dev pmx_uart2;
-extern struct pmx_dev pmx_uart3_4_5;
-extern struct pmx_dev pmx_fsmc;
-extern struct pmx_dev pmx_rs485_0_1;
-extern struct pmx_dev pmx_tdm0;
+extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
+extern struct pmx_dev spear310_pmx_emi_cs_2_3;
+extern struct pmx_dev spear310_pmx_uart1;
+extern struct pmx_dev spear310_pmx_uart2;
+extern struct pmx_dev spear310_pmx_uart3_4_5;
+extern struct pmx_dev spear310_pmx_fsmc;
+extern struct pmx_dev spear310_pmx_rs485_0_1;
+extern struct pmx_dev spear310_pmx_tdm0;
#define SPEAR310_PAD_MUX_CONFIG_REG 0xB4000008
/* Add spear310 machine function declarations here */
-void __init spear310_init(void);
+void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
#endif /* CONFIG_MACH_SPEAR310 */
@@ -168,41 +168,42 @@ void __init spear310_init(void);
/* Add spear320 machine device structure declarations here */
/* pad mux modes */
-extern struct pmx_mode auto_net_smii_mode;
-extern struct pmx_mode auto_net_mii_mode;
-extern struct pmx_mode auto_exp_mode;
-extern struct pmx_mode small_printers_mode;
+extern struct pmx_mode spear320_auto_net_smii_mode;
+extern struct pmx_mode spear320_auto_net_mii_mode;
+extern struct pmx_mode spear320_auto_exp_mode;
+extern struct pmx_mode spear320_small_printers_mode;
/* pad mux devices */
-extern struct pmx_dev pmx_clcd;
-extern struct pmx_dev pmx_emi;
-extern struct pmx_dev pmx_fsmc;
-extern struct pmx_dev pmx_spp;
-extern struct pmx_dev pmx_sdhci;
-extern struct pmx_dev pmx_i2s;
-extern struct pmx_dev pmx_uart1;
-extern struct pmx_dev pmx_uart1_modem;
-extern struct pmx_dev pmx_uart2;
-extern struct pmx_dev pmx_touchscreen;
-extern struct pmx_dev pmx_can;
-extern struct pmx_dev pmx_sdhci_led;
-extern struct pmx_dev pmx_pwm0;
-extern struct pmx_dev pmx_pwm1;
-extern struct pmx_dev pmx_pwm2;
-extern struct pmx_dev pmx_pwm3;
-extern struct pmx_dev pmx_ssp1;
-extern struct pmx_dev pmx_ssp2;
-extern struct pmx_dev pmx_mii1;
-extern struct pmx_dev pmx_smii0;
-extern struct pmx_dev pmx_smii1;
-extern struct pmx_dev pmx_i2c1;
+extern struct pmx_dev spear320_pmx_clcd;
+extern struct pmx_dev spear320_pmx_emi;
+extern struct pmx_dev spear320_pmx_fsmc;
+extern struct pmx_dev spear320_pmx_spp;
+extern struct pmx_dev spear320_pmx_sdhci;
+extern struct pmx_dev spear320_pmx_i2s;
+extern struct pmx_dev spear320_pmx_uart1;
+extern struct pmx_dev spear320_pmx_uart1_modem;
+extern struct pmx_dev spear320_pmx_uart2;
+extern struct pmx_dev spear320_pmx_touchscreen;
+extern struct pmx_dev spear320_pmx_can;
+extern struct pmx_dev spear320_pmx_sdhci_led;
+extern struct pmx_dev spear320_pmx_pwm0;
+extern struct pmx_dev spear320_pmx_pwm1;
+extern struct pmx_dev spear320_pmx_pwm2;
+extern struct pmx_dev spear320_pmx_pwm3;
+extern struct pmx_dev spear320_pmx_ssp1;
+extern struct pmx_dev spear320_pmx_ssp2;
+extern struct pmx_dev spear320_pmx_mii1;
+extern struct pmx_dev spear320_pmx_smii0;
+extern struct pmx_dev spear320_pmx_smii1;
+extern struct pmx_dev spear320_pmx_i2c1;
/* pad multiplexing support */
#define SPEAR320_PAD_MUX_CONFIG_REG 0xB300000C
#define SPEAR320_MODE_CONFIG_REG 0xB3000010
/* Add spear320 machine function declarations here */
-void __init spear320_init(void);
+void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index e1b2580..2618181 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -35,79 +35,79 @@
#define CAML_LCD_MODE (1 << 12)
#define ALL_MODES 0x1FFF
-struct pmx_mode nand_mode = {
+struct pmx_mode spear300_nand_mode = {
.id = NAND_MODE,
.name = "nand mode",
.value = 0x00,
};
-struct pmx_mode nor_mode = {
+struct pmx_mode spear300_nor_mode = {
.id = NOR_MODE,
.name = "nor mode",
.value = 0x01,
};
-struct pmx_mode photo_frame_mode = {
+struct pmx_mode spear300_photo_frame_mode = {
.id = PHOTO_FRAME_MODE,
.name = "photo frame mode",
.value = 0x02,
};
-struct pmx_mode lend_ip_phone_mode = {
+struct pmx_mode spear300_lend_ip_phone_mode = {
.id = LEND_IP_PHONE_MODE,
.name = "lend ip phone mode",
.value = 0x03,
};
-struct pmx_mode hend_ip_phone_mode = {
+struct pmx_mode spear300_hend_ip_phone_mode = {
.id = HEND_IP_PHONE_MODE,
.name = "hend ip phone mode",
.value = 0x04,
};
-struct pmx_mode lend_wifi_phone_mode = {
+struct pmx_mode spear300_lend_wifi_phone_mode = {
.id = LEND_WIFI_PHONE_MODE,
.name = "lend wifi phone mode",
.value = 0x05,
};
-struct pmx_mode hend_wifi_phone_mode = {
+struct pmx_mode spear300_hend_wifi_phone_mode = {
.id = HEND_WIFI_PHONE_MODE,
.name = "hend wifi phone mode",
.value = 0x06,
};
-struct pmx_mode ata_pabx_wi2s_mode = {
+struct pmx_mode spear300_ata_pabx_wi2s_mode = {
.id = ATA_PABX_WI2S_MODE,
.name = "ata pabx wi2s mode",
.value = 0x07,
};
-struct pmx_mode ata_pabx_i2s_mode = {
+struct pmx_mode spear300_ata_pabx_i2s_mode = {
.id = ATA_PABX_I2S_MODE,
.name = "ata pabx i2s mode",
.value = 0x08,
};
-struct pmx_mode caml_lcdw_mode = {
+struct pmx_mode spear300_caml_lcdw_mode = {
.id = CAML_LCDW_MODE,
.name = "caml lcdw mode",
.value = 0x0C,
};
-struct pmx_mode camu_lcd_mode = {
+struct pmx_mode spear300_camu_lcd_mode = {
.id = CAMU_LCD_MODE,
.name = "camu lcd mode",
.value = 0x0D,
};
-struct pmx_mode camu_wlcd_mode = {
+struct pmx_mode spear300_camu_wlcd_mode = {
.id = CAMU_WLCD_MODE,
.name = "camu wlcd mode",
.value = 0x0E,
};
-struct pmx_mode caml_lcd_mode = {
+struct pmx_mode spear300_caml_lcd_mode = {
.id = CAML_LCD_MODE,
.name = "caml lcd mode",
.value = 0x0F,
@@ -130,7 +130,7 @@ static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
},
};
-struct pmx_dev pmx_fsmc_2_chips = {
+struct pmx_dev spear300_pmx_fsmc_2_chips = {
.name = "fsmc_2_chips",
.modes = pmx_fsmc_2_chips_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
@@ -153,7 +153,7 @@ static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
},
};
-struct pmx_dev pmx_fsmc_4_chips = {
+struct pmx_dev spear300_pmx_fsmc_4_chips = {
.name = "fsmc_4_chips",
.modes = pmx_fsmc_4_chips_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
@@ -178,7 +178,7 @@ static struct pmx_dev_mode pmx_keyboard_modes[] = {
},
};
-struct pmx_dev pmx_keyboard = {
+struct pmx_dev spear300_pmx_keyboard = {
.name = "keyboard",
.modes = pmx_keyboard_modes,
.mode_count = ARRAY_SIZE(pmx_keyboard_modes),
@@ -212,7 +212,7 @@ static struct pmx_dev_mode pmx_clcd_modes[] = {
},
};
-struct pmx_dev pmx_clcd = {
+struct pmx_dev spear300_pmx_clcd = {
.name = "clcd",
.modes = pmx_clcd_modes,
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
@@ -279,7 +279,7 @@ static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
},
};
-struct pmx_dev pmx_telecom_gpio = {
+struct pmx_dev spear300_pmx_telecom_gpio = {
.name = "telecom_gpio",
.modes = pmx_telecom_gpio_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
@@ -305,7 +305,7 @@ static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
},
};
-struct pmx_dev pmx_telecom_tdm = {
+struct pmx_dev spear300_pmx_telecom_tdm = {
.name = "telecom_tdm",
.modes = pmx_telecom_tdm_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
@@ -330,7 +330,7 @@ static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
},
};
-struct pmx_dev pmx_telecom_spi_cs_i2c_clk = {
+struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
.name = "telecom_spi_cs_i2c_clk",
.modes = pmx_telecom_spi_cs_i2c_clk_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
@@ -362,7 +362,7 @@ static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
},
};
-struct pmx_dev pmx_telecom_camera = {
+struct pmx_dev spear300_pmx_telecom_camera = {
.name = "telecom_camera",
.modes = pmx_telecom_camera_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
@@ -385,7 +385,7 @@ static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
},
};
-struct pmx_dev pmx_telecom_dac = {
+struct pmx_dev spear300_pmx_telecom_dac = {
.name = "telecom_dac",
.modes = pmx_telecom_dac_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
@@ -410,7 +410,7 @@ static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
},
};
-struct pmx_dev pmx_telecom_i2s = {
+struct pmx_dev spear300_pmx_telecom_i2s = {
.name = "telecom_i2s",
.modes = pmx_telecom_i2s_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
@@ -433,7 +433,7 @@ static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
},
};
-struct pmx_dev pmx_telecom_boot_pins = {
+struct pmx_dev spear300_pmx_telecom_boot_pins = {
.name = "telecom_boot_pins",
.modes = pmx_telecom_boot_pins_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
@@ -461,7 +461,7 @@ static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
},
};
-struct pmx_dev pmx_telecom_sdhci_4bit = {
+struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
.name = "telecom_sdhci_4bit",
.modes = pmx_telecom_sdhci_4bit_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
@@ -488,7 +488,7 @@ static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
},
};
-struct pmx_dev pmx_telecom_sdhci_8bit = {
+struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
.name = "telecom_sdhci_8bit",
.modes = pmx_telecom_sdhci_8bit_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
@@ -511,14 +511,14 @@ static struct pmx_dev_mode pmx_gpio1_modes[] = {
},
};
-struct pmx_dev pmx_gpio1 = {
+struct pmx_dev spear300_pmx_gpio1 = {
.name = "arm gpio1",
.modes = pmx_gpio1_modes,
.mode_count = ARRAY_SIZE(pmx_gpio1_modes),
};
/* pmx driver structure */
-struct pmx_driver pmx_driver = {
+static struct pmx_driver pmx_driver = {
.mode_reg = {.address = SPEAR300_MODE_CONFIG_REG, .mask = 0x0000000f},
};
@@ -596,7 +596,8 @@ struct amba_device gpio1_device = {
};
/* spear300 routines */
-void __init spear300_init(void)
+void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
int ret = 0;
@@ -611,10 +612,13 @@ void __init spear300_init(void)
printk(KERN_ERR "Error registering Shared IRQ\n");
}
+ /* pmx initialization */
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
/* This fixes addresses of all pmx devices for spear300 */
spear3xx_pmx_init_addr(&pmx_driver, SPEAR300_PAD_MUX_CONFIG_REG);
-
- /* pmx initialization */
ret = pmx_register(&pmx_driver);
if (ret)
pr_err("padmux: registeration failed. err no: %d\n", ret);
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 42d2253..405ae09 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -19,17 +19,17 @@
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
- &pmx_i2c,
- &pmx_ssp_cs,
- &pmx_ssp,
- &pmx_mii,
- &pmx_uart0,
+ &spear3xx_pmx_i2c,
+ &spear3xx_pmx_ssp_cs,
+ &spear3xx_pmx_ssp,
+ &spear3xx_pmx_mii,
+ &spear3xx_pmx_uart0,
/* spear300 specific devices */
- &pmx_fsmc_2_chips,
- &pmx_clcd,
- &pmx_telecom_sdhci_4bit,
- &pmx_gpio1,
+ &spear300_pmx_fsmc_2_chips,
+ &spear300_pmx_clcd,
+ &spear300_pmx_telecom_sdhci_4bit,
+ &spear300_pmx_gpio1,
};
static struct amba_device *amba_devs[] __initdata = {
@@ -51,13 +51,9 @@ static void __init spear300_evb_init(void)
{
unsigned int i;
- /* padmux initialization, must be done before spear300_init */
- pmx_driver.mode = &photo_frame_mode;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-
/* call spear300 machine init function */
- spear300_init();
+ spear300_init(&spear300_photo_frame_mode, pmx_devs,
+ ARRAY_SIZE(pmx_devs));
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 9f18d28..4522e48 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -35,7 +35,7 @@ static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
},
};
-struct pmx_dev pmx_emi_cs_0_1_4_5 = {
+struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
.name = "emi_cs_0_1_4_5",
.modes = pmx_emi_cs_0_1_4_5_modes,
.mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
@@ -56,7 +56,7 @@ static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
},
};
-struct pmx_dev pmx_emi_cs_2_3 = {
+struct pmx_dev spear310_pmx_emi_cs_2_3 = {
.name = "emi_cs_2_3",
.modes = pmx_emi_cs_2_3_modes,
.mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
@@ -77,7 +77,7 @@ static struct pmx_dev_mode pmx_uart1_modes[] = {
},
};
-struct pmx_dev pmx_uart1 = {
+struct pmx_dev spear310_pmx_uart1 = {
.name = "uart1",
.modes = pmx_uart1_modes,
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
@@ -98,7 +98,7 @@ static struct pmx_dev_mode pmx_uart2_modes[] = {
},
};
-struct pmx_dev pmx_uart2 = {
+struct pmx_dev spear310_pmx_uart2 = {
.name = "uart2",
.modes = pmx_uart2_modes,
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
@@ -119,7 +119,7 @@ static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
},
};
-struct pmx_dev pmx_uart3_4_5 = {
+struct pmx_dev spear310_pmx_uart3_4_5 = {
.name = "uart3_4_5",
.modes = pmx_uart3_4_5_modes,
.mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
@@ -140,7 +140,7 @@ static struct pmx_dev_mode pmx_fsmc_modes[] = {
},
};
-struct pmx_dev pmx_fsmc = {
+struct pmx_dev spear310_pmx_fsmc = {
.name = "fsmc",
.modes = pmx_fsmc_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
@@ -161,7 +161,7 @@ static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
},
};
-struct pmx_dev pmx_rs485_0_1 = {
+struct pmx_dev spear310_pmx_rs485_0_1 = {
.name = "rs485_0_1",
.modes = pmx_rs485_0_1_modes,
.mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
@@ -182,14 +182,14 @@ static struct pmx_dev_mode pmx_tdm0_modes[] = {
},
};
-struct pmx_dev pmx_tdm0 = {
+struct pmx_dev spear310_pmx_tdm0 = {
.name = "tdm0",
.modes = pmx_tdm0_modes,
.mode_count = ARRAY_SIZE(pmx_tdm0_modes),
};
/* pmx driver structure */
-struct pmx_driver pmx_driver;
+static struct pmx_driver pmx_driver;
/* spear3xx shared irq */
static struct shirq_dev_config shirq_ras1_config[] = {
@@ -310,7 +310,8 @@ static struct spear_shirq shirq_intrcomm_ras = {
/* Add spear310 specific devices here */
/* spear310 routines */
-void __init spear310_init(void)
+void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
void __iomem *base;
int ret = 0;
@@ -346,10 +347,13 @@ void __init spear310_init(void)
printk(KERN_ERR "Error registering Shared IRQ 4\n");
}
+ /* pmx initialization */
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
/* This fixes addresses of all pmx devices for spear310 */
spear3xx_pmx_init_addr(&pmx_driver, SPEAR310_PAD_MUX_CONFIG_REG);
-
- /* pmx initialization */
ret = pmx_register(&pmx_driver);
if (ret)
pr_err("padmux: registeration failed. err no: %d\n", ret);
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 2d7f333..9d4aadb 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -19,25 +19,25 @@
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
- &pmx_i2c,
- &pmx_ssp,
- &pmx_gpio_pin0,
- &pmx_gpio_pin1,
- &pmx_gpio_pin2,
- &pmx_gpio_pin3,
- &pmx_gpio_pin4,
- &pmx_gpio_pin5,
- &pmx_uart0,
+ &spear3xx_pmx_i2c,
+ &spear3xx_pmx_ssp,
+ &spear3xx_pmx_gpio_pin0,
+ &spear3xx_pmx_gpio_pin1,
+ &spear3xx_pmx_gpio_pin2,
+ &spear3xx_pmx_gpio_pin3,
+ &spear3xx_pmx_gpio_pin4,
+ &spear3xx_pmx_gpio_pin5,
+ &spear3xx_pmx_uart0,
/* spear310 specific devices */
- &pmx_emi_cs_0_1_4_5,
- &pmx_emi_cs_2_3,
- &pmx_uart1,
- &pmx_uart2,
- &pmx_uart3_4_5,
- &pmx_fsmc,
- &pmx_rs485_0_1,
- &pmx_tdm0,
+ &spear310_pmx_emi_cs_0_1_4_5,
+ &spear310_pmx_emi_cs_2_3,
+ &spear310_pmx_uart1,
+ &spear310_pmx_uart2,
+ &spear310_pmx_uart3_4_5,
+ &spear310_pmx_fsmc,
+ &spear310_pmx_rs485_0_1,
+ &spear310_pmx_tdm0,
};
static struct amba_device *amba_devs[] __initdata = {
@@ -58,13 +58,8 @@ static void __init spear310_evb_init(void)
{
unsigned int i;
- /* padmux initialization, must be done before spear310_init */
- pmx_driver.mode = NULL;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-
/* call spear310 machine init function */
- spear310_init();
+ spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 69b9549..a99cf7c 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -24,25 +24,25 @@
#define SMALL_PRINTERS_MODE (1 << 3)
#define ALL_MODES 0xF
-struct pmx_mode auto_net_smii_mode = {
+struct pmx_mode spear320_auto_net_smii_mode = {
.id = AUTO_NET_SMII_MODE,
.name = "Automation Networking SMII Mode",
.value = 0x00,
};
-struct pmx_mode auto_net_mii_mode = {
+struct pmx_mode spear320_auto_net_mii_mode = {
.id = AUTO_NET_MII_MODE,
.name = "Automation Networking MII Mode",
.value = 0x01,
};
-struct pmx_mode auto_exp_mode = {
+struct pmx_mode spear320_auto_exp_mode = {
.id = AUTO_EXP_MODE,
.name = "Automation Expanded Mode",
.value = 0x02,
};
-struct pmx_mode small_printers_mode = {
+struct pmx_mode spear320_small_printers_mode = {
.id = SMALL_PRINTERS_MODE,
.name = "Small Printers Mode",
.value = 0x03,
@@ -65,7 +65,7 @@ static struct pmx_dev_mode pmx_clcd_modes[] = {
},
};
-struct pmx_dev pmx_clcd = {
+struct pmx_dev spear320_pmx_clcd = {
.name = "clcd",
.modes = pmx_clcd_modes,
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
@@ -87,7 +87,7 @@ static struct pmx_dev_mode pmx_emi_modes[] = {
},
};
-struct pmx_dev pmx_emi = {
+struct pmx_dev spear320_pmx_emi = {
.name = "emi",
.modes = pmx_emi_modes,
.mode_count = ARRAY_SIZE(pmx_emi_modes),
@@ -109,7 +109,7 @@ static struct pmx_dev_mode pmx_fsmc_modes[] = {
},
};
-struct pmx_dev pmx_fsmc = {
+struct pmx_dev spear320_pmx_fsmc = {
.name = "fsmc",
.modes = pmx_fsmc_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
@@ -131,7 +131,7 @@ static struct pmx_dev_mode pmx_spp_modes[] = {
},
};
-struct pmx_dev pmx_spp = {
+struct pmx_dev spear320_pmx_spp = {
.name = "spp",
.modes = pmx_spp_modes,
.mode_count = ARRAY_SIZE(pmx_spp_modes),
@@ -154,7 +154,7 @@ static struct pmx_dev_mode pmx_sdhci_modes[] = {
},
};
-struct pmx_dev pmx_sdhci = {
+struct pmx_dev spear320_pmx_sdhci = {
.name = "sdhci",
.modes = pmx_sdhci_modes,
.mode_count = ARRAY_SIZE(pmx_sdhci_modes),
@@ -176,7 +176,7 @@ static struct pmx_dev_mode pmx_i2s_modes[] = {
},
};
-struct pmx_dev pmx_i2s = {
+struct pmx_dev spear320_pmx_i2s = {
.name = "i2s",
.modes = pmx_i2s_modes,
.mode_count = ARRAY_SIZE(pmx_i2s_modes),
@@ -198,7 +198,7 @@ static struct pmx_dev_mode pmx_uart1_modes[] = {
},
};
-struct pmx_dev pmx_uart1 = {
+struct pmx_dev spear320_pmx_uart1 = {
.name = "uart1",
.modes = pmx_uart1_modes,
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
@@ -233,7 +233,7 @@ static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
},
};
-struct pmx_dev pmx_uart1_modem = {
+struct pmx_dev spear320_pmx_uart1_modem = {
.name = "uart1_modem",
.modes = pmx_uart1_modem_modes,
.mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
@@ -255,7 +255,7 @@ static struct pmx_dev_mode pmx_uart2_modes[] = {
},
};
-struct pmx_dev pmx_uart2 = {
+struct pmx_dev spear320_pmx_uart2 = {
.name = "uart2",
.modes = pmx_uart2_modes,
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
@@ -277,7 +277,7 @@ static struct pmx_dev_mode pmx_touchscreen_modes[] = {
},
};
-struct pmx_dev pmx_touchscreen = {
+struct pmx_dev spear320_pmx_touchscreen = {
.name = "touchscreen",
.modes = pmx_touchscreen_modes,
.mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
@@ -300,7 +300,7 @@ static struct pmx_dev_mode pmx_can_modes[] = {
},
};
-struct pmx_dev pmx_can = {
+struct pmx_dev spear320_pmx_can = {
.name = "can",
.modes = pmx_can_modes,
.mode_count = ARRAY_SIZE(pmx_can_modes),
@@ -322,7 +322,7 @@ static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
},
};
-struct pmx_dev pmx_sdhci_led = {
+struct pmx_dev spear320_pmx_sdhci_led = {
.name = "sdhci_led",
.modes = pmx_sdhci_led_modes,
.mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
@@ -355,7 +355,7 @@ static struct pmx_dev_mode pmx_pwm0_modes[] = {
},
};
-struct pmx_dev pmx_pwm0 = {
+struct pmx_dev spear320_pmx_pwm0 = {
.name = "pwm0",
.modes = pmx_pwm0_modes,
.mode_count = ARRAY_SIZE(pmx_pwm0_modes),
@@ -388,7 +388,7 @@ static struct pmx_dev_mode pmx_pwm1_modes[] = {
},
};
-struct pmx_dev pmx_pwm1 = {
+struct pmx_dev spear320_pmx_pwm1 = {
.name = "pwm1",
.modes = pmx_pwm1_modes,
.mode_count = ARRAY_SIZE(pmx_pwm1_modes),
@@ -421,7 +421,7 @@ static struct pmx_dev_mode pmx_pwm2_modes[] = {
},
};
-struct pmx_dev pmx_pwm2 = {
+struct pmx_dev spear320_pmx_pwm2 = {
.name = "pwm2",
.modes = pmx_pwm2_modes,
.mode_count = ARRAY_SIZE(pmx_pwm2_modes),
@@ -443,7 +443,7 @@ static struct pmx_dev_mode pmx_pwm3_modes[] = {
},
};
-struct pmx_dev pmx_pwm3 = {
+struct pmx_dev spear320_pmx_pwm3 = {
.name = "pwm3",
.modes = pmx_pwm3_modes,
.mode_count = ARRAY_SIZE(pmx_pwm3_modes),
@@ -465,7 +465,7 @@ static struct pmx_dev_mode pmx_ssp1_modes[] = {
},
};
-struct pmx_dev pmx_ssp1 = {
+struct pmx_dev spear320_pmx_ssp1 = {
.name = "ssp1",
.modes = pmx_ssp1_modes,
.mode_count = ARRAY_SIZE(pmx_ssp1_modes),
@@ -487,7 +487,7 @@ static struct pmx_dev_mode pmx_ssp2_modes[] = {
},
};
-struct pmx_dev pmx_ssp2 = {
+struct pmx_dev spear320_pmx_ssp2 = {
.name = "ssp2",
.modes = pmx_ssp2_modes,
.mode_count = ARRAY_SIZE(pmx_ssp2_modes),
@@ -509,7 +509,7 @@ static struct pmx_dev_mode pmx_mii1_modes[] = {
},
};
-struct pmx_dev pmx_mii1 = {
+struct pmx_dev spear320_pmx_mii1 = {
.name = "mii1",
.modes = pmx_mii1_modes,
.mode_count = ARRAY_SIZE(pmx_mii1_modes),
@@ -531,7 +531,7 @@ static struct pmx_dev_mode pmx_smii0_modes[] = {
},
};
-struct pmx_dev pmx_smii0 = {
+struct pmx_dev spear320_pmx_smii0 = {
.name = "smii0",
.modes = pmx_smii0_modes,
.mode_count = ARRAY_SIZE(pmx_smii0_modes),
@@ -553,7 +553,7 @@ static struct pmx_dev_mode pmx_smii1_modes[] = {
},
};
-struct pmx_dev pmx_smii1 = {
+struct pmx_dev spear320_pmx_smii1 = {
.name = "smii1",
.modes = pmx_smii1_modes,
.mode_count = ARRAY_SIZE(pmx_smii1_modes),
@@ -575,14 +575,14 @@ static struct pmx_dev_mode pmx_i2c1_modes[] = {
},
};
-struct pmx_dev pmx_i2c1 = {
+struct pmx_dev spear320_pmx_i2c1 = {
.name = "i2c1",
.modes = pmx_i2c1_modes,
.mode_count = ARRAY_SIZE(pmx_i2c1_modes),
};
/* pmx driver structure */
-struct pmx_driver pmx_driver = {
+static struct pmx_driver pmx_driver = {
.mode_reg = {.address = SPEAR320_MODE_CONFIG_REG, .mask = 0x00000007},
};
@@ -713,7 +713,8 @@ static struct spear_shirq shirq_intrcomm_ras = {
/* Add spear320 specific devices here */
/* spear320 routines */
-void __init spear320_init(void)
+void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
void __iomem *base;
int ret = 0;
@@ -743,10 +744,13 @@ void __init spear320_init(void)
printk(KERN_ERR "Error registering Shared IRQ 4\n");
}
+ /* pmx initialization */
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
/* This fixes addresses of all pmx devices for spear320 */
spear3xx_pmx_init_addr(&pmx_driver, SPEAR320_PAD_MUX_CONFIG_REG);
-
- /* pmx initialization */
ret = pmx_register(&pmx_driver);
if (ret)
pr_err("padmux: registeration failed. err no: %d\n", ret);
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 8213e4b..7e5f17f 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -19,22 +19,22 @@
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
- &pmx_i2c,
- &pmx_ssp,
- &pmx_mii,
- &pmx_uart0,
+ &spear3xx_pmx_i2c,
+ &spear3xx_pmx_ssp,
+ &spear3xx_pmx_mii,
+ &spear3xx_pmx_uart0,
/* spear320 specific devices */
- &pmx_fsmc,
- &pmx_sdhci,
- &pmx_i2s,
- &pmx_uart1,
- &pmx_uart2,
- &pmx_can,
- &pmx_pwm0,
- &pmx_pwm1,
- &pmx_pwm2,
- &pmx_mii1,
+ &spear320_pmx_fsmc,
+ &spear320_pmx_sdhci,
+ &spear320_pmx_i2s,
+ &spear320_pmx_uart1,
+ &spear320_pmx_uart2,
+ &spear320_pmx_can,
+ &spear320_pmx_pwm0,
+ &spear320_pmx_pwm1,
+ &spear320_pmx_pwm2,
+ &spear320_pmx_mii1,
};
static struct amba_device *amba_devs[] __initdata = {
@@ -55,13 +55,9 @@ static void __init spear320_evb_init(void)
{
unsigned int i;
- /* padmux initialization, must be done before spear320_init */
- pmx_driver.mode = &auto_net_mii_mode;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-
/* call spear320 machine init function */
- spear320_init();
+ spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
+ ARRAY_SIZE(pmx_devs));
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 9ae7009..64dac69 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -118,7 +118,7 @@ static struct pmx_dev_mode pmx_firda_modes[] = {
},
};
-struct pmx_dev pmx_firda = {
+struct pmx_dev spear3xx_pmx_firda = {
.name = "firda",
.modes = pmx_firda_modes,
.mode_count = ARRAY_SIZE(pmx_firda_modes),
@@ -140,7 +140,7 @@ static struct pmx_dev_mode pmx_i2c_modes[] = {
},
};
-struct pmx_dev pmx_i2c = {
+struct pmx_dev spear3xx_pmx_i2c = {
.name = "i2c",
.modes = pmx_i2c_modes,
.mode_count = ARRAY_SIZE(pmx_i2c_modes),
@@ -162,7 +162,7 @@ static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
},
};
-struct pmx_dev pmx_ssp_cs = {
+struct pmx_dev spear3xx_pmx_ssp_cs = {
.name = "ssp_chip_selects",
.modes = pmx_ssp_cs_modes,
.mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
@@ -184,7 +184,7 @@ static struct pmx_dev_mode pmx_ssp_modes[] = {
},
};
-struct pmx_dev pmx_ssp = {
+struct pmx_dev spear3xx_pmx_ssp = {
.name = "ssp",
.modes = pmx_ssp_modes,
.mode_count = ARRAY_SIZE(pmx_ssp_modes),
@@ -206,7 +206,7 @@ static struct pmx_dev_mode pmx_mii_modes[] = {
},
};
-struct pmx_dev pmx_mii = {
+struct pmx_dev spear3xx_pmx_mii = {
.name = "mii",
.modes = pmx_mii_modes,
.mode_count = ARRAY_SIZE(pmx_mii_modes),
@@ -228,7 +228,7 @@ static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
},
};
-struct pmx_dev pmx_gpio_pin0 = {
+struct pmx_dev spear3xx_pmx_gpio_pin0 = {
.name = "gpio_pin0",
.modes = pmx_gpio_pin0_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
@@ -250,7 +250,7 @@ static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
},
};
-struct pmx_dev pmx_gpio_pin1 = {
+struct pmx_dev spear3xx_pmx_gpio_pin1 = {
.name = "gpio_pin1",
.modes = pmx_gpio_pin1_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
@@ -272,7 +272,7 @@ static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
},
};
-struct pmx_dev pmx_gpio_pin2 = {
+struct pmx_dev spear3xx_pmx_gpio_pin2 = {
.name = "gpio_pin2",
.modes = pmx_gpio_pin2_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
@@ -294,7 +294,7 @@ static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
},
};
-struct pmx_dev pmx_gpio_pin3 = {
+struct pmx_dev spear3xx_pmx_gpio_pin3 = {
.name = "gpio_pin3",
.modes = pmx_gpio_pin3_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
@@ -316,7 +316,7 @@ static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
},
};
-struct pmx_dev pmx_gpio_pin4 = {
+struct pmx_dev spear3xx_pmx_gpio_pin4 = {
.name = "gpio_pin4",
.modes = pmx_gpio_pin4_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
@@ -338,7 +338,7 @@ static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
},
};
-struct pmx_dev pmx_gpio_pin5 = {
+struct pmx_dev spear3xx_pmx_gpio_pin5 = {
.name = "gpio_pin5",
.modes = pmx_gpio_pin5_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
@@ -360,7 +360,7 @@ static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
},
};
-struct pmx_dev pmx_uart0_modem = {
+struct pmx_dev spear3xx_pmx_uart0_modem = {
.name = "uart0_modem",
.modes = pmx_uart0_modem_modes,
.mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
@@ -382,7 +382,7 @@ static struct pmx_dev_mode pmx_uart0_modes[] = {
},
};
-struct pmx_dev pmx_uart0 = {
+struct pmx_dev spear3xx_pmx_uart0 = {
.name = "uart0",
.modes = pmx_uart0_modes,
.mode_count = ARRAY_SIZE(pmx_uart0_modes),
@@ -404,7 +404,7 @@ static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
},
};
-struct pmx_dev pmx_timer_3_4 = {
+struct pmx_dev spear3xx_pmx_timer_3_4 = {
.name = "timer_3_4",
.modes = pmx_timer_3_4_modes,
.mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
@@ -426,7 +426,7 @@ static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
},
};
-struct pmx_dev pmx_timer_1_2 = {
+struct pmx_dev spear3xx_pmx_timer_1_2 = {
.name = "timer_1_2",
.modes = pmx_timer_1_2_modes,
.mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
@@ -449,7 +449,7 @@ static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_0_1 = {
+struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
.name = "plgpio 0 and 1",
.modes = pmx_plgpio_0_1_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
@@ -471,7 +471,7 @@ static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_2_3 = {
+struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
.name = "plgpio 2 and 3",
.modes = pmx_plgpio_2_3_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
@@ -493,7 +493,7 @@ static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_4_5 = {
+struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
.name = "plgpio 4 and 5",
.modes = pmx_plgpio_4_5_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
@@ -515,7 +515,7 @@ static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_6_9 = {
+struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
.name = "plgpio 6 to 9",
.modes = pmx_plgpio_6_9_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
@@ -537,7 +537,7 @@ static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_10_27 = {
+struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
.name = "plgpio 10 to 27",
.modes = pmx_plgpio_10_27_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
@@ -559,7 +559,7 @@ static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_28 = {
+struct pmx_dev spear3xx_pmx_plgpio_28 = {
.name = "plgpio 28",
.modes = pmx_plgpio_28_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
@@ -581,7 +581,7 @@ static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_29 = {
+struct pmx_dev spear3xx_pmx_plgpio_29 = {
.name = "plgpio 29",
.modes = pmx_plgpio_29_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
@@ -603,7 +603,7 @@ static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_30 = {
+struct pmx_dev spear3xx_pmx_plgpio_30 = {
.name = "plgpio 30",
.modes = pmx_plgpio_30_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
@@ -625,7 +625,7 @@ static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_31 = {
+struct pmx_dev spear3xx_pmx_plgpio_31 = {
.name = "plgpio 31",
.modes = pmx_plgpio_31_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
@@ -647,7 +647,7 @@ static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_32 = {
+struct pmx_dev spear3xx_pmx_plgpio_32 = {
.name = "plgpio 32",
.modes = pmx_plgpio_32_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
@@ -669,7 +669,7 @@ static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_33 = {
+struct pmx_dev spear3xx_pmx_plgpio_33 = {
.name = "plgpio 33",
.modes = pmx_plgpio_33_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
@@ -691,7 +691,7 @@ static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_34_36 = {
+struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
.name = "plgpio 34 to 36",
.modes = pmx_plgpio_34_36_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
@@ -713,7 +713,7 @@ static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_37_42 = {
+struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
.name = "plgpio 37 to 42",
.modes = pmx_plgpio_37_42_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
@@ -735,7 +735,7 @@ static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_43_44_47_48 = {
+struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
.name = "plgpio 43, 44, 47 and 48",
.modes = pmx_plgpio_43_44_47_48_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
@@ -757,7 +757,7 @@ static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
},
};
-struct pmx_dev pmx_plgpio_45_46_49_50 = {
+struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
.name = "plgpio 45, 46, 49 and 50",
.modes = pmx_plgpio_45_46_49_50_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 07/11] ST SPEAr3xx: Appending spear3** with global device structures
From: Viresh Kumar @ 2011-03-01 11:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977709.git.viresh.kumar@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 6 +++---
arch/arm/mach-spear3xx/spear300.c | 2 +-
arch/arm/mach-spear3xx/spear300_evb.c | 6 +++---
arch/arm/mach-spear3xx/spear310_evb.c | 4 ++--
arch/arm/mach-spear3xx/spear320_evb.c | 4 ++--
arch/arm/mach-spear3xx/spear3xx.c | 4 ++--
6 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 9186e5a..5320ab6 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -31,8 +31,8 @@
#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
/* Add spear3xx family device structure declarations here */
-extern struct amba_device gpio_device;
-extern struct amba_device uart_device;
+extern struct amba_device spear3xx_gpio_device;
+extern struct amba_device spear3xx_uart_device;
extern struct sys_timer spear3xx_timer;
/* Add spear3xx family function declarations here */
@@ -99,7 +99,7 @@ extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
/* spear300 declarations */
#ifdef CONFIG_MACH_SPEAR300
/* Add spear300 machine device structure declarations here */
-extern struct amba_device gpio1_device;
+extern struct amba_device spear300_gpio1_device;
/* pad mux modes */
extern struct pmx_mode spear300_nand_mode;
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 2618181..89999bf 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -582,7 +582,7 @@ static struct pl061_platform_data gpio1_plat_data = {
.irq_base = SPEAR300_GPIO1_INT_BASE,
};
-struct amba_device gpio1_device = {
+struct amba_device spear300_gpio1_device = {
.dev = {
.init_name = "gpio1",
.platform_data = &gpio1_plat_data,
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 405ae09..69006f6 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -34,11 +34,11 @@ static struct pmx_dev *pmx_devs[] = {
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
- &gpio_device,
- &uart_device,
+ &spear3xx_gpio_device,
+ &spear3xx_uart_device,
/* spear300 specific devices */
- &gpio1_device,
+ &spear300_gpio1_device,
};
static struct platform_device *plat_devs[] __initdata = {
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 9d4aadb..c8684ce 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -42,8 +42,8 @@ static struct pmx_dev *pmx_devs[] = {
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
- &gpio_device,
- &uart_device,
+ &spear3xx_gpio_device,
+ &spear3xx_uart_device,
/* spear310 specific devices */
};
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 7e5f17f..a12b353 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -39,8 +39,8 @@ static struct pmx_dev *pmx_devs[] = {
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
- &gpio_device,
- &uart_device,
+ &spear3xx_gpio_device,
+ &spear3xx_uart_device,
/* spear320 specific devices */
};
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 64dac69..c32a186 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -28,7 +28,7 @@ static struct pl061_platform_data gpio_plat_data = {
.irq_base = SPEAR3XX_GPIO_INT_BASE,
};
-struct amba_device gpio_device = {
+struct amba_device spear3xx_gpio_device = {
.dev = {
.init_name = "gpio",
.platform_data = &gpio_plat_data,
@@ -42,7 +42,7 @@ struct amba_device gpio_device = {
};
/* uart device registration */
-struct amba_device uart_device = {
+struct amba_device spear3xx_uart_device = {
.dev = {
.init_name = "uart",
},
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 08/11] ST SPEAr3xx: Rework KConfig to allow all boards to be compiled in
From: Viresh Kumar @ 2011-03-01 11:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977709.git.viresh.kumar@st.com>
From: Ryan Mallon <ryan@bluewatersys.com>
Now that all three SPEAr3xx platforms can be built into one kernel,
rework KConfig to allow this. Move everything into one KConfig file
while we are here.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/Kconfig | 30 ++++++++++++++++++++----------
arch/arm/mach-spear3xx/Kconfig300 | 17 -----------------
arch/arm/mach-spear3xx/Kconfig310 | 17 -----------------
arch/arm/mach-spear3xx/Kconfig320 | 17 -----------------
4 files changed, 20 insertions(+), 61 deletions(-)
delete mode 100644 arch/arm/mach-spear3xx/Kconfig300
delete mode 100644 arch/arm/mach-spear3xx/Kconfig310
delete mode 100644 arch/arm/mach-spear3xx/Kconfig320
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 20d1317..2cee6b0 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -4,9 +4,26 @@
if ARCH_SPEAR3XX
-choice
- prompt "SPEAr3XX Family"
- default MACH_SPEAR300
+menu "SPEAr3xx Implementations"
+config BOARD_SPEAR300_EVB
+ bool "SPEAr300 Evaluation Board"
+ select MACH_SPEAR300
+ help
+ Supports ST SPEAr300 Evaluation Board
+
+config BOARD_SPEAR310_EVB
+ bool "SPEAr310 Evaluation Board"
+ select MACH_SPEAR310
+ help
+ Supports ST SPEAr310 Evaluation Board
+
+config BOARD_SPEAR320_EVB
+ bool "SPEAr320 Evaluation Board"
+ select MACH_SPEAR320
+ help
+ Supports ST SPEAr320 Evaluation Board
+
+endmenu
config MACH_SPEAR300
bool "SPEAr300"
@@ -23,11 +40,4 @@ config MACH_SPEAR320
help
Supports ST SPEAr320 Machine
-endchoice
-
-# Adding SPEAr3XX machine specific configuration files
-source "arch/arm/mach-spear3xx/Kconfig300"
-source "arch/arm/mach-spear3xx/Kconfig310"
-source "arch/arm/mach-spear3xx/Kconfig320"
-
endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Kconfig300 b/arch/arm/mach-spear3xx/Kconfig300
deleted file mode 100644
index c519a05..0000000
--- a/arch/arm/mach-spear3xx/Kconfig300
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr300 machine configuration file
-#
-
-if MACH_SPEAR300
-
-choice
- prompt "SPEAr300 Boards"
- default BOARD_SPEAR300_EVB
-
-config BOARD_SPEAR300_EVB
- bool "SPEAr300 Evaluation Board"
- help
- Supports ST SPEAr300 Evaluation Board
-endchoice
-
-endif #MACH_SPEAR300
diff --git a/arch/arm/mach-spear3xx/Kconfig310 b/arch/arm/mach-spear3xx/Kconfig310
deleted file mode 100644
index 60e7442..0000000
--- a/arch/arm/mach-spear3xx/Kconfig310
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr310 machine configuration file
-#
-
-if MACH_SPEAR310
-
-choice
- prompt "SPEAr310 Boards"
- default BOARD_SPEAR310_EVB
-
-config BOARD_SPEAR310_EVB
- bool "SPEAr310 Evaluation Board"
- help
- Supports ST SPEAr310 Evaluation Board
-endchoice
-
-endif #MACH_SPEAR310
diff --git a/arch/arm/mach-spear3xx/Kconfig320 b/arch/arm/mach-spear3xx/Kconfig320
deleted file mode 100644
index 1c1d438..0000000
--- a/arch/arm/mach-spear3xx/Kconfig320
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr320 machine configuration file
-#
-
-if MACH_SPEAR320
-
-choice
- prompt "SPEAr320 Boards"
- default BOARD_SPEAR320_EVB
-
-config BOARD_SPEAR320_EVB
- bool "SPEAr320 Evaluation Board"
- help
- Supports ST SPEAr320 Evaluation Board
-endchoice
-
-endif #MACH_SPEAR320
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 09/11] ST SPEAr3xx: Replace defconfigs with single unified defconfig
From: Viresh Kumar @ 2011-03-01 11:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977709.git.viresh.kumar@st.com>
From: Ryan Mallon <ryan@bluewatersys.com>
We only need one defconfig for SPEAr3xx now since we can build all
three boards into one kernel.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/configs/spear310_defconfig | 52 --------------------
arch/arm/configs/spear320_defconfig | 52 --------------------
.../{spear300_defconfig => spear3xx_defconfig} | 4 +-
3 files changed, 3 insertions(+), 105 deletions(-)
delete mode 100644 arch/arm/configs/spear310_defconfig
delete mode 100644 arch/arm/configs/spear320_defconfig
rename arch/arm/configs/{spear300_defconfig => spear3xx_defconfig} (93%)
diff --git a/arch/arm/configs/spear310_defconfig b/arch/arm/configs/spear310_defconfig
deleted file mode 100644
index 824e444..0000000
--- a/arch/arm/configs/spear310_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PLAT_SPEAR=y
-CONFIG_MACH_SPEAR310=y
-CONFIG_BINFMT_MISC=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_INPUT_FF_MEMLESS=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=8192
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PL061=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear320_defconfig b/arch/arm/configs/spear320_defconfig
deleted file mode 100644
index 842f7f3..0000000
--- a/arch/arm/configs/spear320_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PLAT_SPEAR=y
-CONFIG_MACH_SPEAR320=y
-CONFIG_BINFMT_MISC=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_INPUT_FF_MEMLESS=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=8192
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PL061=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear300_defconfig b/arch/arm/configs/spear3xx_defconfig
similarity index 93%
rename from arch/arm/configs/spear300_defconfig
rename to arch/arm/configs/spear3xx_defconfig
index cf29f3e..fea7e1f 100644
--- a/arch/arm/configs/spear300_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -7,6 +7,9 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PLAT_SPEAR=y
+CONFIG_BOARD_SPEAR300_EVB=y
+CONFIG_BOARD_SPEAR310_EVB=y
+CONFIG_BOARD_SPEAR320_EVB=y
CONFIG_BINFMT_MISC=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_RAM=y
@@ -24,7 +27,6 @@ CONFIG_MAX_RAW_DEVS=8192
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 00/10] Adding SPEAr13xx support
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds support for SPEAr13xx machine family. Currently support
for to machines SPEAr1300 & SPEAr1310 are added.
Note: These patches were earlier sent as part of a larger patchset:
"Updating SPEAr Support"
Now it is divided into smaller patchsets. In order to apply these patches
cleanly following order of patchsets must be maintained.
- SPEAr3xx & SPEAr6xx Fixes
- SPEAr3xx & SPEAr6xx: Single Image solution and padmux updates
- Adding SPEAr13xx support
- Adding devices support for all spear machines
- Clock Framework & CPU Freq Updates
Bhupesh Sharma (1):
ST SPEAr13xx: Adding support for SPEAr1310
Deepak Sikri (1):
ST SPEAr13xx: Adding CPU hotplug support added for SMP platforms
Shiraz Hashim (7):
ST SPEAr13xx: Adding machine specific header files
ST SPEAr13xx: Adding machine specific src files
ST SPEAr13xx: Adding support in SPEAr generic plat/
ST SPEAr13xx: Added compilation support in arch/arm/
ST SPEAr13xx: Adding default config file
ST SPEAr13xx: Adding information in Documentation/ and MAINTAINERS
ST SPEAr13xx: add L2 cache support
Vipin Kumar (1):
ST SPEAr13xx: Add padmux support
Documentation/arm/SPEAr/overview.txt | 34 +-
MAINTAINERS | 6 +
arch/arm/Kconfig | 4 +-
arch/arm/Makefile | 2 +
arch/arm/configs/spear13xx_defconfig | 61 +
arch/arm/mach-spear13xx/Kconfig | 32 +
arch/arm/mach-spear13xx/Makefile | 21 +
arch/arm/mach-spear13xx/Makefile.boot | 3 +
arch/arm/mach-spear13xx/clock.c | 1167 ++++++++++++++++++++
arch/arm/mach-spear13xx/headsmp.S | 42 +
arch/arm/mach-spear13xx/hotplug.c | 121 ++
arch/arm/mach-spear13xx/include/mach/clkdev.h | 19 +
arch/arm/mach-spear13xx/include/mach/debug-macro.S | 14 +
arch/arm/mach-spear13xx/include/mach/entry-macro.S | 22 +
arch/arm/mach-spear13xx/include/mach/generic.h | 261 +++++
arch/arm/mach-spear13xx/include/mach/gpio.h | 19 +
arch/arm/mach-spear13xx/include/mach/hardware.h | 31 +
arch/arm/mach-spear13xx/include/mach/io.h | 19 +
arch/arm/mach-spear13xx/include/mach/irqs.h | 128 +++
arch/arm/mach-spear13xx/include/mach/memory.h | 19 +
arch/arm/mach-spear13xx/include/mach/misc_regs.h | 386 +++++++
arch/arm/mach-spear13xx/include/mach/smp.h | 25 +
arch/arm/mach-spear13xx/include/mach/spear.h | 95 ++
arch/arm/mach-spear13xx/include/mach/spear1300.h | 21 +
arch/arm/mach-spear13xx/include/mach/spear1310.h | 64 ++
arch/arm/mach-spear13xx/include/mach/system.h | 35 +
arch/arm/mach-spear13xx/include/mach/timex.h | 19 +
arch/arm/mach-spear13xx/include/mach/uncompress.h | 19 +
arch/arm/mach-spear13xx/include/mach/vmalloc.h | 18 +
arch/arm/mach-spear13xx/localtimer.c | 25 +
arch/arm/mach-spear13xx/platsmp.c | 162 +++
arch/arm/mach-spear13xx/spear1300.c | 38 +
arch/arm/mach-spear13xx/spear1300_evb.c | 67 ++
arch/arm/mach-spear13xx/spear1310.c | 494 +++++++++
arch/arm/mach-spear13xx/spear1310_evb.c | 86 ++
arch/arm/mach-spear13xx/spear13xx.c | 697 ++++++++++++
arch/arm/mm/Kconfig | 2 +-
arch/arm/plat-spear/Kconfig | 8 +
arch/arm/plat-spear/Makefile | 1 +
39 files changed, 4273 insertions(+), 14 deletions(-)
create mode 100644 arch/arm/configs/spear13xx_defconfig
create mode 100644 arch/arm/mach-spear13xx/Kconfig
create mode 100644 arch/arm/mach-spear13xx/Makefile
create mode 100644 arch/arm/mach-spear13xx/Makefile.boot
create mode 100644 arch/arm/mach-spear13xx/clock.c
create mode 100644 arch/arm/mach-spear13xx/headsmp.S
create mode 100644 arch/arm/mach-spear13xx/hotplug.c
create mode 100644 arch/arm/mach-spear13xx/include/mach/clkdev.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-spear13xx/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-spear13xx/include/mach/generic.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/gpio.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/hardware.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/io.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/irqs.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/memory.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/misc_regs.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/smp.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1300.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1310.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/system.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/timex.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/uncompress.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-spear13xx/localtimer.c
create mode 100644 arch/arm/mach-spear13xx/platsmp.c
create mode 100644 arch/arm/mach-spear13xx/spear1300.c
create mode 100644 arch/arm/mach-spear13xx/spear1300_evb.c
create mode 100644 arch/arm/mach-spear13xx/spear1310.c
create mode 100644 arch/arm/mach-spear13xx/spear1310_evb.c
create mode 100644 arch/arm/mach-spear13xx/spear13xx.c
--
1.7.2.2
^ permalink raw reply
* [PATCH V6 01/10] ST SPEAr13xx: Adding machine specific header files
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977719.git.viresh.kumar@st.com>
From: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/clkdev.h | 19 +
arch/arm/mach-spear13xx/include/mach/debug-macro.S | 14 +
arch/arm/mach-spear13xx/include/mach/entry-macro.S | 22 ++
arch/arm/mach-spear13xx/include/mach/generic.h | 50 +++
arch/arm/mach-spear13xx/include/mach/gpio.h | 19 +
arch/arm/mach-spear13xx/include/mach/hardware.h | 31 ++
arch/arm/mach-spear13xx/include/mach/io.h | 19 +
arch/arm/mach-spear13xx/include/mach/irqs.h | 91 +++++
arch/arm/mach-spear13xx/include/mach/memory.h | 19 +
arch/arm/mach-spear13xx/include/mach/misc_regs.h | 386 ++++++++++++++++++++
arch/arm/mach-spear13xx/include/mach/smp.h | 25 ++
arch/arm/mach-spear13xx/include/mach/spear.h | 94 +++++
arch/arm/mach-spear13xx/include/mach/spear1300.h | 21 +
arch/arm/mach-spear13xx/include/mach/system.h | 35 ++
arch/arm/mach-spear13xx/include/mach/timex.h | 19 +
arch/arm/mach-spear13xx/include/mach/uncompress.h | 19 +
arch/arm/mach-spear13xx/include/mach/vmalloc.h | 18 +
17 files changed, 901 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/include/mach/clkdev.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-spear13xx/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-spear13xx/include/mach/generic.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/gpio.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/hardware.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/io.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/irqs.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/memory.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/misc_regs.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/smp.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1300.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/system.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/timex.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/uncompress.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/vmalloc.h
diff --git a/arch/arm/mach-spear13xx/include/mach/clkdev.h b/arch/arm/mach-spear13xx/include/mach/clkdev.h
new file mode 100644
index 0000000..effdb81
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/clkdev.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/clkdev.h
+ *
+ * Clock Dev framework definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+#include <plat/clkdev.h>
+
+#endif /* __MACH_CLKDEV_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
new file mode 100644
index 0000000..3933edc
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header spear13xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear13xx/include/mach/entry-macro.S b/arch/arm/mach-spear13xx/include/mach/entry-macro.S
new file mode 100644
index 0000000..5257929
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/entry-macro.S
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * Copy of RealView platform implementation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/hardware/entry-macro-gic.S>
+#include <mach/hardware.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
new file mode 100644
index 0000000..95011a2
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/generic.h
+ *
+ * spear13xx machine family generic header file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GENERIC_H
+#define __MACH_GENERIC_H
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+/*
+ * Each GPT has 2 timer channels
+ * Following GPT channels will be used as clock source and clockevent
+ */
+#define SPEAR_GPT0_BASE SPEAR13XX_GPT0_BASE
+#define SPEAR_GPT0_CHAN0_IRQ IRQ_GPT0_TMR0
+#define SPEAR_GPT0_CHAN1_IRQ IRQ_GPT0_TMR1
+
+/* Add spear13xx family device structure declarations here */
+extern struct amba_device spear13xx_uart_device;
+extern struct sys_timer spear13xx_timer;
+
+/* Add spear13xx family function declarations here */
+void __init clk_init(void);
+void __init spear_setup_timer(void);
+void __init spear13xx_map_io(void);
+void __init spear13xx_init_irq(void);
+void __init spear13xx_init(void);
+void spear13xx_secondary_startup(void);
+
+/* spear1300 declarations */
+#ifdef CONFIG_MACH_SPEAR1300
+/* Add spear1300 machine function declarations here */
+void __init spear1300_init(void);
+
+#endif /* CONFIG_MACH_SPEAR1300 */
+
+#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
new file mode 100644
index 0000000..43fa541
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/gpio.h
+ *
+ * GPIO macros for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#include <plat/gpio.h>
+
+#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
new file mode 100644
index 0000000..fd8c2dc
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/hardware.h
@@ -0,0 +1,31 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/hardware.h
+ *
+ * Hardware definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+
+#include <plat/hardware.h>
+#include <mach/spear.h>
+
+/* Vitual to physical translation of statically mapped space */
+/*
+ * if phy_addr is 0x8...,.... and above then map it to 0xF...,....
+ * else map it to 0xE...,....
+ */
+
+#define IO_ADDRESS(x) ((x) | ((((x) >> 31) << 28) | 0xE0000000))
+
+/* typesafe io address */
+#define __io_address(n) __io(IO_ADDRESS(n))
+
+#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/io.h b/arch/arm/mach-spear13xx/include/mach/io.h
new file mode 100644
index 0000000..2fe3503
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/io.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/io.h
+ *
+ * IO definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+
+#include <plat/io.h>
+
+#endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
new file mode 100644
index 0000000..d9fe051
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -0,0 +1,91 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/irqs.h
+ *
+ * IRQ helper macros for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+/* IRQ definitions */
+/*
+ * SGI : ID0 - ID15
+ * PPI : ID16 - ID31
+ * SHPI : ID32 - ID224
+ */
+
+#define IRQ_LOCALTIMER 29
+#define IRQ_LOCALWDOG 30
+
+/* Shared Peripheral Interrupt (SHPI) */
+#define IRQ_SHPI_START 32
+
+#define IRQ_PLAY_I2S2 (IRQ_SHPI_START + 10)
+#define IRQ_REC_I2S2 (IRQ_SHPI_START + 11)
+#define IRQ_ADC (IRQ_SHPI_START + 12)
+#define IRQ_CLCD (IRQ_SHPI_START + 13)
+#define IRQ_DMAC0_FLAG_0 (IRQ_SHPI_START + 14)
+#define IRQ_DMAC0_FLAG_1 (IRQ_SHPI_START + 15)
+#define IRQ_DMAC0_FLAG_2 (IRQ_SHPI_START + 16)
+#define IRQ_DMAC0_FLAG_3 (IRQ_SHPI_START + 17)
+#define IRQ_DMAC0_FLAG_4 (IRQ_SHPI_START + 18)
+#define IRQ_DMAC0_COMBINED (IRQ_SHPI_START + 19)
+#define IRQ_FSMC0 (IRQ_SHPI_START + 20)
+#define IRQ_FSMC1 (IRQ_SHPI_START + 21)
+#define IRQ_FSMC2 (IRQ_SHPI_START + 22)
+#define IRQ_FSMC3 (IRQ_SHPI_START + 23)
+#define IRQ_GPIO0 (IRQ_SHPI_START + 24)
+#define IRQ_GPIO1 (IRQ_SHPI_START + 25)
+#define IRQ_PLAY_I2S1 (IRQ_SHPI_START + 26)
+#define IRQ_JPEG (IRQ_SHPI_START + 27)
+#define IRQ_SDHCI (IRQ_SHPI_START + 28)
+#define IRQ_CF (IRQ_SHPI_START + 29)
+#define IRQ_SMI (IRQ_SHPI_START + 30)
+#define IRQ_SSP (IRQ_SHPI_START + 31)
+#define IRQ_C3 (IRQ_SHPI_START + 32)
+#define IRQ_GMAC_1 (IRQ_SHPI_START + 33)
+#define IRQ_GMAC_2 (IRQ_SHPI_START + 34)
+#define IRQ_UART (IRQ_SHPI_START + 35)
+#define IRQ_RTC (IRQ_SHPI_START + 36)
+#define IRQ_GPT0_TMR0 (IRQ_SHPI_START + 37)
+#define IRQ_GPT0_TMR1 (IRQ_SHPI_START + 38)
+#define IRQ_GPT1_TMR0 (IRQ_SHPI_START + 39)
+#define IRQ_GPT1_TMR1 (IRQ_SHPI_START + 40)
+#define IRQ_I2C (IRQ_SHPI_START + 41)
+#define IRQ_GPT2_TMR0 (IRQ_SHPI_START + 42)
+#define IRQ_GPT2_TMR1 (IRQ_SHPI_START + 43)
+#define IRQ_GPT3_TMR0 (IRQ_SHPI_START + 44)
+#define IRQ_GPT3_TMR1 (IRQ_SHPI_START + 45)
+
+#define IRQ_JPEG_RME (IRQ_SHPI_START + 52)
+#define IRQ_KBD (IRQ_SHPI_START + 52)
+#define IRQ_REC_I2S1 (IRQ_SHPI_START + 53)
+#define IRQ_DMAC1_FLAG_0 (IRQ_SHPI_START + 54)
+#define IRQ_DMAC1_FLAG_1 (IRQ_SHPI_START + 55)
+#define IRQ_DMAC1_FLAG_2 (IRQ_SHPI_START + 56)
+#define IRQ_DMAC1_FLAG_3 (IRQ_SHPI_START + 57)
+#define IRQ_DMAC1_FLAG_4 (IRQ_SHPI_START + 58)
+#define IRQ_DMAC1_COMBINED (IRQ_SHPI_START + 59)
+
+#define IRQ_UDC (IRQ_SHPI_START + 62)
+#define IRQ_UPD (IRQ_SHPI_START + 63)
+#define IRQ_USBH_EHCI0 (IRQ_SHPI_START + 64)
+#define IRQ_USBH_OHCI0 (IRQ_SHPI_START + 65)
+#define IRQ_USBH_EHCI1 (IRQ_SHPI_START + 66)
+#define IRQ_USBH_OHCI1 (IRQ_SHPI_START + 67)
+#define IRQ_PCIE0 (IRQ_SHPI_START + 68)
+#define IRQ_PCIE1 (IRQ_SHPI_START + 69)
+#define IRQ_PCIE2 (IRQ_SHPI_START + 70)
+
+#define IRQ_GIC_END (IRQ_SHPI_START + 128)
+
+#define NR_IRQS IRQ_GIC_END
+
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/memory.h b/arch/arm/mach-spear13xx/include/mach/memory.h
new file mode 100644
index 0000000..200257c
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/memory.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/memory.h
+ *
+ * Memory map for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MEMORY_H
+#define __MACH_MEMORY_H
+
+#include <plat/memory.h>
+
+#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/misc_regs.h b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
new file mode 100644
index 0000000..98faae1
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/misc_regs.h
@@ -0,0 +1,386 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/misc_regs.h
+ *
+ * Miscellaneous registers definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MISC_REGS_H
+#define __MACH_MISC_REGS_H
+
+#include <mach/hardware.h>
+
+#define MISC_BASE IOMEM(VA_SPEAR13XX_MISC_BASE)
+
+/* General Configuration */
+#define SOC_CFG (MISC_BASE + 0x000)
+#define BOOTSTRAP_CFG (MISC_BASE + 0x004)
+
+/* Power Management Registers */
+#define PCM_CFG (MISC_BASE + 0x100)
+#define PCM_WKUP_CFG (MISC_BASE + 0x104)
+#define SWITCH_CTR (MISC_BASE + 0x108)
+#define SYS_CLK_CTRL (MISC_BASE + 0x200)
+#define SYS_SW_RES (MISC_BASE + 0x204)
+
+/* Clock Configuration Registers */
+#define SYS_CLK_PLLTIMER (MISC_BASE + 0x208)
+#define SYS_CLK_OSCITIMER (MISC_BASE + 0x20c)
+
+/* PLL related registers and bit values */
+#define PLL_CFG (MISC_BASE + 0x210)
+ /* PLL_CFG bit values */
+ #define OSC_24M_VAL 0
+ #define OSC_25M_VAL 1
+ #define PLL_CLK_MASK 3
+ #define PLL1_CLK_SHIFT 20
+ #define PLL2_CLK_SHIFT 22
+ #define PLL3_CLK_SHIFT 24
+ #define CLCD_SYNT_PLL1_DIV4_VAL 0
+ #define CLCD_SYNT_PLL2_VAL 1
+ #define CLCD_SYNT_CLK_MASK 1
+ #define CLCD_SYNT_CLK_SHIFT 31
+
+#define PLL1_CTR (MISC_BASE + 0x214)
+#define PLL1_FRQ (MISC_BASE + 0x218)
+#define PLL1_MOD (MISC_BASE + 0x21c)
+#define PLL2_CTR (MISC_BASE + 0x220)
+#define PLL2_FRQ (MISC_BASE + 0x224)
+#define PLL2_MOD (MISC_BASE + 0x228)
+#define PLL3_CTR (MISC_BASE + 0x22c)
+#define PLL3_FRQ (MISC_BASE + 0x230)
+#define PLL3_MOD (MISC_BASE + 0x234)
+#define PLL4_CTR (MISC_BASE + 0x238)
+ /* PLL_CTR register masks */
+ #define PLL_ENABLE 2
+ #define PLL_MODE_SHIFT 4
+ #define PLL_MODE_MASK 3
+ #define PLL_MODE_NORMAL 0
+ #define PLL_MODE_FRACTION 1
+ #define PLL_MODE_DITH_DSB 2
+ #define PLL_MODE_DITH_SSB 3
+
+#define PLL4_FRQ (MISC_BASE + 0x23c)
+ /* PLL FRQ register masks */
+ #define PLL_DIV_N_SHIFT 0
+ #define PLL_DIV_N_MASK 0xFF
+ #define PLL_DIV_P_SHIFT 8
+ #define PLL_DIV_P_MASK 0x7
+ #define PLL_NORM_FDBK_M_SHIFT 24
+ #define PLL_NORM_FDBK_M_MASK 0xFF
+ #define PLL_DITH_FDBK_M_SHIFT 16
+ #define PLL_DITH_FDBK_M_MASK 0xFFFF
+
+#define PLL4_MOD (MISC_BASE + 0x240)
+
+#define PERIP_CLK_CFG (MISC_BASE + 0x244)
+ /* PERIP_CLK_CFG bit values */
+ #define GPT_OSC24_VAL 0
+ #define GPT_APB_VAL 1
+ #define GPT_CLK_MASK 1
+ #define GPT0_CLK_SHIFT 8
+ #define GPT1_CLK_SHIFT 9
+ #define GPT2_CLK_SHIFT 12
+ #define GPT3_CLK_SHIFT 13
+ #define AUX_CLK_PLL5_VAL 0
+ #define AUX_CLK_SYNT_VAL 1
+ #define UART_CLK_MASK 1
+ #define UART_CLK_SHIFT 4
+ #define CLCD_PLL5_VAL 0
+ #define CLCD_SYNT_MASK 1
+ #define CLCD_CLK_MASK 3
+ #define CLCD_CLK_SHIFT 2
+ #define C3_CLK_MASK 1
+ #define C3_CLK_SHIFT 1
+ #define MCTR_CLK_SHIFT 10
+ #define MCTR_CLK_MASK 0x1
+ #define MCTR_CLK_PLL1_VAL 0x0
+ #define MCTR_CLK_PLL4_VAL 0x1
+
+#define GMAC_CLK_CFG (MISC_BASE + 0x248)
+
+ #define GMAC_PHY_PAD_VAL 0
+ #define GMAC_PHY_PLL2_VAL 1
+ #define GMAC_PHY_OSC3_VAL 2
+ #define GMAC_PHY_INPUT_CLK_MASK 3
+ #define GMAC_PHY_INPUT_CLK_SHIFT 1
+ #define GMAC_PHY_SYNT_ENB 3
+ #define GMAC_PHY_CLK_MASK 1
+ #define GMAC_PHY_CLK_SHIFT 3
+ #define GMAC_PHY_SYNT_ENB_VAL 4
+
+#define C3_CLK_SYNT (MISC_BASE + 0x24c)
+#define CLCD_CLK_SYNT (MISC_BASE + 0x250)
+ /* CLCD synth reg masks */
+ #define CLCD_SYNT_ENB 31
+ #define CLCD_SYNT_DIV_FACTOR_MASK 0x1ffff
+ #define CLCD_SYNT_DIV_FACTOR_SHIFT 0
+
+#define UART_CLK_SYNT (MISC_BASE + 0x254)
+#define GMAC_CLK_SYNT (MISC_BASE + 0x258)
+#define SDHCI_CLK_SYNT (MISC_BASE + 0x25c)
+#define CFXD_CLK_SYNT (MISC_BASE + 0x260)
+#define RAS_CLK_SYNT0 (MISC_BASE + 0x264)
+#define RAS_CLK_SYNT1 (MISC_BASE + 0x268)
+#define RAS_CLK_SYNT2 (MISC_BASE + 0x26c)
+#define RAS_CLK_SYNT3 (MISC_BASE + 0x270)
+ /* aux clk synthesizer register masks */
+ #define AUX_SYNT_ENB 31
+ #define AUX_EQ_SEL_SHIFT 30
+ #define AUX_EQ_SEL_MASK 1
+ #define AUX_EQ1_SEL 0
+ #define AUX_EQ2_SEL 1
+ #define AUX_XSCALE_SHIFT 16
+ #define AUX_XSCALE_MASK 0xFFF
+ #define AUX_YSCALE_SHIFT 0
+ #define AUX_YSCALE_MASK 0xFFF
+
+#define PERIP1_CLK_ENB (MISC_BASE + 0x274)
+ /* PERIP1_CLK_ENB register masks */
+ #define BUS_CLK_ENB 0
+ #define SYSROM_CLK_ENB 1
+ #define SYSRAM1_CLK_ENB 2
+ #define SYSRAM0_CLK_ENB 3
+ #define FSMC_CLK_ENB 4
+ #define SMI_CLK_ENB 5
+ #define SDHCI_CLK_ENB 6
+ #define CFXD_CLK_ENB 7
+ #define GMAC_CLK_ENB 8
+ #define UHC0_CLK_ENB 9
+ #define UHC1_CLK_ENB 10
+ #define USBD_CLK_ENB 11
+ #define PCIE0_CLK_ENB 12
+ #define PCIE1_CLK_ENB 13
+ #define PCIE2_CLK_ENB 14
+ #define UART_CLK_ENB 15
+ #define SSP_CLK_ENB 17
+ #define I2C_CLK_ENB 18
+ #define I2S0_CLK_ENB 19
+ #define I2S1_CLK_ENB 20
+ #define GPT0_CLK_ENB 21
+ #define GPT1_CLK_ENB 22
+ #define GPIO0_CLK_ENB 23
+ #define GPIO1_CLK_ENB 24
+ #define DMA0_CLK_ENB 25
+ #define DMA1_CLK_ENB 26
+ #define CLCD_CLK_ENB 27
+ #define JPEG_CLK_ENB 28
+ #define C3_CLK_ENB 29
+ #define ADC_CLK_ENB 30
+ #define RTC_CLK_ENB 31
+
+#define PERIP2_CLK_ENB (MISC_BASE + 0x278)
+ /* PERIP2_CLK_ENB register masks */
+ #define DDR_CTRL_CLK_ENB 0
+ #define DDR_CORE_CLK_ENB 1
+ #define CPU_DBG_CLK_ENB 2
+ #define KBD_CLK_ENB 3
+ #define GPT2_CLK_ENB 4
+ #define GPT3_CLK_ENB 5
+ #define ACP_CLK_ENB 6
+ #define I2S_REFOUT_CLK_ENB 7
+ #define THSENS_CLK_ENB 8
+
+#define PERIP1_SW_RST (MISC_BASE + 0x27c)
+ #define JPEG_SOF_RST 28
+#define PERIP2_SW_RST (MISC_BASE + 0x280)
+#define RAS_CLK_ENB (MISC_BASE + 0x284)
+ /* RAS_CLK_ENB register masks */
+ #define ACLK_CLK_ENB 0
+ #define PCLK_CLK_ENB 1
+ #define OSC1_CLK_ENB 2
+ #define OSC2_CLK_ENB 3
+ #define OSC3_CLK_ENB 4
+ #define C48_CLK_ENB 5
+ #define C30_CLK_ENB 6
+ #define C125_CLK_ENB 7
+ #define PLL2_CLK_ENB 8
+ #define PLL3_CLK_ENB 9
+ #define PCLK0_CLK_ENB 10
+ #define PCLK1_CLK_ENB 11
+ #define PCLK2_CLK_ENB 12
+ #define PCLK3_CLK_ENB 13
+ #define SYN0_CLK_ENB 14
+ #define SYN1_CLK_ENB 15
+ #define SYN2_CLK_ENB 16
+ #define SYN3_CLK_ENB 17
+#define RAS_SW_RST (MISC_BASE + 0x288)
+#define PLL1_SYNT (MISC_BASE + 0x28c)
+#define I2S_CLK_CFG (MISC_BASE + 0x290)
+
+/* Peripheral Configuration Registers */
+#define DMAC_HS_SEL (MISC_BASE + 0x300)
+#define DMAC_SEL (MISC_BASE + 0x304)
+#define DMAC_FLOW_SEL (MISC_BASE + 0x308)
+#define DMAC_DIR_SEL (MISC_BASE + 0x30c)
+#define DMAC_CFG (MISC_BASE + 0x310)
+#define USBPHY_GEN_CFG (MISC_BASE + 0x314)
+#define USBPHY_P1_CFG (MISC_BASE + 0x318)
+#define USBPHY_P2_CFG (MISC_BASE + 0x31c)
+#define USBPHY_P3_CFG (MISC_BASE + 0x320)
+#define PCIE_CFG (MISC_BASE + 0x324)
+ /* PCIE CFG MASks */
+ #define PCIE2_CFG_AUX_CLK (1 << 0)
+ #define PCIE1_CFG_AUX_CLK (1 << 1)
+ #define PCIE0_CFG_AUX_CLK (1 << 2)
+ #define PCIE2_CFG_CORE_CLK (1 << 3)
+ #define PCIE1_CFG_CORE_CLK (1 << 4)
+ #define PCIE0_CFG_CORE_CLK (1 << 5)
+ #define PCIE2_CFG_POWERUP_RESET (1 << 6)
+ #define PCIE1_CFG_POWERUP_RESET (1 << 7)
+ #define PCIE0_CFG_POWERUP_RESET (1 << 8)
+ #define PCIE2_CFG_DEVICE_PRESENT (1 << 9)
+ #define PCIE1_CFG_DEVICE_PRESENT (1 << 10)
+ #define PCIE0_CFG_DEVICE_PRESENT (1 << 11)
+ #define PCIE0_CFG_VAL (PCIE0_CFG_AUX_CLK | PCIE0_CFG_CORE_CLK \
+ | PCIE0_CFG_POWERUP_RESET | PCIE0_CFG_DEVICE_PRESENT)
+ #define PCIE1_CFG_VAL (PCIE1_CFG_AUX_CLK | PCIE1_CFG_CORE_CLK \
+ | PCIE1_CFG_POWERUP_RESET | PCIE1_CFG_DEVICE_PRESENT)
+ #define PCIE2_CFG_VAL (PCIE2_CFG_AUX_CLK | PCIE2_CFG_CORE_CLK \
+ | PCIE2_CFG_POWERUP_RESET | PCIE2_CFG_DEVICE_PRESENT)
+
+#define PCIE_MIPHY_CFG (MISC_BASE + 0x328)
+#define PERIP_CFG (MISC_BASE + 0x32c)
+ #define MCIF_SEL_SHIFT 3
+ #define MCIF_SEL_MASK 0x3
+ #define SD_MMC_ACTIVE 0x1
+ #define CF_MMC_ACTIVE 0x2
+ #define XD_MMC_ACTIVE 0x3
+#define FSMC_CFG (MISC_BASE + 0x330)
+ /* FSMC_CFG register masks */
+ #define FSMC_MEMSEL_MASK 0x3
+ #define FSMC_MEMSEL_SHIFT 0
+ #define FSMC_MEM_NOR 0
+ #define FSMC_MEM_NAND 1
+ #define FSMC_MEM_SRAM 2
+ #define NAND_BANK_MASK 0x3
+ #define NAND_BANK_SHIFT 2
+ #define NAND_DEV_WIDTH16 4
+
+#define MPMC_CTR_STS (MISC_BASE + 0x334)
+
+/* Inter-Processor Communication Registers */
+#define PRC1_LOCK_CTR (MISC_BASE + 0x500)
+#define PRC2_LOCK_CTR (MISC_BASE + 0x504)
+#define PRC1_IRQ_CTR (MISC_BASE + 0x508)
+#define PRC2_IRQ_CTR (MISC_BASE + 0x51C)
+
+/* Pad Configuration Registers */
+#define PAD_PU_CFG_1 (MISC_BASE + 0x600)
+#define PAD_PU_CFG_2 (MISC_BASE + 0x604)
+#define PAD_PU_CFG_3 (MISC_BASE + 0x608)
+#define PAD_PU_CFG_4 (MISC_BASE + 0x60c)
+#define PAD_PU_CFG_5 (MISC_BASE + 0x610)
+#define PAD_PU_CFG_6 (MISC_BASE + 0x614)
+#define PAD_PU_CFG_7 (MISC_BASE + 0x618)
+#define PAD_PU_CFG_8 (MISC_BASE + 0x61c)
+#define PAD_PD_CFG_1 (MISC_BASE + 0x620)
+#define PAD_PD_CFG_2 (MISC_BASE + 0x624)
+#define PAD_PD_CFG_3 (MISC_BASE + 0x628)
+#define PAD_PD_CFG_4 (MISC_BASE + 0x62c)
+#define PAD_PD_CFG_5 (MISC_BASE + 0x630)
+#define PAD_PD_CFG_6 (MISC_BASE + 0x634)
+#define PAD_PD_CFG_7 (MISC_BASE + 0x638)
+#define PAD_PD_CFG_8 (MISC_BASE + 0x63c)
+#define PAD_SLEEP_CFG (MISC_BASE + 0x640)
+#define PAD_HYST_CFG (MISC_BASE + 0x644)
+#define PAD_DRV_CFG (MISC_BASE + 0x648)
+#define PAD_SLEW_CFG (MISC_BASE + 0x64c)
+#define PAD_FUNCTION_EN_1 (MISC_BASE + 0x650)
+#define PAD_FUNCTION_EN_2 (MISC_BASE + 0x654)
+#define PAD_FUNCTION_EN_3 (MISC_BASE + 0x658)
+#define DDR_PAD_CFG (MISC_BASE + 0x65c)
+#define THSENS_CFG (MISC_BASE + 0x6c4)
+
+/* Compensation Configuration Registers */
+#define COMP_1V8_2V5_3V3__1_CFG (MISC_BASE + 0x700)
+#define COMP_1V8_2V5_3V3__2_CFG (MISC_BASE + 0x704)
+#define COMP_3V3_1_CFG (MISC_BASE + 0x708)
+#define COMP_3V3_2_CFG (MISC_BASE + 0x70c)
+#define COMP_DDR_CFG (MISC_BASE + 0x710)
+
+/* OTP Programming Registers */
+#define OTP_PROG_CTR (MISC_BASE + 0x800)
+#define OTP_WDATA1_1 (MISC_BASE + 0x804)
+#define OTP_WDATA1_2 (MISC_BASE + 0x808)
+#define OTP_WDATA1_3 (MISC_BASE + 0x80c)
+#define OTP_WDATA1_4 (MISC_BASE + 0x810)
+#define OTP_WDATA1_5 (MISC_BASE + 0x814)
+#define OTP_WDATA1_6 (MISC_BASE + 0x818)
+#define OTP_WDATA1_7 (MISC_BASE + 0x81c)
+#define OTP_WDATA1_8 (MISC_BASE + 0x820)
+#define OTP_WDATA2_1 (MISC_BASE + 0x824)
+#define OTP_WDATA2_2 (MISC_BASE + 0x828)
+#define OTP_WDATA2_3 (MISC_BASE + 0x82c)
+#define OTP_WDATA2_4 (MISC_BASE + 0x830)
+#define OTP_WDATA2_5 (MISC_BASE + 0x834)
+#define OTP_WDATA2_6 (MISC_BASE + 0x838)
+#define OTP_WDATA2_7 (MISC_BASE + 0x83c)
+#define OTP_WDATA2_8 (MISC_BASE + 0x840)
+#define OTP_MASK_1 (MISC_BASE + 0x844)
+#define OTP_MASK_2 (MISC_BASE + 0x848)
+#define OTP_MASK_3 (MISC_BASE + 0x84c)
+#define OTP_MASK_4 (MISC_BASE + 0x850)
+#define OTP_MASK_5 (MISC_BASE + 0x854)
+#define OTP_MASK_6 (MISC_BASE + 0x858)
+#define OTP_MASK_7 (MISC_BASE + 0x85c)
+#define OTP_MASK_8 (MISC_BASE + 0x860)
+#define OTP_RDATA1_1 (MISC_BASE + 0x864)
+#define OTP_RDATA1_2 (MISC_BASE + 0x868)
+#define OTP_RDATA1_3 (MISC_BASE + 0x86c)
+#define OTP_RDATA1_4 (MISC_BASE + 0x870)
+#define OTP_RDATA1_5 (MISC_BASE + 0x874)
+#define OTP_RDATA1_6 (MISC_BASE + 0x878)
+#define OTP_RDATA1_7 (MISC_BASE + 0x87c)
+#define OTP_RDATA1_8 (MISC_BASE + 0x880)
+#define OTP_RDATA2_1 (MISC_BASE + 0x884)
+#define OTP_RDATA2_2 (MISC_BASE + 0x888)
+#define OTP_RDATA2_3 (MISC_BASE + 0x88c)
+#define OTP_RDATA2_4 (MISC_BASE + 0x890)
+#define OTP_RDATA2_5 (MISC_BASE + 0x894)
+#define OTP_RDATA2_6 (MISC_BASE + 0x898)
+#define OTP_RDATA2_7 (MISC_BASE + 0x89c)
+#define OTP_RDATA2_8 (MISC_BASE + 0x8a0)
+#define OTP_RDATAM_1 (MISC_BASE + 0x8a4)
+#define OTP_RDATAM_2 (MISC_BASE + 0x8a8)
+#define OTP_RDATAM_3 (MISC_BASE + 0x8ac)
+#define OTP_RDATAM_4 (MISC_BASE + 0x8b0)
+#define OTP_RDATAM_5 (MISC_BASE + 0x8b4)
+#define OTP_RDATAM_6 (MISC_BASE + 0x8b8)
+#define OTP_RDATAM_7 (MISC_BASE + 0x8bc)
+#define OTP_RDATAM_8 (MISC_BASE + 0x8c0)
+
+/* A9SM Registers */
+#define A9SM_CLUSTERID (MISC_BASE + 0x900)
+#define A9SM_STATUS (MISC_BASE + 0x904)
+#define A9SM_DEBUG (MISC_BASE + 0x908)
+#define A9SM_FILTER (MISC_BASE + 0x90c)
+#define A9SM_PARITY_CFG (MISC_BASE + 0x910)
+#define A9SM_PARITY_ERR (MISC_BASE + 0x914)
+
+/* SOC ID Registers */
+#define DIE_ID_1 (MISC_BASE + 0xa00)
+#define DIE_ID_2 (MISC_BASE + 0xa04)
+#define DIE_ID_3 (MISC_BASE + 0xa08)
+#define DIE_ID_4 (MISC_BASE + 0xa0c)
+#define DIE_ID_VALID (MISC_BASE + 0xa10)
+
+/* SOC TEST & DEBUG Registers */
+#define MIPHY_TEST (MISC_BASE + 0x1000)
+#define PCIE_MSTR_P0 (MISC_BASE + 0x1004)
+#define PCIE_AWMISC_P0 (MISC_BASE + 0x1008)
+#define PCIE_ARMISC_P0 (MISC_BASE + 0x100c)
+#define PCIE_MSTR_P1 (MISC_BASE + 0x1010)
+#define PCIE_AWMISC_P1 (MISC_BASE + 0x1014)
+#define PCIE_ARMISC_P1 (MISC_BASE + 0x1018)
+#define PCIE_MSTR_P2 (MISC_BASE + 0x101c)
+#define PCIE_AWMISC_P2 (MISC_BASE + 0x1020)
+#define PCIE_ARMISC_P2 (MISC_BASE + 0x1024)
+
+#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/smp.h b/arch/arm/mach-spear13xx/include/mach/smp.h
new file mode 100644
index 0000000..c1c4580
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/smp.h
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/smp.h
+ *
+ * Few SMP related definitions for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SMP_H
+#define __MACH_SMP_H
+
+#include <asm/hardware/gic.h>
+
+/* We use IRQ1 as the IPI */
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
+{
+ gic_raise_softirq(mask, ipi);
+}
+
+#endif
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
new file mode 100644
index 0000000..1a1af72
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -0,0 +1,94 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear.h
+ *
+ * spear13xx Machine family specific definition
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SPEAR13XX_H
+#define __MACH_SPEAR13XX_H
+
+#include <asm/memory.h>
+#include <mach/spear1300.h>
+
+#define SPEAR13XX_L2CC_BASE UL(0xED000000)
+
+/* ARM9SMP peripheral base address */
+#define SPEAR13XX_A9SM_PERIP_BASE UL(0xEC800000)
+#define VA_SPEAR13XX_A9SM_PERIP_BASE IO_ADDRESS(SPEAR13XX_A9SM_PERIP_BASE)
+/* A9SM peripheral offsets */
+#define SPEAR13XX_SCU_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x00)
+#define SPEAR13XX_GIC_CPU_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x100)
+#define SPEAR13XX_GLOBAL_TMR_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x200)
+#define SPEAR13XX_LOCAL_TMR_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x600)
+#define SPEAR13XX_WDT_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x620)
+#define SPEAR13XX_GIC_DIST_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x1000)
+
+#define SPEAR13XX_UART_BASE UL(0xE0000000)
+#define VA_SPEAR13XX_UART_BASE IO_ADDRESS(SPEAR13XX_UART_BASE)
+
+#define SPEAR13XX_ADC_BASE UL(0xE0080000)
+#define SPEAR13XX_SSP_BASE UL(0xE0100000)
+#define SPEAR13XX_I2S0_BASE UL(0xE0180000)
+#define SPEAR13XX_I2S1_BASE UL(0xE0200000)
+#define SPEAR13XX_I2C_BASE UL(0xE0280000)
+#define SPEAR13XX_KBD_BASE UL(0xE0300000)
+#define SPEAR13XX_GPT0_BASE UL(0xE0380000)
+#define SPEAR13XX_GPT1_BASE UL(0xE0400000)
+#define SPEAR13XX_GPT2_BASE UL(0xE0480000)
+#define SPEAR13XX_GPT3_BASE UL(0xE0500000)
+#define SPEAR13XX_RTC_BASE UL(0xE0580000)
+#define SPEAR13XX_GPIO0_BASE UL(0xE0600000)
+#define SPEAR13XX_GPIO1_BASE UL(0xE0680000)
+#define SPEAR13XX_MISC_BASE UL(0xE0700000)
+#define VA_SPEAR13XX_MISC_BASE IO_ADDRESS(SPEAR13XX_MISC_BASE)
+
+#define SPEAR13XX_SYSRAM0_BASE UL(0xB3800000)
+#define SPEAR13XX_SYSRAM0_SIZE 0x00800000
+
+/*
+ * The system location which is polled by secondary cpus to find the
+ * jump address
+ */
+#define SPEAR13XX_SYS_LOCATION (SPEAR13XX_SYSRAM0_BASE + 0x600)
+
+#define SPEAR13XX_SYSRAM1_BASE UL(0xE0800000)
+#define SPEAR13XX_SYSRAM1_SIZE 0x00800000
+#define SPEAR13XX_CLCD_BASE UL(0xE1000000)
+#define SPEAR13XX_C3_BASE UL(0xE1800000)
+#define SPEAR13XX_GETH_BASE UL(0xE2000000)
+#define SPEAR13XX_UPD_BASE UL(0xE2800000)
+#define SPEAR13XX_UDC_BASE UL(0xE3800000)
+#define SPEAR13XX_UHC0_OHCI_BASE UL(0xE4000000)
+#define SPEAR13XX_UHC0_EHCI_BASE UL(0xE4800000)
+#define SPEAR13XX_UHC1_OHCI_BASE UL(0xE5000000)
+#define SPEAR13XX_UHC1_EHCI_BASE UL(0xE5800000)
+#define SPEAR13XX_SMI_MEM_BASE UL(0xE6000000)
+#define SPEAR13XX_SMI_CTRL_BASE UL(0xEA000000)
+#define SPEAR13XX_DMAC0_BASE UL(0xEA800000)
+#define SPEAR13XX_DMAC1_BASE UL(0xEB000000)
+#define SPEAR13XX_MII_PHY_BASE UL(0xEB800000)
+#define SPEAR13XX_MPMC_BASE UL(0xEC000000)
+#define SPEAR13XX_PCIE0_BASE UL(0x80000000)
+#define SPEAR13XX_PCIE1_BASE UL(0x90000000)
+#define SPEAR13XX_PCIE2_BASE UL(0xC0000000)
+#define SPEAR13XX_PCIE0_APP_BASE UL(0xB1000000)
+#define SPEAR13XX_PCIE1_APP_BASE UL(0xB1800000)
+#define SPEAR13XX_PCIE2_APP_BASE UL(0xB4000000)
+#define SPEAR13XX_FSMC_MEM_BASE UL(0xA0000000)
+#define SPEAR13XX_FSMC_BASE UL(0xB0000000)
+#define SPEAR13XX_JPEG_BASE UL(0xB2000000)
+#define SPEAR13XX_MCIF_CF_BASE UL(0xB2800000)
+#define SPEAR13XX_MCIF_SDHCI_BASE UL(0xB3000000)
+
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE SPEAR13XX_UART_BASE
+#define VA_SPEAR_DBG_UART_BASE VA_SPEAR13XX_UART_BASE
+
+#endif /* __MACH_SPEAR13XX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1300.h b/arch/arm/mach-spear13xx/include/mach/spear1300.h
new file mode 100644
index 0000000..b3ba267
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1300.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear1300.h
+ *
+ * SPEAr1300 Machine specific definition
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef CONFIG_MACH_SPEAR1300
+
+#ifndef __MACH_SPEAR1300_H
+#define __MACH_SPEAR1300_H
+
+#endif /* __MACH_SPEAR1300_H */
+
+#endif /* CONFIG_MACH_SPEAR1300 */
diff --git a/arch/arm/mach-spear13xx/include/mach/system.h b/arch/arm/mach-spear13xx/include/mach/system.h
new file mode 100644
index 0000000..a9b159d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/system.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/system.h
+ *
+ * spear13xx Machine family specific architecture functions
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SYSTEM_H
+#define __MACH_SYSTEM_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/misc_regs.h>
+
+static inline void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks
+ */
+ cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+ writel(0x01, SYS_SW_RES);
+}
+
+#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h
new file mode 100644
index 0000000..0a81490
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/timex.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/timex.h
+ *
+ * spear13xx machine family specific timex definitions
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#define CLOCK_TICK_RATE 24000000
+
+#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h
new file mode 100644
index 0000000..3c27f25
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/uncompress.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#include <plat/uncompress.h>
+
+#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/vmalloc.h b/arch/arm/mach-spear13xx/include/mach/vmalloc.h
new file mode 100644
index 0000000..0f243af
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/vmalloc.h
@@ -0,0 +1,18 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/vmalloc.h
+ *
+ * Defining Vmalloc area for spear13xx machine family
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_VMALLOC_H
+#define __MACH_VMALLOC_H
+
+#define VMALLOC_END 0xEC800000UL
+
+#endif /* __MACH_VMALLOC_H */
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 02/10] ST SPEAr13xx: Adding machine specific src files
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977719.git.viresh.kumar@st.com>
From: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/Kconfig | 21 +
arch/arm/mach-spear13xx/Makefile | 14 +
arch/arm/mach-spear13xx/Makefile.boot | 3 +
arch/arm/mach-spear13xx/clock.c | 1013 ++++++++++++++++++++++++
arch/arm/mach-spear13xx/headsmp.S | 42 +
arch/arm/mach-spear13xx/include/mach/generic.h | 2 +-
arch/arm/mach-spear13xx/localtimer.c | 25 +
arch/arm/mach-spear13xx/platsmp.c | 162 ++++
arch/arm/mach-spear13xx/spear1300.c | 23 +
arch/arm/mach-spear13xx/spear1300_evb.c | 48 ++
arch/arm/mach-spear13xx/spear13xx.c | 121 +++
11 files changed, 1473 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/Kconfig
create mode 100644 arch/arm/mach-spear13xx/Makefile
create mode 100644 arch/arm/mach-spear13xx/Makefile.boot
create mode 100644 arch/arm/mach-spear13xx/clock.c
create mode 100644 arch/arm/mach-spear13xx/headsmp.S
create mode 100644 arch/arm/mach-spear13xx/localtimer.c
create mode 100644 arch/arm/mach-spear13xx/platsmp.c
create mode 100644 arch/arm/mach-spear13xx/spear1300.c
create mode 100644 arch/arm/mach-spear13xx/spear1300_evb.c
create mode 100644 arch/arm/mach-spear13xx/spear13xx.c
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
new file mode 100644
index 0000000..3ea463d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Kconfig
@@ -0,0 +1,21 @@
+#
+# SPEAr13XX Machine configuration file
+#
+
+if ARCH_SPEAR13XX
+
+menu "SPEAr13xx Implementations"
+config BOARD_SPEAR1300_EVB
+ bool "SPEAr1300 Evaluation Board"
+ select MACH_SPEAR1300
+ help
+ Supports ST SPEAr1300 Evaluation Board
+
+endmenu
+
+config MACH_SPEAR1300
+ bool "SPEAr1300"
+ help
+ Supports ST SPEAr1300 Machine
+
+endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
new file mode 100644
index 0000000..cb5ae9e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile for SPEAr13XX machine series
+#
+
+# common files
+obj-y += spear13xx.o clock.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
+
+# spear1300 specific files
+obj-$(CONFIG_MACH_SPEAR1300) += spear1300.o
+
+# spear1300 boards files
+obj-$(CONFIG_BOARD_SPEAR1300_EVB) += spear1300_evb.o
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot
new file mode 100644
index 0000000..7a1f3c0
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-spear13xx/clock.c b/arch/arm/mach-spear13xx/clock.c
new file mode 100644
index 0000000..58d3ec0
--- /dev/null
+++ b/arch/arm/mach-spear13xx/clock.c
@@ -0,0 +1,1013 @@
+/*
+ * arch/arm/mach-spear13xx/clock.c
+ *
+ * SPEAr13xx machines clock framework source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * shiraz hashim<shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <asm/mach-types.h>
+#include <plat/clock.h>
+#include <mach/hardware.h>
+#include <mach/misc_regs.h>
+
+/* root clks */
+/* 24 MHz oscillator clock */
+static struct clk osc1_24m_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 24000000,
+};
+
+/* 32 KHz oscillator clock */
+static struct clk osc2_32k_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 32000,
+};
+
+/* 25 MHz MIPHY oscillator clock */
+static struct clk osc3_25m_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 25000000,
+};
+
+/* clock derived from 32 KHz osc clk */
+/* rtc clock */
+static struct clk rtc_clk = {
+ .pclk = &osc2_32k_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = RTC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from osc1 or osc3 */
+/* pll[1-3] parents */
+static struct pclk_info pll_pclk_info[] = {
+ {
+ .pclk = &osc1_24m_clk,
+ .pclk_val = OSC_24M_VAL,
+ }, {
+ .pclk = &osc3_25m_clk,
+ .pclk_val = OSC_25M_VAL,
+ },
+};
+
+/* pll[1-3] parent select structure */
+static struct pclk_sel pll_pclk_sel = {
+ .pclk_info = pll_pclk_info,
+ .pclk_count = ARRAY_SIZE(pll_pclk_info),
+ .pclk_sel_reg = PLL_CFG,
+ .pclk_sel_mask = PLL_CLK_MASK,
+};
+
+/* pll masks structure */
+static struct pll_clk_masks pll_masks = {
+ .mode_mask = PLL_MODE_MASK,
+ .mode_shift = PLL_MODE_SHIFT,
+ .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
+ .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
+ .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
+ .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
+ .div_p_mask = PLL_DIV_P_MASK,
+ .div_p_shift = PLL_DIV_P_SHIFT,
+ .div_n_mask = PLL_DIV_N_MASK,
+ .div_n_shift = PLL_DIV_N_SHIFT,
+};
+/* pll1 configuration structure */
+static struct pll_clk_config pll1_config = {
+ .mode_reg = PLL1_CTR,
+ .cfg_reg = PLL1_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll rate configuration table, in ascending order of rates */
+struct pll_rate_tbl pll_rtbl[] = {
+ /* PCLK 24MHz */
+ {.mode = 0, .m = 0x7D, .n = 0x03, .p = 0x2}, /* 500 MHz */
+ {.mode = 0, .m = 0xA6, .n = 0x03, .p = 0x2}, /* 664 MHz */
+ {.mode = 0, .m = 0xC8, .n = 0x03, .p = 0x2}, /* 800 MHz */
+ {.mode = 0, .m = 0xFA, .n = 0x06, .p = 0x1}, /* 1000 MHz */
+};
+
+/* pll1 clock */
+static struct clk pll1_clk = {
+ .flags = ENABLED_ON_INIT,
+ .pclk_sel = &pll_pclk_sel,
+ .pclk_sel_shift = PLL1_CLK_SHIFT,
+ .en_reg = PLL1_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
+ .private_data = &pll1_config,
+};
+
+/* pll1div2 clock */
+static struct clk pll1div2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 2,
+ .recalc = &follow_parent,
+};
+
+/* pll1div4 clock */
+static struct clk pll1div4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 4,
+ .recalc = &follow_parent,
+};
+
+/* pll2 configuration structure */
+static struct pll_clk_config pll2_config = {
+ .mode_reg = PLL2_CTR,
+ .cfg_reg = PLL2_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll2 clock */
+static struct clk pll2_clk = {
+ .pclk_sel = &pll_pclk_sel,
+ .pclk_sel_shift = PLL2_CLK_SHIFT,
+ .en_reg = PLL2_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
+ .private_data = &pll2_config,
+};
+
+/* pll3 configuration structure */
+static struct pll_clk_config pll3_config = {
+ .mode_reg = PLL3_CTR,
+ .cfg_reg = PLL3_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll3 clock */
+static struct clk pll3_clk = {
+ .pclk_sel = &pll_pclk_sel,
+ .pclk_sel_shift = PLL3_CLK_SHIFT,
+ .en_reg = PLL3_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 3},
+ .private_data = &pll3_config,
+};
+
+/* pll4 (DDR) configuration structure */
+static struct pll_clk_config pll4_config = {
+ .mode_reg = PLL4_CTR,
+ .cfg_reg = PLL4_FRQ,
+ .masks = &pll_masks,
+};
+
+/* pll4 rate configuration table, in ascending order of rates */
+struct pll_rate_tbl pll4_rtbl[] = {
+ {.mode = 0, .m = 0x7D, .n = 0x03, .p = 0x2}, /* 500 MHz */
+ {.mode = 0, .m = 0xA6, .n = 0x03, .p = 0x2}, /* 664 MHz */
+ {.mode = 0, .m = 0xC8, .n = 0x03, .p = 0x2}, /* 800 MHz */
+ {.mode = 0, .m = 0xFA, .n = 0x06, .p = 0x1}, /* 1000 MHz */
+};
+
+/* pll4 (DDR) clock */
+static struct clk pll4_clk = {
+ .flags = ENABLED_ON_INIT,
+ .pclk = &osc1_24m_clk,
+ .en_reg = PLL4_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .calc_rate = &pll_calc_rate,
+ .recalc = &pll_clk_recalc,
+ .set_rate = &pll_clk_set_rate,
+ .rate_config = {pll4_rtbl, ARRAY_SIZE(pll4_rtbl), 3},
+ .private_data = &pll4_config,
+};
+
+/* pll5 USB 48 MHz clock */
+static struct clk pll5_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &osc1_24m_clk,
+ .rate = 48000000,
+};
+
+/* pll6 (MIPHY) clock */
+static struct clk pll6_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &osc3_25m_clk,
+ .rate = 25000000,
+};
+
+/* clocks derived from pll1 clk */
+/* cpu clock */
+static struct clk cpu_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 2,
+ .recalc = &follow_parent,
+};
+
+/* ahb clock */
+static struct clk ahb_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 6,
+ .recalc = &follow_parent,
+};
+
+/* apb clock */
+static struct clk apb_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .div_factor = 12,
+ .recalc = &follow_parent,
+};
+
+/* clocks derived from osc1, ahb or apb */
+/* gpt[0-3] parents */
+static struct pclk_info gpt_pclk_info[] = {
+ {
+ .pclk = &osc1_24m_clk,
+ .pclk_val = GPT_OSC24_VAL,
+ }, {
+ .pclk = &apb_clk,
+ .pclk_val = GPT_APB_VAL,
+ },
+};
+
+/* gpt[0-3] parent select structure */
+static struct pclk_sel gpt_pclk_sel = {
+ .pclk_info = gpt_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = GPT_CLK_MASK,
+};
+
+/* gpt0 timer clock */
+static struct clk gpt0_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPT0_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT0_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gpt1 timer clock */
+static struct clk gpt1_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPT1_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT1_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gpt2 timer clock */
+static struct clk gpt2_clk = {
+ .en_reg = PERIP2_CLK_ENB,
+ .en_reg_bit = GPT2_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT2_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gpt3 timer clock */
+static struct clk gpt3_clk = {
+ .en_reg = PERIP2_CLK_ENB,
+ .en_reg_bit = GPT3_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT3_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* watch dog timer clock */
+static struct clk wdt_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &cpu_clk,
+ .div_factor = 2,
+ .recalc = &follow_parent,
+};
+
+/* auxiliary synthesizers masks */
+static struct aux_clk_masks aux_masks = {
+ .eq_sel_mask = AUX_EQ_SEL_MASK,
+ .eq_sel_shift = AUX_EQ_SEL_SHIFT,
+ .eq1_mask = AUX_EQ1_SEL,
+ .eq2_mask = AUX_EQ2_SEL,
+ .xscale_sel_mask = AUX_XSCALE_MASK,
+ .xscale_sel_shift = AUX_XSCALE_SHIFT,
+ .yscale_sel_mask = AUX_YSCALE_MASK,
+ .yscale_sel_shift = AUX_YSCALE_SHIFT,
+};
+
+/* clocks derived multiple parents (pll1, pll5, synthesizers or others) */
+/* uart configurations */
+static struct aux_clk_config uart_synth_config = {
+ .synth_reg = UART_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* aux rate configuration table, in ascending order of rates */
+struct aux_rate_tbl aux_rtbl[] = {
+ /* For PLL1div2 = 500 MHz */
+ {.xscale = 2, .yscale = 21, .eq = 1}, /* 48 MHz */
+ {.xscale = 1, .yscale = 6, .eq = 1}, /* 83 MHz */
+ {.xscale = 1, .yscale = 4, .eq = 1}, /* 125 MHz */
+ {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
+ {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
+};
+
+/* uart synth clock */
+static struct clk uart_synth_clk = {
+ .en_reg = UART_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
+ .private_data = &uart_synth_config,
+};
+
+/* uart parents */
+static struct pclk_info uart_pclk_info[] = {
+ {
+ .pclk = &pll5_clk,
+ .pclk_val = AUX_CLK_PLL5_VAL,
+ }, {
+ .pclk = &uart_synth_clk,
+ .pclk_val = AUX_CLK_SYNT_VAL,
+ },
+};
+
+/* uart parent select structure */
+static struct pclk_sel uart_pclk_sel = {
+ .pclk_info = uart_pclk_info,
+ .pclk_count = ARRAY_SIZE(uart_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = UART_CLK_MASK,
+};
+
+/* uart clock */
+static struct clk uart_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UART_CLK_ENB,
+ .pclk_sel = &uart_pclk_sel,
+ .pclk_sel_shift = UART_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* sdhci configurations */
+static struct aux_clk_config sdhci_synth_config = {
+ .synth_reg = SDHCI_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* sdhci synth clock */
+static struct clk sdhci_synth_clk = {
+ .en_reg = SDHCI_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 0},
+ .private_data = &sdhci_synth_config,
+};
+
+/* sdhci clock */
+static struct clk sdhci_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SDHCI_CLK_ENB,
+ .pclk = &sdhci_synth_clk,
+ .recalc = &follow_parent,
+};
+
+/* cfxd configurations */
+static struct aux_clk_config cfxd_synth_config = {
+ .synth_reg = CFXD_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* cfxd synth clock */
+static struct clk cfxd_synth_clk = {
+ .en_reg = CFXD_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 0},
+ .private_data = &cfxd_synth_config,
+};
+
+/* cfxd clock */
+static struct clk cfxd_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = CFXD_CLK_ENB,
+ .pclk = &cfxd_synth_clk,
+ .recalc = &follow_parent,
+};
+
+/* C3 clk configurations */
+static struct aux_clk_config c3_synth_config = {
+ .synth_reg = C3_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* c3 synth clock */
+static struct clk c3_synth_clk = {
+ .en_reg = C3_CLK_SYNT,
+ .en_reg_bit = AUX_SYNT_ENB,
+ .pclk = &pll1div2_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
+ .private_data = &c3_synth_config,
+};
+
+/* c3 parents */
+static struct pclk_info c3_pclk_info[] = {
+ {
+ .pclk = &pll5_clk,
+ .pclk_val = AUX_CLK_PLL5_VAL,
+ }, {
+ .pclk = &c3_synth_clk,
+ .pclk_val = AUX_CLK_SYNT_VAL,
+ },
+};
+
+/* c3 parent select structure */
+static struct pclk_sel c3_pclk_sel = {
+ .pclk_info = c3_pclk_info,
+ .pclk_count = ARRAY_SIZE(c3_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = C3_CLK_MASK,
+};
+
+/* c3 clock */
+static struct clk c3_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = C3_CLK_ENB,
+ .pclk_sel = &c3_pclk_sel,
+ .pclk_sel_shift = C3_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gmac phy clk configurations */
+static struct aux_clk_config gmac_phy_synth_config = {
+ .synth_reg = GMAC_CLK_SYNT,
+ .masks = &aux_masks,
+};
+
+/* gmii external pad clock for phy operation */
+static struct clk gmii_txclk125_pad = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 125000000,
+};
+
+/* gmac phy set of input clks*/
+static struct pclk_info gmac_phy_input_pclk_info[] = {
+ {
+ .pclk = &gmii_txclk125_pad,
+ .pclk_val = GMAC_PHY_PAD_VAL,
+ }, {
+ .pclk = &pll2_clk,
+ .pclk_val = GMAC_PHY_PLL2_VAL,
+ }, {
+ .pclk = &osc3_25m_clk,
+ .pclk_val = GMAC_PHY_OSC3_VAL,
+ },
+};
+
+static struct pclk_sel gmac_phy_input_pclk_sel = {
+ .pclk_info = gmac_phy_input_pclk_info,
+ .pclk_count = ARRAY_SIZE(gmac_phy_input_pclk_info),
+ .pclk_sel_reg = GMAC_CLK_CFG,
+ .pclk_sel_mask = GMAC_PHY_INPUT_CLK_MASK,
+};
+
+static struct clk gmac_phy_input_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gmac_phy_input_pclk_sel,
+ .pclk_sel_shift = GMAC_PHY_INPUT_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* gmac rate configuration table, in ascending order of rates */
+struct aux_rate_tbl gmac_rtbl[] = {
+ /* For gmac phy input clk */
+ {.xscale = 1, .yscale = 6, .eq = 1}, /* divided by 6 */
+ {.xscale = 1, .yscale = 4, .eq = 1}, /* divided by 4 */
+ {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
+ {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
+};
+
+static struct clk gmac_phy_synth_clk = {
+ .en_reg = GMAC_CLK_CFG,
+ .en_reg_bit = GMAC_PHY_SYNT_ENB,
+ .pclk = &gmac_phy_input_clk,
+ .calc_rate = &aux_calc_rate,
+ .recalc = &aux_clk_recalc,
+ .set_rate = &aux_clk_set_rate,
+ .rate_config = {gmac_rtbl, ARRAY_SIZE(gmac_rtbl), 0},
+ .private_data = &gmac_phy_synth_config,
+};
+
+/* gmac phy parents */
+static struct pclk_info gmac_phy_pclk_info[] = {
+ {
+ .pclk = &gmac_phy_input_clk,
+ .pclk_val = 0,
+ }, {
+ .pclk = &gmac_phy_synth_clk,
+ .pclk_val = 1,
+ }
+};
+
+/* gmac phy parent select structure */
+static struct pclk_sel gmac_phy_pclk_sel = {
+ .pclk_info = gmac_phy_pclk_info,
+ .pclk_count = ARRAY_SIZE(gmac_phy_pclk_info),
+ .pclk_sel_reg = GMAC_CLK_CFG,
+ .pclk_sel_mask = GMAC_PHY_CLK_MASK,
+};
+
+/* gmac phy clock */
+static struct clk gmac_phy0_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gmac_phy_pclk_sel,
+ .pclk_sel_shift = GMAC_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* clcd synthesizers masks */
+static struct clcd_synth_masks clcd_masks = {
+ .div_factor_mask = CLCD_SYNT_DIV_FACTOR_MASK,
+ .div_factor_shift = CLCD_SYNT_DIV_FACTOR_SHIFT,
+};
+
+static struct clcd_clk_config clcd_synth_config = {
+ .synth_reg = CLCD_CLK_SYNT,
+ .masks = &clcd_masks,
+};
+
+/* clcd synth parents */
+static struct pclk_info clcd_synth_pclk_info[] = {
+ {
+ .pclk = &pll1div4_clk,
+ .pclk_val = CLCD_SYNT_PLL1_DIV4_VAL,
+ }, {
+ .pclk = &pll2_clk,
+ .pclk_val = CLCD_SYNT_PLL2_VAL,
+ },
+};
+
+/* clcd synth parent select structure */
+static struct pclk_sel clcd_synth_pclk_sel = {
+ .pclk_info = clcd_synth_pclk_info,
+ .pclk_count = ARRAY_SIZE(clcd_synth_pclk_info),
+ .pclk_sel_reg = PLL_CFG,
+ .pclk_sel_mask = CLCD_SYNT_CLK_MASK,
+};
+
+/* clcd rate configuration table, in ascending order of rates */
+struct clcd_rate_tbl clcd_rtbl[] = {
+ /* For pll1div4 = 250 MHz */
+ {.div = 0x4000}, /* 62.5 MHz */
+ {.div = 0x2000}, /* 125 MHz */
+};
+
+/* clcd synth clock */
+static struct clk clcd_synth_clk = {
+ .en_reg = CLCD_CLK_SYNT,
+ .en_reg_bit = CLCD_SYNT_ENB,
+ .pclk_sel = &clcd_synth_pclk_sel,
+ .pclk_sel_shift = CLCD_SYNT_CLK_SHIFT,
+ .calc_rate = &clcd_calc_rate,
+ .recalc = &clcd_clk_recalc,
+ .set_rate = &clcd_clk_set_rate,
+ .rate_config = {clcd_rtbl, ARRAY_SIZE(clcd_rtbl), 1},
+ .private_data = &clcd_synth_config,
+};
+
+/* clcd clock parents */
+static struct pclk_info clcd_pclk_info[] = {
+ {
+ .pclk = &pll5_clk,
+ .pclk_val = AUX_CLK_PLL5_VAL,
+ }, {
+ .pclk = &clcd_synth_clk,
+ .pclk_val = AUX_CLK_SYNT_VAL,
+ },
+};
+
+/* clcd parent select structure */
+static struct pclk_sel clcd_pclk_sel = {
+ .pclk_info = clcd_pclk_info,
+ .pclk_count = ARRAY_SIZE(clcd_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = CLCD_CLK_MASK,
+};
+
+/* clcd clock */
+static struct clk clcd_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = CLCD_CLK_ENB,
+ .pclk_sel = &clcd_pclk_sel,
+ .pclk_sel_shift = CLCD_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from ahb clk */
+
+/* i2c clock */
+static struct clk i2c_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2C_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* dma clock */
+static struct clk dma0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = DMA0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk dma1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = DMA1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* jpeg clock */
+static struct clk jpeg_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = JPEG_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gmac clock :Fixed Part*/
+static struct clk gmac0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GMAC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* fsmc clock */
+static struct clk fsmc_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = FSMC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* smi clock */
+static struct clk smi_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SMI_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* uhc0 clock */
+static struct clk uhci0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UHC0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* uhc1 clock */
+static struct clk uhci1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UHC1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* usbd clock */
+static struct clk usbd_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = USBD_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* pci clocks */
+static struct clk pcie0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = PCIE0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk pcie1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = PCIE1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk pcie2_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = PCIE2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* sysram clocks */
+static struct clk sysram0_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SYSRAM0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+static struct clk sysram1_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SYSRAM1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from apb clk */
+/* adc clock */
+static struct clk adc_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = ADC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* ssp clock */
+static struct clk ssp_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SSP_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gpio clock */
+static struct clk gpio0_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPIO0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gpio clock */
+static struct clk gpio1_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPIO1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* i2s0 clock */
+static struct clk i2s0_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2S0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* i2s1 clock */
+static struct clk i2s1_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2S1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* keyboard clock */
+static struct clk kbd_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP2_CLK_ENB,
+ .en_reg_bit = KBD_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* RAS CLOCKS */
+/* pll3 generated clock */
+static struct clk ras_pll3_clk = {
+ .pclk = &pll3_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = PLL3_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* pll2 generated clock */
+static struct clk ras_pll2_clk = {
+ .pclk = &pll2_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = PLL2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* 125MHz clock generated on Tx pad */
+static struct clk ras_tx125_clk = {
+ .pclk = &gmii_txclk125_pad,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = C125_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* 30 MHz clock generated by USB PHy Pll */
+static struct clk ras_30Mhz_clk = {
+ .rate = 30000000,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = C30_CLK_ENB,
+};
+
+/* 48 MHz clock generated by USB PHy Pll */
+static struct clk ras_48Mhz_clk = {
+ .pclk = &pll5_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = C48_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* osc3 generated clock */
+static struct clk ras_osc3_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = OSC3_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* osc2 generated clock */
+static struct clk ras_osc2_clk = {
+ .pclk = &osc2_32k_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = OSC2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* osc1 generated clock */
+static struct clk ras_osc1_clk = {
+ .pclk = &osc1_24m_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = OSC1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* apb generated clock */
+static struct clk ras_pclk_clk = {
+ .pclk = &apb_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = PCLK_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* ahb generated clock */
+static struct clk ras_aclk_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = RAS_CLK_ENB,
+ .en_reg_bit = ACLK_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* External pad 50 MHz clock for phy operation */
+static struct clk ras_tx50_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 50000000,
+};
+
+/* spear1300 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR1300
+
+#endif
+
+static struct clk dummy_apb_pclk;
+
+/* array of all spear 13xx clock lookups */
+static struct clk_lookup spear_clk_lookups[] = {
+ { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
+ /* root clks */
+ {.con_id = "osc1_24m_clk", .clk = &osc1_24m_clk},
+ {.con_id = "osc2_32k_clk", .clk = &osc2_32k_clk},
+ {.con_id = "osc3_25m_clk", .clk = &osc3_25m_clk},
+
+ /* clock derived from 32 KHz osc clk */
+ {.dev_id = "rtc-spear", .clk = &rtc_clk},
+
+ /* clock derived from 24/25 MHz osc1/osc3 clk */
+ {.con_id = "pll1_clk", .clk = &pll1_clk},
+ {.con_id = "pll2_clk", .clk = &pll2_clk},
+ {.con_id = "pll3_clk", .clk = &pll3_clk},
+ {.con_id = "pll4_clk", .clk = &pll4_clk},
+ {.con_id = "pll5_clk", .clk = &pll5_clk},
+ {.con_id = "pll6_clk", .clk = &pll6_clk},
+
+ /* clock derived from pll1 clk */
+ {.con_id = "cpu_clk", .clk = &cpu_clk},
+ {.con_id = "ahb_clk", .clk = &ahb_clk},
+ {.con_id = "apb_clk", .clk = &apb_clk},
+
+ /* synthesizers/prescaled clocks */
+ {.con_id = "pll1div2_clk", .clk = &pll1div2_clk},
+ {.con_id = "pll1div4_clk", .clk = &pll1div4_clk},
+ {.con_id = "c3_synth_clk", .clk = &c3_synth_clk},
+ {.con_id = "gmii_txclk123_pad_clk", .clk = &gmii_txclk125_pad},
+ {.con_id = "clcd_synth_clk", .clk = &clcd_synth_clk},
+ {.con_id = "uart_synth_clk", .clk = &uart_synth_clk},
+ {.con_id = "sdhci_synth_clk", .clk = &sdhci_synth_clk},
+ {.con_id = "cfxd_synth_clk", .clk = &cfxd_synth_clk},
+ {.con_id = "gmac_phy_input_clk", .clk = &gmac_phy_input_clk},
+ {.con_id = "gmac_phy_synth_clk", .clk = &gmac_phy_synth_clk},
+ {.dev_id = "stmmacphy.0", .clk = &gmac_phy0_clk},
+
+ /* RAS clocks */
+ {.con_id = "ras_pll3_clk", .clk = &ras_pll3_clk},
+ {.con_id = "ras_pll2_clk", .clk = &ras_pll2_clk},
+ {.con_id = "ras_tx125_clk", .clk = &ras_tx125_clk},
+ {.con_id = "ras_30Mhz_clk", .clk = &ras_30Mhz_clk},
+ {.con_id = "ras_48Mhz_clk", .clk = &ras_48Mhz_clk},
+ {.con_id = "ras_osc3_clk", .clk = &ras_osc3_clk},
+ {.con_id = "ras_osc2_clk", .clk = &ras_osc2_clk},
+ {.con_id = "ras_osc1_clk", .clk = &ras_osc1_clk},
+ {.con_id = "ras_pclk_clk", .clk = &ras_pclk_clk},
+ {.con_id = "ras_aclk_clk", .clk = &ras_aclk_clk},
+ {.con_id = "ras_tx50_clk", .clk = &ras_tx50_clk},
+
+ /* clocks having multiple parent source from above clocks */
+ {.dev_id = "clcd", .clk = &clcd_clk},
+ {.dev_id = "gpt0", .clk = &gpt0_clk},
+ {.dev_id = "gpt1", .clk = &gpt1_clk},
+ {.dev_id = "gpt2", .clk = &gpt2_clk},
+ {.dev_id = "gpt3", .clk = &gpt3_clk},
+ {.dev_id = "uart", .clk = &uart_clk},
+
+ /* clock derived from ahb clk */
+ {.dev_id = "smi", .clk = &smi_clk},
+ {.con_id = "usbh.0_clk", .clk = &uhci0_clk},
+ {.con_id = "usbh.1_clk", .clk = &uhci1_clk},
+ {.dev_id = "designware_udc", .clk = &usbd_clk},
+ {.dev_id = "i2c_designware.0", .clk = &i2c_clk},
+ {.dev_id = "dma0", .clk = &dma0_clk},
+ {.dev_id = "dma1", .clk = &dma1_clk},
+ {.dev_id = "jpeg", .clk = &jpeg_clk},
+ {.dev_id = "stmmaceth.0", .clk = &gmac0_clk},
+ {.dev_id = "c3", .clk = &c3_clk},
+ {.dev_id = "pcie0", .clk = &pcie0_clk},
+ {.dev_id = "pcie1", .clk = &pcie1_clk},
+ {.dev_id = "pcie2", .clk = &pcie2_clk},
+ {.dev_id = "cfxd", .clk = &cfxd_clk},
+ {.dev_id = "sdhci", .clk = &sdhci_clk},
+ {.con_id = "fsmc", .clk = &fsmc_clk},
+ {.dev_id = "sysram0", .clk = &sysram0_clk},
+ {.dev_id = "sysram1", .clk = &sysram1_clk},
+
+ /* clock derived from apb clk */
+ {.dev_id = "i2s0", .clk = &i2s0_clk},
+ {.dev_id = "i2s1", .clk = &i2s1_clk},
+ {.dev_id = "adc", .clk = &adc_clk},
+ {.dev_id = "ssp-pl022", .clk = &ssp_clk},
+ {.dev_id = "gpio0", .clk = &gpio0_clk},
+ {.dev_id = "gpio1", .clk = &gpio1_clk},
+ {.dev_id = "keyboard", .clk = &kbd_clk},
+ {.dev_id = "wdt", .clk = &wdt_clk},
+};
+
+/* array of all spear 1300 clock lookups */
+#ifdef CONFIG_MACH_SPEAR1300
+static struct clk_lookup spear1300_clk_lookups[] = {
+};
+#endif
+
+void __init spear13xx_clk_init(void)
+{
+ int i, cnt;
+ struct clk_lookup *lookups;
+
+ if (machine_is_spear1300()) {
+ cnt = ARRAY_SIZE(spear1300_clk_lookups);
+ lookups = spear1300_clk_lookups;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+ clk_register(&spear_clk_lookups[i]);
+
+ for (i = 0; i < cnt; i++)
+ clk_register(&lookups[i]);
+
+ clk_init();
+}
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S
new file mode 100644
index 0000000..502c4fe
--- /dev/null
+++ b/arch/arm/mach-spear13xx/headsmp.S
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-spear13XX/headsmp.S
+ *
+ * Picked from realview
+ * Copyright (c) 2010 ST Microelectronics Limited
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ __INIT
+
+/*
+ * spear13xx specific entry point for secondary CPUs. This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(spear13xx_secondary_startup)
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #15
+ adr r4, 1f
+ ldmia r4, {r5, r6}
+ sub r4, r4, r5
+ add r6, r6, r4
+pen: ldr r7, [r6]
+ cmp r7, r0
+ bne pen
+
+ /*
+ * we've been released from the holding pen: secondary_stack
+ * should now contain the SVC stack for this core
+ */
+ b secondary_startup
+
+ .align
+1: .long .
+ .long pen_release
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 95011a2..781894e 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -33,7 +33,7 @@ extern struct amba_device spear13xx_uart_device;
extern struct sys_timer spear13xx_timer;
/* Add spear13xx family function declarations here */
-void __init clk_init(void);
+void __init spear13xx_clk_init(void);
void __init spear_setup_timer(void);
void __init spear13xx_map_io(void);
void __init spear13xx_init_irq(void);
diff --git a/arch/arm/mach-spear13xx/localtimer.c b/arch/arm/mach-spear13xx/localtimer.c
new file mode 100644
index 0000000..816b08c
--- /dev/null
+++ b/arch/arm/mach-spear13xx/localtimer.c
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-spear13xx/localtimer.c
+ * Directly picked from realview
+ *
+ * Copyright (C) 2010 ST Microelectronics Ltd.
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/irq.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+
+/* Setup the local clock events for a CPU. */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+ evt->irq = IRQ_LOCALTIMER;
+ twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
new file mode 100644
index 0000000..6aa4435
--- /dev/null
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -0,0 +1,162 @@
+/*
+ * arch/arm/mach-spear13xx/platsmp.c
+ *
+ * based upon linux/arch/arm/mach-realview/platsmp.c
+ *
+ * Copyright (C) 2010 ST Microelectronics Ltd.
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+#include <asm/smp_scu.h>
+#include <asm/system.h>
+#include <asm/unified.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+static DEFINE_SPINLOCK(boot_lock);
+
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not. This is necessary for the hotplug code to work reliably.
+ */
+static void write_pen_release(int val)
+{
+ pen_release = val;
+ smp_wmb();
+ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+static void __iomem *scu_base_addr(void)
+{
+ return __io_address(SPEAR13XX_SCU_BASE);
+}
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+ /*
+ * if any interrupts are already enabled for the primary
+ * core (e.g. timer irq), then they will not have been enabled
+ * for us: do so
+ */
+ gic_secondary_init(0);
+
+ /*
+ * let the primary processor know we're out of the
+ * pen, then head off into the C entry point
+ */
+ write_pen_release(-1);
+
+ /*
+ * Synchronise with the boot thread.
+ */
+ spin_lock(&boot_lock);
+ spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ unsigned long timeout;
+
+ /*
+ * set synchronisation state between this boot processor
+ * and the secondary one
+ */
+ spin_lock(&boot_lock);
+
+ /*
+ * The secondary processor is waiting to be released from
+ * the holding pen - release it, then wait for it to flag
+ * that it has been released by resetting pen_release.
+ *
+ * Note that "pen_release" is the hardware CPU ID, whereas
+ * "cpu" is Linux's internal ID.
+ */
+ write_pen_release(cpu);
+
+ timeout = jiffies + (1 * HZ);
+ while (time_before(jiffies, timeout)) {
+ smp_rmb();
+ if (pen_release == -1)
+ break;
+
+ udelay(10);
+ }
+
+ /*
+ * now the secondary core is starting up let it run its
+ * calibrations, then wait for it to finish
+ */
+ spin_unlock(&boot_lock);
+
+ return pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+ void __iomem *scu_base = scu_base_addr();
+ unsigned int i, ncores;
+
+ ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+}
+
+static void __init wakeup_secondary(void)
+{
+ /*
+ * Write the address of secondary startup into the system-wide
+ * location (presently it is in SRAM). The BootMonitor waits
+ * for this register to become non-zero.
+ * We must also send an sev to wake it up
+ */
+ __raw_writel(BSYM(virt_to_phys(spear13xx_secondary_startup)),
+ __io_address(SPEAR13XX_SYS_LOCATION));
+
+ mb();
+
+ /*
+ * Send a 'sev' to wake the secondary core from WFE.
+ */
+ sev();
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+ int i;
+
+ /*
+ * Initialise the present map, which describes the set of CPUs
+ * actually populated at the present time.
+ */
+ for (i = 0; i < max_cpus; i++)
+ set_cpu_present(i, true);
+
+ scu_enable(scu_base_addr());
+ wakeup_secondary();
+}
diff --git a/arch/arm/mach-spear13xx/spear1300.c b/arch/arm/mach-spear13xx/spear1300.c
new file mode 100644
index 0000000..9c38bec
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1300.c
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-spear13xx/spear1300.c
+ *
+ * SPEAr1300 machine source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/* Add spear1300 specific devices here */
+
+void __init spear1300_init(void)
+{
+ /* call spear13xx family common init function */
+ spear13xx_init();
+}
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
new file mode 100644
index 0000000..c95c141
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-spear13xx/spear1300_evb.c
+ *
+ * SPEAr1300 evaluation board source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+static struct amba_device *amba_devs[] __initdata = {
+ &spear13xx_uart_device,
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+};
+
+static void __init spear1300_evb_init(void)
+{
+ unsigned int i;
+
+ /* call spear1300 machine init function */
+ spear1300_init();
+
+ /* Add Platform Devices */
+ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+ /* Add Amba Devices */
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+ amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR1300, "ST-SPEAR1300-EVB")
+ .boot_params = 0x00000100,
+ .map_io = spear13xx_map_io,
+ .init_irq = spear13xx_init_irq,
+ .timer = &spear13xx_timer,
+ .init_machine = spear1300_evb_init,
+MACHINE_END
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
new file mode 100644
index 0000000..06f9abb
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -0,0 +1,121 @@
+/*
+ * arch/arm/mach-spear13xx/spear13xx.c
+ *
+ * SPEAr13XX machines common source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/io.h>
+#include <asm/hardware/gic.h>
+#include <asm/irq.h>
+#include <asm/localtimer.h>
+#include <asm/mach/arch.h>
+#include <asm/smp_twd.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+/* Add spear13xx machines common devices here */
+/* uart device registeration */
+struct amba_device spear13xx_uart_device = {
+ .dev = {
+ .init_name = "uart",
+ },
+ .res = {
+ .start = SPEAR13XX_UART_BASE,
+ .end = SPEAR13XX_UART_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART, NO_IRQ},
+};
+
+/* Do spear13xx familiy common initialization part here */
+void __init spear13xx_init(void)
+{
+ /* nothing to do for now */
+}
+
+/* This will initialize vic */
+void __init spear13xx_init_irq(void)
+{
+ gic_init(0, 29, __io_address(SPEAR13XX_GIC_DIST_BASE),
+ __io_address(SPEAR13XX_GIC_CPU_BASE));
+}
+
+/* Following will create static virtual/physical mappings */
+struct map_desc spear13xx_io_desc[] __initdata = {
+ {
+ .virtual = IO_ADDRESS(SPEAR13XX_UART_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_UART_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_A9SM_PERIP_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_A9SM_PERIP_BASE),
+ .length = SZ_8K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_MISC_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_MISC_BASE),
+ .length = SZ_8K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_SYSRAM0_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_SYSRAM0_BASE),
+ .length = SZ_32K,
+ .type = MT_DEVICE
+ },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear13xx_map_io(void)
+{
+ iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
+
+ /* This will initialize clock framework */
+ spear13xx_clk_init();
+}
+
+static void __init spear13xx_timer_init(void)
+{
+ char pclk_name[] = "osc1_24m_clk";
+ struct clk *gpt_clk, *pclk;
+
+#ifdef CONFIG_LOCAL_TIMERS
+ /* Setup the local timer base */
+ twd_base = __io_address(SPEAR13XX_LOCAL_TMR_BASE);
+#endif
+
+ /* get the system timer clock */
+ gpt_clk = clk_get_sys("gpt0", NULL);
+ if (IS_ERR(gpt_clk)) {
+ pr_err("%s:couldn't get clk for gpt\n", __func__);
+ BUG();
+ }
+
+ /* get the suitable parent clock for timer*/
+ pclk = clk_get(NULL, pclk_name);
+ if (IS_ERR(pclk)) {
+ pr_err("%s:couldn't get %s as parent for gpt\n",
+ __func__, pclk_name);
+ BUG();
+ }
+
+ clk_set_parent(gpt_clk, pclk);
+ clk_put(gpt_clk);
+ clk_put(pclk);
+
+ spear_setup_timer();
+}
+
+struct sys_timer spear13xx_timer = {
+ .init = spear13xx_timer_init,
+};
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 03/10] ST SPEAr13xx: Adding support in SPEAr generic plat/
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977719.git.viresh.kumar@st.com>
From: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/plat-spear/Kconfig | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbc..29a25d2 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -8,6 +8,13 @@ choice
prompt "ST SPEAr Family"
default ARCH_SPEAR3XX
+config ARCH_SPEAR13XX
+ bool "SPEAr13XX"
+ select ARM_GIC
+ select CPU_V7
+ help
+ Supports for ARM's SPEAR13XX family
+
config ARCH_SPEAR3XX
bool "SPEAr3XX"
select ARM_VIC
@@ -25,6 +32,7 @@ config ARCH_SPEAR6XX
endchoice
# Adding SPEAr machine specific configuration files
+source "arch/arm/mach-spear13xx/Kconfig"
source "arch/arm/mach-spear3xx/Kconfig"
source "arch/arm/mach-spear6xx/Kconfig"
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 04/10] ST SPEAr13xx: Added compilation support in arch/arm/
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977719.git.viresh.kumar@st.com>
From: Shiraz Hashim <shiraz.hashim@st.com>
This patch adds compilation support for ST Microelectronics SPEAr13xx machines.
SPEAr13xx SOC's are based on Arm CortexA9 CPUs.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/Kconfig | 4 ++--
arch/arm/Makefile | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 166efa2..d9efe86 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1278,8 +1278,8 @@ config SMP
depends on GENERIC_CLOCKEVENTS
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
- ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
- ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
+ ARCH_S5PV310 || ARCH_SPEAR13XX || ARCH_TEGRA || ARCH_U8500 || \
+ ARCH_VEXPRESS_CA9X4 || ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
select USE_GENERIC_SMP_HELPERS
select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
help
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6f7b292..f4f3021 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -193,6 +193,7 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_ARCH_NUC93X) := nuc93x
machine-$(CONFIG_FOOTBRIDGE) := footbridge
+machine-$(CONFIG_MACH_SPEAR1300) := spear13xx
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 05/10] ST SPEAr13xx: Adding default config file
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977719.git.viresh.kumar@st.com>
From: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/configs/spear13xx_defconfig | 60 ++++++++++++++++++++++++++++++++++
1 files changed, 60 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/configs/spear13xx_defconfig
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
new file mode 100644
index 0000000..10b1cf5
--- /dev/null
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -0,0 +1,60 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR13XX=y
+CONFIG_BOARD_SPEAR1300_EVB=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_AEABI=y
+CONFIG_BINFMT_MISC=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+# CONFIG_HWMON is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_AUTOFS4_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+CONFIG_DEBUG_INFO=y
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 06/10] ST SPEAr13xx: Adding information in Documentation/ and MAINTAINERS
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977719.git.viresh.kumar@st.com>
From: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
Documentation/arm/SPEAr/overview.txt | 34 +++++++++++++++++++++++-----------
MAINTAINERS | 6 ++++++
2 files changed, 29 insertions(+), 11 deletions(-)
diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 253a35c..4e510061 100644
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -9,8 +9,9 @@ Introduction
The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
supported by the 'spear' platform of ARM Linux. Currently SPEAr300,
- SPEAr310, SPEAr320 and SPEAr600 SOCs are supported. Support for the SPEAr13XX
- series is in progress.
+ SPEAr310, SPEAr320, SPEAr600, SPEAr1300 and SPEAr1310 SOCs are supported.
+ SPEAr3XX and SPEAr6XX are based on ARM9 whereas SPEAr13XX is based on latest
+ ARM Cortex A9 CPUs.
Hierarchy in SPEAr is as follows:
@@ -27,16 +28,25 @@ Introduction
- SPEAr600_EVB (Evaluation Board)
- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
- SPEAr1300 (SOC)
+ - SPEAr1300_EVB (Evaluation Board)
+ - SPEAr1310 (SOC)
+ - SPEAr1310_EVB (Evaluation Board)
Configuration
-------------
- A generic configuration is provided for each machine, and can be used as the
+ A generic configuration is provided for each machine family, and can be used as the
default by
- make spear600_defconfig
- make spear300_defconfig
- make spear310_defconfig
- make spear320_defconfig
+ #make ARCH=arm spear13xx_defconfig
+ #make ARCH=arm spear3xx_defconfig
+ #make ARCH=arm spear6xx_defconfig
+
+ Compilation
+ -----------
+
+ After applying default configuration, Linux kernel for SPEAr architecture
+ can be compiled as
+ #make ARCH=arm CROSS_COMPILE=arm-linux- uImage
Layout
------
@@ -48,13 +58,15 @@ Introduction
Each machine series have a directory with name arch/arm/mach-spear followed by
series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx.
- Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
- spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
+ Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c, for
+ spear6xx is mach-spear6xx/spear6xx.c and similarly for spear13xx is
+ mach-spear13xx/spear13xx.c. mach-spear* also contain soc/machine
specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
- mach-spear* also contains board specific files for each machine type.
+ Board specific files for each machine type is also contained in mach-spear*
+ folder.
Document Author
---------------
- Viresh Kumar, (c) 2010 ST Microelectronics
+ Viresh Kumar, Shiraz Hashim (c) 2010 ST Microelectronics
diff --git a/MAINTAINERS b/MAINTAINERS
index 8afba63..da45149 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5852,6 +5852,12 @@ W: http://www.st.com/spear
S: Maintained
F: arch/arm/plat-spear/
+SPEAR13XX MACHINE SUPPORT
+M: Shiraz Hashim <shiraz.hashim@st.com>
+W: http://www.st.com/spear
+S: Maintained
+F: arch/arm/mach-spear13xx/
+
SPEAR3XX MACHINE SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
W: http://www.st.com/spear
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 07/10] ST SPEAr13xx: Adding CPU hotplug support added for SMP platforms
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977719.git.viresh.kumar@st.com>
From: Deepak Sikri <deepak.sikri@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/Makefile | 1 +
arch/arm/mach-spear13xx/hotplug.c | 121 +++++++++++++++++++++++++++++++++++++
2 files changed, 122 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/hotplug.c
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
index cb5ae9e..09b71e4 100644
--- a/arch/arm/mach-spear13xx/Makefile
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -5,6 +5,7 @@
# common files
obj-y += spear13xx.o clock.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
# spear1300 specific files
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c
new file mode 100644
index 0000000..ee6b06d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/hotplug.c
@@ -0,0 +1,121 @@
+/*
+ * linux/arch/arm/mach-spear13xx/hotplug.c
+ *
+ * Copyright (C) 2010 ST Microelectronics Ltd.
+ * Deepak Sikri <deepak.sikri@st.com>
+ *
+ * based upon linux/arch/arm/mach-realview/hotplug.c
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/system.h>
+
+extern volatile int pen_release;
+
+static inline void cpu_enter_lowpower(void)
+{
+ unsigned int v;
+
+ flush_cache_all();
+ asm volatile(
+ " mcr p15, 0, %1, c7, c5, 0\n"
+ " dsb\n"
+ /*
+ * Turn off coherency
+ */
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " bic %0, %0, #0x20\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ " mrc p15, 0, %0, c1, c0, 0\n"
+ " bic %0, %0, %2\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ : "=&r" (v)
+ : "r" (0), "Ir" (CR_C)
+ : "cc", "memory");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+ unsigned int v;
+
+ asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+ " orr %0, %0, %1\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " orr %0, %0, #0x20\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ : "=&r" (v)
+ : "Ir" (CR_C)
+ : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+ for (;;) {
+ wfi();
+
+ if (pen_release == cpu) {
+ /*
+ * OK, proper wakeup, we're done
+ */
+ break;
+ }
+
+ /*
+ * Getting here, means that we have come out of WFI without
+ * having been woken up - this shouldn't happen
+ *
+ * Just note it happening - when we're woken, we can report
+ * its occurrence.
+ */
+ (*spurious)++;
+ }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+ return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __cpuinit platform_cpu_die(unsigned int cpu)
+{
+ int spurious = 0;
+
+ /*
+ * we're ready for shutdown now, so do it
+ */
+ cpu_enter_lowpower();
+ platform_do_lowpower(cpu, &spurious);
+
+ /*
+ * bring this CPU back into the world of cache
+ * coherency, and then restore interrupts
+ */
+ cpu_leave_lowpower();
+
+ if (spurious)
+ pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+ /*
+ * we don't allow CPU 0 to be shutdown (it is still too special
+ * e.g. clock tick interrupts)
+ */
+ return cpu == 0 ? -EPERM : 0;
+}
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 08/10] ST SPEAr13xx: add L2 cache support
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977719.git.viresh.kumar@st.com>
From: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear13xx/spear13xx.c | 19 ++++++++++++++++++-
arch/arm/mm/Kconfig | 2 +-
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 06f9abb..b5da555 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -18,6 +18,7 @@
#include <asm/irq.h>
#include <asm/localtimer.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
#include <asm/smp_twd.h>
#include <mach/generic.h>
#include <mach/hardware.h>
@@ -40,7 +41,16 @@ struct amba_device spear13xx_uart_device = {
/* Do spear13xx familiy common initialization part here */
void __init spear13xx_init(void)
{
- /* nothing to do for now */
+#ifdef CONFIG_CACHE_L2X0
+ /*
+ * 512KB (64KB/way), 8-way associativity, parity supported
+ *
+ * TODO: 0x249, picked from nomadik, to be analyzed
+ * Comment from nomadik:
+ * At full speed latency must be >=2, so 0x249 in low bits
+ */
+ l2x0_init(__io_address(SPEAR13XX_L2CC_BASE), 0x00260249, 0xfe00ffff);
+#endif
}
/* This will initialize vic */
@@ -62,6 +72,13 @@ struct map_desc spear13xx_io_desc[] __initdata = {
.pfn = __phys_to_pfn(SPEAR13XX_A9SM_PERIP_BASE),
.length = SZ_8K,
.type = MT_DEVICE
+#ifdef CONFIG_CACHE_L2X0
+ }, {
+ .virtual = IO_ADDRESS(SPEAR13XX_L2CC_BASE),
+ .pfn = __phys_to_pfn(SPEAR13XX_L2CC_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+#endif
}, {
.virtual = IO_ADDRESS(SPEAR13XX_MISC_BASE),
.pfn = __phys_to_pfn(SPEAR13XX_MISC_BASE),
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e4509ba..fff2d89 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -813,7 +813,7 @@ config CACHE_L2X0
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
+ ARCH_SPEAR13XX || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
default y
select OUTER_CACHE
select OUTER_CACHE_SYNC
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 09/10] ST SPEAr13xx: Adding support for SPEAr1310
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977719.git.viresh.kumar@st.com>
From: Bhupesh Sharma <bhupesh.sharma@st.com>
This patch adds support for SPEAr1310 Machine and evaluation board.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
---
arch/arm/Makefile | 1 +
arch/arm/configs/spear13xx_defconfig | 1 +
arch/arm/mach-spear13xx/Kconfig | 11 ++
arch/arm/mach-spear13xx/Makefile | 6 +
arch/arm/mach-spear13xx/clock.c | 154 ++++++++++++++++++++++
arch/arm/mach-spear13xx/include/mach/generic.h | 17 +++
arch/arm/mach-spear13xx/include/mach/irqs.h | 37 +++++
arch/arm/mach-spear13xx/include/mach/spear.h | 1 +
arch/arm/mach-spear13xx/include/mach/spear1310.h | 64 +++++++++
arch/arm/mach-spear13xx/spear1310.c | 144 ++++++++++++++++++++
arch/arm/mach-spear13xx/spear1310_evb.c | 61 +++++++++
11 files changed, 497 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1310.h
create mode 100644 arch/arm/mach-spear13xx/spear1310.c
create mode 100644 arch/arm/mach-spear13xx/spear1310_evb.c
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index f4f3021..4b25e69 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -194,6 +194,7 @@ machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_ARCH_NUC93X) := nuc93x
machine-$(CONFIG_FOOTBRIDGE) := footbridge
machine-$(CONFIG_MACH_SPEAR1300) := spear13xx
+machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 10b1cf5..9f3baf8 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -9,6 +9,7 @@ CONFIG_MODVERSIONS=y
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR13XX=y
CONFIG_BOARD_SPEAR1300_EVB=y
+CONFIG_BOARD_SPEAR1310_EVB=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_AEABI=y
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
index 3ea463d..229ef93 100644
--- a/arch/arm/mach-spear13xx/Kconfig
+++ b/arch/arm/mach-spear13xx/Kconfig
@@ -11,6 +11,12 @@ config BOARD_SPEAR1300_EVB
help
Supports ST SPEAr1300 Evaluation Board
+config BOARD_SPEAR1310_EVB
+ bool "SPEAr1310 Evaluation Board"
+ select MACH_SPEAR1310
+ help
+ Supports ST SPEAr1310 Evaluation Board
+
endmenu
config MACH_SPEAR1300
@@ -18,4 +24,9 @@ config MACH_SPEAR1300
help
Supports ST SPEAr1300 Machine
+config MACH_SPEAR1310
+ bool "SPEAr1310"
+ help
+ Supports ST SPEAr1310 Machine
+
endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
index 09b71e4..24bbe16 100644
--- a/arch/arm/mach-spear13xx/Makefile
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -13,3 +13,9 @@ obj-$(CONFIG_MACH_SPEAR1300) += spear1300.o
# spear1300 boards files
obj-$(CONFIG_BOARD_SPEAR1300_EVB) += spear1300_evb.o
+
+# spear1310 specific files
+obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o
+
+# spear1310 boards files
+obj-$(CONFIG_BOARD_SPEAR1310_EVB) += spear1310_evb.o
diff --git a/arch/arm/mach-spear13xx/clock.c b/arch/arm/mach-spear13xx/clock.c
index 58d3ec0..008749a 100644
--- a/arch/arm/mach-spear13xx/clock.c
+++ b/arch/arm/mach-spear13xx/clock.c
@@ -896,6 +896,136 @@ static struct clk ras_tx50_clk = {
#endif
+/* spear1310 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR1310
+/* can0 clock */
+static struct clk can0_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* can1 clock */
+static struct clk can1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* gmac clocks :RAS part*/
+static struct clk gmac_ras1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_aclk_clk,
+ .recalc = &follow_parent,
+};
+
+static struct clk gmac_ras2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_aclk_clk,
+ .recalc = &follow_parent,
+};
+
+static struct clk gmac_ras3_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_aclk_clk,
+ .recalc = &follow_parent,
+};
+
+static struct clk gmac_ras4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_aclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* phy clock parent select */
+static struct pclk_info phy_pclk_info[] = {
+ {
+ .pclk = &ras_pll2_clk,
+ .pclk_val = 0x8,
+ }, {
+ .pclk = &ras_tx125_clk,
+ .pclk_val = 0x4,
+ }, {
+ .pclk = &ras_tx50_clk,
+ .pclk_val = 0x0,
+ },
+};
+
+static struct pclk_sel phy_pclk_sel = {
+ .pclk_info = phy_pclk_info,
+ .pclk_count = ARRAY_SIZE(phy_pclk_info),
+ .pclk_sel_reg = IOMEM(IO_ADDRESS(SPEAR1310_RAS_CTRL_REG1)),
+ .pclk_sel_mask = SPEAR1310_PHY_CLK_MASK,
+};
+
+/* Phy 1 Clock */
+struct clk gmac_phy1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &phy_pclk_sel,
+ .pclk_sel_shift = SPEAR1310_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* Phy 2 Clock */
+static struct clk gmac_phy2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &phy_pclk_sel,
+ .pclk_sel_shift = SPEAR1310_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* Phy 3 Clock */
+static struct clk gmac_phy3_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &phy_pclk_sel,
+ .pclk_sel_shift = SPEAR1310_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* Phy 4 Clock */
+static struct clk gmac_phy4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &phy_pclk_sel,
+ .pclk_sel_shift = SPEAR1310_PHY_CLK_SHIFT,
+ .recalc = &follow_parent,
+};
+
+/* uart1 clock */
+static struct clk uart1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart2 clock */
+static struct clk uart2_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart3 clock */
+static struct clk uart3_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart4 clock */
+static struct clk uart4_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+
+/* uart5 clock */
+static struct clk uart5_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ras_pclk_clk,
+ .recalc = &follow_parent,
+};
+#endif
+
static struct clk dummy_apb_pclk;
/* array of all spear 13xx clock lookups */
@@ -993,6 +1123,27 @@ static struct clk_lookup spear1300_clk_lookups[] = {
};
#endif
+/* array of all spear 1310 clock lookups */
+#ifdef CONFIG_MACH_SPEAR1310
+static struct clk_lookup spear1310_clk_lookups[] = {
+ {.dev_id = "c_can_platform.0", .clk = &can0_clk},
+ {.dev_id = "c_can_platform.1", .clk = &can1_clk},
+ {.dev_id = "stmmaceth.1", .clk = &gmac_ras1_clk},
+ {.dev_id = "stmmaceth.2", .clk = &gmac_ras2_clk},
+ {.dev_id = "stmmaceth.3", .clk = &gmac_ras3_clk},
+ {.dev_id = "stmmaceth.4", .clk = &gmac_ras4_clk},
+ {.dev_id = "stmmacphy.1", .clk = &gmac_phy1_clk},
+ {.dev_id = "stmmacphy.2", .clk = &gmac_phy2_clk},
+ {.dev_id = "stmmacphy.3", .clk = &gmac_phy3_clk},
+ {.dev_id = "stmmacphy.4", .clk = &gmac_phy4_clk},
+ {.dev_id = "uart1", .clk = &uart1_clk},
+ {.dev_id = "uart2", .clk = &uart2_clk},
+ {.dev_id = "uart3", .clk = &uart3_clk},
+ {.dev_id = "uart4", .clk = &uart4_clk},
+ {.dev_id = "uart5", .clk = &uart5_clk},
+};
+#endif
+
void __init spear13xx_clk_init(void)
{
int i, cnt;
@@ -1001,6 +1152,9 @@ void __init spear13xx_clk_init(void)
if (machine_is_spear1300()) {
cnt = ARRAY_SIZE(spear1300_clk_lookups);
lookups = spear1300_clk_lookups;
+ } else {
+ cnt = ARRAY_SIZE(spear1310_clk_lookups);
+ lookups = spear1310_clk_lookups;
}
for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index 781894e..64feaa5 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -47,4 +47,21 @@ void __init spear1300_init(void);
#endif /* CONFIG_MACH_SPEAR1300 */
+/* spear1310 declarations */
+#ifdef CONFIG_MACH_SPEAR1310
+/* Add spear1310 machine device structure declarations here */
+extern struct amba_device spear1310_uart1_device;
+extern struct amba_device spear1310_uart2_device;
+extern struct amba_device spear1310_uart3_device;
+extern struct amba_device spear1310_uart4_device;
+extern struct amba_device spear1310_uart5_device;
+extern struct platform_device spear1310_can0_device;
+extern struct platform_device spear1310_can1_device;
+
+/* Add spear1310 machine function declarations here */
+void __init spear1310_init(void);
+void __init spear1310_map_io(void);
+
+#endif /* CONFIG_MACH_SPEAR1310 */
+
#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
index d9fe051..c175175 100644
--- a/arch/arm/mach-spear13xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -5,6 +5,7 @@
*
* Copyright (C) 2010 ST Microelectronics
* Shiraz Hashim <shiraz.hashim@st.com>
+ * Bhupesh Sharma <bhupesh.sharma@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
@@ -84,6 +85,42 @@
#define IRQ_PCIE1 (IRQ_SHPI_START + 69)
#define IRQ_PCIE2 (IRQ_SHPI_START + 70)
+/* Add spear1310 specific IRQs here */
+#ifdef CONFIG_MACH_SPEAR1310
+#define IRQ_FSMC_PC1 (IRQ_SHPI_START + 76)
+#define IRQ_FSMC_PC2 (IRQ_SHPI_START + 77)
+#define IRQ_FSMC_PC3 (IRQ_SHPI_START + 78)
+#define IRQ_FSMC_PC4 (IRQ_SHPI_START + 79)
+#define IRQ_RS4850 (IRQ_SHPI_START + 80)
+#define IRQ_RS4851 (IRQ_SHPI_START + 81)
+#define IRQ_CCAN0 (IRQ_SHPI_START + 82)
+#define IRQ_CCAN1 (IRQ_SHPI_START + 83)
+#define IRQ_TDM0 (IRQ_SHPI_START + 84)
+#define IRQ_TDM1 (IRQ_SHPI_START + 85)
+#define IRQ_UART1 (IRQ_SHPI_START + 86)
+#define IRQ_UART2 (IRQ_SHPI_START + 87)
+#define IRQ_UART3 (IRQ_SHPI_START + 88)
+#define IRQ_UART4 (IRQ_SHPI_START + 89)
+#define IRQ_UART5 (IRQ_SHPI_START + 90)
+#define IRQ_I2C_CNTR (IRQ_SHPI_START + 91)
+#define IRQ_GMAC0_SBD (IRQ_SHPI_START + 92)
+#define IRQ_GMAC0_PMT (IRQ_SHPI_START + 93)
+#define IRQ_GMAC1_SBD (IRQ_SHPI_START + 94)
+#define IRQ_GMAC1_PMT (IRQ_SHPI_START + 95)
+#define IRQ_GMAC2_SBD (IRQ_SHPI_START + 96)
+#define IRQ_GMAC2_PMT (IRQ_SHPI_START + 97)
+#define IRQ_GMAC3_SBD (IRQ_SHPI_START + 98)
+#define IRQ_GMAC3_PMT (IRQ_SHPI_START + 99)
+#define IRQ_GPIO (IRQ_SHPI_START + 100)
+#define IRQ_PCI_BRDG_HOST_FATAL (IRQ_SHPI_START + 101)
+#define IRQ_PCI_INTA (IRQ_SHPI_START + 102)
+#define IRQ_PCI_INTB (IRQ_SHPI_START + 103)
+#define IRQ_PCI_INTC (IRQ_SHPI_START + 104)
+#define IRQ_PCI_INTD (IRQ_SHPI_START + 105)
+#define IRQ_PCI_ME_TO_ARM (IRQ_SHPI_START + 106)
+#define IRQ_PCI_SERR_TO_ARM (IRQ_SHPI_START + 107)
+#endif /* CONFIG_MACH_SPEAR1310 */
+
#define IRQ_GIC_END (IRQ_SHPI_START + 128)
#define NR_IRQS IRQ_GIC_END
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 1a1af72..cf25eb5 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -16,6 +16,7 @@
#include <asm/memory.h>
#include <mach/spear1300.h>
+#include <mach/spear1310.h>
#define SPEAR13XX_L2CC_BASE UL(0xED000000)
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1310.h b/arch/arm/mach-spear13xx/include/mach/spear1310.h
new file mode 100644
index 0000000..34f0a27
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1310.h
@@ -0,0 +1,64 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear1310.h
+ *
+ * SPEAr1310 Machine specific definition
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Bhupesh Sharma <bhupesh.sharma@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef CONFIG_MACH_SPEAR1310
+
+#ifndef __MACH_SPEAR1310_H
+#define __MACH_SPEAR1310_H
+
+#define SPEAR1310_TDM_E1_0_BASE UL(0x6C200000)
+#define SPEAR1310_TDM_E1_1_BASE UL(0x6C300000)
+#define SPEAR1310_RS485_0_BASE UL(0x6C400000)
+#define SPEAR1310_RS485_1_BASE UL(0x6C500000)
+#define SPEAR1310_GETH1_BASE UL(0x6D000000)
+#define SPEAR1310_GETH2_BASE UL(0x6D100000)
+#define SPEAR1310_GETH3_BASE UL(0x6D200000)
+#define SPEAR1310_GETH4_BASE UL(0x6D300000)
+#define SPEAR1310_UART1_BASE UL(0x6D400000)
+#define SPEAR1310_UART2_BASE UL(0x6D500000)
+#define SPEAR1310_UART3_BASE UL(0x6D600000)
+#define SPEAR1310_UART4_BASE UL(0x6D700000)
+#define SPEAR1310_UART5_BASE UL(0x6D800000)
+#define SPEAR1310_I2C1_BASE UL(0x6D900000)
+#define SPEAR1310_CAN0_BASE UL(0x6DA00000)
+#define SPEAR1310_CAN1_BASE UL(0x6DB00000)
+#define SPEAR1310_RAS_BASE UL(0x6C800000)
+#define SPEAR1310_GETH1_BASE UL(0x6D000000)
+#define SPEAR1310_GETH2_BASE UL(0x6D100000)
+#define SPEAR1310_GETH3_BASE UL(0x6D200000)
+#define SPEAR1310_GETH4_BASE UL(0x6D300000)
+#define SPEAR1310_FSMC1_CS0_BASE UL(0x70000000)
+#define SPEAR1310_FSMC1_CS1_BASE UL(0x74000000)
+#define SPEAR1310_FSMC1_CS2_BASE UL(0x78000000)
+#define SPEAR1310_FSMC1_CS3_BASE UL(0x7C000000)
+#define SPEAR1310_FSMC1_BASE UL(0x6FF00000)
+
+/* RAS Area Control Register */
+#define SPEAR1310_RAS_CTRL_REG0 (SPEAR1310_RAS_BASE + 0x0)
+#define SPEAR1310_RAS_CTRL_REG1 (SPEAR1310_RAS_BASE + 0x4)
+#define SPEAR1310_PHY_CLK_MASK 0xF
+#define SPEAR1310_PHY_CLK_SHIFT 0
+
+#define RAS_FSMC_MODE_MASK 0x3
+#define RAS_FSMC_MODE_NOR 0
+#define RAS_FSMC_MODE_NAND 1
+#define RAS_FSMC_MODE_SRAM 2
+#define RAS_FSMC_WIDTH_MASK 0x30
+#define RAS_FSMC_WIDTH_8 0x00
+#define RAS_FSMC_WIDTH_16 0x10
+#define RAS_FSMC_WIDTH_32 0x20
+#define RAS_FSMC_CS_SPLIT 0x40
+
+#endif /* __MACH_SPEAR1310_H */
+
+#endif /* CONFIG_MACH_SPEAR1310 */
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
new file mode 100644
index 0000000..e4ad092
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -0,0 +1,144 @@
+/*
+ * arch/arm/mach-spear13xx/spear1310.c
+ *
+ * SPEAr1310 machine source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Bhupesh Sharma <bhupesh.sharma@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/ptrace.h>
+#include <asm/irq.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/* Add spear1310 specific devices here */
+/* uart1 device registeration */
+struct amba_device spear1310_uart1_device = {
+ .dev = {
+ .init_name = "uart1",
+ },
+ .res = {
+ .start = SPEAR1310_UART1_BASE,
+ .end = SPEAR1310_UART1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART1, NO_IRQ},
+};
+
+/* uart2 device registeration */
+struct amba_device spear1310_uart2_device = {
+ .dev = {
+ .init_name = "uart2",
+ },
+ .res = {
+ .start = SPEAR1310_UART2_BASE,
+ .end = SPEAR1310_UART2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART2, NO_IRQ},
+};
+
+/* uart3 device registeration */
+struct amba_device spear1310_uart3_device = {
+ .dev = {
+ .init_name = "uart3",
+ },
+ .res = {
+ .start = SPEAR1310_UART3_BASE,
+ .end = SPEAR1310_UART3_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART3, NO_IRQ},
+};
+
+/* uart4 device registeration */
+struct amba_device spear1310_uart4_device = {
+ .dev = {
+ .init_name = "uart4",
+ },
+ .res = {
+ .start = SPEAR1310_UART4_BASE,
+ .end = SPEAR1310_UART4_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART4, NO_IRQ},
+};
+
+/* uart5 device registeration */
+struct amba_device spear1310_uart5_device = {
+ .dev = {
+ .init_name = "uart5",
+ },
+ .res = {
+ .start = SPEAR1310_UART5_BASE,
+ .end = SPEAR1310_UART5_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART5, NO_IRQ},
+};
+
+/* CAN device registeration */
+static struct resource can0_resources[] = {
+ {
+ .start = SPEAR1310_CAN0_BASE,
+ .end = SPEAR1310_CAN0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_CCAN0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear1310_can0_device = {
+ .name = "c_can_platform",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(can0_resources),
+ .resource = can0_resources,
+};
+
+static struct resource can1_resources[] = {
+ {
+ .start = SPEAR1310_CAN1_BASE,
+ .end = SPEAR1310_CAN1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_CCAN1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear1310_can1_device = {
+ .name = "c_can_platform",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(can1_resources),
+ .resource = can1_resources,
+};
+
+/* Following will create 1310 specific static virtual/physical mappings */
+struct map_desc spear1310_io_desc[] __initdata = {
+ {
+ .virtual = IO_ADDRESS(SPEAR1310_RAS_BASE),
+ .pfn = __phys_to_pfn(SPEAR1310_RAS_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+ },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear1310_map_io(void)
+{
+ iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc));
+ spear13xx_map_io();
+}
+
+void __init spear1310_init(void)
+{
+ /* call spear13xx family common init function */
+ spear13xx_init();
+}
diff --git a/arch/arm/mach-spear13xx/spear1310_evb.c b/arch/arm/mach-spear13xx/spear1310_evb.c
new file mode 100644
index 0000000..a87e82b
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1310_evb.c
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-spear13xx/spear1310_evb.c
+ *
+ * SPEAr1310 evaluation board source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Bhupesh Sharma <bhupesh.sharma@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+static struct amba_device *amba_devs[] __initdata = {
+ /* spear13xx specific devices */
+ &spear13xx_uart_device,
+
+ /* spear1310 specific devices */
+ &spear1310_uart1_device,
+ &spear1310_uart2_device,
+ &spear1310_uart3_device,
+ &spear1310_uart4_device,
+ &spear1310_uart5_device,
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+ /* spear13xx specific devices */
+
+ /* spear1310 specific devices */
+ &spear1310_can0_device,
+ &spear1310_can1_device,
+};
+
+static void __init spear1310_evb_init(void)
+{
+ unsigned int i;
+
+ /* call spear1310 machine init function */
+ spear1310_init();
+
+ /* Add Platform Devices */
+ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+ /* Add Amba Devices */
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+ amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR1310, "ST-SPEAR1310-EVB")
+ .boot_params = 0x00000100,
+ .map_io = spear1310_map_io,
+ .init_irq = spear13xx_init_irq,
+ .timer = &spear13xx_timer,
+ .init_machine = spear1310_evb_init,
+MACHINE_END
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 00/17] Adding devices support for all spear machines
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds device drivers and their machine support for all SPEAr
Families.
Note: These patches were earlier sent as part of a larger patchset:
"Updating SPEAr Support"
Now it is divided into smaller patchsets. In order to apply these patches
cleanly following order of patchsets must be maintained.
- SPEAr3xx & SPEAr6xx Fixes
- SPEAr3xx & SPEAr6xx: Single Image solution and padmux updates
- Adding SPEAr13xx support
- Adding devices support for all spear machines
- Clock Framework & CPU Freq Updates
Deepak Sikri (2):
ST SPEAr: Adding machine support for USB host
ST SPEAr Power Management: Added the support for Standby mode.
Pratyush Anand (1):
ST SPEAr13xx: Added PCIe host controller base driver support.
Rajeev Kumar (3):
ST SPEAr: Adding machine support for rtc-spear
ST SPEAr: adding support for synopsis i2c designware
ST SPEAr: Adding machine support for keyboard
Vipin Kumar (2):
ST SPEAr3xx: EMI (External Memory Interface) controller driver
ST SPEAr: Adding machine support for nand
Viresh Kumar (9):
ST SPEAr13xx: Added ARM PL061 GPIO Support
ST SPEAr: Adding PLGPIO driver for spear platform
ST SPEAr3xx: Adding support for ST's PWM IP
ST SPEAr: Adding Watchdog support on spear3xx & spear6xx machines
ST SPEAr3xx: Adding RAS uart devices
ST SPEAr320: Adding support for CAN
ST SPEAr: Adding support for SSP PL022
ST SPEAr: Adding support for SDHCI (SDIO)
ST SPEAr: Updating defconfigs
arch/arm/Kconfig | 1 +
arch/arm/configs/spear13xx_defconfig | 78 ++-
arch/arm/configs/spear3xx_defconfig | 80 ++-
arch/arm/configs/spear6xx_defconfig | 72 ++-
arch/arm/mach-spear13xx/Makefile | 2 +
arch/arm/mach-spear13xx/include/mach/generic.h | 15 +
arch/arm/mach-spear13xx/include/mach/gpio.h | 18 +
arch/arm/mach-spear13xx/include/mach/hardware.h | 7 +
arch/arm/mach-spear13xx/include/mach/irqs.h | 27 +-
arch/arm/mach-spear13xx/include/mach/pcie.h | 170 +++++
arch/arm/mach-spear13xx/include/mach/suspend.h | 47 ++
arch/arm/mach-spear13xx/pcie.c | 861 +++++++++++++++++++++++
arch/arm/mach-spear13xx/pm.c | 107 +++
arch/arm/mach-spear13xx/sleep.S | 435 ++++++++++++
arch/arm/mach-spear13xx/spear1300_evb.c | 90 +++
arch/arm/mach-spear13xx/spear1310.c | 22 +
arch/arm/mach-spear13xx/spear1310_evb.c | 91 +++
arch/arm/mach-spear13xx/spear13xx.c | 355 ++++++++++
arch/arm/mach-spear3xx/Makefile | 4 +
arch/arm/mach-spear3xx/emi.c | 98 +++
arch/arm/mach-spear3xx/include/mach/emi.h | 61 ++
arch/arm/mach-spear3xx/include/mach/generic.h | 35 +
arch/arm/mach-spear3xx/include/mach/gpio.h | 143 ++++
arch/arm/mach-spear3xx/include/mach/spear310.h | 9 +
arch/arm/mach-spear3xx/include/mach/spear320.h | 6 +
arch/arm/mach-spear3xx/include/mach/suspend.h | 44 ++
arch/arm/mach-spear3xx/spear300.c | 146 ++++
arch/arm/mach-spear3xx/spear300_evb.c | 85 +++
arch/arm/mach-spear3xx/spear310.c | 155 ++++
arch/arm/mach-spear3xx/spear310_evb.c | 102 +++
arch/arm/mach-spear3xx/spear320.c | 216 ++++++
arch/arm/mach-spear3xx/spear320_evb.c | 92 +++
arch/arm/mach-spear3xx/spear3xx.c | 168 +++++-
arch/arm/mach-spear6xx/include/mach/generic.h | 10 +
arch/arm/mach-spear6xx/include/mach/gpio.h | 27 +
arch/arm/mach-spear6xx/include/mach/suspend.h | 44 ++
arch/arm/mach-spear6xx/spear600_evb.c | 37 +
arch/arm/mach-spear6xx/spear6xx.c | 260 +++++++-
arch/arm/plat-spear/Kconfig | 9 +
arch/arm/plat-spear/Makefile | 17 +
arch/arm/plat-spear/i2c_eval_board.c | 29 +
arch/arm/plat-spear/include/plat/gpio.h | 35 +
arch/arm/plat-spear/include/plat/keyboard.h | 7 -
arch/arm/plat-spear/include/plat/spi.h | 74 ++
arch/arm/plat-spear/plgpio.c | 473 +++++++++++++
arch/arm/plat-spear/pm.c | 104 +++
arch/arm/plat-spear/pwm.c | 484 +++++++++++++
arch/arm/plat-spear/sleep.S | 288 ++++++++
48 files changed, 5711 insertions(+), 29 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/include/mach/pcie.h
create mode 100644 arch/arm/mach-spear13xx/include/mach/suspend.h
create mode 100644 arch/arm/mach-spear13xx/pcie.c
create mode 100644 arch/arm/mach-spear13xx/pm.c
create mode 100644 arch/arm/mach-spear13xx/sleep.S
create mode 100644 arch/arm/mach-spear3xx/emi.c
create mode 100644 arch/arm/mach-spear3xx/include/mach/emi.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/suspend.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/suspend.h
create mode 100644 arch/arm/plat-spear/i2c_eval_board.c
create mode 100644 arch/arm/plat-spear/include/plat/spi.h
create mode 100644 arch/arm/plat-spear/plgpio.c
create mode 100644 arch/arm/plat-spear/pm.c
create mode 100644 arch/arm/plat-spear/pwm.c
create mode 100644 arch/arm/plat-spear/sleep.S
--
1.7.2.2
^ permalink raw reply
* [PATCH V6 01/17] ST SPEAr13xx: Added ARM PL061 GPIO Support
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977727.git.viresh.kumar@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
---
arch/arm/mach-spear13xx/include/mach/generic.h | 1 +
arch/arm/mach-spear13xx/include/mach/gpio.h | 18 +++++++++++
arch/arm/mach-spear13xx/include/mach/irqs.h | 10 +++++-
arch/arm/mach-spear13xx/spear1300_evb.c | 2 +
arch/arm/mach-spear13xx/spear1310_evb.c | 2 +
arch/arm/mach-spear13xx/spear13xx.c | 38 ++++++++++++++++++++++++
6 files changed, 70 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index a75de93..de9de17 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -221,6 +221,7 @@ extern struct pmx_dev pmx_uart1_modem;
#define SPEAR_GPT0_CHAN1_IRQ IRQ_GPT0_TMR1
/* Add spear13xx family device structure declarations here */
+extern struct amba_device spear13xx_gpio_device[];
extern struct amba_device spear13xx_uart_device;
extern struct sys_timer spear13xx_timer;
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
index 43fa541..2f8ad23 100644
--- a/arch/arm/mach-spear13xx/include/mach/gpio.h
+++ b/arch/arm/mach-spear13xx/include/mach/gpio.h
@@ -16,4 +16,22 @@
#include <plat/gpio.h>
+#define GPIO0_0 0
+#define GPIO0_1 1
+#define GPIO0_2 2
+#define GPIO0_3 3
+#define GPIO0_4 4
+#define GPIO0_5 5
+#define GPIO0_6 6
+#define GPIO0_7 7
+
+#define GPIO1_0 8
+#define GPIO1_1 9
+#define GPIO1_2 10
+#define GPIO1_3 11
+#define GPIO1_4 12
+#define GPIO1_5 13
+#define GPIO1_6 14
+#define GPIO1_7 15
+
#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
index c175175..c4f0c9d 100644
--- a/arch/arm/mach-spear13xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -123,6 +123,14 @@
#define IRQ_GIC_END (IRQ_SHPI_START + 128)
-#define NR_IRQS IRQ_GIC_END
+#define VIRQ_START IRQ_GIC_END
+
+/* GPIO pins virtual irqs */
+#define SPEAR_GPIO0_INT_BASE (VIRQ_START + 0)
+#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8)
+#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8)
+
+#define VIRQ_END SPEAR_GPIO_INT_END
+#define NR_IRQS VIRQ_END
#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index 2e966cf..cba0fee 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -37,6 +37,8 @@ static struct pmx_dev *pmx_devs[] = {
};
static struct amba_device *amba_devs[] __initdata = {
+ &spear13xx_gpio_device[0],
+ &spear13xx_gpio_device[1],
&spear13xx_uart_device,
};
diff --git a/arch/arm/mach-spear13xx/spear1310_evb.c b/arch/arm/mach-spear13xx/spear1310_evb.c
index 42625c8..62af911 100644
--- a/arch/arm/mach-spear13xx/spear1310_evb.c
+++ b/arch/arm/mach-spear13xx/spear1310_evb.c
@@ -44,6 +44,8 @@ static struct pmx_dev *pmx_devs[] = {
static struct amba_device *amba_devs[] __initdata = {
/* spear13xx specific devices */
+ &spear13xx_gpio_device[0],
+ &spear13xx_gpio_device[1],
&spear13xx_uart_device,
/* spear1310 specific devices */
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 7832c1a..35582a6 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -12,6 +12,7 @@
*/
#include <linux/types.h>
+#include <linux/amba/pl061.h>
#include <linux/ptrace.h>
#include <linux/io.h>
#include <asm/hardware/gic.h>
@@ -25,6 +26,43 @@
#include <mach/irqs.h>
/* Add spear13xx machines common devices here */
+/* gpio device registeration */
+static struct pl061_platform_data gpio_plat_data[] = {
+ {
+ .gpio_base = 0,
+ .irq_base = SPEAR_GPIO0_INT_BASE,
+ }, {
+ .gpio_base = 8,
+ .irq_base = SPEAR_GPIO1_INT_BASE,
+ },
+};
+
+struct amba_device spear13xx_gpio_device[] = {
+ {
+ .dev = {
+ .init_name = "gpio0",
+ .platform_data = &gpio_plat_data[0],
+ },
+ .res = {
+ .start = SPEAR13XX_GPIO0_BASE,
+ .end = SPEAR13XX_GPIO0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_GPIO0, NO_IRQ},
+ }, {
+ .dev = {
+ .init_name = "gpio1",
+ .platform_data = &gpio_plat_data[1],
+ },
+ .res = {
+ .start = SPEAR13XX_GPIO1_BASE,
+ .end = SPEAR13XX_GPIO1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_GPIO1, NO_IRQ},
+ }
+};
+
/* uart device registeration */
struct amba_device spear13xx_uart_device = {
.dev = {
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 02/17] ST SPEAr13xx: Added PCIe host controller base driver support.
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977727.git.viresh.kumar@st.com>
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr13xx family contains Synopsys designware PCIe version 3.30a. This
patch adds support for this PCIe module for spear platform.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: shiraz hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-spear13xx/Makefile | 1 +
arch/arm/mach-spear13xx/include/mach/hardware.h | 7 +
arch/arm/mach-spear13xx/include/mach/irqs.h | 19 +-
arch/arm/mach-spear13xx/include/mach/pcie.h | 170 +++++
arch/arm/mach-spear13xx/pcie.c | 861 +++++++++++++++++++++++
arch/arm/mach-spear13xx/spear1300_evb.c | 31 +
arch/arm/mach-spear13xx/spear1310_evb.c | 31 +
arch/arm/mach-spear13xx/spear13xx.c | 28 +
arch/arm/plat-spear/Kconfig | 2 +
10 files changed, 1150 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-spear13xx/include/mach/pcie.h
create mode 100644 arch/arm/mach-spear13xx/pcie.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d9efe86..0aca70d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1263,6 +1263,7 @@ config PCI_HOST_ITE8152
select DMABOUNCE
source "drivers/pci/Kconfig"
+source "drivers/pci/pcie/Kconfig"
source "drivers/pcmcia/Kconfig"
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
index 24bbe16..2a113b0 100644
--- a/arch/arm/mach-spear13xx/Makefile
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -7,6 +7,7 @@ obj-y += spear13xx.o clock.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
+obj-$(CONFIG_PCIEPORTBUS) += pcie.o
# spear1300 specific files
obj-$(CONFIG_MACH_SPEAR1300) += spear1300.o
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
index fd8c2dc..c3fb454 100644
--- a/arch/arm/mach-spear13xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear13xx/include/mach/hardware.h
@@ -28,4 +28,11 @@
/* typesafe io address */
#define __io_address(n) __io(IO_ADDRESS(n))
+#if defined(CONFIG_PCI)
+#define PCIBIOS_MIN_IO 0
+#define PCIBIOS_MIN_MEM 0
+#define pcibios_assign_all_busses() 0
+#endif
+
+
#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
index c4f0c9d..59bf61a 100644
--- a/arch/arm/mach-spear13xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -130,7 +130,24 @@
#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8)
#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8)
-#define VIRQ_END SPEAR_GPIO_INT_END
+/* PCIE MSI virtual irqs */
+#define SPEAR_NUM_MSI_IRQS 64
+#define SPEAR_MSI0_INT_BASE (SPEAR_GPIO_INT_END + 0)
+#define SPEAR_MSI0_INT_END (SPEAR_MSI0_INT_BASE + SPEAR_NUM_MSI_IRQS)
+#define SPEAR_MSI1_INT_BASE (SPEAR_MSI0_INT_END + 0)
+#define SPEAR_MSI1_INT_END (SPEAR_MSI1_INT_BASE + SPEAR_NUM_MSI_IRQS)
+#define SPEAR_MSI2_INT_BASE (SPEAR_MSI1_INT_END + 0)
+#define SPEAR_MSI2_INT_END (SPEAR_MSI2_INT_BASE + SPEAR_NUM_MSI_IRQS)
+
+#define SPEAR_NUM_INTX_IRQS 4
+#define SPEAR_INTX0_BASE (SPEAR_MSI2_INT_END + 0)
+#define SPEAR_INTX0_END (SPEAR_INTX0_BASE + SPEAR_NUM_INTX_IRQS)
+#define SPEAR_INTX1_BASE (SPEAR_INTX0_END + 0)
+#define SPEAR_INTX1_END (SPEAR_INTX1_BASE + SPEAR_NUM_INTX_IRQS)
+#define SPEAR_INTX2_BASE (SPEAR_INTX1_END + 0)
+#define SPEAR_INTX2_END (SPEAR_INTX2_BASE + SPEAR_NUM_INTX_IRQS)
+
+#define VIRQ_END SPEAR_INTX2_END
#define NR_IRQS VIRQ_END
#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/pcie.h b/arch/arm/mach-spear13xx/include/mach/pcie.h
new file mode 100644
index 0000000..fa302e5
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/pcie.h
@@ -0,0 +1,170 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/pcie.h
+ *
+ * Spear SoC PCIe handling.
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_PCIE_H
+#define __MACH_PCIE_H
+
+extern int (*pcie_port_is_host)(int port);
+extern int enable_pcie0_clk(void);
+
+
+struct pcie_port {
+ u8 port;
+ u8 root_bus_nr;
+ void __iomem *base;
+ void __iomem *app_base;
+ void __iomem *va_app_base;
+ void __iomem *va_dbi_base;
+ void __iomem *va_cfg0_base;
+ spinlock_t conf_lock;
+ char mem_space_name[16];
+ char io_space_name[16];
+ struct resource res[2];
+};
+
+struct pcie_app_reg {
+ u32 app_ctrl_0; /*cr0*/
+ u32 app_ctrl_1; /*cr1*/
+ u32 app_status_0; /*cr2*/
+ u32 app_status_1; /*cr3*/
+ u32 msg_status; /*cr4*/
+ u32 msg_payload; /*cr5*/
+ u32 int_sts; /*cr6*/
+ u32 int_clr; /*cr7*/
+ u32 int_mask; /*cr8*/
+ u32 mst_bmisc; /*cr9*/
+ u32 phy_ctrl; /*cr10*/
+ u32 phy_status; /*cr11*/
+ u32 cxpl_debug_info_0; /*cr12*/
+ u32 cxpl_debug_info_1; /*cr13*/
+ u32 ven_msg_ctrl_0; /*cr14*/
+ u32 ven_msg_ctrl_1; /*cr15*/
+ u32 ven_msg_data_0; /*cr16*/
+ u32 ven_msg_data_1; /*cr17*/
+ u32 ven_msi_0; /*cr18*/
+ u32 ven_msi_1; /*cr19*/
+ u32 mst_rmisc; /*cr 20*/
+ u32 slv_awmisc; /*cr 21*/
+ u32 slv_armisc; /*cr 22*/
+ u32 pom0_mem_addr_start; /*cr23*/
+ u32 pom1_mem_addr_start; /*cr24*/
+ u32 pom_io_addr_start; /*cr25*/
+ u32 pom_cfg0_addr_start; /*cr26*/
+ u32 pom_cfg1_addr_start; /*cr27*/
+ u32 in0_mem_addr_start; /*cr28*/
+ u32 in1_mem_addr_start; /*cr29*/
+ u32 in_io_addr_start; /*cr30*/
+ u32 in_cfg0_addr_start; /*cr31*/
+ u32 in_cfg1_addr_start; /*cr32*/
+ u32 in_msg_addr_start; /*cr33*/
+ u32 in0_mem_addr_limit; /*cr34*/
+ u32 in1_mem_addr_limit; /*cr35*/
+ u32 in_io_addr_limit; /*cr36*/
+ u32 in_cfg0_addr_limit; /*cr37*/
+ u32 in_cfg1_addr_limit; /*cr38*/
+ u32 in_msg_addr_limit; /*cr39*/
+ u32 mem0_addr_offset_limit; /*cr40*/
+ u32 pim0_mem_addr_start; /*cr41*/
+ u32 pim1_mem_addr_start; /*cr42*/
+ u32 pim_io_addr_start; /*cr43*/
+ u32 pim_rom_addr_start; /*cr44*/
+};
+
+/*CR0 ID*/
+#define RX_LANE_FLIP_EN_ID 0
+#define TX_LANE_FLIP_EN_ID 1
+#define SYS_AUX_PWR_DET_ID 2
+#define APP_LTSSM_ENABLE_ID 3
+#define SYS_ATTEN_BUTTON_PRESSED_ID 4
+#define SYS_MRL_SENSOR_STATE_ID 5
+#define SYS_PWR_FAULT_DET_ID 6
+#define SYS_MRL_SENSOR_CHGED_ID 7
+#define SYS_PRE_DET_CHGED_ID 8
+#define SYS_CMD_CPLED_INT_ID 9
+#define APP_INIT_RST_0_ID 11
+#define APP_REQ_ENTR_L1_ID 12
+#define APP_READY_ENTR_L23_ID 13
+#define APP_REQ_EXIT_L1_ID 14
+#define DEVICE_TYPE_EP (0 << 25)
+#define DEVICE_TYPE_LEP (1 << 25)
+#define DEVICE_TYPE_RC (4 << 25)
+#define SYS_INT_ID 29
+#define MISCTRL_EN_ID 30
+#define REG_TRANSLATION_ENABLE 31
+
+/*CR1 ID*/
+#define APPS_PM_XMT_TURNOFF_ID 2
+#define APPS_PM_XMT_PME_ID 5
+
+/*CR3 ID*/
+#define XMLH_LTSSM_STATE_ID 0
+#define XMLH_LTSSM_STATE_L0 ((u32)0x11 << XMLH_LTSSM_STATE_ID)
+#define XMLH_LTSSM_STATE_MASK ((u32)0x1F << XMLH_LTSSM_STATE_ID)
+#define XMLH_LINK_UP_ID 5
+
+/*CR4 ID*/
+#define CFG_MSI_EN_ID 18
+
+/*CR6*/
+#define INTA_CTRL_INT (1 << 7)
+#define INTB_CTRL_INT (1 << 8)
+#define INTC_CTRL_INT (1 << 9)
+#define INTD_CTRL_INT (1 << 10)
+#define MSI_CTRL_INT (1 << 26)
+
+/*CR19 ID*/
+#define VEN_MSI_REQ_ID 11
+#define VEN_MSI_FUN_NUM_ID 8
+#define VEN_MSI_TC_ID 5
+#define VEN_MSI_VECTOR_ID 0
+#define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID)
+#define VEN_MSI_FUN_NUM_MASK ((u32)0x7 << VEN_MSI_FUN_NUM_ID)
+#define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID)
+#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
+#endif
+
+/*CE21-22 ID*/
+/*ID definitio of ARMISC*/
+#define AXI_OP_TYPE_ID 0
+#define AXI_OP_BCM_ID 5
+#define AXI_OP_EP_ID 6
+#define AXI_OP_TD_ID 7
+#define AXI_OP_ATTRIBUTE_ID 8
+#define AXI_OP_TC_ID 10
+#define AXI_OP_MSG_CODE_ID 13
+#define AXI_OP_DBI_ACCESS_ID 21
+#define AXI_OP_TYPE_MASK 0x1F
+#define AXI_OP_TYPE_MEM_RDRW 0
+#define AXI_OP_TYPE_MEM_RDRW_LOCKED 1
+#define AXI_OP_TYPE_IO_RDRW 2
+#define AXI_OP_TYPE_CONFIG_RDRW_TYPE0 4
+#define AXI_OP_TYPE_CONFIG_RDRW_TYPE1 5
+#define AXI_OP_TYPE_MSG_REQ 16
+#define AXI_OP_TYPE_COMPLETION 10
+#define AXI_OP_TYPE_COMPLETION_LOCKED 11
+#define AXI_OP_TYPE_DBI_ELBI_ENABLE 1
+
+/* synopsis specific PCIE configuration registers*/
+#define PCIE_MSI_ADDR_LO 0x820 /* 32 bits */
+#define PCIE_MSI_ADDR_HI 0x824 /* 32 bits */
+#define PCIE_MSI_INTR0_ENABLE 0x828 /* 32 bits */
+#define PCIE_MSI_INTR0_MASK 0x82C /* 32 bits */
+#define PCIE_MSI_INTR0_STATUS 0x830 /* 32 bits */
+
+/*BAR MASK registers*/
+#define PCIE_BAR0_MASK_REG 0x1010
+
+static inline void pcie_init(int (*fptr)(int port))
+{
+ pcie_port_is_host = fptr;
+}
diff --git a/arch/arm/mach-spear13xx/pcie.c b/arch/arm/mach-spear13xx/pcie.c
new file mode 100644
index 0000000..3528830
--- /dev/null
+++ b/arch/arm/mach-spear13xx/pcie.c
@@ -0,0 +1,861 @@
+/*
+ * arch/arm/mach-spear13xx/pcie.c
+ *
+ * PCIe functions for SPEAr 13xx SoCs
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/msi.h>
+#include <linux/mbus.h>
+#include <linux/sched.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/pci.h>
+#include <mach/misc_regs.h>
+#include <mach/pcie.h>
+
+#define NUM_PCIE_PORTS 3
+
+/* Sum of all these space can maximum be 256MB*/
+#define IN0_MEM_SIZE (200 * 1024 * 1024 - 1)
+/* In current implementation address translation is done using IN0 only.
+ * So IN1 start address and IN0 end address has been kept same
+*/
+#define IN1_MEM_SIZE (0 * 1024 * 1024 - 1)
+#define IN_IO_SIZE (20 * 1024 * 1024 - 1)
+#define IN_CFG0_SIZE (1 * 1024 * 1024 - 1)
+#define IN_CFG1_SIZE (1 * 1024 * 1024 - 1)
+#define IN_MSG_SIZE (1 * 1024 * 1024 - 1)
+
+#define MAX_LINK_UP_WAIT_JIFFIES 10
+
+int (*pcie_port_is_host)(int port);
+static struct pcie_port pcie_port[NUM_PCIE_PORTS];
+static u32 spr_pcie_base[NUM_PCIE_PORTS] = {
+ SPEAR13XX_PCIE0_BASE,
+ SPEAR13XX_PCIE1_BASE,
+ SPEAR13XX_PCIE2_BASE,
+};
+static u32 spr_pcie_app_base[NUM_PCIE_PORTS] = {
+ SPEAR13XX_PCIE0_APP_BASE,
+ SPEAR13XX_PCIE1_APP_BASE,
+ SPEAR13XX_PCIE2_APP_BASE,
+};
+
+/* Keeping all DDR area of 256MB accesible for inbound transaction */
+#define INBOUND_ADDR_MASK 0xFFFFFFF
+
+#ifdef CONFIG_PCI_MSI
+static DECLARE_BITMAP(msi_irq_in_use[NUM_PCIE_PORTS], SPEAR_NUM_MSI_IRQS);
+static unsigned int spear_msi_data[NUM_PCIE_PORTS];
+
+static void spear13xx_msi_init(struct pcie_port *pp);
+#endif
+
+static void spear_pcie_int_handler(unsigned int irq, struct irq_desc *desc);
+
+static void enable_dbi_access(struct pcie_app_reg *app_reg)
+{
+ /* Enable DBI access */
+ writel(readl(&app_reg->slv_armisc) | (1 << AXI_OP_DBI_ACCESS_ID),
+ &app_reg->slv_armisc);
+ writel(readl(&app_reg->slv_awmisc) | (1 << AXI_OP_DBI_ACCESS_ID),
+ &app_reg->slv_awmisc);
+
+}
+
+static void disable_dbi_access(struct pcie_app_reg *app_reg)
+{
+ /* disable DBI access */
+ writel(readl(&app_reg->slv_armisc) & ~(1 << AXI_OP_DBI_ACCESS_ID),
+ &app_reg->slv_armisc);
+ writel(readl(&app_reg->slv_awmisc) & ~(1 << AXI_OP_DBI_ACCESS_ID),
+ &app_reg->slv_awmisc);
+
+}
+
+static void spear_dbi_read_reg(struct pcie_port *pp, int where, int size,
+ u32 *val)
+{
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *) pp->va_app_base;
+ u32 va_address;
+
+ /* Enable DBI access */
+ enable_dbi_access(app_reg);
+
+ va_address = (u32)pp->va_dbi_base + (where & ~0x3);
+
+ *val = readl(va_address);
+
+ if (size == 1)
+ *val = (*val >> (8 * (where & 3))) & 0xff;
+ else if (size == 2)
+ *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+ /* Disable DBI access */
+ disable_dbi_access(app_reg);
+}
+
+static void spear_dbi_write_reg(struct pcie_port *pp, int where, int size,
+ u32 val)
+{
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *) pp->va_app_base;
+ u32 va_address;
+
+ /* Enable DBI access */
+ enable_dbi_access(app_reg);
+
+ va_address = (u32)pp->va_dbi_base + (where & ~0x3);
+
+ if (size == 4)
+ writel(val, va_address);
+ else if (size == 2)
+ writew(val, va_address + (where & 2));
+ else if (size == 1)
+ writeb(val, va_address + (where & 3));
+
+ /* Disable DBI access */
+ disable_dbi_access(app_reg);
+}
+
+static int spear13xx_pcie_link_up(void __iomem *va_app_base)
+{
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *) va_app_base;
+ unsigned long deadline = jiffies + MAX_LINK_UP_WAIT_JIFFIES;
+
+ do {
+ if (readl(&app_reg->app_status_1) &
+ ((u32)1 << XMLH_LINK_UP_ID))
+ return 1;
+
+ cond_resched();
+ } while (!time_after_eq(jiffies, deadline));
+
+ return 0;
+}
+
+static void spear13xx_pcie_host_init(struct pcie_port *pp)
+{
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *)pp->va_app_base;
+
+ /*setup registers for outbound translation */
+
+ writel(pp->base, &app_reg->in0_mem_addr_start);
+ writel(app_reg->in0_mem_addr_start + IN0_MEM_SIZE,
+ &app_reg->in0_mem_addr_limit);
+ writel(app_reg->in0_mem_addr_limit + 1, &app_reg->in1_mem_addr_start);
+ writel(app_reg->in1_mem_addr_start + IN1_MEM_SIZE,
+ &app_reg->in1_mem_addr_limit);
+ writel(app_reg->in1_mem_addr_limit + 1, &app_reg->in_io_addr_start);
+ writel(app_reg->in_io_addr_start + IN_IO_SIZE,
+ &app_reg->in_io_addr_limit);
+ writel(app_reg->in_io_addr_limit + 1, &app_reg->in_cfg0_addr_start);
+ writel(app_reg->in_cfg0_addr_start + IN_CFG0_SIZE,
+ &app_reg->in_cfg0_addr_limit);
+ writel(app_reg->in_cfg0_addr_limit + 1, &app_reg->in_cfg1_addr_start);
+ writel(app_reg->in_cfg1_addr_start + IN_CFG1_SIZE,
+ &app_reg->in_cfg1_addr_limit);
+ writel(app_reg->in_cfg1_addr_limit + 1, &app_reg->in_msg_addr_start);
+ writel(app_reg->in_msg_addr_start + IN_MSG_SIZE,
+ &app_reg->in_msg_addr_limit);
+
+ writel(app_reg->in0_mem_addr_start, &app_reg->pom0_mem_addr_start);
+ writel(app_reg->in1_mem_addr_start, &app_reg->pom1_mem_addr_start);
+ writel(app_reg->in_io_addr_start, &app_reg->pom_io_addr_start);
+
+ /*setup registers for inbound translation */
+
+ writel(INBOUND_ADDR_MASK + 1, &app_reg->mem0_addr_offset_limit);
+ writel(0, &app_reg->pim0_mem_addr_start);
+ writel(0, &app_reg->pim1_mem_addr_start);
+ spear_dbi_write_reg(pp, PCIE_BAR0_MASK_REG, 4, INBOUND_ADDR_MASK);
+ spear_dbi_write_reg(pp, PCI_BASE_ADDRESS_0, 4, 0);
+
+ writel(0x0, &app_reg->pim_io_addr_start);
+ writel(0x0, &app_reg->pim_io_addr_start);
+ writel(0x0, &app_reg->pim_rom_addr_start);
+
+ writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
+ | (1 << APP_LTSSM_ENABLE_ID)
+ | ((u32)1 << REG_TRANSLATION_ENABLE),
+ &app_reg->app_ctrl_0);
+}
+
+static void __init spear13xx_pcie_preinit(void)
+{
+ int i;
+ struct pcie_port *pp;
+ struct pcie_app_reg *app_reg;
+
+ for (i = 0; i < NUM_PCIE_PORTS; i++) {
+ pp = pcie_port + i;
+ app_reg = (struct pcie_app_reg *) (pp->va_app_base);
+
+ /* init hosts only */
+ if ((*pcie_port_is_host)(i) != 1)
+ continue;
+ snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
+ "PCIe %d MEM", pp->port);
+ pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
+ pp->res[0].name = pp->mem_space_name;
+ pp->res[0].start = app_reg->in0_mem_addr_start;
+ pp->res[0].end = app_reg->in0_mem_addr_limit;
+ pp->res[0].flags = IORESOURCE_MEM;
+
+ snprintf(pp->io_space_name, sizeof(pp->io_space_name),
+ "PCIe %d I/O", pp->port);
+ pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
+ pp->res[1].name = pp->io_space_name;
+ pp->res[1].start = app_reg->in_io_addr_start;
+ pp->res[1].end = app_reg->in_io_addr_limit;
+ pp->res[1].flags = IORESOURCE_IO;
+
+ if (request_resource(&iomem_resource, &pp->res[0]))
+ panic("can't allocate PCIe I/O space");
+ if (request_resource(&iomem_resource, &pp->res[1]))
+ panic("can't allocate PCIe MEM space");
+ }
+}
+
+static int __init spear13xx_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+ struct pcie_port *pp;
+ u32 val = 0;
+
+ if (nr >= NUM_PCIE_PORTS)
+ return 0;
+
+ if ((*pcie_port_is_host)(nr) != 1)
+ return 0;
+
+ pp = &pcie_port[nr];
+ if (!spear13xx_pcie_link_up((void __iomem *)pp->va_app_base))
+ return 0;
+ pp->root_bus_nr = sys->busnr;
+
+ /* Generic PCIe unit setup.*/
+
+ /* Enable own BME. It is necessary to enable own BME to do a
+ * memory transaction on a downstream device
+ */
+ spear_dbi_read_reg(pp, PCI_COMMAND, 2, &val);
+ val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
+ spear_dbi_write_reg(pp, PCI_COMMAND, 2, val);
+
+ /* Need to come back here*/
+
+ sys->resource[0] = &pp->res[0];
+ sys->resource[1] = &pp->res[1];
+ sys->resource[2] = NULL;
+
+ return 1;
+}
+
+static struct pcie_port *bus_to_port(int bus)
+{
+ int i;
+
+ for (i = NUM_PCIE_PORTS - 1; i >= 0; i--) {
+ int rbus = pcie_port[i].root_bus_nr;
+ if ((*pcie_port_is_host)(i) != 1)
+ continue;
+ if (rbus != -1 && rbus <= bus)
+ break;
+ }
+
+ return i >= 0 ? pcie_port + i : NULL;
+}
+
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
+{
+ /*If there is no link, then there is no device*/
+ if (!spear13xx_pcie_link_up((void __iomem *)pp->va_app_base))
+ return 0;
+ /*
+ * Don't go out when trying to access nonexisting devices
+ * on the local bus.
+ * we have only one slot on each root port.
+ */
+ if (bus == pp->root_bus_nr && dev > 0)
+ return 0;
+ return 1;
+}
+
+static int spear13xx_pcie_rd_conf(struct pcie_port *pp, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val)
+{
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *) pp->va_app_base;
+ u32 address = (u32)pp->va_cfg0_base | (PCI_FUNC(devfn) << 16)
+ | (where & 0xFFFC);
+
+ writel((bus->number << 24) | (PCI_SLOT(devfn) << 19),
+ &app_reg->pom_cfg0_addr_start);
+ writel(readl(&app_reg->slv_armisc) & ~(AXI_OP_TYPE_MASK),
+ &app_reg->slv_armisc);
+ writel(readl(&app_reg->slv_armisc) | AXI_OP_TYPE_CONFIG_RDRW_TYPE0,
+ &app_reg->slv_armisc);
+
+ *val = readl(address);
+ if (size == 1)
+ *val = (*val >> (8 * (where & 3))) & 0xff;
+ else if (size == 2)
+ *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+ writel(readl(&app_reg->slv_armisc) & ~(AXI_OP_TYPE_MASK),
+ &app_reg->slv_armisc);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+ int size, u32 *val)
+{
+ struct pcie_port *pp = bus_to_port(bus->number);
+ unsigned long flags;
+ int ret;
+
+ if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
+ *val = 0xffffffff;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ spin_lock_irqsave(&pp->conf_lock, flags);
+ ret = spear13xx_pcie_rd_conf(pp, bus, devfn, where, size, val);
+ spin_unlock_irqrestore(&pp->conf_lock, flags);
+
+ return ret;
+}
+
+static int spear13xx_pcie_wr_conf(struct pcie_port *pp, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 val)
+{
+ int ret = PCIBIOS_SUCCESSFUL;
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *) pp->va_app_base;
+ u32 address = (u32)pp->va_cfg0_base | (PCI_FUNC(devfn) << 16)
+ | (where & 0xFFFC);
+
+ writel((bus->number << 24) | (PCI_SLOT(devfn) << 19),
+ &app_reg->pom_cfg0_addr_start);
+ writel(readl(&app_reg->slv_awmisc) & ~(AXI_OP_TYPE_MASK),
+ &app_reg->slv_awmisc);
+ writel(readl(&app_reg->slv_awmisc) | AXI_OP_TYPE_CONFIG_RDRW_TYPE0,
+ &app_reg->slv_awmisc);
+ if (size == 4)
+ writel(val, address);
+ else if (size == 2)
+ writew(val, address + (where & 2));
+ else if (size == 1)
+ writeb(val, address + (where & 3));
+ else
+ ret = PCIBIOS_BAD_REGISTER_NUMBER;
+ writel(readl(&app_reg->slv_awmisc) & ~(AXI_OP_TYPE_MASK),
+ &app_reg->slv_awmisc);
+ return ret;
+}
+
+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+ int where, int size, u32 val)
+{
+ struct pcie_port *pp = bus_to_port(bus->number);
+ unsigned long flags;
+ int ret;
+
+ if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ spin_lock_irqsave(&pp->conf_lock, flags);
+ ret = spear13xx_pcie_wr_conf(pp, bus, devfn, where, size, val);
+ spin_unlock_irqrestore(&pp->conf_lock, flags);
+
+ return ret;
+}
+
+static struct pci_ops pcie_ops = {
+ .read = pcie_rd_conf,
+ .write = pcie_wr_conf,
+};
+
+static struct pci_bus __init *
+spear13xx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+ struct pci_bus *bus;
+
+ if ((nr < NUM_PCIE_PORTS) && ((*pcie_port_is_host)(nr)) == 1) {
+ bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+ } else {
+ bus = NULL;
+ BUG();
+ }
+
+ return bus;
+}
+
+static int __init spear13xx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ struct pcie_port *pp = bus_to_port(dev->bus->number);
+ int irq = (SPEAR_INTX0_BASE + pp->port * SPEAR_NUM_INTX_IRQS + pin - 1);
+
+ return irq;
+}
+
+static struct hw_pci spear13xx_pci __initdata = {
+ .nr_controllers = NUM_PCIE_PORTS,
+ .preinit = spear13xx_pcie_preinit,
+ .swizzle = pci_std_swizzle,
+ .setup = spear13xx_pcie_setup,
+ .scan = spear13xx_pcie_scan_bus,
+ .map_irq = spear13xx_pcie_map_irq,
+};
+
+void mask_intx_irq(unsigned int irq)
+{
+ int irq_offset = (irq - SPEAR_INTX0_BASE) % SPEAR_NUM_INTX_IRQS;
+ int port = (irq - SPEAR_INTX0_BASE) / SPEAR_NUM_INTX_IRQS;
+ struct pcie_port *pp = &pcie_port[port];
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *)pp->va_app_base;
+
+ switch (irq_offset) {
+ case 0:
+ writel(readl(&app_reg->int_mask) & ~INTA_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ case 1:
+ writel(readl(&app_reg->int_mask) & ~INTB_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ case 2:
+ writel(readl(&app_reg->int_mask) & ~INTC_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ case 3:
+ writel(readl(&app_reg->int_mask) & ~INTD_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ }
+}
+
+void unmask_intx_irq(unsigned int irq)
+{
+ int irq_offset = (irq - SPEAR_INTX0_BASE) % SPEAR_NUM_INTX_IRQS;
+ int port = (irq - SPEAR_INTX0_BASE) / SPEAR_NUM_INTX_IRQS;
+ struct pcie_port *pp = &pcie_port[port];
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *)pp->va_app_base;
+
+ switch (irq_offset) {
+ case 0:
+ writel(readl(&app_reg->int_mask) | INTA_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ case 1:
+ writel(readl(&app_reg->int_mask) | INTB_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ case 2:
+ writel(readl(&app_reg->int_mask) | INTC_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ case 3:
+ writel(readl(&app_reg->int_mask) | INTD_CTRL_INT,
+ &app_reg->int_mask);
+ break;
+ }
+}
+
+static struct irq_chip spear13xx_intx_chip = {
+ .name = "PCI-INTX",
+ .mask = mask_intx_irq,
+ .unmask = unmask_intx_irq,
+};
+
+static void spear13xx_int_init(struct pcie_port *pp)
+{
+ int i, irq;
+ struct pcie_app_reg *app_reg;
+
+ set_irq_chained_handler(IRQ_PCIE0 + pp->port, spear_pcie_int_handler);
+
+#ifdef CONFIG_PCI_MSI
+ spear13xx_msi_init(pp);
+#endif
+ /* Enbale INTX interrupt*/
+ app_reg = (struct pcie_app_reg *)pp->va_app_base;
+ writel(readl(&app_reg->int_mask) | INTA_CTRL_INT
+ | INTB_CTRL_INT | INTC_CTRL_INT
+ | INTD_CTRL_INT, &app_reg->int_mask);
+
+ /* initilize INTX chip here only. MSI chip will be
+ * initilized dynamically.*/
+ irq = (SPEAR_INTX0_BASE + pp->port * SPEAR_NUM_INTX_IRQS);
+ for (i = 0; i < SPEAR_NUM_INTX_IRQS; i++) {
+ set_irq_chip_and_handler(irq + i, &spear13xx_intx_chip,
+ handle_simple_irq);
+ set_irq_flags(irq + i, IRQF_VALID);
+ }
+}
+
+static void __init add_pcie_port(int port, u32 base, u32 app_base)
+{
+ struct pcie_port *pp = &pcie_port[port];
+ struct pcie_app_reg *app_reg;
+
+ pp->port = port;
+ pp->root_bus_nr = -1;
+ pp->base = (void __iomem *)base;
+ pp->app_base = (void __iomem *)app_base;
+ pp->va_app_base = (void __iomem *) ioremap(app_base, 0x200);
+ if (!pp->va_app_base) {
+ pr_err("error with ioremap in function %s\n", __func__);
+ return;
+ }
+ pp->va_dbi_base = (void __iomem *) ioremap(base, 0x2000);
+ if (!pp->va_dbi_base) {
+ pr_err("error with ioremap in function %s\n", __func__);
+ return;
+ }
+ spin_lock_init(&pp->conf_lock);
+ memset(pp->res, 0, sizeof(pp->res));
+ pr_info("spear13xx PCIe port %d\n", port);
+ if (spear13xx_pcie_link_up((void __iomem *)pp->va_app_base)) {
+ pr_info("link up in bios\n");
+ } else {
+ pr_info("link down in bios\n");
+ spear13xx_pcie_host_init(pp);
+ spear13xx_int_init(pp);
+ app_reg = (struct pcie_app_reg *)pp->va_app_base;
+ pp->va_cfg0_base = (void __iomem *)
+ ioremap(app_reg->in_cfg0_addr_start, IN_CFG0_SIZE);
+ if (!pp->va_cfg0_base) {
+ pr_err("error with ioremap in function %s\n", __func__);
+ return;
+ }
+
+ }
+}
+
+static int __init spear13xx_pcie_init(void)
+{
+ int port;
+ struct clk *clk;
+
+ for (port = 0; port < NUM_PCIE_PORTS; port++) {
+ /* do not enable clock if it is PCIE0. Ideally , all controller
+ * should have been independent from others with respect to
+ * clock. But PCIE1 and 2 depends on PCIE0.So PCIE0 clk
+ * is provided during board init.*/
+ if (port == 1) {
+ /* Ideally CFG Clock should have been also enabled
+ * here. But it is done currently during board
+ * init routne*/
+ clk = clk_get_sys("pcie1", NULL);
+ if (IS_ERR(clk)) {
+ pr_err("%s:couldn't get clk for pcie1\n",
+ __func__);
+ continue;
+ }
+ if (clk_enable(clk)) {
+ pr_err("%s:couldn't enable clk for pcie1\n",
+ __func__);
+ continue;
+ }
+ } else if (port == 2) {
+ /* Ideally CFG Clock should have been also enabled
+ * here. But it is done currently during board
+ * init routne*/
+ clk = clk_get_sys("pcie2", NULL);
+ if (IS_ERR(clk)) {
+ pr_err("%s:couldn't get clk for pcie2\n",
+ __func__);
+ continue;
+ }
+ if (clk_enable(clk)) {
+ pr_err("%s:couldn't enable clk for pcie2\n",
+ __func__);
+ continue;
+ }
+ }
+
+ if ((*pcie_port_is_host)(port) == 1)
+ add_pcie_port(port, spr_pcie_base[port],
+ spr_pcie_app_base[port]);
+ }
+
+ pci_common_init(&spear13xx_pci);
+
+ return 0;
+}
+subsys_initcall(spear13xx_pcie_init);
+
+#ifdef CONFIG_PCI_MSI
+/* MSI int handler
+ */
+static void handle_msi(struct pcie_port *pp)
+{
+ unsigned long val;
+ int i, pos;
+
+ for (i = 0; i < 8; i++) {
+ spear_dbi_read_reg(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
+ (u32 *)&val);
+ if (val) {
+ pos = 0;
+ while ((pos = find_next_bit(&val, 32, pos)) != 32) {
+ generic_handle_irq(SPEAR_MSI0_INT_BASE
+ + pp->port * SPEAR_NUM_MSI_IRQS
+ + (i * 32) + pos);
+ pos++;
+ }
+ }
+ spear_dbi_write_reg(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, val);
+ }
+}
+#else
+static void handle_msi(struct pcie_port *pp)
+{
+}
+#endif
+
+static void spear_pcie_int_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct pcie_port *pp = &pcie_port[irq - IRQ_PCIE0];
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *)pp->va_app_base;
+ unsigned int status;
+
+ status = readl(&app_reg->int_sts);
+
+ desc->chip->ack(irq);
+
+ if (status & MSI_CTRL_INT) {
+ handle_msi(pp);
+ writel(MSI_CTRL_INT, &app_reg->int_clr);
+ } else if (status & INTA_CTRL_INT)
+ generic_handle_irq(SPEAR_INTX0_BASE
+ + pp->port * SPEAR_NUM_INTX_IRQS);
+ else if (status & INTB_CTRL_INT)
+ generic_handle_irq(SPEAR_INTX0_BASE
+ + pp->port * SPEAR_NUM_INTX_IRQS + 1);
+ else if (status & INTC_CTRL_INT)
+ generic_handle_irq(SPEAR_INTX0_BASE
+ + pp->port * SPEAR_NUM_INTX_IRQS + 2);
+ else if (status & INTD_CTRL_INT)
+ generic_handle_irq(SPEAR_INTX0_BASE
+ + pp->port * SPEAR_NUM_INTX_IRQS + 3);
+ else
+ writel(status, &app_reg->int_clr);
+
+ desc->chip->unmask(irq);
+}
+
+#ifdef CONFIG_PCI_MSI
+static int find_valid_pos0(int port, int nvec, int pos, int *pos0)
+{
+ int flag = 1;
+ do {
+ pos = find_next_zero_bit(msi_irq_in_use[port],
+ SPEAR_NUM_MSI_IRQS, pos);
+ /*if you have reached to the end then get out from here.*/
+ if (pos == SPEAR_NUM_MSI_IRQS)
+ return -ENOSPC;
+ /* Check if this position is at correct offset.nvec is always a
+ * power of two. pos0 must be nvec bit alligned.
+ */
+ if (pos % nvec)
+ pos += nvec - (pos % nvec);
+ else
+ flag = 0;
+ } while (flag);
+
+ *pos0 = pos;
+ return 0;
+}
+
+static void spear13xx_msi_nop(unsigned int irq)
+{
+ return;
+}
+
+static struct irq_chip spear13xx_msi_chip = {
+ .name = "PCI-MSI",
+ .ack = spear13xx_msi_nop,
+ .irq_enable = unmask_msi_irq,
+ .irq_disable = mask_msi_irq,
+ .irq_mask = mask_msi_irq,
+ .irq_unmask = unmask_msi_irq,
+};
+
+/*
+ * Dynamic irq allocate and deallocation
+ */
+static int get_irq(int nvec, struct msi_desc *desc, int *pos)
+{
+ int res, bit, irq, pos0, pos1, i;
+ u32 val;
+ struct pcie_port *pp = bus_to_port(desc->dev->bus->number);
+
+ pos0 = find_first_zero_bit(msi_irq_in_use[pp->port],
+ SPEAR_NUM_MSI_IRQS);
+ if (pos0 % nvec) {
+ if (find_valid_pos0(pp->port, nvec, pos0, &pos0))
+ goto no_valid_irq;
+ }
+ if (nvec > 1) {
+ pos1 = find_next_bit(msi_irq_in_use[pp->port],
+ SPEAR_NUM_MSI_IRQS, pos0);
+ /* there must be nvec number of consecutive free bits */
+ while ((pos1 - pos0) < nvec) {
+ if (find_valid_pos0(pp->port, nvec, pos1, &pos0))
+ goto no_valid_irq;
+ pos1 = find_next_bit(msi_irq_in_use[pp->port],
+ SPEAR_NUM_MSI_IRQS, pos0);
+ }
+ }
+
+ irq = (SPEAR_MSI0_INT_BASE + (pp->port * SPEAR_NUM_MSI_IRQS)) + pos0;
+
+ if ((irq + nvec) > (SPEAR_MSI0_INT_END
+ + (pp->port * SPEAR_NUM_MSI_IRQS)))
+ goto no_valid_irq;
+
+ i = 0;
+ while (i < nvec) {
+ set_bit(pos0 + i, msi_irq_in_use[pp->port]);
+ dynamic_irq_init(irq + i);
+ set_irq_msi(irq + i, desc);
+ set_irq_chip_and_handler(irq + i, &spear13xx_msi_chip,
+ handle_simple_irq);
+
+ /* Enable corresponding interrupt on MSI interrupt
+ * controller.
+ */
+ res = ((pos0 + i) / 32) * 12;
+ bit = (pos0 + i) % 32;
+ spear_dbi_read_reg(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
+ val |= 1 << bit;
+ spear_dbi_write_reg(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
+
+ i++;
+ }
+
+ *pos = pos0;
+ return irq;
+no_valid_irq:
+ *pos = pos0;
+ return -ENOSPC;
+}
+
+static void clean_irq(unsigned int irq)
+{
+ int res, bit, val, pos;
+ struct irq_desc *desc = irq_to_desc(irq);
+ struct pcie_port *pp = bus_to_port(desc->msi_desc->dev->bus->number);
+
+ pos = irq - (SPEAR_MSI0_INT_BASE + (pp->port * SPEAR_NUM_MSI_IRQS));
+
+ dynamic_irq_cleanup(irq);
+
+ clear_bit(pos, msi_irq_in_use[pp->port]);
+
+ /* Disable corresponding interrupt on MSI interrupt
+ * controller.
+ */
+ res = (pos / 32) * 12;
+ bit = pos % 32;
+ spear_dbi_read_reg(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
+ val &= ~(1 << bit);
+ spear_dbi_write_reg(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
+
+}
+
+int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
+{
+ int cvec, rvec, irq, pos;
+ struct msi_msg msg;
+ uint16_t control;
+ struct pcie_port *pp = bus_to_port(pdev->bus->number);
+
+ /*
+ * Read the MSI config to figure out how many IRQs this device
+ * wants.Most devices only want 1, which will give
+ * configured_private_bits and request_private_bits equal 0.
+ */
+ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
+ &control);
+
+ /*
+ * If the number of private bits has been configured then use
+ * that value instead of the requested number. This gives the
+ * driver the chance to override the number of interrupts
+ * before calling pci_enable_msi().
+ */
+
+ cvec = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
+
+ if (cvec == 0) {
+ /* Nothing is configured, so use the hardware requested size */
+ rvec = (control & PCI_MSI_FLAGS_QMASK) >> 1;
+ } else {
+ /*
+ * Use the number of configured bits, assuming the
+ * driver wanted to override the hardware request
+ * value.
+ */
+ rvec = cvec;
+ }
+
+ /*
+ * The PCI 2.3 spec mandates that there are at most 32
+ * interrupts. If this device asks for more, only give it one.
+ */
+ if (rvec > 5)
+ rvec = 0;
+
+ irq = get_irq((1 << rvec), desc, &pos);
+
+ if (irq < 0)
+ return irq;
+
+ /* Update the number of IRQs the device has available to it */
+ control &= ~PCI_MSI_FLAGS_QSIZE;
+ control |= rvec << 4;
+ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
+ control);
+ desc->msi_attrib.multiple = rvec;
+
+ /* An EP will modify lower 8 bits(max) of msi data while
+ * sending any msi interrupt
+ */
+ msg.address_hi = 0x0;
+ msg.address_lo = __virt_to_phys((u32)(&spear_msi_data[pp->port]));
+ msg.data = pos;
+ write_msi_msg(irq, &msg);
+
+ return 0;
+}
+
+void arch_teardown_msi_irq(unsigned int irq)
+{
+ clean_irq(irq);
+}
+
+static void spear13xx_msi_init(struct pcie_port *pp)
+{
+ struct pcie_app_reg *app_reg = (struct pcie_app_reg *)pp->va_app_base;
+
+ spear_dbi_write_reg(pp, PCIE_MSI_ADDR_LO, 4,
+ __virt_to_phys((u32)(&spear_msi_data[pp->port])));
+ spear_dbi_write_reg(pp, PCIE_MSI_ADDR_HI, 4, 0);
+ /* Enbale MSI interrupt*/
+ writel(readl(&app_reg->int_mask) | MSI_CTRL_INT,
+ &app_reg->int_mask);
+}
+#endif
diff --git a/arch/arm/mach-spear13xx/spear1300_evb.c b/arch/arm/mach-spear13xx/spear1300_evb.c
index cba0fee..4799ae1 100644
--- a/arch/arm/mach-spear13xx/spear1300_evb.c
+++ b/arch/arm/mach-spear13xx/spear1300_evb.c
@@ -16,6 +16,7 @@
#include <asm/mach-types.h>
#include <mach/generic.h>
#include <mach/hardware.h>
+#include <mach/pcie.h>
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
@@ -45,6 +46,30 @@ static struct amba_device *amba_devs[] __initdata = {
static struct platform_device *plat_devs[] __initdata = {
};
+#ifdef CONFIG_PCIEPORTBUS
+/*
+ * This function is needed for PCIE host and device driver. Same
+ * controller can not be programmed as host as well as device. So host
+ * driver must call this function and if this function returns 1 then
+ * only host should add that particular port as RC.
+ * A port to be added as device, one must also add device's information
+ * in plat_devs array defined in this file.
+ */
+static int spear1300_pcie_port_is_host(int port)
+{
+ switch (port) {
+ case 0:
+ return 0;
+ case 1:
+ return 1;
+ case 2:
+ return 1;
+ }
+
+ return -EINVAL;
+}
+#endif
+
static void __init spear1300_evb_init(void)
{
unsigned int i;
@@ -52,6 +77,12 @@ static void __init spear1300_evb_init(void)
/* call spear1300 machine init function */
spear1300_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
+#ifdef CONFIG_PCIEPORTBUS
+ /* Enable PCIE0 clk */
+ enable_pcie0_clk();
+ pcie_init(spear1300_pcie_port_is_host);
+#endif
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear13xx/spear1310_evb.c b/arch/arm/mach-spear13xx/spear1310_evb.c
index 62af911..2e74879 100644
--- a/arch/arm/mach-spear13xx/spear1310_evb.c
+++ b/arch/arm/mach-spear13xx/spear1310_evb.c
@@ -16,6 +16,7 @@
#include <asm/mach-types.h>
#include <mach/generic.h>
#include <mach/hardware.h>
+#include <mach/pcie.h>
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
@@ -64,6 +65,30 @@ static struct platform_device *plat_devs[] __initdata = {
&spear1310_can1_device,
};
+#ifdef CONFIG_PCIEPORTBUS
+/*
+ * This function is needed for PCIE host and device driver. Same
+ * controller can not be programmed as host as well as device. So host
+ * driver must call this function and if this function returns 1 then
+ * only host should add that particular port as RC.
+ * A port to be added as device, one must also add device's information
+ * in plat_devs array defined in this file.
+ */
+static int spear1310_pcie_port_is_host(int port)
+{
+ switch (port) {
+ case 0:
+ return 0;
+ case 1:
+ return 1;
+ case 2:
+ return 1;
+ }
+
+ return -EINVAL;
+}
+#endif
+
static void __init spear1310_evb_init(void)
{
unsigned int i;
@@ -71,6 +96,12 @@ static void __init spear1310_evb_init(void)
/* call spear1310 machine init function */
spear1310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
+#ifdef CONFIG_PCIEPORTBUS
+ /* Enable PCIE0 clk */
+ enable_pcie0_clk();
+ pcie_init(spear1310_pcie_port_is_host);
+#endif
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 35582a6..6c2525a 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -76,6 +76,34 @@ struct amba_device spear13xx_uart_device = {
.irq = {IRQ_UART, NO_IRQ},
};
+#ifdef CONFIG_PCIEPORTBUS
+/* PCIE0 clock always needs to be enabled if any of the three PCIE port
+ * have to be used. So call this function from the board initilization
+ * file. Ideally , all controller should have been independent from
+ * others with respect to clock.
+ */
+int enable_pcie0_clk(void)
+{
+ struct clk *clk;
+ /*Enable all CLK in CFG registers here only. Idealy only PCIE0
+ * should have been enabled. But Controler does not work
+ * properly if PCIE1 and PCIE2's CFG CLK is enabled in stages.
+ */
+ writel(PCIE0_CFG_VAL | PCIE1_CFG_VAL | PCIE2_CFG_VAL, PCIE_CFG);
+ clk = clk_get_sys("pcie0", NULL);
+ if (IS_ERR(clk)) {
+ pr_err("%s:couldn't get clk for pcie0\n", __func__);
+ return -ENODEV;
+ }
+ if (clk_enable(clk)) {
+ pr_err("%s:couldn't enable clk for pcie0\n", __func__);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+#endif
+
/* Do spear13xx familiy common initialization part here */
void __init spear13xx_init(void)
{
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 29a25d2..ee5fd4a 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -12,6 +12,8 @@ config ARCH_SPEAR13XX
bool "SPEAr13XX"
select ARM_GIC
select CPU_V7
+ select ARCH_SUPPORTS_MSI
+ select MIGHT_HAVE_PCI
help
Supports for ARM's SPEAR13XX family
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 03/17] ST SPEAr: Adding PLGPIO driver for spear platform
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977727.git.viresh.kumar@st.com>
Plgpio pads on few spear machines can be configured as gpios. This patch add
support for configuring these PLGPIOs.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 2 +
arch/arm/mach-spear3xx/include/mach/gpio.h | 143 ++++++++
arch/arm/mach-spear3xx/spear310.c | 68 ++++
arch/arm/mach-spear3xx/spear310_evb.c | 1 +
arch/arm/mach-spear3xx/spear320.c | 28 ++
arch/arm/mach-spear3xx/spear320_evb.c | 1 +
arch/arm/mach-spear6xx/include/mach/gpio.h | 27 ++
arch/arm/plat-spear/Makefile | 2 +
arch/arm/plat-spear/include/plat/gpio.h | 35 ++
arch/arm/plat-spear/plgpio.c | 473 +++++++++++++++++++++++++
10 files changed, 780 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/plat-spear/plgpio.c
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 5320ab6..31e7a03 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -145,6 +145,7 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
/* spear310 declarations */
#ifdef CONFIG_MACH_SPEAR310
/* Add spear310 machine device structure declarations here */
+extern struct platform_device spear310_plgpio_device;
/* pad mux devices */
extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
@@ -166,6 +167,7 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
/* spear320 declarations */
#ifdef CONFIG_MACH_SPEAR320
/* Add spear320 machine device structure declarations here */
+extern struct platform_device spear320_plgpio_device;
/* pad mux modes */
extern struct pmx_mode spear320_auto_net_smii_mode;
diff --git a/arch/arm/mach-spear3xx/include/mach/gpio.h b/arch/arm/mach-spear3xx/include/mach/gpio.h
index 451b208..1881f70 100644
--- a/arch/arm/mach-spear3xx/include/mach/gpio.h
+++ b/arch/arm/mach-spear3xx/include/mach/gpio.h
@@ -16,4 +16,147 @@
#include <plat/gpio.h>
+#ifdef CONFIG_MACH_SPEAR310
+#define SPEAR310_PLGPIO_ENB 0x0010
+#define SPEAR310_PLGPIO_WDATA 0x0020
+#define SPEAR310_PLGPIO_DIR 0x0030
+#define SPEAR310_PLGPIO_IE 0x0040
+#define SPEAR310_PLGPIO_RDATA 0x0050
+#define SPEAR310_PLGPIO_MIS 0x0060
+#endif /* CONFIG_MACH_SPEAR310 */
+
+#ifdef CONFIG_MACH_SPEAR320
+#define SPEAR320_PLGPIO_ENB 0x0024
+#define SPEAR320_PLGPIO_WDATA 0x0034
+#define SPEAR320_PLGPIO_DIR 0x0044
+#define SPEAR320_PLGPIO_RDATA 0x0054
+#define SPEAR320_PLGPIO_IE 0x0064
+#define SPEAR320_PLGPIO_MIS 0x0074
+#endif /* CONFIG_MACH_SPEAR320 */
+
+#define BASIC_GPIO_0 0
+#define BASIC_GPIO_1 1
+#define BASIC_GPIO_2 2
+#define BASIC_GPIO_3 3
+#define BASIC_GPIO_4 4
+#define BASIC_GPIO_5 5
+#define BASIC_GPIO_6 6
+#define BASIC_GPIO_7 7
+
+#ifdef CONFIG_MACH_SPEAR300
+#define RAS_GPIO_0 8
+#define RAS_GPIO_1 9
+#define RAS_GPIO_2 10
+#define RAS_GPIO_3 11
+#define RAS_GPIO_4 12
+#define RAS_GPIO_5 13
+#define RAS_GPIO_6 14
+#define RAS_GPIO_7 15
+#endif /* CONFIG_MACH_SPEAR300 */
+
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#define PLGPIO_0 8
+#define PLGPIO_1 9
+#define PLGPIO_2 10
+#define PLGPIO_3 11
+#define PLGPIO_4 12
+#define PLGPIO_5 13
+#define PLGPIO_6 14
+#define PLGPIO_7 15
+#define PLGPIO_8 16
+#define PLGPIO_9 17
+#define PLGPIO_10 18
+#define PLGPIO_11 19
+#define PLGPIO_12 20
+#define PLGPIO_13 21
+#define PLGPIO_14 22
+#define PLGPIO_15 23
+#define PLGPIO_16 24
+#define PLGPIO_17 25
+#define PLGPIO_18 26
+#define PLGPIO_19 27
+#define PLGPIO_20 28
+#define PLGPIO_21 29
+#define PLGPIO_22 30
+#define PLGPIO_23 31
+#define PLGPIO_24 32
+#define PLGPIO_25 33
+#define PLGPIO_26 34
+#define PLGPIO_27 35
+#define PLGPIO_28 36
+#define PLGPIO_29 37
+#define PLGPIO_30 38
+#define PLGPIO_31 39
+#define PLGPIO_32 40
+#define PLGPIO_33 41
+#define PLGPIO_34 42
+#define PLGPIO_35 43
+#define PLGPIO_36 44
+#define PLGPIO_37 45
+#define PLGPIO_38 46
+#define PLGPIO_39 47
+#define PLGPIO_40 48
+#define PLGPIO_41 49
+#define PLGPIO_42 50
+#define PLGPIO_43 51
+#define PLGPIO_44 52
+#define PLGPIO_45 53
+#define PLGPIO_46 54
+#define PLGPIO_47 55
+#define PLGPIO_48 56
+#define PLGPIO_49 57
+#define PLGPIO_50 58
+#define PLGPIO_51 59
+#define PLGPIO_52 60
+#define PLGPIO_53 61
+#define PLGPIO_54 62
+#define PLGPIO_55 63
+#define PLGPIO_56 64
+#define PLGPIO_57 65
+#define PLGPIO_58 66
+#define PLGPIO_59 67
+#define PLGPIO_60 68
+#define PLGPIO_61 69
+#define PLGPIO_62 70
+#define PLGPIO_63 71
+#define PLGPIO_64 72
+#define PLGPIO_65 73
+#define PLGPIO_66 74
+#define PLGPIO_67 75
+#define PLGPIO_68 76
+#define PLGPIO_69 77
+#define PLGPIO_70 78
+#define PLGPIO_71 79
+#define PLGPIO_72 80
+#define PLGPIO_73 81
+#define PLGPIO_74 82
+#define PLGPIO_75 83
+#define PLGPIO_76 84
+#define PLGPIO_77 85
+#define PLGPIO_78 86
+#define PLGPIO_79 87
+#define PLGPIO_80 88
+#define PLGPIO_81 89
+#define PLGPIO_82 90
+#define PLGPIO_83 91
+#define PLGPIO_84 92
+#define PLGPIO_85 93
+#define PLGPIO_86 94
+#define PLGPIO_87 95
+#define PLGPIO_88 96
+#define PLGPIO_89 97
+#define PLGPIO_90 98
+#define PLGPIO_91 99
+#define PLGPIO_92 100
+#define PLGPIO_93 101
+#define PLGPIO_94 102
+#define PLGPIO_95 103
+#define PLGPIO_96 104
+#define PLGPIO_97 105
+#define PLGPIO_98 106
+#define PLGPIO_99 107
+#define PLGPIO_100 108
+#define PLGPIO_101 109
+#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
+
#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 4522e48..a4cd44c 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -13,6 +13,7 @@
#include <linux/ptrace.h>
#include <asm/irq.h>
+#include <plat/gpio.h>
#include <plat/shirq.h>
#include <mach/generic.h>
#include <mach/hardware.h>
@@ -308,6 +309,73 @@ static struct spear_shirq shirq_intrcomm_ras = {
};
/* Add spear310 specific devices here */
+/* plgpio device registeration */
+/*
+ * pin to offset and offset to pin converter functions
+ *
+ * In spear310 there is inconsistency among bit positions in plgpio regiseters,
+ * for different plgpio pins. For example: for pin 27, bit offset is 23, pin
+ * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1
+ */
+static int spear300_p2o(int pin)
+{
+ int offset = pin;
+
+ if (pin <= 27)
+ offset += 4;
+ else if (pin <= 33)
+ offset = -1;
+ else if (pin <= 97)
+ offset -= 2;
+ else if (pin <= 101)
+ offset = 101 - pin;
+ else
+ offset = -1;
+
+ return offset;
+}
+
+int spear300_o2p(int offset)
+{
+ if (offset <= 3)
+ return 101 - offset;
+ else if (offset <= 31)
+ return offset - 4;
+ else
+ return offset + 2;
+}
+
+static struct plgpio_platform_data plgpio_plat_data = {
+ .gpio_base = 8,
+ .irq_base = SPEAR3XX_PLGPIO_INT_BASE,
+ .gpio_count = SPEAR3XX_PLGPIO_COUNT,
+ .p2o = spear300_p2o,
+ .o2p = spear300_o2p,
+ /* list of registers with inconsistency */
+ .p2o_regs = PTO_RDATA_REG | PTO_WDATA_REG | PTO_DIR_REG |
+ PTO_IE_REG | PTO_RDATA_REG | PTO_MIS_REG,
+};
+
+static struct resource plgpio_resources[] = {
+ {
+ .start = SPEAR310_SOC_CONFIG_BASE,
+ .end = SPEAR310_SOC_CONFIG_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = SPEAR310_VIRQ_PLGPIO,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear310_plgpio_device = {
+ .name = "plgpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &plgpio_plat_data,
+ },
+ .num_resources = ARRAY_SIZE(plgpio_resources),
+ .resource = plgpio_resources,
+};
/* spear310 routines */
void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index c8684ce..f6832c4 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -52,6 +52,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
/* spear310 specific devices */
+ &spear310_plgpio_device,
};
static void __init spear310_evb_init(void)
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index a99cf7c..06b3332 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -13,6 +13,7 @@
#include <linux/ptrace.h>
#include <asm/irq.h>
+#include <plat/gpio.h>
#include <plat/shirq.h>
#include <mach/generic.h>
#include <mach/hardware.h>
@@ -711,6 +712,33 @@ static struct spear_shirq shirq_intrcomm_ras = {
};
/* Add spear320 specific devices here */
+/* plgpio device registeration */
+static struct plgpio_platform_data plgpio_plat_data = {
+ .gpio_base = 8,
+ .irq_base = SPEAR3XX_PLGPIO_INT_BASE,
+ .gpio_count = SPEAR3XX_PLGPIO_COUNT,
+};
+
+static struct resource plgpio_resources[] = {
+ {
+ .start = SPEAR320_SOC_CONFIG_BASE,
+ .end = SPEAR320_SOC_CONFIG_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = SPEAR320_VIRQ_PLGPIO,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear320_plgpio_device = {
+ .name = "plgpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &plgpio_plat_data,
+ },
+ .num_resources = ARRAY_SIZE(plgpio_resources),
+ .resource = plgpio_resources,
+};
/* spear320 routines */
void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index a12b353..4d747db 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -49,6 +49,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
/* spear320 specific devices */
+ &spear320_plgpio_device,
};
static void __init spear320_evb_init(void)
diff --git a/arch/arm/mach-spear6xx/include/mach/gpio.h b/arch/arm/mach-spear6xx/include/mach/gpio.h
index 3a789db..465b2e7 100644
--- a/arch/arm/mach-spear6xx/include/mach/gpio.h
+++ b/arch/arm/mach-spear6xx/include/mach/gpio.h
@@ -16,4 +16,31 @@
#include <plat/gpio.h>
+#define CPU_GPIO_0 0
+#define CPU_GPIO_1 1
+#define CPU_GPIO_2 2
+#define CPU_GPIO_3 3
+#define CPU_GPIO_4 4
+#define CPU_GPIO_5 5
+#define CPU_GPIO_6 6
+#define CPU_GPIO_7 7
+
+#define BASIC_GPIO_0 8
+#define BASIC_GPIO_1 9
+#define BASIC_GPIO_2 10
+#define BASIC_GPIO_3 11
+#define BASIC_GPIO_4 12
+#define BASIC_GPIO_5 13
+#define BASIC_GPIO_6 14
+#define BASIC_GPIO_7 15
+
+#define APPL_GPIO_0 16
+#define APPL_GPIO_1 17
+#define APPL_GPIO_2 18
+#define APPL_GPIO_3 19
+#define APPL_GPIO_4 20
+#define APPL_GPIO_5 21
+#define APPL_GPIO_6 22
+#define APPL_GPIO_7 23
+
#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 03f9acc..f462c8f 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -7,3 +7,5 @@ obj-y := clock.o time.o
obj-$(CONFIG_ARCH_SPEAR13XX) += padmux.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
+obj-$(CONFIG_MACH_SPEAR310) += plgpio.o
+obj-$(CONFIG_MACH_SPEAR320) += plgpio.o
diff --git a/arch/arm/plat-spear/include/plat/gpio.h b/arch/arm/plat-spear/include/plat/gpio.h
index b857c91..450671e 100644
--- a/arch/arm/plat-spear/include/plat/gpio.h
+++ b/arch/arm/plat-spear/include/plat/gpio.h
@@ -21,4 +21,39 @@
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
+/* plgpio driver declarations */
+/*
+ * plgpio pins in all machines are not one to one mapped, bitwise with
+ * registers bits. These set of macros define register masks for which below
+ * functions (pin_to_offset and offset_to_pin) are required to be called.
+ */
+#define PTO_ENB_REG 0x001
+#define PTO_WDATA_REG 0x002
+#define PTO_DIR_REG 0x004
+#define PTO_IE_REG 0x008
+#define PTO_RDATA_REG 0x010
+#define PTO_MIS_REG 0x020
+
+/* functions for converting pin to correct offset in register and vice versa */
+/**
+ * struct plgpio_platform_data: plgpio driver platform data
+ *
+ * gpio_base: gpio start number of plgpios
+ * irq_base: irq number of plgpio0
+ * gpio_count: total count of plgpios
+ * p2o: function ptr for pin to offset conversion. This is required only for
+ * machines where mapping b/w pin and offset is not 1-to-1.
+ * o2p: function ptr for offset to pin conversion. This is required only for
+ * machines where mapping b/w pin and offset is not 1-to-1.
+ * p2o_regs: mask of registers for which p2o and o2p are applicable
+ */
+struct plgpio_platform_data {
+ u32 gpio_base;
+ u32 irq_base;
+ u32 gpio_count;
+ int (*p2o)(int pin); /* pin_to_offset */
+ int (*o2p)(int offset); /* offset_to_pin */
+ u32 p2o_regs;
+};
+
#endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/plat-spear/plgpio.c b/arch/arm/plat-spear/plgpio.c
new file mode 100644
index 0000000..4db9a07
--- /dev/null
+++ b/arch/arm/plat-spear/plgpio.c
@@ -0,0 +1,473 @@
+/*
+ * arch/arm/plat-spear/plgpio.c
+ *
+ * SPEAr platform PLGPIO driver source file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <asm/mach-types.h>
+
+#define MAX_GPIO_PER_REG 32
+#define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
+#define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG)\
+ * sizeof(int *))
+
+static unsigned int plgpio_enb, plgpio_wdata, plgpio_dir, plgpio_rdata,
+ plgpio_ie, plgpio_mis;
+
+/*
+ * struct plgpio: plgpio driver specific structure
+ *
+ * lock: lock for guarding gpio registers
+ * base: base address of plgpio block
+ * irq_base: irq number of plgpio0
+ * chip: gpio framework specific chip information structure
+ * p2o: function ptr for pin to offset conversion. This is required only for
+ * machines where mapping b/w pin and offset is not 1-to-1.
+ * o2p: function ptr for offset to pin conversion. This is required only for
+ * machines where mapping b/w pin and offset is not 1-to-1.
+ * p2o_regs: mask of registers for which p2o and o2p are applicable
+ */
+struct plgpio {
+ spinlock_t lock;
+ void __iomem *base;
+ unsigned irq_base;
+ struct gpio_chip chip;
+ int (*p2o)(int pin); /* pin_to_offset */
+ int (*o2p)(int offset); /* offset_to_pin */
+ u32 p2o_regs;
+};
+
+/* register manipulation inline functions */
+static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg)
+{
+ u32 offset = PIN_OFFSET(pin);
+ void __iomem *reg_off = REG_OFFSET(base, reg, pin);
+ u32 val = readl(reg_off);
+
+ return val & (1 << offset);
+}
+
+static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg)
+{
+ u32 offset = PIN_OFFSET(pin);
+ void __iomem *reg_off = REG_OFFSET(base, reg, pin);
+ u32 val = readl(reg_off);
+
+ writel(val | (1 << offset), reg_off);
+}
+
+static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg)
+{
+ u32 offset = PIN_OFFSET(pin);
+ void __iomem *reg_off = REG_OFFSET(base, reg, pin);
+ u32 val = readl(reg_off);
+
+ writel(val & ~(1 << offset), reg_off);
+}
+
+/* gpio framework specific routines */
+static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+ unsigned long flags;
+
+ if (offset >= chip->ngpio)
+ return -EINVAL;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&plgpio->lock, flags);
+ plgpio_reg_set(plgpio->base, offset, plgpio_dir);
+ spin_unlock_irqrestore(&plgpio->lock, flags);
+
+ return 0;
+}
+
+static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+ unsigned long flags;
+ unsigned dir_offset = offset, wdata_offset = offset, tmp;
+
+ if (offset >= chip->ngpio)
+ return -EINVAL;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) {
+ tmp = plgpio->p2o(offset);
+ if (tmp == -1)
+ return -EINVAL;
+
+ if (plgpio->p2o_regs & PTO_DIR_REG)
+ dir_offset = tmp;
+ if (plgpio->p2o_regs & PTO_WDATA_REG)
+ wdata_offset = tmp;
+ }
+
+ spin_lock_irqsave(&plgpio->lock, flags);
+ plgpio_reg_reset(plgpio->base, dir_offset, plgpio_dir);
+ if (value)
+ plgpio_reg_set(plgpio->base, wdata_offset, plgpio_wdata);
+ else
+ plgpio_reg_reset(plgpio->base, wdata_offset, plgpio_wdata);
+ spin_unlock_irqrestore(&plgpio->lock, flags);
+
+ return 0;
+}
+
+static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+
+ if (offset >= chip->ngpio)
+ return -EINVAL;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return -EINVAL;
+ }
+
+ return is_plgpio_set(plgpio->base, offset, plgpio_rdata);
+}
+
+static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+
+ if (offset >= chip->ngpio)
+ return;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return;
+ }
+
+ if (value)
+ plgpio_reg_set(plgpio->base, offset, plgpio_wdata);
+ else
+ plgpio_reg_reset(plgpio->base, offset, plgpio_wdata);
+}
+
+static int plgpio_request(struct gpio_chip *chip, unsigned offset)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+ unsigned long flags;
+ int ret = 0;
+
+ if (offset >= chip->ngpio)
+ return -EINVAL;
+
+ /*
+ * put gpio in IN mode before enabling it. This make enabling gpio safe
+ */
+ ret = plgpio_direction_input(chip, offset);
+ if (ret)
+ return ret;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&plgpio->lock, flags);
+ plgpio_reg_set(plgpio->base, offset, plgpio_enb);
+ spin_unlock_irqrestore(&plgpio->lock, flags);
+
+ return 0;
+}
+
+static void plgpio_free(struct gpio_chip *chip, unsigned offset)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+ unsigned long flags;
+
+ if (offset >= chip->ngpio)
+ return;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return;
+ }
+
+ spin_lock_irqsave(&plgpio->lock, flags);
+ plgpio_reg_reset(plgpio->base, offset, plgpio_enb);
+ spin_unlock_irqrestore(&plgpio->lock, flags);
+}
+
+static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
+
+ if (plgpio->irq_base == (unsigned) -1)
+ return -EINVAL;
+
+ return plgpio->irq_base + offset;
+}
+
+/* PLGPIO IRQ */
+static void plgpio_irq_mask(unsigned irq)
+{
+ struct plgpio *plgpio = get_irq_chip_data(irq);
+ int offset = irq - plgpio->irq_base;
+ unsigned long flags;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return;
+ }
+
+ spin_lock_irqsave(&plgpio->lock, flags);
+ plgpio_reg_set(plgpio->base, offset, plgpio_ie);
+ spin_unlock_irqrestore(&plgpio->lock, flags);
+}
+
+static void plgpio_irq_unmask(unsigned irq)
+{
+ struct plgpio *plgpio = get_irq_chip_data(irq);
+ int offset = irq - plgpio->irq_base;
+ unsigned long flags;
+
+ /* get correct offset for "offset" pin */
+ if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
+ offset = plgpio->p2o(offset);
+ if (offset == -1)
+ return;
+ }
+
+ spin_lock_irqsave(&plgpio->lock, flags);
+ plgpio_reg_reset(plgpio->base, offset, plgpio_ie);
+ spin_unlock_irqrestore(&plgpio->lock, flags);
+}
+
+static int plgpio_irq_type(unsigned irq, unsigned trigger)
+{
+ struct plgpio *plgpio = get_irq_chip_data(irq);
+ int offset = irq - plgpio->irq_base;
+
+ if (offset >= plgpio->chip.ngpio)
+ return -EINVAL;
+
+ if (trigger != IRQ_TYPE_LEVEL_HIGH)
+ return -EINVAL;
+ return 0;
+}
+
+static struct irq_chip plgpio_irqchip = {
+ .name = "PLGPIO",
+ .mask = plgpio_irq_mask,
+ .unmask = plgpio_irq_unmask,
+ .set_type = plgpio_irq_type,
+};
+
+static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+ struct plgpio *plgpio = get_irq_data(irq);
+ unsigned long pending;
+ int regs_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG),
+ count, pin, offset, i = 0;
+
+ /* check all plgpio MIS registers for a possible interrupt */
+ for (; i < regs_count; i++) {
+ pending = readl(plgpio->base + plgpio_mis + i * sizeof(int *));
+ if (!pending)
+ continue;
+
+ /*
+ * clear extra bits in last register having gpios < MAX/REG
+ * ex: Suppose there are max 102 plgpios. then last register
+ * must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits
+ * so, we must not take other 28 bits into consideration for
+ * checking interrupt. so clear those bits.
+ */
+ count = plgpio->chip.ngpio - i * MAX_GPIO_PER_REG;
+ if (count < MAX_GPIO_PER_REG)
+ pending &= (1 << count) - 1;
+
+ for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) {
+ /* get correct pin for "offset" */
+ if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) {
+ pin = plgpio->o2p(offset);
+ if (pin == -1)
+ continue;
+ } else
+ pin = offset;
+
+ generic_handle_irq(plgpio_to_irq(&plgpio->chip,
+ i * MAX_GPIO_PER_REG + pin));
+ }
+ }
+}
+
+static int __devinit plgpio_probe(struct platform_device *pdev)
+{
+ struct plgpio_platform_data *pdata;
+ struct plgpio *plgpio;
+ int ret, irq, i;
+ struct resource *res;
+
+ pdata = pdev->dev.platform_data;
+ if (!pdata) {
+ ret = -ENODEV;
+ dev_dbg(&pdev->dev, "invalid platform data\n");
+ goto fail;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ ret = -EBUSY;
+ dev_dbg(&pdev->dev, "invalid IORESOURCE_MEM\n");
+ goto fail;
+ }
+
+ if (!request_mem_region(res->start, resource_size(res), "plgpio")) {
+ ret = -EBUSY;
+ dev_dbg(&pdev->dev, "request mem region fail\n");
+ goto fail;
+ }
+
+ plgpio = kzalloc(sizeof(*plgpio), GFP_KERNEL);
+ if (!plgpio) {
+ ret = -ENOMEM;
+ dev_dbg(&pdev->dev, "memory allocation fail\n");
+ goto release_region;
+ }
+
+ plgpio->base = ioremap(res->start, resource_size(res));
+ if (!plgpio->base) {
+ ret = -ENOMEM;
+ dev_dbg(&pdev->dev, "ioremap fail\n");
+ goto kfree;
+ }
+
+ spin_lock_init(&plgpio->lock);
+
+ plgpio->chip.request = plgpio_request;
+ plgpio->chip.free = plgpio_free;
+ plgpio->chip.direction_input = plgpio_direction_input;
+ plgpio->chip.direction_output = plgpio_direction_output;
+ plgpio->chip.get = plgpio_get_value;
+ plgpio->chip.set = plgpio_set_value;
+ plgpio->chip.to_irq = plgpio_to_irq;
+ plgpio->chip.base = pdata->gpio_base;
+ plgpio->chip.ngpio = pdata->gpio_count;
+ plgpio->chip.label = dev_name(&pdev->dev);
+ plgpio->chip.dev = &pdev->dev;
+ plgpio->chip.owner = THIS_MODULE;
+ plgpio->irq_base = pdata->irq_base;
+ plgpio->p2o = pdata->p2o;
+ plgpio->o2p = pdata->o2p;
+ plgpio->p2o_regs = pdata->p2o_regs;
+
+ ret = gpiochip_add(&plgpio->chip);
+ if (ret) {
+ dev_dbg(&pdev->dev, "unable to add gpio chip\n");
+ goto iounmap;
+ }
+
+ /* irq_chip support */
+ if (pdata->irq_base == (unsigned) -1) {
+ dev_info(&pdev->dev, "Initialization successful\n");
+ return 0;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ ret = -ENODEV;
+ dev_dbg(&pdev->dev, "invalid irq number\n");
+ goto remove_gpiochip;
+ }
+
+ set_irq_chained_handler(irq, plgpio_irq_handler);
+ for (i = 0; i < pdata->gpio_count; i++) {
+ set_irq_chip(i+plgpio->irq_base, &plgpio_irqchip);
+ set_irq_handler(i+plgpio->irq_base, handle_simple_irq);
+ set_irq_flags(i+plgpio->irq_base, IRQF_VALID);
+ set_irq_chip_data(i+plgpio->irq_base, plgpio);
+ }
+ set_irq_data(irq, plgpio);
+ dev_info(&pdev->dev, "Initialization successful\n");
+
+ return 0;
+
+remove_gpiochip:
+ if (gpiochip_remove(&plgpio->chip))
+ dev_dbg(&pdev->dev, "unable to remove gpiochip\n");
+iounmap:
+ iounmap(plgpio->base);
+kfree:
+ kfree(plgpio);
+release_region:
+ release_mem_region(res->start, resource_size(res));
+fail:
+ dev_err(&pdev->dev, "probe fail: %d\n", ret);
+ return ret;
+}
+
+static struct platform_driver plgpio_driver = {
+ .probe = plgpio_probe,
+ .driver = {
+ .name = "plgpio",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init plgpio_init(void)
+{
+ if (machine_is_spear310()) {
+ plgpio_enb = SPEAR310_PLGPIO_ENB;
+ plgpio_wdata = SPEAR310_PLGPIO_WDATA;
+ plgpio_dir = SPEAR310_PLGPIO_DIR;
+ plgpio_rdata = SPEAR310_PLGPIO_IE;
+ plgpio_ie = SPEAR310_PLGPIO_RDATA;
+ plgpio_mis = SPEAR310_PLGPIO_MIS;
+ } else if (machine_is_spear320()) {
+ plgpio_enb = SPEAR320_PLGPIO_ENB;
+ plgpio_wdata = SPEAR320_PLGPIO_WDATA;
+ plgpio_dir = SPEAR320_PLGPIO_DIR;
+ plgpio_rdata = SPEAR320_PLGPIO_IE;
+ plgpio_ie = SPEAR320_PLGPIO_RDATA;
+ plgpio_mis = SPEAR320_PLGPIO_MIS;
+ } else
+ return -EACCES;
+
+ return platform_driver_register(&plgpio_driver);
+}
+subsys_initcall(plgpio_init);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("SPEAr PLGPIO driver");
+MODULE_LICENSE("GPL");
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 04/17] ST SPEAr3xx: Adding support for ST's PWM IP
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977727.git.viresh.kumar@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 1 +
arch/arm/mach-spear3xx/spear320.c | 16 +
arch/arm/mach-spear3xx/spear320_evb.c | 1 +
arch/arm/plat-spear/Kconfig | 7 +
arch/arm/plat-spear/Makefile | 2 +
arch/arm/plat-spear/pwm.c | 484 +++++++++++++++++++++++++
6 files changed, 511 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/plat-spear/pwm.c
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 31e7a03..f43d104 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -168,6 +168,7 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
#ifdef CONFIG_MACH_SPEAR320
/* Add spear320 machine device structure declarations here */
extern struct platform_device spear320_plgpio_device;
+extern struct platform_device spear320_pwm_device;
/* pad mux modes */
extern struct pmx_mode spear320_auto_net_smii_mode;
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 06b3332..c1642c1 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -740,6 +740,22 @@ struct platform_device spear320_plgpio_device = {
.resource = plgpio_resources,
};
+/* pwm device registeration */
+static struct resource pwm_resources[] = {
+ {
+ .start = SPEAR320_PWM_BASE,
+ .end = SPEAR320_PWM_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device spear320_pwm_device = {
+ .name = "pwm",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(pwm_resources),
+ .resource = pwm_resources,
+};
+
/* spear320 routines */
void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
u8 pmx_dev_count)
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 4d747db..6190660 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -50,6 +50,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear320 specific devices */
&spear320_plgpio_device,
+ &spear320_pwm_device,
};
static void __init spear320_evb_init(void)
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index ee5fd4a..21f31cd 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -38,4 +38,11 @@ source "arch/arm/mach-spear13xx/Kconfig"
source "arch/arm/mach-spear3xx/Kconfig"
source "arch/arm/mach-spear6xx/Kconfig"
+config SPEAR_PWM
+ tristate "SPEAr Pulse Width Modulator"
+ depends on MACH_SPEAR320
+ default y
+ help
+ Support for ST Microelectronics Pulse Width Modulator present on SPEAr Platform.
+
endif
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index f462c8f..636678a 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -9,3 +9,5 @@ obj-$(CONFIG_ARCH_SPEAR13XX) += padmux.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
obj-$(CONFIG_MACH_SPEAR310) += plgpio.o
obj-$(CONFIG_MACH_SPEAR320) += plgpio.o
+
+obj-$(CONFIG_SPEAR_PWM) += pwm.o
diff --git a/arch/arm/plat-spear/pwm.c b/arch/arm/plat-spear/pwm.c
new file mode 100644
index 0000000..307c725
--- /dev/null
+++ b/arch/arm/plat-spear/pwm.c
@@ -0,0 +1,484 @@
+/*
+ * arch/arm/plat-spear/pwm.c
+ *
+ * ST Microelectronics SPEAr Pulse Width Modulator driver
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+/* PWM registers and bits definitions */
+#define PWMCR 0x00
+#define PWMDCR 0x04
+#define PWMPCR 0x08
+
+#define PWM_EN_MASK 0x1
+#define MIN_PRESCALE 0x00
+#define MAX_PRESCALE 0x3FFF
+#define PRESCALE_SHIFT 2
+#define MIN_DUTY 0x0001
+#define MAX_DUTY 0xFFFF
+#define MAX_PERIOD 0xFFFF
+#define MIN_PERIOD 0x0001
+
+#define PWM_DEVICE_PER_IP 4
+#define PWM_DEVICE_OFFSET 0x10
+
+/* lock for pwm_list */
+static DEFINE_SPINLOCK(list_lock);
+/* list of all pwm ips available in system */
+static LIST_HEAD(pwm_list);
+
+/**
+ * struct pwm_device: struct representing pwm device/channel
+ *
+ * pwmd_id: id of pwm device
+ * pwm: pointer to parent pwm ip
+ * label: used for storing label passed in pwm_request
+ * offset: base address offset from parent pwm mmio_base
+ * busy: represents usage status of a pwm device
+ * lock: lock specific to a pwm device
+ * node: node for adding device to parent pwm's devices list
+ *
+ * Each pwm IP contains four independent pwm device/channels. Some or all of
+ * which may be present in our configuration.
+ */
+struct pwm_device {
+ unsigned pwmd_id;
+ struct pwm *pwm;
+ const char *label;
+ unsigned offset;
+ unsigned busy;
+ spinlock_t lock;
+ struct list_head node;
+};
+
+/**
+ * struct pwm: struct representing pwm ip
+ *
+ * id: id of pwm ip
+ * mmio_base: base address of pwm
+ * clk: pointer to clk structure of pwm ip
+ * clk_enabled: clock enable status
+ * pdev: pointer to pdev structure of pwm
+ * lock: lock specific to current pwm ip
+ * devices: list of devices/childrens of pwm ip
+ * node: node for adding pwm to global list of all pwm ips
+ */
+struct pwm {
+ unsigned id;
+ void __iomem *mmio_base;
+ struct clk *clk;
+ int clk_enabled;
+ struct platform_device *pdev;
+ spinlock_t lock;
+ struct list_head devices;
+ struct list_head node;
+};
+
+/*
+ * period_ns = 10^9 * (PRESCALE + 1) * PV / PWM_CLK_RATE
+ * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
+ *
+ * PV = (PWM_CLK_RATE * period_ns)/ (10^9 * (PRESCALE + 1))
+ * DC = (PWM_CLK_RATE * duty_ns)/ (10^9 * (PRESCALE + 1))
+ */
+int pwm_config(struct pwm_device *pwmd, int duty_ns, int period_ns)
+{
+ u64 val, div, clk_rate;
+ unsigned long prescale = MIN_PRESCALE, pv, dc;
+ int ret = 0;
+
+ if (!pwmd) {
+ pr_err("pwm: config - NULL pwm device pointer\n");
+ return -EFAULT;
+ }
+
+ if (period_ns == 0 || duty_ns > period_ns) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* TODO: Need to optimize this loop */
+ while (1) {
+ div = 1000000000;
+ div *= 1 + prescale;
+ clk_rate = clk_get_rate(pwmd->pwm->clk);
+ val = clk_rate * period_ns;
+ pv = div64_u64(val, div);
+ val = clk_rate * duty_ns;
+ dc = div64_u64(val, div);
+
+ if ((pv == 0) || (dc == 0)) {
+ ret = -EINVAL;
+ goto err;
+ }
+ if ((pv > MAX_PERIOD) || (dc > MAX_DUTY)) {
+ prescale++;
+ if (prescale > MAX_PRESCALE) {
+ ret = -EINVAL;
+ goto err;
+ }
+ continue;
+ }
+ if ((pv < MIN_PERIOD) || (dc < MIN_DUTY)) {
+ ret = -EINVAL;
+ goto err;
+ }
+ break;
+ }
+
+ /*
+ * NOTE: the clock to PWM has to be enabled first
+ * before writing to the registers
+ */
+ spin_lock(&pwmd->pwm->lock);
+ ret = clk_enable(pwmd->pwm->clk);
+ if (ret) {
+ spin_unlock(&pwmd->pwm->lock);
+ goto err;
+ }
+
+ spin_lock(&pwmd->lock);
+ writel(prescale << PRESCALE_SHIFT, pwmd->pwm->mmio_base +
+ pwmd->offset + PWMCR);
+ writel(dc, pwmd->pwm->mmio_base + pwmd->offset + PWMDCR);
+ writel(pv, pwmd->pwm->mmio_base + pwmd->offset + PWMPCR);
+ spin_unlock(&pwmd->lock);
+ clk_disable(pwmd->pwm->clk);
+ spin_unlock(&pwmd->pwm->lock);
+
+ return 0;
+err:
+ dev_err(&pwmd->pwm->pdev->dev, "pwm config fail\n");
+ return ret;
+}
+EXPORT_SYMBOL(pwm_config);
+
+int pwm_enable(struct pwm_device *pwmd)
+{
+ int ret = 0;
+ u32 val = 0;
+
+ if (!pwmd) {
+ pr_err("pwm: enable - NULL pwm device pointer\n");
+ return -EFAULT;
+ }
+
+ spin_lock(&pwmd->pwm->lock);
+ ret = clk_enable(pwmd->pwm->clk);
+ if (!ret)
+ pwmd->pwm->clk_enabled++;
+ else {
+ spin_unlock(&pwmd->pwm->lock);
+ goto err;
+ }
+
+ spin_lock(&pwmd->lock);
+ val = readl(pwmd->pwm->mmio_base + pwmd->offset + PWMCR);
+ writel(val | PWM_EN_MASK, pwmd->pwm->mmio_base + pwmd->offset + PWMCR);
+ spin_unlock(&pwmd->lock);
+ spin_unlock(&pwmd->pwm->lock);
+ return 0;
+err:
+ dev_err(&pwmd->pwm->pdev->dev, "pwm enable fail\n");
+ return ret;
+}
+EXPORT_SYMBOL(pwm_enable);
+
+void pwm_disable(struct pwm_device *pwmd)
+{
+ if (!pwmd) {
+ pr_err("pwm: disable - NULL pwm device pointer\n");
+ return;
+ }
+
+ spin_lock(&pwmd->pwm->lock);
+ spin_lock(&pwmd->lock);
+ writel(0, pwmd->pwm->mmio_base + pwmd->offset + PWMCR);
+ if (pwmd->pwm->clk_enabled) {
+ clk_disable(pwmd->pwm->clk);
+ pwmd->pwm->clk_enabled--;
+ }
+ spin_unlock(&pwmd->lock);
+ spin_unlock(&pwmd->pwm->lock);
+}
+EXPORT_SYMBOL(pwm_disable);
+
+struct pwm_device *pwm_request(int pwmd_id, const char *label)
+{
+ int found = 0;
+ struct pwm *pwm;
+ struct pwm_device *pwmd = NULL;
+
+ spin_lock(&list_lock);
+ list_for_each_entry(pwm, &pwm_list, node) {
+ spin_lock(&pwm->lock);
+ list_for_each_entry(pwmd, &pwm->devices, node) {
+ if (pwmd->pwmd_id == pwmd_id) {
+ found = 1;
+ break;
+ }
+ }
+ spin_unlock(&pwm->lock);
+ if (found)
+ break;
+ }
+ spin_unlock(&list_lock);
+
+ if (found) {
+ spin_lock(&pwmd->lock);
+ if (pwmd->busy == 0) {
+ pwmd->busy++;
+ pwmd->label = label;
+ } else
+ pwmd = ERR_PTR(-EBUSY);
+ spin_unlock(&pwmd->lock);
+ } else
+ pwmd = ERR_PTR(-ENOENT);
+
+ if (IS_ERR(pwmd))
+ pr_err("pwm: request fail\n");
+
+ return pwmd;
+}
+EXPORT_SYMBOL(pwm_request);
+
+void pwm_free(struct pwm_device *pwmd)
+{
+ if (!pwmd) {
+ pr_err("pwm: disable - NULL pwm device pointer\n");
+ return;
+ }
+
+ spin_lock(&pwmd->lock);
+ if (pwmd->busy) {
+ pwmd->busy--;
+ pwmd->label = NULL;
+ } else {
+ spin_unlock(&pwmd->lock);
+ dev_warn(&pwmd->pwm->pdev->dev, "pwm device already freed\n");
+ return;
+ }
+
+ spin_unlock(&pwmd->lock);
+}
+EXPORT_SYMBOL(pwm_free);
+
+/* creates and add pwmd device to parent pwm's devices list */
+static int add_pwm_device(unsigned int pwmd_id, struct pwm *pwm)
+{
+ struct pwm_device *pwmd;
+
+ pwmd = kzalloc(sizeof(*pwmd), GFP_KERNEL);
+ if (!pwmd)
+ return -ENOMEM;
+
+ pwmd->pwm = pwm;
+ pwmd->busy = 0;
+ pwmd->pwmd_id = pwmd_id + pwm->id * PWM_DEVICE_PER_IP;
+ pwmd->offset = pwmd_id * PWM_DEVICE_OFFSET;
+ spin_lock_init(&pwmd->lock);
+
+ spin_lock(&pwm->lock);
+ list_add_tail(&pwmd->node, &pwm->devices);
+ spin_unlock(&pwm->lock);
+
+ return 0;
+}
+
+/* removes all pwmd devices from parent pwm's devices list */
+static void remove_pwm_devices(struct pwm *pwm)
+{
+ struct pwm_device *pwmd;
+
+ spin_lock(&pwm->lock);
+ list_for_each_entry(pwmd, &pwm->devices, node) {
+ list_del(&pwmd->node);
+ kfree(pwmd);
+ }
+ spin_unlock(&pwm->lock);
+}
+
+static int __devinit spear_pwm_probe(struct platform_device *pdev)
+{
+ struct pwm *pwm = NULL;
+ struct resource *res;
+ int ret = 0, pwmd_id = 0;
+
+ pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
+ if (!pwm) {
+ ret = -ENOMEM;
+ dev_dbg(&pdev->dev, "failed to allocate memory\n");
+ goto err;
+ }
+
+ pwm->clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pwm->clk)) {
+ ret = PTR_ERR(pwm->clk);
+ dev_dbg(&pdev->dev, "Error getting clock\n");
+ goto err_free;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ ret = -ENODEV;
+ dev_dbg(&pdev->dev, "no memory resource defined\n");
+ goto err_free_clk;
+ }
+
+ if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
+ ret = -EBUSY;
+ dev_dbg(&pdev->dev, "failed to request memory resource\n");
+ goto err_free_clk;
+ }
+
+ pwm->mmio_base = ioremap(res->start, resource_size(res));
+ if (!pwm->mmio_base) {
+ ret = -ENOMEM;
+ dev_dbg(&pdev->dev, "failed to ioremap\n");
+ goto err_free_mem;
+ }
+
+ /* initialize pwm structure */
+ pwm->clk_enabled = 0;
+ pwm->pdev = pdev;
+ /* if pdev->id is -1, only one pwm ip is present */
+ if (pdev->id == -1)
+ pwm->id = 0;
+ else
+ pwm->id = pdev->id;
+
+ spin_lock_init(&pwm->lock);
+ INIT_LIST_HEAD(&pwm->devices);
+ platform_set_drvdata(pdev, pwm);
+
+ /* add pwm to pwm list */
+ spin_lock(&list_lock);
+ list_add_tail(&pwm->node, &pwm_list);
+ spin_unlock(&list_lock);
+
+ /* add pwm devices */
+ for (pwmd_id = 0; pwmd_id < PWM_DEVICE_PER_IP; pwmd_id++) {
+ ret = add_pwm_device(pwmd_id, pwm);
+ if (!ret)
+ continue;
+ dev_err(&pdev->dev, "Add device fail for pwm device id: %d\n",
+ pwmd_id);
+ }
+
+ if (list_empty(&pwm->node))
+ goto err_remove_pwm;
+
+ dev_info(&pdev->dev, "Initialization successful\n");
+ return 0;
+
+err_remove_pwm:
+ spin_lock(&list_lock);
+ list_del(&pwm->node);
+ spin_unlock(&list_lock);
+
+ platform_set_drvdata(pdev, NULL);
+ iounmap(pwm->mmio_base);
+err_free_mem:
+ release_mem_region(res->start, resource_size(res));
+err_free_clk:
+ clk_put(pwm->clk);
+err_free:
+ kfree(pwm);
+err:
+ dev_err(&pdev->dev, "Initialization Fail. Error: %d\n", ret);
+
+ return ret;
+}
+
+static int __devexit spear_pwm_remove(struct platform_device *pdev)
+{
+ struct pwm *pwm;
+ struct resource *res;
+ int ret = 0;
+
+ pwm = platform_get_drvdata(pdev);
+ if (pwm == NULL) {
+ ret = -ENODEV;
+ dev_dbg(&pdev->dev, "Remove: get_drvdata fail\n");
+ goto err;
+ }
+ platform_set_drvdata(pdev, NULL);
+
+ /* remove pwm devices */
+ remove_pwm_devices(pwm);
+
+ /* remove pwm from pwm_list */
+ spin_lock(&list_lock);
+ list_del(&pwm->node);
+ spin_unlock(&list_lock);
+
+ iounmap(pwm->mmio_base);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ ret = -ENODEV;
+ dev_dbg(&pdev->dev, "Remove: get_resource fail\n");
+ goto err;
+ }
+ release_mem_region(res->start, resource_size(res));
+
+ if (pwm->clk_enabled)
+ clk_disable(pwm->clk);
+ clk_put(pwm->clk);
+
+ kfree(pwm);
+ return 0;
+
+err:
+ dev_err(&pdev->dev, "Remove: Fail - %d\n", ret);
+ return ret;
+}
+
+static struct platform_driver spear_pwm_driver = {
+ .driver = {
+ .name = "pwm",
+ .bus = &platform_bus_type,
+ .owner = THIS_MODULE,
+ },
+ .probe = spear_pwm_probe,
+ .remove = __devexit_p(spear_pwm_remove)
+};
+
+static int __init spear_pwm_init(void)
+{
+ int ret = 0;
+
+ ret = platform_driver_register(&spear_pwm_driver);
+ if (ret)
+ pr_err("failed to register spear_pwm_driver\n");
+
+ return ret;
+}
+module_init(spear_pwm_init);
+
+static void __exit spear_pwm_exit(void)
+{
+ platform_driver_unregister(&spear_pwm_driver);
+}
+module_exit(spear_pwm_exit);
+
+MODULE_AUTHOR("Viresh Kumar");
+MODULE_DESCRIPTION("SPEAr PWM Driver");
+MODULE_LICENSE("GPL");
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 05/17] ST SPEAr: Adding Watchdog support on spear3xx & spear6xx machines
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977727.git.viresh.kumar@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 1 +
arch/arm/mach-spear3xx/spear300_evb.c | 1 +
arch/arm/mach-spear3xx/spear310_evb.c | 1 +
arch/arm/mach-spear3xx/spear320_evb.c | 1 +
arch/arm/mach-spear3xx/spear3xx.c | 12 ++++++++++++
arch/arm/mach-spear6xx/include/mach/generic.h | 1 +
arch/arm/mach-spear6xx/spear600_evb.c | 1 +
arch/arm/mach-spear6xx/spear6xx.c | 12 ++++++++++++
8 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index f43d104..6d4db44 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -33,6 +33,7 @@
/* Add spear3xx family device structure declarations here */
extern struct amba_device spear3xx_gpio_device;
extern struct amba_device spear3xx_uart_device;
+extern struct amba_device spear3xx_wdt_device;
extern struct sys_timer spear3xx_timer;
/* Add spear3xx family function declarations here */
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 69006f6..f4fd6db 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -36,6 +36,7 @@ static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&spear3xx_gpio_device,
&spear3xx_uart_device,
+ &spear3xx_wdt_device,
/* spear300 specific devices */
&spear300_gpio1_device,
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index f6832c4..9c1b7ca 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -44,6 +44,7 @@ static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&spear3xx_gpio_device,
&spear3xx_uart_device,
+ &spear3xx_wdt_device,
/* spear310 specific devices */
};
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 6190660..7b12f0c 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -41,6 +41,7 @@ static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&spear3xx_gpio_device,
&spear3xx_uart_device,
+ &spear3xx_wdt_device,
/* spear320 specific devices */
};
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index c32a186..b07c659 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -54,6 +54,18 @@ struct amba_device spear3xx_uart_device = {
.irq = {SPEAR3XX_IRQ_UART, NO_IRQ},
};
+/* watchdog device registeration */
+struct amba_device spear3xx_wdt_device = {
+ .dev = {
+ .init_name = "wdt",
+ },
+ .res = {
+ .start = SPEAR3XX_ICM3_WDT_BASE,
+ .end = SPEAR3XX_ICM3_WDT_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
/* Do spear3xx familiy common initialization part here */
void __init spear3xx_init(void)
{
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 183f023..0d17e65 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -31,6 +31,7 @@
/* Add spear6xx family device structure declarations here */
extern struct amba_device gpio_device[];
extern struct amba_device uart_device[];
+extern struct amba_device wdt_device;
extern struct sys_timer spear6xx_timer;
/* Add spear6xx family function declarations here */
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index f19cefe..6730868 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -22,6 +22,7 @@ static struct amba_device *amba_devs[] __initdata = {
&gpio_device[2],
&uart_device[0],
&uart_device[1],
+ &wdt_device,
};
static struct platform_device *plat_devs[] __initdata = {
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index e0f6628..3842545 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -99,6 +99,18 @@ struct amba_device gpio_device[] = {
}
};
+/* watchdog device registeration */
+struct amba_device wdt_device = {
+ .dev = {
+ .init_name = "wdt",
+ },
+ .res = {
+ .start = SPEAR6XX_ICM3_WDT_BASE,
+ .end = SPEAR6XX_ICM3_WDT_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
/* This will add devices, and do machine specific tasks */
void __init spear6xx_init(void)
{
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 06/17] ST SPEAr3xx: Adding RAS uart devices
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977727.git.viresh.kumar@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 7 +++
arch/arm/mach-spear3xx/spear310.c | 65 +++++++++++++++++++++++++
arch/arm/mach-spear3xx/spear310_evb.c | 5 ++
arch/arm/mach-spear3xx/spear320.c | 26 ++++++++++
arch/arm/mach-spear3xx/spear320_evb.c | 2 +
5 files changed, 105 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 6d4db44..8925b7b 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -146,6 +146,11 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
/* spear310 declarations */
#ifdef CONFIG_MACH_SPEAR310
/* Add spear310 machine device structure declarations here */
+extern struct amba_device spear310_uart1_device;
+extern struct amba_device spear310_uart2_device;
+extern struct amba_device spear310_uart3_device;
+extern struct amba_device spear310_uart4_device;
+extern struct amba_device spear310_uart5_device;
extern struct platform_device spear310_plgpio_device;
/* pad mux devices */
@@ -168,6 +173,8 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
/* spear320 declarations */
#ifdef CONFIG_MACH_SPEAR320
/* Add spear320 machine device structure declarations here */
+extern struct amba_device spear320_uart1_device;
+extern struct amba_device spear320_uart2_device;
extern struct platform_device spear320_plgpio_device;
extern struct platform_device spear320_pwm_device;
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index a4cd44c..ba21b75 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -309,6 +309,71 @@ static struct spear_shirq shirq_intrcomm_ras = {
};
/* Add spear310 specific devices here */
+/* uart1 device registeration */
+struct amba_device spear310_uart1_device = {
+ .dev = {
+ .init_name = "uart1",
+ },
+ .res = {
+ .start = SPEAR310_UART1_BASE,
+ .end = SPEAR310_UART1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {SPEAR310_VIRQ_UART1, NO_IRQ},
+};
+
+/* uart2 device registeration */
+struct amba_device spear310_uart2_device = {
+ .dev = {
+ .init_name = "uart2",
+ },
+ .res = {
+ .start = SPEAR310_UART2_BASE,
+ .end = SPEAR310_UART2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {SPEAR310_VIRQ_UART2, NO_IRQ},
+};
+
+/* uart3 device registeration */
+struct amba_device spear310_uart3_device = {
+ .dev = {
+ .init_name = "uart3",
+ },
+ .res = {
+ .start = SPEAR310_UART3_BASE,
+ .end = SPEAR310_UART3_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {SPEAR310_VIRQ_UART3, NO_IRQ},
+};
+
+/* uart4 device registeration */
+struct amba_device spear310_uart4_device = {
+ .dev = {
+ .init_name = "uart4",
+ },
+ .res = {
+ .start = SPEAR310_UART4_BASE,
+ .end = SPEAR310_UART4_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {SPEAR310_VIRQ_UART4, NO_IRQ},
+};
+
+/* uart5 device registeration */
+struct amba_device spear310_uart5_device = {
+ .dev = {
+ .init_name = "uart5",
+ },
+ .res = {
+ .start = SPEAR310_UART5_BASE,
+ .end = SPEAR310_UART5_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {SPEAR310_VIRQ_UART5, NO_IRQ},
+};
+
/* plgpio device registeration */
/*
* pin to offset and offset to pin converter functions
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 9c1b7ca..36fb611 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -47,6 +47,11 @@ static struct amba_device *amba_devs[] __initdata = {
&spear3xx_wdt_device,
/* spear310 specific devices */
+ &spear310_uart1_device,
+ &spear310_uart2_device,
+ &spear310_uart3_device,
+ &spear310_uart4_device,
+ &spear310_uart5_device,
};
static struct platform_device *plat_devs[] __initdata = {
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index c1642c1..77089a7 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -712,6 +712,32 @@ static struct spear_shirq shirq_intrcomm_ras = {
};
/* Add spear320 specific devices here */
+/* uart1 device registeration */
+struct amba_device spear320_uart1_device = {
+ .dev = {
+ .init_name = "uart1",
+ },
+ .res = {
+ .start = SPEAR320_UART1_BASE,
+ .end = SPEAR320_UART1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {SPEAR320_VIRQ_UART1, NO_IRQ},
+};
+
+/* uart2 device registeration */
+struct amba_device spear320_uart2_device = {
+ .dev = {
+ .init_name = "uart2",
+ },
+ .res = {
+ .start = SPEAR320_UART2_BASE,
+ .end = SPEAR320_UART2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {SPEAR320_VIRQ_UART2, NO_IRQ},
+};
+
/* plgpio device registeration */
static struct plgpio_platform_data plgpio_plat_data = {
.gpio_base = 8,
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 7b12f0c..ebc4bb9 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -44,6 +44,8 @@ static struct amba_device *amba_devs[] __initdata = {
&spear3xx_wdt_device,
/* spear320 specific devices */
+ &spear320_uart1_device,
+ &spear320_uart2_device,
};
static struct platform_device *plat_devs[] __initdata = {
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 07/17] ST SPEAr320: Adding support for CAN
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977727.git.viresh.kumar@st.com>
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 2 +
arch/arm/mach-spear3xx/spear320.c | 37 +++++++++++++++++++++++++
arch/arm/mach-spear3xx/spear320_evb.c | 2 +
3 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 8925b7b..e8dfbb5 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -175,6 +175,8 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
/* Add spear320 machine device structure declarations here */
extern struct amba_device spear320_uart1_device;
extern struct amba_device spear320_uart2_device;
+extern struct platform_device spear320_can0_device;
+extern struct platform_device spear320_can1_device;
extern struct platform_device spear320_plgpio_device;
extern struct platform_device spear320_pwm_device;
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 77089a7..3f058c7 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -738,6 +738,43 @@ struct amba_device spear320_uart2_device = {
.irq = {SPEAR320_VIRQ_UART2, NO_IRQ},
};
+/* CAN device registeration */
+static struct resource can0_resources[] = {
+ {
+ .start = SPEAR320_CAN0_BASE,
+ .end = SPEAR320_CAN0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ }, {
+ .start = SPEAR320_VIRQ_CANU,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear320_can0_device = {
+ .name = "c_can_platform",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(can0_resources),
+ .resource = can0_resources,
+};
+
+static struct resource can1_resources[] = {
+ {
+ .start = SPEAR320_CAN1_BASE,
+ .end = SPEAR320_CAN1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+ }, {
+ .start = SPEAR320_VIRQ_CANL,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device spear320_can1_device = {
+ .name = "c_can_platform",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(can1_resources),
+ .resource = can1_resources,
+};
+
/* plgpio device registeration */
static struct plgpio_platform_data plgpio_plat_data = {
.gpio_base = 8,
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index ebc4bb9..f2c3cd3 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -52,6 +52,8 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
/* spear320 specific devices */
+ &spear320_can0_device,
+ &spear320_can1_device,
&spear320_plgpio_device,
&spear320_pwm_device,
};
--
1.7.2.2
^ permalink raw reply related
* [PATCH V6 08/17] ST SPEAr3xx: EMI (External Memory Interface) controller driver
From: Viresh Kumar @ 2011-03-01 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1298977727.git.viresh.kumar@st.com>
From: Vipin Kumar <vipin.kumar@st.com>
Two SPEAr platform SoCs(spear310 and spear320) support an External Memory
Interface controller. This controller is used to interface with
Parallel NOR Flash devices.
This patch adds just the platform code needed for EMI (mainly EMI
initialization). The driver being used is driver/mtd/maps/physmap.c
Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/Makefile | 4 +
arch/arm/mach-spear3xx/emi.c | 98 ++++++++++++++++++++++++
arch/arm/mach-spear3xx/include/mach/emi.h | 61 +++++++++++++++
arch/arm/mach-spear3xx/include/mach/spear310.h | 9 ++
arch/arm/mach-spear3xx/include/mach/spear320.h | 6 ++
arch/arm/mach-spear3xx/spear310_evb.c | 35 +++++++++
arch/arm/mach-spear3xx/spear320_evb.c | 35 +++++++++
7 files changed, 248 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear3xx/emi.c
create mode 100644 arch/arm/mach-spear3xx/include/mach/emi.h
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b248624..d38ae47 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -24,3 +24,7 @@ obj-$(CONFIG_MACH_SPEAR320) += spear320.o
# spear320 boards files
obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
+
+# specific files
+obj-$(CONFIG_MACH_SPEAR310) += emi.o
+obj-$(CONFIG_MACH_SPEAR320) += emi.o
diff --git a/arch/arm/mach-spear3xx/emi.c b/arch/arm/mach-spear3xx/emi.c
new file mode 100644
index 0000000..4d01322
--- /dev/null
+++ b/arch/arm/mach-spear3xx/emi.c
@@ -0,0 +1,98 @@
+/*
+ * arch/arm/mach-spear3xx/emi.c
+ *
+ * EMI (External Memory Interface) file
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Vipin Kumar<vipin.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/mach-types.h>
+#include <mach/emi.h>
+
+int __init emi_init(unsigned long base, u32 bank, u32 width)
+{
+ void __iomem *emi_reg_base;
+ struct clk *clk;
+ int ret;
+ u32 ack_reg, max_banks;
+ /* u32 timeout_reg, irq_reg; */
+
+ /* fixing machine dependent values */
+ if (machine_is_spear310()) {
+ ack_reg = SPEAR310_ACK_REG;
+ max_banks = SPEAR310_EMI_MAX_BANKS;
+ /* timeout_reg = SPEAR310_TIMEOUT_REG; */
+ /* irq_reg = SPEAR310_IRQ_REG; */
+ } else {
+ ack_reg = SPEAR320_ACK_REG;
+ max_banks = SPEAR320_EMI_MAX_BANKS;
+ /* timeout_reg = SPEAR320_TIMEOUT_REG; */
+ /* irq_reg = SPEAR320_IRQ_REG; */
+ }
+
+ if (bank > (max_banks - 1))
+ return -EINVAL;
+
+ emi_reg_base = ioremap(base, EMI_REG_SIZE);
+ if (!emi_reg_base)
+ return -ENOMEM;
+
+ clk = clk_get(NULL, "emi");
+ if (IS_ERR(clk)) {
+ iounmap(emi_reg_base);
+ return PTR_ERR(clk);
+ }
+
+ ret = clk_enable(clk);
+ if (ret) {
+ iounmap(emi_reg_base);
+ return ret;
+ }
+
+ /*
+ * Note: These are relaxed NOR device timings. Nor devices on spear
+ * eval machines are working fine with these timings. Specific board
+ * files can optimize these timings based on devices found on board.
+ */
+ writel(0x10, emi_reg_base + (EMI_BANK_REG_SIZE * bank) + TAP_REG);
+ writel(0x05, emi_reg_base + (EMI_BANK_REG_SIZE * bank) + TSDP_REG);
+ writel(0x0a, emi_reg_base + (EMI_BANK_REG_SIZE * bank) + TDPW_REG);
+ writel(0x0a, emi_reg_base + (EMI_BANK_REG_SIZE * bank) + TDPR_REG);
+ writel(0x05, emi_reg_base + (EMI_BANK_REG_SIZE * bank) + TDCS_REG);
+
+ switch (width) {
+ case EMI_FLASH_WIDTH8:
+ width = EMI_CNTL_WIDTH8;
+ break;
+
+ case EMI_FLASH_WIDTH16:
+ width = EMI_CNTL_WIDTH16;
+ break;
+
+ case EMI_FLASH_WIDTH32:
+ width = EMI_CNTL_WIDTH32;
+ break;
+ default:
+ width = EMI_CNTL_WIDTH8;
+ break;
+ }
+ /* set the data width */
+ writel(width | EMI_CNTL_ENBBYTERW,
+ emi_reg_base + (EMI_BANK_REG_SIZE * bank) + CTRL_REG);
+
+ /* disable all the acks */
+ writel(0x3f, emi_reg_base + ack_reg);
+
+ iounmap(emi_reg_base);
+
+ return 0;
+}
diff --git a/arch/arm/mach-spear3xx/include/mach/emi.h b/arch/arm/mach-spear3xx/include/mach/emi.h
new file mode 100644
index 0000000..c15b12e
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/emi.h
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/emi.h
+ *
+ * EMI macros for SPEAr platform
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Vipin Kumar <vipin.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_EMI_H
+#define __MACH_EMI_H
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+
+#define EMI_FLASH_WIDTH8 1
+#define EMI_FLASH_WIDTH16 2
+#define EMI_FLASH_WIDTH32 4
+
+#define EMI_REG_SIZE 0x100
+#define EMI_BANK_REG_SIZE 0x18
+
+#define TAP_REG (0x0)
+#define TSDP_REG (0x4)
+#define TDPW_REG (0x8)
+#define TDPR_REG (0xC)
+#define TDCS_REG (0x10)
+#define CTRL_REG (0x14)
+
+#if defined(CONFIG_MACH_SPEAR310)
+#define SPEAR310_TIMEOUT_REG (0x90)
+#define SPEAR310_ACK_REG (0x94)
+#define SPEAR310_IRQ_REG (0x98)
+
+#define SPEAR310_EMI_MAX_BANKS 6
+#endif
+
+#if defined(CONFIG_MACH_SPEAR320)
+#define SPEAR320_TIMEOUT_REG (0x60)
+#define SPEAR320_ACK_REG (0x64)
+#define SPEAR320_IRQ_REG (0x68)
+
+#define SPEAR320_EMI_MAX_BANKS 4
+
+#endif
+
+/* Control register definitions */
+#define EMI_CNTL_WIDTH8 (0 << 0)
+#define EMI_CNTL_WIDTH16 (1 << 0)
+#define EMI_CNTL_WIDTH32 (2 << 0)
+#define EMI_CNTL_ENBBYTEW (1 << 2)
+#define EMI_CNTL_ENBBYTER (1 << 3)
+#define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW)
+
+extern int __init emi_init(unsigned long base, u32 bank, u32 width);
+#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index 1567d0da..0780c47 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -18,6 +18,15 @@
#define SPEAR310_NAND_BASE UL(0x40000000)
#define SPEAR310_FSMC_BASE UL(0x44000000)
+#define SPEAR310_EMI_REG_BASE UL(0x4F000000)
+#define SPEAR310_EMI_MEM_0_BASE UL(0x50000000)
+#define SPEAR310_EMI_MEM_1_BASE UL(0x60000000)
+#define SPEAR310_EMI_MEM_2_BASE UL(0x70000000)
+#define SPEAR310_EMI_MEM_3_BASE UL(0x80000000)
+#define SPEAR310_EMI_MEM_4_BASE UL(0x90000000)
+#define SPEAR310_EMI_MEM_5_BASE UL(0xA0000000)
+#define SPEAR310_EMI_MEM_SIZE UL(0x10000000)
+
#define SPEAR310_UART1_BASE UL(0xB2000000)
#define SPEAR310_UART2_BASE UL(0xB2080000)
#define SPEAR310_UART3_BASE UL(0xB2100000)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 8cfa83f..30ea941 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -17,6 +17,12 @@
#define __MACH_SPEAR320_H
#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
+#define SPEAR320_EMI_MEM_0_BASE UL(0x44000000)
+#define SPEAR320_EMI_MEM_1_BASE UL(0x45000000)
+#define SPEAR320_EMI_MEM_2_BASE UL(0x46000000)
+#define SPEAR320_EMI_MEM_3_BASE UL(0x47000000)
+#define SPEAR320_EMI_MEM_SIZE UL(0x01000000)
+
#define SPEAR320_FSMC_BASE UL(0x4C000000)
#define SPEAR320_NAND_BASE UL(0x50000000)
#define SPEAR320_I2S_BASE UL(0x60000000)
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 36fb611..8d5becb 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -13,9 +13,40 @@
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <mach/emi.h>
#include <mach/generic.h>
#include <mach/hardware.h>
+#define PARTITION(n, off, sz) {.name = n, .offset = off, .size = sz}
+static struct mtd_partition partition_info[] = {
+ PARTITION("X-loader", 0, 1 * 0x20000),
+ PARTITION("U-Boot", 0x20000, 3 * 0x20000),
+ PARTITION("Kernel", 0x80000, 24 * 0x20000),
+ PARTITION("Root File System", 0x380000, 84 * 0x20000),
+};
+
+/* emi nor flash resources registeration */
+static struct resource emi_nor_resources[] = {
+ {
+ .start = SPEAR310_EMI_MEM_0_BASE,
+ .end = SPEAR310_EMI_MEM_0_BASE + SPEAR310_EMI_MEM_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct physmap_flash_data emi_norflash_data = {
+ .parts = partition_info,
+ .nr_parts = ARRAY_SIZE(partition_info),
+ .width = 4,
+};
+static struct platform_device spear310_emi_nor_device = {
+ .name = "physmap-flash",
+ .id = -1,
+ .dev.platform_data = &emi_norflash_data,
+ .resource = emi_nor_resources,
+ .num_resources = ARRAY_SIZE(emi_nor_resources),
+};
+
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
@@ -58,6 +89,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
/* spear310 specific devices */
+ &spear310_emi_nor_device,
&spear310_plgpio_device,
};
@@ -68,6 +100,9 @@ static void __init spear310_evb_init(void)
/* call spear310 machine init function */
spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
+ /* Initialize emi regiters */
+ emi_init(SPEAR310_EMI_REG_BASE, 0, EMI_FLASH_WIDTH32);
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index f2c3cd3..8addd5f 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -13,9 +13,40 @@
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <mach/emi.h>
#include <mach/generic.h>
#include <mach/hardware.h>
+#define PARTITION(n, off, sz) {.name = n, .offset = off, .size = sz}
+static struct mtd_partition partition_info[] = {
+ PARTITION("X-loader", 0, 1 * 0x20000),
+ PARTITION("U-Boot", 0x20000, 3 * 0x20000),
+ PARTITION("Kernel", 0x80000, 24 * 0x20000),
+ PARTITION("Root File System", 0x380000, 84 * 0x20000),
+};
+
+/* emi nor flash resources registeration */
+static struct resource emi_nor_resources[] = {
+ {
+ .start = SPEAR320_EMI_MEM_0_BASE,
+ .end = SPEAR320_EMI_MEM_0_BASE + SPEAR320_EMI_MEM_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct physmap_flash_data emi_norflash_data = {
+ .parts = partition_info,
+ .nr_parts = ARRAY_SIZE(partition_info),
+ .width = 2,
+};
+static struct platform_device spear320_emi_nor_device = {
+ .name = "physmap-flash",
+ .id = -1,
+ .dev.platform_data = &emi_norflash_data,
+ .resource = emi_nor_resources,
+ .num_resources = ARRAY_SIZE(emi_nor_resources),
+};
+
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
@@ -54,6 +85,7 @@ static struct platform_device *plat_devs[] __initdata = {
/* spear320 specific devices */
&spear320_can0_device,
&spear320_can1_device,
+ &spear320_emi_nor_device,
&spear320_plgpio_device,
&spear320_pwm_device,
};
@@ -66,6 +98,9 @@ static void __init spear320_evb_init(void)
spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
ARRAY_SIZE(pmx_devs));
+ /* Initialize emi regiters */
+ emi_init(SPEAR320_EMI_CTRL_BASE, 0, EMI_FLASH_WIDTH16);
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
--
1.7.2.2
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