* [PATCH] ARM: S5PC210: add support for i2c PMICs on Universal_C210 board
From: Kyungmin Park @ 2011-03-03 2:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215113504.GF4152@n2100.arm.linux.org.uk>
On Tue, Feb 15, 2011 at 8:35 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Tue, Feb 15, 2011 at 11:59:15AM +0100, Marek Szyprowski wrote:
>> ?#include <mach/map.h>
>> +#include <mach/gpio.h>
>
> Need I say anything about this?
Hi Russell,
How about to prevent it as compiler error? It's frequent mistake.
At each mach/gpio.h
#ifndef __LINUX_GPIO_H
#error "You should include <linux/gpio.h> instead of <mach/gpio.h>."
#endif
Thank you,
Kyungmin Park
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH v2] ARM: S5PC210: add support for i2c PMICs on Universal_C210 board
From: Kukjin Kim @ 2011-03-03 2:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297774241-16149-1-git-send-email-m.szyprowski@samsung.com>
Marek Szyprowski wrote:
>
> This patch adds basic definitions for MAX8952 & LP3974 (MAX8998
> compatible) PMICs for UniversalC210 board. Power consumers for the
> device drivers will be added later. These two PMICs occupy I2C5 bus.
>
Hi Marek,
Could you please re-work this based on Exynos4?
And there are really small comments below :)
(snip)
> +static struct regulator_init_data lp3974_buck1_data = {
> + .constraints = {
> + .name = "VINT_1.1V",
> + .min_uV = 750000,
> + .max_uV = 1500000,
> + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
> + REGULATOR_CHANGE_STATUS,
> + .boot_on = 1,
> + .state_mem = {
> + .enabled = 0,
^
> + .disabled = 1,
^
Do we need "disabled" with "enabled"?
(snip)
> +static struct max8998_platform_data universal_lp3974_pdata = {
> + .num_regulators = ARRAY_SIZE(lp3974_regulators),
> + .regulators = lp3974_regulators,
> + .buck1_voltage1 = 1100000, /* INT */
> + .buck1_voltage2 = 1000000,
> + .buck1_voltage3 = 1100000,
> + .buck1_voltage4 = 1000000,
> + .buck1_set1 = S5PV310_GPX0(5),
^^^^^^^^^^^^^
tab?
> + .buck1_set2 = S5PV310_GPX0(6),
^^^^^^^^^^^^^
same.
> + .buck2_voltage1 = 1200000, /* G3D */
> + .buck2_voltage2 = 1100000,
> + .buck1_default_idx = 0,
> + .buck2_set3 = S5PV310_GPE2(0),
^^^^^^^^^^^^^
same.
> + .buck2_default_idx = 0,
> + .wakeup = true,
> +};
(snip)
> @@ -223,6 +661,9 @@ static void __init universal_machine_init(void)
> i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
> i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
>
> + s3c_i2c5_set_platdata(NULL);
> + i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5));
How about "i2c5_devs" like others?
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [PATCHv2] omap:mailbox: resolve hang issue
From: Tony Lindgren @ 2011-03-03 1:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299104058-28565-1-git-send-email-x0095078@ti.com>
* Armando Uribe <x0095078@ti.com> [110302 13:54]:
> From: Hari Kanigeri <h-kanigeri2@ti.com>
>
> omap4 interrupt disable bits is different. On rx kfifo full, the mbox rx
> interrupts wasn't getting disabled, and this is causing the rcm stress tests
> to hang.
>
> Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
> Signed-off-by: Armando Uribe <x0095078@ti.com>
> Signed-off-by: Fernando Guzman Lugo <fernando.lugo@ti.com>
Should we merge this as a fix for the 2.6.38 still?
Tony
> ---
> arch/arm/mach-omap2/mailbox.c | 10 ++++++----
> 1 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
> index 394413d..011ca50 100644
> --- a/arch/arm/mach-omap2/mailbox.c
> +++ b/arch/arm/mach-omap2/mailbox.c
> @@ -193,10 +193,12 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
> omap_mbox_type_t irq)
> {
> struct omap_mbox2_priv *p = mbox->priv;
> - u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
> - l = mbox_read_reg(p->irqdisable);
> - l &= ~bit;
> - mbox_write_reg(l, p->irqdisable);
> + u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
> +
> + if (!cpu_is_omap44xx())
> + bit = mbox_read_reg(p->irqdisable) & ~bit;
> +
> + mbox_write_reg(bit, p->irqdisable);
> }
>
> static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
> --
> 1.7.0.4
>
^ permalink raw reply
* [PATCH 0/6] omap3: pm: Fixes for low power code
From: Kevin Hilman @ 2011-03-03 1:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298294365-30770-1-git-send-email-santosh.shilimkar@ti.com>
Hi Santosh,
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> The series does below fixes to the omap3 low power code.
> 1. Use supported ARMv7 instructions instead of the legacy ones
> 2. Fix the MMU on sequence
> 3. Fix the cache flush scenario when only L1 lost.
> 4. Remove all un-necessary context save registers
> 5. Disable C-bit before cache clean
> 6. Use set_cr() exported API instead of custom one.
Look like good cleanups, thanks.
> It's generated against mainline and tested with OMAP3630 ZOOM3.
> 1. Renetion and off-mode mode in suspend - ok.
> 2. Retention in idle - ok
Testing this series along with other PM changes queued up for mainline
(my pm-core branch), this doesn't work for me on 3630/Zoom3 (but works
fine on 3430/n900.)
Here's what I did using omap2plus_defconfig + enabling CPUidle
First tested suspend:
echo 4 > /debug/pm_debug/wakeup_timer_seconds
echo mem > /sys/power/state
then, setup UART idle/wakeup:
echo 5 > /sys/devices/platform/omap/omap_uart.0/sleep_timeout
echo 5 > /sys/devices/platform/omap/omap_uart.1/sleep_timeout
echo 5 > /sys/devices/platform/omap/omap_uart.2/sleep_timeout
echo 5 > /sys/devices/platform/omap/omap_uart.3/sleep_timeout
echo enabled > /sys/devices/platform/serial8250.0/tty/ttyS0/power/wakeup
then enabled idle:
echo 1 > /debug/pm_debug/sleep_while_idle
As soon as I do this, it hangs.
Without your series, it's working fine for me. Only after merging your
series it hangs.
Kevin
> The following changes since commit 85e2efbb1db9a18d218006706d6e4fbeb0216213:
> Linus Torvalds (1):
> Linux 2.6.38-rc5
>
> Santosh Shilimkar (6):
> omap3: pm: Use amrv7 supported instructions instead of legacy cp15
> ones
> omap3: pm: Fix the mmu on sequence in the asm code
> omap3: pm: Allow the cache clean when L1 is lost.
> omap3: pm: Remove un-necessary cp15 registers form low power cpu
> context
> omap3: pm: Clear the SCTLR C bit in asm code to prevent data cache
> allocation
> omap3: pm: Use exported set_cr() instead of a custom one.
>
> arch/arm/mach-omap2/pm34xx.c | 7 +-
> arch/arm/mach-omap2/sleep34xx.S | 223 ++++++++++++++-------------------------
> 2 files changed, 78 insertions(+), 152 deletions(-)
^ permalink raw reply
* [PATCH] ARM: mx51: Print silicon revision on boot
From: Fabio Estevam @ 2011-03-03 1:12 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/mach-mx5/clock-mx51-mx53.c | 1 +
arch/arm/mach-mx5/cpu.c | 21 +++++++++++++++++++++
arch/arm/plat-mxc/include/mach/mx51.h | 1 +
3 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 652ace4..1282a60 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1510,6 +1510,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
clk_enable(&iim_clk);
mx51_revision();
+ mx51_display_revision();
clk_disable(&iim_clk);
/* move usb_phy_clk to 24MHz */
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index df46b5e..565ed4d 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -51,6 +51,27 @@ int mx51_revision(void)
}
EXPORT_SYMBOL(mx51_revision);
+void mx51_display_revision(void)
+{
+ int rev;
+ char *srev;
+ rev = mx51_revision();
+
+ switch (rev) {
+ case IMX_CHIP_REVISION_2_0:
+ srev = "2.0";
+ break;
+ case IMX_CHIP_REVISION_3_0:
+ srev = "3.0";
+ break;
+ default:
+ return IMX_CHIP_REVISION_UNKNOWN;
+ srev = "unknown";
+ }
+ printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev);
+}
+EXPORT_SYMBOL(mx51_display_revision);
+
#ifdef CONFIG_NEON
/*
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 1eb339e..dede19a 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -347,6 +347,7 @@
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern int mx51_revision(void);
+extern void mx51_display_revision(void);
#endif
/* tape-out 1 defines */
--
1.6.0.4
^ permalink raw reply related
* [PATCH] ldp: Fix regulator mapping for ads7846 TS controller
From: Tony Lindgren @ 2011-03-03 1:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298552202-28307-1-git-send-email-rnayak@ti.com>
* Rajendra Nayak <rnayak@ti.com> [110224 04:54]:
> On the OMAP3430LDP board, the ads7846 touchscreen controller
> is powered by VAUX1 regulator (supplying 3.0v).
> Fix this mapping in the board file, and hence prevent
> the ads7846 driver init to fail with the below error..
>
> ads7846 spi1.0: unable to get regulator: -19
Applying for the merge window.
Tony
^ permalink raw reply
* [PATCH] perf: add OMAP support for the new power events
From: Kevin Hilman @ 2011-03-03 0:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298052645-4164-1-git-send-email-j-pihet@ti.com>
Hi Jean,
jean.pihet at newoldbits.com writes:
> From: Jean Pihet <j-pihet@ti.com>
>
> The patch adds the new power management trace points for
> the OMAP architecture.
There are some other core clock/powerdomain changes queued for 2.6.39
ahead of this that conflict with your patch.
Could you rebase this against my pm-core branch where these other
changes are queued?
Thanks,
Kevin
> The trace points are for:
> - default idle handler. Since the cpuidle framework is
> instrumented in the generic way there is no need to
> add trace points in the OMAP specific cpuidle handler;
> - cpufreq (DVFS),
> - SoC clocks changes (enable, disable, set_rate),
> - power domain states: the desired target state and -if different-
> the actually hit state.
>
> Because of the generic nature of the changes, OMAP3 and OMAP4 are supported.
>
> Tested on OMAP3 with suspend/resume, cpuidle, basic DVFS.
>
> Signed-off-by: Jean Pihet <j-pihet@ti.com>
> ---
> arch/arm/mach-omap2/clock.c | 8 +++++++-
> arch/arm/mach-omap2/pm34xx.c | 7 +++++++
> arch/arm/mach-omap2/powerdomain.c | 26 +++++++++++++++++++++++---
> 3 files changed, 37 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index 2a2f152..72af75d 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -22,7 +22,9 @@
> #include <linux/clk.h>
> #include <linux/io.h>
> #include <linux/bitops.h>
> +#include <trace/events/power.h>
>
> +#include <asm/cpu.h>
> #include <plat/clock.h>
> #include "clockdomain.h"
> #include <plat/cpu.h>
> @@ -261,6 +263,7 @@ void omap2_clk_disable(struct clk *clk)
>
> pr_debug("clock: %s: disabling in hardware\n", clk->name);
>
> + trace_clock_disable(clk->name, 0, smp_processor_id());
> clk->ops->disable(clk);
>
> if (clk->clkdm)
> @@ -312,6 +315,7 @@ int omap2_clk_enable(struct clk *clk)
> }
> }
>
> + trace_clock_enable(clk->name, 1, smp_processor_id());
> ret = clk->ops->enable(clk);
> if (ret) {
> WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret);
> @@ -349,8 +353,10 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
> pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
>
> /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
> - if (clk->set_rate)
> + if (clk->set_rate) {
> + trace_clock_set_rate(clk->name, rate, smp_processor_id());
> ret = clk->set_rate(clk, rate);
> + }
>
> return ret;
> }
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 2f864e4..d1cc3f4 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -29,6 +29,7 @@
> #include <linux/delay.h>
> #include <linux/slab.h>
> #include <linux/console.h>
> +#include <trace/events/power.h>
>
> #include <plat/sram.h>
> #include "clockdomain.h"
> @@ -519,8 +520,14 @@ static void omap3_pm_idle(void)
> if (omap_irq_pending() || need_resched())
> goto out;
>
> + trace_power_start(POWER_CSTATE, 1, smp_processor_id());
> + trace_cpu_idle(1, smp_processor_id());
> +
> omap_sram_idle();
>
> + trace_power_end(smp_processor_id());
> + trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
> +
> out:
> local_fiq_enable();
> local_irq_enable();
> diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
> index eaed0df..1495eed 100644
> --- a/arch/arm/mach-omap2/powerdomain.c
> +++ b/arch/arm/mach-omap2/powerdomain.c
> @@ -19,12 +19,15 @@
> #include <linux/list.h>
> #include <linux/errno.h>
> #include <linux/string.h>
> +#include <trace/events/power.h>
> +
> #include "cm2xxx_3xxx.h"
> #include "prcm44xx.h"
> #include "cm44xx.h"
> #include "prm2xxx_3xxx.h"
> #include "prm44xx.h"
>
> +#include <asm/cpu.h>
> #include <plat/cpu.h>
> #include "powerdomain.h"
> #include "clockdomain.h"
> @@ -32,6 +35,8 @@
>
> #include "pm.h"
>
> +#define PWRDM_TRACE_STATES_FLAG (1<<31)
> +
> enum {
> PWRDM_STATE_NOW = 0,
> PWRDM_STATE_PREV,
> @@ -130,8 +135,7 @@ static void _update_logic_membank_counters(struct powerdomain *pwrdm)
> static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
> {
>
> - int prev;
> - int state;
> + int prev, state, trace_state = 0;
>
> if (pwrdm == NULL)
> return -EINVAL;
> @@ -148,6 +152,17 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
> pwrdm->state_counter[prev]++;
> if (prev == PWRDM_POWER_RET)
> _update_logic_membank_counters(pwrdm);
> + /*
> + * If the power domain did not hit the desired state,
> + * generate a trace event with both the desired and hit states
> + */
> + if (state != prev) {
> + trace_state = (PWRDM_TRACE_STATES_FLAG |
> + ((state & OMAP_POWERSTATE_MASK) << 8) |
> + ((prev & OMAP_POWERSTATE_MASK) << 0));
> + trace_power_domain_target(pwrdm->name, trace_state,
> + smp_processor_id());
> + }
> break;
> default:
> return -EINVAL;
> @@ -406,8 +421,13 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
> pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
> pwrdm->name, pwrst);
>
> - if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst)
> + if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
> + /* Trace the pwrdm desired target state */
> + trace_power_domain_target(pwrdm->name, pwrst,
> + smp_processor_id());
> + /* Program the pwrdm desired target state */
> ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
> + }
>
> return ret;
> }
^ permalink raw reply
* [PATCH] arm: omap: fix section mismatch warning
From: Tony Lindgren @ 2011-03-03 0:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299105706-2970-1-git-send-email-tom.leiming@gmail.com>
* tom.leiming at gmail.com <tom.leiming@gmail.com> [110302 06:41]:
> From: Ming Lei <tom.leiming@gmail.com>
>
> WARNING: arch/arm/plat-omap/built-in.o(.data+0x6d4): Section mismatch in reference from the variable omap_driver to the function .init.text:omap_cpu_init()
> The variable omap_driver references
> the function __init omap_cpu_init()
> If the reference is valid then annotate the
> variable with __init* or __refdata (see linux/init.h) or name the variable:
> *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
Thanks I'll queue this for the upcoming merge window.
Tony
^ permalink raw reply
* [PATCH V4] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL
From: Kevin Hilman @ 2011-03-03 0:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297756738-2696-1-git-send-email-shweta.gulati@ti.com>
Shweta Gulati <shweta.gulati@ti.com> writes:
> From: Thara Gopinath <thara@ti.com>
>
> Voltage control on TWL can be done using VMODE/I2C1/I2C_SR.
> Since almost all platforms use I2C_SR on omap3, omap3_twl_init by
> default expects that OMAP's I2C_SR is plugged in to TWL's I2C
> and calls omap3_twl_set_sr_bit. On platforms where I2C_SR is not connected,
> the board files are expected to call omap3_twl_set_sr_bit(false) to
> ensure that I2C_SR path is not set for voltage control and prevent
> the default behavior of omap3_twl_init.
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Thara Gopinath <thara@ti.com>
> Signed-off-by: Shweta Gulati <shweta.gulati@ti.com>
> Cc: linux-arm-kernel at lists.infradead.org
queueing this one for 2.6.39 (branch: for_2.6.39/pm-misc)
Kevin
> ---
> This patch is based on LO PM Branch and Smartreflex has been
> tested on OMAP3430 SDP, OMAP3630 SDP and boot tested on
> OMAP2430 SDP.
>
> arch/arm/mach-omap2/omap_twl.c | 60 ++++++++++++++++++++++++++++++++++++++++
> arch/arm/mach-omap2/pm.h | 1 +
> 2 files changed, 61 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
> index 00e1d2b..b341c36 100644
> --- a/arch/arm/mach-omap2/omap_twl.c
> +++ b/arch/arm/mach-omap2/omap_twl.c
> @@ -59,8 +59,15 @@
>
> static bool is_offset_valid;
> static u8 smps_offset;
> +/*
> + * Flag to ensure Smartreflex bit in TWL
> + * being cleared in board file is not overwritten.
> + */
> +static bool __initdata twl_sr_enable_autoinit;
>
> +#define TWL4030_DCDC_GLOBAL_CFG 0x06
> #define REG_SMPS_OFFSET 0xE0
> +#define SMARTREFLEX_ENABLE BIT(3)
>
> static unsigned long twl4030_vsel_to_uv(const u8 vsel)
> {
> @@ -269,6 +276,18 @@ int __init omap3_twl_init(void)
> omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
> }
>
> + /*
> + * The smartreflex bit on twl4030 specifies if the setting of voltage
> + * is done over the I2C_SR path. Since this setting is independent of
> + * the actual usage of smartreflex AVS module, we enable TWL SR bit
> + * by default irrespective of whether smartreflex AVS module is enabled
> + * on the OMAP side or not. This is because without this bit enabled,
> + * the voltage scaling through vp forceupdate/bypass mechanism of
> + * voltage scaling will not function on TWL over I2C_SR.
> + */
> + if (!twl_sr_enable_autoinit)
> + omap3_twl_set_sr_bit(true);
> +
> voltdm = omap_voltage_domain_lookup("mpu");
> omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
>
> @@ -277,3 +296,44 @@ int __init omap3_twl_init(void)
>
> return 0;
> }
> +
> +/**
> + * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
> + * @enable: enable SR mode in twl or not
> + *
> + * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
> + * voltage scaling through OMAP SR works. Else, the smartreflex bit
> + * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
> + * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
> + * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
> + * in those scenarios this bit is to be cleared (enable = false).
> + *
> + * Returns 0 on sucess, error is returned if I2C read/write fails.
> + */
> +int __init omap3_twl_set_sr_bit(bool enable)
> +{
> + u8 temp;
> + int ret;
> + if (twl_sr_enable_autoinit)
> + pr_warning("%s: unexpected multiple calls\n", __func__);
> +
> + ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
> + TWL4030_DCDC_GLOBAL_CFG);
> + if (ret)
> + goto err;
> +
> + if (enable)
> + temp |= SMARTREFLEX_ENABLE;
> + else
> + temp &= ~SMARTREFLEX_ENABLE;
> +
> + ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
> + TWL4030_DCDC_GLOBAL_CFG);
> + if (!ret) {
> + twl_sr_enable_autoinit = true;
> + return 0;
> + }
> +err:
> + pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
> + return ret;
> +}
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 39580e6..797bfd1 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -127,6 +127,7 @@ static inline void omap_enable_smartreflex_on_init(void) {}
> #ifdef CONFIG_TWL4030_CORE
> extern int omap3_twl_init(void);
> extern int omap4_twl_init(void);
> +extern int omap3_twl_set_sr_bit(bool enable);
> #else
> static inline int omap3_twl_init(void)
> {
^ permalink raw reply
* [PATCHv1] ARM: imx: Add support for low power suspend on MX51.
From: Thomas Gleixner @ 2011-03-02 23:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110302215238.GK22310@pengutronix.de>
Uwe,
On Wed, 2 Mar 2011, Uwe Kleine-K?nig wrote:
> On Wed, Mar 02, 2011 at 11:17:58AM -0600, Dinh.Nguyen at freescale.com wrote:
> > From: Dinh Nguyen <Dinh.Nguyen@freescale.com>
> > --- /dev/null
> > +++ b/arch/arm/mach-mx5/pm.c
> I'd like to have that called pm-imx51.c
And I'd like to have a pony.
> > + ccm_clpcr |= (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET);
> the parentheses aren't needed here
Could you finally provide a patch to checkpatch.pl or git commit which
resolves that issue once and forever ?
Not to mention the fact, that those parentheses are not disturbing the
readability of that code at all.
> > + ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET);
> ditto
Ditto.
> > +static int __init mx5_pm_init(void)
> I'd prefer to have that called by imx51_init_early.
And the reason is?
1) your personal preference
2) there is some useful technical reason
If #1, then this comment was just waste of electrons
If #2, you failed to provide some reasonable explanation
Again, I'd like to have a pony.
Seriously, while all of us admire your invaluable skills of running
scripts over patches and kernel code, that kind of review you are
trying to provide is utterly useless.
1) The patch itself has been questioned about its correctness hours
before you added the output of your secret script. It was already
reported to be non functional. So what's the value of adding
scriptable review to it?
2) As long as you do not see the most obvious functional problems with
a patch please spare your script computing power and the bandwidth
you are consuming by your futile attempts to gain a profile as a
patch reviewer.
Just for the record. The obvious bug with this code is this:
> > + plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
> > + | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
> > + arm_srpgcr |= MXC_SRPGCR_PCR;
> > +
> > + __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
> > + __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
> > + __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
> > + __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
> > +
> > + if (tzic_enable_wake(0) != 0)
> > + return -EAGAIN;
It happily returns here with -EAGAIN w/o undoing the already committed
changes which are preparatory to the tzic_enable_wake() check.
I might be wrong as usual, but if this is cleaned up by the calling
code magically then the "return -EINVAL"; lacks a big fat
comment. While such an omission is not a triggerable bug it documents
the lack of tought and taste by creating asymetric mechanisms w/o the
courtesy to document them properly. Even if documented, asymetric
interfaces are crap most of the time.
> > + cpu_do_idle();
> > + return 0;
> > +}
Thanks,
tglx
^ permalink raw reply
* [PATCH 00/17] omap4: pm: suspend, hotplug and cpuilde support
From: Kevin Hilman @ 2011-03-02 23:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298112158-28469-1-git-send-email-santosh.shilimkar@ti.com>
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> This series adds OMAP4 suspend and cpuidle support till MPU subsystem
> (MPUSS) off-mode. The suspend on SMP machines uses cpu-hotplug
> infrastructure to take down the non-boot CPUs. We put secondary
> CPU(CPU1 in OMAP4) to OFF state via cpu-hotplug.
> In cpuidle too, low power states are attempted only when the
> CPU1 is put to OFF state via cpu-hotplug because of hardware
> constraints.
Minor nit on patch subjects: both OMAP and PM are acronyms, please
capitalize.
Also, can you rebase this on Paul's integration-2.6.39 branch? There
are several things in this series that conflict with changes there.
Thanks,
Kevin
^ permalink raw reply
* [PATCH 07/17] omap4: pm: CPU1 wakeup workaround form Low power modes
From: Kevin Hilman @ 2011-03-02 23:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298112158-28469-8-git-send-email-santosh.shilimkar@ti.com>
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> The SGI(Software Generated Interrupts) are not wakeup capable from
> low power states. This is known limitation on OMAP4 and needs to be
> worked around by using software forced clockdomain wake-up. CPU0 forces
> the CPU1 clockdomain to software force wakeup. After the wakeup, CPU1
> restores its clockdomain hardware supervised mode.
>
> More details can be found in OMAP4430 TRM - Version J
> Section :
> 4.3.4.2 Power States of CPU0 and CPU1
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Reviewed-by: Kevin Hilman <khilman@ti.com>
One other thing...
in subject: s/form/from/
Kevin
^ permalink raw reply
* [PATCH 16/17] omap4: cpuidle: Allow debugfs control through enable_off_mode
From: Kevin Hilman @ 2011-03-02 23:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298112158-28469-17-git-send-email-santosh.shilimkar@ti.com>
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> Only MPU OFF and RET is controllable. CORE state is blocked
> at ON state till the CORE RET support is added.
-ECONFUSED
None of the C-states currently have CORE != ON:
./cpuidle44xx.c:219: omap4_power_states[OMAP4_STATE_C1].core_state = PWRDM_POWER_ON;
./cpuidle44xx.c:240: omap4_power_states[OMAP4_STATE_C2].core_state = PWRDM_POWER_ON;
./cpuidle44xx.c:262: omap4_power_states[OMAP4_STATE_C3].core_state = PWRDM_POWER_ON;
./cpuidle44xx.c:284: omap4_power_states[OMAP4_STATE_C4].core_state = PWRDM_POWER_ON;
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Reviewed-by: Kevin Hilman <khilman@ti.com>
> ---
> arch/arm/mach-omap2/cpuidle44xx.c | 30 ++++++++++++++++++++++++++++++
> arch/arm/mach-omap2/pm.h | 1 +
> arch/arm/mach-omap2/pm44xx.c | 4 ++++
> 3 files changed, 35 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
> index e887eb5..4207862 100644
> --- a/arch/arm/mach-omap2/cpuidle44xx.c
> +++ b/arch/arm/mach-omap2/cpuidle44xx.c
> @@ -170,6 +170,31 @@ static int omap4_enter_idle_bm(struct cpuidle_device *dev,
> }
>
> /**
> + * omap4_cpuidle_update_states() - Update the cpuidle states
> + * @mpu_deepest_state: Enable states upto and including this for mpu domain
> + * @core_deepest_state: Enable states upto and including this for core domain
> + *
> + * This goes through the list of states available and enables and disables the
> + * validity of C states based on deepest state that can be achieved for the
> + * variable domain
> + */
> +void omap4_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
> +{
> + int i;
> +
> + for (i = OMAP4_STATE_C1; i < OMAP4_MAX_STATES; i++) {
> + struct omap4_processor_cx *cx = &omap4_power_states[i];
> +
> + if ((cx->mpu_state >= mpu_deepest_state) &&
> + (cx->core_state >= core_deepest_state)) {
> + cx->valid = 1;
> + } else {
> + cx->valid = 0;
> + }
> + }
> +}
Also, as mentioned in a previous patch, for OMAP4 I'd like to move away
from this approach to updating the states and rather use the ->prepare
hook along with the ignore flag.
> +/**
> * omap4_init_power_states - Initialises the OMAP4 specific C states.
> *
> */
> @@ -325,6 +350,11 @@ int __init omap4_idle_init(void)
> }
> }
>
> + if (enable_off_mode)
> + omap4_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
> + else
> + omap4_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
> +
> return 0;
> }
> #else
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index ce848b0..4df89d1 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -77,6 +77,7 @@ extern u32 sleep_while_idle;
>
> #if defined(CONFIG_CPU_IDLE)
> extern void omap3_cpuidle_update_states(u32, u32);
> +extern void omap4_cpuidle_update_states(u32, u32);
> #endif
>
> #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> index 628242d..6244ab2 100644
> --- a/arch/arm/mach-omap2/pm44xx.c
> +++ b/arch/arm/mach-omap2/pm44xx.c
> @@ -183,6 +183,10 @@ void omap4_pm_off_mode_enable(int enable)
> else
> state = PWRDM_POWER_RET;
>
> +#ifdef CONFIG_CPU_IDLE
> + omap4_cpuidle_update_states(state, PWRDM_POWER_ON);
> +#endif
> +
> list_for_each_entry(pwrst, &pwrst_list, node) {
> /* FIXME: Remove this check when core retention is supported */
> if (!strcmp(pwrst->pwrdm->name, "mpu_pwrdm")) {
^ permalink raw reply
* [PATCH 14/17] omap4: cpuidle: Add MPUSS RET OFF states
From: Kevin Hilman @ 2011-03-02 23:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298112158-28469-15-git-send-email-santosh.shilimkar@ti.com>
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> This patch adds MPUSS low power states in cpuidle.
>
> C1 - CPU0 ON + CPU1 ON/OFF + MPU ON + CORE ON
> C2 - CPU0 ON + CPU1 OFF + MPU ON + CORE ON
> C3 - CPU0 OFF + CPU1 OFF + MPU CSWR + CORE ON
> C4 - CPU0 OFF + CPU1 OFF + MPU OFF + CORE ON
>
> MPU OSWR isn't supported yet. To support OSWR, power domain context
> registers needs to be managed which are not supported yet. A patch
> to address this was submitted but it's not ready for merge yet because
> it was not addressing all OMAP4 power domain context registers.
> More info on this issue:
> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg38667.html
>
> OMAP4 powerdomain INACTIVE support is also dropped because of inconsistency
> of it with OMAP3. More information on this thread.
> http://www.spinics.net/lists/linux-omap/msg45370.html
>
> CORE low power states and associated latencies will be updated as part
> along with chip retention support.
>
> On OMAP4 because of hardware constraints, no low power states are
> targeted when both CPUs are online and in SMP mode. The low power
> states are attempted only when secondary CPU gets offline to OFF
> through hotplug infrastructure.
>
> Thanks to Nicole Chalhoub <n-chalhoub@ti.com> for doing exhaustive
> C-state latency profiling.
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Reviewed-by: Kevin Hilman <khilman@ti.com>
> ---
> arch/arm/mach-omap2/cpuidle44xx.c | 190 ++++++++++++++++++++++++++++++++++---
> 1 files changed, 176 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
> index 6c3c69d..aa1584e 100644
> --- a/arch/arm/mach-omap2/cpuidle44xx.c
> +++ b/arch/arm/mach-omap2/cpuidle44xx.c
> @@ -3,6 +3,7 @@
> *
> * Copyright (C) 2011 Texas Instruments, Inc.
> * Rajendra Nayak <rnayak@ti.com>
> + * Santosh Shilimkar <santosh.shilimkar@ti.com>
> *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License version 2 as
> @@ -17,12 +18,21 @@
> #include <mach/omap4-common.h>
>
> #include "pm.h"
> +#include "prm.h"
>
> #ifdef CONFIG_CPU_IDLE
>
> -#define OMAP4_MAX_STATES 1
> -/* C1 - CPUx wfi + MPU inactive + CORE inactive */
> +#define CPUIDLE_FLAG_CHECK_BM 0x10000 /* use omap4_enter_idle_bm() */
> +#define OMAP4_MAX_STATES 4
> +
> +/* C1 - CPU0 ON + CPU1 ON/OFF + MPU ON + CORE ON */
> #define OMAP4_STATE_C1 0
> +/* C2 - CPU0 ON + CPU1 OFF + MPU ON + CORE ON */
> +#define OMAP4_STATE_C2 1
> +/* C3 - CPU0 OFF + CPU1 OFF + MPU CSWR + CORE ON */
> +#define OMAP4_STATE_C3 2
> +/* C4 - CPU0 OFF + CPU1 OFF + MPU OFF + CORE ON */
> +#define OMAP4_STATE_C4 3
>
> struct omap4_processor_cx {
> u8 valid;
> @@ -32,19 +42,44 @@ struct omap4_processor_cx {
> u32 cpu0_state;
> u32 cpu1_state;
> u32 mpu_state;
> + u32 mpu_logic_state;
> u32 core_state;
> + u32 core_logic_state;
> u32 threshold;
> u32 flags;
> + const char *desc;
> };
>
> -struct omap4_processor_cx omap4_power_states[OMAP4_MAX_STATES];
> -struct omap4_processor_cx current_cx_state;
> +static struct omap4_processor_cx omap4_power_states[OMAP4_MAX_STATES];
> +static struct powerdomain *mpu_pd, *cpu1_pd, *core_pd;
>
> +/*
> + * FIXME: Full latenecy numbers needs to be updated as part of
> + * cpuidle CORE retention support.
> + * Currently only MPUSS latency numbers are added based on
> + * measurements done internally. The numbers for MPUSS are
> + * not board dependent and hence set directly here instead of
> + * passing it from board files.
> + */
> static struct cpuidle_params cpuidle_params_table[] = {
> - /* C1 */
> - {1, 2, 2, 5},
> + /* C1 - CPU0 WFI + CPU1 ON/OFF + MPU ON + CORE ON */
Above comments say 'CPU0 ON' intead of WFI. Make this consistent.
Also, according to the code, CPU1 is always programmed to OFF.
That being the case, what's the difference between C1 and C2?
> + {1, 2, 2, 5},
> + /* C2 - CPU0 ON + CPU1 OFF + MPU ON + CORE ON */
> + {1, 140, 160, 300},
> + /* C3 - CPU0 OFF + CPU1 OFF + MPU CSWR + CORE ON */
> + {1, 200, 300, 700},
> + /* C4 - CPU0 OFF + CPU1 OFF + MPU OFF + CORE ON */
> + {1, 1400, 600, 5000},
> };
>
> +DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
> +
> +static int omap4_idle_bm_check(void)
The 'bm' terminology here is from legacy x86-based CPUidle code (for
bus-master.) Let's just call this 'activity' check.
> +{
> + /* FIXME: Populate this with CORE retention support */
> + return 0;
> +}
How about just leaving this function out altogether until it's needed.
Also leave out the #define CPUIDLE_FLAG_CHECK_BM for now.
I think we may be able to do OMAP4 a little smarter than we've done
OMAP3 using the ->prepare hook of struct cpuidle_device, and get rid of
this 'bm' check. More on that below...
> /**
> * omap4_enter_idle - Programs OMAP4 to enter the specified state
> * @dev: cpuidle device
> @@ -57,7 +92,9 @@ static struct cpuidle_params cpuidle_params_table[] = {
> static int omap4_enter_idle(struct cpuidle_device *dev,
> struct cpuidle_state *state)
> {
> + struct omap4_processor_cx *cx = cpuidle_get_statedata(state);
> struct timespec ts_preidle, ts_postidle, ts_idle;
> + u32 cpu1_state;
>
> /* Used to keep track of the total time in idle */
> getnstimeofday(&ts_preidle);
> @@ -65,28 +102,74 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
> local_irq_disable();
> local_fiq_disable();
>
> - cpu_do_idle();
> + /*
> + * Special hardware/software considerations:
> + * 1. Do only WFI for secondary CPU(non-boot - CPU1).
> + * Secondary cores are taken down only via hotplug path.
Then why even create a 'struct cpuidle_device' for the non-boot CPUs?
If you only create a cpuidle_device for the boot CPU, the non-boot CPUs
will just use the default pm_idle which should be WFI only, right?
> + * 2. Do only a WFI as long as in SMP mode.
> + * 3. Continue to do only WFI till CPU1 hits OFF state.
> + * This is necessary to honour hardware recommondation
> + * of triggeing all the possible low power modes once CPU1 is
> + * out of coherency and in OFF mode.
> + * Update dev->last_state so that governor stats reflects right
> + * data.
> + */
> + cpu1_state = pwrdm_read_pwrst(cpu1_pd);
> + if ((dev->cpu) || (num_online_cpus() > 1) ||
> + (cpu1_state != PWRDM_POWER_OFF)) {
> + dev->last_state = dev->safe_state;
We currently have 2 existing ways of doing some pre-transition
checking.
1) through the ->prepare hook of 'struct cpuidle_device'
2) through the existing 'bm_check' mechanism
Here you're adding yet another one, and I don't really like it.
Also, The 'safe state' is C1, but you're not doing the same thing as a
"normal" C1.
What's wrong with just updating 'cx' and falling through so you actually
do the same thing as the C-state you're reporting.
That being said, I think it might be better to use the ->prepare hook
for this. Here's what I propose.
By default, all C-states except C1 have the CPUIDLE_FLAG_IGNORE flag set
(meaning they will be ignored by the governor.) Only on CPU1 hot-unplug
is the ignore flag removed from the other states, and conversly when
CPU1 is hot-plugged, the ignore flag is added back.
Doing this shifts the burden up to the governor and will prevent all of
this logic from happening for every idle transition.
> + cpu_do_idle();
> + goto return_sleep_time;
> + }
>
> + pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
> + omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
> + pwrdm_set_logic_retst(core_pd, cx->core_logic_state);
> + omap_set_pwrdm_state(core_pd, cx->core_state);
> +
> + omap4_enter_lowpower(dev->cpu, cx->cpu0_state);
> +
> +return_sleep_time:
> getnstimeofday(&ts_postidle);
> ts_idle = timespec_sub(ts_postidle, ts_preidle);
>
> local_irq_enable();
> local_fiq_enable();
>
> +
> return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
> }
[...]
Kevin
^ permalink raw reply
* [PATCH 13/17] omap4: cpuidle: Basic CPUidle support
From: Kevin Hilman @ 2011-03-02 22:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298112158-28469-14-git-send-email-santosh.shilimkar@ti.com>
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> From: Rajendra Nayak <rnayak@ti.com>
>
> The patch adds a basic CPUidle driver for OMAP4. Just
> one C state is registered for both CPU cores which
> does a wfi.
s/wfi/WFI/
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Reviewed-by: Kevin Hilman <khilman@ti.com>
Mostly minor nits below...
> ---
> arch/arm/mach-omap2/Makefile | 3 +-
> arch/arm/mach-omap2/cpuidle44xx.c | 165 +++++++++++++++++++++++++++++++++++++
> arch/arm/mach-omap2/pm.h | 1 +
> arch/arm/mach-omap2/pm44xx.c | 2 +
> 4 files changed, 170 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/mach-omap2/cpuidle44xx.c
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index 5d94f7e..2b4fe44 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -64,7 +64,8 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o voltage.o
> obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o voltage.o \
> cpuidle34xx.o pm_bus.o
> obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o voltage.o pm_bus.o \
> - omap4-mpuss-lowpower.o sleep44xx.o
> + omap4-mpuss-lowpower.o sleep44xx.o \
> + cpuidle44xx.o
> obj-$(CONFIG_PM_DEBUG) += pm-debug.o
> obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
> obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o
> diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
> new file mode 100644
> index 0000000..6c3c69d
> --- /dev/null
> +++ b/arch/arm/mach-omap2/cpuidle44xx.c
> @@ -0,0 +1,165 @@
> +/*
> + * OMAP4 CPU IDLE Routines
s/IDLE/idle/
> + *
> + * Copyright (C) 2011 Texas Instruments, Inc.
> + * Rajendra Nayak <rnayak@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/sched.h>
> +#include <linux/cpuidle.h>
> +
> +#include <asm/proc-fns.h>
> +
> +#include <mach/omap4-common.h>
> +
> +#include "pm.h"
> +
> +#ifdef CONFIG_CPU_IDLE
> +
> +#define OMAP4_MAX_STATES 1
> +/* C1 - CPUx wfi + MPU inactive + CORE inactive */
s/wfi/WFI/
> +#define OMAP4_STATE_C1 0
> +
> +struct omap4_processor_cx {
> + u8 valid;
> + u8 type;
> + u32 sleep_latency;
> + u32 wakeup_latency;
> + u32 cpu0_state;
> + u32 cpu1_state;
> + u32 mpu_state;
> + u32 core_state;
> + u32 threshold;
> + u32 flags;
> +};
> +
> +struct omap4_processor_cx omap4_power_states[OMAP4_MAX_STATES];
> +struct omap4_processor_cx current_cx_state;
> +
> +static struct cpuidle_params cpuidle_params_table[] = {
> + /* C1 */
> + {1, 2, 2, 5},
> +};
> +
> +/**
> + * omap4_enter_idle - Programs OMAP4 to enter the specified state
> + * @dev: cpuidle device
> + * @state: The target state to be programmed
> + *
> + * Called from the CPUidle framework to program the device to the
> + * specified low power state selected by the governor.
> + * Returns the amount of time spent in the low power state.
> + */
> +static int omap4_enter_idle(struct cpuidle_device *dev,
> + struct cpuidle_state *state)
> +{
> + struct timespec ts_preidle, ts_postidle, ts_idle;
> +
> + /* Used to keep track of the total time in idle */
> + getnstimeofday(&ts_preidle);
> +
> + local_irq_disable();
> + local_fiq_disable();
> +
> + cpu_do_idle();
> +
> + getnstimeofday(&ts_postidle);
> + ts_idle = timespec_sub(ts_postidle, ts_preidle);
> +
> + local_irq_enable();
> + local_fiq_enable();
> +
> + return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
> +}
> +
> +DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
> +
> +/**
> + * omap4_init_power_states - Initialises the OMAP4 specific C states.
> + *
> + * Below is the desciption of each C state.
> + * C1 : CPUx wfi + MPU inative + Core inactive
> + */
> +void omap_init_power_states(void)
> +{
> + /* C1 . CPUx wfi + MPU inactive + Core inactive */
> + omap4_power_states[OMAP4_STATE_C1].valid =
> + cpuidle_params_table[OMAP4_STATE_C1].valid;
> + omap4_power_states[OMAP4_STATE_C1].type = OMAP4_STATE_C1;
> + omap4_power_states[OMAP4_STATE_C1].sleep_latency =
> + cpuidle_params_table[OMAP4_STATE_C1].sleep_latency;
> + omap4_power_states[OMAP4_STATE_C1].wakeup_latency =
> + cpuidle_params_table[OMAP4_STATE_C1].wake_latency;
> + omap4_power_states[OMAP4_STATE_C1].threshold =
> + cpuidle_params_table[OMAP4_STATE_C1].threshold;
> + omap4_power_states[OMAP4_STATE_C1].mpu_state = PWRDM_POWER_ON;
> + omap4_power_states[OMAP4_STATE_C1].core_state = PWRDM_POWER_ON;
> + omap4_power_states[OMAP4_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
> +
> +}
> +
> +struct cpuidle_driver omap4_idle_driver = {
> + .name = "omap4_idle",
> + .owner = THIS_MODULE,
> +};
> +
> +/**
> + * omap4_idle_init - Init routine for OMAP4 idle
> + *
> + * Registers the OMAP4 specific cpuidle driver with the cpuidle
> + * framework with the valid set of states.
> + */
> +int __init omap4_idle_init(void)
> +{
> + int cpu_id, i, count = 0;
> + struct omap4_processor_cx *cx;
> + struct cpuidle_state *state;
> + struct cpuidle_device *dev;
> +
> + omap_init_power_states();
> + cpuidle_register_driver(&omap4_idle_driver);
> +
> + for_each_cpu(cpu_id, cpu_online_mask) {
> + pr_err("CPUidle for CPU%d registered\n", cpu_id);
stray debug print?
> + dev = &per_cpu(omap4_idle_dev, cpu_id);
> + dev->cpu = cpu_id;
> + count = 0;
> + for (i = OMAP4_STATE_C1; i < OMAP4_MAX_STATES; i++) {
> + cx = &omap4_power_states[i];
> + state = &dev->states[count];
> +
> + if (!cx->valid)
> + continue;
> + cpuidle_set_statedata(state, cx);
> + state->exit_latency = cx->sleep_latency +
> + cx->wakeup_latency;
> + state->target_residency = cx->threshold;
> + state->flags = cx->flags;
> + state->enter = omap4_enter_idle;
> + sprintf(state->name, "C%d", count+1);
> + count++;
> + }
> +
> + if (!count)
> + return -EINVAL;
> + dev->state_count = count;
> +
> + if (cpuidle_register_device(dev)) {
> + pr_err("%s: CPUidle register device failed\n",
> + __func__);
> + return -EIO;
> + }
> + }
> +
> + return 0;
> +}
> +#else
> +int __init omap4_idle_init(void)
> +{
> + return 0;
> +}
> +#endif /* CONFIG_CPU_IDLE */
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index f557407..ce848b0 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -22,6 +22,7 @@ extern void omap_sram_idle(void);
> extern int omap3_can_sleep(void);
> extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
> extern int omap3_idle_init(void);
> +extern int omap4_idle_init(void);
>
> #if defined(CONFIG_PM_OPP)
> extern int omap3_opp_init(void);
> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> index 8e57b42..628242d 100644
> --- a/arch/arm/mach-omap2/pm44xx.c
> +++ b/arch/arm/mach-omap2/pm44xx.c
> @@ -230,6 +230,8 @@ static int __init omap4_pm_init(void)
> suspend_set_ops(&omap_pm_ops);
> #endif /* CONFIG_SUSPEND */
>
> + omap4_idle_init();
> +
> err2:
> return ret;
> }
^ permalink raw reply
* [PATCH 12/17] omap4: pm-debug: Add wakeup timer and debug counters
From: Kevin Hilman @ 2011-03-02 22:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298112158-28469-13-git-send-email-santosh.shilimkar@ti.com>
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> This patch adds configurable wakeup timer support in suspend. Also
> for statistics pm counter support is added.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Reviewed-by: Kevin Hilman <khilman@ti.com>
> ---
> arch/arm/mach-omap2/omap4-mpuss-lowpower.c | 8 ++++++++
> arch/arm/mach-omap2/pm-debug.c | 6 ++++--
> arch/arm/mach-omap2/pm44xx.c | 5 +++++
> 3 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
> index ab2e101..5e0141e 100644
> --- a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
> +++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
> @@ -287,6 +287,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
> if (cpu)
> goto cpu_prepare;
>
> +#ifdef CONFIG_PM_DEBUG
> + pwrdm_pre_transition();
> +#endif
Why the #ifdef?
> /*
> * Check MPUSS next state and save GIC if needed
> * GIC lost during MPU OFF and OSWR
> @@ -332,6 +336,10 @@ cpu_prepare:
> gic_dist_set(CPU0_ID, 1);
> }
>
> +#ifdef CONFIG_PM_DEBUG
> + pwrdm_post_transition();
> +#endif
> +
> ret:
> return 0;
> }
> diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
> index 9b46b3e..7d6dd5b 100644
> --- a/arch/arm/mach-omap2/pm-debug.c
> +++ b/arch/arm/mach-omap2/pm-debug.c
> @@ -606,9 +606,11 @@ static int __init pm_dbg_init(void)
> if (pm_dbg_init_done)
> return 0;
>
> - if (cpu_is_omap34xx())
> + if (cpu_is_omap34xx()) {
> pm_dbg_reg_modules = omap3_pm_reg_modules;
> - else {
> + } else if (cpu_is_omap44xx()) {
> + /* Allow pm_dbg_init on OMAP4. */
Doing this will cause crashes if the 'registers/*' debugfs file is
accessed.
Since there are no 'reg_modules' created, you should also prevent the
creation of the 'registers' debugfs entries.
Kevin
> + } else {
> printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
> return -ENODEV;
> }
> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> index f527e33..8e57b42 100644
> --- a/arch/arm/mach-omap2/pm44xx.c
> +++ b/arch/arm/mach-omap2/pm44xx.c
> @@ -42,6 +42,11 @@ static int omap4_pm_suspend(void)
> int state, ret = 0;
> u32 cpu_id = smp_processor_id();
>
> + /* Wakeup timer from suspend */
> + if (wakeup_timer_seconds || wakeup_timer_milliseconds)
> + omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
> + wakeup_timer_milliseconds);
> +
> /* Save current powerdomain state */
> list_for_each_entry(pwrst, &pwrst_list, node) {
> pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
^ permalink raw reply
* [Qualcomm PM8921 MFD 5/6] MAINTAINERS: Add pmic8921, pmic8xxx subdevices maintainers
From: Joe Perches @ 2011-03-02 22:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299104001-5240-6-git-send-email-adharmap@codeaurora.org>
On Wed, 2011-03-02 at 14:13 -0800, adharmap at codeaurora.org wrote:
> diff --git a/MAINTAINERS b/MAINTAINERS
The patch subject is not quite correct.
You're adding patterns, not maintainers.
> index 696cb18..97107fd 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -905,6 +905,12 @@ F: drivers/mmc/host/msm_sdcc.h
> F: drivers/tty/serial/msm_serial.h
> F: drivers/tty/serial/msm_serial.c
> F: drivers/platform/msm/
> +F: drivers/mfd/pm8921-core.c
> +F: drivers/mfd/pm8xxx-mpp.c
> +F: include/linux/mfd/pm8921.h
> +F: include/linux/mfd/pm8xxx/
> +F: drivers/gpio/pm8xxx-gpio.c
> +F: drivers/mfd/pm8xxx-irq.c
My preference is to keep these in alphabetic order.
Another option is a wildcard pattern match like:
F: drivers/*/pm8???-*
instead of:
F: drivers/gpio/pm8xxx-gpio.c
F: drivers/mfd/pm8921-core.c
F: drivers/mfd/pm8xxx-irq.c
F: drivers/mfd/pm8xxx-mpp.c
^ permalink raw reply
* [Qualcomm PM8921 MFD 2/6] mfd: pm8xxx: Add irq support
From: Mark Brown @ 2011-03-02 22:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299104001-5240-3-git-send-email-adharmap@codeaurora.org>
On Wed, Mar 02, 2011 at 02:13:17PM -0800, adharmap at codeaurora.org wrote:
>
> Change-Id: Ibb23878cd382af9a750d62ab49482f5dc72e3714
> Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Remove the change IDs from upstream submissions. The kernel doesn't use
gerritt.
> struct pm8921 {
> - struct device *dev;
> + struct device *dev;
> + struct device *irq_dev;
Is it really useful to register a struct device purely for the interrupt
controller? I'd have expected this to be core functionality of the
device. The fact that you need to store the device at all is a bit odd
too as you're using the MFD API.
> static struct pm8xxx_drvdata pm8921_drvdata = {
> - .pmic_readb = pm8921_readb,
> - .pmic_writeb = pm8921_writeb,
> - .pmic_read_buf = pm8921_read_buf,
> - .pmic_write_buf = pm8921_write_buf,
> + .pmic_readb = pm8921_readb,
> + .pmic_writeb = pm8921_writeb,
> + .pmic_read_buf = pm8921_read_buf,
> + .pmic_write_buf = pm8921_write_buf,
> + .pmic_read_irq_stat = pm8921_read_irq_stat,
> +};
It'd seem better to indent things as per the final driver in the first
patch - this reindentation creates a lot of noise in the diff.
> goto err_read_rev;
> }
> - pr_info("PMIC revision: %02X\n", val);
> + pr_info("PMIC revision 1: %02X\n", val);
> + rev = val;
>
Again, do this in the first patch.
> +static int
> +pm8xxx_read_block(const struct pm_irq_chip *chip, u8 bp, u8 *ip)
> +{
> + int rc;
> +
> + rc = pm8xxx_writeb(chip->dev->parent,
> + SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
> + if (rc) {
> + pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
> + goto bail_out;
> + }
> +
> + rc = pm8xxx_readb(chip->dev->parent,
> + SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
> + if (rc)
> + pr_err("Failed Reading Status rc=%d\n", rc);
> +bail_out:
> + return rc;
> +}
The namespacing here is odd, this looks like it should be a generic API
not a block specific one.
> + /* Check IRQ bits */
> + for (k = 0; k < 8; k++) {
> + if (bits & (1 << k)) {
> + pmirq = block * 8 + k;
> + irq = pmirq + chip->irq_base;
> + /* Check spurious interrupts */
> + if (((1 << k) & chip->irqs_allowed[block])) {
> + /* Found one */
> + chip->irqs_to_handle[*handled] = irq;
> + (*handled)++;
> + } else { /* Clear and mask wrong one */
> + config = PM_IRQF_W_C_M |
> + (k << PM_IRQF_BITS_SHIFT);
> +
> + pm8xxx_config_irq(chip,
> + block, config);
> +
> + if (pm8xxx_can_print())
> + pr_err("Spurious IRQ: %d "
> + "[block, bit]="
> + "[%d, %d]\n",
> + irq, block, k);
> + }
The generic IRQ code should be able to take care of spurious interrupts
for you? It's a bit surprising that there's all this logic - I'd expect
an IRQ chip to just defer logic about which interrupts are valid and so
on to the generic IRQ code.
> #include <linux/device.h>
> +#include <linux/mfd/pm8xxx/irq.h>
> +
> +#define NR_PM8921_IRQS 256
Traditionally this'd be namespaced like this:
+#define PM8921_NR_IRQS 256
^ permalink raw reply
* [PATCH 11/17] omap4: suspend: Add MPUSS RET and OFF support
From: Kevin Hilman @ 2011-03-02 22:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298112158-28469-12-git-send-email-santosh.shilimkar@ti.com>
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> This patch adds MPUSS(MPU Sub System) RET and OFF mode support
> to suspend path. For both MPUSS RET and OFF support, CPUs are
> programmed to OFF state.
>
> Only MPUSS RET and OFF supported at this point of time. CORE RET
> will be added subsequently.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Reviewed-by: Kevin Hilman <khilman@ti.com>
> ---
> arch/arm/mach-omap2/omap4-mpuss-lowpower.c | 8 ++-
> arch/arm/mach-omap2/pm-debug.c | 2 +
> arch/arm/mach-omap2/pm.h | 1 +
> arch/arm/mach-omap2/pm44xx.c | 88 ++++++++++++++++++++++++++--
> 4 files changed, 93 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
> index bff768f..ab2e101 100644
> --- a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
> +++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
> @@ -25,7 +25,7 @@
> * ON(Inactive) OFF ON(Inactive)
> * OFF OFF CSWR
> * OFF OFF OSWR (*TBD)
> - * OFF OFF OFF* (*TBD)
> + * OFF OFF OFF
> * ----------------------------------------------
> *
> * Note: CPU0 is the master core and it is the last CPU to go down
> @@ -291,6 +291,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
> * Check MPUSS next state and save GIC if needed
> * GIC lost during MPU OFF and OSWR
> */
> + pwrdm_clear_all_prev_pwrst(mpuss_pd);
> if (pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_OFF) {
> omap_wakeupgen_save();
> gic_save_context();
> @@ -357,6 +358,8 @@ int __init omap4_mpuss_init(void)
> pr_err("Lookup failed for CPU0 pwrdm\n");
> return -ENODEV;
> }
> + /* Clear CPU previous power domain state */
> + pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
? duplicate of lines immediately following.
> /* Clear CPU previous power domain state */
> pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
> @@ -394,6 +397,9 @@ int __init omap4_mpuss_init(void)
> return -ENODEV;
> }
>
> + /* Clear CPU previous power domain state */
> + pwrdm_clear_all_prev_pwrst(mpuss_pd);
> +
> /*
> * Find out how many interrupts are supported.
> * OMAP4 supports max of 128 SPIs where as GIC can support
> diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
> index 125f565..9b46b3e 100644
> --- a/arch/arm/mach-omap2/pm-debug.c
> +++ b/arch/arm/mach-omap2/pm-debug.c
> @@ -588,6 +588,8 @@ static int option_set(void *data, u64 val)
> omap_pm_disable_off_mode();
> if (cpu_is_omap34xx())
> omap3_pm_off_mode_enable(val);
> + else if (cpu_is_omap44xx())
> + omap4_pm_off_mode_enable(val);
> }
>
> return 0;
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 1c1b0ab..f557407 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -17,6 +17,7 @@
>
> extern void *omap3_secure_ram_storage;
> extern void omap3_pm_off_mode_enable(int);
> +extern void omap4_pm_off_mode_enable(int);
> extern void omap_sram_idle(void);
> extern int omap3_can_sleep(void);
> extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> index 9a9dc41..f527e33 100644
> --- a/arch/arm/mach-omap2/pm44xx.c
> +++ b/arch/arm/mach-omap2/pm44xx.c
> @@ -1,8 +1,9 @@
> /*
> * OMAP4 Power Management Routines
> *
> - * Copyright (C) 2010 Texas Instruments, Inc.
> + * Copyright (C) 2010-2011 Texas Instruments, Inc.
> * Rajendra Nayak <rnayak@ti.com>
> + * Santosh Shilimkar <santosh.shilimkar@ti.com>
> *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License version 2 as
> @@ -21,6 +22,7 @@
>
> #include "powerdomain.h"
> #include "clockdomain.h"
> +#include "pm.h"
>
> struct power_state {
> struct powerdomain *pwrdm;
> @@ -36,7 +38,50 @@ static LIST_HEAD(pwrst_list);
> #ifdef CONFIG_SUSPEND
> static int omap4_pm_suspend(void)
> {
> - do_wfi();
> + struct power_state *pwrst;
> + int state, ret = 0;
> + u32 cpu_id = smp_processor_id();
> +
> + /* Save current powerdomain state */
> + list_for_each_entry(pwrst, &pwrst_list, node) {
> + pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
> + }
> +
> + /* Set targeted power domain states by suspend */
> + list_for_each_entry(pwrst, &pwrst_list, node) {
> + /* FIXME: Remove this check when CORE retention is supported */
> + if (!strcmp(pwrst->pwrdm->name, "mpu_pwrdm"))
> + omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
> + }
pwrst_list is the list of powerdomains to that will be changed during
suspend.
Rather than doing this string match for every suspend, just do the check
once during init and only add powerdomains that can transition to the
list.
> + /*
> + * For MPUSS to hit power domain retention(CSWR or OSWR),
> + * CPU0 and CPU1 power domain needs to be in OFF or DORMANT
> + * state. For MPUSS to reach off-mode. CPU0 and CPU1 power domain
> + * should be in off state.
> + * Only master CPU followes suspend path. All other CPUs follow
> + * cpu-hotplug path in system wide suspend. On OMAP4, CPU power
> + * domain CSWR is not supported by hardware.
> + * More details can be found in OMAP4430 TRM section 4.3.4.2.
> + */
> + omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
> +
> + /* Restore next powerdomain state */
> + list_for_each_entry(pwrst, &pwrst_list, node) {
> + state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
> + if (state > pwrst->next_state) {
> + pr_info("Powerdomain (%s) didn't enter "
> + "target state %d\n",
> + pwrst->pwrdm->name, pwrst->next_state);
> + ret = -1;
> + }
> + omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
> + }
> + if (ret)
> + pr_err("Could not enter target state in pm_suspend\n");
> + else
> + pr_err("Successfully put all powerdomains to target state\n");
> +
> return 0;
> }
>
> @@ -91,7 +136,6 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
> return 0;
> }
>
> -
stray whitespace change
> static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
> {
> struct power_state *pwrst;
> @@ -99,14 +143,48 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
> if (!pwrdm->pwrsts)
> return 0;
>
> + /*
> + * Skip CPU0 and CPU1 power domains. CPU1 is programmed
> + * through hotplug path and CPU0 explicitly programmed
> + * further down in the code path
> + */
> + if ((!strcmp(pwrdm->name, "cpu0_pwrdm")) ||
> + (!strcmp(pwrdm->name, "cpu1_pwrdm")))
> + return 0;
> +
> pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
> if (!pwrst)
> return -ENOMEM;
> pwrst->pwrdm = pwrdm;
> - pwrst->next_state = PWRDM_POWER_ON;
> +
> + /* FIXME: Remove this check when core retention is supported */
> + if (!strcmp(pwrst->pwrdm->name, "mpu_pwrdm"))
> + pwrst->next_state = PWRDM_POWER_RET;
> + else
> + pwrst->next_state = PWRDM_POWER_ON;
> +
> list_add(&pwrst->node, &pwrst_list);
>
> - return pwrdm_set_next_pwrst(pwrst->pwrdm, pwrst->next_state);
> + return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
> +}
> +
> +void omap4_pm_off_mode_enable(int enable)
> +{
> + struct power_state *pwrst;
> + u32 state;
> +
> + if (enable)
> + state = PWRDM_POWER_OFF;
> + else
> + state = PWRDM_POWER_RET;
> +
> + list_for_each_entry(pwrst, &pwrst_list, node) {
> + /* FIXME: Remove this check when core retention is supported */
> + if (!strcmp(pwrst->pwrdm->name, "mpu_pwrdm")) {
same string-match comment as above
> + pwrst->next_state = state;
> + omap_set_pwrdm_state(pwrst->pwrdm, state);
> + }
> + }
> }
>
> /**
Kevin
^ permalink raw reply
* [PATCH] arm: omap: fix section mismatch warning
From: tom.leiming at gmail.com @ 2011-03-02 22:41 UTC (permalink / raw)
To: linux-arm-kernel
From: Ming Lei <tom.leiming@gmail.com>
WARNING: arch/arm/plat-omap/built-in.o(.data+0x6d4): Section mismatch in reference from the variable omap_driver to the function .init.text:omap_cpu_init()
The variable omap_driver references
the function __init omap_cpu_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
Signed-off-by: Ming Lei <tom.leiming@gmail.com>
---
arch/arm/plat-omap/cpu-omap.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 11c54ec..da4f68d 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -101,7 +101,7 @@ static int omap_target(struct cpufreq_policy *policy,
return ret;
}
-static int __init omap_cpu_init(struct cpufreq_policy *policy)
+static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
{
int result = 0;
--
1.7.3
^ permalink raw reply related
* [PATCH] arm: etm: fix section mismatch warning
From: tom.leiming at gmail.com @ 2011-03-02 22:41 UTC (permalink / raw)
To: linux-arm-kernel
From: Ming Lei <tom.leiming@gmail.com>
The patch fixes the warning below:
WARNING: arch/arm/kernel/built-in.o(.data+0x27c): Section mismatch in reference from the variable etb_driver to the function .init.text:etb_probe()
The variable etb_driver references
the function __init etb_probe()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
WARNING: arch/arm/kernel/built-in.o(.data+0x2cc): Section mismatch in reference from the variable etm_driver to the function .init.text:etm_probe()
The variable etm_driver references
the function __init etm_probe()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
Signed-off-by: Ming Lei <tom.leiming@gmail.com>
---
arch/arm/kernel/etm.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
index 052b509..1bec8b5 100644
--- a/arch/arm/kernel/etm.c
+++ b/arch/arm/kernel/etm.c
@@ -338,7 +338,7 @@ static struct miscdevice etb_miscdev = {
.fops = &etb_fops,
};
-static int __init etb_probe(struct amba_device *dev, const struct amba_id *id)
+static int __devinit etb_probe(struct amba_device *dev, const struct amba_id *id)
{
struct tracectx *t = &tracer;
int ret = 0;
@@ -530,7 +530,7 @@ static ssize_t trace_mode_store(struct kobject *kobj,
static struct kobj_attribute trace_mode_attr =
__ATTR(trace_mode, 0644, trace_mode_show, trace_mode_store);
-static int __init etm_probe(struct amba_device *dev, const struct amba_id *id)
+static int __devinit etm_probe(struct amba_device *dev, const struct amba_id *id)
{
struct tracectx *t = &tracer;
int ret = 0;
--
1.7.3
^ permalink raw reply related
* [PATCH 10/17] omap4: pm: Add L2 cache lowpower support
From: Kevin Hilman @ 2011-03-02 22:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298112158-28469-11-git-send-email-santosh.shilimkar@ti.com>
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> When MPUSS hits off-mode e, L2 cache is lost. This patch adds L2X0
> necessary maintenance operations and context restoration in the
> low power code.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Reviewed-by: Kevin Hilman <khilman@ti.com>
> ---
> arch/arm/mach-omap2/omap4-mpuss-lowpower.c | 11 +++++
> arch/arm/mach-omap2/omap4-sar-layout.h | 2 +
> arch/arm/mach-omap2/sleep44xx.S | 64 ++++++++++++++++++++++++++++
> 3 files changed, 77 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
> index a30f19b..bff768f 100644
> --- a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
> +++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
> @@ -49,6 +49,7 @@
> #include <asm/system.h>
> #include <asm/irq.h>
> #include <asm/hardware/gic.h>
> +#include <asm/hardware/cache-l2x0.h>
>
> #include <plat/omap44xx.h>
> #include <mach/omap4-common.h>
> @@ -341,6 +342,7 @@ int __init omap4_mpuss_init(void)
> {
> struct omap4_cpu_pm_info *pm_info;
> u8 i;
> + u32 val;
This will cause an 'unused variable' compiler warning when
!CONFIG_CACHE_L2X0
[...]
Kevin
^ permalink raw reply
* [PATCH 09/17] omap4: pm: Add WakeupGen save/restore support
From: Kevin Hilman @ 2011-03-02 22:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298112158-28469-10-git-send-email-santosh.shilimkar@ti.com>
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> WakeupGen is lost only when device hits off-mode. Though the register
> context is retained in MPUSS OFF/OSWR state, hardware recommondation is
> to save/restore WakeupGen along with GIC to have consistent interrupt
> state at both the blocks. The ROM code restore mechinism also does
> restore of wakeupgen on mpu OFF/OSWR
Changelog needs some clarification...
The way I read the above is that "save is not needed, but we do it
anyways for consistency"
It's not terribly clear (to me) how "consistent state" would be lost
if this does not happen.
IOW, describing a potential inconsistent state would be helpful for the
changelog (and code.)
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Reviewed-by: Kevin Hilman <khilman@ti.com>
> ---
> arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 1 +
> arch/arm/mach-omap2/omap-wakeupgen.c | 74 +++++++++++++++++++++
> arch/arm/mach-omap2/omap4-mpuss-lowpower.c | 2 +
> arch/arm/mach-omap2/omap4-sar-layout.h | 11 +++
> 4 files changed, 88 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
> index f10d106..66f31c3 100644
> --- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
> +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
> @@ -37,4 +37,5 @@
>
> extern int __init omap_wakeupgen_init(void);
> extern void omap_wakeupgen_irqmask_all(unsigned int cpu, unsigned int set);
> +extern void omap_wakeupgen_save(void);
> #endif
> diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
> index e26a0ed..0f0a5ed 100644
> --- a/arch/arm/mach-omap2/omap-wakeupgen.c
> +++ b/arch/arm/mach-omap2/omap-wakeupgen.c
> @@ -24,6 +24,9 @@
> #include <asm/hardware/gic.h>
>
> #include <mach/omap-wakeupgen.h>
> +#include <mach/omap4-common.h>
> +
> +#include "omap4-sar-layout.h"
>
> #define NR_BANKS 4
> #define MAX_IRQS 128
> @@ -54,6 +57,11 @@ static inline void cpu_writel(u32 val, u8 idx, u32 cpu)
> (cpu * CPU_ENA_OFFSET) + (idx * 4));
> }
>
> +static inline void sar_writel(u32 val, u32 offset, u8 idx)
> +{
> + __raw_writel(val, sar_ram_base + offset + (idx * 4));
> +}
> +
aha, another function that belongs in the SAR code.
[...]
Kevin
^ permalink raw reply
* [PATCH 08/17] omap4: pm: Add GIC save/restore support
From: Kevin Hilman @ 2011-03-02 22:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1298112158-28469-9-git-send-email-santosh.shilimkar@ti.com>
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> On OMAP4 when attempting MPU off-mode or OSWR, the GIC context is
> lost. This patch adds GIC context save and restore support.
>
> The context save is done by software and restore is done by
> ROM code from predefined SAR locations where the context suppose
s/suppose/supposed/
> to be saved. Refer to ROM code specs for the GIC layout details.
Does this doc have a name? I've never seen such a thing and would
really like to.
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Reviewed-by: Kevin Hilman <khilman@ti.com>
> ---
> arch/arm/mach-omap2/omap-hotplug.c | 4 +
> arch/arm/mach-omap2/omap4-mpuss-lowpower.c | 176 +++++++++++++++++++++++++++-
> arch/arm/mach-omap2/omap4-sar-layout.h | 20 +++
> 3 files changed, 199 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
> index cf4ab15..deab389 100644
> --- a/arch/arm/mach-omap2/omap-hotplug.c
> +++ b/arch/arm/mach-omap2/omap-hotplug.c
> @@ -19,6 +19,8 @@
> #include <linux/smp.h>
>
> #include <asm/cacheflush.h>
> +#include <asm/hardware/gic.h>
> +
> #include <mach/omap4-common.h>
> #include <mach/omap-wakeupgen.h>
>
> @@ -58,6 +60,7 @@ void platform_cpu_die(unsigned int cpu)
> * clear all interrupt wakeup sources
> */
> omap_wakeupgen_irqmask_all(cpu, 1);
> + gic_secondary_set(0, true);
> omap4_enter_lowpower(cpu, PWRDM_POWER_OFF);
> this_cpu = hard_smp_processor_id();
> if (omap_read_auxcoreboot0() == this_cpu) {
> @@ -65,6 +68,7 @@ void platform_cpu_die(unsigned int cpu)
> * OK, proper wakeup, we're done
> */
> omap_wakeupgen_irqmask_all(this_cpu, 0);
> + gic_secondary_set(0, false);
>
> /* Restore clockdomain to hardware supervised */
> clkdm_allow_idle(cpu1_clkdm);
> diff --git a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
> index c0f358d..4140251 100644
> --- a/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
> +++ b/arch/arm/mach-omap2/omap4-mpuss-lowpower.c
> @@ -47,6 +47,8 @@
> #include <asm/tlbflush.h>
> #include <asm/smp_scu.h>
> #include <asm/system.h>
> +#include <asm/irq.h>
> +#include <asm/hardware/gic.h>
>
> #include <plat/omap44xx.h>
> #include <mach/omap4-common.h>
> @@ -59,6 +61,19 @@
>
> #define CPU0_ID 0x0
> #define CPU1_ID 0x1
> +#define GIC_MASK_ALL 0x0
> +#define GIC_ISR_NON_SECURE 0xffffffff
> +#define SPI_ENABLE_SET_OFFSET 0x04
> +#define PPI_PRI_OFFSET 0x1c
> +#define SPI_PRI_OFFSET 0x20
> +#define SPI_TARGET_OFFSET 0x20
> +#define SPI_CONFIG_OFFSET 0x20
> +
> +/* GIC save SAR bank base */
> +static struct powerdomain *mpuss_pd;
> +
> +/* Variables to store maximum spi(Shared Peripheral Interrupts) registers. */
> +static u32 max_spi_irq, max_spi_reg;
>
> struct omap4_cpu_pm_info {
> struct powerdomain *pwrdm;
> @@ -67,6 +82,17 @@ struct omap4_cpu_pm_info {
>
> static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
>
> +/* Helper functions */
> +static inline void sar_writel(u32 val, u32 offset, u8 idx)
> +{
> + __raw_writel(val, sar_ram_base + offset + 4 * idx);
> +}
aha, this is what I was thinking of in the earlier SAR patch.
Something like this should be part of the SAR code, not here.
> +static inline u32 gic_readl(u32 offset, u8 idx)
> +{
> + return __raw_readl(gic_dist_base_addr + offset + 4 * idx);
> +}
Similarily, it would be nice tos see this as part of GIC code so
this code doesn't have to access a global base address pointer.
> /*
> * Set the CPUx powerdomain's previous power state
> */
> @@ -124,6 +150,85 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
> }
>
> /*
> + * Save GIC context in SAR RAM. Restore is done by ROM code
> + * GIC is lost only when MPU hits OSWR or OFF. It consists
> + * of a distributor and a per-CPU interface module. The GIC
> + * save restore is optimised to save only necessary registers.
> + */
> +static void gic_save_context(void)
> +{
> + u8 i;
> + u32 val;
> +
> + /*
> + * Interrupt Clear Enable registers are inverse of set enable
> + * and hence not needed to be saved. ROM code programs it
> + * based on Set Enable register values.
> + */
> +
> + /* Save CPU 0 Interrupt Set Enable register */
> + val = gic_readl(GIC_DIST_ENABLE_SET, 0);
> + sar_writel(val, ICDISER_CPU0_OFFSET, 0);
> +
> + /* Disable interrupts on CPU1 */
> + sar_writel(GIC_MASK_ALL, ICDISER_CPU1_OFFSET, 0);
> +
> + /* Save all SPI Set Enable register */
> + for (i = 0; i < max_spi_reg; i++) {
> + val = gic_readl(GIC_DIST_ENABLE_SET + SPI_ENABLE_SET_OFFSET, i);
> + sar_writel(val, ICDISER_SPI_OFFSET, i);
> + }
> +
> + /*
> + * Interrupt Priority Registers
> + * Secure sw accesses, last 5 bits of the 8 bits (bit[7:3] are used)
> + * Non-Secure sw accesses, last 4 bits (i.e. bits[7:4] are used)
> + * But the Secure Bits[7:3] are shifted by 1 in Non-Secure access.
> + * Secure (bits[7:3] << 1)== Non Secure bits[7:4]
> + * Hence right shift the value by 1 while saving the priority
> + */
> +
> + /* Save SGI priority registers (Software Generated Interrupt) */
> + for (i = 0; i < 4; i++) {
> + val = gic_readl(GIC_DIST_PRI, i);
> +
> + /* Save the priority bits of the Interrupts */
> + sar_writel(val >> 0x1, ICDIPR_SFI_CPU0_OFFSET, i);
> +
> + /* Disable the interrupts on CPU1 */
> + sar_writel(GIC_MASK_ALL, ICDIPR_SFI_CPU1_OFFSET, i);
> + }
> +
> + /* Save PPI priority registers (Private Peripheral Intterupts) */
> + val = gic_readl(GIC_DIST_PRI + PPI_PRI_OFFSET, 0);
> + sar_writel(val >> 0x1, ICDIPR_PPI_CPU0_OFFSET, 0);
> + sar_writel(GIC_MASK_ALL, ICDIPR_PPI_CPU1_OFFSET, 0);
> +
> + /* SPI priority registers - 4 interrupts/register */
> + for (i = 0; i < (max_spi_irq / 4); i++) {
> + val = gic_readl((GIC_DIST_PRI + SPI_PRI_OFFSET), i);
> + sar_writel(val >> 0x1, ICDIPR_SPI_OFFSET, i);
> + }
> +
> + /* SPI Interrupt Target registers - 4 interrupts/register */
> + for (i = 0; i < (max_spi_irq / 4); i++) {
> + val = gic_readl((GIC_DIST_TARGET + SPI_TARGET_OFFSET), i);
> + sar_writel(val, ICDIPTR_SPI_OFFSET, i);
> + }
> +
> + /* SPI Interrupt Congigeration eegisters- 16 interrupts/register */
> + for (i = 0; i < (max_spi_irq / 16); i++) {
> + val = gic_readl((GIC_DIST_CONFIG + SPI_CONFIG_OFFSET), i);
> + sar_writel(val, ICDICFR_OFFSET, i);
> + }
> +
> + /* Set the Backup Bit Mask status for GIC */
> + val = __raw_readl(sar_ram_base + SAR_BACKUP_STATUS_OFFSET);
> + val |= (SAR_BACKUP_STATUS_GIC_CPU0 | SAR_BACKUP_STATUS_GIC_CPU1);
> + __raw_writel(val, sar_ram_base + SAR_BACKUP_STATUS_OFFSET);
> +}
> +
> +/*
> * OMAP4 MPUSS Low Power Entry Function
> *
> * The purpose of this function is to manage low power programming
> @@ -131,11 +236,25 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
> * Paramenters:
> * cpu : CPU ID
> * power_state: Targetted Low power state.
> + *
> + * MPUSS Low power states
> + * The basic rule is that the MPUSS power domain must be at the higher or
> + * equal power state (state that consume more power) than the higher of the
> + * two CPUs. For example, it is illegal for system power to be OFF, while
> + * the power of one or both of the CPU is DORMANT. When an illegal state is
> + * entered, then the hardware behavior is unpredictable.
> + *
> + * MPUSS state for the context save
> + * save_state =
> + * 0 - Nothing lost and no need to save: MPUSS INACTIVE
> + * 1 - CPUx L1 and logic lost: MPUSS CSWR
> + * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
> + * 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
> */
> int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
> {
> unsigned int save_state = 0;
> - unsigned int wakeup_cpu = hard_smp_processor_id();
> + unsigned int wakeup_cpu;
>
> if ((cpu > NR_CPUS) || (omap_rev() == OMAP4430_REV_ES1_0))
> goto ret;
> @@ -159,6 +278,23 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
> goto ret;
> }
>
> + /*
> + * MPUSS book keeping should be executed by master
> + * CPU only which is also the last CPU to go down.
> + */
> + if (cpu)
> + goto cpu_prepare;
> +
> + /*
> + * Check MPUSS next state and save GIC if needed
> + * GIC lost during MPU OFF and OSWR
> + */
> + if (pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_OFF) {
> + gic_save_context();
> + save_state = 3;
> + }
> +
> +cpu_prepare:
> clear_cpu_prev_pwrst(cpu);
> set_cpu_next_pwrst(cpu, power_state);
> scu_pwrst_prepare(cpu, power_state);
> @@ -179,6 +315,19 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
> wakeup_cpu = hard_smp_processor_id();
> set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
>
> + /* If !master cpu return to hotplug-path */
> + if (wakeup_cpu)
> + goto ret;
> +
> + /* Check MPUSS previous power state and enable GIC if needed */
> + if (pwrdm_read_prev_pwrst(mpuss_pd) == PWRDM_POWER_OFF) {
> + /* Clear SAR BACKUP status */
> + __raw_writel(0x0, sar_ram_base + SAR_BACKUP_STATUS_OFFSET);
> + /* Enable GIC distributor and inteface on CPU0*/
> + gic_secondary_set(CPU0_ID, 1);
> + gic_dist_set(CPU0_ID, 1);
> + }
> +
> ret:
> return 0;
> }
> @@ -189,6 +338,7 @@ ret:
> int __init omap4_mpuss_init(void)
> {
> struct omap4_cpu_pm_info *pm_info;
> + u8 i;
>
> if (omap_rev() == OMAP4430_REV_ES1_0) {
> WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
> @@ -234,6 +384,30 @@ int __init omap4_mpuss_init(void)
> __raw_writel(virt_to_phys(omap4_cpu_resume),
> sar_ram_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET);
>
> + mpuss_pd = pwrdm_lookup("mpu_pwrdm");
> + if (!mpuss_pd) {
> + pr_err("Failed to get lookup for MPUSS pwrdm\n");
> + return -ENODEV;
> + }
> +
> + /*
> + * Find out how many interrupts are supported.
> + * OMAP4 supports max of 128 SPIs where as GIC can support
> + * up to 1020 interrupt sources.
> + */
> + max_spi_reg = __raw_readl(gic_dist_base_addr + GIC_DIST_CTR) & 0x1f;
> + max_spi_irq = max_spi_reg * 32;
Based on the spec, this should also be max'd at 1020 so you never write
the reserved values after 1020.
Kevin
> + /*
> + * Mark the PPI and SPI interrupts as non-secure.
> + * program the SAR locations for interrupt security registers to
> + * reflect the same.
> + */
> + sar_writel(GIC_ISR_NON_SECURE, ICDISR_CPU0_OFFSET, 0);
> + sar_writel(GIC_ISR_NON_SECURE, ICDISR_CPU1_OFFSET, 0);
> + for (i = 0; i < max_spi_reg; i++)
> + sar_writel(GIC_ISR_NON_SECURE, ICDISR_SPI_OFFSET, i);
> +
> return 0;
> }
>
> diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
> index c4251db..0a19f49 100644
> --- a/arch/arm/mach-omap2/omap4-sar-layout.h
> +++ b/arch/arm/mach-omap2/omap4-sar-layout.h
> @@ -30,6 +30,26 @@
> #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04
> #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08
>
> + /* GIC save restore offset from SAR_BANK3 */
> +#define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500)
> +#define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504)
> +#define SAR_SECRAM_SAVED_AT_OFFSET (SAR_BANK3_OFFSET + 0x508)
> +#define ICDISR_CPU0_OFFSET (SAR_BANK3_OFFSET + 0x50c)
> +#define ICDISR_CPU1_OFFSET (SAR_BANK3_OFFSET + 0x510)
> +#define ICDISR_SPI_OFFSET (SAR_BANK3_OFFSET + 0x514)
> +#define ICDISER_CPU0_OFFSET (SAR_BANK3_OFFSET + 0x524)
> +#define ICDISER_CPU1_OFFSET (SAR_BANK3_OFFSET + 0x528)
> +#define ICDISER_SPI_OFFSET (SAR_BANK3_OFFSET + 0x52c)
> +#define ICDIPR_SFI_CPU0_OFFSET (SAR_BANK3_OFFSET + 0x53c)
> +#define ICDIPR_PPI_CPU0_OFFSET (SAR_BANK3_OFFSET + 0x54c)
> +#define ICDIPR_SFI_CPU1_OFFSET (SAR_BANK3_OFFSET + 0x550)
> +#define ICDIPR_PPI_CPU1_OFFSET (SAR_BANK3_OFFSET + 0x560)
> +#define ICDIPR_SPI_OFFSET (SAR_BANK3_OFFSET + 0x564)
> +#define ICDIPTR_SPI_OFFSET (SAR_BANK3_OFFSET + 0x5e4)
> +#define ICDICFR_OFFSET (SAR_BANK3_OFFSET + 0x664)
> +#define SAR_BACKUP_STATUS_GIC_CPU0 0x1
> +#define SAR_BACKUP_STATUS_GIC_CPU1 0x2
> +
> #ifndef __ASSEMBLER__
>
> extern void __iomem *sar_ram_base;
^ permalink raw reply
* [Qualcomm PM8921 MFD 1/6] mfd: pm8921: Add PMIC 8921 core driver
From: Mark Brown @ 2011-03-02 22:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299104001-5240-2-git-send-email-adharmap@codeaurora.org>
On Wed, Mar 02, 2011 at 02:13:16PM -0800, adharmap at codeaurora.org wrote:
> +config MFD_PM8XXX
> + tristate "Support for Qualcomm PM8xxx subdevices"
> + help
> + This option enables the usage of various Qualcomm PMIC 8xxx subdevice
> + drivers. This is required in order to use generic PM8xxx subdevice
> + drivers. Selecting with option will result in PM8xxx subdevice
> + drivers being compiled by default.
As this is selected by the driver it shouldn't have any help text -
there's no point in users seeing the option since it's useless by
itself. If we get enough to make an option useful either a menu or
dependencies from the individual MFDs would be a better option.
> +static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
> + *pdata,
> + struct pm8921 *pmic)
> +{
> + return 0;
> +}
This looks suspicious.
> +static int __init pm8921_init(void)
> +{
> + return platform_driver_register(&pm8921_driver);
> +}
> +postcore_initcall(pm8921_init);
Typically subsys_initcall() has been used.
^ permalink raw reply
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