* [PATCH 16/19] ARM: move iotable mappings within the vmalloc region
From: Russell King - ARM Linux @ 2011-09-19 11:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1109190013120.20358@xanadu.home>
On Mon, Sep 19, 2011 at 12:18:09AM -0400, Nicolas Pitre wrote:
> OK, here we go with version 2:
Looks fine, thanks.
^ permalink raw reply
* [PATCH 16/19] ARM: move iotable mappings within the vmalloc region
From: Russell King - ARM Linux @ 2011-09-19 11:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1109190008140.20358@xanadu.home>
On Mon, Sep 19, 2011 at 12:13:02AM -0400, Nicolas Pitre wrote:
> OK, so I moved this into a patch of its own not to confuse things. Here
> it is:
Looks fine, thanks.
^ permalink raw reply
* [PATCH 01/19] ARM: sort the meminfo array earlier
From: Russell King - ARM Linux @ 2011-09-19 11:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1109182340370.20358@xanadu.home>
On Mon, Sep 19, 2011 at 12:06:53AM -0400, Nicolas Pitre wrote:
> Well, I'm about to post some revised patches for this series, and I'm
> now taking advantage of the sorted array. So here's this patch again
> which is also revised:
Looks fine, thanks.
^ permalink raw reply
* [PATCH v2] dmaengine: add CSR SiRFprimaII DMAC driver
From: Barry Song @ 2011-09-19 11:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316430878.26662.46.camel@vkoul-udesk3>
2011/9/19 Vinod Koul <vinod.koul@intel.com>:
> On Mon, 2011-09-19 at 09:56 +0000, Barry Song wrote:
>> > > > Not sure why you support this, there seem to be no DMA_SLAVE
>> support in
>> > > > this version ate least
>> > >
>> > > Not. I support dma_slave. But I have no prep_slave_sg function
>> since I can
>> > use the gen xfer to replace it.
>> > Yes thats okay...
>> >
>> > Then I have questions on genxfer function...
>> > where are you copying either src or dstn_start address, you seem to
>> > completely ignore them?
>>
>> Since I only support memory->device or device ->memory, and channel
>> number is fixed to every device. Then I actually don't care device
>> address at all. Either src or dst is fixed to the device's address.
> peripheral address can be fixed, not the memory, where do you copy the
> memory address?
+static int sirfsoc_dma_slave_config(struct sirfsoc_dma_chan *schan,
+ struct dma_slave_config *config)
+{
+ u32 addr, direction;
+ unsigned long flags;
+
+ switch (config->direction) {
+ case DMA_FROM_DEVICE:
+ direction = 0;
+ addr = config->dst_addr;
+ break;
+
+ case DMA_TO_DEVICE:
+ direction = 1;
+ addr = config->src_addr;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ ...
+static void sirfsoc_dma_execute(struct sirfsoc_dma_chan *schan)
+{
+ ...
+ writel_relaxed(schan->addr >> 2, sdma->base + cid * 0x10 +
SIRFSOC_DMA_CH_ADDR);
+}
+
>>
>> >
>> > Do you support only slave transfers or M2M as well for this driver?
>> > If only slave you might want to check if dma_config_slave is set for
>> > this channel or not.
>>
>> I support only slave transfer. Actually I have dma_config_slave. do
>> you mean I need to check whether slave config cmd is really called
>> before executing dma?
> Yes
>
>
> --
> ~Vinod
>
>
-Barry
^ permalink raw reply
* [PATCH] ARM: SAMSUNG: Cleanup mach/clkdev.h
From: Kukjin Kim @ 2011-09-19 11:36 UTC (permalink / raw)
To: linux-arm-kernel
According to commit a3831cf ("ARM: Consolidate the
clkdev header files"), current mach/clkdev.h is no
needed in Samsung stuff.
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/include/mach/clkdev.h | 7 -------
arch/arm/mach-s3c64xx/include/mach/clkdev.h | 7 -------
arch/arm/mach-s5p64x0/include/mach/clkdev.h | 7 -------
arch/arm/mach-s5pc100/include/mach/clkdev.h | 7 -------
arch/arm/mach-s5pv210/include/mach/clkdev.h | 7 -------
arch/arm/plat-s3c24xx/include/mach/clkdev.h | 7 -------
6 files changed, 0 insertions(+), 42 deletions(-)
delete mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
delete mode 100644 arch/arm/mach-s3c64xx/include/mach/clkdev.h
delete mode 100644 arch/arm/mach-s5p64x0/include/mach/clkdev.h
delete mode 100644 arch/arm/mach-s5pc100/include/mach/clkdev.h
delete mode 100644 arch/arm/mach-s5pv210/include/mach/clkdev.h
delete mode 100644 arch/arm/plat-s3c24xx/include/mach/clkdev.h
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h
b/arch/arm/mach-exynos4/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83..0000000
--- a/arch/arm/mach-exynos4/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h
b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83..0000000
--- a/arch/arm/mach-s3c64xx/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/mach-s5p64x0/include/mach/clkdev.h
b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83..0000000
--- a/arch/arm/mach-s5p64x0/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/mach-s5pc100/include/mach/clkdev.h
b/arch/arm/mach-s5pc100/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83..0000000
--- a/arch/arm/mach-s5pc100/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h
b/arch/arm/mach-s5pv210/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83..0000000
--- a/arch/arm/mach-s5pv210/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/plat-s3c24xx/include/mach/clkdev.h
b/arch/arm/plat-s3c24xx/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83..0000000
--- a/arch/arm/plat-s3c24xx/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
--
1.7.1
^ permalink raw reply related
* [PATCH] ARM: SAMSUNG: plat-samsung/include/plat/pwm-clock.h
From: Kukjin Kim @ 2011-09-19 11:37 UTC (permalink / raw)
To: linux-arm-kernel
Removed
- arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
- arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
- arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
- arch/arm/mach-s5pc100/include/mach/pwm-clock.h
- arch/arm/mach-s5pv210/include/mach/pwm-clock.h
- arch/arm/mach-exynos4/include/mach/pwm-clock.h
And created
- arch/arm/plat-samsung/include/plat/pwm-clock.h
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s3c64xx/include/mach/pwm-clock.h | 56 ----------------
arch/arm/mach-s5p64x0/include/mach/pwm-clock.h | 68
-------------------
arch/arm/mach-s5pc100/include/mach/pwm-clock.h | 56 ----------------
arch/arm/mach-s5pv210/include/mach/pwm-clock.h | 70
--------------------
arch/arm/plat-s3c24xx/include/mach/pwm-clock.h | 55 ---------------
.../mach => plat-samsung/include/plat}/pwm-clock.h | 39 +++++++----
arch/arm/plat-samsung/pwm-clock.c | 13 +++-
7 files changed, 36 insertions(+), 321 deletions(-)
delete mode 100644 arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
delete mode 100644 arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
delete mode 100644 arch/arm/mach-s5pc100/include/mach/pwm-clock.h
delete mode 100644 arch/arm/mach-s5pv210/include/mach/pwm-clock.h
delete mode 100644 arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
rename arch/arm/{mach-exynos4/include/mach =>
plat-samsung/include/plat}/pwm-clock.h (68%)
diff --git a/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
deleted file mode 100644
index b25bede..0000000
--- a/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C64xx - pwm clock and timer support
- */
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @tcfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
- return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
- return 1 << tcfg1;
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
- return 1;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
- return ilog2(div);
-}
-
-#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
diff --git a/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
deleted file mode 100644
index 19fff8b..0000000
--- a/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S5P64X0 - pwm clock and timer support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_PWMCLK_H
-#define __ASM_ARCH_PWMCLK_H __FILE__
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @tcfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
- return 0;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
- return 1 << tcfg1;
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
- return 1;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
- return ilog2(div);
-}
-
-#define S3C_TCFG1_MUX_TCLK 0
-
-#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
b/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
deleted file mode 100644
index b34d2f7..0000000
--- a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
- *
- * Copyright 2009 Samsung Electronics Co.
- * Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 - pwm clock and timer support
- *
- * Based on mach-s3c6400/include/mach/pwm-clock.h
- */
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @tcfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
- return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
- return 1 << tcfg1;
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
- return 1;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
- return ilog2(div);
-}
-
-#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
diff --git a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
deleted file mode 100644
index f8a9f1b..0000000
--- a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
- *
- * S5PV210 - pwm clock and timer support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_PWMCLK_H
-#define __ASM_ARCH_PWMCLK_H __FILE__
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @tcfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
- return tcfg == S3C64XX_TCFG1_MUX_TCLK;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
- return 1 << tcfg1;
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
- return 1;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
- return ilog2(div);
-}
-
-#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
-
-#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
deleted file mode 100644
index a087de2..0000000
--- a/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
- *
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C24xx - pwm clock and timer support
- */
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @cfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
- return tcfg == S3C2410_TCFG1_MUX_TCLK;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
- return 1 << (1 + tcfg1);
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
- return 0;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
- return ilog2(div) - 1;
-}
-
-#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
diff --git a/arch/arm/mach-exynos4/include/mach/pwm-clock.h
b/arch/arm/plat-samsung/include/plat/pwm-clock.h
similarity index 68%
rename from arch/arm/mach-exynos4/include/mach/pwm-clock.h
rename to arch/arm/plat-samsung/include/plat/pwm-clock.h
index 8e12090..bf6a60e 100644
--- a/arch/arm/mach-exynos4/include/mach/pwm-clock.h
+++ b/arch/arm/plat-samsung/include/plat/pwm-clock.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h
+/* linux/arch/arm/plat-samsung/include/plat/pwm-clock.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -8,17 +8,15 @@
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
- * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
- *
- * EXYNOS4 - pwm clock and timer support
+ * SAMSUNG - pwm clock and timer support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#ifndef __ASM_ARCH_PWMCLK_H
-#define __ASM_ARCH_PWMCLK_H __FILE__
+#ifndef __ASM_PLAT_PWM_CLOCK_H
+#define __ASM_PLAT_PWM_CLOCK_H __FILE__
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
@@ -29,7 +27,14 @@
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
- return tcfg == S3C64XX_TCFG1_MUX_TCLK;
+ if (soc_is_s3c24xx())
+ return tcfg == S3C2410_TCFG1_MUX_TCLK;
+ else if (soc_is_s3c64xx() || soc_is_s5pc100())
+ return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
+ else if (soc_is_s5p6440() || soc_is_s5p6450())
+ return 0;
+ else
+ return tcfg == S3C64XX_TCFG1_MUX_TCLK;
}
/**
@@ -41,7 +46,10 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
- return 1 << tcfg1;
+ if (soc_is_s3c24xx())
+ return 1 << (tcfg1 + 1);
+ else
+ return 1 << tcfg1;
}
/**
@@ -51,7 +59,10 @@ static inline unsigned long tcfg_to_divisor(unsigned long
tcfg1)
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
- return 1;
+ if (soc_is_s3c24xx())
+ return 0;
+ else
+ return 1;
}
/**
@@ -62,9 +73,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
- return ilog2(div);
+ if (soc_is_s3c24xx())
+ return ilog2(div) - 1;
+ else
+ return ilog2(div);
}
-
-#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
-
-#endif /* __ASM_ARCH_PWMCLK_H */
+#endif /* __ASM_PLAT_PWM_CLOCK_H */
diff --git a/arch/arm/plat-samsung/pwm-clock.c
b/arch/arm/plat-samsung/pwm-clock.c
index f1bba88..a35ff3b 100644
--- a/arch/arm/plat-samsung/pwm-clock.c
+++ b/arch/arm/plat-samsung/pwm-clock.c
@@ -27,7 +27,7 @@
#include <plat/cpu.h>
#include <plat/regs-timer.h>
-#include <mach/pwm-clock.h>
+#include <plat/pwm-clock.h>
/* Each of the timers 0 through 5 go through the following
* clock tree, with the inputs depending on the timers.
@@ -339,8 +339,17 @@ static int clk_pwm_tin_set_parent(struct clk *clk,
struct clk *parent)
unsigned long bits;
unsigned long shift = S3C2410_TCFG1_SHIFT(id);
+ unsigned long mux_tclk;
+
+ if (soc_is_s3c24xx())
+ mux_tclk = S3C2410_TCFG1_MUX_TCLK;
+ else if (soc_is_s5p6440() || soc_is_s5p6450())
+ mux_tclk = 0;
+ else
+ mux_tclk = S3C64XX_TCFG1_MUX_TCLK;
+
if (parent == s3c24xx_pwmclk_tclk(id))
- bits = S3C_TCFG1_MUX_TCLK << shift;
+ bits = mux_tclk << shift;
else if (parent == s3c24xx_pwmclk_tdiv(id))
bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
else
--
1.7.1
^ permalink raw reply related
* [PATCH] ARM: SAMSUNG: Cleanup plat/pll.h
From: Kukjin Kim @ 2011-09-19 11:39 UTC (permalink / raw)
To: linux-arm-kernel
Removed
- arch/arm/plat-s3c24xx/include/plat/pll.h
- arch/arm/mach-s3c64xx/include/mach/pll.h
- arch/arm/plat-s5p/include/plat/pll.h
- arch/arm/plat-samsung/include/plat/pll6553x.h
And created
- arch/arm/plat-samsung/include/plat/pll.h
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s3c2410/mach-h1940.c | 6 +-
arch/arm/mach-s3c2416/clock.c | 1 -
arch/arm/mach-s3c64xx/clock.c | 5 +-
arch/arm/mach-s3c64xx/include/mach/pll.h | 45 -----
arch/arm/plat-s3c24xx/include/plat/pll.h | 62 ------
arch/arm/plat-s5p/include/plat/pll.h | 153 --------------
arch/arm/plat-samsung/include/plat/pll.h | 262
+++++++++++++++++++++++++
arch/arm/plat-samsung/include/plat/pll6553x.h | 51 -----
8 files changed, 268 insertions(+), 317 deletions(-)
delete mode 100644 arch/arm/mach-s3c64xx/include/mach/pll.h
delete mode 100644 arch/arm/plat-s3c24xx/include/plat/pll.h
delete mode 100644 arch/arm/plat-s5p/include/plat/pll.h
create mode 100644 arch/arm/plat-samsung/include/plat/pll.h
delete mode 100644 arch/arm/plat-samsung/include/plat/pll6553x.h
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c
b/arch/arm/mach-s3c2410/mach-h1940.c
index 2a2fa06..a9201ea 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -696,9 +696,9 @@ static void __init h1940_init(void)
S3C2410_MISCCR_USBSUSPND0 |
S3C2410_MISCCR_USBSUSPND1, 0x0);
- tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
- | (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
- | (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
+ tmp = (0x78 << S3C24XX_PLL_MDIV_SHIFT)
+ | (0x02 << S3C24XX_PLL_PDIV_SHIFT)
+ | (0x03 << S3C24XX_PLL_SDIV_SHIFT);
writel(tmp, S3C2410_UPLLCON);
gpio_request(S3C2410_GPC(0), "LCD power");
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 21a5e81..c7b91d0 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -21,7 +21,6 @@
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
-#include <plat/pll6553x.h>
#include <plat/pll.h>
#include <asm/mach/map.h>
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 8cf39e3..4adc51c 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -25,13 +25,13 @@
#include <mach/regs-sys.h>
#include <mach/regs-clock.h>
-#include <mach/pll.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>
+#include <plat/pll.h>
/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
* ext_xtal_mux for want of an actual name from the manual.
@@ -735,7 +735,8 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
/* For now assume the mux always selects the crystal */
clk_ext_xtal_mux.parent = xtal_clk;
- epll = s3c6400_get_epll(xtal);
+ epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
+ __raw_readl(S3C_EPLL_CON1));
mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
diff --git a/arch/arm/mach-s3c64xx/include/mach/pll.h
b/arch/arm/mach-s3c64xx/include/mach/pll.h
deleted file mode 100644
index 5ef0bb6..0000000
--- a/arch/arm/mach-s3c64xx/include/mach/pll.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* arch/arm/plat-s3c64xx/include/plat/pll.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C64XX PLL code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
-#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
-#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
-#define S3C6400_PLL_MDIV_SHIFT (16)
-#define S3C6400_PLL_PDIV_SHIFT (8)
-#define S3C6400_PLL_SDIV_SHIFT (0)
-
-#include <asm/div64.h>
-#include <plat/pll6553x.h>
-
-static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
- u32 pllcon)
-{
- u32 mdiv, pdiv, sdiv;
- u64 fvco = baseclk;
-
- mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
- pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
- sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
-
- fvco *= mdiv;
- do_div(fvco, (pdiv << sdiv));
-
- return (unsigned long)fvco;
-}
-
-static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
-{
- return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),
- __raw_readl(S3C_EPLL_CON1));
-}
diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h
b/arch/arm/plat-s3c24xx/include/plat/pll.h
deleted file mode 100644
index 005729a..0000000
--- a/arch/arm/plat-s3c24xx/include/plat/pll.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
- *
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C24xx - common pll registers and code
- */
-
-#define S3C24XX_PLLCON_MDIVSHIFT 12
-#define S3C24XX_PLLCON_PDIVSHIFT 4
-#define S3C24XX_PLLCON_SDIVSHIFT 0
-#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
-#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1)
-#define S3C24XX_PLLCON_SDIVMASK 3
-
-#include <asm/div64.h>
-
-static inline unsigned int
-s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
-{
- unsigned int mdiv, pdiv, sdiv;
- uint64_t fvco;
-
- mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;
- pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;
- sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;
-
- mdiv &= S3C24XX_PLLCON_MDIVMASK;
- pdiv &= S3C24XX_PLLCON_PDIVMASK;
- sdiv &= S3C24XX_PLLCON_SDIVMASK;
-
- fvco = (uint64_t)baseclk * (mdiv + 8);
- do_div(fvco, (pdiv + 2) << sdiv);
-
- return (unsigned int)fvco;
-}
-
-#define S3C2416_PLL_M_SHIFT (14)
-#define S3C2416_PLL_P_SHIFT (5)
-#define S3C2416_PLL_S_MASK (7)
-#define S3C2416_PLL_M_MASK ((1 << 10) - 1)
-#define S3C2416_PLL_P_MASK (63)
-
-static inline unsigned int
-s3c2416_get_pll(unsigned int pllval, unsigned int baseclk)
-{
- unsigned int m, p, s;
- uint64_t fvco;
-
- m = pllval >> S3C2416_PLL_M_SHIFT;
- p = pllval >> S3C2416_PLL_P_SHIFT;
-
- s = pllval & S3C2416_PLL_S_MASK;
- m &= S3C2416_PLL_M_MASK;
- p &= S3C2416_PLL_P_MASK;
-
- fvco = (uint64_t)baseclk * m;
- do_div(fvco, (p << s));
-
- return (unsigned int)fvco;
-}
diff --git a/arch/arm/plat-s5p/include/plat/pll.h
b/arch/arm/plat-s5p/include/plat/pll.h
deleted file mode 100644
index bf28fad..0000000
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* arch/arm/plat-s5p/include/plat/pll.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- *
- * S5P PLL code
- *
- * Based on arch/arm/plat-s3c64xx/include/plat/pll.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define PLL45XX_MDIV_MASK (0x3FF)
-#define PLL45XX_PDIV_MASK (0x3F)
-#define PLL45XX_SDIV_MASK (0x7)
-#define PLL45XX_MDIV_SHIFT (16)
-#define PLL45XX_PDIV_SHIFT (8)
-#define PLL45XX_SDIV_SHIFT (0)
-
-#include <asm/div64.h>
-
-enum pll45xx_type_t {
- pll_4500,
- pll_4502,
- pll_4508
-};
-
-static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32
pll_con,
- enum pll45xx_type_t pll_type)
-{
- u32 mdiv, pdiv, sdiv;
- u64 fvco = baseclk;
-
- mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
- pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
- sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
-
- if (pll_type == pll_4508)
- sdiv = sdiv - 1;
-
- fvco *= mdiv;
- do_div(fvco, (pdiv << sdiv));
-
- return (unsigned long)fvco;
-}
-
-#define PLL46XX_KDIV_MASK (0xFFFF)
-#define PLL4650C_KDIV_MASK (0xFFF)
-#define PLL46XX_MDIV_MASK (0x1FF)
-#define PLL46XX_PDIV_MASK (0x3F)
-#define PLL46XX_SDIV_MASK (0x7)
-#define PLL46XX_MDIV_SHIFT (16)
-#define PLL46XX_PDIV_SHIFT (8)
-#define PLL46XX_SDIV_SHIFT (0)
-
-enum pll46xx_type_t {
- pll_4600,
- pll_4650,
- pll_4650c,
-};
-
-static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
- u32 pll_con0, u32 pll_con1,
- enum pll46xx_type_t pll_type)
-{
- unsigned long result;
- u32 mdiv, pdiv, sdiv, kdiv;
- u64 tmp;
-
- mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
- pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
- sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
- kdiv = pll_con1 & PLL46XX_KDIV_MASK;
-
- if (pll_type == pll_4650c)
- kdiv = pll_con1 & PLL4650C_KDIV_MASK;
- else
- kdiv = pll_con1 & PLL46XX_KDIV_MASK;
-
- tmp = baseclk;
-
- if (pll_type == pll_4600) {
- tmp *= (mdiv << 16) + kdiv;
- do_div(tmp, (pdiv << sdiv));
- result = tmp >> 16;
- } else {
- tmp *= (mdiv << 10) + kdiv;
- do_div(tmp, (pdiv << sdiv));
- result = tmp >> 10;
- }
-
- return result;
-}
-
-#define PLL90XX_MDIV_MASK (0xFF)
-#define PLL90XX_PDIV_MASK (0x3F)
-#define PLL90XX_SDIV_MASK (0x7)
-#define PLL90XX_KDIV_MASK (0xffff)
-#define PLL90XX_MDIV_SHIFT (16)
-#define PLL90XX_PDIV_SHIFT (8)
-#define PLL90XX_SDIV_SHIFT (0)
-#define PLL90XX_KDIV_SHIFT (0)
-
-static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
- u32 pll_con, u32 pll_conk)
-{
- unsigned long result;
- u32 mdiv, pdiv, sdiv, kdiv;
- u64 tmp;
-
- mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
- pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
- sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
- kdiv = pll_conk & PLL90XX_KDIV_MASK;
-
- /* We need to multiple baseclk by mdiv (the integer part) and kdiv
- * which is in 2^16ths, so shift mdiv up (does not overflow) and
- * add kdiv before multiplying. The use of tmp is to avoid any
- * overflows before shifting bac down into result when multipling
- * by the mdiv and kdiv pair.
- */
-
- tmp = baseclk;
- tmp *= (mdiv << 16) + kdiv;
- do_div(tmp, (pdiv << sdiv));
- result = tmp >> 16;
-
- return result;
-}
-
-#define PLL65XX_MDIV_MASK (0x3FF)
-#define PLL65XX_PDIV_MASK (0x3F)
-#define PLL65XX_SDIV_MASK (0x7)
-#define PLL65XX_MDIV_SHIFT (16)
-#define PLL65XX_PDIV_SHIFT (8)
-#define PLL65XX_SDIV_SHIFT (0)
-
-static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32
pll_con)
-{
- u32 mdiv, pdiv, sdiv;
- u64 fvco = baseclk;
-
- mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
- pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
- sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
-
- fvco *= mdiv;
- do_div(fvco, (pdiv << sdiv));
-
- return (unsigned long)fvco;
-}
diff --git a/arch/arm/plat-samsung/include/plat/pll.h
b/arch/arm/plat-samsung/include/plat/pll.h
new file mode 100644
index 0000000..98dd15e
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pll.h
@@ -0,0 +1,262 @@
+/* linux/arch/arm/plat-samsung/include/plat/pll.h
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * Samsung PLL codes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/div64.h>
+
+#define S3C24XX_PLL_MDIV_MASK (0xFF)
+#define S3C24XX_PLL_PDIV_MASK (0x1F)
+#define S3C24XX_PLL_SDIV_MASK (0x3)
+#define S3C24XX_PLL_MDIV_SHIFT (12)
+#define S3C24XX_PLL_PDIV_SHIFT (4)
+#define S3C24XX_PLL_SDIV_SHIFT (0)
+
+static inline unsigned int s3c24xx_get_pll(unsigned int pllval,
+ unsigned int baseclk)
+{
+ unsigned int mdiv, pdiv, sdiv;
+ uint64_t fvco;
+
+ mdiv = (pllval >> S3C24XX_PLL_MDIV_SHIFT) & S3C24XX_PLL_MDIV_MASK;
+ pdiv = (pllval >> S3C24XX_PLL_PDIV_SHIFT) & S3C24XX_PLL_PDIV_MASK;
+ sdiv = (pllval >> S3C24XX_PLL_SDIV_SHIFT) & S3C24XX_PLL_SDIV_MASK;
+
+ fvco = (uint64_t)baseclk * (mdiv + 8);
+ do_div(fvco, (pdiv + 2) << sdiv);
+
+ return (unsigned int)fvco;
+}
+
+#define S3C2416_PLL_MDIV_MASK (0x3FF)
+#define S3C2416_PLL_PDIV_MASK (0x3F)
+#define S3C2416_PLL_SDIV_MASK (0x7)
+#define S3C2416_PLL_MDIV_SHIFT (14)
+#define S3C2416_PLL_PDIV_SHIFT (5)
+#define S3C2416_PLL_SDIV_SHIFT (0)
+
+static inline unsigned int s3c2416_get_pll(unsigned int pllval,
+ unsigned int baseclk)
+{
+ unsigned int mdiv, pdiv, sdiv;
+ uint64_t fvco;
+
+ mdiv = (pllval >> S3C2416_PLL_MDIV_SHIFT) & S3C2416_PLL_MDIV_MASK;
+ pdiv = (pllval >> S3C2416_PLL_PDIV_SHIFT) & S3C2416_PLL_PDIV_MASK;
+ sdiv = (pllval >> S3C2416_PLL_SDIV_SHIFT) & S3C2416_PLL_SDIV_MASK;
+
+ fvco = (uint64_t)baseclk * mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned int)fvco;
+}
+
+#define S3C6400_PLL_MDIV_MASK (0x3FF)
+#define S3C6400_PLL_PDIV_MASK (0x3F)
+#define S3C6400_PLL_SDIV_MASK (0x7)
+#define S3C6400_PLL_MDIV_SHIFT (16)
+#define S3C6400_PLL_PDIV_SHIFT (8)
+#define S3C6400_PLL_SDIV_SHIFT (0)
+
+static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
+ u32 pllcon)
+{
+ u32 mdiv, pdiv, sdiv;
+ u64 fvco = baseclk;
+
+ mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
+ pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
+ sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+#define PLL6553X_MDIV_MASK (0x7F)
+#define PLL6553X_PDIV_MASK (0x1F)
+#define PLL6553X_SDIV_MASK (0x3)
+#define PLL6553X_KDIV_MASK (0xFFFF)
+#define PLL6553X_MDIV_SHIFT (16)
+#define PLL6553X_PDIV_SHIFT (8)
+#define PLL6553X_SDIV_SHIFT (0)
+
+static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
+ u32 pll_con0, u32 pll_con1)
+{
+ unsigned long result;
+ u32 mdiv, pdiv, sdiv, kdiv;
+ u64 tmp;
+
+ mdiv = (pll_con0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
+ kdiv = pll_con1 & PLL6553X_KDIV_MASK;
+
+ /*
+ * We need to multiple baseclk by mdiv (the integer part) and kdiv
+ * which is in 2^16ths, so shift mdiv up (does not overflow) and
+ * add kdiv before multiplying. The use of tmp is to avoid any
+ * overflows before shifting bac down into result when multipling
+ * by the mdiv and kdiv pair.
+ */
+
+ tmp = baseclk;
+ tmp *= (mdiv << 16) + kdiv;
+ do_div(tmp, (pdiv << sdiv));
+ result = tmp >> 16;
+
+ return result;
+}
+
+#define PLL45XX_MDIV_MASK (0x3FF)
+#define PLL45XX_PDIV_MASK (0x3F)
+#define PLL45XX_SDIV_MASK (0x7)
+#define PLL45XX_MDIV_SHIFT (16)
+#define PLL45XX_PDIV_SHIFT (8)
+#define PLL45XX_SDIV_SHIFT (0)
+
+enum pll45xx_type_t {
+ pll_4500,
+ pll_4502,
+ pll_4508
+};
+
+static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32
pll_con,
+ enum pll45xx_type_t pll_type)
+{
+ u32 mdiv, pdiv, sdiv;
+ u64 fvco = baseclk;
+
+ mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
+
+ if (pll_type == pll_4508)
+ sdiv = sdiv - 1;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+#define PLL46XX_KDIV_MASK (0xFFFF)
+#define PLL4650C_KDIV_MASK (0xFFF)
+#define PLL46XX_MDIV_MASK (0x1FF)
+#define PLL46XX_PDIV_MASK (0x3F)
+#define PLL46XX_SDIV_MASK (0x7)
+#define PLL46XX_MDIV_SHIFT (16)
+#define PLL46XX_PDIV_SHIFT (8)
+#define PLL46XX_SDIV_SHIFT (0)
+
+enum pll46xx_type_t {
+ pll_4600,
+ pll_4650,
+ pll_4650c,
+};
+
+static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
+ u32 pll_con0, u32 pll_con1,
+ enum pll46xx_type_t pll_type)
+{
+ unsigned long result;
+ u32 mdiv, pdiv, sdiv, kdiv;
+ u64 tmp;
+
+ mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
+ kdiv = pll_con1 & PLL46XX_KDIV_MASK;
+
+ if (pll_type == pll_4650c)
+ kdiv = pll_con1 & PLL4650C_KDIV_MASK;
+ else
+ kdiv = pll_con1 & PLL46XX_KDIV_MASK;
+
+ tmp = baseclk;
+
+ if (pll_type == pll_4600) {
+ tmp *= (mdiv << 16) + kdiv;
+ do_div(tmp, (pdiv << sdiv));
+ result = tmp >> 16;
+ } else {
+ tmp *= (mdiv << 10) + kdiv;
+ do_div(tmp, (pdiv << sdiv));
+ result = tmp >> 10;
+ }
+
+ return result;
+}
+
+#define PLL90XX_MDIV_MASK (0xFF)
+#define PLL90XX_PDIV_MASK (0x3F)
+#define PLL90XX_SDIV_MASK (0x7)
+#define PLL90XX_KDIV_MASK (0xffff)
+#define PLL90XX_MDIV_SHIFT (16)
+#define PLL90XX_PDIV_SHIFT (8)
+#define PLL90XX_SDIV_SHIFT (0)
+#define PLL90XX_KDIV_SHIFT (0)
+
+static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
+ u32 pll_con, u32 pll_conk)
+{
+ unsigned long result;
+ u32 mdiv, pdiv, sdiv, kdiv;
+ u64 tmp;
+
+ mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
+ kdiv = pll_conk & PLL90XX_KDIV_MASK;
+
+ /*
+ * We need to multiple baseclk by mdiv (the integer part) and kdiv
+ * which is in 2^16ths, so shift mdiv up (does not overflow) and
+ * add kdiv before multiplying. The use of tmp is to avoid any
+ * overflows before shifting bac down into result when multipling
+ * by the mdiv and kdiv pair.
+ */
+
+ tmp = baseclk;
+ tmp *= (mdiv << 16) + kdiv;
+ do_div(tmp, (pdiv << sdiv));
+ result = tmp >> 16;
+
+ return result;
+}
+
+#define PLL65XX_MDIV_MASK (0x3FF)
+#define PLL65XX_PDIV_MASK (0x3F)
+#define PLL65XX_SDIV_MASK (0x7)
+#define PLL65XX_MDIV_SHIFT (16)
+#define PLL65XX_PDIV_SHIFT (8)
+#define PLL65XX_SDIV_SHIFT (0)
+
+static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32
pll_con)
+{
+ u32 mdiv, pdiv, sdiv;
+ u64 fvco = baseclk;
+
+ mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
diff --git a/arch/arm/plat-samsung/include/plat/pll6553x.h
b/arch/arm/plat-samsung/include/plat/pll6553x.h
deleted file mode 100644
index b8b7e1d..0000000
--- a/arch/arm/plat-samsung/include/plat/pll6553x.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/pll6553x.h
- * partially from arch/arm/mach-s3c64xx/include/mach/pll.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * Samsung PLL6553x PLL code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* S3C6400 and compatible (S3C2416, etc.) EPLL code */
-
-#define PLL6553X_MDIV_MASK ((1 << (23-16)) - 1)
-#define PLL6553X_PDIV_MASK ((1 << (13-8)) - 1)
-#define PLL6553X_SDIV_MASK ((1 << (2-0)) - 1)
-#define PLL6553X_MDIV_SHIFT (16)
-#define PLL6553X_PDIV_SHIFT (8)
-#define PLL6553X_SDIV_SHIFT (0)
-#define PLL6553X_KDIV_MASK (0xffff)
-
-static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
- u32 pll0, u32 pll1)
-{
- unsigned long result;
- u32 mdiv, pdiv, sdiv, kdiv;
- u64 tmp;
-
- mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
- pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
- sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
- kdiv = pll1 & PLL6553X_KDIV_MASK;
-
- /* We need to multiple baseclk by mdiv (the integer part) and kdiv
- * which is in 2^16ths, so shift mdiv up (does not overflow) and
- * add kdiv before multiplying. The use of tmp is to avoid any
- * overflows before shifting bac down into result when multipling
- * by the mdiv and kdiv pair.
- */
-
- tmp = baseclk;
- tmp *= (mdiv << 16) + kdiv;
- do_div(tmp, (pdiv << sdiv));
- result = tmp >> 16;
-
- return result;
-}
--
1.7.1
^ permalink raw reply related
* [PATCH 5/5] ARM: gic: add OF based initialization
From: Dave Martin @ 2011-09-19 12:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110918062144.GF3523@ponder.secretlab.ca>
On Sun, Sep 18, 2011 at 7:21 AM, Grant Likely <grant.likely@secretlab.ca> wrote:
> On Fri, Sep 16, 2011 at 05:09:39PM +0100, Dave Martin wrote:
>> For now, we express the mapping by putting an interrupt-map in the
>> core-tile DT, but this feels inelegant as well as wasteful -- expressing
>> "+ 32" using a table which is about 1K in size and duplicates that
>> information 43 times.
>>
>> Using a dedicated irq domain or a fake interrupt controller node to
>> encapsulate the motherboard interrupts feels like a cleaner approach,
>> but for now I'm not clear on the best way to do it.
>
> An irq nexus node would indeed be something to investigate for your
> particular case. ?Look for examples of interrupt-map. ?It is most
> often used for handling IRQ swizzling on PCI busses.
That's what I currently have -- this is logically correct, and it
works; it just feels like a sledgehammer for cracking this particular
nut, because we don't really have 43 independent interrupt mappings
and types. We have one offset and one type which is applied to all
the interrupts, and this situation is expected to be the same for all
variations of this board, except that offset may change. I suspect
this situation applies to many platforms -- the number of interrupts
may in general be much larger than the number of independent mappings.
Another way of looking at the problem is that it's difficult to come
up with a one-size-fits-all description of interrupt mappings which is
also efficient. Requiring a single set of mapping semantics requires
the mappings to be both rather overspecified for most cases, and
flattened into a large, structureless table which may become pretty
large and unwieldy. If there were 100+ interrupts instead of 43, we'd
really have to be generating the device tree using a script in order
for it to be maintainable (which is not necessarily a problem, but can
be a warning sign)
An alternative approach is to introduce a special interrupt controller
node which serves as the interrupt-parent for the child domain and
maps the interrupts with flexible semantics defined by the node's
bindings; or different kinds of interrupt-map/interrupt-map-mask
properties could be defined. Bindings could be added as needed to
support different cases -- though really we should only expect to have
a small number at most. When the interrupt mapping is significantly
complex, using interrupt-map will probably be the best approach
anyway.
This is just a view for discussion.
For now, I'll keep the interrupt-map for VE. since although it feels
inefficient it is at least obviously correct.
Cheers
---Dave
^ permalink raw reply
* [PATCH 5/5] ARM: gic: add OF based initialization
From: Cousson, Benoit @ 2011-09-19 12:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E76615C.3000005@gmail.com>
On 9/18/2011 11:23 PM, Rob Herring wrote:
> On 09/15/2011 11:43 AM, Rob Herring wrote:
>> On 09/15/2011 08:52 AM, Cousson, Benoit wrote:
>>> On 9/15/2011 3:11 PM, Rob Herring wrote:
>>>> On 09/15/2011 05:07 AM, Cousson, Benoit wrote:
[...]
>>>>> I have another concern on a similar topic.
>>>>>
>>>>> On OMAP4 the SoC interrupts external to the MPU (SPI) have an offset of
>>>>> 32. Only the internal PPI are between 0 and 31.
>>>>>
>>>>> For the moment we add 32 to every SoC interrupts in the irq.h define,
>>>>
>>>> Those defines will not be used in the DT case. So the question is
>>>> whether to add 32 or not in the DT. Since we have just a single node and
>>>> a linear mapping of PPIs and SPIs, the only choice is to have SPIs start
>>>> at 32. And from the h/w definition, SPIs always start at 32, so it's in
>>>> agreement.
>>>
>>> This is a agreement inside the MPUSS, but not outside.
>>> Both Tegra and OMAP4 must add an offset to the HW irq number to deal
>>> with that today.
>>>
>>>>> but I'm assuming that this offset calculation should be done thanks to a
>>>>> dedicated irq domain for the SPI.
>>>>> The real HW physical number start at 0, and thus this is that value that
>>>>> should be in the irq binding of the device.
>>>>>
>>>>> So ideally we should have a irq domain for the PPI starting at 0 and
>>>>> another one for the SPI starting at 32. Or 32 and 64 for the exynos4
>>>>> case, but it looks like the PPI/SPI offset is always 32.
>>>>>
>>>>
>>>> That offset of SPIs is always there. If you have a GIC as a secondary
>>>> controller, It will have 32 reserved interrupts and the register layout
>>>> is exactly the same as a cpu's GIC.
>>>
>>> Yep, but that's the GIC view and not the SoC one. My concern is to have
>>> to tweak the HW number provided by the HW spec in order to add that offset.
>>> If you look at SoC level, the MPUSS is just an IP that can be
>>> potentially replaced by other one that will not have a GIC. In that case
>>> you will not change the IRQ mapping at SoC level.
>>> For example if you replace the Dual-cortexA9 by a single CortexA8, then
>>> all the interrupts will have to be shifted by 32 just because the MPU
>>> subsystem is different.
>>>
>>
>> Is that a realistic case? That would be a new chip and new device tree.
>> You could argue that the whole peripheral subsystem DT could be reused
>> and the numbering needs to be the same. However, there's one thing that
>> would prevent that. The number of interrupt cells is defined by the
>> controller binding. So you have to change the peripheral nodes anyway.
>>
>> It's good that OMAP is trying to standardize the peripheral layout, but
>> in my experience that's not something you can rely on.
>>
>> At some point the interrupt numbering is going to differ from the h/w
>> documentation. If it's not in the DT, then it will be in linux. Right
>> now its just offset of 32, but if irqdescs get assigned on demand as PPC
>> is doing, then there will be no relationship to the documentation.
>>
>>> Since that offset is dependent of the GIC internals and is not exposed
>>> outside the MPUSS, it should not be visible by the SoC IPs. And the HW
>>> spec is exposing exactly that.
>>>
>>>> Since the idea of splitting PPIs for each core out to a flattened linux
>>>> irq map has been abandoned, I see no reason to have more than 1 domain
>>>> with a simple linear translation. Ultimately, domains will do dynamic
>>>> irqdesc allocation and the translation within the gic will be completely
>>>> dynamic.
>>>
>>> I think the only reason to do that is to separate internal MPU
>>> interrupts with the external ones that should not have a clue about the
>>> GIC.
>>
>> I see 2 options (besides leaving it as is):
>>
>> - Revert back to my previous binding where PPIs are a sub-node and a
>> different interrupt parent.
>>
>> - Use the current binding, but allow SPIs to start at 0. We can still
>> distinguish PPIs and SPIs by the cpu mask cell. A cpu mask of 0 is a
>> SPI. If there was ever a reason to have a cpu mask for an SPI, you would
>> not be able to with this scheme.
>>
>> Either way you will still have the above issue with the cell size changing.
>>
>
> I was headed down the path of implementing the 2nd option above, but had
> a dilemma. What would be the numbering base for PPIs in this case?
> Should it be 0 in the DT as proposed for SPIs or does it stay at 16?
Both SGI and PPI are internal to the CortexA9 MP core, and referring to the CortexA9 MP core TRM [1], you can see that the PPI# -> ID# mapping is already documented:
- Private timer, PPI(2) Each Cortex-A9 processor has its own private timers that can generate interrupts, using ID29.
- Watchdog timers, PPI(3) Each Cortex-A9 processor has its own watchdog timers that can generate interrupts, using ID30.
So in that case, it can makes sense to use the ID. But it is interesting to note that the PPI is identified with a 0 based index number.
> Numbering PPIs at 0 will just cause confusion as will numbering
> differently from SPIs. There is absolutely no mention of SPI0 or SPIx
> numbering in the GIC spec.
Probably because it is the generic GIC spec that focus on internals stuff only, it not an integration spec that will show how the SPIs are connected to the outside world. But it is clear that the SPIs are identified as 0-XXX lines outside the Cortex MP core.
In TRM [1] page 53: Shared Peripheral Interrupts (SPI): SPIs are triggered by events generated on associated interrupt input lines. The Interrupt Controller can support up to 224 interrupt input lines. The interrupt input lines can be configured to be edge sensitive (posedge) or level sensitive (high level).
SPIs start at ID32.
> All interrupt number references refer to the
> absolute interrupt ID, not a relative number based on the type. The fact
> that the Cortex-A9 implementation has interrupt lines numbered equal to
> the GIC SPI interrupts is an implementation detail of the A9.
> Other cores could have different arrangement including bringing out PPI
> interrupts or reserving some SPIs.
Absolutely, that's why we should not use that internal GIC convention to capture external IRQ mapping. It you separate the PPI and the SPI controller, you can allow any kind of internal mapping.
> As there are many users of the GIC, it makes more sense to align with
> the GIC documentation rather than the documentation of 1 SOC. BTW, I
> have the exact same issue in our documentation.
It is not about one SoC, this is probably done like that for every other SoCs. I do not have the TRM for the other SoCs, but here is how it is done in various irqs.h file today:
- arch/arm/mach-exynos4/include/mach
/* PPI: Private Peripheral Interrupt */
#define IRQ_PPI(x) S5P_IRQ(x+16)
/* SPI: Shared Peripheral Interrupt */
#define IRQ_SPI(x) S5P_IRQ(x+32)
#define IRQ_EINT0 IRQ_SPI(16)
#define IRQ_EINT1 IRQ_SPI(17)
#define IRQ_EINT2 IRQ_SPI(18)
#define IRQ_EINT3 IRQ_SPI(19)
- arch/arm/mach-tegra/include/mach
/* Primary Interrupt Controller */
#define INT_PRI_BASE (INT_GIC_BASE + 32)
#define INT_TMR1 (INT_PRI_BASE + 0)
#define INT_TMR2 (INT_PRI_BASE + 1)
#define INT_RTC (INT_PRI_BASE + 2)
#define INT_I2S2 (INT_PRI_BASE + 3)
- arch/arm/mach-ux500/include/mach
/* Shared Peripheral Interrupt (SHPI) */
#define IRQ_SHPI_START 32
#define IRQ_MTU0 (IRQ_SHPI_START + 4)
- arch/arm/plat-omap/include/plat
#define OMAP44XX_IRQ_GIC_START 32
#define OMAP44XX_IRQ_PL310 (0 + OMAP44XX_IRQ_GIC_START)
#define OMAP44XX_IRQ_CTI0 (1 + OMAP44XX_IRQ_GIC_START)
#define OMAP44XX_IRQ_CTI1 (2 + OMAP44XX_IRQ_GIC_START)
#define OMAP44XX_IRQ_ELM (4 + OMAP44XX_IRQ_GIC_START)
Every CortexA9 based SoC have to add the 32 offset to the SoC level interrupt number line. The ID numbering scheme is relevant only inside the GIC, but at SoC level only the IRQ lines that entered the MP core are relevant. That ID is a pure internal GIC encoding.
If you refer to the GIC-400 spec [2] (Please note that I do not know what that GIC is exactly...) p 25:
"SPIs are triggered by events generated on associated interrupt input lines. The GIC-400 can support up to 480 SPIs corresponding to the external IRQS[479:0] signal. The number of SPIs available depends on the implemented configuration of the GIC-400. The permitted values are 0-480, in steps of 32. SPIs start at ID32."
In that case the external IRQS numbering scheme is clear: [479:0], which is exactly what will be seen outside of the MP core.
Having two interrupt controllers, one for SGIs + PPIs starting at 0 (hwirq#) and another one from SPIs starting at 32 (hwirq#), seems to me a much better approach. Moreover, it will avoid exposing a cpumask for SPIs.
Regards,
Benoit
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407f/I1006347.html
[2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0471a/DDI0471A_gic400_r0p0_trm.pdf
^ permalink raw reply
* Link failures due to __bug_table in current -next
From: Mark Brown @ 2011-09-19 12:09 UTC (permalink / raw)
To: linux-arm-kernel
I'm seeing linker failures in -next as of today:
`.exit.text' referenced in section `__bug_table' of fs/built-in.o:
defined in discarded section `.exit.text' of fs/built-in.o
`.exit.text' referenced in section `__bug_table' of crypto/built-in.o:
defined in discarded section `.exit.text' of crypto/built-in.o
`.exit.text' referenced in section `__bug_table' of net/built-in.o:
defined in discarded section `.exit.text' of net/built-in.o
`.exit.text' referenced in section `__bug_table' of net/built-in.o:
defined in discarded section `.exit.text' of net/built-in.o
which appears to be due to the chnage to use generic BUG() introduced in
commit 5254a3 (ARM: 7017/1: Use generic BUG() handler), reverting that
commit resolves the issue for me.
I'm wondering if we need something like 7c8a25 (CRIS: Discard exit.text
and .data at runtime) but figuring it out is a bit beyond my ld skills
right now.
^ permalink raw reply
* [PATCH] ARM: kdump: copy kernel relocation code at the kexec prepare stage
From: Russell King - ARM Linux @ 2011-09-19 12:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316151129-30491-1-git-send-email-leiwen@marvell.com>
On Thu, Sep 15, 2011 at 10:32:09PM -0700, Lei Wen wrote:
> diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
> index e59bbd4..f60fc90 100644
> --- a/arch/arm/kernel/machine_kexec.c
> +++ b/arch/arm/kernel/machine_kexec.c
> @@ -32,6 +32,21 @@ static atomic_t waiting_for_crash_ipi;
>
> int machine_kexec_prepare(struct kimage *image)
> {
> + unsigned long page_list;
> + void *reboot_code_buffer;
> + page_list = image->head & PAGE_MASK;
> +
> + reboot_code_buffer = page_address(image->control_code_page);
> +
> + /* Prepare parameters for reboot_code_buffer*/
> + kexec_start_address = image->start;
> + kexec_indirection_page = page_list;
> + kexec_mach_type = machine_arch_type;
> + kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET;
> +
> + /* copy our kernel relocation code to the control code page */
> + memcpy(reboot_code_buffer,
> + relocate_new_kernel, relocate_new_kernel_size);
> return 0;
> }
>
> @@ -82,29 +97,14 @@ void (*kexec_reinit)(void);
>
> void machine_kexec(struct kimage *image)
> {
> - unsigned long page_list;
> unsigned long reboot_code_buffer_phys;
> void *reboot_code_buffer;
>
> -
> - page_list = image->head & PAGE_MASK;
> -
> /* we need both effective and real address here */
> reboot_code_buffer_phys =
> page_to_pfn(image->control_code_page) << PAGE_SHIFT;
> reboot_code_buffer = page_address(image->control_code_page);
>
> - /* Prepare parameters for reboot_code_buffer*/
> - kexec_start_address = image->start;
> - kexec_indirection_page = page_list;
> - kexec_mach_type = machine_arch_type;
> - kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET;
> -
> - /* copy our kernel relocation code to the control code page */
> - memcpy(reboot_code_buffer,
> - relocate_new_kernel, relocate_new_kernel_size);
> -
> -
> flush_icache_range((unsigned long) reboot_code_buffer,
> (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
You should keep this flush with the memcpy - the two are intimately
related - the flush is to ensure I/D cache coherency for the code
which was copied into the page. Splitting them into two different
functions is asking for future bugs.
^ permalink raw reply
* [PATCH 01/11] at91/gpio: make gpio register base soc independant
From: Jean-Christophe PLAGNIOL-VILLARD @ 2011-09-19 12:51 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Reviewed-by: Ryan Mallon <rmallon@gmail.com>
---
arch/arm/mach-at91/at91cap9.c | 8 ++++----
arch/arm/mach-at91/at91rm9200.c | 8 ++++----
arch/arm/mach-at91/at91sam9260.c | 6 +++---
arch/arm/mach-at91/at91sam9261.c | 6 +++---
arch/arm/mach-at91/at91sam9263.c | 10 +++++-----
arch/arm/mach-at91/at91sam9g45.c | 10 +++++-----
arch/arm/mach-at91/at91sam9rl.c | 8 ++++----
arch/arm/mach-at91/generic.h | 2 +-
arch/arm/mach-at91/gpio.c | 8 ++++++--
arch/arm/mach-at91/include/mach/at91cap9.h | 9 +++++----
arch/arm/mach-at91/include/mach/at91rm9200.h | 9 +++++----
arch/arm/mach-at91/include/mach/at91sam9260.h | 7 ++++---
arch/arm/mach-at91/include/mach/at91sam9261.h | 7 ++++---
arch/arm/mach-at91/include/mach/at91sam9263.h | 11 ++++++-----
arch/arm/mach-at91/include/mach/at91sam9g45.h | 11 ++++++-----
arch/arm/mach-at91/include/mach/at91sam9rl.h | 9 +++++----
16 files changed, 70 insertions(+), 59 deletions(-)
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index ecdd54d..fe00dce 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -296,19 +296,19 @@ void __init at91cap9_set_console_clock(int id)
static struct at91_gpio_bank at91cap9_gpio[] = {
{
.id = AT91CAP9_ID_PIOABCD,
- .offset = AT91_PIOA,
+ .regbase = AT91CAP9_BASE_PIOA,
.clock = &pioABCD_clk,
}, {
.id = AT91CAP9_ID_PIOABCD,
- .offset = AT91_PIOB,
+ .regbase = AT91CAP9_BASE_PIOB,
.clock = &pioABCD_clk,
}, {
.id = AT91CAP9_ID_PIOABCD,
- .offset = AT91_PIOC,
+ .regbase = AT91CAP9_BASE_PIOC,
.clock = &pioABCD_clk,
}, {
.id = AT91CAP9_ID_PIOABCD,
- .offset = AT91_PIOD,
+ .regbase = AT91CAP9_BASE_PIOD,
.clock = &pioABCD_clk,
}
};
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 713d3bd..8ce8675 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -271,19 +271,19 @@ void __init at91rm9200_set_console_clock(int id)
static struct at91_gpio_bank at91rm9200_gpio[] = {
{
.id = AT91RM9200_ID_PIOA,
- .offset = AT91_PIOA,
+ .regbase = AT91RM9200_BASE_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91RM9200_ID_PIOB,
- .offset = AT91_PIOB,
+ .regbase = AT91RM9200_BASE_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91RM9200_ID_PIOC,
- .offset = AT91_PIOC,
+ .regbase = AT91RM9200_BASE_PIOC,
.clock = &pioC_clk,
}, {
.id = AT91RM9200_ID_PIOD,
- .offset = AT91_PIOD,
+ .regbase = AT91RM9200_BASE_PIOD,
.clock = &pioD_clk,
}
};
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index a9be758..d7ad3e0 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -265,15 +265,15 @@ void __init at91sam9260_set_console_clock(int id)
static struct at91_gpio_bank at91sam9260_gpio[] = {
{
.id = AT91SAM9260_ID_PIOA,
- .offset = AT91_PIOA,
+ .regbase = AT91SAM9260_BASE_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9260_ID_PIOB,
- .offset = AT91_PIOB,
+ .regbase = AT91SAM9260_BASE_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9260_ID_PIOC,
- .offset = AT91_PIOC,
+ .regbase = AT91SAM9260_BASE_PIOC,
.clock = &pioC_clk,
}
};
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 658a518..574aa6b 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -254,15 +254,15 @@ void __init at91sam9261_set_console_clock(int id)
static struct at91_gpio_bank at91sam9261_gpio[] = {
{
.id = AT91SAM9261_ID_PIOA,
- .offset = AT91_PIOA,
+ .regbase = AT91SAM9261_BASE_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9261_ID_PIOB,
- .offset = AT91_PIOB,
+ .regbase = AT91SAM9261_BASE_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9261_ID_PIOC,
- .offset = AT91_PIOC,
+ .regbase = AT91SAM9261_BASE_PIOC,
.clock = &pioC_clk,
}
};
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index f83fbb0..dee0ed7 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -266,23 +266,23 @@ void __init at91sam9263_set_console_clock(int id)
static struct at91_gpio_bank at91sam9263_gpio[] = {
{
.id = AT91SAM9263_ID_PIOA,
- .offset = AT91_PIOA,
+ .regbase = AT91SAM9263_BASE_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9263_ID_PIOB,
- .offset = AT91_PIOB,
+ .regbase = AT91SAM9263_BASE_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
- .offset = AT91_PIOC,
+ .regbase = AT91SAM9263_BASE_PIOC,
.clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
- .offset = AT91_PIOD,
+ .regbase = AT91SAM9263_BASE_PIOD,
.clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
- .offset = AT91_PIOE,
+ .regbase = AT91SAM9263_BASE_PIOE,
.clock = &pioCDE_clk,
}
};
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 8f5db7b..753df63 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -282,23 +282,23 @@ void __init at91sam9g45_set_console_clock(int id)
static struct at91_gpio_bank at91sam9g45_gpio[] = {
{
.id = AT91SAM9G45_ID_PIOA,
- .offset = AT91_PIOA,
+ .regbase = AT91SAM9G45_BASE_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9G45_ID_PIOB,
- .offset = AT91_PIOB,
+ .regbase = AT91SAM9G45_BASE_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9G45_ID_PIOC,
- .offset = AT91_PIOC,
+ .regbase = AT91SAM9G45_BASE_PIOC,
.clock = &pioC_clk,
}, {
.id = AT91SAM9G45_ID_PIODE,
- .offset = AT91_PIOD,
+ .regbase = AT91SAM9G45_BASE_PIOD,
.clock = &pioDE_clk,
}, {
.id = AT91SAM9G45_ID_PIODE,
- .offset = AT91_PIOE,
+ .regbase = AT91SAM9G45_BASE_PIOE,
.clock = &pioDE_clk,
}
};
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index a238105..c4004e2 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -246,19 +246,19 @@ void __init at91sam9rl_set_console_clock(int id)
static struct at91_gpio_bank at91sam9rl_gpio[] = {
{
.id = AT91SAM9RL_ID_PIOA,
- .offset = AT91_PIOA,
+ .regbase = AT91SAM9RL_BASE_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9RL_ID_PIOB,
- .offset = AT91_PIOB,
+ .regbase = AT91SAM9RL_BASE_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9RL_ID_PIOC,
- .offset = AT91_PIOC,
+ .regbase = AT91SAM9RL_BASE_PIOC,
.clock = &pioC_clk,
}, {
.id = AT91SAM9RL_ID_PIOD,
- .offset = AT91_PIOD,
+ .regbase = AT91SAM9RL_BASE_PIOD,
.clock = &pioD_clk,
}
};
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 938b34f..11d7297 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -65,7 +65,7 @@ extern void at91sam9_alt_reset(void);
struct at91_gpio_bank {
unsigned short id; /* peripheral ID */
- unsigned long offset; /* offset from system peripheral base */
+ unsigned long regbase; /* offset from system peripheral base */
struct clk *clock; /* associated clock */
};
extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 4615528..04beff1 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -616,8 +616,12 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
at91_gpio->bank = &data[i];
at91_gpio->chip.base = PIN_BASE + i * 32;
- at91_gpio->regbase = at91_gpio->bank->offset +
- (void __iomem *)AT91_VA_BASE_SYS;
+
+ at91_gpio->regbase = ioremap(at91_gpio->bank->regbase, 512);
+ if (!at91_gpio->regbase) {
+ pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", i);
+ continue;
+ }
/* enable PIO controller's clock */
clk_enable(at91_gpio->bank->clock);
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index c5df1e8..f65d083 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -88,10 +88,6 @@
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
@@ -102,6 +98,11 @@
(0xfffffd50 - AT91_BASE_SYS) : \
(0xfffffd60 - AT91_BASE_SYS))
+#define AT91CAP9_BASE_PIOA 0xfffff200
+#define AT91CAP9_BASE_PIOB 0xfffff400
+#define AT91CAP9_BASE_PIOC 0xfffff600
+#define AT91CAP9_BASE_PIOD 0xfffff800
+
#define AT91_USART0 AT91CAP9_BASE_US0
#define AT91_USART1 AT91CAP9_BASE_US1
#define AT91_USART2 AT91CAP9_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index e4037b5..5740954 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -81,15 +81,16 @@
*/
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
-#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */
-#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */
-#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */
-#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
+#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
+#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
+#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
+#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
+
#define AT91_USART0 AT91RM9200_BASE_US0
#define AT91_USART1 AT91RM9200_BASE_US1
#define AT91_USART2 AT91RM9200_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 9a79116..1bea3dc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -87,9 +87,6 @@
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
@@ -98,6 +95,10 @@
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
+#define AT91SAM9260_BASE_PIOA 0xfffff400
+#define AT91SAM9260_BASE_PIOB 0xfffff600
+#define AT91SAM9260_BASE_PIOC 0xfffff800
+
#define AT91_USART0 AT91SAM9260_BASE_US0
#define AT91_USART1 AT91SAM9260_BASE_US1
#define AT91_USART2 AT91SAM9260_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index ce59620..17ae9c7 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -70,9 +70,6 @@
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
@@ -81,6 +78,10 @@
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
+#define AT91SAM9261_BASE_PIOA 0xfffff400
+#define AT91SAM9261_BASE_PIOB 0xfffff600
+#define AT91SAM9261_BASE_PIOC 0xfffff800
+
#define AT91_USART0 AT91SAM9261_BASE_US0
#define AT91_USART1 AT91SAM9261_BASE_US1
#define AT91_USART2 AT91SAM9261_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index f1b9296..dd54079 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -84,11 +84,6 @@
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
@@ -98,6 +93,12 @@
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
+#define AT91SAM9263_BASE_PIOA 0xfffff200
+#define AT91SAM9263_BASE_PIOB 0xfffff400
+#define AT91SAM9263_BASE_PIOC 0xfffff600
+#define AT91SAM9263_BASE_PIOD 0xfffff800
+#define AT91SAM9263_BASE_PIOE 0xfffffa00
+
#define AT91_USART0 AT91SAM9263_BASE_US0
#define AT91_USART1 AT91SAM9263_BASE_US1
#define AT91_USART2 AT91SAM9263_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 2c611b9..ec370cc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -94,11 +94,6 @@
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
@@ -108,6 +103,12 @@
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
+#define AT91SAM9G45_BASE_PIOA 0xfffff200
+#define AT91SAM9G45_BASE_PIOB 0xfffff400
+#define AT91SAM9G45_BASE_PIOC 0xfffff600
+#define AT91SAM9G45_BASE_PIOD 0xfffff800
+#define AT91SAM9G45_BASE_PIOE 0xfffffa00
+
#define AT91_USART0 AT91SAM9G45_BASE_US0
#define AT91_USART1 AT91SAM9G45_BASE_US1
#define AT91_USART2 AT91SAM9G45_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 1aabacd..d3ef11a 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -77,10 +77,6 @@
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
@@ -91,6 +87,11 @@
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
+#define AT91SAM9RL_BASE_PIOA 0xfffff400
+#define AT91SAM9RL_BASE_PIOB 0xfffff600
+#define AT91SAM9RL_BASE_PIOC 0xfffff800
+#define AT91SAM9RL_BASE_PIOD 0xfffffa00
+
#define AT91_USART0 AT91SAM9RL_BASE_US0
#define AT91_USART1 AT91SAM9RL_BASE_US1
#define AT91_USART2 AT91SAM9RL_BASE_US2
--
1.7.5.4
^ permalink raw reply related
* [PATCH 02/11] at91/boards: use -1 for invalid gpio
From: Jean-Christophe PLAGNIOL-VILLARD @ 2011-09-19 12:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316436695-19194-1-git-send-email-plagnioj@jcrosoft.com>
this will allow to use gpio_is_valid
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/mach-at91/board-1arm.c | 1 +
arch/arm/mach-at91/board-afeb-9260v1.c | 7 ++++++-
arch/arm/mach-at91/board-cam60.c | 3 ++-
arch/arm/mach-at91/board-cap9adk.c | 14 ++++++++------
arch/arm/mach-at91/board-carmeva.c | 6 ++++--
arch/arm/mach-at91/board-cpu9krea.c | 7 ++++++-
arch/arm/mach-at91/board-cpuat91.c | 4 ++++
arch/arm/mach-at91/board-csb337.c | 4 +++-
arch/arm/mach-at91/board-csb637.c | 1 +
arch/arm/mach-at91/board-eb9200.c | 8 ++++++--
arch/arm/mach-at91/board-ecbat91.c | 4 ++++
arch/arm/mach-at91/board-eco920.c | 4 ++++
arch/arm/mach-at91/board-flexibity.c | 4 +++-
arch/arm/mach-at91/board-foxg20.c | 6 +++++-
arch/arm/mach-at91/board-gsia18s.c | 4 +++-
arch/arm/mach-at91/board-kafa.c | 1 +
arch/arm/mach-at91/board-kb9202.c | 5 ++++-
arch/arm/mach-at91/board-neocore926.c | 4 +++-
arch/arm/mach-at91/board-pcontrol-g20.c | 1 +
arch/arm/mach-at91/board-picotux200.c | 2 ++
arch/arm/mach-at91/board-qil-a9260.c | 11 ++++++-----
arch/arm/mach-at91/board-rm9200dk.c | 10 +++++++---
arch/arm/mach-at91/board-rm9200ek.c | 2 ++
arch/arm/mach-at91/board-sam9-l9260.c | 7 ++++---
arch/arm/mach-at91/board-sam9260ek.c | 11 ++++++-----
arch/arm/mach-at91/board-sam9261ek.c | 8 ++++++--
arch/arm/mach-at91/board-sam9263ek.c | 7 ++++---
arch/arm/mach-at91/board-sam9g20ek.c | 8 +++++++-
arch/arm/mach-at91/board-sam9m10g45ek.c | 3 +++
arch/arm/mach-at91/board-sam9rlek.c | 7 ++++---
arch/arm/mach-at91/board-snapper9260.c | 5 +++++
arch/arm/mach-at91/board-stamp9g20.c | 11 +++++++++--
arch/arm/mach-at91/board-usb-a926x.c | 5 +++--
arch/arm/mach-at91/board-yl-9200.c | 6 ++++--
34 files changed, 141 insertions(+), 50 deletions(-)
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 5aa5885..17d9163 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -70,6 +70,7 @@ static struct at91_eth_data __initdata onearm_eth_data = {
static struct at91_usbh_data __initdata onearm_usbh_data = {
.ports = 1,
+ .vbus_pin = {-1, -1},
};
static struct at91_udc_data __initdata onearm_udc_data = {
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index b0c796d..c489c27 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -75,6 +75,7 @@ static void __init afeb9260_init_early(void)
*/
static struct at91_usbh_data __initdata afeb9260_usbh_data = {
.ports = 1,
+ .vbus_pin = {-1, -1},
};
/*
@@ -82,7 +83,7 @@ static struct at91_usbh_data __initdata afeb9260_usbh_data = {
*/
static struct at91_udc_data __initdata afeb9260_udc_data = {
.vbus_pin = AT91_PIN_PC5,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
@@ -143,6 +144,7 @@ static struct atmel_nand_data __initdata afeb9260_nand_data = {
.enable_pin = AT91_PIN_PC14,
.partition_info = nand_partitions,
.bus_width_16 = 0,
+ .det_pin = -1,
};
@@ -154,6 +156,7 @@ static struct at91_mmc_data __initdata afeb9260_mmc_data = {
.wp_pin = AT91_PIN_PC4,
.slot_b = 1,
.wire4 = 1,
+ .vcc_pin = -1,
};
@@ -174,6 +177,8 @@ static struct i2c_board_info __initdata afeb9260_i2c_devices[] = {
static struct at91_cf_data afeb9260_cf_data = {
.chipselect = 4,
.irq_pin = AT91_PIN_PA6,
+ .det_pin = -1,
+ .vcc_pin = -1,
.rst_pin = AT91_PIN_PA7,
.flags = AT91_CF_TRUE_IDE,
};
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index d1abd58..ed3d87d 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -62,6 +62,7 @@ static void __init cam60_init_early(void)
*/
static struct at91_usbh_data __initdata cam60_usbh_data = {
.ports = 1,
+ .vbus_pin = {-1, -1},
};
@@ -141,7 +142,7 @@ static struct mtd_partition * __init nand_partitions(int size, int *num_partitio
static struct atmel_nand_data __initdata cam60_nand_data = {
.ale = 21,
.cle = 22,
- // .det_pin = ... not there
+ .det_pin = -1,
.rdy_pin = AT91_PIN_PA9,
.enable_pin = AT91_PIN_PA7,
.partition_info = nand_partitions,
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index 679b0b7..da392f3 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -70,6 +70,7 @@ static void __init cap9adk_init_early(void)
*/
static struct at91_usbh_data __initdata cap9adk_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
/*
@@ -144,9 +145,9 @@ static struct spi_board_info cap9adk_spi_devices[] = {
*/
static struct at91_mmc_data __initdata cap9adk_mmc_data = {
.wire4 = 1,
-// .det_pin = ... not connected
-// .wp_pin = ... not connected
-// .vcc_pin = ... not connected
+ .det_pin = -1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
@@ -154,6 +155,7 @@ static struct at91_mmc_data __initdata cap9adk_mmc_data = {
* MACB Ethernet device
*/
static struct at91_eth_data __initdata cap9adk_macb_data = {
+ .phy_irq_pin = -1,
.is_rmii = 1,
};
@@ -178,8 +180,8 @@ static struct mtd_partition * __init nand_partitions(int size, int *num_partitio
static struct atmel_nand_data __initdata cap9adk_nand_data = {
.ale = 21,
.cle = 22,
-// .det_pin = ... not connected
-// .rdy_pin = ... not connected
+ .det_pin = -1,
+ .rdy_pin = -1,
.enable_pin = AT91_PIN_PD15,
.partition_info = nand_partitions,
};
@@ -356,7 +358,7 @@ static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data;
* AC97
*/
static struct ac97c_platform_data cap9adk_ac97_data = {
-// .reset_pin = ... not connected
+ .reset_pin = -1,
};
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index c578c5d..40be90a 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -64,6 +64,7 @@ static struct at91_eth_data __initdata carmeva_eth_data = {
static struct at91_usbh_data __initdata carmeva_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
static struct at91_udc_data __initdata carmeva_udc_data = {
@@ -75,8 +76,8 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
// static struct at91_cf_data __initdata carmeva_cf_data = {
// .det_pin = AT91_PIN_PB0,
// .rst_pin = AT91_PIN_PC5,
- // .irq_pin = ... not connected
- // .vcc_pin = ... always powered
+ // .irq_pin = -1,
+ // .vcc_pin = -1,
// };
static struct at91_mmc_data __initdata carmeva_mmc_data = {
@@ -84,6 +85,7 @@ static struct at91_mmc_data __initdata carmeva_mmc_data = {
.wire4 = 1,
.det_pin = AT91_PIN_PB10,
.wp_pin = AT91_PIN_PC14,
+ .vcc_pin = -1,
};
static struct spi_board_info carmeva_spi_devices[] = {
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index f4da8a1..a8cdccc 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -86,6 +86,7 @@ static void __init cpu9krea_init_early(void)
*/
static struct at91_usbh_data __initdata cpu9krea_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
/*
@@ -93,13 +94,14 @@ static struct at91_usbh_data __initdata cpu9krea_usbh_data = {
*/
static struct at91_udc_data __initdata cpu9krea_udc_data = {
.vbus_pin = AT91_PIN_PC8,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
/*
* MACB Ethernet device
*/
static struct at91_eth_data __initdata cpu9krea_macb_data = {
+ .phy_irq_pin = -1,
.is_rmii = 1,
};
@@ -112,6 +114,7 @@ static struct atmel_nand_data __initdata cpu9krea_nand_data = {
.rdy_pin = AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
.bus_width_16 = 0,
+ .det_pin = -1,
};
#ifdef CONFIG_MACH_CPU9260
@@ -337,6 +340,8 @@ static struct at91_mmc_data __initdata cpu9krea_mmc_data = {
.slot_b = 0,
.wire4 = 1,
.det_pin = AT91_PIN_PA29,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
static void __init cpu9krea_board_init(void)
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 2d919f5..02af1cf 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -83,11 +83,13 @@ static void __init cpuat91_init_early(void)
}
static struct at91_eth_data __initdata cpuat91_eth_data = {
+ .phy_irq_pin = -1,
.is_rmii = 1,
};
static struct at91_usbh_data __initdata cpuat91_usbh_data = {
.ports = 1,
+ .vbus_pin = {-1, -1},
};
static struct at91_udc_data __initdata cpuat91_udc_data = {
@@ -98,6 +100,8 @@ static struct at91_udc_data __initdata cpuat91_udc_data = {
static struct at91_mmc_data __initdata cpuat91_mmc_data = {
.det_pin = AT91_PIN_PC2,
.wire4 = 1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
static struct physmap_flash_data cpuat91_flash_data = {
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 17654d5..c16f0f7 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -65,11 +65,12 @@ static struct at91_eth_data __initdata csb337_eth_data = {
static struct at91_usbh_data __initdata csb337_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
static struct at91_udc_data __initdata csb337_udc_data = {
- // this has no VBUS sensing pin
.pullup_pin = AT91_PIN_PA24,
+ .vbus_pin = -1,
};
static struct i2c_board_info __initdata csb337_i2c_devices[] = {
@@ -98,6 +99,7 @@ static struct at91_mmc_data __initdata csb337_mmc_data = {
.slot_b = 0,
.wire4 = 1,
.wp_pin = AT91_PIN_PD6,
+ .vcc_pin = -1,
};
static struct spi_board_info csb337_spi_devices[] = {
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 72b5567..0e2d219 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -59,6 +59,7 @@ static struct at91_eth_data __initdata csb637_eth_data = {
static struct at91_usbh_data __initdata csb637_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
static struct at91_udc_data __initdata csb637_udc_data = {
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index 01170a2..b920f46 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -67,6 +67,7 @@ static struct at91_eth_data __initdata eb9200_eth_data = {
static struct at91_usbh_data __initdata eb9200_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
static struct at91_udc_data __initdata eb9200_udc_data = {
@@ -75,15 +76,18 @@ static struct at91_udc_data __initdata eb9200_udc_data = {
};
static struct at91_cf_data __initdata eb9200_cf_data = {
+ .irq_pin = -1,
.det_pin = AT91_PIN_PB0,
+ .vcc_pin = -1,
.rst_pin = AT91_PIN_PC5,
- // .irq_pin = ... not connected
- // .vcc_pin = ... always powered
};
static struct at91_mmc_data __initdata eb9200_mmc_data = {
.slot_b = 0,
.wire4 = 1,
+ .det_pin = -1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
static struct i2c_board_info __initdata eb9200_i2c_devices[] = {
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 7c0313c..b2ae86c 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -71,11 +71,15 @@ static struct at91_eth_data __initdata ecb_at91eth_data = {
static struct at91_usbh_data __initdata ecb_at91usbh_data = {
.ports = 1,
+ .vbus_pin = {-1, -1},
};
static struct at91_mmc_data __initdata ecb_at91mmc_data = {
.slot_b = 0,
.wire4 = 1,
+ .det_pin = -1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 8252c72..ca1a7d0 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -54,6 +54,7 @@ static struct at91_eth_data __initdata eco920_eth_data = {
static struct at91_usbh_data __initdata eco920_usbh_data = {
.ports = 1,
+ .vbus_pin = {-1, -1},
};
static struct at91_udc_data __initdata eco920_udc_data = {
@@ -64,6 +65,9 @@ static struct at91_udc_data __initdata eco920_udc_data = {
static struct at91_mmc_data __initdata eco920_mmc_data = {
.slot_b = 0,
.wire4 = 0,
+ .det_pin = -1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
static struct physmap_flash_data eco920_flash_data = {
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 4c3f65d..8605d49 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -52,12 +52,13 @@ static void __init flexibity_init_early(void)
/* USB Host port */
static struct at91_usbh_data __initdata flexibity_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
/* USB Device port */
static struct at91_udc_data __initdata flexibity_udc_data = {
.vbus_pin = AT91_PIN_PC5,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
/* SPI devices */
@@ -76,6 +77,7 @@ static struct at91_mmc_data __initdata flexibity_mmc_data = {
.wire4 = 1,
.det_pin = AT91_PIN_PC9,
.wp_pin = AT91_PIN_PC4,
+ .vcc_pin = -1,
};
/* LEDs */
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index f27d1a7..7a2e505 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -106,6 +106,7 @@ static void __init foxg20_init_early(void)
*/
static struct at91_usbh_data __initdata foxg20_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
/*
@@ -113,7 +114,7 @@ static struct at91_usbh_data __initdata foxg20_usbh_data = {
*/
static struct at91_udc_data __initdata foxg20_udc_data = {
.vbus_pin = AT91_PIN_PC6,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
@@ -147,6 +148,9 @@ static struct at91_eth_data __initdata foxg20_macb_data = {
static struct at91_mmc_data __initdata foxg20_mmc_data = {
.slot_b = 1,
.wire4 = 1,
+ .det_pin = -1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index 2e95949..1c36ea2 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -80,6 +80,7 @@ static void __init gsia18s_init_early(void)
*/
static struct at91_usbh_data __initdata usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
/*
@@ -87,7 +88,7 @@ static struct at91_usbh_data __initdata usbh_data = {
*/
static struct at91_udc_data __initdata udc_data = {
.vbus_pin = AT91_PIN_PA22,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
/*
@@ -530,6 +531,7 @@ static struct i2c_board_info __initdata gsia18s_i2c_devices[] = {
static struct at91_cf_data __initdata gsia18s_cf1_data = {
.irq_pin = AT91_PIN_PA27,
.det_pin = AT91_PIN_PB30,
+ .vcc_pin = -1,
.rst_pin = AT91_PIN_PB31,
.chipselect = 5,
.flags = AT91_CF_TRUE_IDE,
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 4a17089..8d64e90 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -68,6 +68,7 @@ static struct at91_eth_data __initdata kafa_eth_data = {
static struct at91_usbh_data __initdata kafa_usbh_data = {
.ports = 1,
+ .vbus_pin = {-1, -1},
};
static struct at91_udc_data __initdata kafa_udc_data = {
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 9dc8d49..be5ed23 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -76,6 +76,7 @@ static struct at91_eth_data __initdata kb9202_eth_data = {
static struct at91_usbh_data __initdata kb9202_usbh_data = {
.ports = 1,
+ .vbus_pin = {-1, -1},
};
static struct at91_udc_data __initdata kb9202_udc_data = {
@@ -87,6 +88,8 @@ static struct at91_mmc_data __initdata kb9202_mmc_data = {
.det_pin = AT91_PIN_PB2,
.slot_b = 0,
.wire4 = 1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
static struct mtd_partition __initdata kb9202_nand_partition[] = {
@@ -106,7 +109,7 @@ static struct mtd_partition * __init nand_partitions(int size, int *num_partitio
static struct atmel_nand_data __initdata kb9202_nand_data = {
.ale = 22,
.cle = 21,
- // .det_pin = ... not there
+ .det_pin = -1,
.rdy_pin = AT91_PIN_PC29,
.enable_pin = AT91_PIN_PC28,
.partition_info = nand_partitions,
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 9bc6ab3..2f6cc36 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -79,7 +79,7 @@ static struct at91_usbh_data __initdata neocore926_usbh_data = {
*/
static struct at91_udc_data __initdata neocore926_udc_data = {
.vbus_pin = AT91_PIN_PA25,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
@@ -149,6 +149,7 @@ static struct at91_mmc_data __initdata neocore926_mmc_data = {
.wire4 = 1,
.det_pin = AT91_PIN_PE18,
.wp_pin = AT91_PIN_PE19,
+ .vcc_pin = -1,
};
@@ -195,6 +196,7 @@ static struct atmel_nand_data __initdata neocore926_nand_data = {
.rdy_pin_active_low = 1,
.enable_pin = AT91_PIN_PD15,
.partition_info = nand_partitions,
+ .det_pin = -1,
};
static struct sam9_smc_config __initdata neocore926_nand_smc_config = {
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 49e3f69..f817cb8 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -107,6 +107,7 @@ static void __init add_device_pcontrol(void)
*/
static struct at91_usbh_data __initdata usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index b7b8390..88b2a84 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -67,6 +67,7 @@ static struct at91_eth_data __initdata picotux200_eth_data = {
static struct at91_usbh_data __initdata picotux200_usbh_data = {
.ports = 1,
+ .vbus_pin = {-1, -1},
};
static struct at91_mmc_data __initdata picotux200_mmc_data = {
@@ -74,6 +75,7 @@ static struct at91_mmc_data __initdata picotux200_mmc_data = {
.slot_b = 0,
.wire4 = 1,
.wp_pin = AT91_PIN_PA17,
+ .vcc_pin = -1,
};
#define PICOTUX200_FLASH_BASE AT91_CHIPSELECT_0
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 81f9110..1cdde5c 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -77,6 +77,7 @@ static void __init ek_init_early(void)
*/
static struct at91_usbh_data __initdata ek_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
/*
@@ -84,7 +85,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
*/
static struct at91_udc_data __initdata ek_udc_data = {
.vbus_pin = AT91_PIN_PC5,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
/*
@@ -139,7 +140,7 @@ static struct mtd_partition * __init nand_partitions(int size, int *num_partitio
static struct atmel_nand_data __initdata ek_nand_data = {
.ale = 21,
.cle = 22,
-// .det_pin = ... not connected
+ .det_pin = -1,
.rdy_pin = AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
.partition_info = nand_partitions,
@@ -177,9 +178,9 @@ static void __init ek_add_device_nand(void)
static struct at91_mmc_data __initdata ek_mmc_data = {
.slot_b = 0,
.wire4 = 1,
-// .det_pin = ... not connected
-// .wp_pin = ... not connected
-// .vcc_pin = ... not connected
+ .det_pin = -1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
/*
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 6f08faa..5198d87 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -72,6 +72,7 @@ static struct at91_eth_data __initdata dk_eth_data = {
static struct at91_usbh_data __initdata dk_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
static struct at91_udc_data __initdata dk_udc_data = {
@@ -80,16 +81,19 @@ static struct at91_udc_data __initdata dk_udc_data = {
};
static struct at91_cf_data __initdata dk_cf_data = {
+ .irq_pin = -1,
.det_pin = AT91_PIN_PB0,
+ .vcc_pin = -1,
.rst_pin = AT91_PIN_PC5,
- // .irq_pin = ... not connected
- // .vcc_pin = ... always powered
};
#ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
static struct at91_mmc_data __initdata dk_mmc_data = {
.slot_b = 0,
.wire4 = 1,
+ .det_pin = -1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
#endif
@@ -149,7 +153,7 @@ static struct atmel_nand_data __initdata dk_nand_data = {
.cle = 21,
.det_pin = AT91_PIN_PB1,
.rdy_pin = AT91_PIN_PC2,
- // .enable_pin = ... not there
+ .enable_pin = -1,
.partition_info = nand_partitions,
};
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 85bcccd..4fb14c0 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -72,6 +72,7 @@ static struct at91_eth_data __initdata ek_eth_data = {
static struct at91_usbh_data __initdata ek_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
static struct at91_udc_data __initdata ek_udc_data = {
@@ -85,6 +86,7 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
.slot_b = 0,
.wire4 = 1,
.wp_pin = AT91_PIN_PA17,
+ .vcc_pin = -1,
};
#endif
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 4d3a02f..6069d0f 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -72,6 +72,7 @@ static void __init ek_init_early(void)
*/
static struct at91_usbh_data __initdata ek_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
/*
@@ -79,7 +80,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
*/
static struct at91_udc_data __initdata ek_udc_data = {
.vbus_pin = AT91_PIN_PC5,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
@@ -140,7 +141,7 @@ static struct mtd_partition * __init nand_partitions(int size, int *num_partitio
static struct atmel_nand_data __initdata ek_nand_data = {
.ale = 21,
.cle = 22,
-// .det_pin = ... not connected
+ .det_pin = -1,
.rdy_pin = AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
.partition_info = nand_partitions,
@@ -181,7 +182,7 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
.wire4 = 1,
.det_pin = AT91_PIN_PC8,
.wp_pin = AT91_PIN_PC4,
-// .vcc_pin = ... not connected
+ .vcc_pin = -1,
};
static void __init ek_board_init(void)
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 8a50c3e..9681120 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -75,6 +75,7 @@ static void __init ek_init_early(void)
*/
static struct at91_usbh_data __initdata ek_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
/*
@@ -82,7 +83,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
*/
static struct at91_udc_data __initdata ek_udc_data = {
.vbus_pin = AT91_PIN_PC5,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
@@ -182,7 +183,7 @@ static struct mtd_partition * __init nand_partitions(int size, int *num_partitio
static struct atmel_nand_data __initdata ek_nand_data = {
.ale = 21,
.cle = 22,
-// .det_pin = ... not connected
+ .det_pin = -1,
.rdy_pin = AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
.partition_info = nand_partitions,
@@ -228,9 +229,9 @@ static void __init ek_add_device_nand(void)
static struct at91_mmc_data __initdata ek_mmc_data = {
.slot_b = 1,
.wire4 = 1,
-// .det_pin = ... not connected
-// .wp_pin = ... not connected
-// .vcc_pin = ... not connected
+ .det_pin = -1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 5096a0e..8ce4753 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -151,6 +151,7 @@ static void __init ek_add_device_dm9000(void) {}
*/
static struct at91_usbh_data __initdata ek_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
@@ -159,7 +160,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
*/
static struct at91_udc_data __initdata ek_udc_data = {
.vbus_pin = AT91_PIN_PB29,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
@@ -188,7 +189,7 @@ static struct mtd_partition * __init nand_partitions(int size, int *num_partitio
static struct atmel_nand_data __initdata ek_nand_data = {
.ale = 22,
.cle = 21,
-// .det_pin = ... not connected
+ .det_pin = -1,
.rdy_pin = AT91_PIN_PC15,
.enable_pin = AT91_PIN_PC14,
.partition_info = nand_partitions,
@@ -350,6 +351,9 @@ static struct spi_board_info ek_spi_devices[] = {
*/
static struct at91_mmc_data __initdata ek_mmc_data = {
.wire4 = 1,
+ .det_pin = -1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
#endif /* CONFIG_SPI_ATMEL_* */
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index ea8f185..4855a9a 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -81,7 +81,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
*/
static struct at91_udc_data __initdata ek_udc_data = {
.vbus_pin = AT91_PIN_PA25,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
@@ -151,7 +151,7 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
.wire4 = 1,
.det_pin = AT91_PIN_PE18,
.wp_pin = AT91_PIN_PE19,
-// .vcc_pin = ... not connected
+ .vcc_pin = -1,
};
@@ -189,7 +189,7 @@ static struct mtd_partition * __init nand_partitions(int size, int *num_partitio
static struct atmel_nand_data __initdata ek_nand_data = {
.ale = 21,
.cle = 22,
-// .det_pin = ... not connected
+ .det_pin = -1,
.rdy_pin = AT91_PIN_PA22,
.enable_pin = AT91_PIN_PD15,
.partition_info = nand_partitions,
@@ -358,6 +358,7 @@ static void __init ek_add_device_buttons(void) {}
* reset_pin is not connected: NRST
*/
static struct ac97c_platform_data ek_ac97_data = {
+ .reset_pin = -1,
};
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 817f59d..90fb231 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -86,6 +86,7 @@ static void __init ek_init_early(void)
*/
static struct at91_usbh_data __initdata ek_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
/*
@@ -93,7 +94,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
*/
static struct at91_udc_data __initdata ek_udc_data = {
.vbus_pin = AT91_PIN_PC5,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
@@ -170,6 +171,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
.rdy_pin = AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
.partition_info = nand_partitions,
+ .det_pin = -1,
};
static struct sam9_smc_config __initdata ek_nand_smc_config = {
@@ -215,6 +217,7 @@ static struct mci_platform_data __initdata ek_mmc_data = {
.slot[1] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PC9,
+ .wp_pin = -1;
},
};
@@ -223,6 +226,8 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
.slot_b = 1, /* Only one slot so use slot B */
.wire4 = 1,
.det_pin = AT91_PIN_PC9,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
#endif
@@ -232,6 +237,7 @@ static void __init ek_add_device_mmc(void)
if (ek_have_2mmc()) {
ek_mmc_data.slot[0].bus_width = 4;
ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2;
+ ek_mmc_data.slot[0].wp_pin = -1;
}
at91_add_device_mci(0, &ek_mmc_data);
#else
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ad234cc..a5dad78 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -100,6 +100,7 @@ static struct mci_platform_data __initdata mci0_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PD10,
+ .wp_pin = -1;
},
};
@@ -150,6 +151,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
.rdy_pin = AT91_PIN_PC8,
.enable_pin = AT91_PIN_PC14,
.partition_info = nand_partitions,
+ .det_pin = -1,
};
static struct sam9_smc_config __initdata ek_nand_smc_config = {
@@ -335,6 +337,7 @@ static void __init ek_add_device_buttons(void) {}
* reset_pin is not connected: NRST
*/
static struct ac97c_platform_data ek_ac97_data = {
+ .reset_pin = -1,
};
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 4f14b54..903505a 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -67,8 +67,8 @@ static struct usba_platform_data __initdata ek_usba_udc_data = {
static struct at91_mmc_data __initdata ek_mmc_data = {
.wire4 = 1,
.det_pin = AT91_PIN_PA15,
-// .wp_pin = ... not connected
-// .vcc_pin = ... not connected
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
@@ -97,7 +97,7 @@ static struct mtd_partition * __init nand_partitions(int size, int *num_partitio
static struct atmel_nand_data __initdata ek_nand_data = {
.ale = 21,
.cle = 22,
-// .det_pin = ... not connected
+ .det_pin = -1,
.rdy_pin = AT91_PIN_PD17,
.enable_pin = AT91_PIN_PB6,
.partition_info = nand_partitions,
@@ -209,6 +209,7 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data;
* reset_pin is not connected: NRST
*/
static struct ac97c_platform_data ek_ac97_data = {
+ .reset_pin = -1,
};
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index c73d25e..837591b 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -57,15 +57,18 @@ static void __init snapper9260_init_early(void)
static struct at91_usbh_data __initdata snapper9260_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
static struct at91_udc_data __initdata snapper9260_udc_data = {
.vbus_pin = SNAPPER9260_IO_EXP_GPIO(5),
.vbus_active_low = 1,
.vbus_polled = 1,
+ .pullup_pin = -1,
};
static struct at91_eth_data snapper9260_macb_data = {
+ .phy_irq_pin = -1,
.is_rmii = 1,
};
@@ -110,6 +113,8 @@ static struct atmel_nand_data __initdata snapper9260_nand_data = {
.rdy_pin = AT91_PIN_PC13,
.partition_info = snapper9260_nand_partition_info,
.bus_width_16 = 0,
+ .enable_pin = -1,
+ .det_pin = -1,
};
static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 936e5fd..6162976 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -85,6 +85,7 @@ static struct atmel_nand_data __initdata nand_data = {
.rdy_pin = AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
.bus_width_16 = 0,
+ .det_pin = -1,
};
static struct sam9_smc_config __initdata nand_smc_config = {
@@ -122,12 +123,17 @@ static void __init add_device_nand(void)
static struct mci_platform_data __initdata mmc_data = {
.slot[0] = {
.bus_width = 4,
+ .detect_pin = -1;
+ .wp_pin = -1;
},
};
#else
static struct at91_mmc_data __initdata mmc_data = {
.slot_b = 0,
.wire4 = 1,
+ .det_pin = -1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
#endif
@@ -137,6 +143,7 @@ static struct at91_mmc_data __initdata mmc_data = {
*/
static struct at91_usbh_data __initdata usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
@@ -145,12 +152,12 @@ static struct at91_usbh_data __initdata usbh_data = {
*/
static struct at91_udc_data __initdata portuxg20_udc_data = {
.vbus_pin = AT91_PIN_PC7,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
static struct at91_udc_data __initdata stamp9g20evb_udc_data = {
.vbus_pin = AT91_PIN_PA22,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index 260260b..ffa5aab 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -66,6 +66,7 @@ static void __init ek_init_early(void)
*/
static struct at91_usbh_data __initdata ek_usbh_data = {
.ports = 2,
+ .vbus_pin = {-1, -1},
};
/*
@@ -73,7 +74,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
*/
static struct at91_udc_data __initdata ek_udc_data = {
.vbus_pin = AT91_PIN_PB11,
- .pullup_pin = 0, /* pull-up driven by UDC */
+ .pullup_pin = -1, /* pull-up driven by UDC */
};
static void __init ek_add_device_udc(void)
@@ -199,7 +200,7 @@ static struct mtd_partition * __init nand_partitions(int size, int *num_partitio
static struct atmel_nand_data __initdata ek_nand_data = {
.ale = 21,
.cle = 22,
-// .det_pin = ... not connected
+ .det_pin = -1,
.rdy_pin = AT91_PIN_PA22,
.enable_pin = AT91_PIN_PD15,
.partition_info = nand_partitions,
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 95edcbd..5108bd7 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -120,6 +120,7 @@ static struct at91_eth_data __initdata yl9200_eth_data = {
*/
static struct at91_usbh_data __initdata yl9200_usbh_data = {
.ports = 1, /* PQFP version of AT91RM9200 */
+ .vbus_pin = {-1, -1},
};
/*
@@ -137,8 +138,9 @@ static struct at91_udc_data __initdata yl9200_udc_data = {
*/
static struct at91_mmc_data __initdata yl9200_mmc_data = {
.det_pin = AT91_PIN_PB9,
- // .wp_pin = ... not connected
.wire4 = 1,
+ .wp_pin = -1,
+ .vcc_pin = -1,
};
/*
@@ -181,7 +183,7 @@ static struct mtd_partition * __init nand_partitions(int size, int *num_partitio
static struct atmel_nand_data __initdata yl9200_nand_data = {
.ale = 6,
.cle = 7,
- // .det_pin = ... not connected
+ .det_pin = -1,
.rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
.enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
.partition_info = nand_partitions,
--
1.7.5.4
^ permalink raw reply related
* [PATCH 03/11] at91/soc: use gpio_is_valid to check the gpio
From: Jean-Christophe PLAGNIOL-VILLARD @ 2011-09-19 12:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316436695-19194-1-git-send-email-plagnioj@jcrosoft.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/mach-at91/at91cap9_devices.c | 20 ++++++++++----------
arch/arm/mach-at91/at91rm9200_devices.c | 22 +++++++++++-----------
arch/arm/mach-at91/at91sam9260_devices.c | 26 +++++++++++++-------------
arch/arm/mach-at91/at91sam9261_devices.c | 14 +++++++-------
arch/arm/mach-at91/at91sam9263_devices.c | 26 +++++++++++++-------------
arch/arm/mach-at91/at91sam9g45_devices.c | 20 ++++++++++----------
arch/arm/mach-at91/at91sam9rl_devices.c | 16 ++++++++--------
7 files changed, 72 insertions(+), 72 deletions(-)
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index dba0d8d..2838f8b 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -76,7 +76,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
/* Enable VBus control for UHP ports */
for (i = 0; i < data->ports; i++) {
- if (data->vbus_pin[i])
+ if (gpio_is_valid(data->vbus_pin[i]))
at91_set_gpio_output(data->vbus_pin[i], 0);
}
@@ -173,7 +173,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data)
usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
- if (data && data->vbus_pin > 0) {
+ if (data && gpio_is_valid(data->vbus_pin)) {
at91_set_gpio_input(data->vbus_pin, 0);
at91_set_deglitch(data->vbus_pin, 1);
usba_udc_data.pdata.vbus_pin = data->vbus_pin;
@@ -226,7 +226,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
if (!data)
return;
- if (data->phy_irq_pin) {
+ if (gpio_is_valid(data->phy_irq_pin)) {
at91_set_gpio_input(data->phy_irq_pin, 0);
at91_set_deglitch(data->phy_irq_pin, 1);
}
@@ -326,13 +326,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
return;
/* input/irq */
- if (data->det_pin) {
+ if (gpio_is_valid(data->det_pin)) {
at91_set_gpio_input(data->det_pin, 1);
at91_set_deglitch(data->det_pin, 1);
}
- if (data->wp_pin)
+ if (gpio_is_valid(data->wp_pin))
at91_set_gpio_input(data->wp_pin, 1);
- if (data->vcc_pin)
+ if (gpio_is_valid(data->vcc_pin))
at91_set_gpio_output(data->vcc_pin, 0);
if (mmc_id == 0) { /* MCI0 */
@@ -419,15 +419,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
/* enable pin */
- if (data->enable_pin)
+ if (gpio_is_valid(data->enable_pin))
at91_set_gpio_output(data->enable_pin, 1);
/* ready/busy pin */
- if (data->rdy_pin)
+ if (gpio_is_valid(data->rdy_pin))
at91_set_gpio_input(data->rdy_pin, 1);
/* card detect pin */
- if (data->det_pin)
+ if (gpio_is_valid(data->det_pin))
at91_set_gpio_input(data->det_pin, 1);
nand_data = *data;
@@ -801,7 +801,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
at91_set_A_periph(AT91_PIN_PA9, 0); /* AC97RX */
/* reset */
- if (data->reset_pin)
+ if (gpio_is_valid(data->reset_pin))
at91_set_gpio_output(data->reset_pin, 0);
ac97_data = *data;
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 7227755..ff90b63 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -106,11 +106,11 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
if (!data)
return;
- if (data->vbus_pin) {
+ if (gpio_is_valid(data->vbus_pin)) {
at91_set_gpio_input(data->vbus_pin, 0);
at91_set_deglitch(data->vbus_pin, 1);
}
- if (data->pullup_pin)
+ if (gpio_is_valid(data->pullup_pin))
at91_set_gpio_output(data->pullup_pin, 0);
udc_data = *data;
@@ -159,7 +159,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
if (!data)
return;
- if (data->phy_irq_pin) {
+ if (gpio_is_valid(data->phy_irq_pin)) {
at91_set_gpio_input(data->phy_irq_pin, 0);
at91_set_deglitch(data->phy_irq_pin, 1);
}
@@ -252,7 +252,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
);
/* input/irq */
- if (data->irq_pin) {
+ if (gpio_is_valid(data->irq_pin)) {
at91_set_gpio_input(data->irq_pin, 1);
at91_set_deglitch(data->irq_pin, 1);
}
@@ -260,7 +260,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
at91_set_deglitch(data->det_pin, 1);
/* outputs, initially off */
- if (data->vcc_pin)
+ if (gpio_is_valid(data->vcc_pin))
at91_set_gpio_output(data->vcc_pin, 0);
at91_set_gpio_output(data->rst_pin, 0);
@@ -320,13 +320,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
return;
/* input/irq */
- if (data->det_pin) {
+ if (gpio_is_valid(data->det_pin)) {
at91_set_gpio_input(data->det_pin, 1);
at91_set_deglitch(data->det_pin, 1);
}
- if (data->wp_pin)
+ if (gpio_is_valid(data->wp_pin))
at91_set_gpio_input(data->wp_pin, 1);
- if (data->vcc_pin)
+ if (gpio_is_valid(data->vcc_pin))
at91_set_gpio_output(data->vcc_pin, 0);
/* CLK */
@@ -411,15 +411,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
);
/* enable pin */
- if (data->enable_pin)
+ if (gpio_is_valid(data->enable_pin))
at91_set_gpio_output(data->enable_pin, 1);
/* ready/busy pin */
- if (data->rdy_pin)
+ if (gpio_is_valid(data->rdy_pin))
at91_set_gpio_input(data->rdy_pin, 1);
/* card detect pin */
- if (data->det_pin)
+ if (gpio_is_valid(data->det_pin))
at91_set_gpio_input(data->det_pin, 1);
at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 39f81f4..b981a5c 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -107,7 +107,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
if (!data)
return;
- if (data->vbus_pin) {
+ if (gpio_is_valid(data->vbus_pin)) {
at91_set_gpio_input(data->vbus_pin, 0);
at91_set_deglitch(data->vbus_pin, 1);
}
@@ -160,7 +160,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
if (!data)
return;
- if (data->phy_irq_pin) {
+ if (gpio_is_valid(data->phy_irq_pin)) {
at91_set_gpio_input(data->phy_irq_pin, 0);
at91_set_deglitch(data->phy_irq_pin, 1);
}
@@ -235,13 +235,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
return;
/* input/irq */
- if (data->det_pin) {
+ if (gpio_is_valid(data->det_pin)) {
at91_set_gpio_input(data->det_pin, 1);
at91_set_deglitch(data->det_pin, 1);
}
- if (data->wp_pin)
+ if (gpio_is_valid(data->wp_pin))
at91_set_gpio_input(data->wp_pin, 1);
- if (data->vcc_pin)
+ if (gpio_is_valid(data->vcc_pin))
at91_set_gpio_output(data->vcc_pin, 0);
/* CLK */
@@ -322,11 +322,11 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
if (data->slot[i].bus_width) {
/* input/irq */
- if (data->slot[i].detect_pin) {
+ if (gpio_is_valid(data->slot[i].detect_pin)) {
at91_set_gpio_input(data->slot[i].detect_pin, 1);
at91_set_deglitch(data->slot[i].detect_pin, 1);
}
- if (data->slot[i].wp_pin)
+ if (gpio_is_valid(data->slot[i].wp_pin))
at91_set_gpio_input(data->slot[i].wp_pin, 1);
switch (i) {
@@ -418,15 +418,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* enable pin */
- if (data->enable_pin)
+ if (gpio_is_valid(data->enable_pin))
at91_set_gpio_output(data->enable_pin, 1);
/* ready/busy pin */
- if (data->rdy_pin)
+ if (gpio_is_valid(data->rdy_pin))
at91_set_gpio_input(data->rdy_pin, 1);
/* card detect pin */
- if (data->det_pin)
+ if (gpio_is_valid(data->det_pin))
at91_set_gpio_input(data->det_pin, 1);
nand_data = *data;
@@ -1274,17 +1274,17 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
at91_sys_write(AT91_MATRIX_EBICSA, csa);
- if (data->rst_pin) {
+ if (gpio_is_valid(data->rst_pin)) {
at91_set_multi_drive(data->rst_pin, 0);
at91_set_gpio_output(data->rst_pin, 1);
}
- if (data->irq_pin) {
+ if (gpio_is_valid(data->irq_pin)) {
at91_set_gpio_input(data->irq_pin, 0);
at91_set_deglitch(data->irq_pin, 1);
}
- if (data->det_pin) {
+ if (gpio_is_valid(data->det_pin)) {
at91_set_gpio_input(data->det_pin, 0);
at91_set_deglitch(data->det_pin, 1);
}
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 0f91792..0dd3960 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -110,7 +110,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
if (!data)
return;
- if (data->vbus_pin) {
+ if (gpio_is_valid(data->vbus_pin)) {
at91_set_gpio_input(data->vbus_pin, 0);
at91_set_deglitch(data->vbus_pin, 1);
}
@@ -163,13 +163,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
return;
/* input/irq */
- if (data->det_pin) {
+ if (gpio_is_valid(data->det_pin)) {
at91_set_gpio_input(data->det_pin, 1);
at91_set_deglitch(data->det_pin, 1);
}
- if (data->wp_pin)
+ if (gpio_is_valid(data->wp_pin))
at91_set_gpio_input(data->wp_pin, 1);
- if (data->vcc_pin)
+ if (gpio_is_valid(data->vcc_pin))
at91_set_gpio_output(data->vcc_pin, 0);
/* CLK */
@@ -232,15 +232,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* enable pin */
- if (data->enable_pin)
+ if (gpio_is_valid(data->enable_pin))
at91_set_gpio_output(data->enable_pin, 1);
/* ready/busy pin */
- if (data->rdy_pin)
+ if (gpio_is_valid(data->rdy_pin))
at91_set_gpio_input(data->rdy_pin, 1);
/* card detect pin */
- if (data->det_pin)
+ if (gpio_is_valid(data->det_pin))
at91_set_gpio_input(data->det_pin, 1);
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index a050f41..077d853 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -70,7 +70,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
/* Enable VBus control for UHP ports */
for (i = 0; i < data->ports; i++) {
- if (data->vbus_pin[i])
+ if (gpio_is_valid(data->vbus_pin[i]))
at91_set_gpio_output(data->vbus_pin[i], 0);
}
@@ -117,7 +117,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
if (!data)
return;
- if (data->vbus_pin) {
+ if (gpio_is_valid(data->vbus_pin)) {
at91_set_gpio_input(data->vbus_pin, 0);
at91_set_deglitch(data->vbus_pin, 1);
}
@@ -170,7 +170,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
if (!data)
return;
- if (data->phy_irq_pin) {
+ if (gpio_is_valid(data->phy_irq_pin)) {
at91_set_gpio_input(data->phy_irq_pin, 0);
at91_set_deglitch(data->phy_irq_pin, 1);
}
@@ -270,13 +270,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
return;
/* input/irq */
- if (data->det_pin) {
+ if (gpio_is_valid(data->det_pin)) {
at91_set_gpio_input(data->det_pin, 1);
at91_set_deglitch(data->det_pin, 1);
}
- if (data->wp_pin)
+ if (gpio_is_valid(data->wp_pin))
at91_set_gpio_input(data->wp_pin, 1);
- if (data->vcc_pin)
+ if (gpio_is_valid(data->vcc_pin))
at91_set_gpio_output(data->vcc_pin, 0);
if (mmc_id == 0) { /* MCI0 */
@@ -424,17 +424,17 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
}
at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
- if (data->det_pin) {
+ if (gpio_is_valid(data->det_pin)) {
at91_set_gpio_input(data->det_pin, 1);
at91_set_deglitch(data->det_pin, 1);
}
- if (data->irq_pin) {
+ if (gpio_is_valid(data->irq_pin)) {
at91_set_gpio_input(data->irq_pin, 1);
at91_set_deglitch(data->irq_pin, 1);
}
- if (data->vcc_pin)
+ if (gpio_is_valid(data->vcc_pin))
/* initially off */
at91_set_gpio_output(data->vcc_pin, 0);
@@ -494,15 +494,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
/* enable pin */
- if (data->enable_pin)
+ if (gpio_is_valid(data->enable_pin))
at91_set_gpio_output(data->enable_pin, 1);
/* ready/busy pin */
- if (data->rdy_pin)
+ if (gpio_is_valid(data->rdy_pin))
at91_set_gpio_input(data->rdy_pin, 1);
/* card detect pin */
- if (data->det_pin)
+ if (gpio_is_valid(data->det_pin))
at91_set_gpio_input(data->det_pin, 1);
nand_data = *data;
@@ -743,7 +743,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */
/* reset */
- if (data->reset_pin)
+ if (gpio_is_valid(data->reset_pin))
at91_set_gpio_output(data->reset_pin, 0);
ac97_data = *data;
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 600bffb..3a0daa3 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -120,7 +120,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
/* Enable VBus control for UHP ports */
for (i = 0; i < data->ports; i++) {
- if (data->vbus_pin[i])
+ if (gpio_is_valid(data->vbus_pin[i]))
at91_set_gpio_output(data->vbus_pin[i], 0);
}
@@ -175,7 +175,7 @@ void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
/* Enable VBus control for UHP ports */
for (i = 0; i < data->ports; i++) {
- if (data->vbus_pin[i])
+ if (gpio_is_valid(data->vbus_pin[i]))
at91_set_gpio_output(data->vbus_pin[i], 0);
}
@@ -257,7 +257,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data)
usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
- if (data && data->vbus_pin > 0) {
+ if (data && gpio_is_valid(data->vbus_pin)) {
at91_set_gpio_input(data->vbus_pin, 0);
at91_set_deglitch(data->vbus_pin, 1);
usba_udc_data.pdata.vbus_pin = data->vbus_pin;
@@ -310,7 +310,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
if (!data)
return;
- if (data->phy_irq_pin) {
+ if (gpio_is_valid(data->phy_irq_pin)) {
at91_set_gpio_input(data->phy_irq_pin, 0);
at91_set_deglitch(data->phy_irq_pin, 1);
}
@@ -443,11 +443,11 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
/* input/irq */
- if (data->slot[0].detect_pin) {
+ if (gpio_is_valid(data->slot[0].detect_pin)) {
at91_set_gpio_input(data->slot[0].detect_pin, 1);
at91_set_deglitch(data->slot[0].detect_pin, 1);
}
- if (data->slot[0].wp_pin)
+ if (gpio_is_valid(data->slot[0].wp_pin))
at91_set_gpio_input(data->slot[0].wp_pin, 1);
if (mmc_id == 0) { /* MCI0 */
@@ -550,15 +550,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
/* enable pin */
- if (data->enable_pin)
+ if (gpio_is_valid(data->enable_pin))
at91_set_gpio_output(data->enable_pin, 1);
/* ready/busy pin */
- if (data->rdy_pin)
+ if (gpio_is_valid(data->rdy_pin))
at91_set_gpio_input(data->rdy_pin, 1);
/* card detect pin */
- if (data->det_pin)
+ if (gpio_is_valid(data->det_pin))
at91_set_gpio_input(data->det_pin, 1);
nand_data = *data;
@@ -853,7 +853,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
/* reset */
- if (data->reset_pin)
+ if (gpio_is_valid(data->reset_pin))
at91_set_gpio_output(data->reset_pin, 0);
ac97_data = *data;
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index aacb19d..56cb73d 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -147,7 +147,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data)
usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
- if (data && data->vbus_pin > 0) {
+ if (data && gpio_is_valid(data->vbus_pin)) {
at91_set_gpio_input(data->vbus_pin, 0);
at91_set_deglitch(data->vbus_pin, 1);
usba_udc_data.pdata.vbus_pin = data->vbus_pin;
@@ -201,13 +201,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
return;
/* input/irq */
- if (data->det_pin) {
+ if (gpio_is_valid(data->det_pin)) {
at91_set_gpio_input(data->det_pin, 1);
at91_set_deglitch(data->det_pin, 1);
}
- if (data->wp_pin)
+ if (gpio_is_valid(data->wp_pin))
at91_set_gpio_input(data->wp_pin, 1);
- if (data->vcc_pin)
+ if (gpio_is_valid(data->vcc_pin))
at91_set_gpio_output(data->vcc_pin, 0);
/* CLK */
@@ -275,15 +275,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* enable pin */
- if (data->enable_pin)
+ if (gpio_is_valid(data->enable_pin))
at91_set_gpio_output(data->enable_pin, 1);
/* ready/busy pin */
- if (data->rdy_pin)
+ if (gpio_is_valid(data->rdy_pin))
at91_set_gpio_input(data->rdy_pin, 1);
/* card detect pin */
- if (data->det_pin)
+ if (gpio_is_valid(data->det_pin))
at91_set_gpio_input(data->det_pin, 1);
at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
@@ -483,7 +483,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
at91_set_A_periph(AT91_PIN_PD4, 0); /* AC97RX */
/* reset */
- if (data->reset_pin)
+ if (gpio_is_valid(data->reset_pin))
at91_set_gpio_output(data->reset_pin, 0);
ac97_data = *data;
--
1.7.5.4
^ permalink raw reply related
* [PATCH 04/11] at91/pata: use gpio_is_valid to check the gpio
From: Jean-Christophe PLAGNIOL-VILLARD @ 2011-09-19 12:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316436695-19194-1-git-send-email-plagnioj@jcrosoft.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: linux-ide at vger.kernel.org
---
drivers/ata/pata_at91.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/ata/pata_at91.c b/drivers/ata/pata_at91.c
index 960c725..3915353 100644
--- a/drivers/ata/pata_at91.c
+++ b/drivers/ata/pata_at91.c
@@ -360,7 +360,7 @@ static int __devinit pata_at91_probe(struct platform_device *pdev)
ap->flags |= ATA_FLAG_SLAVE_POSS;
ap->pio_mask = ATA_PIO4;
- if (!irq) {
+ if (!gpio_is_valid(irq)) {
ap->flags |= ATA_FLAG_PIO_POLLING;
ata_port_desc(ap, "no IRQ, using PIO polling");
}
@@ -414,8 +414,8 @@ static int __devinit pata_at91_probe(struct platform_device *pdev)
host->private_data = info;
- return ata_host_activate(host, irq ? gpio_to_irq(irq) : 0,
- irq ? ata_sff_interrupt : NULL,
+ return ata_host_activate(host, gpio_is_valid(irq) ? gpio_to_irq(irq) : 0,
+ gpio_is_valid(irq) ? ata_sff_interrupt : NULL,
irq_flags, &pata_at91_sht);
err_put:
--
1.7.5.4
^ permalink raw reply related
* [PATCH 05/11] at91/ide: use gpio_is_valid to check the gpio
From: Jean-Christophe PLAGNIOL-VILLARD @ 2011-09-19 12:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316436695-19194-1-git-send-email-plagnioj@jcrosoft.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: linux-ide at vger.kernel.org
---
Hi,
I'd like to apply this patch via AT91 with the whole gpio patch series
Best Regards,
J.
drivers/ide/at91_ide.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/ide/at91_ide.c b/drivers/ide/at91_ide.c
index 000a78e..ba2eda3 100644
--- a/drivers/ide/at91_ide.c
+++ b/drivers/ide/at91_ide.c
@@ -314,7 +314,7 @@ static int __init at91_ide_probe(struct platform_device *pdev)
apply_timings(board->chipselect, 0, ide_timing_find_mode(XFER_PIO_0), 0);
/* with GPIO interrupt we have to do quirks in handler */
- if (board->irq_pin >= PIN_BASE)
+ if (gpio_is_valid(board->irq_pin))
host->irq_handler = at91_irq_handler;
host->ports[0]->select_data = board->chipselect;
--
1.7.5.4
^ permalink raw reply related
* [PATCH 5/5] ARM: gic: add OF based initialization
From: Thomas Abraham @ 2011-09-19 12:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110918061024.GD3523@ponder.secretlab.ca>
Hi Grant,
On 18 September 2011 11:40, Grant Likely <grant.likely@secretlab.ca> wrote:
> On Fri, Sep 16, 2011 at 03:04:11PM +0530, Thomas Abraham wrote:
>> Hi Rob,
>>
>> On 15 September 2011 18:24, Rob Herring <robherring2@gmail.com> wrote:
>> > On 09/15/2011 02:55 AM, Thomas Abraham wrote:
>> >>> +void __init gic_of_init(struct device_node *node, struct device_node *parent)
>> >>> +{
>> >>> + ? ? ? void __iomem *cpu_base;
>> >>> + ? ? ? void __iomem *dist_base;
>> >>> + ? ? ? int irq;
>> >>> + ? ? ? struct irq_domain *domain = &gic_data[gic_cnt].domain;
>> >>> +
>> >>> + ? ? ? if (WARN_ON(!node))
>> >>> + ? ? ? ? ? ? ? return;
>> >>> +
>> >>> + ? ? ? dist_base = of_iomap(node, 0);
>> >>> + ? ? ? WARN(!dist_base, "unable to map gic dist registers\n");
>> >>> +
>> >>> + ? ? ? cpu_base = of_iomap(node, 1);
>> >>> + ? ? ? WARN(!cpu_base, "unable to map gic cpu registers\n");
>> >>> +
>> >>> + ? ? ? domain->nr_irq = gic_irq_count(dist_base);
>> >>> + ? ? ? domain->irq_base = irq_alloc_descs(-1, 0, domain->nr_irq, numa_node_id());
>> >>
>> >> For exynos4, all the interrupts originating from GIC are statically
>> >> mapped to start from 32 in the linux virq space (GIC SPI interrupts
>> >> start from 64). In the above code, since irq_base would be 0 for
>> >> exynos4, the interrupt mapping is not working correctly. In your
>> >> previous version of the patch, you have given a option to the platform
>> >> code to choose the offset. Could that option be added to this series
>> >> also. Or a provision to use platform specific translate function
>> >> instead of the irq_domain_simple translator.
>> >>
>> >
>> > So I guess you have the A9 external nIRQ hooked up to another
>> > controller? Why can't the 0-31 interrupts get mapped to after the gic
>> > interrupts? Ultimately we want h/w irq numbers completely decoupled from
>> > linux irq numbers. So you will want to put that controller in devicetree
>> > and have an DT init function for it as well.
>>
>> There are chained interrupt handlers mapped in between linux irq
>> number 0 to 31. So the offset for GIC interrupts was set to 32 (SGI[0]
>> = 32). The interrupt chaining for the interrupts mapped between 0 to
>> 31 seems unnecessary though. I will try removing them and check.
>
> Please note; when using the DT, the linux virq number should be
> dynamically assigned and therefore will not matter. ?Historically
> Exynos may have started from irq 32, but it doesn't really have any
> relevance when all IRQ references are via DT irq specifiers.
Ok. But the exynos4 modules that have dt support depend on other
modules that are yet to get dt support. Those modules still use static
linux interrupt numbers and so until all the modules get dt support,
interrupt number specified in dt would have to follow the static
numbering that the rest of the system uses.
So to use Rob's patches for exynos4 dt, the interrupts mapped in the
range 1 to 31 will have to be reworked or moved to some other irq
numbers.
>
> Plus, for dynamically allocated irq_descs, I really want to make sure
> that irq 0 never gets assigned. ?We're not supposed to be using it,
> and that becomes an easy rule to enforce when interrupt numbers are no
> longer assigned with #defines.
>
> g.
>
Thanks,
Thomas.
^ permalink raw reply
* [PATCH 5/5] ARM: gic: add OF based initialization
From: Cousson, Benoit @ 2011-09-19 13:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CA+wbFddVw5+CDMzNXE9Q4-v4kByQmC6xp-rK5e81ChbYFGVe=A@mail.gmail.com>
On 9/19/2011 2:07 PM, Dave Martin wrote:
> On Sun, Sep 18, 2011 at 7:21 AM, Grant Likely<grant.likely@secretlab.ca> wrote:
>> On Fri, Sep 16, 2011 at 05:09:39PM +0100, Dave Martin wrote:
>>> For now, we express the mapping by putting an interrupt-map in the
>>> core-tile DT, but this feels inelegant as well as wasteful -- expressing
>>> "+ 32" using a table which is about 1K in size and duplicates that
>>> information 43 times.
>>>
>>> Using a dedicated irq domain or a fake interrupt controller node to
>>> encapsulate the motherboard interrupts feels like a cleaner approach,
>>> but for now I'm not clear on the best way to do it.
>>
>> An irq nexus node would indeed be something to investigate for your
>> particular case. Look for examples of interrupt-map. It is most
>> often used for handling IRQ swizzling on PCI busses.
>
> That's what I currently have -- this is logically correct, and it
> works; it just feels like a sledgehammer for cracking this particular
> nut, because we don't really have 43 independent interrupt mappings
> and types. We have one offset and one type which is applied to all
> the interrupts, and this situation is expected to be the same for all
> variations of this board, except that offset may change. I suspect
> this situation applies to many platforms -- the number of interrupts
> may in general be much larger than the number of independent mappings.
>
> Another way of looking at the problem is that it's difficult to come
> up with a one-size-fits-all description of interrupt mappings which is
> also efficient. Requiring a single set of mapping semantics requires
> the mappings to be both rather overspecified for most cases, and
> flattened into a large, structureless table which may become pretty
> large and unwieldy. If there were 100+ interrupts instead of 43, we'd
> really have to be generating the device tree using a script in order
> for it to be maintainable (which is not necessarily a problem, but can
> be a warning sign)
Yep, this is exactly the issue I was facing when I tried to map the 128
interrupts lines of an OMAP4 to the GIC. Adding 128 entries to an
interrupt map just to handle a simple linear translation with a constant
value of 32 is clearly overkill.
> An alternative approach is to introduce a special interrupt controller
> node which serves as the interrupt-parent for the child domain and
> maps the interrupts with flexible semantics defined by the node's
> bindings; or different kinds of interrupt-map/interrupt-map-mask
> properties could be defined. Bindings could be added as needed to
> support different cases -- though really we should only expect to have
> a small number at most. When the interrupt mapping is significantly
> complex, using interrupt-map will probably be the best approach
> anyway.
Maybe we can just extend or add a new type of interrupt nexus to handle
simple translation. The actual one was done for complex PCI mapping but
with a small number of lines to handle. In our case, the mapping is
simple, but the number of lines is huge.
Regards,
Benoit
^ permalink raw reply
* [PATCH v2 1/2] OMAP: omap_device: Add omap_device_[alloc|delete] for DT integration
From: Cousson, Benoit @ 2011-09-19 13:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110917160514.GU3523@ponder.secretlab.ca>
On 9/17/2011 6:05 PM, Grant Likely wrote:
> On Fri, Sep 16, 2011 at 04:43:18PM +0200, Benoit Cousson wrote:
>> Split the omap_device_build_ss into two smaller functions
>> that will allow to populate a platform_device already allocated by
>> device-tree.
>> The functionality of the omap_device_build_ss is still the same, but
>> the omap_device_alloc will be usable with devices already built by
>> device-tree.
>>
>> Signed-off-by: Benoit Cousson<b-cousson@ti.com>
>> Cc: Kevin Hilman<khilman@ti.com>
>
> Looks pretty good. Comments below.
>
> g.
>
>> ---
>> arch/arm/plat-omap/omap_device.c | 177 +++++++++++++++++++++++++------------
>> 1 files changed, 119 insertions(+), 58 deletions(-)
>>
>> diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
>> index 54bbe7b..cac7b9a 100644
>> --- a/arch/arm/plat-omap/omap_device.c
>> +++ b/arch/arm/plat-omap/omap_device.c
>> @@ -96,6 +96,11 @@
>>
>> static int omap_device_register(struct platform_device *pdev);
>> static int omap_early_device_register(struct platform_device *pdev);
>> +static struct omap_device *omap_device_alloc(struct platform_device *pdev,
>> + struct omap_hwmod **ohs, int oh_cnt,
>> + struct omap_device_pm_latency *pm_lats,
>> + int pm_lats_cnt);
>> +
>>
>> static struct omap_device_pm_latency omap_default_latency[] = {
>> {
>> @@ -397,6 +402,110 @@ static int omap_device_fill_resources(struct omap_device *od,
>> }
>>
>> /**
>> + * omap_device_alloc - allocate an omap_device
>> + * @pdev: platform_device that will be included in this omap_device
>> + * @oh: ptr to the single omap_hwmod that backs this omap_device
>> + * @pdata: platform_data ptr to associate with the platform_device
>> + * @pdata_len: amount of memory pointed to by @pdata
>> + * @pm_lats: pointer to a omap_device_pm_latency array for this device
>> + * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
>> + *
>> + * Convenience function for allocating an omap_device structure and filling
>> + * hwmods, resources and pm_latency attributes.
>> + *
>> + * Returns an struct omap_device pointer or ERR_PTR() on error;
>> + */
>> +static struct omap_device *omap_device_alloc(struct platform_device *pdev,
>> + struct omap_hwmod **ohs, int oh_cnt,
>> + struct omap_device_pm_latency *pm_lats,
>> + int pm_lats_cnt)
>> +{
>> + int ret = -ENOMEM;
>> + struct omap_device *od;
>> + struct resource *res = NULL;
>> + int i, res_count;
>> + struct omap_hwmod **hwmods;
>> +
>> + od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
>
> possible enhancement: devm_kzalloc() perhaps? Would simplify the cleanup paths.
>
>> + if (!od) {
>> + ret = -ENOMEM;
>> + goto oda_exit1;
>> + }
>> + od->hwmods_cnt = oh_cnt;
>> +
>> + hwmods = kmemdup(ohs, sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
>
> Ditto here. would require creation of devm_kmemdup()
>
>> + if (!hwmods)
>> + goto oda_exit2;
>> +
>> + od->hwmods = hwmods;
>> + od->pdev = pdev;
>> +
>> + /*
>> + * HACK: Ideally the resources from DT should match, and hwmod
>> + * should just add the missing ones. Since the name is not
>> + * properly populated by DT, stick to hwmod resources only.
>> + */
>> + if (pdev->num_resources&& pdev->resource)
>> + dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
>> + __func__, pdev->num_resources);
>> +
>> + res_count = omap_device_count_resources(od);
>> + if (res_count> 0) {
>> + dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
>> + __func__, res_count);
>> + res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
>> + if (!res)
>> + goto oda_exit3;
>> +
>> + omap_device_fill_resources(od, res);
>> +
>> + ret = platform_device_add_resources(pdev, res, res_count);
>> + kfree(res);
>
> How big is res_count? Struct resource isn't very big. It can
> probably be on the stack.
It will depend of the number of entries in the hwmod DB that can vary
from one address space to 10 addresses + a bunch of irqs + a bunch of
dmas. To be honest, that code is just a cut&paste of the original one.
But since that number can vary based on another file content and
considering that this code is supposed to disappear as soon as the
resource will come from DT, I'm not 100% convince it worth the effort.
>> +
>> + if (ret)
>> + goto oda_exit3;
>> + }
>> +
>> + if (!pm_lats) {
>> + pm_lats = omap_default_latency;
>> + pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
>> + }
>> +
>> + od->pm_lats_cnt = pm_lats_cnt;
>> + od->pm_lats = kmemdup(pm_lats,
>> + sizeof(struct omap_device_pm_latency) * pm_lats_cnt,
>> + GFP_KERNEL);
>> + if (!od->pm_lats)
>> + goto oda_exit3;
>> +
>> + pdev->archdata.od = od;
>> +
>> + for (i = 0; i< oh_cnt; i++) {
>> + hwmods[i]->od = od;
>> + _add_hwmod_clocks_clkdev(od, hwmods[i]);
>> + }
>> +
>> + return od;
>> +
>> +oda_exit3:
>> + kfree(hwmods);
>> +oda_exit2:
>> + kfree(od);
>> +oda_exit1:
>> + dev_err(&pdev->dev, "omap_device: build failed (%d)\n", ret);
>> +
>> + return ERR_PTR(ret);
>> +}
>> +
>> +static void omap_device_delete(struct omap_device *od)
>> +{
>> + od->pdev->archdata.od = NULL;
>> + kfree(od->pm_lats);
>> + kfree(od->hwmods);
>> + kfree(od);
>> +}
>> +
>> +/**
>> * omap_device_build - build and register an omap_device with one omap_hwmod
>> * @pdev_name: name of the platform_device driver to use
>> * @pdev_id: this platform_device's connection ID
>> @@ -455,9 +564,6 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
>> int ret = -ENOMEM;
>> struct platform_device *pdev;
>> struct omap_device *od;
>> - struct resource *res = NULL;
>> - int i, res_count;
>> - struct omap_hwmod **hwmods;
>>
>> if (!ohs || oh_cnt == 0 || !pdev_name)
>> return ERR_PTR(-EINVAL);
>> @@ -471,76 +577,31 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
>> goto odbs_exit;
>> }
>>
>> - pr_debug("omap_device: %s: building with %d hwmods\n", pdev_name,
>> - oh_cnt);
>> + /* Set the dev_name early to allow dev_xxx in omap_device_alloc */
>> + if (pdev->id != -1)
>> + dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
>> + else
>> + dev_set_name(&pdev->dev, "%s", pdev->name);
>
> This is duplicated from the core platform_device code. What is the
> reasoning for doing it again here?
Well, it is written in the comment... But this is maybe not that obvious :-)
That part is only needed for the legacy path that will create a
omap_device before having created the device, and thus at that time the
dev_xxx will not give the device name. This is not a big deal, but that
was painful for the debug.
That being said, by writing that, I'm now realizing that this is due to
the way the legacy code was working, because I didn't try to change the
sequence.
But maybe, I can easily avoid that by changing the original sequence.
In fact If I create the omap_device after the omap_device_register, the
platform_device will already have the correct name...
That should work, I'll give it a try.
Thanks for the comments,
Benoit
^ permalink raw reply
* [PATCH v2 2/2] OMAP: omap_device: Add a method to build an omap_device from a DT node
From: Cousson, Benoit @ 2011-09-19 13:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110917161314.GV3523@ponder.secretlab.ca>
On 9/17/2011 6:13 PM, Grant Likely wrote:
> On Fri, Sep 16, 2011 at 04:43:19PM +0200, Benoit Cousson wrote:
>> Add a notifier called during device_add phase. If an of_node is present,
>> retrieve the hwmod entry in order to populate properly the omap_device
>> structure.
>> For the moment the resource from the device-tree are overloaded.
>> DT does not support named resource yet, and thus, most driver
>> will not work without that information.
>>
>> Add two helpers function to parse a property that contains multiple
>> strings.
>>
>> Signed-off-by: Benoit Cousson<b-cousson@ti.com>
>> Cc: Kevin Hilman<khilman@ti.com>
>> ---
>> arch/arm/plat-omap/omap_device.c | 144 ++++++++++++++++++++++++++++++++++++++
>> 1 files changed, 144 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
>> index cac7b9a..da13630 100644
>> --- a/arch/arm/plat-omap/omap_device.c
>> +++ b/arch/arm/plat-omap/omap_device.c
>> @@ -85,6 +85,8 @@
>> #include<linux/clk.h>
>> #include<linux/clkdev.h>
>> #include<linux/pm_runtime.h>
>> +#include<linux/of.h>
>> +#include<linux/notifier.h>
>>
>> #include<plat/omap_device.h>
>> #include<plat/omap_hwmod.h>
>> @@ -94,12 +96,15 @@
>> #define USE_WAKEUP_LAT 0
>> #define IGNORE_WAKEUP_LAT 1
>>
>> +#define MAX_HWMOD_NAME_SIZE 32
>> +
>> static int omap_device_register(struct platform_device *pdev);
>> static int omap_early_device_register(struct platform_device *pdev);
>> static struct omap_device *omap_device_alloc(struct platform_device *pdev,
>> struct omap_hwmod **ohs, int oh_cnt,
>> struct omap_device_pm_latency *pm_lats,
>> int pm_lats_cnt);
>> +static void omap_device_delete(struct omap_device *od);
>>
>>
>> static struct omap_device_pm_latency omap_default_latency[] = {
>> @@ -315,6 +320,138 @@ static void _add_hwmod_clocks_clkdev(struct omap_device *od,
>> _add_clkdev(od, oh->opt_clks[i].role, oh->opt_clks[i].clk);
>> }
>>
>> +/*
>> + * XXX: DT helper functions that should probably move elsewhere if
>> + * they become usefull for other needs.
>> + */
>
> Lets just *assume* these are useful for other needs and start with
> them in drivers/of so that other people know that they actually exist.
> Otherwise they will never be made generic. :-)
Good point...
But, meanwhile Stephen Warren proposed a much nicer iterator to deal
with that. Since these patches are still not in mainline, I didn't want
to depend on them yet. So my "secret" plan was to remove these functions
once the ones from Stephen will be merged.
>> +static int _dt_count_property_string(const char *prop, int len)
>> +{
>> + int i = 0;
>> + size_t l = 0, total = 0;
>> +
>> + if (!prop || !len)
>> + return -EINVAL;
>> +
>> + for (i = 0; len>= total; total += l, prop += l) {
>> + l = strlen(prop) + 1;
>> + if (*prop != 0)
>> + i++;
>> + }
>> + return i;
>> +}
>> +
>> +static int _dt_get_property(const char *prop, int len, int index, char *output,
>> + int size)
>> +{
>> + int i = 0;
>> + size_t l = 0, total = 0;
>> +
>> + if (!prop || !len)
>> + return -EINVAL;
>> +
>> + for (i = 0; len>= total; total += l, prop += l) {
>> + l = strlcpy(output, prop, size) + 1;
>> + if (*prop != 0) {
>> + if (i++ == index)
>> + return 0;
>> + }
>> + }
>> + return -ENODEV;
>> +}
>> +
>> +static struct dev_pm_domain omap_device_pm_domain;
>> +
>> +/**
>> + * omap_device_build_from_dt - build an omap_device with multiple hwmods
>> + * @pdev_name: name of the platform_device driver to use
>> + * @pdev_id: this platform_device's connection ID
>> + * @oh: ptr to the single omap_hwmod that backs this omap_device
>> + * @pdata: platform_data ptr to associate with the platform_device
>> + * @pdata_len: amount of memory pointed to by @pdata
>> + * @pm_lats: pointer to a omap_device_pm_latency array for this device
>> + * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
>> + * @is_early_device: should the device be registered as an early device or not
>> + *
>> + * Function for building an omap_device already registered from device-tree
>> + *
>> + * Returns 0 or PTR_ERR() on error.
>> + */
>> +static int omap_device_build_from_dt(struct platform_device *pdev)
>> +{
>> + struct omap_hwmod **hwmods;
>> + struct omap_device *od;
>> + struct omap_hwmod *oh;
>> + char oh_name[MAX_HWMOD_NAME_SIZE];
>> + const char *prop;
>> + int oh_cnt, i, prop_len;
>> + int ret = 0;
>> +
>> + prop = of_get_property(pdev->dev.of_node, "hwmods",&prop_len);
>
> I know you've posted it before, but what is the status of the "hwmods"
> binding documentation. I would expect it to be part of this patch.
It was part of the series that introduced the first node with hwmods
attribute
(http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-August/007621.html).
I do agree, it makes sense to add it here.
>> + oh_cnt = _dt_count_property_string(prop, prop_len);
>> + if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) {
>> + dev_warn(&pdev->dev, "No 'hwmods' to build omap_device\n");
>> + return -ENODEV;
>> + }
>> +
>> + hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
>> + if (!hwmods) {
>> + ret = -ENOMEM;
>> + goto odbfd_exit;
>> + }
>> +
>> + for (i = 0; i< oh_cnt; i++) {
>> + _dt_get_property(prop, prop_len, i, oh_name,
>> + MAX_HWMOD_NAME_SIZE);
>> +
>> + oh = omap_hwmod_lookup(oh_name);
>> + if (!oh) {
>> + dev_err(&pdev->dev, "Cannot lookup hwmod '%s'\n",
>> + oh_name);
>> + ret = -EINVAL;
>> + goto odbfd_exit1;
>> + }
>> + hwmods[i] = oh;
>> + }
>> +
>> + od = omap_device_alloc(pdev, hwmods, oh_cnt, NULL, 0);
>> + if (!od) {
>> + dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",
>> + oh_name);
>> + ret = PTR_ERR(od);
>> + goto odbfd_exit1;
>> + }
>> +
>> + if (of_get_property(pdev->dev.of_node, "no_idle_on_suspend", NULL))
>> + omap_device_disable_idle_on_suspend(pdev);
>> +
>> + pdev->dev.pm_domain =&omap_device_pm_domain;
>> +
>> +odbfd_exit1:
>> + kfree(hwmods);
>> +odbfd_exit:
>> + return ret;
>> +}
>> +
>> +static int _omap_device_notifier_call(struct notifier_block *nb,
>> + unsigned long event, void *dev)
>
> Nit: Why the preceding underscore? Generally that is only done for
> 'special' variants of public functions. ie. for a variant that
> expects a lock to already be held.
Yeah, the convention in this file is not that strict, and it is used for
internal static helper function as well.
I'll let Kevin arbitrate that point :-)
>> +{
>> + struct platform_device *pdev = to_platform_device(dev);
>> +
>> + switch (event) {
>> + case BUS_NOTIFY_ADD_DEVICE:
>> + if (pdev->dev.of_node)
>> + omap_device_build_from_dt(pdev);
>> + break;
>> +
>> + case BUS_NOTIFY_DEL_DEVICE:
>> + if (pdev->archdata.od)
>> + omap_device_delete(pdev->archdata.od);
>> + break;
>> + }
>> +
>> + return NOTIFY_DONE;
>> +}
>> +
>>
>> /* Public functions for use by core code */
>>
>> @@ -499,6 +636,9 @@ oda_exit1:
>>
>> static void omap_device_delete(struct omap_device *od)
>> {
>> + if (!od)
>> + return;
>> +
>> od->pdev->archdata.od = NULL;
>> kfree(od->pm_lats);
>> kfree(od->hwmods);
>> @@ -1034,8 +1174,12 @@ struct device omap_device_parent = {
>> .parent =&platform_bus,
>> };
>>
>> +static struct notifier_block platform_nb;
>
> Nit: Since it is static initialization, you can do the following
> instead of setting it up in the init function.
>
> static struct notifier_block platform_nb = {
> .notifier_call = _omap_device_notifier_call;
> };
Much better, indeed.
Thanks,
Benoit
^ permalink raw reply
* [RFC v3] arm: Add platform bus driver for memory mapped virtio device
From: Anthony Liguori @ 2011-09-19 13:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <874o09ryzm.fsf@rustcorp.com.au>
On 09/18/2011 10:29 PM, Rusty Russell wrote:
> On Fri, 16 Sep 2011 12:01:49 -0500, Anthony Liguori<aliguori@us.ibm.com> wrote:
>> On 09/16/2011 11:47 AM, Pawel Moll wrote:
>>> This patch, based on virtio PCI driver, adds support for memory
>>> mapped (platform) virtio device. This should allow environments
>>> like qemu to use virtio-based block& network devices.
>>>
>>> One can define and register a platform device which resources
>>> will describe memory mapped control registers and "mailbox"
>>> interrupt. Such device can be also instantiated using the Device
>>> Tree node with compatible property equal "virtio,mmio".
>>>
>>> Cc: Rusty Russell<rusty@rustcorp.com.au>
>>> Cc: Anthony Liguori<aliguori@us.ibm.com>
>>> Cc: Michael S.Tsirkin<mst@redhat.com>
>>> Signed-off-by: Pawel Moll<pawel.moll@arm.com>
>>
>> Have you written a specification for this device?
>>
>> Rusty maintains a formal spec for all virtio devices at:
>>
>> http://ozlabs.org/~rusty/virtio-spec/
>>
>> The spec should be written before merging the code to make sure that there
>> aren't future compatibility problems.
>
> A good idea, but the current spec is for PCI. I wonder if we should
> move the PCI part out to an appendix and make it more general?
>
> Meanwhile, perhaps this would be suitable as an appendix.
I was thinking an appendix would be a good start.
Regards,
Anthony Liguori
>
> Cheers,
> Rusty.
^ permalink raw reply
* [PATCH 5/5] ARM: gic: add OF based initialization
From: Russell King - ARM Linux @ 2011-09-19 13:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E770FA6.2070305@ti.com>
On Mon, Sep 19, 2011 at 11:47:18AM +0200, Cousson, Benoit wrote:
> Since the cpumask is not relevant for the SPI, maybe having two
> interrupt controllers will be more relevant. Or maybe 3, since there is
> some SGIs as well.
I don't think anyone uses SGIs outside of the common SMP code.
Therefore they're handled entirely separately for the root GIC.
(If there's two GICs - some platforms do have two - then the SGIs on
the non-root GIC are unused.)
^ permalink raw reply
* [PATCH 06/19] ARM: mach-at91: remove arch specific special handling for ioremap
From: Jean-Christophe PLAGNIOL-VILLARD @ 2011-09-19 13:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316156850-31013-7-git-send-email-nico@fluxnic.net>
On 03:07 Fri 16 Sep , Nicolas Pitre wrote:
> From: Nicolas Pitre <nicolas.pitre@linaro.org>
>
> A generic version should replace this later.
>
> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Untill the replace will availlable
do not remove it
Best Regards,
J.
^ permalink raw reply
* [PATCH 5/5] ARM: gic: add OF based initialization
From: Rob Herring @ 2011-09-19 13:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E77310A.3000106@ti.com>
On 09/19/2011 07:09 AM, Cousson, Benoit wrote:
> On 9/18/2011 11:23 PM, Rob Herring wrote:
>> On 09/15/2011 11:43 AM, Rob Herring wrote:
>>> On 09/15/2011 08:52 AM, Cousson, Benoit wrote:
>>>> On 9/15/2011 3:11 PM, Rob Herring wrote:
>>>>> On 09/15/2011 05:07 AM, Cousson, Benoit wrote:
>
> [...]
>
>>>>>> I have another concern on a similar topic.
>>>>>>
>>>>>> On OMAP4 the SoC interrupts external to the MPU (SPI) have
>>>>>> an offset of 32. Only the internal PPI are between 0 and
>>>>>> 31.
>>>>>>
>>>>>> For the moment we add 32 to every SoC interrupts in the
>>>>>> irq.h define,
>>>>>
>>>>> Those defines will not be used in the DT case. So the
>>>>> question is whether to add 32 or not in the DT. Since we have
>>>>> just a single node and a linear mapping of PPIs and SPIs, the
>>>>> only choice is to have SPIs start at 32. And from the h/w
>>>>> definition, SPIs always start at 32, so it's in agreement.
>>>>
>>>> This is a agreement inside the MPUSS, but not outside. Both
>>>> Tegra and OMAP4 must add an offset to the HW irq number to
>>>> deal with that today.
>>>>
>>>>>> but I'm assuming that this offset calculation should be
>>>>>> done thanks to a dedicated irq domain for the SPI. The real
>>>>>> HW physical number start at 0, and thus this is that value
>>>>>> that should be in the irq binding of the device.
>>>>>>
>>>>>> So ideally we should have a irq domain for the PPI starting
>>>>>> at 0 and another one for the SPI starting at 32. Or 32 and
>>>>>> 64 for the exynos4 case, but it looks like the PPI/SPI
>>>>>> offset is always 32.
>>>>>>
>>>>>
>>>>> That offset of SPIs is always there. If you have a GIC as a
>>>>> secondary controller, It will have 32 reserved interrupts and
>>>>> the register layout is exactly the same as a cpu's GIC.
>>>>
>>>> Yep, but that's the GIC view and not the SoC one. My concern is
>>>> to have to tweak the HW number provided by the HW spec in order
>>>> to add that offset. If you look at SoC level, the MPUSS is just
>>>> an IP that can be potentially replaced by other one that will
>>>> not have a GIC. In that case you will not change the IRQ
>>>> mapping at SoC level. For example if you replace the
>>>> Dual-cortexA9 by a single CortexA8, then all the interrupts
>>>> will have to be shifted by 32 just because the MPU subsystem is
>>>> different.
>>>>
>>>
>>> Is that a realistic case? That would be a new chip and new device
>>> tree. You could argue that the whole peripheral subsystem DT
>>> could be reused and the numbering needs to be the same. However,
>>> there's one thing that would prevent that. The number of
>>> interrupt cells is defined by the controller binding. So you have
>>> to change the peripheral nodes anyway.
>>>
>>> It's good that OMAP is trying to standardize the peripheral
>>> layout, but in my experience that's not something you can rely
>>> on.
>>>
>>> At some point the interrupt numbering is going to differ from the
>>> h/w documentation. If it's not in the DT, then it will be in
>>> linux. Right now its just offset of 32, but if irqdescs get
>>> assigned on demand as PPC is doing, then there will be no
>>> relationship to the documentation.
>>>
>>>> Since that offset is dependent of the GIC internals and is not
>>>> exposed outside the MPUSS, it should not be visible by the SoC
>>>> IPs. And the HW spec is exposing exactly that.
>>>>
>>>>> Since the idea of splitting PPIs for each core out to a
>>>>> flattened linux irq map has been abandoned, I see no reason
>>>>> to have more than 1 domain with a simple linear translation.
>>>>> Ultimately, domains will do dynamic irqdesc allocation and
>>>>> the translation within the gic will be completely dynamic.
>>>>
>>>> I think the only reason to do that is to separate internal MPU
>>>> interrupts with the external ones that should not have a clue
>>>> about the GIC.
>>>
>>> I see 2 options (besides leaving it as is):
>>>
>>> - Revert back to my previous binding where PPIs are a sub-node
>>> and a different interrupt parent.
>>>
>>> - Use the current binding, but allow SPIs to start at 0. We can
>>> still distinguish PPIs and SPIs by the cpu mask cell. A cpu mask
>>> of 0 is a SPI. If there was ever a reason to have a cpu mask for
>>> an SPI, you would not be able to with this scheme.
>>>
>>> Either way you will still have the above issue with the cell size
>>> changing.
>>>
>>
>> I was headed down the path of implementing the 2nd option above,
>> but had a dilemma. What would be the numbering base for PPIs in
>> this case? Should it be 0 in the DT as proposed for SPIs or does it
>> stay at 16?
>
> Both SGI and PPI are internal to the CortexA9 MP core, and referring
> to the CortexA9 MP core TRM [1], you can see that the PPI# -> ID#
> mapping is already documented: - Private timer, PPI(2) Each Cortex-A9
> processor has its own private timers that can generate interrupts,
> using ID29. - Watchdog timers, PPI(3) Each Cortex-A9 processor has
> its own watchdog timers that can generate interrupts, using ID30.
>
> So in that case, it can makes sense to use the ID. But it is
> interesting to note that the PPI is identified with a 0 based index
> number.
>
It's even worse than I thought: we could use 13 (ID16 == PPI0), 29 or 2
for the timer interrupt. The first would match 0 based SPI convention.
The last 2 would both match the documentation. We could never use 2 as
this will for sure be different and the GIC code will have no way to
know how to do the translation to ID. The only sane choice is using the
ID as you say.
But you can't have it both ways. It does not make sense to use the ID
for some interrupts and a different scheme for others.
>> Numbering PPIs at 0 will just cause confusion as will numbering
>> differently from SPIs. There is absolutely no mention of SPI0 or
>> SPIx numbering in the GIC spec.
>
> Probably because it is the generic GIC spec that focus on internals
> stuff only, it not an integration spec that will show how the SPIs
> are connected to the outside world. But it is clear that the SPIs are
> identified as 0-XXX lines outside the Cortex MP core.
>
What if the A9 or some other implementation used some SPIs internally?
Then the external connection would be shifted differently. The interrupt
binding for a peripheral is defined by it's interrupt parent (the
interrupt controller). The number of cells and what the values mean are
defined by the interrupt controller binding. This is independent of any
SOC. The binding must be defined from the perspective of the interrupt
controller.
> In TRM [1] page 53: Shared Peripheral Interrupts (SPI): SPIs are
> triggered by events generated on associated interrupt input lines.
> The Interrupt Controller can support up to 224 interrupt input lines.
> The interrupt input lines can be configured to be edge sensitive
> (posedge) or level sensitive (high level). SPIs start at ID32.
>
>> All interrupt number references refer to the absolute interrupt ID,
>> not a relative number based on the type. The fact that the
>> Cortex-A9 implementation has interrupt lines numbered equal to the
>> GIC SPI interrupts is an implementation detail of the A9.
>
>> Other cores could have different arrangement including bringing out
>> PPI interrupts or reserving some SPIs.
>
> Absolutely, that's why we should not use that internal GIC convention
> to capture external IRQ mapping. It you separate the PPI and the SPI
> controller, you can allow any kind of internal mapping.
>
The GIC convention is the only part that is consistent and not dependent
on the implementation.
>> As there are many users of the GIC, it makes more sense to align
>> with the GIC documentation rather than the documentation of 1 SOC.
>> BTW, I have the exact same issue in our documentation.
>
> It is not about one SoC, this is probably done like that for every
> other SoCs. I do not have the TRM for the other SoCs, but here is how
> it is done in various irqs.h file today:
>
> - arch/arm/mach-exynos4/include/mach
>
> /* PPI: Private Peripheral Interrupt */ #define IRQ_PPI(x)
> S5P_IRQ(x+16)
>
> /* SPI: Shared Peripheral Interrupt */ #define IRQ_SPI(x)
> S5P_IRQ(x+32)
>
> #define IRQ_EINT0 IRQ_SPI(16) #define IRQ_EINT1 IRQ_SPI(17) #define
> IRQ_EINT2 IRQ_SPI(18) #define IRQ_EINT3 IRQ_SPI(19)
>
>
> - arch/arm/mach-tegra/include/mach
>
> /* Primary Interrupt Controller */ #define INT_PRI_BASE
> (INT_GIC_BASE + 32) #define INT_TMR1 (INT_PRI_BASE + 0) #define
> INT_TMR2 (INT_PRI_BASE + 1) #define INT_RTC (INT_PRI_BASE + 2)
> #define INT_I2S2 (INT_PRI_BASE + 3)
>
>
> - arch/arm/mach-ux500/include/mach
>
> /* Shared Peripheral Interrupt (SHPI) */ #define IRQ_SHPI_START 32
>
> #define IRQ_MTU0 (IRQ_SHPI_START + 4)
>
>
> - arch/arm/plat-omap/include/plat
>
> #define OMAP44XX_IRQ_GIC_START 32
>
> #define OMAP44XX_IRQ_PL310 (0 + OMAP44XX_IRQ_GIC_START) #define
> OMAP44XX_IRQ_CTI0 (1 + OMAP44XX_IRQ_GIC_START) #define
> OMAP44XX_IRQ_CTI1 (2 + OMAP44XX_IRQ_GIC_START) #define
> OMAP44XX_IRQ_ELM (4 + OMAP44XX_IRQ_GIC_START)
>
>
> Every CortexA9 based SoC have to add the 32 offset to the SoC level
> interrupt number line. The ID numbering scheme is relevant only
> inside the GIC, but at SoC level only the IRQ lines that entered the
> MP core are relevant. That ID is a pure internal GIC encoding.
>
Exactly. For DT, the irq numbering is supposed to be local to the
interrupt controller. So from a GIC perspective, what numbering makes sense?
It's also relevant to the software running on the system.
> If you refer to the GIC-400 spec [2] (Please note that I do not know
> what that GIC is exactly...) p 25: "SPIs are triggered by events
> generated on associated interrupt input lines. The GIC-400 can
> support up to 480 SPIs corresponding to the external IRQS[479:0]
> signal. The number of SPIs available depends on the implemented
> configuration of the GIC-400. The permitted values are 0-480, in
> steps of 32. SPIs start at ID32."
>
> In that case the external IRQS numbering scheme is clear: [479:0],
> which is exactly what will be seen outside of the MP core.
>
> Having two interrupt controllers, one for SGIs + PPIs starting at 0
> (hwirq#) and another one from SPIs starting at 32 (hwirq#), seems to
> me a much better approach. Moreover, it will avoid exposing a cpumask
> for SPIs.
>
Having implemented both ways already, I'm fine either way, but the
current consensus seems to be to use the cpumask.
Rob
> Regards, Benoit
>
>
> [1]
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407f/I1006347.html
>
> [2]
> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0471a/DDI0471A_gic400_r0p0_trm.pdf
>
>
>
>
^ permalink raw reply
* [PATCH] ARM: mach-qong: Add watchdog support
From: Fabio Estevam @ 2011-09-19 13:59 UTC (permalink / raw)
To: linux-arm-kernel
Add watchdog support for mach-qong target.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/mach-imx/Kconfig | 1 +
arch/arm/mach-imx/mach-qong.c | 1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0519dd7..8748531 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -485,6 +485,7 @@ config MACH_QONG
bool "Support Dave/DENX QongEVB-LITE platform"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_IMX2_WDT
help
Include support for Dave/DENX QongEVB-LITE platform. This includes
specific configurations for the board and its peripherals.
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 3626f48..44462ce 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -249,6 +249,7 @@ static void __init qong_init(void)
mxc_init_imx_uart();
qong_init_nor_mtd();
qong_init_fpga();
+ imx31_add_imx2_wdt(NULL);
}
static void __init qong_timer_init(void)
--
1.6.0.4
^ permalink raw reply related
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