* [PATCH v3 2/3] net/fec: fix fec1 check in fec_enet_mii_init()
From: Shawn Guo @ 2011-09-21 16:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316621270-27805-1-git-send-email-shawn.guo@linaro.org>
In function fec_enet_mii_init(), it uses non-zero pdev->id as part
of the condition to check the second fec instance (fec1). This works
before the driver supports device tree probe. But in case of device
tree probe, pdev->id is -1 which is also non-zero, so the logic becomes
broken when device tree probe gets supported.
The patch change the logic to check "pdev->id > 0" as the part of the
condition for identifying fec1.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/net/ethernet/freescale/fec.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index 9c1d059..2bbe6a5 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -996,7 +996,7 @@ static int fec_enet_mii_init(struct platform_device *pdev)
* mdio interface in board design, and need to be configured by
* fec0 mii_bus.
*/
- if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) {
+ if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id > 0) {
/* fec1 uses fec0 mii_bus */
fep->mii_bus = fec0_mii_bus;
return 0;
--
1.7.4.1
^ permalink raw reply related
* [PATCH v3 3/3] net/fec: add imx6q enet support
From: Shawn Guo @ 2011-09-21 16:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316621270-27805-1-git-send-email-shawn.guo@linaro.org>
The imx6q enet is a derivative of imx28 enet controller. It fixed
the frame endian issue found on imx28, and added 1 Gbps support.
It also fixes a typo on vendor name in Kconfig.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/net/ethernet/freescale/Kconfig | 9 ++---
drivers/net/ethernet/freescale/fec.c | 61 +++++++++++++++++++++++++------
2 files changed, 53 insertions(+), 17 deletions(-)
diff --git a/drivers/net/ethernet/freescale/Kconfig b/drivers/net/ethernet/freescale/Kconfig
index 4dbe41f..1cf6716 100644
--- a/drivers/net/ethernet/freescale/Kconfig
+++ b/drivers/net/ethernet/freescale/Kconfig
@@ -7,7 +7,7 @@ config NET_VENDOR_FREESCALE
default y
depends on FSL_SOC || QUICC_ENGINE || CPM1 || CPM2 || PPC_MPC512x || \
M523x || M527x || M5272 || M528x || M520x || M532x || \
- IMX_HAVE_PLATFORM_FEC || MXS_HAVE_PLATFORM_FEC || \
+ ARCH_MXC || ARCH_MXS || \
(PPC_MPC52xx && PPC_BESTCOMM)
---help---
If you have a network (Ethernet) card belonging to this class, say Y
@@ -16,16 +16,15 @@ config NET_VENDOR_FREESCALE
Note that the answer to this question doesn't directly affect the
kernel: saying N will just cause the configurator to skip all
- the questions about IBM devices. If you say Y, you will be asked for
- your specific card in the following questions.
+ the questions about Freescale devices. If you say Y, you will be
+ asked for your specific card in the following questions.
if NET_VENDOR_FREESCALE
config FEC
bool "FEC ethernet controller (of ColdFire and some i.MX CPUs)"
depends on (M523x || M527x || M5272 || M528x || M520x || M532x || \
- IMX_HAVE_PLATFORM_FEC || MXS_HAVE_PLATFORM_FEC)
- default IMX_HAVE_PLATFORM_FEC || MXS_HAVE_PLATFORM_FEC if ARM
+ ARCH_MXC || ARCH_MXS)
select PHYLIB
---help---
Say Y here if you want to use the built-in 10/100 Fast ethernet
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index 2bbe6a5..3101d05 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -18,7 +18,7 @@
* Bug fixes and cleanup by Philippe De Muyter (phdm at macqel.be)
* Copyright (c) 2004-2006 Macq Electronique SA.
*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
*/
#include <linux/module.h>
@@ -72,6 +72,10 @@
#define FEC_QUIRK_SWAP_FRAME (1 << 1)
/* Controller uses gasket */
#define FEC_QUIRK_USE_GASKET (1 << 2)
+/* Controller has GBIT support */
+#define FEC_QUIRK_HAS_GBIT (1 << 3)
+/* Controller's phy_speed bit field need to minus one */
+#define FEC_QUIRK_PHY_SPEED_MINUS_ONE (1 << 4)
static struct platform_device_id fec_devtype[] = {
{
@@ -88,6 +92,10 @@ static struct platform_device_id fec_devtype[] = {
.name = "imx28-fec",
.driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
}, {
+ .name = "imx6q-fec",
+ .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
+ FEC_QUIRK_PHY_SPEED_MINUS_ONE,
+ }, {
/* sentinel */
}
};
@@ -97,12 +105,14 @@ enum imx_fec_type {
IMX25_FEC = 1, /* runs on i.mx25/50/53 */
IMX27_FEC, /* runs on i.mx27/35/51 */
IMX28_FEC,
+ IMX6Q_FEC,
};
static const struct of_device_id fec_dt_ids[] = {
{ .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
{ .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
{ .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
+ { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fec_dt_ids);
@@ -373,6 +383,7 @@ fec_restart(struct net_device *ndev, int duplex)
int i;
u32 temp_mac[2];
u32 rcntl = OPT_FRAME_SIZE | 0x04;
+ u32 ecntl = 0x2; /* ETHEREN */
/* Whack a reset. We should wait for this. */
writel(1, fep->hwp + FEC_ECNTRL);
@@ -442,18 +453,23 @@ fec_restart(struct net_device *ndev, int duplex)
/* Enable flow control and length check */
rcntl |= 0x40000000 | 0x00000020;
- /* MII or RMII */
- if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
+ /* RGMII, RMII or MII */
+ if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
+ rcntl |= (1 << 6);
+ else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
rcntl |= (1 << 8);
else
rcntl &= ~(1 << 8);
- /* 10M or 100M */
- if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
- rcntl &= ~(1 << 9);
- else
- rcntl |= (1 << 9);
-
+ /* 1G, 100M or 10M */
+ if (fep->phy_dev) {
+ if (fep->phy_dev->speed == SPEED_1000)
+ ecntl |= (1 << 5);
+ else if (fep->phy_dev->speed == SPEED_100)
+ rcntl &= ~(1 << 9);
+ else
+ rcntl |= (1 << 9);
+ }
} else {
#ifdef FEC_MIIGSK_ENR
if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
@@ -478,8 +494,15 @@ fec_restart(struct net_device *ndev, int duplex)
}
writel(rcntl, fep->hwp + FEC_R_CNTRL);
+ if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
+ /* enable ENET endian swap */
+ ecntl |= (1 << 8);
+ /* enable ENET store and forward mode */
+ writel(1 << 8, fep->hwp + FEC_X_WMRK);
+ }
+
/* And last, enable the transmit and receive processing */
- writel(2, fep->hwp + FEC_ECNTRL);
+ writel(ecntl, fep->hwp + FEC_ECNTRL);
writel(0, fep->hwp + FEC_R_DES_ACTIVE);
/* Enable interrupts we wish to service */
@@ -490,6 +513,8 @@ static void
fec_stop(struct net_device *ndev)
{
struct fec_enet_private *fep = netdev_priv(ndev);
+ const struct platform_device_id *id_entry =
+ platform_get_device_id(fep->pdev);
/* We cannot expect a graceful transmit stop without link !!! */
if (fep->link) {
@@ -504,6 +529,10 @@ fec_stop(struct net_device *ndev)
udelay(10);
writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
+
+ /* We have to keep ENET enabled to have MII interrupt stay working */
+ if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
+ writel(2, fep->hwp + FEC_ECNTRL);
}
@@ -918,6 +947,8 @@ static int fec_enet_mdio_reset(struct mii_bus *bus)
static int fec_enet_mii_probe(struct net_device *ndev)
{
struct fec_enet_private *fep = netdev_priv(ndev);
+ const struct platform_device_id *id_entry =
+ platform_get_device_id(fep->pdev);
struct phy_device *phy_dev = NULL;
char mdio_bus_id[MII_BUS_ID_SIZE];
char phy_name[MII_BUS_ID_SIZE + 3];
@@ -949,14 +980,18 @@ static int fec_enet_mii_probe(struct net_device *ndev)
snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
- PHY_INTERFACE_MODE_MII);
+ fep->phy_interface);
if (IS_ERR(phy_dev)) {
printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
return PTR_ERR(phy_dev);
}
/* mask with MAC supported features */
- phy_dev->supported &= PHY_BASIC_FEATURES;
+ if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT)
+ phy_dev->supported &= PHY_GBIT_FEATURES;
+ else
+ phy_dev->supported &= PHY_BASIC_FEATURES;
+
phy_dev->advertising = phy_dev->supported;
fep->phy_dev = phy_dev;
@@ -1008,6 +1043,8 @@ static int fec_enet_mii_init(struct platform_device *pdev)
* Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
*/
fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
+ if (id_entry->driver_data & FEC_QUIRK_PHY_SPEED_MINUS_ONE)
+ fep->phy_speed--;
writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
fep->mii_bus = mdiobus_alloc();
--
1.7.4.1
^ permalink raw reply related
* [PATCH 00/10] hwspinlock-next
From: Ohad Ben-Cohen @ 2011-09-21 16:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK=WgbZ_1M-p+BtJnhw_uvaCnLaFRPA_tyv-rSGWMv2GQcB5Cw@mail.gmail.com>
On Wed, Sep 21, 2011 at 6:56 PM, Ohad Ben-Cohen <ohad@wizery.com> wrote:
> On Wed, Sep 21, 2011 at 6:28 PM, Tony Lindgren <tony@atomide.com> wrote:
>> Ohad can you please try this first? Just please make sure your patches are
>> first in next tree before sending in the pull request.
>
> Sure thing.
>
> Stephen, I'll send you the location of my tree in a few.
Just before I do, Tony can I please have your Ack for the mach-omap2
part of this patch-set:
arch/arm/mach-omap2/hwspinlock.c | 8 +-
Thanks,
Ohad.
^ permalink raw reply
* [PATCH 04/10] hwspinlock/core/omap: fix id issues on multiple hwspinlock devices
From: Tony Lindgren @ 2011-09-21 16:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1315846025-11453-5-git-send-email-ohad@wizery.com>
* Ohad Ben-Cohen <ohad@wizery.com> [110912 09:14]:
> hwspinlock devices provide system-wide hardware locks that are used
> by remote processors that have no other way to achieve synchronization.
>
> For that to work, each physical lock must have a system-wide unique id
> number that all processors are familiar with, otherwise they can't
> possibly assume they're using the same hardware lock.
>
> Usually SoCs have a single hwspinlock device, which provides several
> hwspinlocks, and in this case, they can be trivially numbered 0 to
> (num-of-locks - 1).
>
> In case boards have several hwspinlocks devices (each of which
> providing numerous hardware spinlocks) a different base id should be
> used for each hwspinlock device (they can't all use 0 as a starting
> id!).
>
> While this is certainly not common, it's just plain wrong to just
> silently use 0 as a base id whenever the hwspinlock driver is probed.
>
> This patch provides a hwspinlock_pdata structure, that boards can use
> to set a different base id for each of the hwspinlock devices they may
> have, and demonstrates how to use it with the omap hwspinlock driver
> (ultimately it will be DT which will supply this base_id information).
>
> While we're at it, make sure the hwspinlock core prints an explicit
> error message in case an hwspinlock is registered with an id number
> that already exists; this will help users catch such base id issues.
>
> Reported-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
Acked-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply
* [PATCH] ARM: tegra: Remove redundant change to the CPSR in headsmp.S
From: Colin Cross @ 2011-09-21 16:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110914091531.GA2104@arm.com>
On Wed, Sep 14, 2011 at 2:15 AM, Dave Martin <dave.martin@linaro.org> wrote:
<snip>
> With regard to Thumb-2 kernels, what code is responsible for
> performing the jump to tegra_secondary_startup?
arch/arm/mach-tegra/platsmp.c puts the physical address of
tegra_secondary_startup into the reset vector, and then brings the cpu
out of reset. As far as I know, it is always in ARM mode, but it is
possible that it comes through ROM code that ends with a bx, allowing
it to be entered in Thumb mode.
> If the jump is done by making an exception return from some firmware,
> you may find you hit tegra_secondary_starup in ARM state, and
> everything will go horribly wrong...
>
> It could be worth making the secondary kernel entry point ARM code
> unconditionally (just as is now done for the primary kernel entry
> point).
That seems safest.
> Cheers
> ---Dave
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply
* [PATCH 00/10] hwspinlock-next
From: Tony Lindgren @ 2011-09-21 16:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK=WgbZw=q1HkU2U6iuzjSW==za5saFXmnf0yaYoHWkJfduZVA@mail.gmail.com>
* Ohad Ben-Cohen <ohad@wizery.com> [110921 08:34]:
> On Wed, Sep 21, 2011 at 6:56 PM, Ohad Ben-Cohen <ohad@wizery.com> wrote:
> > On Wed, Sep 21, 2011 at 6:28 PM, Tony Lindgren <tony@atomide.com> wrote:
> >> Ohad can you please try this first? Just please make sure your patches are
> >> first in next tree before sending in the pull request.
> >
> > Sure thing.
> >
> > Stephen, I'll send you the location of my tree in a few.
>
> Just before I do, Tony can I please have your Ack for the mach-omap2
> part of this patch-set:
>
> arch/arm/mach-omap2/hwspinlock.c | 8 +-
OK acked the related patch.
Tony
^ permalink raw reply
* [PATCH 00/10] hwspinlock-next
From: Ohad Ben-Cohen @ 2011-09-21 16:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110921161424.GG2937@atomide.com>
On Wed, Sep 21, 2011 at 7:14 PM, Tony Lindgren <tony@atomide.com> wrote:
> OK acked the related patch.
Thanks!
^ permalink raw reply
* [PATCH] ARM: vexpress: initial device tree support
From: Dave Martin @ 2011-09-21 16:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316620877.4611.647.camel@hornet.cambridge.arm.com>
On Wed, Sep 21, 2011 at 5:01 PM, Pawel Moll <pawel.moll@arm.com> wrote:
> On Wed, 2011-09-21 at 15:57 +0100, Grant Likely wrote:
>> On Wed, Sep 21, 2011 at 7:24 AM, Rob Herring <robherring2@gmail.com> wrote:
>> > On 09/21/2011 04:19 AM, Dave Martin wrote:
>> >> ? ? ? * arm,amba-bus -- widely used by other boards and patchsets, but
>> >> ? ? ? ? seems not to be documented.
>> >>
>> >
>> > This should be dropped. There's not really any bus component to an amba
>> > bus. All the probing info is within the primecell peripherals.
>>
>> No, if it is an AMBA bus, then it is entirely appropriate to declare
>> it as an amba bus, but to also be compatible with "simple-bus". ?In
>> fact, it would be better to use a compatible string that specifies the
>> specific implementation of AMBA bus since there are several versions
>> of the spec.
>
> Dave asked me about details of the VE implementation. It's
> sort-of-complicated... ;-)
>
> 1. Core talks to Static Memory Controller via AMBA (AXI)
>
> ? SOC { core --AXI--> SMC }
>
> 2. SMC generates transaction on Static Memory Bus talking to the IO FPGA
>
> ? tile/motherboard connector { SMC --SMB--> IOFPGA }
>
> 3. Now, depending on the device being accessed:
>
> a) Transactions accessing SMSC9118, ISP1761, NOR Flash and PSRAM are
> routed directly to the devices
>
> ? IOFPGA { SMB --> SMSC9118 et al. }
>
> b) The rest of the traffic is converted back to AMBA (AHB/APB)
> transactions and sent to the devices connected to internal AMBA matrix.
>
> ? IOFPGA { SMB --> AHB/APB bus master --AHB/APB--> PL180 }
>
> I don't believe, though, that the DTS must reflect such level of
> details. That's why I think that:
>
> + ? ? ? motherboard {
> + ? ? ? ? ? ? ? compatible = "simple-bus";
>
> and
>
> + ? ? ? ? ? ? ? peripherals at 7,00000000 {
> + ? ? ? ? ? ? ? ? ? ? ? compatible = "arm,amba-bus", "simple-bus";
>
> is the best description of the reality :-)
I wonder whether an OS will ever need to know this detail.
Am I right in understanding that these buses are just interconnect
logic, with no OS-visible control/configuration interface?
Cheers
---Dave
^ permalink raw reply
* [PATCH 00/10] hwspinlock-next
From: Arnd Bergmann @ 2011-09-21 16:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdbqVuFEgntw=bUYka5NuvpbPhjB8L0cD4CTmsjwoZBDSA@mail.gmail.com>
On Wednesday 21 September 2011, Linus Walleij wrote:
> On Wed, Sep 21, 2011 at 4:12 PM, Arnd Bergmann <arnd@arndb.de> wrote:
>
> > My feeling is that it would be best for Ohad to send these directly
> > to Linus, since it's basically a standalone subsystem and he's listed
> > as the maintainer (well, after this series at least).
>
> I agree. That's the path of least resistance and trouble.
>
> If/when ARM-specific driver subsystems need their own zuper-maintainer
> we can deal with it, can't we? There aren't many of them yet.
Definitely, I think that's the ideal case. I would very much like to
see independent subsystem maintainers for the device drivers that are
currently buried in per-architecture or per-platform directories.
Among the ones that we should be moving out of there (or have already)
are cpufreq, gpio, irqchip, pinmux, clock, dmaengine, timer, and there
are probably some more. Since none of these are strictly ARM specific,
my feeling is that they should not be part of the arm or arm-soc tree
in the future but have their own trees.
Arnd
^ permalink raw reply
* [PATCH] ARM: OMAP: voltage layer present, even when CONFIG_PM=n
From: Kevin Hilman @ 2011-09-21 16:24 UTC (permalink / raw)
To: linux-arm-kernel
Even when CONFIG_PM=n, we try to scale the boot voltage to a sane,
known value using OPP table to find matching voltage based on boot
frequency. This should be done, even when CONFIG_PM=n to avoid
mis-configured bootloaders and/or boot voltage assumptions made by
boot loaders.
Also fixes various compile problems due to depenencies between voltage
domain and powerdomain code (also present when CONFIG_PM=n).
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kevin Hilman <khilman@ti.com>
---
Compile tested with CONFIG_PM=n
Applies to arm-soc/next/voltage
arch/arm/mach-omap2/Makefile | 2 --
arch/arm/mach-omap2/voltage.h | 14 --------------
2 files changed, 0 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8bd389d..5129785 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -89,7 +89,6 @@ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
vp44xx_data.o
# OMAP voltage domains
-ifeq ($(CONFIG_PM),y)
voltagedomain-common := voltage.o vc.o vp.o
obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) \
voltagedomains2xxx_data.o
@@ -97,7 +96,6 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \
voltagedomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) \
voltagedomains44xx_data.o
-endif
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 4c09809..16a1b09 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -148,25 +148,11 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
struct omap_volt_data **volt_data);
struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
unsigned long volt);
-#ifdef CONFIG_PM
int omap_voltage_register_pmic(struct voltagedomain *voltdm,
struct omap_voltdm_pmic *pmic);
void omap_change_voltscale_method(struct voltagedomain *voltdm,
int voltscale_method);
int omap_voltage_late_init(void);
-#else
-static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm,
- struct omap_voltdm_pmic *pmic)
-{
- return -EINVAL;
-}
-static inline void omap_change_voltscale_method(struct voltagedomain *voltdm,
- int voltscale_method) {}
-static inline int omap_voltage_late_init(void)
-{
- return -EINVAL;
-}
-#endif
extern void omap2xxx_voltagedomains_init(void);
extern void omap3xxx_voltagedomains_init(void);
--
1.7.6
^ permalink raw reply related
* [PATCH] gpio/mxc: add chained_irq_enter/exit() to mx3_gpio_irq_handler()
From: Grant Likely @ 2011-09-21 16:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316611444-14126-1-git-send-email-shawn.guo@linaro.org>
On Wed, Sep 21, 2011 at 09:24:04PM +0800, Shawn Guo wrote:
> The mx3_gpio_irq_handler() is also called on imx6q which has GIC as
> the primary interrupt controller. As GIC implements the fasteoi flow
> control, we need to add chained_irq_enter/exit() to
> mx3_gpio_irq_handler() for signaling EOI, otherwise system will hang
> whenever there is a gpio irq triggered.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> This is the second post of '[PATCH] gpio/mxc: make it work with imx6q'
> to adopt the point given by Jamie.
Nit: don't forget to include the patch version in the subject line, and I like to see the revision history appear before the s-o-b lines so that it makes it into the final commit.
I'll merge this one, thanks.
g.
>
> drivers/gpio/gpio-mxc.c | 6 ++++++
> 1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
> index 4340aca..82f7b65 100644
> --- a/drivers/gpio/gpio-mxc.c
> +++ b/drivers/gpio/gpio-mxc.c
> @@ -30,6 +30,7 @@
> #include <linux/of.h>
> #include <linux/of_device.h>
> #include <asm-generic/bug.h>
> +#include <asm/mach/irq.h>
>
> enum mxc_gpio_hwtype {
> IMX1_GPIO, /* runs on i.mx1 */
> @@ -232,10 +233,15 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
> {
> u32 irq_stat;
> struct mxc_gpio_port *port = irq_get_handler_data(irq);
> + struct irq_chip *chip = irq_get_chip(irq);
> +
> + chained_irq_enter(chip, desc);
>
> irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
>
> mxc_gpio_irq_handler(port, irq_stat);
> +
> + chained_irq_exit(chip, desc);
> }
>
> /* MX2 has one interrupt *for all* gpio ports */
> --
> 1.7.4.1
>
>
^ permalink raw reply
* [PATCH 1/3] fixup! mm: alloc_contig_freed_pages() added
From: Michal Nazarewicz @ 2011-09-21 16:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316619959.16137.308.camel@nimitz>
From: Michal Nazarewicz <mina86@mina86.com>
Signed-off-by: Michal Nazarewicz <mina86@mina86.com>
---
include/asm-generic/memory_model.h | 17 ++++++++++++++
include/linux/page-isolation.h | 4 ++-
mm/page_alloc.c | 43 +++++++++++++++++++++++++++--------
3 files changed, 53 insertions(+), 11 deletions(-)
> On Wed, 2011-09-21 at 17:19 +0200, Michal Nazarewicz wrote:
>> I wanted to avoid calling pfn_to_page() each time as it seem fairly
>> expensive in sparsemem and disctontig modes. At the same time, the
>> macro trickery is so that users of sparsemem-vmemmap and flatmem won't
>> have to pay the price.
On Wed, 21 Sep 2011 17:45:59 +0200, Dave Hansen <dave@linux.vnet.ibm.com> wrote:
> Personally, I'd say the (incredibly minuscule) runtime cost is worth the
> cost of making folks' eyes bleed when they see those macros. I think
> there are some nicer ways to do it.
Yeah. I wasn't amazed by them either.
> Is there a reason you can't logically do?
> page = pfn_to_page(pfn);
> for (;;) {
> if (pfn_to_section_nr(pfn) == pfn_to_section_nr(pfn+1))
> page++;
> else
> page = pfn_to_page(pfn+1);
> }
Done. Thanks for the suggestions!
>> +#define __contig_next_page(page, pageblock_left, pfn, increment) \
>> + (likely((pageblock_left) -= (increment)) ? (page) + (increment) \
>> + : (((pageblock_left) = pageblock_nr_pages), pfn_to_page(pfn)))
>> +
>> +#define __contig_first_page(pageblock_left, pfn) ( \
>> + ((pageblock_left) = pageblock_nr_pages - \
>> + ((pfn) & (pageblock_nr_pages - 1))), \
>> + pfn_to_page(pfn))
>> +
>> +#endif
> For the love of Pete, please make those in to functions if you're going
> to keep them.
That was tricky because they modify pageblock_left. Not relevant now
anyways though.
diff --git a/include/asm-generic/memory_model.h b/include/asm-generic/memory_model.h
index fb2d63f..900da88 100644
--- a/include/asm-generic/memory_model.h
+++ b/include/asm-generic/memory_model.h
@@ -69,6 +69,23 @@
})
#endif /* CONFIG_FLATMEM/DISCONTIGMEM/SPARSEMEM */
+#if defined(CONFIG_SPARSEMEM) && !defined(CONFIG_SPARSEMEM_VMEMMAP)
+
+/*
+ * Both PFNs must be from the same zone! If this function returns
+ * true, pfn_to_page(pfn1) + (pfn2 - pfn1) == pfn_to_page(pfn2).
+ */
+static inline bool zone_pfn_same_memmap(unsigned long pfn1, unsigned long pfn2)
+{
+ return pfn_to_section_nr(pfn1) == pfn_to_section_nr(pfn2);
+}
+
+#else
+
+#define zone_pfn_same_memmap(pfn1, pfn2) (true)
+
+#endif
+
#define page_to_pfn __page_to_pfn
#define pfn_to_page __pfn_to_page
diff --git a/include/linux/page-isolation.h b/include/linux/page-isolation.h
index b2a81fd..003c52f 100644
--- a/include/linux/page-isolation.h
+++ b/include/linux/page-isolation.h
@@ -46,11 +46,13 @@ static inline void unset_migratetype_isolate(struct page *page)
{
__unset_migratetype_isolate(page, MIGRATE_MOVABLE);
}
+
+/* The below functions must be run on a range from a single zone. */
extern unsigned long alloc_contig_freed_pages(unsigned long start,
unsigned long end, gfp_t flag);
extern int alloc_contig_range(unsigned long start, unsigned long end,
gfp_t flags, unsigned migratetype);
-extern void free_contig_pages(struct page *page, int nr_pages);
+extern void free_contig_pages(unsigned long pfn, unsigned nr_pages);
/*
* For migration.
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 46e78d4..bc200a9 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -5725,31 +5725,46 @@ unsigned long alloc_contig_freed_pages(unsigned long start, unsigned long end,
int order;
VM_BUG_ON(!pfn_valid(start));
- zone = page_zone(pfn_to_page(start));
+ page = pfn_to_page(start);
+ zone = page_zone(page);
spin_lock_irq(&zone->lock);
- page = pfn_to_page(pfn);
for (;;) {
- VM_BUG_ON(page_count(page) || !PageBuddy(page));
+ VM_BUG_ON(!page_count(page) || !PageBuddy(page) ||
+ page_zone(page) != zone);
+
list_del(&page->lru);
order = page_order(page);
+ count = 1UL << order;
zone->free_area[order].nr_free--;
rmv_page_order(page);
- __mod_zone_page_state(zone, NR_FREE_PAGES, -(1UL << order));
- pfn += 1 << order;
+ __mod_zone_page_state(zone, NR_FREE_PAGES, -(long)count);
+
+ pfn += count;
if (pfn >= end)
break;
VM_BUG_ON(!pfn_valid(pfn));
- page += 1 << order;
+
+ if (zone_pfn_same_memmap(pfn - count, pfn))
+ page += count;
+ else
+ page = pfn_to_page(pfn);
}
spin_unlock_irq(&zone->lock);
/* After this, pages in the range can be freed one be one */
- page = pfn_to_page(start);
- for (count = pfn - start; count; --count, ++page)
+ count = pfn - start;
+ pfn = start;
+ for (page = pfn_to_page(pfn); count; --count) {
prep_new_page(page, 0, flag);
+ ++pfn;
+ if (likely(zone_pfn_same_memmap(pfn - 1, pfn)))
+ ++page;
+ else
+ page = pfn_to_page(pfn);
+ }
return pfn;
}
@@ -5903,10 +5918,18 @@ done:
return ret;
}
-void free_contig_pages(struct page *page, int nr_pages)
+void free_contig_pages(unsigned long pfn, unsigned nr_pages)
{
- for (; nr_pages; --nr_pages, ++page)
+ struct page *page = pfn_to_page(pfn);
+
+ while (nr_pages--) {
__free_page(page);
+ ++pfn;
+ if (likely(zone_pfn_same_memmap(pfn - 1, pfn)))
+ ++page;
+ else
+ page = pfn_to_page(pfn);
+ }
}
#ifdef CONFIG_MEMORY_HOTREMOVE
--
1.7.3.1
^ permalink raw reply related
* [PATCH] ARM: vexpress: initial device tree support
From: Pawel Moll @ 2011-09-21 16:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CA+wbFdcOSC6YfsmLndM9CCg2WC9GbQqHmgzk3r8JKs71Bsn8Xg@mail.gmail.com>
> > Dave asked me about details of the VE implementation. It's
> > sort-of-complicated... ;-)
> >
> > 1. Core talks to Static Memory Controller via AMBA (AXI)
> >
> > SOC { core --AXI--> SMC }
> >
> > 2. SMC generates transaction on Static Memory Bus talking to the IO FPGA
> >
> > tile/motherboard connector { SMC --SMB--> IOFPGA }
> >
> > 3. Now, depending on the device being accessed:
> >
> > a) Transactions accessing SMSC9118, ISP1761, NOR Flash and PSRAM are
> > routed directly to the devices
> >
> > IOFPGA { SMB --> SMSC9118 et al. }
> >
> > b) The rest of the traffic is converted back to AMBA (AHB/APB)
> > transactions and sent to the devices connected to internal AMBA matrix.
> >
> > IOFPGA { SMB --> AHB/APB bus master --AHB/APB--> PL180 }
> >
> > I don't believe, though, that the DTS must reflect such level of
> > details. That's why I think that:
> >
> > + motherboard {
> > + compatible = "simple-bus";
> >
> > and
> >
> > + peripherals at 7,00000000 {
> > + compatible = "arm,amba-bus", "simple-bus";
> >
> > is the best description of the reality :-)
>
> I wonder whether an OS will ever need to know this detail.
Which one of the details you mean? Exact architecture describing what I
said above? I don't think so.
The compatible = "arm,amba-bus" for CS7? Probably not, but I think it's
good to have it there as it answers the question "so how can AMBA device
like PL180 be connected to a static memory bus?!?".
> Am I right in understanding that these buses are just interconnect
> logic, with no OS-visible control/configuration interface?
Definitely nothing publicly specified :-)
Cheers!
Pawe?
^ permalink raw reply
* [PATCH 1/3] fixup! mm: alloc_contig_freed_pages() added
From: Dave Hansen @ 2011-09-21 16:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f57b57f83bc5980e3db7d9d42f91c7e1765b4766.1316622205.git.mina86@mina86.com>
On Wed, 2011-09-21 at 18:26 +0200, Michal Nazarewicz wrote:
> - page += 1 << order;
> +
> + if (zone_pfn_same_memmap(pfn - count, pfn))
> + page += count;
> + else
> + page = pfn_to_page(pfn);
> }
That all looks sane to me and should fix the bug I brought up.
-- Dave
^ permalink raw reply
* [PATCH] ARM: vexpress: initial device tree support
From: Rob Herring @ 2011-09-21 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACxGe6sTYYXbpXvPb4C+y4JX0eRxLvwjbFycXA8Mjc-XWS1QUA@mail.gmail.com>
On 09/21/2011 09:57 AM, Grant Likely wrote:
> On Wed, Sep 21, 2011 at 7:24 AM, Rob Herring <robherring2@gmail.com> wrote:
>> On 09/21/2011 04:19 AM, Dave Martin wrote:
>>> * arm,amba-bus -- widely used by other boards and patchsets, but
>>> seems not to be documented.
>>>
>>
>> This should be dropped. There's not really any bus component to an amba
>> bus. All the probing info is within the primecell peripherals.
>
> No, if it is an AMBA bus, then it is entirely appropriate to declare
> it as an amba bus, but to also be compatible with "simple-bus". In
> fact, it would be better to use a compatible string that specifies the
> specific implementation of AMBA bus since there are several versions
> of the spec.
And type of AMBA bus as the spec includes AXI, AHB, and APB. None of
which have any sort of programmability or software view.
If this is required, then the policy should be simple-bus should never
be allowed alone as every bus has some underlying type. Seems like
overkill for buses like this.
Rob
^ permalink raw reply
* [GIT PULL] omap cleanup part1 for v3.2 merge window
From: Kevin Hilman @ 2011-09-21 16:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2241590.uiCS2D9jjt@wuerfel>
Hi Arnd,
Arnd Bergmann <arnd@arndb.de> writes:
> On Tuesday 20 September 2011 23:46:11 Arnd Bergmann wrote:
>
>> It seems that you replace the #ifdef in the board-flash.c file
>> with a similar #ifdef in the header that replaces this with an
>> empty inline function when the object is not built.
>
> Found another similar problem over night, presumably in the voltage series:
>
Found. Patch below.
If this one is OK, I'll push to my for_3.2/voltage-cleanup branch (which
is already pulled into arm-soc/next/voltage) so just re-pulling will
pick up the fix.
Kevin
^ permalink raw reply
* [PATCH 0/19] removal of mach/vmalloc.h and generic optimizations
From: Nicolas Pitre @ 2011-09-21 17:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1109202047400.12663@xanadu.home>
On Tue, 20 Sep 2011, Nicolas Pitre wrote:
> On Sun, 18 Sep 2011, Arnd Bergmann wrote:
>
> > No, I couldn't find anything in the code or the changelog why this was
> > done.
>
> I found that drivers/video/sh_mobile_lcdcfb.c appears to be a heavy user
> of dma_alloc_coherent():
>
> buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
> &ch->dma_handle, GFP_KERNEL);
>
> So for this particular hypothetical case: 1920 * 1080 * 2 * 32 / 8 = 16MB
>
> We are far from the 158MB figure. Furthermore, the highest allowed
> amount is 14MB according to the available documentation, and none of the
> other ARM targets use more than that either.
For the record, here's the patch I'm including in my series:
From: Nicolas Pitre <nicolas.pitre@linaro.org>
Date: Mon, 19 Sep 2011 00:28:45 -0400
Subject: [PATCH] ARM: move VMALLOC_END down temporarily for shmobile
THIS IS A TEMPORARY HACK. The purpose of this is _only_ to avoid a
regression on an existing machine while a better fix is implemented.
On shmobile the consistent DMA memory area was set to 158MB in commit
28f0721a79 with no explanation. The documented size for this area should
vary between 2MB and 14MB, and none of the other ARM targets exceed that.
The included #warning is therefore meant to be noisy on purpose to get
shmobile maintainers attention and this commit reverted once this
consistent DMA size conflict is resolved.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Magnus Damm <damm@opensource.se>
Cc: Paul Mundt <lethal@linux-sh.org>
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 950dee3ce2..35eb517a21 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -35,6 +35,13 @@
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END 0xff000000UL
+/* This is a temporary hack until shmobile's DMA area size is sorted out */
+#ifdef CONFIG_ARCH_SHMOBILE
+#warning "SH-Mobile's consistent DMA size conflicts with VMALLOC_END by 144MB"
+#undef VMALLOC_END
+#define VMALLOC_END 0xF6000000UL
+#endif
+
/*
* Hardware-wise, we have a two level page table structure, where the first
* level has 4096 entries, and the second level has 256 entries. Each entry
Nicolas
^ permalink raw reply related
* [PATCH] ARM: vexpress: initial device tree support
From: Dave Martin @ 2011-09-21 17:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E7A12E2.9040107@gmail.com>
On Wed, Sep 21, 2011 at 11:37:54AM -0500, Rob Herring wrote:
> On 09/21/2011 09:57 AM, Grant Likely wrote:
> > On Wed, Sep 21, 2011 at 7:24 AM, Rob Herring <robherring2@gmail.com> wrote:
> >> On 09/21/2011 04:19 AM, Dave Martin wrote:
> >>> * arm,amba-bus -- widely used by other boards and patchsets, but
> >>> seems not to be documented.
> >>>
> >>
> >> This should be dropped. There's not really any bus component to an amba
> >> bus. All the probing info is within the primecell peripherals.
> >
> > No, if it is an AMBA bus, then it is entirely appropriate to declare
> > it as an amba bus, but to also be compatible with "simple-bus". In
> > fact, it would be better to use a compatible string that specifies the
> > specific implementation of AMBA bus since there are several versions
> > of the spec.
>
> And type of AMBA bus as the spec includes AXI, AHB, and APB. None of
> which have any sort of programmability or software view.
>
> If this is required, then the policy should be simple-bus should never
> be allowed alone as every bus has some underlying type. Seems like
> overkill for buses like this.
The key question is _where_ to draw the line between generic and specific.
By definition, the DT can never be a comprehensive description of the
hardware -- rather a good DT is a description of those details of the hardware
which could relevant to any hypothetical OS.
The flipside is that details which were thought to be irrelevant at
design/implementation time can turn out to be relevant in practice, due
to errata and implementation issues etc. So taking the description slightly
beyond what the OS needs to know can still have some merit.
I still don't know how to say where the line should be drawn in this particular
case though.
Cheers
---Dave
^ permalink raw reply
* [PATCH 3/3] ARM: gic: add OF based initialization
From: Cousson, Benoit @ 2011-09-21 17:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316550244-3655-4-git-send-email-robherring2@gmail.com>
Hi Rob,
I'm testing that series with OMAP4 but have some issues for the moment :-(
[ 0.000000] WARNING: at kernel/irq/irqdomain.c:34 gic_of_init+0x10c/0x180()
[ 0.000000] error: irq_desc already assigned to a domain
[ 0.000000] Modules linked in:
[ 0.000000] [<c001b284>] (unwind_backtrace+0x0/0xf0) from [<c0051c34>] (warn_slowpath_common+0x4c/0x64)
[ 0.000000] [<c0051c34>] (warn_slowpath_common+0x4c/0x64) from [<c0051ce0>] (warn_slowpath_fmt+0x30/0x40)
[ 0.000000] [<c0051ce0>] (warn_slowpath_fmt+0x30/0x40) from [<c05f6874>] (gic_of_init+0x10c/0x180)
[ 0.000000] [<c05f6874>] (gic_of_init+0x10c/0x180) from [<c05fa2e0>] (omap_gic_of_init+0x8/0x28)
[ 0.000000] [<c05fa2e0>] (omap_gic_of_init+0x8/0x28) from [<c0616b44>] (of_irq_init+0x148/0x28c)
[ 0.000000] [<c0616b44>] (of_irq_init+0x148/0x28c) from [<c05f3074>] (init_IRQ+0x14/0x1c)
[ 0.000000] [<c05f3074>] (init_IRQ+0x14/0x1c) from [<c05f0650>] (start_kernel+0x184/0x2fc)
[ 0.000000] [<c05f0650>] (start_kernel+0x184/0x2fc) from [<80008040>] (0x80008040)
I'm not super familiar with all the irq stuff but I'm wondering if there is not something wrong with the test that print that message:
void irq_domain_add(struct irq_domain *domain)
{
struct irq_data *d;
int hwirq;
/*
* This assumes that the irq_domain owner has already allocated
* the irq_descs. This block will be removed when support for dynamic
* allocation of irq_descs is added to irq_domain.
*/
for (hwirq = 0; hwirq < domain->nr_irq; hwirq++) {
d = irq_get_irq_data(irq_domain_to_irq(domain, hwirq));
if (d || d->domain) {
/* things are broken; just report, don't clean up */
WARN(1, "error: irq_desc already assigned to a domain");
return;
}
[...]
Is the (d || d->domain) correct? Shouldn't it be (d && d->domain)?
But since that used to work properly, I have some doubt. Moreover the driver will not even get the proper interrupt later...
Do you have any clue?
Thanks,
Benoit
On 9/20/2011 10:24 PM, Rob Herring wrote:
> From: Rob Herring<rob.herring@calxeda.com>
>
> This adds ARM gic interrupt controller initialization using device tree
> data.
>
> The initialization function is intended to be called by of_irq_init
> function like this:
>
> const static struct of_device_id irq_match[] = {
> { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
> {}
> };
>
> static void __init init_irqs(void)
> {
> of_irq_init(irq_match);
> }
>
> Signed-off-by: Rob Herring<rob.herring@calxeda.com>
> ---
> Documentation/devicetree/bindings/arm/gic.txt | 55 +++++++++++++++
> arch/arm/common/gic.c | 89 +++++++++++++++++++++++-
> arch/arm/include/asm/hardware/gic.h | 12 ++++
> 3 files changed, 152 insertions(+), 4 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/gic.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
> new file mode 100644
> index 0000000..52916b4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/gic.txt
> @@ -0,0 +1,55 @@
> +* ARM Generic Interrupt Controller
> +
> +ARM SMP cores are often associated with a GIC, providing per processor
> +interrupts (PPI), shared processor interrupts (SPI) and software
> +generated interrupts (SGI).
> +
> +Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
> +Secondary GICs are cascaded into the upward interrupt controller and do not
> +have PPIs or SGIs.
> +
> +Main node required properties:
> +
> +- compatible : should be one of:
> + "arm,cortex-a9-gic"
> + "arm,arm11mp-gic"
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> + interrupt source. The type shall be a<u32> and the value shall be 3.
> +
> + The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
> + interrupts.
> +
> + The 2nd cell contains the interrupt number for the interrupt type.
> + SPI interrupts are in the range [0-987]. PPI interrupts are in the
> + range [0-15].
> +
> + The 3rd cell is the flags, encoded as follows:
> + bits[3:0] trigger type and level flags.
> + 1 = low-to-high edge triggered
> + 2 = high-to-low edge triggered
> + 4 = active high level-sensitive
> + 8 = active low level-sensitive
> + bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
> + the 8 possible cpus attached to the GIC. A bit set to '1' indicated
> + the interrupt is wired to that CPU. Only valid for PPI interrupts.
> +
> +- reg : Specifies base physical address(s) and size of the GIC registers. The
> + first region is the GIC distributor register base and size. The 2nd region is
> + the GIC cpu interface register base and size.
> +
> +Optional
> +- interrupts : Interrupt source of the parent interrupt controller. Only
> + present on secondary GICs.
> +
> +Example:
> +
> + intc: interrupt-controller at fff11000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells =<3>;
> + #address-cells =<1>;
> + interrupt-controller;
> + reg =<0xfff11000 0x1000>,
> + <0xfff10100 0x100>;
> + };
> +
> diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
> index 666b278..84e69a4 100644
> --- a/arch/arm/common/gic.c
> +++ b/arch/arm/common/gic.c
> @@ -28,6 +28,10 @@
> #include<linux/smp.h>
> #include<linux/cpumask.h>
> #include<linux/io.h>
> +#include<linux/of.h>
> +#include<linux/of_address.h>
> +#include<linux/of_irq.h>
> +#include<linux/irqdomain.h>
>
> #include<asm/irq.h>
> #include<asm/mach/irq.h>
> @@ -255,6 +259,15 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
> irq_set_chained_handler(irq, gic_handle_cascade_irq);
> }
>
> +static int gic_irq_count(void __iomem *dist_base)
> +{
> + int gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR)& 0x1f;
> + gic_irqs = (gic_irqs + 1) * 32;
> + if (gic_irqs> 1020)
> + gic_irqs = 1020;
> + return gic_irqs;
> +}
> +
> static void __init gic_dist_init(struct gic_chip_data *gic,
> unsigned int irq_start)
> {
> @@ -277,10 +290,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
> * Find out how many interrupts are supported.
> * The GIC only supports up to 1020 interrupt sources.
> */
> - gic_irqs = readl_relaxed(base + GIC_DIST_CTR)& 0x1f;
> - gic_irqs = (gic_irqs + 1) * 32;
> - if (gic_irqs> 1020)
> - gic_irqs = 1020;
> + gic_irqs = gic_irq_count(base);
>
> /*
> * Set all global interrupts to be level triggered, active low.
> @@ -405,3 +415,74 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
> writel_relaxed(map<< 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
> }
> #endif
> +
> +#ifdef CONFIG_OF
> +static int gic_cnt __initdata = 0;
> +
> +int gic_irq_domain_dt_translate(struct irq_domain *d,
> + struct device_node *controller,
> + const u32 *intspec, unsigned int intsize,
> + unsigned long *out_hwirq, unsigned int *out_type)
> +{
> + struct gic_chip_data *gic_data = d->priv;
> +
> + if (d->of_node != controller)
> + return -EINVAL;
> + if (intsize< 3)
> + return -EINVAL;
> +
> + *out_hwirq = intspec[1];
> + /*
> + * We've already skipped over SGIs, so PPIs need no translation.
> + * For SPIs, we need to skip over 16 PPIs on primary GICs.
> + */
> + if (!intspec[0]&& !gic_data->irq_offset)
> + *out_hwirq += 16;
> +
> + *out_type = intspec[2]& IRQ_TYPE_SENSE_MASK;
> + return 0;
> +}
> +
> +struct irq_domain_ops gic_irq_domain_ops = {
> + .dt_translate = gic_irq_domain_dt_translate,
> +};
> +
> +int __init gic_of_init(struct device_node *node, struct device_node *parent)
> +{
> + void __iomem *cpu_base;
> + void __iomem *dist_base;
> + int irq;
> + struct irq_domain *domain =&gic_data[gic_cnt].domain;
> +
> + if (WARN_ON(!node))
> + return -ENODEV;
> +
> + dist_base = of_iomap(node, 0);
> + WARN(!dist_base, "unable to map gic dist registers\n");
> +
> + cpu_base = of_iomap(node, 1);
> + WARN(!cpu_base, "unable to map gic cpu registers\n");
> +
> + domain->nr_irq = gic_irq_count(dist_base);
> + /* subtract off SGIs. Also subtract off PPIs for secondary GICs */
> + if (parent)
> + domain->nr_irq -= 32;
> + else
> + domain->nr_irq -= 16;
> +
> + domain->irq_base = irq_alloc_descs(-1, 16, domain->nr_irq, numa_node_id());
> + domain->of_node = of_node_get(node);
> + domain->ops =&gic_irq_domain_ops;
> + domain->priv =&gic_data[gic_cnt];
> + irq_domain_add(domain);
> +
> + gic_init(gic_cnt, domain->irq_base, dist_base, cpu_base);
> +
> + if (parent) {
> + irq = irq_of_parse_and_map(node, 0);
> + gic_cascade_irq(gic_cnt, irq);
> + }
> + gic_cnt++;
> + return 0;
> +}
> +#endif
> diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
> index 435d3f8..2862d0e 100644
> --- a/arch/arm/include/asm/hardware/gic.h
> +++ b/arch/arm/include/asm/hardware/gic.h
> @@ -33,10 +33,21 @@
> #define GIC_DIST_SOFTINT 0xf00
>
> #ifndef __ASSEMBLY__
> +#include<linux/irqdomain.h>
> +
> extern void __iomem *gic_cpu_base_addr;
> extern struct irq_chip gic_arch_extn;
>
> void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
> +#ifdef CONFIG_OF
> +int gic_of_init(struct device_node *node, struct device_node *parent);
> +#else
> +static inline void gic_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + return -ENODEV;
> +}
> +#endif
> void gic_secondary_init(unsigned int);
> void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
> void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
> @@ -46,6 +57,7 @@ struct gic_chip_data {
> unsigned int irq_offset;
> void __iomem *dist_base;
> void __iomem *cpu_base;
> + struct irq_domain domain;
> };
> #endif
>
^ permalink raw reply
* [PATCH 8/8] OMAP4: Fix the emif and dmm virtual mapping
From: Kevin Hilman @ 2011-09-21 17:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E7A0292.4020408@ti.com>
Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
> On Tuesday 20 September 2011 08:31 PM, Santosh Shilimkar wrote:
>> On Friday 16 September 2011 11:26 PM, Kevin Hilman wrote:
>>> Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
>>>
>
> [...]
>
>>
>>>> #define OMAP44XX_EMIF2_SIZE SZ_1M
>>>>
>>>> #define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
>>>> /* 0x4e000000 --> 0xfd300000 */
>>>> -#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
>>>> +#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + SZ_1M)
>>>
>>> and '+ OMAP44XX_EMIF2_SIZE' here.
>>>
>> Will add OMAP44XX_EMIF_SIZE since 2 EMIFs instaces are and
>> suppose to be identical.Almost missed this email in other traffic.
>
> OPPs. It was already there. Dumb of me not using it. Below
> is the update what I will do.
>
> diff --git a/arch/arm/plat-omap/include/plat/io.h
> b/arch/arm/plat-omap/include/plat/io.h
> index d72ec85..db36292 100644
> --- a/arch/arm/plat-omap/include/plat/io.h
> +++ b/arch/arm/plat-omap/include/plat/io.h
> @@ -228,13 +228,13 @@
>
> #define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
> /* 0x4d000000 --> 0xfd200000 */
> -#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
> #define OMAP44XX_EMIF2_SIZE SZ_1M
> +#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF2_SIZE)
This doesn't look right either.
This #define is for the *start* of EMIF2 virtual address space, so
assuming the start address of EMIF2 is immediatly after EMIF1, it should
be EMIF1_VIRT + EMIF1_SIZE (not EMIF2_SIZE.)
> #define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
> /* 0x4e000000 --> 0xfd300000 */
> -#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
> #define OMAP44XX_DMM_SIZE SZ_1M
> +#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_DMM_SIZE)
And here, assuming DMM range is immediately after EMIF2, this should be
EMIF2_VIRT + EMFI2_SIZE)
Kevin
^ permalink raw reply
* [PATCH v2 0/3] Add support for TI814X processor series
From: Hemant Pedanekar @ 2011-09-21 17:38 UTC (permalink / raw)
To: linux-arm-kernel
This patch set adds support for DM814x/AM387x device series having Cortex-A8
MPU.
The technical documents are available from following link:
http://focus.ti.com/docs/prod/folders/print/tms320dm8148.html
This series is referred in code as TI814X.
Since these devices share similar architecture as TI816X devices, existing
TI816X code is updated to accomodate TI814X support. The code shared across
TI816X and TI814X devices is updated with TI81XX/ti81xx prefix as applicable,
while maintaining cpu_is_ti816x() and cpu_is_ti814x() to distinguish specific
execution differences.
Changes since v1:
1) Rebased and updated after Paul's CHIP_IS removal changes
2) Removed call to omap2_init_common_devices() as per Kevin's comment
Hemant Pedanekar (3):
TI81XX: Prepare for addition of TI814X support
TI814X: Add cpu type macros and detection support
TI814X: Create board support and enable build for TI8148 EVM
arch/arm/mach-omap2/Kconfig | 11 +++-
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/board-ti8148evm.c | 51 ++++++++++++++++++++
arch/arm/mach-omap2/board-ti8168evm.c | 8 ++--
arch/arm/mach-omap2/clock.c | 2 +-
arch/arm/mach-omap2/clock.h | 2 +-
arch/arm/mach-omap2/clock3xxx_data.c | 5 ++-
arch/arm/mach-omap2/common.c | 22 ++++----
arch/arm/mach-omap2/control.h | 8 ++--
arch/arm/mach-omap2/id.c | 30 ++++++++++--
arch/arm/mach-omap2/include/mach/debug-macro.S | 12 ++--
arch/arm/mach-omap2/include/mach/entry-macro.S | 4 +-
arch/arm/mach-omap2/io.c | 12 ++--
arch/arm/mach-omap2/irq.c | 2 +-
arch/arm/mach-omap2/opp2xxx.h | 2 +-
arch/arm/mach-omap2/serial.c | 6 +-
arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 +
arch/arm/plat-omap/include/plat/clock.h | 3 +-
arch/arm/plat-omap/include/plat/common.h | 4 +-
arch/arm/plat-omap/include/plat/cpu.h | 22 ++++++++
arch/arm/plat-omap/include/plat/hardware.h | 2 +-
arch/arm/plat-omap/include/plat/io.h | 6 +-
arch/arm/plat-omap/include/plat/irqs.h | 2 +-
arch/arm/plat-omap/include/plat/serial.h | 14 +++---
.../plat-omap/include/plat/{ti816x.h => ti81xx.h} | 18 ++++----
arch/arm/plat-omap/include/plat/uncompress.h | 11 +++--
arch/arm/plat-omap/io.c | 2 +-
27 files changed, 186 insertions(+), 77 deletions(-)
create mode 100644 arch/arm/mach-omap2/board-ti8148evm.c
rename arch/arm/plat-omap/include/plat/{ti816x.h => ti81xx.h} (60%)
--
1.7.3.5
^ permalink raw reply
* [PATCH v2 1/3] TI81XX: Prepare for addition of TI814X support
From: Hemant Pedanekar @ 2011-09-21 17:38 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates existing macros, functions used for TI816X, to enable
addition of other SoCs belonging to TI81XX family (e.g., TI814X).
The approach taken is to use TI81XX/ti81xx for code/data going to be common
across all TI81XX devices.
cpu_is_ti81xx() is introduced to handle code common across TI81XX devices.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
---
arch/arm/mach-omap2/Kconfig | 6 ++--
arch/arm/mach-omap2/board-ti8168evm.c | 8 +++---
arch/arm/mach-omap2/clock3xxx_data.c | 2 +-
arch/arm/mach-omap2/common.c | 22 ++++++++++----------
arch/arm/mach-omap2/control.h | 8 +++---
arch/arm/mach-omap2/id.c | 8 +++---
arch/arm/mach-omap2/include/mach/debug-macro.S | 12 +++++-----
arch/arm/mach-omap2/include/mach/entry-macro.S | 4 +-
arch/arm/mach-omap2/io.c | 12 +++++-----
arch/arm/mach-omap2/irq.c | 2 +-
arch/arm/mach-omap2/serial.c | 6 ++--
arch/arm/plat-omap/include/plat/common.h | 4 +-
arch/arm/plat-omap/include/plat/cpu.h | 13 +++++++++++
arch/arm/plat-omap/include/plat/hardware.h | 2 +-
arch/arm/plat-omap/include/plat/io.h | 6 ++--
arch/arm/plat-omap/include/plat/irqs.h | 2 +-
arch/arm/plat-omap/include/plat/serial.h | 14 ++++++------
.../plat-omap/include/plat/{ti816x.h => ti81xx.h} | 18 ++++++++--------
arch/arm/plat-omap/include/plat/uncompress.h | 8 +++---
arch/arm/plat-omap/io.c | 2 +-
20 files changed, 86 insertions(+), 73 deletions(-)
rename arch/arm/plat-omap/include/plat/{ti816x.h => ti81xx.h} (60%)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 7edf802..a3b9227 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -73,8 +73,8 @@ config SOC_OMAP3430
default y
select ARCH_OMAP_OTG
-config SOC_OMAPTI816X
- bool "TI816X support"
+config SOC_OMAPTI81XX
+ bool "TI81XX support"
depends on ARCH_OMAP3
default y
@@ -313,7 +313,7 @@ config MACH_OMAP_3630SDP
config MACH_TI8168EVM
bool "TI8168 Evaluation Module"
- depends on SOC_OMAPTI816X
+ depends on SOC_OMAPTI81XX
default y
config MACH_OMAP_4430SDP
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index e26c79c..e0c7300 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -37,16 +37,16 @@ static void __init ti8168_evm_init(void)
static void __init ti8168_evm_map_io(void)
{
- omap2_set_globals_ti816x();
- omapti816x_map_common_io();
+ omap2_set_globals_ti81xx();
+ omapti81xx_map_common_io();
}
MACHINE_START(TI8168EVM, "ti8168evm")
/* Maintainer: Texas Instruments */
.atag_offset = 0x100,
.map_io = ti8168_evm_map_io,
- .init_early = ti816x_init_early,
- .init_irq = ti816x_init_irq,
+ .init_early = ti81xx_init_early,
+ .init_irq = ti81xx_init_irq,
.timer = &omap3_timer,
.init_machine = ti8168_evm_init,
MACHINE_END
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index dadb8c6..6054654 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3576,7 +3576,7 @@ int __init omap3xxx_clk_init(void)
* Lock DPLL5 -- here only until other device init code can
* handle this
*/
- if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+ if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
omap3_clk_lock_dpll5();
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 3f20cbb..7ce80f2 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -101,23 +101,23 @@ void __init omap3_map_io(void)
/*
* Adjust TAP register base such that omap3_check_revision accesses the correct
- * TI816X register for checking device ID (it adds 0x204 to tap base while
- * TI816X DEVICE ID register is at offset 0x600 from control base).
+ * TI81XX register for checking device ID (it adds 0x204 to tap base while
+ * TI81XX DEVICE ID register is at offset 0x600 from control base).
*/
-#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \
- TI816X_CONTROL_DEVICE_ID - 0x204)
+#define TI81XX_TAP_BASE (TI81XX_CTRL_BASE + \
+ TI81XX_CONTROL_DEVICE_ID - 0x204)
-static struct omap_globals ti816x_globals = {
+static struct omap_globals ti81xx_globals = {
.class = OMAP343X_CLASS,
- .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
- .ctrl = TI816X_CTRL_BASE,
- .prm = TI816X_PRCM_BASE,
- .cm = TI816X_PRCM_BASE,
+ .tap = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE),
+ .ctrl = TI81XX_CTRL_BASE,
+ .prm = TI81XX_PRCM_BASE,
+ .cm = TI81XX_PRCM_BASE,
};
-void __init omap2_set_globals_ti816x(void)
+void __init omap2_set_globals_ti81xx(void)
{
- __omap2_set_globals(&ti816x_globals);
+ __omap2_set_globals(&ti81xx_globals);
}
#endif
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index d4ef75d..0ba68d3 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -52,8 +52,8 @@
#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
-/* TI816X spefic control submodules */
-#define TI816X_CONTROL_DEVCONF 0x600
+/* TI81XX spefic control submodules */
+#define TI81XX_CONTROL_DEVCONF 0x600
/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
@@ -244,8 +244,8 @@
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
-/* TI816X CONTROL_DEVCONF register offsets */
-#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000)
+/* TI81XX CONTROL_DEVCONF register offsets */
+#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
/*
* REVISIT: This list of registers is not comprehensive - there are more
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index d27daf9..ab2f417 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -223,7 +223,7 @@ static void __init omap4_check_features(void)
}
}
-static void __init ti816x_check_features(void)
+static void __init ti81xx_check_features(void)
{
omap_features = OMAP3_HAS_NEON;
}
@@ -469,11 +469,11 @@ void __init omap2_check_revision(void)
} else if (cpu_is_omap34xx()) {
omap3_check_revision(&cpu_rev);
- /* TI816X doesn't have feature register */
- if (!cpu_is_ti816x())
+ /* TI81XX doesn't have feature register */
+ if (!cpu_is_ti81xx())
omap3_check_features();
else
- ti816x_check_features();
+ ti81xx_check_features();
omap3_cpuinfo(cpu_rev);
return;
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 48adfe9..309e328 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -72,11 +72,11 @@ omap_uart_lsr: .word 0
beq 34f @ configure OMAP3UART4
cmp \rp, #OMAP4UART4 @ only on 44xx
beq 44f @ configure OMAP4UART4
- cmp \rp, #TI816XUART1 @ ti816x UART offsets different
+ cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different
beq 81f @ configure UART1
- cmp \rp, #TI816XUART2 @ ti816x UART offsets different
+ cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different
beq 82f @ configure UART2
- cmp \rp, #TI816XUART3 @ ti816x UART offsets different
+ cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different
beq 83f @ configure UART3
cmp \rp, #ZOOM_UART @ only on zoom2/3
beq 95f @ configure ZOOM_UART
@@ -100,11 +100,11 @@ omap_uart_lsr: .word 0
b 98f
44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
b 98f
-81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE)
+81: mov \rp, #UART_OFFSET(TI81XX_UART1_BASE)
b 98f
-82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE)
+82: mov \rp, #UART_OFFSET(TI81XX_UART2_BASE)
b 98f
-83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE)
+83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
b 98f
95: ldr \rp, =ZOOM_UART_BASE
mrc p15, 0, \rv, c1, c0
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index ceb8b7e..cb2fb98 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -64,7 +64,7 @@
bne 9998f
/*
- * ti816x has additional IRQ pending register. Checking this
+ * ti81xx has additional IRQ pending register. Checking this
* register on omap2 & omap3 has no effect (read as 0).
*/
ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
@@ -141,7 +141,7 @@
bne 9999f
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
-#ifdef CONFIG_SOC_OMAPTI816X
+#ifdef CONFIG_SOC_OMAPTI81XX
bne 9999f
ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
cmp \irqnr, #0x0
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 15f91c4..f065edf 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -176,8 +176,8 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
};
#endif
-#ifdef CONFIG_SOC_OMAPTI816X
-static struct map_desc omapti816x_io_desc[] __initdata = {
+#ifdef CONFIG_SOC_OMAPTI81XX
+static struct map_desc omapti81xx_io_desc[] __initdata = {
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
@@ -279,10 +279,10 @@ void __init omap34xx_map_common_io(void)
}
#endif
-#ifdef CONFIG_SOC_OMAPTI816X
-void __init omapti816x_map_common_io(void)
+#ifdef CONFIG_SOC_OMAPTI81XX
+void __init omapti81xx_map_common_io(void)
{
- iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
+ iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
_omap2_map_common_io();
}
#endif
@@ -435,7 +435,7 @@ void __init am35xx_init_early(void)
omap2_init_common_infrastructure();
}
-void __init ti816x_init_early(void)
+void __init ti81xx_init_early(void)
{
omap2_init_common_infrastructure();
}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 3a12f75..f8a18f7 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -186,7 +186,7 @@ void __init omap3_init_irq(void)
omap_init_irq(OMAP34XX_IC_BASE, 96);
}
-void __init ti816x_init_irq(void)
+void __init ti81xx_init_irq(void)
{
omap_init_irq(OMAP34XX_IC_BASE, 128);
}
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 466fc722..08ec099 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -486,7 +486,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
mod_timer(&uart->timer, jiffies + uart->timeout);
omap_uart_smart_idle_enable(uart, 0);
- if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
+ if (cpu_is_omap34xx() && !cpu_is_ti81xx()) {
u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
u32 wk_mask = 0;
u32 padconf = 0;
@@ -768,7 +768,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
*/
uart->regshift = p->regshift;
uart->membase = p->membase;
- if (cpu_is_omap44xx() || cpu_is_ti816x())
+ if (cpu_is_omap44xx() || cpu_is_ti81xx())
uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
@@ -851,7 +851,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
}
/* Enable the MDR1 errata for OMAP3 */
- if (cpu_is_omap34xx() && !cpu_is_ti816x())
+ if (cpu_is_omap34xx() && !cpu_is_ti81xx())
uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
}
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 5cac97e..34480b5 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -51,7 +51,7 @@ void omap3430_init_early(void);
void omap35xx_init_early(void);
void omap3630_init_early(void);
void am35xx_init_early(void);
-void ti816x_init_early(void);
+void ti81xx_init_early(void);
void omap4430_init_early(void);
/*
@@ -75,7 +75,7 @@ void omap2_set_globals_242x(void);
void omap2_set_globals_243x(void);
void omap2_set_globals_3xxx(void);
void omap2_set_globals_443x(void);
-void omap2_set_globals_ti816x(void);
+void omap2_set_globals_ti81xx(void);
/* These get called from omap2_set_globals_xxxx(), do not call these */
void omap2_set_globals_tap(struct omap_globals *);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2f90269..2c3fbce 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -78,6 +78,14 @@ static inline int is_omap ##class (void) \
return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
}
+#define GET_TI_CLASS ((omap_rev() >> 24) & 0xff)
+
+#define IS_TI_CLASS(class, id) \
+static inline int is_ti ##class (void) \
+{ \
+ return (GET_TI_CLASS == (id)) ? 1 : 0; \
+}
+
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
#define IS_OMAP_SUBCLASS(subclass, id) \
@@ -99,6 +107,8 @@ IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
+IS_TI_CLASS(81xx, 0x81)
+
IS_OMAP_SUBCLASS(242x, 0x242)
IS_OMAP_SUBCLASS(243x, 0x243)
IS_OMAP_SUBCLASS(343x, 0x343)
@@ -116,6 +126,7 @@ IS_TI_SUBCLASS(816x, 0x816)
#define cpu_is_omap243x() 0
#define cpu_is_omap34xx() 0
#define cpu_is_omap343x() 0
+#define cpu_is_ti81xx() 0
#define cpu_is_ti816x() 0
#define cpu_is_omap44xx() 0
#define cpu_is_omap443x() 0
@@ -322,6 +333,7 @@ IS_OMAP_TYPE(3517, 0x3517)
# undef cpu_is_omap3530
# undef cpu_is_omap3505
# undef cpu_is_omap3517
+# undef cpu_is_ti81xx
# undef cpu_is_ti816x
# define cpu_is_omap3430() is_omap3430()
# define cpu_is_omap3503() (cpu_is_omap3430() && \
@@ -339,6 +351,7 @@ IS_OMAP_TYPE(3517, 0x3517)
!omap3_has_sgx())
# undef cpu_is_omap3630
# define cpu_is_omap3630() is_omap363x()
+# define cpu_is_ti81xx() is_ti81xx()
# define cpu_is_ti816x() is_ti816x()
#endif
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e87efe1..1a2f830 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -286,6 +286,6 @@
#include <plat/omap24xx.h>
#include <plat/omap34xx.h>
#include <plat/omap44xx.h>
-#include <plat/ti816x.h>
+#include <plat/ti81xx.h>
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 75311fc..ca36735 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -283,10 +283,10 @@ static inline void omap34xx_map_common_io(void)
}
#endif
-#ifdef CONFIG_SOC_OMAPTI816X
-extern void omapti816x_map_common_io(void);
+#ifdef CONFIG_SOC_OMAPTI81XX
+extern void omapti81xx_map_common_io(void);
#else
-static inline void omapti816x_map_common_io(void)
+static inline void omapti81xx_map_common_io(void)
{
}
#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 30e1071..0af9a22 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -441,7 +441,7 @@ extern void __iomem *omap_irq_base;
void omap1_init_irq(void);
void omap2_init_irq(void);
void omap3_init_irq(void);
-void ti816x_init_irq(void);
+void ti81xx_init_irq(void);
extern int omap_irq_pending(void);
void omap_intc_save_context(void);
void omap_intc_restore_context(void);
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index de3b10c..865b13e 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -51,10 +51,10 @@
#define OMAP4_UART3_BASE 0x48020000
#define OMAP4_UART4_BASE 0x4806e000
-/* TI816X serial ports */
-#define TI816X_UART1_BASE 0x48020000
-#define TI816X_UART2_BASE 0x48022000
-#define TI816X_UART3_BASE 0x48024000
+/* TI81XX serial ports */
+#define TI81XX_UART1_BASE 0x48020000
+#define TI81XX_UART2_BASE 0x48022000
+#define TI81XX_UART3_BASE 0x48024000
/* AM3505/3517 UART4 */
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
@@ -89,9 +89,9 @@
#define OMAP4UART2 OMAP2UART2
#define OMAP4UART3 43
#define OMAP4UART4 44
-#define TI816XUART1 81
-#define TI816XUART2 82
-#define TI816XUART3 83
+#define TI81XXUART1 81
+#define TI81XXUART2 82
+#define TI81XXUART3 83
#define ZOOM_UART 95 /* Only on zoom2/3 */
/* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti81xx.h
similarity index 60%
rename from arch/arm/plat-omap/include/plat/ti816x.h
rename to arch/arm/plat-omap/include/plat/ti81xx.h
index 50510f5..8f9843f 100644
--- a/arch/arm/plat-omap/include/plat/ti816x.h
+++ b/arch/arm/plat-omap/include/plat/ti81xx.h
@@ -1,5 +1,5 @@
/*
- * This file contains the address data for various TI816X modules.
+ * This file contains the address data for various TI81XX modules.
*
* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
*
@@ -13,15 +13,15 @@
* GNU General Public License for more details.
*/
-#ifndef __ASM_ARCH_TI816X_H
-#define __ASM_ARCH_TI816X_H
+#ifndef __ASM_ARCH_TI81XX_H
+#define __ASM_ARCH_TI81XX_H
-#define L4_SLOW_TI816X_BASE 0x48000000
+#define L4_SLOW_TI81XX_BASE 0x48000000
-#define TI816X_SCM_BASE 0x48140000
-#define TI816X_CTRL_BASE TI816X_SCM_BASE
-#define TI816X_PRCM_BASE 0x48180000
+#define TI81XX_SCM_BASE 0x48140000
+#define TI81XX_CTRL_BASE TI81XX_SCM_BASE
+#define TI81XX_PRCM_BASE 0x48180000
-#define TI816X_ARM_INTC_BASE 0x48200000
+#define TI81XX_ARM_INTC_BASE 0x48200000
-#endif /* __ASM_ARCH_TI816X_H */
+#endif /* __ASM_ARCH_TI81XX_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index cb4a6c2..40336ad 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -93,9 +93,9 @@ static inline void flush(void)
#define DEBUG_LL_ZOOM(mach) \
_DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
-#define DEBUG_LL_TI816X(p, mach) \
- _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \
- TI816XUART##p)
+#define DEBUG_LL_TI81XX(p, mach) \
+ _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
+ TI81XXUART##p)
static inline void __arch_decomp_setup(unsigned long arch_id)
{
@@ -173,7 +173,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
DEBUG_LL_ZOOM(omap_zoom3);
/* TI8168 base boards using UART3 */
- DEBUG_LL_TI816X(3, ti8168evm);
+ DEBUG_LL_TI81XX(3, ti8168evm);
} while (0);
}
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index f1ecfa9..1443992 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -85,7 +85,7 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
}
#endif
#ifdef CONFIG_ARCH_OMAP3
- if (cpu_is_ti816x()) {
+ if (cpu_is_ti81xx()) {
if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
} else if (cpu_is_omap34xx()) {
--
1.7.3.5
^ permalink raw reply related
* [PATCH v2 2/3] TI814X: Add cpu type macros and detection support
From: Hemant Pedanekar @ 2011-09-21 17:39 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds cpu type, macros for identification of TI814X device.
Note that following update to common OMAP data structures is made:
cpu_mask and RATE_IN_XXX flags have crossed 8 bit hence struct
clksel_rate.flags, struct prcm_config.flags and cpu_mask are changed to u16 from
u8.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
---
arch/arm/mach-omap2/clock.c | 2 +-
arch/arm/mach-omap2/clock.h | 2 +-
arch/arm/mach-omap2/clock3xxx_data.c | 3 +++
arch/arm/mach-omap2/id.c | 22 ++++++++++++++++++++++
arch/arm/mach-omap2/opp2xxx.h | 2 +-
arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 +
arch/arm/plat-omap/include/plat/clock.h | 3 ++-
arch/arm/plat-omap/include/plat/cpu.h | 9 +++++++++
8 files changed, 40 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 1f3481f..f57ed5b 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -35,7 +35,7 @@
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
-u8 cpu_mask;
+u16 cpu_mask;
/*
* clkdm_control: if true, then when a clock is enabled in the
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 48ac568..687d3d3 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -130,7 +130,7 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
const char *core_ck_name,
const char *mpu_ck_name);
-extern u8 cpu_mask;
+extern u16 cpu_mask;
extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_dummy;
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 6054654..b4d5f84 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3493,6 +3493,9 @@ int __init omap3xxx_clk_init(void)
} else if (cpu_is_ti816x()) {
cpu_mask = RATE_IN_TI816X;
cpu_clkflg = CK_TI816X;
+ } else if (cpu_is_ti814x()) {
+ cpu_mask = RATE_IN_TI814X;
+ cpu_clkflg = CK_TI814X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index ab2f417..f07faa9 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -337,6 +337,26 @@ static void __init omap3_check_revision(const char **cpu_rev)
break;
}
break;
+ case 0xb8f2:
+ switch (rev) {
+ case 0:
+ /* FALLTHROUGH */
+ case 1:
+ omap_revision = TI8148_REV_ES1_0;
+ *cpu_rev = "1.0";
+ break;
+ case 2:
+ omap_revision = TI8148_REV_ES2_0;
+ *cpu_rev = "2.0";
+ break;
+ case 3:
+ /* FALLTHROUGH */
+ default:
+ omap_revision = TI8148_REV_ES2_1;
+ *cpu_rev = "2.1";
+ break;
+ }
+ break;
default:
/* Unknown default to latest silicon rev as default */
omap_revision = OMAP3630_REV_ES1_2;
@@ -429,6 +449,8 @@ static void __init omap3_cpuinfo(const char *cpu_rev)
cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
} else if (cpu_is_ti816x()) {
cpu_name = "TI816X";
+ } else if (cpu_is_ti814x()) {
+ cpu_name = "TI814X";
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
cpu_name = "OMAP3430/3530";
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
index 8affc66..8fae534 100644
--- a/arch/arm/mach-omap2/opp2xxx.h
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -51,7 +51,7 @@ struct prcm_config {
unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
unsigned long base_sdrc_rfr; /* base refresh timing for a set */
- unsigned char flags;
+ unsigned short flags;
};
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index 387a963..3c50ec8 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -40,6 +40,7 @@ struct omap_clk {
#define CK_443X (1 << 11)
#define CK_TI816X (1 << 12)
#define CK_446X (1 << 13)
+#define CK_TI814X (1 << 14)
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 197ca03..3c6e6f8 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -59,6 +59,7 @@ struct clkops {
#define RATE_IN_4430 (1 << 5)
#define RATE_IN_TI816X (1 << 6)
#define RATE_IN_4460 (1 << 7)
+#define RATE_IN_TI814X (1 << 8)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@@ -84,7 +85,7 @@ struct clkops {
struct clksel_rate {
u32 val;
u8 div;
- u8 flags;
+ u16 flags;
};
/**
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2c3fbce..35f9d43 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -117,6 +117,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
IS_OMAP_SUBCLASS(446x, 0x446)
IS_TI_SUBCLASS(816x, 0x816)
+IS_TI_SUBCLASS(814x, 0x814)
#define cpu_is_omap7xx() 0
#define cpu_is_omap15xx() 0
@@ -128,6 +129,7 @@ IS_TI_SUBCLASS(816x, 0x816)
#define cpu_is_omap343x() 0
#define cpu_is_ti81xx() 0
#define cpu_is_ti816x() 0
+#define cpu_is_ti814x() 0
#define cpu_is_omap44xx() 0
#define cpu_is_omap443x() 0
#define cpu_is_omap446x() 0
@@ -335,6 +337,7 @@ IS_OMAP_TYPE(3517, 0x3517)
# undef cpu_is_omap3517
# undef cpu_is_ti81xx
# undef cpu_is_ti816x
+# undef cpu_is_ti814x
# define cpu_is_omap3430() is_omap3430()
# define cpu_is_omap3503() (cpu_is_omap3430() && \
(!omap3_has_iva()) && \
@@ -353,6 +356,7 @@ IS_OMAP_TYPE(3517, 0x3517)
# define cpu_is_omap3630() is_omap363x()
# define cpu_is_ti81xx() is_ti81xx()
# define cpu_is_ti816x() is_ti816x()
+# define cpu_is_ti814x() is_ti814x()
#endif
# if defined(CONFIG_ARCH_OMAP4)
@@ -399,6 +403,11 @@ IS_OMAP_TYPE(3517, 0x3517)
#define TI8168_REV_ES1_0 TI816X_CLASS
#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
+#define TI814X_CLASS 0x81400034
+#define TI8148_REV_ES1_0 TI814X_CLASS
+#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8))
+#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8))
+
#define OMAP443X_CLASS 0x44300044
#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
--
1.7.3.5
^ permalink raw reply related
* [PATCH v2 3/3] TI814X: Create board support and enable build for TI8148 EVM
From: Hemant Pedanekar @ 2011-09-21 17:39 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds minimal support and build configuration for TI8148 EVM. Also
adds support for low level debugging on UART1 console on the EVM.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
---
arch/arm/mach-omap2/Kconfig | 5 +++
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/board-ti8148evm.c | 51 ++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/uncompress.h | 3 ++
4 files changed, 60 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/board-ti8148evm.c
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index a3b9227..cc4f213 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -316,6 +316,11 @@ config MACH_TI8168EVM
depends on SOC_OMAPTI81XX
default y
+config MACH_TI8148EVM
+ bool "TI8148 Evaluation Module"
+ depends on SOC_OMAPTI81XX
+ default y
+
config MACH_OMAP_4430SDP
bool "OMAP 4430 SDP board"
default y
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 46a3497..597a2b6 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -242,6 +242,7 @@ obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o
obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o
+obj-$(CONFIG_MACH_TI8148EVM) += board-ti8148evm.o
# Platform specific device init code
diff --git a/arch/arm/mach-omap2/board-ti8148evm.c b/arch/arm/mach-omap2/board-ti8148evm.c
new file mode 100644
index 0000000..355c766
--- /dev/null
+++ b/arch/arm/mach-omap2/board-ti8148evm.c
@@ -0,0 +1,51 @@
+/*
+ * Code for TI8148 EVM.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/irqs.h>
+#include <plat/board.h>
+#include <plat/common.h>
+
+static struct omap_board_config_kernel ti8148_evm_config[] __initdata = {
+};
+
+static void __init ti8148_evm_init(void)
+{
+ omap_serial_init();
+ omap_board_config = ti8148_evm_config;
+ omap_board_config_size = ARRAY_SIZE(ti8148_evm_config);
+}
+
+static void __init ti8148_evm_map_io(void)
+{
+ omap2_set_globals_ti81xx();
+ omapti81xx_map_common_io();
+}
+
+MACHINE_START(TI8148EVM, "ti8148evm")
+ /* Maintainer: Texas Instruments */
+ .atag_offset = 0x100,
+ .map_io = ti8148_evm_map_io,
+ .init_early = ti81xx_init_early,
+ .init_irq = ti81xx_init_irq,
+ .timer = &omap3_timer,
+ .init_machine = ti8148_evm_init,
+MACHINE_END
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 40336ad..8d052e7 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -175,6 +175,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
/* TI8168 base boards using UART3 */
DEBUG_LL_TI81XX(3, ti8168evm);
+ /* TI8148 base boards using UART1 */
+ DEBUG_LL_TI81XX(1, ti8148evm);
+
} while (0);
}
--
1.7.3.5
^ permalink raw reply related
* [PATCH] ARM: vexpress: initial device tree support
From: Mitch Bradley @ 2011-09-21 17:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110921171545.GG2872@arm.com>
On 9/21/2011 7:15 AM, Dave Martin wrote:
> On Wed, Sep 21, 2011 at 11:37:54AM -0500, Rob Herring wrote:
>> On 09/21/2011 09:57 AM, Grant Likely wrote:
>>> On Wed, Sep 21, 2011 at 7:24 AM, Rob Herring<robherring2@gmail.com> wrote:
>>>> On 09/21/2011 04:19 AM, Dave Martin wrote:
>>>>> * arm,amba-bus -- widely used by other boards and patchsets, but
>>>>> seems not to be documented.
>>>>>
>>>>
>>>> This should be dropped. There's not really any bus component to an amba
>>>> bus. All the probing info is within the primecell peripherals.
>>>
>>> No, if it is an AMBA bus, then it is entirely appropriate to declare
>>> it as an amba bus, but to also be compatible with "simple-bus". In
>>> fact, it would be better to use a compatible string that specifies the
>>> specific implementation of AMBA bus since there are several versions
>>> of the spec.
>>
>> And type of AMBA bus as the spec includes AXI, AHB, and APB. None of
>> which have any sort of programmability or software view.
>>
>> If this is required, then the policy should be simple-bus should never
>> be allowed alone as every bus has some underlying type. Seems like
>> overkill for buses like this.
>
> The key question is _where_ to draw the line between generic and specific.
> By definition, the DT can never be a comprehensive description of the
> hardware -- rather a good DT is a description of those details of the hardware
> which could relevant to any hypothetical OS.
>
> The flipside is that details which were thought to be irrelevant at
> design/implementation time can turn out to be relevant in practice, due
> to errata and implementation issues etc. So taking the description slightly
> beyond what the OS needs to know can still have some merit.
>
>
> I still don't know how to say where the line should be drawn in this particular
> case though.
Here are some criteria:
If the controller for the bus itself has registers, include the bus node
If it is possible to plug new stuff into the bus, include the bus node
If the base address for the bus can be changed, thereby changing all the
addresses of its subordinates by the same offset, include the bus node
(this usually goes along with "has registers".)
ARM buses typically don't have any of those attributes, but there are
some weaker criteria that can be used to justify including a bus node.
The SoC on which I'm currently working has some peripherals on AXI and
others on APB. That doesn't matter from that addressing standpoint -
the individual peripherals can each be viewed as having an address, end
of story - but it does matter from a power management standpoint. The
clock tree is quite related to the bus layout. Including bus nodes in
the device tree might provide useful place-holders for properties
describing power or clock domains.
So, on the whole, I'm in favor of including bus nodes for ARM standard
buses. There is little down side to doing so, and a fair chance that it
might come in handy in the future.
>
> Cheers
> ---Dave
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
>
^ permalink raw reply
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