* [PATCH 4/9] serial: samsung: remove struct 's3c24xx_uart_clksrc' and all uses of it
From: Thomas Abraham @ 2011-09-26 19:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317064038-32428-1-git-send-email-thomas.abraham@linaro.org>
With clkdev based clock lookup added to samsung serial driver, the use
of 'struct s3c24xx_uart_clksrc' to supply clock names in platform
data can be removed.
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Ramax Lo <ramaxlo@gmail.com>
Cc: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos4/init.c | 15 +----------
arch/arm/mach-s3c2410/mach-bast.c | 22 ---------------
arch/arm/mach-s3c2410/mach-vr1000.c | 24 -----------------
arch/arm/mach-s3c2440/mach-anubis.c | 22 +--------------
arch/arm/mach-s3c2440/mach-at2440evb.c | 22 +--------------
arch/arm/mach-s3c2440/mach-osiris.c | 24 ++---------------
arch/arm/mach-s3c2440/mach-rx1950.c | 18 ++----------
arch/arm/mach-s3c2440/mach-rx3715.c | 19 ++-----------
arch/arm/mach-s5p64x0/init.c | 31 ----------------------
arch/arm/mach-s5pv210/init.c | 19 -------------
arch/arm/plat-samsung/include/plat/regs-serial.h | 23 ----------------
drivers/tty/serial/samsung.h | 1 -
12 files changed, 14 insertions(+), 226 deletions(-)
diff --git a/arch/arm/mach-exynos4/init.c b/arch/arm/mach-exynos4/init.c
index a8a83e3..e836c9c 100644
--- a/arch/arm/mach-exynos4/init.c
+++ b/arch/arm/mach-exynos4/init.c
@@ -14,15 +14,6 @@
#include <plat/devs.h>
#include <plat/regs-serial.h>
-static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
- [0] = {
- .name = "uclk1",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- },
-};
-
/* uart registration process */
void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
@@ -30,11 +21,7 @@ void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
u32 ucnt;
for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
- if (!tcfg->clocks) {
- tcfg->has_fracval = 1;
- tcfg->clocks = exynos4_serial_clocks;
- tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
- }
+ tcfg->has_fracval = 1;
tcfg->flags |= NO_NEED_CHECK_CLKSRC;
}
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 1e2d536..e92e29b 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -164,22 +164,6 @@ static struct map_desc bast_iodesc[] __initdata = {
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
- [0] = {
- .name = "uclk",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- },
- [1] = {
- .name = "pclk",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- }
-};
-
-
static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
@@ -187,8 +171,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = bast_serial_clocks,
- .clocks_size = ARRAY_SIZE(bast_serial_clocks),
},
[1] = {
.hwport = 1,
@@ -196,8 +178,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = bast_serial_clocks,
- .clocks_size = ARRAY_SIZE(bast_serial_clocks),
},
/* port 2 is not actually used */
[2] = {
@@ -206,8 +186,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = bast_serial_clocks,
- .clocks_size = ARRAY_SIZE(bast_serial_clocks),
}
};
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 6ccce5a..208d83a 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -109,23 +109,6 @@ static struct map_desc vr1000_iodesc[] __initdata = {
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-/* uart clock source(s) */
-
-static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
- [0] = {
- .name = "uclk",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- },
- [1] = {
- .name = "pclk",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0.
- }
-};
-
static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
@@ -133,8 +116,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = vr1000_serial_clocks,
- .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
},
[1] = {
.hwport = 1,
@@ -142,8 +123,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = vr1000_serial_clocks,
- .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
},
/* port 2 is not actually used */
[2] = {
@@ -152,9 +131,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = vr1000_serial_clocks,
- .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
-
}
};
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index d708678..0097585 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -96,22 +96,6 @@ static struct map_desc anubis_iodesc[] __initdata = {
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
- [0] = {
- .name = "uclk",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- },
- [1] = {
- .name = "pclk",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- }
-};
-
-
static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
@@ -119,8 +103,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = anubis_serial_clocks,
- .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
},
[1] = {
.hwport = 2,
@@ -128,8 +111,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = anubis_serial_clocks,
- .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
},
};
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 6c98b78..4cc60b1 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -57,22 +57,6 @@ static struct map_desc at2440evb_iodesc[] __initdata = {
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
-static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = {
- [0] = {
- .name = "uclk",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- },
- [1] = {
- .name = "pclk",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- }
-};
-
-
static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
@@ -80,8 +64,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = at2440evb_serial_clocks,
- .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
},
[1] = {
.hwport = 1,
@@ -89,8 +72,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = at2440evb_serial_clocks,
- .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
},
};
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index d885363..b75ed46 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -100,21 +100,6 @@ static struct map_desc osiris_iodesc[] __initdata = {
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
- [0] = {
- .name = "uclk",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- },
- [1] = {
- .name = "pclk",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- }
-};
-
static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
@@ -122,8 +107,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = osiris_serial_clocks,
- .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
},
[1] = {
.hwport = 1,
@@ -131,8 +115,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = osiris_serial_clocks,
- .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
},
[2] = {
.hwport = 2,
@@ -140,8 +123,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
- .clocks = osiris_serial_clocks,
- .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
}
};
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 9528b37..04bb392 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -67,15 +67,6 @@
static struct map_desc rx1950_iodesc[] __initdata = {
};
-static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = {
- [0] = {
- .name = "fclk_n",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- },
-};
-
static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
@@ -83,8 +74,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
- .clocks = rx1950_serial_clocks,
- .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL3,
},
[1] = {
.hwport = 1,
@@ -92,8 +82,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
- .clocks = rx1950_serial_clocks,
- .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL3,
},
/* IR port */
[2] = {
@@ -102,8 +91,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
.ucon = 0x3c5,
.ulcon = 0x43,
.ufcon = 0xf1,
- .clocks = rx1950_serial_clocks,
- .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL3,
},
};
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index a88247e..3c0d17c 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -67,16 +67,6 @@ static struct map_desc rx3715_iodesc[] __initdata = {
},
};
-
-static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
- [0] = {
- .name = "fclk_n",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- }
-};
-
static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
[0] = {
.hwport = 0,
@@ -84,8 +74,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
- .clocks = rx3715_serial_clocks,
- .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL3,
},
[1] = {
.hwport = 1,
@@ -93,8 +82,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x00,
- .clocks = rx3715_serial_clocks,
- .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL3,
},
/* IR port */
[2] = {
@@ -103,8 +91,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
.ucon = 0x3c5,
.ulcon = 0x43,
.ufcon = 0x51,
- .clocks = rx3715_serial_clocks,
- .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
+ .clk_sel = S3C2410_UCON_CLKSEL3,
}
};
diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
index 79833ca..659a66c 100644
--- a/arch/arm/mach-s5p64x0/init.c
+++ b/arch/arm/mach-s5p64x0/init.c
@@ -23,36 +23,7 @@
#include <plat/s5p6450.h>
#include <plat/regs-serial.h>
-static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
- [0] = {
- .name = "pclk_low",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- },
- [1] = {
- .name = "uclk1",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- },
-};
-
/* uart registration process */
-
-void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
- struct s3c2410_uartcfg *tcfg = cfg;
- u32 ucnt;
-
- for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
- if (!tcfg->clocks) {
- tcfg->clocks = s5p64x0_serial_clocks;
- tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
- }
- }
-}
-
void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
int uart;
@@ -62,12 +33,10 @@ void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
}
- s5p64x0_common_init_uarts(cfg, no);
s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
}
void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
- s5p64x0_common_init_uarts(cfg, no);
s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
}
diff --git a/arch/arm/mach-s5pv210/init.c b/arch/arm/mach-s5pv210/init.c
index 4865ae2..468a5f8 100644
--- a/arch/arm/mach-s5pv210/init.c
+++ b/arch/arm/mach-s5pv210/init.c
@@ -18,27 +18,8 @@
#include <plat/s5pv210.h>
#include <plat/regs-serial.h>
-static struct s3c24xx_uart_clksrc s5pv210_serial_clocks[] = {
- [0] = {
- .name = "pclk",
- .divisor = 1,
- .min_baud = 0,
- .max_baud = 0,
- },
-};
-
/* uart registration process */
void __init s5pv210_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
- struct s3c2410_uartcfg *tcfg = cfg;
- u32 ucnt;
-
- for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
- if (!tcfg->clocks) {
- tcfg->clocks = s5pv210_serial_clocks;
- tcfg->clocks_size = ARRAY_SIZE(s5pv210_serial_clocks);
- }
- }
-
s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
}
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index b493d8d..25f0c36 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -229,26 +229,6 @@
#ifndef __ASSEMBLY__
-/* struct s3c24xx_uart_clksrc
- *
- * this structure defines a named clock source that can be used for the
- * uart, so that the best clock can be selected for the requested baud
- * rate.
- *
- * min_baud and max_baud define the range of baud-rates this clock is
- * acceptable for, if they are both zero, it is assumed any baud rate that
- * can be generated from this clock will be used.
- *
- * divisor gives the divisor from the clock to the one seen by the uart
-*/
-
-struct s3c24xx_uart_clksrc {
- const char *name;
- unsigned int divisor;
- unsigned int min_baud;
- unsigned int max_baud;
-};
-
/* configuration structure for per-machine configurations for the
* serial port
*
@@ -268,9 +248,6 @@ struct s3c2410_uartcfg {
unsigned long ucon; /* value of ucon for port */
unsigned long ulcon; /* value of ulcon for port */
unsigned long ufcon; /* value of ufcon for port */
-
- struct s3c24xx_uart_clksrc *clocks;
- unsigned int clocks_size;
};
/* s3c24xx_uart_devs
diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
index 11369f3..40e9ef1 100644
--- a/drivers/tty/serial/samsung.h
+++ b/drivers/tty/serial/samsung.h
@@ -47,7 +47,6 @@ struct s3c24xx_uart_port {
unsigned int tx_irq;
struct s3c24xx_uart_info *info;
- struct s3c24xx_uart_clksrc *clksrc;
struct clk *clk;
struct clk *baudclk;
struct uart_port port;
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 3/9] serial: samsung: switch to clkdev based clock lookup
From: Thomas Abraham @ 2011-09-26 19:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317064038-32428-1-git-send-email-thomas.abraham@linaro.org>
Instead of using clock names supplied in platform data, use a generic
clock name 'clk_uart_baud' to look up clocks. The platform code should
register clocks with the name 'clk_uart_baud' which can be used by the
baud rate generator. The clock lookup and selection of the best clock
as baud rate clock is reworked.
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/plat-samsung/include/plat/regs-serial.h | 5 +
drivers/tty/serial/samsung.c | 207 +++++++++-------------
drivers/tty/serial/samsung.h | 4 +
3 files changed, 95 insertions(+), 121 deletions(-)
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index 7207348..b493d8d 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -222,6 +222,10 @@
#define S5PV210_UFSTAT_RXSHIFT (0)
#define NO_NEED_CHECK_CLKSRC 1
+#define S3C2410_UCON_CLKSEL0 (1 << 0)
+#define S3C2410_UCON_CLKSEL1 (1 << 1)
+#define S3C2410_UCON_CLKSEL2 (1 << 2)
+#define S3C2410_UCON_CLKSEL3 (1 << 3)
#ifndef __ASSEMBLY__
@@ -257,6 +261,7 @@ struct s3c2410_uartcfg {
unsigned char unused;
unsigned short flags;
upf_t uart_flags; /* default uart flags */
+ unsigned int clk_sel;
unsigned int has_fracval;
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index fc242b2..dc5a4ed 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -49,6 +49,7 @@
#include <mach/map.h>
#include <plat/regs-serial.h>
+#include <plat/clock.h>
#include "samsung.h"
@@ -558,133 +559,98 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
*
*/
+#define MAX_CLK_NAME_LENGTH 15
-#define MAX_CLKS (8)
-
-static struct s3c24xx_uart_clksrc tmp_clksrc = {
- .name = "pclk",
- .min_baud = 0,
- .max_baud = 0,
- .divisor = 1,
-};
-
-static inline int
-s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
+static inline int s3c24xx_serial_getsource(struct uart_port *port)
{
struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
+ unsigned int ucon;
- return (info->get_clksrc)(port, c);
-}
-
-static inline int
-s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
-{
- struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
+ if (info->num_clks == 1)
+ return 0;
- return (info->set_clksrc)(port, c);
+ ucon = rd_regl(port, S3C2410_UCON);
+ ucon &= info->clksel_mask;
+ return ucon >> info->clksel_shift;
}
-struct baud_calc {
- struct s3c24xx_uart_clksrc *clksrc;
- unsigned int calc;
- unsigned int divslot;
- unsigned int quot;
- struct clk *src;
-};
-
-static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
- struct uart_port *port,
- struct s3c24xx_uart_clksrc *clksrc,
- unsigned int baud)
+static void s3c24xx_serial_setsource(struct uart_port *port,
+ unsigned int clk_sel)
{
- struct s3c24xx_uart_port *ourport = to_ourport(port);
- unsigned long rate;
-
- calc->src = clk_get(port->dev, clksrc->name);
- if (calc->src == NULL || IS_ERR(calc->src))
- return 0;
-
- rate = clk_get_rate(calc->src);
- rate /= clksrc->divisor;
+ struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
+ unsigned int ucon;
- calc->clksrc = clksrc;
+ if (info->num_clks == 1)
+ return;
- if (ourport->info->has_divslot) {
- unsigned long div = rate / baud;
-
- /* The UDIVSLOT register on the newer UARTs allows us to
- * get a divisor adjustment of 1/16th on the baud clock.
- *
- * We don't keep the UDIVSLOT value (the 16ths we calculated
- * by not multiplying the baud by 16) as it is easy enough
- * to recalculate.
- */
-
- calc->quot = div / 16;
- calc->calc = rate / div;
- } else {
- calc->quot = (rate + (8 * baud)) / (16 * baud);
- calc->calc = (rate / (calc->quot * 16));
- }
+ ucon = rd_regl(port, S3C2410_UCON);
+ if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
+ return;
- calc->quot--;
- return 1;
+ ucon &= ~info->clksel_mask;
+ ucon |= clk_sel << info->clksel_shift;
+ wr_regl(port, S3C2410_UCON, ucon);
}
-static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
- struct s3c24xx_uart_clksrc **clksrc,
- struct clk **clk,
- unsigned int baud)
+static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
+ unsigned int req_baud, struct clk **best_clk,
+ unsigned int *clk_num)
{
- struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
- struct s3c24xx_uart_clksrc *clkp;
- struct baud_calc res[MAX_CLKS];
- struct baud_calc *resptr, *best, *sptr;
- int i;
-
- clkp = cfg->clocks;
- best = NULL;
-
- if (cfg->clocks_size < 2) {
- if (cfg->clocks_size == 0)
- clkp = &tmp_clksrc;
-
- s3c24xx_serial_calcbaud(res, port, clkp, baud);
- best = res;
- resptr = best + 1;
- } else {
- resptr = res;
-
- for (i = 0; i < cfg->clocks_size; i++, clkp++) {
- if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
- resptr++;
+ struct s3c24xx_uart_info *info = ourport->info;
+ struct clk *clk;
+ unsigned long rate;
+ unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
+ char clkname[MAX_CLK_NAME_LENGTH];
+ int calc_deviation, deviation = (1 << 30) - 1;
+
+ *best_clk = NULL;
+ clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
+ ourport->info->def_clk_sel;
+ for (cnt = 0; cnt < info->num_clks; cnt++) {
+ if (!(clk_sel & (1 << cnt)))
+ continue;
+
+ sprintf(clkname, "clk_uart_baud%d", cnt);
+ clk = clk_get(ourport->port.dev, clkname);
+ if (IS_ERR_OR_NULL(clk))
+ continue;
+
+ rate = clk_get_rate(clk);
+ if (!rate)
+ continue;
+
+ if (ourport->info->has_divslot) {
+ unsigned long div = rate / req_baud;
+
+ /* The UDIVSLOT register on the newer UARTs allows us to
+ * get a divisor adjustment of 1/16th on the baud clock.
+ *
+ * We don't keep the UDIVSLOT value (the 16ths we
+ * calculated by not multiplying the baud by 16) as it
+ * is easy enough to recalculate.
+ */
+
+ quot = div / 16;
+ baud = rate / div;
+ } else {
+ quot = (rate + (8 * req_baud)) / (16 * req_baud);
+ baud = rate / (quot * 16);
}
- }
-
- /* ok, we now need to select the best clock we found */
-
- if (!best) {
- unsigned int deviation = (1<<30)|((1<<30)-1);
- int calc_deviation;
+ quot--;
- for (sptr = res; sptr < resptr; sptr++) {
- calc_deviation = baud - sptr->calc;
- if (calc_deviation < 0)
- calc_deviation = -calc_deviation;
+ calc_deviation = req_baud - baud;
+ if (calc_deviation < 0)
+ calc_deviation = -calc_deviation;
- if (calc_deviation < deviation) {
- best = sptr;
- deviation = calc_deviation;
- }
+ if (calc_deviation < deviation) {
+ *best_clk = clk;
+ best_quot = quot;
+ *clk_num = cnt;
+ deviation = calc_deviation;
}
}
- /* store results to pass back */
-
- *clksrc = best->clksrc;
- *clk = best->src;
-
- return best->quot;
+ return best_quot;
}
/* udivslot_table[]
@@ -717,10 +683,9 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
{
struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
struct s3c24xx_uart_port *ourport = to_ourport(port);
- struct s3c24xx_uart_clksrc *clksrc = NULL;
struct clk *clk = NULL;
unsigned long flags;
- unsigned int baud, quot;
+ unsigned int baud, quot, clk_sel = 0;
unsigned int ulcon;
unsigned int umcon;
unsigned int udivslot = 0;
@@ -736,17 +701,16 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
*/
baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
-
+ quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
quot = port->custom_divisor;
- else
- quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
+ if (!clk)
+ return;
/* check to see if we need to change clock source */
- if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
- dbg("selecting clock %p\n", clk);
- s3c24xx_serial_setsource(port, clksrc);
+ if (ourport->baudclk != clk) {
+ s3c24xx_serial_setsource(port, clk_sel);
if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
clk_disable(ourport->baudclk);
@@ -755,7 +719,6 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
clk_enable(clk);
- ourport->clksrc = clksrc;
ourport->baudclk = clk;
ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
}
@@ -1202,7 +1165,7 @@ static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
struct uart_port *port = s3c24xx_dev_to_port(dev);
struct s3c24xx_uart_port *ourport = to_ourport(port);
- return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name);
+ return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->baudclk->name);
}
static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
@@ -1382,12 +1345,13 @@ static void __init
s3c24xx_serial_get_options(struct uart_port *port, int *baud,
int *parity, int *bits)
{
- struct s3c24xx_uart_clksrc clksrc;
struct clk *clk;
unsigned int ulcon;
unsigned int ucon;
unsigned int ubrdiv;
unsigned long rate;
+ unsigned int clk_sel;
+ char clk_name[MAX_CLK_NAME_LENGTH];
ulcon = rd_regl(port, S3C2410_ULCON);
ucon = rd_regl(port, S3C2410_UCON);
@@ -1432,11 +1396,12 @@ s3c24xx_serial_get_options(struct uart_port *port, int *baud,
/* now calculate the baud rate */
- s3c24xx_serial_getsource(port, &clksrc);
+ clk_sel = s3c24xx_serial_getsource(port);
+ sprintf(clk_name, "clk_uart_baud%d", clk_sel);
- clk = clk_get(port->dev, clksrc.name);
+ clk = clk_get(port->dev, clk_name);
if (!IS_ERR(clk) && clk != NULL)
- rate = clk_get_rate(clk) / clksrc.divisor;
+ rate = clk_get_rate(clk);
else
rate = 1;
diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
index 6c9cb9d..11369f3 100644
--- a/drivers/tty/serial/samsung.h
+++ b/drivers/tty/serial/samsung.h
@@ -19,6 +19,10 @@ struct s3c24xx_uart_info {
unsigned long tx_fifomask;
unsigned long tx_fifoshift;
unsigned long tx_fifofull;
+ unsigned int def_clk_sel;
+ unsigned long num_clks;
+ unsigned long clksel_mask;
+ unsigned long clksel_shift;
/* uart port features */
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 2/9] serial: samsung: move handling of fclk/n clock to platform code
From: Thomas Abraham @ 2011-09-26 19:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317064038-32428-1-git-send-email-thomas.abraham@linaro.org>
s3c2440 uses fclk/n (fclk divided by n) clock as one of the possible clocks used
to generate the baud rate clock. The divider 'n' in this case can be logically
represented outside of the uart controller.
This patch creates a new clock by name "fclk_n" for s3c2440 based platforms to
represent the fclk/n clock in the platform code. This clock provides a get_rate
callback that checks the UCON0/1/2 registers to determine the clock rate. The
samsung uart driver would receive the "fclk_n" clock name as one of the possible
baud rate clock options and the driver need not determine clock rate of fclk/n.
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-s3c2440/clock.c | 37 +++++++++++++++++++++++++++++++++++
arch/arm/mach-s3c2440/mach-rx1950.c | 4 +-
arch/arm/mach-s3c2440/mach-rx3715.c | 4 +-
drivers/tty/serial/s3c2440.c | 33 ++----------------------------
drivers/tty/serial/samsung.c | 21 -------------------
5 files changed, 44 insertions(+), 55 deletions(-)
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index f9e6bda..f85853c 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -34,6 +34,7 @@
#include <linux/mutex.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/serial_core.h>
#include <mach/hardware.h>
#include <linux/atomic.h>
@@ -43,6 +44,7 @@
#include <plat/clock.h>
#include <plat/cpu.h>
+#include <plat/regs-serial.h>
/* S3C2440 extended clock support */
@@ -108,6 +110,40 @@ static struct clk s3c2440_clk_ac97 = {
.ctrlbit = S3C2440_CLKCON_CAMERA,
};
+static unsigned long s3c2440_fclk_n_getrate(struct clk *clk)
+{
+ unsigned long ucon0, ucon1, ucon2, divisor;
+
+ /* the fun of calculating the uart divisors on the s3c2440 */
+ ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
+ ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
+ ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
+
+ ucon0 &= S3C2440_UCON0_DIVMASK;
+ ucon1 &= S3C2440_UCON1_DIVMASK;
+ ucon2 &= S3C2440_UCON2_DIVMASK;
+
+ if (ucon0 != 0)
+ divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
+ else if (ucon1 != 0)
+ divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
+ else if (ucon2 != 0)
+ divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
+ else
+ /* manual calims 44, seems to be 9 */
+ divisor = 9;
+
+ return clk_get_rate(clk->parent) / divisor;
+}
+
+static struct clk s3c2440_clk_fclk_n = {
+ .name = "fclk_n",
+ .parent = &clk_f,
+ .ops = &(struct clk_ops) {
+ .get_rate = s3c2440_fclk_n_getrate,
+ },
+};
+
static int s3c2440_clk_add(struct sys_device *sysdev)
{
struct clk *clock_upll;
@@ -126,6 +162,7 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
s3c2440_clk_cam.parent = clock_h;
s3c2440_clk_ac97.parent = clock_p;
s3c2440_clk_cam_upll.parent = clock_upll;
+ s3c24xx_register_clock(&s3c2440_clk_fclk_n);
s3c24xx_register_clock(&s3c2440_clk_ac97);
s3c24xx_register_clock(&s3c2440_clk_cam);
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 27ea950..9528b37 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -69,8 +69,8 @@ static struct map_desc rx1950_iodesc[] __initdata = {
static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = {
[0] = {
- .name = "fclk",
- .divisor = 0x0a,
+ .name = "fclk_n",
+ .divisor = 1,
.min_baud = 0,
.max_baud = 0,
},
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 1472b1a..a88247e 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -70,8 +70,8 @@ static struct map_desc rx3715_iodesc[] __initdata = {
static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
[0] = {
- .name = "fclk",
- .divisor = 0,
+ .name = "fclk_n",
+ .divisor = 1,
.min_baud = 0,
.max_baud = 0,
}
diff --git a/drivers/tty/serial/s3c2440.c b/drivers/tty/serial/s3c2440.c
index 1d0c324..4498828 100644
--- a/drivers/tty/serial/s3c2440.c
+++ b/drivers/tty/serial/s3c2440.c
@@ -39,7 +39,7 @@ static int s3c2440_serial_setsource(struct uart_port *port,
ucon |= S3C2440_UCON_UCLK;
else if (strcmp(clk->name, "pclk") == 0)
ucon |= S3C2440_UCON_PCLK;
- else if (strcmp(clk->name, "fclk") == 0)
+ else if (strcmp(clk->name, "fclk_n") == 0)
ucon |= S3C2440_UCON_FCLK;
else {
printk(KERN_ERR "unknown clock source %s\n", clk->name);
@@ -55,7 +55,6 @@ static int s3c2440_serial_getsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
{
unsigned long ucon = rd_regl(port, S3C2410_UCON);
- unsigned long ucon0, ucon1, ucon2;
switch (ucon & S3C2440_UCON_CLKMASK) {
case S3C2440_UCON_UCLK:
@@ -70,34 +69,8 @@ static int s3c2440_serial_getsource(struct uart_port *port,
break;
case S3C2440_UCON_FCLK:
- /* the fun of calculating the uart divisors on
- * the s3c2440 */
-
- ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
- ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
- ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
-
- printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
-
- ucon0 &= S3C2440_UCON0_DIVMASK;
- ucon1 &= S3C2440_UCON1_DIVMASK;
- ucon2 &= S3C2440_UCON2_DIVMASK;
-
- if (ucon0 != 0) {
- clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
- clk->divisor += 6;
- } else if (ucon1 != 0) {
- clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
- clk->divisor += 21;
- } else if (ucon2 != 0) {
- clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
- clk->divisor += 36;
- } else {
- /* manual calims 44, seems to be 9 */
- clk->divisor = 9;
- }
-
- clk->name = "fclk";
+ clk->divisor = 1;
+ clk->name = "fclk_n";
break;
}
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 51cfb9f..fc242b2 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -649,27 +649,6 @@ static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
if (cfg->clocks_size == 0)
clkp = &tmp_clksrc;
- /* check to see if we're sourcing fclk, and if so we're
- * going to have to update the clock source
- */
-
- if (strcmp(clkp->name, "fclk") == 0) {
- struct s3c24xx_uart_clksrc src;
-
- s3c24xx_serial_getsource(port, &src);
-
- /* check that the port already using fclk, and if
- * not, then re-select fclk
- */
-
- if (strcmp(src.name, clkp->name) == 0) {
- s3c24xx_serial_setsource(port, clkp);
- s3c24xx_serial_getsource(port, &src);
- }
-
- clkp->divisor = src.divisor;
- }
-
s3c24xx_serial_calcbaud(res, port, clkp, baud);
best = res;
resptr = best + 1;
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 1/9] serial: samsung: Keep a copy of the location of platform data in driver's private data
From: Thomas Abraham @ 2011-09-26 19:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317064038-32428-1-git-send-email-thomas.abraham@linaro.org>
Add a pointer to the location of the platform data in the driver's private
data. When instantiated using device tree, pdev->dev->platform_data does not
necessarily point to a valid instance of platform data. The platform data
pointer in the driver's private data could be set to pdev->dev->platform_data
or platform data instance created from device tree.
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
drivers/tty/serial/s5pv210.c | 12 ++++++++++--
drivers/tty/serial/samsung.c | 16 ++++++++++++----
drivers/tty/serial/samsung.h | 4 +++-
3 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/tty/serial/s5pv210.c b/drivers/tty/serial/s5pv210.c
index 8b0b888..03b249e 100644
--- a/drivers/tty/serial/s5pv210.c
+++ b/drivers/tty/serial/s5pv210.c
@@ -28,9 +28,13 @@
static int s5pv210_serial_setsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
{
- struct s3c2410_uartcfg *cfg = port->dev->platform_data;
+ struct s3c24xx_uart_port *ourport;
+ struct s3c2410_uartcfg *cfg;
unsigned long ucon = rd_regl(port, S3C2410_UCON);
+ ourport = container_of(port, struct s3c24xx_uart_port, port);
+ cfg = ourport->cfg;
+
if (cfg->flags & NO_NEED_CHECK_CLKSRC)
return 0;
@@ -51,9 +55,13 @@ static int s5pv210_serial_setsource(struct uart_port *port,
static int s5pv210_serial_getsource(struct uart_port *port,
struct s3c24xx_uart_clksrc *clk)
{
- struct s3c2410_uartcfg *cfg = port->dev->platform_data;
+ struct s3c24xx_uart_port *ourport;
+ struct s3c2410_uartcfg *cfg;
u32 ucon = rd_regl(port, S3C2410_UCON);
+ ourport = container_of(port, struct s3c24xx_uart_port, port);
+ cfg = ourport->cfg;
+
clk->divisor = 1;
if (cfg->flags & NO_NEED_CHECK_CLKSRC)
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index b31f1c3..51cfb9f 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -190,10 +190,13 @@ static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *p
static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
{
+ struct s3c24xx_uart_port *ourport;
+
if (port->dev == NULL)
return NULL;
- return (struct s3c2410_uartcfg *)port->dev->platform_data;
+ ourport = container_of(port, struct s3c24xx_uart_port, port);
+ return ourport->cfg;
}
static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
@@ -1125,7 +1128,7 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
struct platform_device *platdev)
{
struct uart_port *port = &ourport->port;
- struct s3c2410_uartcfg *cfg;
+ struct s3c2410_uartcfg *cfg = platdev->dev.platform_data;
struct resource *res;
int ret;
@@ -1134,11 +1137,16 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
if (platdev == NULL)
return -ENODEV;
- cfg = s3c24xx_dev_to_cfg(&platdev->dev);
-
if (port->mapbase != 0)
return 0;
+ /*
+ * If platform data is supplied, keep a copy of the location of
+ * platform data in the driver's private data.
+ */
+ if (cfg)
+ ourport->cfg = cfg;
+
if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
index 8e87b78..6c9cb9d 100644
--- a/drivers/tty/serial/samsung.h
+++ b/drivers/tty/serial/samsung.h
@@ -48,6 +48,9 @@ struct s3c24xx_uart_port {
struct clk *baudclk;
struct uart_port port;
+ /* reference to platform data */
+ struct s3c2410_uartcfg *cfg;
+
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
#endif
@@ -56,7 +59,6 @@ struct s3c24xx_uart_port {
/* conversion functions */
#define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
-#define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
/* register access controls */
--
1.6.6.rc2
^ permalink raw reply related
* serial: samsung: add clkdev based clock lookup and device tree support
From: Thomas Abraham @ 2011-09-26 19:07 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds clkdev based clock lookup support and device tree based
discovery for Samsung uart controller driver. Passing of clock names in
platform data is removed.
In the process of adding these features, other changes have also been made
that merges all the SoC specfic extensions into the parent driver.
This patch has been tested with a following addtional macro suggested by
Russell King (<rmk+kernel@arm.linux.org.uk>) but this macro is not
included in this patch nor is it available in any tree yet. There is a
seperate work going on to prepare a patch series that consolidates
the macros used to instantiate a 'struct clk_lookup'. This patchset
would use that work when it is submitted.
diff --git a/include/linux/clkdev.h b/include/linux/clkdev.h
index 457bcb0..13ffbb8 100644
--- a/include/linux/clkdev.h
+++ b/include/linux/clkdev.h
@@ -24,6 +24,13 @@ struct clk_lookup {
struct clk *clk;
};
+#define CLKDEV_INIT(dev, con, ck) \
+ { \
+ .dev_id = dev, \
+ .con_id = con, \
+ .clk = ck, \
+ }
+
struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
const char *dev_fmt, ...);
This patchset is based on the following tree
https://github.com/kgene/linux-samsung.git branch: for-next
with the following two patches applied
[PATCH] serial: samsung: Add unified interrupt handler for s3c64xx and later SoC's
[PATCH] ARM: SAMSUNG: Remove uart irq handling from plaform code
and tested on the following boards.
SMDK2440, SMDK2416, SMDK6410, SMDK6440, SMDK6450, SMDKC100, SMDKV210, SMDKV310.
Thomas Abraham (9):
serial: samsung: Keep a copy of the location of platform data in driver's private data
serial: samsung: move handling of fclk/n clock to platform code
serial: samsung: switch to clkdev based clock lookup
serial: samsung: remove struct 's3c24xx_uart_clksrc' and all uses of it
serial: samsung: remove all uses of get_clksrc and set_clksrc
arm: samsung: register uart clocks to clock lookup list
serial: samsung: merge all SoC specific port reset functions
serial: samsung: merge probe() function from all SoC specific extensions
serial: samsung: add device tree support
arch/arm/mach-exynos4/clock.c | 106 +++--
arch/arm/mach-exynos4/init.c | 21 +-
arch/arm/mach-s3c2410/mach-bast.c | 22 -
arch/arm/mach-s3c2410/mach-vr1000.c | 24 -
arch/arm/mach-s3c2410/s3c2410.c | 6 +
arch/arm/mach-s3c2412/clock.c | 7 +
arch/arm/mach-s3c2440/clock.c | 44 ++
arch/arm/mach-s3c2440/mach-anubis.c | 22 +-
arch/arm/mach-s3c2440/mach-at2440evb.c | 22 +-
arch/arm/mach-s3c2440/mach-osiris.c | 24 +-
arch/arm/mach-s3c2440/mach-rx1950.c | 18 +-
arch/arm/mach-s3c2440/mach-rx3715.c | 19 +-
arch/arm/mach-s3c64xx/clock.c | 37 +-
arch/arm/mach-s5p64x0/clock-s5p6440.c | 32 +-
arch/arm/mach-s5p64x0/clock-s5p6450.c | 32 +-
arch/arm/mach-s5p64x0/init.c | 31 -
arch/arm/mach-s5pc100/clock.c | 33 +-
arch/arm/mach-s5pv210/clock.c | 107 +++--
arch/arm/mach-s5pv210/init.c | 19 -
arch/arm/plat-s3c24xx/s3c2443-clock.c | 22 +-
arch/arm/plat-samsung/include/plat/regs-serial.h | 45 +-
drivers/tty/serial/Kconfig | 45 +--
drivers/tty/serial/Makefile | 5 -
drivers/tty/serial/s3c2410.c | 115 ----
drivers/tty/serial/s3c2412.c | 149 -----
drivers/tty/serial/s3c2440.c | 178 ------
drivers/tty/serial/s3c6400.c | 149 -----
drivers/tty/serial/s5pv210.c | 158 ------
drivers/tty/serial/samsung.c | 639 +++++++++++++---------
drivers/tty/serial/samsung.h | 32 +-
30 files changed, 737 insertions(+), 1426 deletions(-)
delete mode 100644 drivers/tty/serial/s3c2410.c
delete mode 100644 drivers/tty/serial/s3c2412.c
delete mode 100644 drivers/tty/serial/s3c2440.c
delete mode 100644 drivers/tty/serial/s3c6400.c
delete mode 100644 drivers/tty/serial/s5pv210.c
^ permalink raw reply related
* [PATCH v2 1/3] ARM: imx: Add imx cpuidle driver
From: Rob Lee @ 2011-09-26 18:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMXH7KEGyb+nu0ZbvwxFHe8+BZHp5qko_+goFNSxS3DxEoVBhg@mail.gmail.com>
On 25 September 2011 22:54, Rob Lee <rob.lee@linaro.org> wrote:
> Hello Russell,
>
> On 16 September 2011 16:36, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
>> On Fri, Sep 16, 2011 at 12:27:48PM -0500, Robert Lee wrote:
>>> Introduce a new cpuidle driver which provides the common cpuidle
>>> functionality necessary for any imx soc cpuidle implementation.
>>
>> I think its probably about time we said no to this duplication of CPU
>> idle infrastructure. ?There seems to be a common pattern appearing
>> through all SoCs - they're all doing this:
>>
>>> +static int imx_enter_idle(struct cpuidle_device *dev,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct cpuidle_state *state)
>>> +{
>>> + ? ? struct timeval before, after;
>>> + ? ? int idle_time;
>>> +
>>> + ? ? local_irq_disable();
>>> + ? ? local_fiq_disable();
>>> +
>>> + ? ? do_gettimeofday(&before);
>>> +
>>> + ? ? mach_cpuidle(dev, state);
>>> +
>>> + ? ? do_gettimeofday(&after);
>>> +
>>> + ? ? local_fiq_enable();
>>> + ? ? local_irq_enable();
>>> +
>>> + ? ? idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
>>> + ? ? ? ? ? ? (after.tv_usec - before.tv_usec);
>>> +
>>> + ? ? return idle_time;
>>> +}
>>
>
> If I understand you correctly, it sounds like you are suggesting
> adding cpuidle initialization functionality that is common for all ARM.
> Did you mean just the above function or also the functionality found
> in imx_cpuidle_init and imx_cpuidle_dev_init? ?For this common
> ARM functionality, would a cpuidle.c file in arch/arm/common/ be the
> right location?
After looking at this further today, it appears that there is precedence
for putting a cpuidle driver common to a particular cpu
architecture in drivers/idle. So perhaps a new file "arm_idle.c" that
has common cpuidle functionality could be added to that location.
>
>> in some form, where 'do_gettimeofday' might be ktime_get() or
>> getnstimeofday(). ?If we can standardize on which of the many time
>> functions can be used (which would be a definite plus) we should move
>> this out to common code.
>
> Looking into the time keeping functionality more, of the time functions
> you mentioned I think that ktime_get is preferable as its result it effectively
> a monotonic time that won't be changed with calls to do_settimeofday
> unlike the other two functions whose use of xtime only could result in
> an error in the reported time difference on SMP systems.
>
>>
>> Maybe also the initialization code could be standardized and improved
>> too - for instance, what if you boot with maxcpus=1 on a platform
>> supporting 2 CPUs, and you bring CPU1 online from userspace? ?When
>> these CPU idle initialization functions are called, only one CPU will
>> be online, and as they use 'for_each_cpu(cpu_id, cpu_online_mask)'
>> CPU1 will be missing the cpu idle init.
>>
>
^ permalink raw reply
* [PATCH-V3 2/4] arm:omap:am33xx: Update common OMAP machine specific sources
From: Kevin Hilman @ 2011-09-26 18:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316529142-27564-3-git-send-email-hvaibhav@ti.com>
<hvaibhav@ti.com> writes:
> From: Afzal Mohammed <afzal@ti.com>
>
> This patch updates the common machine specific source files for
> support for AM33XX/AM335x with cpu type, macros for identification of
> AM33XX/AM335X device.
>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
[...]
> @@ -3576,7 +3579,8 @@ int __init omap3xxx_clk_init(void)
> * Lock DPLL5 -- here only until other device init code can
> * handle this
> */
> - if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
> + if (!cpu_is_ti816x() && !cpu_is_am33xx() &&
> + (omap_rev() >= OMAP3430_REV_ES2_0))
> omap3_clk_lock_dpll5();
This is getting ugly.
Instead of continuing to expand this if-list, I think it's time for a
new feature-flag for whether or not an SoC has DPLL5 instead.
Kevin
^ permalink raw reply
* [PATCH v2 4/7] clk: Add simple gated clock
From: Jamie Iles @ 2011-09-26 18:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E80C564.3050004@gmail.com>
Hi Rob,
On Mon, Sep 26, 2011 at 01:33:08PM -0500, Rob Herring wrote:
> Mike,
>
> On 09/22/2011 05:26 PM, Mike Turquette wrote:
> > From: Jeremy Kerr <jeremy.kerr@canonical.com>
> >
> > Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com>
> > Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
> > Signed-off-by: Jamie Iles <jamie@jamieiles.com>
> > Signed-off-by: Mike Turquette <mturquette@ti.com>
> > ---
> > Changes since v1:
> > Add copyright header
> > Fold in Jamie's patch for set-to-disable clks
> > Use BIT macro instead of shift
> >
> > drivers/clk/Kconfig | 4 ++
> > drivers/clk/Makefile | 1 +
> > drivers/clk/clk-gate.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++++
> > include/linux/clk.h | 13 ++++++++
> > 4 files changed, 96 insertions(+), 0 deletions(-)
> > create mode 100644 drivers/clk/clk-gate.c
> >
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index d8313d7..a78967c 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -12,3 +12,7 @@ config GENERIC_CLK
> > config GENERIC_CLK_FIXED
> > bool
> > depends on GENERIC_CLK
> > +
> > +config GENERIC_CLK_GATE
> > + bool
> > + depends on GENERIC_CLK
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index 9a3325a..d186446 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -2,3 +2,4 @@
> > obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
> > obj-$(CONFIG_GENERIC_CLK) += clk.o
> > obj-$(CONFIG_GENERIC_CLK_FIXED) += clk-fixed.o
> > +obj-$(CONFIG_GENERIC_CLK_GATE) += clk-gate.o
> > diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> > new file mode 100644
> > index 0000000..a1d8e79
> > --- /dev/null
> > +++ b/drivers/clk/clk-gate.c
> > @@ -0,0 +1,78 @@
> > +/*
> > + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * Simple clk gate implementation
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/module.h>
> > +#include <asm/io.h>
>
> use linux/io.h
>
> > +
> > +#define to_clk_gate(clk) container_of(clk, struct clk_gate, hw)
> > +
> > +static unsigned long clk_gate_get_rate(struct clk_hw *clk)
> > +{
> > + return clk_get_rate(clk_get_parent(clk->clk));
> > +}
> > +
> > +static void clk_gate_set_bit(struct clk_hw *clk)
> > +{
> > + struct clk_gate *gate = to_clk_gate(clk);
> > + u32 reg;
> > +
> > + reg = __raw_readl(gate->reg);
> > + reg |= BIT(gate->bit_idx);
> > + __raw_writel(reg, gate->reg);
>
> Don't these read-mod-writes need a spinlock around it?
>
> It's possible to have an enable bits and dividers in the same register.
> If you did a set_rate and while doing an enable/disable, there would be
> a problem. Also, it may be 2 different clocks in the same register, so
> the spinlock needs to be shared and not per clock.
Well the prepare lock will be held here and I believe that would be
sufficient.
> > +}
> > +
> > +static void clk_gate_clear_bit(struct clk_hw *clk)
> > +{
> > + struct clk_gate *gate = to_clk_gate(clk);
> > + u32 reg;
> > +
> > + reg = __raw_readl(gate->reg);
> > + reg &= ~BIT(gate->bit_idx);
> > + __raw_writel(reg, gate->reg);
> > +}
> > +
> > +static int clk_gate_enable_set(struct clk_hw *clk)
> > +{
> > + clk_gate_set_bit(clk);
> > +
> > + return 0;
> > +}
> > +
> > +static void clk_gate_disable_clear(struct clk_hw *clk)
> > +{
> > + clk_gate_clear_bit(clk);
> > +}
> > +
> > +struct clk_hw_ops clk_gate_set_enable_ops = {
>
> const?
Yup.
> > + .recalc_rate = clk_gate_get_rate,
> > + .enable = clk_gate_enable_set,
> > + .disable = clk_gate_disable_clear,
> > +};
> > +EXPORT_SYMBOL_GPL(clk_gate_set_enable_ops);
> > +
> > +static int clk_gate_enable_clear(struct clk_hw *clk)
> > +{
> > + clk_gate_clear_bit(clk);
> > +
> > + return 0;
> > +}
> > +
> > +static void clk_gate_disable_set(struct clk_hw *clk)
> > +{
> > + clk_gate_set_bit(clk);
> > +}
>
> Are these wrapper functions really needed? Just assign set_bit and
> clear_bit functions directly to the ops structs. Only the ops struct
> name is exposed to the user.
I used the wrappers because the .enable method has to return an int, but
the disable needs to return void. It's either that or open code the
set/clear in each.
> > +
> > +struct clk_hw_ops clk_gate_set_disable_ops = {
>
> const?
Yes.
Jamie
^ permalink raw reply
* [PATCH v2 0/7] Initial Calxeda Highbank support
From: Rob Herring @ 2011-09-26 18:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1314841446-11006-1-git-send-email-robherring2@gmail.com>
Arnd,
On 08/31/2011 08:43 PM, Rob Herring wrote:
> From: Rob Herring <rob.herring@calxeda.com>
>
> This adds initial platform support for Calxeda's Highbank ARM SOC including
> SMP, hotplug, and suspend support. One new patch to add empty version of
> l2x0_of_init. Changes for v2 are listed in each patch.
>
> Based on rmk's for-next branch with gpio.h and io.h clean-ups plus previously
> posted GIC devicetree binding support. The GIC patches are here:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2011-August/060570.html
> http://lists.infradead.org/pipermail/linux-arm-kernel/2011-August/060790.html
> http://lists.infradead.org/pipermail/linux-arm-kernel/2011-August/062735.html
>
> Rob
>
> Martin Bogomolni (1):
> ARM: highbank: Add cpu hotplug support
>
> Rob Herring (6):
> ARM: l2x0: add empty l2x0_of_init
> ARM: highbank: add devicetree source
> ARM: add Highbank core platform support
> MAINTAINERS: add Calxeda Highbank ARM platform
> ARM: highbank: add SMP support
> ARM: highbank: add suspend support
>
> Documentation/devicetree/bindings/arm/calxeda.txt | 8 +
> MAINTAINERS | 6 +
> arch/arm/Kconfig | 18 ++-
> arch/arm/Makefile | 1 +
> arch/arm/boot/dts/highbank.dts | 224 +++++++++++++++++++++
> arch/arm/include/asm/hardware/cache-l2x0.h | 7 +
> arch/arm/mach-highbank/Makefile | 6 +
> arch/arm/mach-highbank/Makefile.boot | 1 +
> arch/arm/mach-highbank/clock.c | 62 ++++++
> arch/arm/mach-highbank/core.h | 9 +
> arch/arm/mach-highbank/highbank.c | 150 ++++++++++++++
> arch/arm/mach-highbank/hotplug.c | 56 +++++
> arch/arm/mach-highbank/include/mach/debug-macro.S | 19 ++
> arch/arm/mach-highbank/include/mach/entry-macro.S | 7 +
> arch/arm/mach-highbank/include/mach/gpio.h | 1 +
> arch/arm/mach-highbank/include/mach/io.h | 7 +
> arch/arm/mach-highbank/include/mach/irqs.h | 6 +
> arch/arm/mach-highbank/include/mach/memory.h | 1 +
> arch/arm/mach-highbank/include/mach/system.h | 26 +++
> arch/arm/mach-highbank/include/mach/timex.h | 6 +
> arch/arm/mach-highbank/include/mach/uncompress.h | 9 +
> arch/arm/mach-highbank/include/mach/vmalloc.h | 6 +
> arch/arm/mach-highbank/lluart.c | 34 +++
> arch/arm/mach-highbank/localtimer.c | 38 ++++
> arch/arm/mach-highbank/platsmp.c | 78 +++++++
> arch/arm/mach-highbank/pm.c | 55 +++++
> arch/arm/mach-highbank/sysregs.h | 52 +++++
> arch/arm/mach-highbank/system.c | 33 +++
> arch/arm/mm/Kconfig | 2 +-
> 29 files changed, 926 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt
> create mode 100644 arch/arm/boot/dts/highbank.dts
> create mode 100644 arch/arm/mach-highbank/Makefile
> create mode 100644 arch/arm/mach-highbank/Makefile.boot
> create mode 100644 arch/arm/mach-highbank/clock.c
> create mode 100644 arch/arm/mach-highbank/core.h
> create mode 100644 arch/arm/mach-highbank/highbank.c
> create mode 100644 arch/arm/mach-highbank/hotplug.c
> create mode 100644 arch/arm/mach-highbank/include/mach/debug-macro.S
> create mode 100644 arch/arm/mach-highbank/include/mach/entry-macro.S
> create mode 100644 arch/arm/mach-highbank/include/mach/gpio.h
> create mode 100644 arch/arm/mach-highbank/include/mach/io.h
> create mode 100644 arch/arm/mach-highbank/include/mach/irqs.h
> create mode 100644 arch/arm/mach-highbank/include/mach/memory.h
> create mode 100644 arch/arm/mach-highbank/include/mach/system.h
> create mode 100644 arch/arm/mach-highbank/include/mach/timex.h
> create mode 100644 arch/arm/mach-highbank/include/mach/uncompress.h
> create mode 100644 arch/arm/mach-highbank/include/mach/vmalloc.h
> create mode 100644 arch/arm/mach-highbank/lluart.c
> create mode 100644 arch/arm/mach-highbank/localtimer.c
> create mode 100644 arch/arm/mach-highbank/platsmp.c
> create mode 100644 arch/arm/mach-highbank/pm.c
> create mode 100644 arch/arm/mach-highbank/sysregs.h
> create mode 100644 arch/arm/mach-highbank/system.c
>
Any comments on v2?
The GIC binding series seems to be firming up. As myself and several
others are dependent on it, I was planning to send both through arm-soc
tree as 2 pulls. I also have some dependencies on rmk's tree with l2x0
DT support and mach header clean-ups.
Rob
^ permalink raw reply
* [PATCH v7 00/26] gpio/omap: driver cleanup and fixes
From: Kevin Hilman @ 2011-09-26 18:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAC83ZvLfCOjKja1rZ6GB4bmn_KrcjitTJZJsa5jy01QVj2OXXw@mail.gmail.com>
"DebBarma, Tarun Kanti" <tarun.kanti@ti.com> writes:
> Santosh, Kevin,
>
> [...]
>>>> After that, pm_runtime_put_sync() is called, which will trigger the
>>>> driver's ->runtime_suspend callback. ?The ->runtime_suspend() callback
>>>> checks bank->mod_usage as well, and if zero, doesn't do anything
>>>> (notably, it doesn't disable debounce clocks.)
>>> I need some clarification in reproducing/testing the fix on OMAP3430SDP.
>>> The first thing I am trying to verify is the code flow of suspend.
>>>
>>> 1) With no debounce clock enabled, when I enable UART timeouts, I
>>> automatically see
>>> system going to retention. That is I don't have to type echo mem >
>>> /sys/power/state
>>> echo 5 > /sys/devices/platform/omap/omap_uart.0/sleep_timeout
>>> echo 5 > /sys/devices/platform/omap/omap_uart.1/sleep_timeout
>>> echo 5 > /sys/devices/platform/omap/omap_uart.2/sleep_timeout
>>>
>>> 2) I am do not see the print in omap_gpio_suspend/resume(), but I see
>>> the print in
>>> *_prepare_for_idle()/*_resume_after_idle().
>>>
>> Hmmm,
>>
>> This is mostly happening because you are missing a below
>> fix from Kevin in the branch you are testing with.
>>
>> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg54927.html
>> {OMAP: omap_device: fix !CONFIG_SUSPEND case in _noirq handlers}
>>
>> If you rebase, your branch against 3.1-rc6, you should already
>> have this fix. Commit {126caf1376e7}
> Yes, this patch was missing in Kevin's branch and was
> causing the suspend issue.
>
> As pointed out by Kevin, debounce clock was not getting disabled.
> In my testing I was somehow grepping CORE power domain instead
> of PER power domain and hence missed it. The fix for the debounce
> clock issue is at the end of the email.
>
> - Have re-based the for_3.2/gpio-cleanup branch against 3.1-rc6.
Not needed. Just merge with v3.1-rc6 when testing.
> - Dropped [PATCH 26/26] gpio/omap: add dbclk aliases for all gpio modules
> as suggested by Kevin since it's already taken care by hwmod.
good
> - Added the debounce clock fix in the end.
Thanks. Glad you found and fixed it.
Rather than add this patch as a fix at the end, I prefer if the problem
is fixed in the original patches that added/created the problem.
Kevin
> With above, PER is hitting low power state in Suspend and Idle path.
>
> Have pushed a branch at below URL with mentioned changes.
> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> for_3.2/kevin/gpio-cleanup
>
> Regards,
> Tarun
>
> From 5d9a97197ea5426fc79b7a47dd0fd9c6b6ebbbba Mon Sep 17 00:00:00 2001
> From: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> Date: Sat, 24 Sep 2011 13:32:32 +0530
> Subject: [PATCH] gpio/omap: fix debounce clock handling
>
> GPIO debounce clock can gate the PER power domain transition
> and needs to be disabled in GPIO driver suspend.
>
> The debounce clock is not getting disabled in runtime_suspend
> callback because of an un-necessary bank->mod_usage check.
> In omap_gpio_suspend/resume too, there is no need to do
> any operation if the gpio bank is not used.
>
> Remove the un-necessary bank->mod_usage check from
> suspend callbacks.
>
> Thanks to Kevin Hilman for pointing out this issue.
>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> Cc: Kevin Hilman <khilman@ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> drivers/gpio/gpio-omap.c | 12 ++++++------
> 1 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index c597303..349e774 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -1107,6 +1107,9 @@ static int omap_gpio_suspend(struct device *dev)
> void __iomem *wake_status;
> unsigned long flags;
>
> + if (!bank->mod_usage || !bank->loses_context)
> + return 0;
> +
> if (!bank->regs->wkup_en || !bank->suspend_wakeup)
> return 0;
>
> @@ -1128,6 +1131,9 @@ static int omap_gpio_resume(struct device *dev)
> void __iomem *base = bank->base;
> unsigned long flags;
>
> + if (!bank->mod_usage || !bank->loses_context)
> + return 0;
> +
> if (!bank->regs->wkup_en || !bank->saved_wakeup)
> return 0;
>
> @@ -1151,9 +1157,6 @@ static int omap_gpio_runtime_suspend(struct device *dev)
> int j;
> unsigned long flags;
>
> - if (!bank->mod_usage)
> - return 0;
> -
> spin_lock_irqsave(&bank->lock, flags);
> /*
> * If going to OFF, remove triggering for all
> @@ -1199,9 +1202,6 @@ static int omap_gpio_runtime_resume(struct device *dev)
> int j;
> unsigned long flags;
>
> - if (!bank->mod_usage)
> - return 0;
> -
> spin_lock_irqsave(&bank->lock, flags);
> for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
> clk_enable(bank->dbck);
^ permalink raw reply
* [PATCH v16 00/12] OMAP: dmtimer: adaptation to platform_driver
From: DebBarma, Tarun Kanti @ 2011-09-26 18:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110926172527.GF6324@atomide.com>
On Mon, Sep 26, 2011 at 10:55 PM, Tony Lindgren <tony@atomide.com> wrote:
> * DebBarma, Tarun Kanti <tarun.kanti@ti.com> [110923 01:54]:
>> Hi Tony,
>> [...]
>> >> I've applied these into dmtimer branch with some changes to simplify
>> >> things further. I've also merged it into linux-omap master branch
>> >> for further testing.
>> >>
>> >> I'll reply to your patches with the changes I've done. Care give the
>> >> dmtimer branch a try and see if I've missed something?
>> > Sure, I will go through the changes and do testing on it.
>> Please find the missing/correction in the patch below.
>> You can include them as part of patch 9.
>
> Thanks I've updated your original patch with that. The missing part
> I probably accidentally dropped while rebasing, sorry about that.
Ok, no problem.
--
Tarun
>
> Regards,
>
> Tony
>
^ permalink raw reply
* [PATCH v2 4/7] clk: Add simple gated clock
From: Rob Herring @ 2011-09-26 18:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316730422-20027-5-git-send-email-mturquette@ti.com>
Mike,
On 09/22/2011 05:26 PM, Mike Turquette wrote:
> From: Jeremy Kerr <jeremy.kerr@canonical.com>
>
> Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com>
> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
> Signed-off-by: Mike Turquette <mturquette@ti.com>
> ---
> Changes since v1:
> Add copyright header
> Fold in Jamie's patch for set-to-disable clks
> Use BIT macro instead of shift
>
> drivers/clk/Kconfig | 4 ++
> drivers/clk/Makefile | 1 +
> drivers/clk/clk-gate.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++++
> include/linux/clk.h | 13 ++++++++
> 4 files changed, 96 insertions(+), 0 deletions(-)
> create mode 100644 drivers/clk/clk-gate.c
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index d8313d7..a78967c 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -12,3 +12,7 @@ config GENERIC_CLK
> config GENERIC_CLK_FIXED
> bool
> depends on GENERIC_CLK
> +
> +config GENERIC_CLK_GATE
> + bool
> + depends on GENERIC_CLK
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 9a3325a..d186446 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -2,3 +2,4 @@
> obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
> obj-$(CONFIG_GENERIC_CLK) += clk.o
> obj-$(CONFIG_GENERIC_CLK_FIXED) += clk-fixed.o
> +obj-$(CONFIG_GENERIC_CLK_GATE) += clk-gate.o
> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> new file mode 100644
> index 0000000..a1d8e79
> --- /dev/null
> +++ b/drivers/clk/clk-gate.c
> @@ -0,0 +1,78 @@
> +/*
> + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Simple clk gate implementation
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/module.h>
> +#include <asm/io.h>
use linux/io.h
> +
> +#define to_clk_gate(clk) container_of(clk, struct clk_gate, hw)
> +
> +static unsigned long clk_gate_get_rate(struct clk_hw *clk)
> +{
> + return clk_get_rate(clk_get_parent(clk->clk));
> +}
> +
> +static void clk_gate_set_bit(struct clk_hw *clk)
> +{
> + struct clk_gate *gate = to_clk_gate(clk);
> + u32 reg;
> +
> + reg = __raw_readl(gate->reg);
> + reg |= BIT(gate->bit_idx);
> + __raw_writel(reg, gate->reg);
Don't these read-mod-writes need a spinlock around it?
It's possible to have an enable bits and dividers in the same register.
If you did a set_rate and while doing an enable/disable, there would be
a problem. Also, it may be 2 different clocks in the same register, so
the spinlock needs to be shared and not per clock.
> +}
> +
> +static void clk_gate_clear_bit(struct clk_hw *clk)
> +{
> + struct clk_gate *gate = to_clk_gate(clk);
> + u32 reg;
> +
> + reg = __raw_readl(gate->reg);
> + reg &= ~BIT(gate->bit_idx);
> + __raw_writel(reg, gate->reg);
> +}
> +
> +static int clk_gate_enable_set(struct clk_hw *clk)
> +{
> + clk_gate_set_bit(clk);
> +
> + return 0;
> +}
> +
> +static void clk_gate_disable_clear(struct clk_hw *clk)
> +{
> + clk_gate_clear_bit(clk);
> +}
> +
> +struct clk_hw_ops clk_gate_set_enable_ops = {
const?
> + .recalc_rate = clk_gate_get_rate,
> + .enable = clk_gate_enable_set,
> + .disable = clk_gate_disable_clear,
> +};
> +EXPORT_SYMBOL_GPL(clk_gate_set_enable_ops);
> +
> +static int clk_gate_enable_clear(struct clk_hw *clk)
> +{
> + clk_gate_clear_bit(clk);
> +
> + return 0;
> +}
> +
> +static void clk_gate_disable_set(struct clk_hw *clk)
> +{
> + clk_gate_set_bit(clk);
> +}
Are these wrapper functions really needed? Just assign set_bit and
clear_bit functions directly to the ops structs. Only the ops struct
name is exposed to the user.
> +
> +struct clk_hw_ops clk_gate_set_disable_ops = {
const?
Rob
^ permalink raw reply
* [PATCHv3 2/4] picoxcell: add the DTS for pc3x2 and pc3x3 devices
From: Jamie Iles @ 2011-09-26 18:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E80BEA3.1030803@gmail.com>
Hi Rob,
Thanks for taking a look at this! A few comments inline.
Jamie
On Mon, Sep 26, 2011 at 01:04:19PM -0500, Rob Herring wrote:
> Jamie,
>
> On 09/26/2011 10:24 AM, Jamie Iles wrote:
> > This describes the basic hierarchy of picoxcell pc3x3 devices including
> > clocks and bus interconnect. Some onchip devices are currently omitted
> > as there haven't been bindings created for them.
> >
> > v2: - change timer compatible strings to be more soc specific
> > - split vic node into 2 devices
> >
> > Signed-off-by: Jamie Iles <jamie@jamieiles.com>
> > ---
> > arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 249 ++++++++++++++++++++++
> > arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 365 ++++++++++++++++++++++++++++++++
> > 2 files changed, 614 insertions(+), 0 deletions(-)
> > create mode 100644 arch/arm/boot/dts/picoxcell-pc3x2.dtsi
> > create mode 100644 arch/arm/boot/dts/picoxcell-pc3x3.dtsi
> >
> > diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
> > new file mode 100644
> > index 0000000..f0a8c20
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
> > @@ -0,0 +1,249 @@
> > +/*
> > + * Copyright (C) 2011 Picochip, Jamie Iles
> > + *
> > + * This software is licensed under the terms of the GNU General Public
> > + * License version 2, as published by the Free Software Foundation, and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +/include/ "skeleton.dtsi"
> > +/ {
> > + model = "Picochip picoXcell PC3X2";
> > + compatible = "picochip,pc3x2";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu at 0 {
> > + compatible = "arm,1176jz-s";
> > + clock-frequency = <400000000>;
> > + reg = <0>;
> > + d-cache-line-size = <32>;
> > + d-cache-size = <32768>;
> > + i-cache-line-size = <32>;
> > + i-cache-size = <32768>;
> > + };
> > + };
> > +
> > + clocks {
>
> I would hold off on clock bindings. Grant expressed at LPC the desire to
> re-work the binding.
OK, that's fine with me.
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + pclk: clock at 0 {
> > + compatible = "fixed-clock";
> > + clock-outputs = "bus", "pclk";
> > + clock-frequency = <200000000>;
> > + ref-clock = <&ref_clk>, "ref";
> > + };
> > + };
> > +
> > + paxi {
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0x80000000 0x400000>;
> > +
> > + emac: gem at 30000 {
>
> ethernet is the preferred generic name here. See section 2.2.2 of ePAPR.
>
> So it would be "emac: ethernet at 30000"
I'll take a closer look at that document, I don't think I've spent much
time with it.
> > + compatible = "cadence,gem";
> > + reg = <0x30000 0x10000>;
> > + interrupts = <31>;
> > + };
> > +
> > + dmac1: dmac at 40000 {
> > + compatible = "snps,dw-dmac";
> > + reg = <0x40000 0x10000>;
> > + interrupts = <25>;
> > + };
> > +
> > + dmac2: dmac at 50000 {
> > + compatible = "snps,dw-dmac";
> > + reg = <0x50000 0x10000>;
> > + interrupts = <26>;
> > + };
> > +
> > + vic0: interrupt-controller at 60000 {
> > + compatible = "arm,pl192-vic";
> > + interrupt-controller;
> > + reg = <0x60000 0x1000>;
> > + #interrupt-cells = <1>;
>
> No edge/level control/settings for the vic? Needs binding documentation.
No, there's no configuration for the interrupts. The binding is
documented in the picoxcell bindings, but as there isn't a generic
driver yet I thought I'd hold off from doing a separate binding.
> > + };
> > +
> > + vic1: interrupt-controller at 64000 {
> > + compatible = "arm,pl192-vic";
> > + interrupt-controller;
> > + reg = <0x64000 0x1000>;
> > + #interrupt-cells = <1>;
> > + };
> > +
> > + fuse: picoxcell-fuse at 80000 {
> > + compatible = "picoxcell,fuse-pc3x2";
> > + reg = <0x80000 0x10000>;
> > + };
> > +
> > + ssi: picoxcell-spi at 90000 {
> > + compatible = "picoxcell,spi";
> > + reg = <0x90000 0x10000>;
> > + interrupt-parent = <&vic0>;
> > + interrupts = <10>;
> > + };
> > +
> > + ipsec: spacc at 100000 {
> > + compatible = "picochip,spacc-ipsec";
> > + reg = <0x100000 0x10000>;
> > + interrupt-parent = <&vic0>;
> > + interrupts = <24>;
> > + ref-clock = <&pclk>, "ref";
> > + };
> > +
> > + srtp: spacc at 140000 {
> > + compatible = "picochip,spacc-srtp";
> > + reg = <0x140000 0x10000>;
> > + interrupt-parent = <&vic0>;
> > + interrupts = <23>;
> > + };
> > +
> > + l2_engine: spacc at 180000 {
> > + compatible = "picochip,spacc-l2";
> > + reg = <0x180000 0x10000>;
> > + interrupt-parent = <&vic0>;
> > + interrupts = <22>;
> > + ref-clock = <&pclk>, "ref";
> > + };
> > +
> > + apb {
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0x200000 0x80000>;
> > +
> > + rtc0: rtc at 00000 {
> > + compatible = "picochip,pc3x2-rtc";
> > + clock-freq = <200000000>;
> > + reg = <0x00000 0xf>;
> > + interrupt-parent = <&vic1>;
> > + interrupts = <8>;
> > + };
> > +
> > + timer0: timer at 10000 {
> > + compatible = "picochip,pc3x2-timer";
> > + interrupt-parent = <&vic0>;
> > + interrupts = <4>;
> > + clock-freq = <200000000>;
> > + reg = <0x10000 0x14>;
> > + };
> > +
> > + timer1: timer at 10014 {
> > + compatible = "picochip,pc3x2-timer";
> > + interrupt-parent = <&vic0>;
> > + interrupts = <5>;
> > + clock-freq = <200000000>;
> > + reg = <0x10014 0x14>;
> > + };
> > +
> > + timer2: timer at 10028 {
> > + compatible = "picochip,pc3x2-timer";
> > + interrupt-parent = <&vic0>;
> > + interrupts = <6>;
> > + clock-freq = <200000000>;
> > + reg = <0x10028 0x14>;
> > + };
> > +
> > + timer3: timer at 1003c {
> > + compatible = "picochip,pc3x2-timer";
> > + interrupt-parent = <&vic0>;
> > + interrupts = <7>;
> > + clock-freq = <200000000>;
> > + reg = <0x1003c 0x14>;
> > + };
> > +
> > + gpio: gpio at 20000 {
> > + compatible = "snps,dw-apb-gpio";
> > + reg = <0x20000 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg-io-width = <4>;
> > +
> > + banka: gpio-controller at 0 {
> > + compatible = "snps,dw-apb-gpio-bank";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + gpio-generic,nr-gpio = <8>;
>
> This seems like Linux creeping into device tree.
Yes, I was trying to come up with a fairly generic binding for the
generic-gpio driver. I can remove this for now if you think appropriate
though.
> > +
> > + regoffset-dat = <0x50>;
> > + regoffset-set = <0x00>;
> > + regoffset-dirout = <0x04>;
> > + };
> > +
> > + bankb: gpio-controller at 1 {
> > + compatible = "snps,dw-apb-gpio-bank";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + gpio-generic,nr-gpio = <8>;
> > +
> > + regoffset-dat = <0x54>;
> > + regoffset-set = <0x0c>;
> > + regoffset-dirout = <0x10>;
> > + };
> > + };
> > +
> > + uart0: uart at 30000 {
>
> Preferred name is serial at 30000
OK.
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x30000 0x1000>;
> > + interrupt-parent = <&vic1>;
> > + interrupts = <10>;
> > + clock-frequency = <3686400>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + };
> > +
> > + uart1: uart at 40000 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x40000 0x1000>;
> > + interrupt-parent = <&vic1>;
> > + interrupts = <9>;
> > + clock-frequency = <3686400>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + };
> > +
> > + wdog: watchdog at 50000 {
> > + compatible = "snps,dw-apb-wdg";
> > + reg = <0x50000 0x10000>;
> > + interrupt-parent = <&vic0>;
> > + interrupts = <11>;
> > + bus-clock = <&pclk>, "bus";
> > + };
> > + };
> > + };
> > +
> > + rwid-axi {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "simple-bus";
> > + ranges;
> > +
> > + ebi at 50000000 {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <1>;
> > + ranges = <0 0 0x40000000 0x08000000
> > + 1 0 0x48000000 0x08000000
> > + 2 0 0x50000000 0x08000000
> > + 3 0 0x58000000 0x08000000>;
> > + };
> > +
> > + axi2pico at c0000000 {
> > + compatible = "picochip,axi2pico-pc3x2";
> > + reg = <0xc0000000 0x10000>;
> > + interrupts = <13 14 15 16 17 18 19 20 21>;
> > + };
> > + };
> > +};
> > diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
>
> Mostly same comments apply here. All these bindings need documentation.
I followed prima2 as an example here where the device tree lists all of
the devices but only the register and interrupt resources even if there
aren't full drivers/bindings for them yet. I could remove the unused
peripherals for now if you think appropriate though.
^ permalink raw reply
* [PATCH v2 1/6] OMAP: omap_device: Add omap_hwmod_name_get_dev
From: Kevin Hilman @ 2011-09-26 18:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1314973520-3585-2-git-send-email-b-cousson@ti.com>
Benoit Cousson <b-cousson@ti.com> writes:
> From: Nishanth Menon <nm@ti.com>
>
> An API which translates a standard hwmod name to corresponding
> platform_device is useful for drivers when they need to look up the
> device associated with a hwmod name to map back into the device
> structure pointers. These ideally should be used by drivers in
> mach directory. Using a generic hwmod name like "gpu" instead of
> the actual device name which could change in the future, allows
> us to:
> a) Could in effect help replace apis such as omap2_get_mpuss_device,
> omap2_get_iva_device, omap2_get_l3_device, omap4_get_dsp_device,
> etc..
> b) Scale to more devices rather than be restricted to named functions
> c) Simplify driver's platform_data from passing additional fields
> all doing the same thing with different function pointer names
> just for accessing a different device name.
>
> Provide an omap_hwmod_name_get_dev helper function to convert
> hwmod to device pointer.
> This wrapper provides ability for drivers to convert directly
> from hwmod name back to device pointer without having to handle
> this on a driver by driver basis.
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> [b-cousson at ti.com: Adapt it to the new pdev pointer inside od,
> remove the unneeded helpers, and fold the next patch here]
> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
I replied to wrong version of patch before, here's the comment again:
One other comment on the API here.
This is an omap_hwmod_* API being added to omap_device.h.
Seems like the function name should be something more like:
omap_device_get_by_name(), or probably omap_device_get_by_hwmod_name().
Kevin
^ permalink raw reply
* [PATCH] ARM: tegra: Make earlyprintk choose a UART at runtime.
From: Doug Anderson @ 2011-09-26 18:23 UTC (permalink / raw)
To: linux-arm-kernel
With this change we automatically detect which UART to use for
earlyprintk (and for printing during decompression). The
detection involves coordination with the bootloader: it's expected
that the bootloader will leave a 'D' (for [D]ebug) in the UART
scratchpad register for whichever UART we should use for debugging.
If we don't find any UART that specified, we'll fall back to the
UART that was specified during config time:
CONFIG_TEGRA_DEBUG_UART_XXX.
As a side effect of this change, earlyprintk will no longer fail
if you've specified CONFIG_TEGRA_DEBUG_UART_NONE.
This change is in line with what is documented in the
Documentation/arm/Booting file. In other words: it's expected
that the bootloader initialize one serial port so that the
kernel can detect it.
Other approaches considered:
* Hardcode based on machine ID (as many other ARM boards do).
OK, but nice to not have yet another place to add per-board
code. Better to have bootloader parse device tree and pass us
this info.
* Check for TXE bit (like SA1110). Nice (and doesn't require
a bootloader change), but a little less explicit. Also: if
bootloader (for some reason) uses another UART, it needs to
remember to turn it off before jumping to the kernel or we may
print to it. NOTE: adapting this patch to check TXE is easy
for me to move to if maintainers would prefer it.
* Check for which UART clock is enabled. Similar to TXE
solution, but might be more robust of reads from an unclocked
UART hang the system.
* Communicate from decompression code to assembly with magic
memory area (like OMAP_UART_INFO). Would prefer to avoid for
the downsides described in the OMAP patch that added this,
especially the fact that running without a zImage would (I
think) make earlyprintk fail.
Signed-off-by: Doug Anderson <dianders@chromium.org>
---
arch/arm/mach-tegra/include/mach/debug-macro.S | 155 ++++++++++++++++++++++--
arch/arm/mach-tegra/include/mach/uncompress.h | 50 ++++++--
2 files changed, 181 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
index e0ebe65..8a4190a 100644
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -1,11 +1,12 @@
/*
* arch/arm/mach-tegra/include/mach/debug-macro.S
*
- * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 Google, Inc.
*
* Author:
* Colin Cross <ccross@google.com>
* Erik Gilling <konkers@google.com>
+ * Doug Anderson <dianders@chromium.org>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -18,18 +19,150 @@
*
*/
+#include <linux/serial_reg.h>
+
+#include <asm/memory.h>
+
#include <mach/io.h>
#include <mach/iomap.h>
- .macro addruart, rp, rv
- ldr \rp, =IO_APB_PHYS @ physical
- ldr \rv, =IO_APB_VIRT @ virtual
- orr \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF)
- orr \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF00)
- orr \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF)
- orr \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF00)
- .endm
+#define UART_SHIFT 2
+#define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
+
+#define tegra_uart_v2p(x) ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
+
+ /*
+ * Order matters for this section; code below assumes that
+ * phys is 4 from config and virt is 8 from config.
+ *
+ * By default, we'll start the UART by looking at whatever
+ * was specified by CONFIG_TEGRA_DEBUG_UART_XXX, but on the
+ * first use of addruart we'll search all UARTs for one with
+ * a 'D' in the scratchpad register. If we find one, we'll
+ * use it instead.
+ */
+ .pushsection .data
+tegra_uart_config: .word 0
+tegra_uart_phys: .word IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET
+tegra_uart_virt: .word IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET
+ .popsection
+
+
+ /* Put address of tegra_uart_config into \ra */
+ .macro get_uart_config_addr, ra
+ mrc p15, 0, \ra, c1, c0
+ tst \ra, #1 @ MMU enabled?
+ ldreq \ra, =tegra_uart_v2p(tegra_uart_config) @ not enabled
+ ldrne \ra, =tegra_uart_config @ enabled
+ .endm
+
+ /* Check whether a given UART is the debug UART; sets cond. */
+ .macro check_uart, rio, rtmp, uart_base
+ orr \rtmp, \rio, #(\uart_base & 0xFF)
+ orr \rtmp, \rtmp, #(\uart_base & 0xFF00)
+ ldrb \rtmp, [\rtmp, #(UART_SCR << UART_SHIFT)]
+ cmp \rtmp, #'D'
+ .endm
+
+ /*
+ * Store the given UART in the data section; needs two
+ * temp registers to work with.
+ */
+ .macro store_uart, rx, ry, uart_base
+ get_uart_config_addr \rx
+ ldr \ry, =(IO_APB_PHYS + (\uart_base & 0xFFFF))
+ str \ry, [\rx, #4]
+ ldr \ry, =(IO_APB_VIRT + (\uart_base & 0xFFFF))
+ str \ry, [\rx, #8]
+ .endm
+
+
+ /*
+ * Get phys and virt addr of the debug UART. Return results in
+ * registers \rp and \rv, which are the only two registers
+ * we get to work with. Code is loosely based on OMAP
+ * version of debug-macro.S.
+ */
+ .macro addruart, rp, rv
+
+10: get_uart_config_addr \rp
+ ldr \rv, [\rp, #0]
+ cmp \rv, #1 @ is port configured?
+ beq 99f @ ...yes? jump to end
+
+ mov \rv, #1 @ store so next time we are
+ str \rv, [\rp, #0] @ consider oursevles configured
+
+ /* Use \rp to hold IO base address while we search for 'D' */
+ mrc p15, 0, \rp, c1, c0
+ tst \rp, #1 @ MMU enabled?
+ ldreq \rp, =IO_APB_PHYS @ MMU not enabled
+ ldrne \rp, =IO_APB_VIRT @ MMU enabled
+
+ /* Check for UARTA */
+ check_uart \rp, \rv, TEGRA_UARTA_BASE
+ bne 21f @ not UARTA
+ store_uart \rp, \rv, TEGRA_UARTA_BASE
+ b 10b
+
+ /* Check for UARTB */
+21: check_uart \rp, \rv, TEGRA_UARTB_BASE
+ bne 22f @ not UARTB
+ store_uart \rp, \rv, TEGRA_UARTB_BASE
+ b 10b
+
+ /* Check for UARTC */
+22: check_uart \rp, \rv, TEGRA_UARTC_BASE
+ bne 23f @ not UARTC
+ store_uart \rp, \rv, TEGRA_UARTC_BASE
+ b 10b
+
+ /* Check for UARTD */
+23: check_uart \rp, \rv, TEGRA_UARTD_BASE
+ bne 24f @ not UARTD
+ store_uart \rp, \rv, TEGRA_UARTD_BASE
+ b 10b
+
+ /* Check for UARTE */
+24: check_uart \rp, \rv, TEGRA_UARTE_BASE
+ bne 10b @ not UARTE; give up
+ store_uart \rp, \rv, TEGRA_UARTE_BASE
+ b 10b
+
+ /* When you jump to here \rp has addr of tegra_uart_config */
+99: ldr \rv, [\rp, #8] @ virt is 8 bytes after config
+ ldr \rp, [\rp, #4] @ phys is 4 bytes after config
+ .endm
+
+/*
+ * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
+ * check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case.
+ * We use the fact that all 5 valid UARTS addresses all have something in the
+ * 2nd-to-lowest byte.
+ */
+ .macro senduart,rd,rx
+ tst \rx, #0x0000ff00
+ strneb \rd, [\rx, #UART_TX << UART_SHIFT]
+1001:
+ .endm
-#define UART_SHIFT 2
-#include <asm/hardware/debug-8250.S>
+ .macro busyuart,rd,rx
+ tst \rx, #0x0000ff00
+ beq 1002f
+1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
+ and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ bne 1001b
+1002:
+ .endm
+ .macro waituart,rd,rx
+#ifdef FLOW_CONTROL
+ tst \rx, #0x0000ff00
+ beq 1002f
+1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
+ tst \rd, #UART_MSR_CTS
+ beq 1001b
+1002:
+#endif
+ .endm
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 4e83237..2f776bd 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -1,11 +1,12 @@
/*
* arch/arm/mach-tegra/include/mach/uncompress.h
*
- * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 Google, Inc.
*
* Author:
* Colin Cross <ccross@google.com>
* Erik Gilling <konkers@google.com>
+ * Doug Anderson <dianders@chromium.org>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -21,40 +22,63 @@
#ifndef __MACH_TEGRA_UNCOMPRESS_H
#define __MACH_TEGRA_UNCOMPRESS_H
+#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/serial_reg.h>
#include <mach/iomap.h>
+u32 uart_base;
+
+#define DEBUG_UART_SHIFT 2
+
static void putc(int c)
{
- volatile u8 *uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE;
- int shift = 2;
+ volatile u8 *uart = (volatile u8 *)uart_base;
if (uart == NULL)
return;
- while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
+ while (!(uart[UART_LSR << DEBUG_UART_SHIFT] & UART_LSR_THRE))
barrier();
- uart[UART_TX << shift] = c;
+ uart[UART_TX << DEBUG_UART_SHIFT] = c;
}
static inline void flush(void)
{
}
+/*
+ * Setup before decompression. This is where we do UART selection for
+ * earlyprintk and init the uart_base register.
+ */
static inline void arch_decomp_setup(void)
{
- volatile u8 *uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE;
- int shift = 2;
+ static const u32 uarts[] = {
+ TEGRA_UARTA_BASE,
+ TEGRA_UARTB_BASE,
+ TEGRA_UARTC_BASE,
+ TEGRA_UARTD_BASE,
+ TEGRA_UARTE_BASE,
+ };
+ const u32 num_uarts = ARRAY_SIZE(uarts);
+ u32 i;
- if (uart == NULL)
- return;
+ /*
+ * Look for the first UART that has a 'D' in the scratchpad register,
+ * which should be set by the bootloader to tell us which UART to use
+ * for debugging. If nothing found, we'll fall back to what's
+ * specified in TEGRA_DEBUG_UART_BASE.
+ */
+ uart_base = TEGRA_DEBUG_UART_BASE;
+ for (i = 0; i < num_uarts; i++) {
+ volatile u8 *uart = (volatile u8 *)uarts[i];
- uart[UART_LCR << shift] |= UART_LCR_DLAB;
- uart[UART_DLL << shift] = 0x75;
- uart[UART_DLM << shift] = 0x0;
- uart[UART_LCR << shift] = 3;
+ if (uart[UART_SCR << DEBUG_UART_SHIFT] == 'D') {
+ uart_base = uarts[i];
+ break;
+ }
+ }
}
static inline void arch_decomp_wdog(void)
--
1.7.3.1
^ permalink raw reply related
* [PATCH 1/7] OMAP: PM: omap_device: add omap_hwmod_name_get_odev
From: Kevin Hilman @ 2011-09-26 18:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1314026347-21623-2-git-send-email-b-cousson@ti.com>
On 08/22/2011 08:19 AM, Benoit Cousson wrote:
> From: Nishanth Menon<nm@ti.com>
>
> An API which translates a standard hwmod name to corresponding
> omap_device is useful for drivers when they need to look up the
> device associated with a hwmod name to map back into the device
> structure pointers. These ideally should be used by drivers in
> mach directory. Using a generic hwmod name like "gpu" instead of
> the actual device name which could change in the future, allows
> us to:
> a) Could in effect help replace apis such as omap2_get_mpuss_device,
> omap2_get_iva_device, omap2_get_l3_device, omap4_get_dsp_device,
> etc..
> b) Scale to more devices rather than be restricted to named functions
> c) Simplify driver's platform_data from passing additional fields
> all doing the same thing with different function pointer names
> just for accessing a different device name.
>
> Signed-off-by: Nishanth Menon<nm@ti.com>
> [b-cousson at ti.com: rebased on top of Kevin's changes]
> Signed-off-by: Benoit Cousson<b-cousson@ti.com>
> ---
> arch/arm/plat-omap/include/plat/omap_device.h | 1 +
> arch/arm/plat-omap/omap_device.c | 32 +++++++++++++++++++++++++
> 2 files changed, 33 insertions(+), 0 deletions(-)
One other comment on the API here.
This is an omap_hwmod_* API being added to omap_device.h.
Seems like the function name should be something more like:
omap_device_get_by_name() (or _get_by_hwmod_name() or something.)
Kevin
^ permalink raw reply
* [PATCHv3 2/4] picoxcell: add the DTS for pc3x2 and pc3x3 devices
From: Rob Herring @ 2011-09-26 18:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317050689-16417-3-git-send-email-jamie@jamieiles.com>
Jamie,
On 09/26/2011 10:24 AM, Jamie Iles wrote:
> This describes the basic hierarchy of picoxcell pc3x3 devices including
> clocks and bus interconnect. Some onchip devices are currently omitted
> as there haven't been bindings created for them.
>
> v2: - change timer compatible strings to be more soc specific
> - split vic node into 2 devices
>
> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
> ---
> arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 249 ++++++++++++++++++++++
> arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 365 ++++++++++++++++++++++++++++++++
> 2 files changed, 614 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/boot/dts/picoxcell-pc3x2.dtsi
> create mode 100644 arch/arm/boot/dts/picoxcell-pc3x3.dtsi
>
> diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
> new file mode 100644
> index 0000000..f0a8c20
> --- /dev/null
> +++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
> @@ -0,0 +1,249 @@
> +/*
> + * Copyright (C) 2011 Picochip, Jamie Iles
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +/include/ "skeleton.dtsi"
> +/ {
> + model = "Picochip picoXcell PC3X2";
> + compatible = "picochip,pc3x2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu at 0 {
> + compatible = "arm,1176jz-s";
> + clock-frequency = <400000000>;
> + reg = <0>;
> + d-cache-line-size = <32>;
> + d-cache-size = <32768>;
> + i-cache-line-size = <32>;
> + i-cache-size = <32768>;
> + };
> + };
> +
> + clocks {
I would hold off on clock bindings. Grant expressed at LPC the desire to
re-work the binding.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + pclk: clock at 0 {
> + compatible = "fixed-clock";
> + clock-outputs = "bus", "pclk";
> + clock-frequency = <200000000>;
> + ref-clock = <&ref_clk>, "ref";
> + };
> + };
> +
> + paxi {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x80000000 0x400000>;
> +
> + emac: gem at 30000 {
ethernet is the preferred generic name here. See section 2.2.2 of ePAPR.
So it would be "emac: ethernet at 30000"
> + compatible = "cadence,gem";
> + reg = <0x30000 0x10000>;
> + interrupts = <31>;
> + };
> +
> + dmac1: dmac at 40000 {
> + compatible = "snps,dw-dmac";
> + reg = <0x40000 0x10000>;
> + interrupts = <25>;
> + };
> +
> + dmac2: dmac at 50000 {
> + compatible = "snps,dw-dmac";
> + reg = <0x50000 0x10000>;
> + interrupts = <26>;
> + };
> +
> + vic0: interrupt-controller at 60000 {
> + compatible = "arm,pl192-vic";
> + interrupt-controller;
> + reg = <0x60000 0x1000>;
> + #interrupt-cells = <1>;
No edge/level control/settings for the vic? Needs binding documentation.
> + };
> +
> + vic1: interrupt-controller at 64000 {
> + compatible = "arm,pl192-vic";
> + interrupt-controller;
> + reg = <0x64000 0x1000>;
> + #interrupt-cells = <1>;
> + };
> +
> + fuse: picoxcell-fuse at 80000 {
> + compatible = "picoxcell,fuse-pc3x2";
> + reg = <0x80000 0x10000>;
> + };
> +
> + ssi: picoxcell-spi at 90000 {
> + compatible = "picoxcell,spi";
> + reg = <0x90000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <10>;
> + };
> +
> + ipsec: spacc at 100000 {
> + compatible = "picochip,spacc-ipsec";
> + reg = <0x100000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <24>;
> + ref-clock = <&pclk>, "ref";
> + };
> +
> + srtp: spacc at 140000 {
> + compatible = "picochip,spacc-srtp";
> + reg = <0x140000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <23>;
> + };
> +
> + l2_engine: spacc at 180000 {
> + compatible = "picochip,spacc-l2";
> + reg = <0x180000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <22>;
> + ref-clock = <&pclk>, "ref";
> + };
> +
> + apb {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x200000 0x80000>;
> +
> + rtc0: rtc at 00000 {
> + compatible = "picochip,pc3x2-rtc";
> + clock-freq = <200000000>;
> + reg = <0x00000 0xf>;
> + interrupt-parent = <&vic1>;
> + interrupts = <8>;
> + };
> +
> + timer0: timer at 10000 {
> + compatible = "picochip,pc3x2-timer";
> + interrupt-parent = <&vic0>;
> + interrupts = <4>;
> + clock-freq = <200000000>;
> + reg = <0x10000 0x14>;
> + };
> +
> + timer1: timer at 10014 {
> + compatible = "picochip,pc3x2-timer";
> + interrupt-parent = <&vic0>;
> + interrupts = <5>;
> + clock-freq = <200000000>;
> + reg = <0x10014 0x14>;
> + };
> +
> + timer2: timer at 10028 {
> + compatible = "picochip,pc3x2-timer";
> + interrupt-parent = <&vic0>;
> + interrupts = <6>;
> + clock-freq = <200000000>;
> + reg = <0x10028 0x14>;
> + };
> +
> + timer3: timer at 1003c {
> + compatible = "picochip,pc3x2-timer";
> + interrupt-parent = <&vic0>;
> + interrupts = <7>;
> + clock-freq = <200000000>;
> + reg = <0x1003c 0x14>;
> + };
> +
> + gpio: gpio at 20000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x20000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg-io-width = <4>;
> +
> + banka: gpio-controller at 0 {
> + compatible = "snps,dw-apb-gpio-bank";
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-generic,nr-gpio = <8>;
This seems like Linux creeping into device tree.
> +
> + regoffset-dat = <0x50>;
> + regoffset-set = <0x00>;
> + regoffset-dirout = <0x04>;
> + };
> +
> + bankb: gpio-controller at 1 {
> + compatible = "snps,dw-apb-gpio-bank";
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-generic,nr-gpio = <8>;
> +
> + regoffset-dat = <0x54>;
> + regoffset-set = <0x0c>;
> + regoffset-dirout = <0x10>;
> + };
> + };
> +
> + uart0: uart at 30000 {
Preferred name is serial at 30000
> + compatible = "snps,dw-apb-uart";
> + reg = <0x30000 0x1000>;
> + interrupt-parent = <&vic1>;
> + interrupts = <10>;
> + clock-frequency = <3686400>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + };
> +
> + uart1: uart at 40000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x40000 0x1000>;
> + interrupt-parent = <&vic1>;
> + interrupts = <9>;
> + clock-frequency = <3686400>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + };
> +
> + wdog: watchdog at 50000 {
> + compatible = "snps,dw-apb-wdg";
> + reg = <0x50000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <11>;
> + bus-clock = <&pclk>, "bus";
> + };
> + };
> + };
> +
> + rwid-axi {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + ranges;
> +
> + ebi at 50000000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0 0x40000000 0x08000000
> + 1 0 0x48000000 0x08000000
> + 2 0 0x50000000 0x08000000
> + 3 0 0x58000000 0x08000000>;
> + };
> +
> + axi2pico at c0000000 {
> + compatible = "picochip,axi2pico-pc3x2";
> + reg = <0xc0000000 0x10000>;
> + interrupts = <13 14 15 16 17 18 19 20 21>;
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
Mostly same comments apply here. All these bindings need documentation.
Rob
> new file mode 100644
> index 0000000..daa962d
> --- /dev/null
> +++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
> @@ -0,0 +1,365 @@
> +/*
> + * Copyright (C) 2011 Picochip, Jamie Iles
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +/include/ "skeleton.dtsi"
> +/ {
> + model = "Picochip picoXcell PC3X3";
> + compatible = "picochip,pc3x3";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu at 0 {
> + compatible = "arm,1176jz-s";
> + cpu-clock = <&arm_clk>, "cpu";
> + reg = <0>;
> + d-cache-line-size = <32>;
> + d-cache-size = <32768>;
> + i-cache-line-size = <32>;
> + i-cache-size = <32768>;
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clkgate: clkgate at 800a0048 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x800a0048 4>;
> + compatible = "picochip,pc3x3-clk-gate";
> +
> + tzprot_clk: clock at 0 {
> + compatible = "picochip,pc3x3-gated-clk";
> + clock-outputs = "bus";
> + picochip,clk-disable-bit = <0>;
> + clock-frequency = <200000000>;
> + ref-clock = <&ref_clk>, "ref";
> + };
> +
> + spi_clk: clock at 1 {
> + compatible = "picochip,pc3x3-gated-clk";
> + clock-outputs = "bus";
> + picochip,clk-disable-bit = <1>;
> + clock-frequency = <200000000>;
> + ref-clock = <&ref_clk>, "ref";
> + };
> +
> + dmac0_clk: clock at 2 {
> + compatible = "picochip,pc3x3-gated-clk";
> + clock-outputs = "bus";
> + picochip,clk-disable-bit = <2>;
> + clock-frequency = <200000000>;
> + ref-clock = <&ref_clk>, "ref";
> + };
> +
> + dmac1_clk: clock at 3 {
> + compatible = "picochip,pc3x3-gated-clk";
> + clock-outputs = "bus";
> + picochip,clk-disable-bit = <3>;
> + clock-frequency = <200000000>;
> + ref-clock = <&ref_clk>, "ref";
> + };
> +
> + ebi_clk: clock at 4 {
> + compatible = "picochip,pc3x3-gated-clk";
> + clock-outputs = "bus";
> + picochip,clk-disable-bit = <4>;
> + clock-frequency = <200000000>;
> + ref-clock = <&ref_clk>, "ref";
> + };
> +
> + ipsec_clk: clock at 5 {
> + compatible = "picochip,pc3x3-gated-clk";
> + clock-outputs = "bus";
> + picochip,clk-disable-bit = <5>;
> + clock-frequency = <200000000>;
> + ref-clock = <&ref_clk>, "ref";
> + };
> +
> + l2_clk: clock at 6 {
> + compatible = "picochip,pc3x3-gated-clk";
> + clock-outputs = "bus";
> + picochip,clk-disable-bit = <6>;
> + clock-frequency = <200000000>;
> + ref-clock = <&ref_clk>, "ref";
> + };
> +
> + trng_clk: clock at 7 {
> + compatible = "picochip,pc3x3-gated-clk";
> + clock-outputs = "bus";
> + picochip,clk-disable-bit = <7>;
> + clock-frequency = <200000000>;
> + ref-clock = <&ref_clk>, "ref";
> + };
> +
> + fuse_clk: clock at 8 {
> + compatible = "picochip,pc3x3-gated-clk";
> + clock-outputs = "bus";
> + picochip,clk-disable-bit = <8>;
> + clock-frequency = <200000000>;
> + ref-clock = <&ref_clk>, "ref";
> + };
> +
> + otp_clk: clock at 9 {
> + compatible = "picochip,pc3x3-gated-clk";
> + clock-outputs = "bus";
> + picochip,clk-disable-bit = <9>;
> + clock-frequency = <200000000>;
> + ref-clock = <&ref_clk>, "ref";
> + };
> + };
> +
> + arm_clk: clock at 11 {
> + compatible = "picochip,pc3x3-pll";
> + reg = <0x800a0050 0x8>;
> + picochip,min-freq = <140000000>;
> + picochip,max-freq = <700000000>;
> + ref-clock = <&ref_clk>, "ref";
> + clock-outputs = "cpu";
> + };
> +
> + pclk: clock at 12 {
> + compatible = "fixed-clock";
> + clock-outputs = "bus", "pclk";
> + clock-frequency = <200000000>;
> + ref-clock = <&ref_clk>, "ref";
> + };
> + };
> +
> + paxi {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x80000000 0x400000>;
> +
> + emac: gem at 30000 {
> + compatible = "cadence,gem";
> + reg = <0x30000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <31>;
> + };
> +
> + dmac1: dmac at 40000 {
> + compatible = "snps,dw-dmac";
> + reg = <0x40000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <25>;
> + };
> +
> + dmac2: dmac at 50000 {
> + compatible = "snps,dw-dmac";
> + reg = <0x50000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <26>;
> + };
> +
> + vic0: interrupt-controller at 60000 {
> + compatible = "arm,pl192-vic";
> + interrupt-controller;
> + reg = <0x60000 0x1000>;
> + #interrupt-cells = <1>;
> + };
> +
> + vic1: interrupt-controller at 64000 {
> + compatible = "arm,pl192-vic";
> + interrupt-controller;
> + reg = <0x64000 0x1000>;
> + #interrupt-cells = <1>;
> + };
> +
> + fuse: picoxcell-fuse at 80000 {
> + compatible = "picoxcell,fuse-pc3x3";
> + reg = <0x80000 0x10000>;
> + };
> +
> + ssi: picoxcell-spi at 90000 {
> + compatible = "picoxcell,spi";
> + reg = <0x90000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <10>;
> + };
> +
> + ipsec: spacc at 100000 {
> + compatible = "picochip,spacc-ipsec";
> + reg = <0x100000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <24>;
> + ref-clock = <&ipsec_clk>, "ref";
> + };
> +
> + srtp: spacc at 140000 {
> + compatible = "picochip,spacc-srtp";
> + reg = <0x140000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <23>;
> + };
> +
> + l2_engine: spacc at 180000 {
> + compatible = "picochip,spacc-l2";
> + reg = <0x180000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <22>;
> + ref-clock = <&l2_clk>, "ref";
> + };
> +
> + apb {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x200000 0x80000>;
> +
> + rtc0: rtc at 00000 {
> + compatible = "picochip,pc3x2-rtc";
> + clock-freq = <200000000>;
> + reg = <0x00000 0xf>;
> + interrupt-parent = <&vic0>;
> + interrupts = <8>;
> + };
> +
> + timer0: timer at 10000 {
> + compatible = "picochip,pc3x2-timer";
> + interrupt-parent = <&vic0>;
> + interrupts = <4>;
> + clock-freq = <200000000>;
> + reg = <0x10000 0x14>;
> + };
> +
> + timer1: timer at 10014 {
> + compatible = "picochip,pc3x2-timer";
> + interrupt-parent = <&vic0>;
> + interrupts = <5>;
> + clock-freq = <200000000>;
> + reg = <0x10014 0x14>;
> + };
> +
> + gpio: gpio at 20000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x20000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg-io-width = <4>;
> +
> + banka: gpio-controller at 0 {
> + compatible = "snps,dw-apb-gpio-bank";
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-generic,nr-gpio = <8>;
> +
> + regoffset-dat = <0x50>;
> + regoffset-set = <0x00>;
> + regoffset-dirout = <0x04>;
> + };
> +
> + bankb: gpio-controller at 1 {
> + compatible = "snps,dw-apb-gpio-bank";
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-generic,nr-gpio = <16>;
> +
> + regoffset-dat = <0x54>;
> + regoffset-set = <0x0c>;
> + regoffset-dirout = <0x10>;
> + };
> +
> + bankd: gpio-controller at 2 {
> + compatible = "snps,dw-apb-gpio-bank";
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-generic,nr-gpio = <30>;
> +
> + regoffset-dat = <0x5c>;
> + regoffset-set = <0x24>;
> + regoffset-dirout = <0x28>;
> + };
> + };
> +
> + uart0: uart at 30000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x30000 0x1000>;
> + interrupt-parent = <&vic1>;
> + interrupts = <10>;
> + clock-frequency = <3686400>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + };
> +
> + uart1: uart at 40000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x40000 0x1000>;
> + interrupt-parent = <&vic1>;
> + interrupts = <9>;
> + clock-frequency = <3686400>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + };
> +
> + wdog: watchdog at 50000 {
> + compatible = "snps,dw-apb-wdg";
> + reg = <0x50000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <11>;
> + bus-clock = <&pclk>, "bus";
> + };
> +
> + timer2: timer at 60000 {
> + compatible = "picochip,pc3x2-timer";
> + interrupt-parent = <&vic0>;
> + interrupts = <6>;
> + clock-freq = <200000000>;
> + reg = <0x60000 0x14>;
> + };
> +
> + timer3: timer at 60014 {
> + compatible = "picochip,pc3x2-timer";
> + interrupt-parent = <&vic0>;
> + interrupts = <7>;
> + clock-freq = <200000000>;
> + reg = <0x60014 0x14>;
> + };
> + };
> + };
> +
> + rwid-axi {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + ranges;
> +
> + ebi at 50000000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0 0x40000000 0x08000000
> + 1 0 0x48000000 0x08000000
> + 2 0 0x50000000 0x08000000
> + 3 0 0x58000000 0x08000000>;
> + };
> +
> + axi2pico at c0000000 {
> + compatible = "picochip,axi2pico-pc3x3";
> + reg = <0xc0000000 0x10000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <13 14 15 16 17 18 19 20 21>;
> + };
> +
> + otp at ffff8000 {
> + compatible = "picochip,otp-pc3x3";
> + reg = <0xffff8000 0x8000>;
> + };
> + };
> +};
^ permalink raw reply
* [PATCH] ARM: platform fixups: remove mdesc argument to fixup function
From: Stephen Boyd @ 2011-09-26 17:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1R6kA4-0002vc-HZ@rmk-PC.arm.linux.org.uk>
On 09/22/11 07:22, Russell King - ARM Linux wrote:
> Get rid of the mdesc pointer in the fixup function call. No one uses
> the mdesc pointer, it shouldn't be modified anyway, and we can't wrap
> it, so let's remove it. Updated for 3.1-rc6.
>
> Platform files found by:
>
> $ regexp=$(git grep -h '\.fixup.*=' arch/arm |
> sed 's!.*= *\([^,]*\),* *!\1!' | sort -u |
> tr '\n' '|' | sed 's,|$,,;s,|,\\|,g')
> $ git grep $regexp arch/arm
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
>
When this merges into your for-next branch it breaks 9e775ad (ARM:
7012/1: Set proper TEXT_OFFSET for newer MSMs, 2011-08-12). Here is a
fixup patch on top of your for-next branch. How should we deal with this?
-----8<---[ cut here ]--->8-----
From: Stephen Boyd <sboyd@codeaurora.org>
Subject: [PATCH] msm: boards: Fix fallout from removal of machine_desc in
fixup
After 77821af (ARM: platform fixups: remove mdesc argument to
fixup function, 2010-12-20) the fixup functions introduced in
9e775ad (ARM: 7012/1: Set proper TEXT_OFFSET for newer MSMs,
2011-08-12) cause warnings like:
arch/arm/mach-msm/board-msm8x60.c:85: warning: initialization
from incompatible pointer type
Fix them by removing the machine_desc argument from the fixup
functions.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
arch/arm/mach-msm/board-msm7x30.c | 4 ++--
arch/arm/mach-msm/board-msm8960.c | 4 ++--
arch/arm/mach-msm/board-msm8x60.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 71de506..db81ed5 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -42,8 +42,8 @@
extern struct sys_timer msm_timer;
-static void __init msm7x30_fixup(struct machine_desc *desc, struct tag *tag,
- char **cmdline, struct meminfo *mi)
+static void __init msm7x30_fixup(struct tag *tag, char **cmdline,
+ struct meminfo *mi)
{
for (; tag->hdr.size; tag = tag_next(tag))
if (tag->hdr.tag == ATAG_MEM && tag->u.mem.start == 0x200000) {
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index b04468e..6dc1cbd 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -32,8 +32,8 @@
#include "devices.h"
-static void __init msm8960_fixup(struct machine_desc *desc, struct tag *tag,
- char **cmdline, struct meminfo *mi)
+static void __init msm8960_fixup(struct tag *tag, char **cmdline,
+ struct meminfo *mi)
{
for (; tag->hdr.size; tag = tag_next(tag))
if (tag->hdr.tag == ATAG_MEM &&
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 9221f54..056d9d7 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -30,8 +30,8 @@
#include <mach/board.h>
#include <mach/msm_iomap.h>
-static void __init msm8x60_fixup(struct machine_desc *desc, struct tag *tag,
- char **cmdline, struct meminfo *mi)
+static void __init msm8x60_fixup(struct tag *tag, char **cmdline,
+ struct meminfo *mi)
{
for (; tag->hdr.size; tag = tag_next(tag))
if (tag->hdr.tag == ATAG_MEM &&
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply related
* [PATCH v16 00/12] OMAP: dmtimer: adaptation to platform_driver
From: Tony Lindgren @ 2011-09-26 17:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAC83Zv+Vd4r2Ja-KQo956WigoxV0mhoygJwi0aQjmY6Dw9L2qA@mail.gmail.com>
* DebBarma, Tarun Kanti <tarun.kanti@ti.com> [110923 01:54]:
> Hi Tony,
> [...]
> >> I've applied these into dmtimer branch with some changes to simplify
> >> things further. I've also merged it into linux-omap master branch
> >> for further testing.
> >>
> >> I'll reply to your patches with the changes I've done. Care give the
> >> dmtimer branch a try and see if I've missed something?
> > Sure, I will go through the changes and do testing on it.
> Please find the missing/correction in the patch below.
> You can include them as part of patch 9.
Thanks I've updated your original patch with that. The missing part
I probably accidentally dropped while rebasing, sorry about that.
Regards,
Tony
^ permalink raw reply
* [PATCH v3] mach-integrator: update defconfig
From: Linus Walleij @ 2011-09-26 17:24 UTC (permalink / raw)
To: linux-arm-kernel
Update the Integrator defconfig with some sensible defaults:
- Compile a combined image supporting Integrator/AP and
Integrator/CP, with the core modules CM720, CM920, CM922,
CM926, CM1020, CM1022 and CM1026 in a single image, this
works just fine and gives some nice compilation coverage
- NOHZ (tickless) and HRTIMERS turned on
- Compile using EABI, let's assume recent compilers are used
now (tested using GCC 4.4.1)
- Remove forced 32MiB at command line, the bootloader usually
knows this better, and my U-Boot patches nowadays make that
boot loader pass the correct adjusted value
- Enable the MTD Physmap flash driver, so that the changes done
earlier by Marc Zyngier replacing integrator-flash takes
effect
- Enable the PL030 RTC driver that has not been default-compiled
with any config for a while
This has been tested on the real hardware Integrator AP with
both an ARM920T and ARM926EJ-S core module.
Cc: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- None - by mistake
ChangeLog v2->v3:
- Actually commit and include the intended changes
---
arch/arm/configs/integrator_defconfig | 19 +++++++++++++++----
1 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
index 7196ade..1103f62 100644
--- a/arch/arm/configs/integrator_defconfig
+++ b/arch/arm/configs/integrator_defconfig
@@ -1,5 +1,6 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
+CONFIG_TINY_RCU=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
@@ -8,20 +9,29 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
+CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CPU_ARM720T=y
CONFIG_CPU_ARM920T=y
+CONFIG_CPU_ARM922T=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_ARM1020=y
+CONFIG_CPU_ARM1022=y
+CONFIG_CPU_ARM1026=y
CONFIG_PCI=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
CONFIG_LEDS=y
CONFIG_LEDS_CPU=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp mem=32M"
+CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp"
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -32,7 +42,6 @@ CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_AFS_PARTS=y
CONFIG_MTD_CHAR=y
@@ -40,6 +49,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
@@ -56,6 +66,8 @@ CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_MATROX=y
CONFIG_FB_MATROX_MILLENIUM=y
CONFIG_FB_MATROX_MYSTIQUE=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL030=y
CONFIG_EXT2_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
@@ -68,4 +80,3 @@ CONFIG_NFSD_V3=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_ERRORS=y
--
1.7.6
^ permalink raw reply related
* [RFC PATCH 3/3] ARM: mm: add l2x0 suspend/resume support
From: Lorenzo Pieralisi @ 2011-09-26 17:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110926150645.GN22455@n2100.arm.linux.org.uk>
On Mon, Sep 26, 2011 at 04:06:45PM +0100, Russell King - ARM Linux wrote:
> On Mon, Sep 26, 2011 at 03:32:41PM +0100, Lorenzo Pieralisi wrote:
> > Context is saved once for all at boot time, along with the L2 physical address
> > and cache type.
>
> Why is this assembly code? As Barry's previous patch shows, it's
> entirely possible to save all the state required at init time from
> the existing C code without needing any additional functions.
>
It need not be, but variables that are needed when the MMU is off (L2
phys address and cache type) must be made visible to C code and
initialized there then.
> > The resume hook avoids using the stack since it might be called
> > before the C environment is up and running and fetches data using
> > program counter relative addressing so that it can be run both
> > with MMU on or off to simplify its adoption.
>
> What about parts where the security gets in the way of reinitializing
> the L2 cache?
>
That's a fair point. I think L2 must be initialized by secure code, and
we should not reprogramme it at all.
Having said that, this code only adds support for L2 resume when the
MMU is off to Barry's patch. The security "problem" exists anyway.
I check the control register to see if it is already enabled; all in all
it is just an assembly stub that can be called before or after cpu_resume,
that's it, to support suspend and idle also when L2 is retained and the
boot firmware just jumps back to Linux on power up.
Whether we need an L2 resume function in the kernel or not, I think it is still
a moot point. Let's keep the discussion going.
> > +resume_l210:
> > + ldr r2, [r0], #4 @ just use scratch regs
> > + str r2, [r1, #L2X0_AUX_CTRL]
> > + mov r3, #0
> > + mov r12, #L2X0_LOCKDOWN_WAY_D_BASE
> > + mov r2, r12
> > + str r3, [r1, r2]
> > + add r2, r2, #4
> > + str r3, [r1, r2]
> > + movne r0, #0x1 @ if l210 we are done
> > + strne r0, [r1, #L2X0_CTRL] @ enable L2
> > + movne pc, lr
>
> It's not very obvious where the compare is for this conditional (which is
> at the end of l2x0_resume in the .data section. Also, wouldn't a branch
> to the enable at the end of this function be better and a more obvious
> flow?
>
I added a comment to the function entry for the flags, but it is agreed,
it can be improved; and yes a branch is the way to go.
> > +resume_l310:
> > + add r12, r12, r1
> > + add r12, r12, #L2X0_LOCKDOWN_STRIDE @ start D lock
> > + mov r2, #0
> > + mov r3, #7
> > +unlock:
> > + str r2, [r12, #4] @ I lock
> > + str r2, [r12], #L2X0_LOCKDOWN_STRIDE @ D lock and increment
> > + subs r3, r3, #1
> > + bne unlock
>
> Why not reverse r2 and r3 here? r3 was already set to zero previously.
>
> And given what you're doing, this code could become:
>
> mov r3, #0
> add r12, r1, #L2X0_LOCKDOWN_WAY_D_BASE
> str r3, [r12, #4] @ I lock
> str r3, [r12], #L2X0_LOCKDOWN_STRIDE @ D lock and increment
> bne enable_l2
> resume_l310:
> mov r2, #7
> unlock:
> str r3, [r12, #4] @ I lock
> str r3, [r12], #L2X0_LOCKDOWN_STRIDE @ D lock and increment
> subs r2, r2, #1
> bne unlock
>
>
Definitely, I reshuffled the instructions to adapt the latest changes and I
missed out on this optimization you spotted straight away. Thanks for this.
> > + ldmia r0!, {r2, r3, r12}
> > + str r2, [r1, #L2X0_TAG_LATENCY_CTRL]
> > + str r3, [r1, #L2X0_DATA_LATENCY_CTRL]
> > + str r12, [r1, #L2X0_ADDR_FILTER_START]
> > + ldmia r0!, {r2, r3, r12}
> > + str r2, [r1, #L2X0_ADDR_FILTER_END]
> > + str r3, [r1, #L2X0_DEBUG_CTRL]
> > + str r12, [r1, #L2X0_PREFETCH_CTRL]
> > + ldr r2, [r0]
> > + str r2, [r1, #L2X0_POWER_CTRL]
>
> enable_l2:
>
> > + mov r0, #0x1
> > + str r0, [r1, #L2X0_CTRL] @ enable L2
> > + mov pc, lr
>
Consider it done.
Thanks,
Lorenzo
^ permalink raw reply
* [PATCH 13/13] OMAP2+: board-generic: Remove i2c static init
From: Benoit Cousson @ 2011-09-26 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317055821-20652-1-git-send-email-b-cousson@ti.com>
This mainly reverts the commit that was adding the i2c static init.
Since the i2c and twl nodes are now present, there is no need
for the static initialization anymore.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/board-generic.c | 41 +---------------------------------
1 files changed, 2 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 1186a76..dcbd64c 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -11,7 +11,6 @@
#include <linux/io.h>
#include <linux/of_platform.h>
#include <linux/irqdomain.h>
-#include <linux/i2c/twl.h>
#include <mach/hardware.h>
#include <asm/mach/arch.h>
@@ -19,31 +18,7 @@
#include <plat/board.h>
#include <plat/common.h>
#include <mach/omap4-common.h>
-#include "common-board-devices.h"
-/*
- * XXX: Still needed to boot until the i2c & twl driver is adapted to
- * device-tree
- */
-static struct twl4030_platform_data sdp4430_twldata = {
- .irq_base = TWL6030_IRQ_BASE,
- .irq_end = TWL6030_IRQ_END,
-};
-
-static void __init omap4_i2c_init(void)
-{
- omap4_pmic_init("twl6030", &sdp4430_twldata);
-}
-
-static struct twl4030_platform_data beagle_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
-};
-
-static void __init omap3_i2c_init(void)
-{
- omap3_pmic_init("twl4030", &beagle_twldata);
-}
static struct of_device_id omap_dt_match_table[] __initdata = {
{ .compatible = "simple-bus", },
@@ -69,18 +44,6 @@ static void __init omap_generic_init(void)
of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
}
-static void __init omap4_init(void)
-{
- omap4_i2c_init();
- omap_generic_init();
-}
-
-static void __init omap3_init(void)
-{
- omap3_i2c_init();
- omap_generic_init();
-}
-
#if defined(CONFIG_SOC_OMAP2420)
static const char *omap242x_boards_compat[] __initdata = {
"ti,omap2420",
@@ -126,7 +89,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap3_init_irq,
- .init_machine = omap3_init,
+ .init_machine = omap_generic_init,
.timer = &omap3_timer,
.dt_compat = omap3_boards_compat,
MACHINE_END
@@ -143,7 +106,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
.map_io = omap4_map_io,
.init_early = omap4430_init_early,
.init_irq = gic_init_irq,
- .init_machine = omap4_init,
+ .init_machine = omap_generic_init,
.timer = &omap4_timer,
.dt_compat = omap4_boards_compat,
MACHINE_END
--
1.7.0.4
^ permalink raw reply related
* [PATCH 12/13] arm/dts: omap3-beagle: Add twl4030 and i2c EEPROM
From: Benoit Cousson @ 2011-09-26 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317055821-20652-1-git-send-email-b-cousson@ti.com>
Add required clock frequencies for the i2c client devices existing
on beagle board.
Add the twl4030 basic description with only the twl_rtc module.
Add the EEPROM node.
Based on original patch from Manju:
http://www.spinics.net/lists/linux-omap/msg55831.html
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: G, Manjunath Kondaiah <manjugk@ti.com>
---
arch/arm/boot/dts/omap3-beagle.dts | 38 ++++++++++++++++++++++++++++++++++++
1 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 9486be6..a65f39d 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -27,3 +27,41 @@
reg = <0x80000000 0x20000000>; /* 512 MB */
};
};
+
+&i2c1 {
+ clock-frequency = <2600000>;
+
+ /*
+ * Integrated Power Management Chip
+ */
+ twl at 48 {
+ compatible = "ti,twl4030";
+ reg = <0x48>;
+ interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ twl_rtc {
+ compatible = "ti,twl4030-rtc";
+ interrupts = <11>;
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+
+ /*
+ * Display monitor features are burnt in the EEPROM
+ * as EDID data.
+ */
+ eeprom at 50 {
+ compatible = "ti,eeprom";
+ reg = <0x50>;
+ };
+};
--
1.7.0.4
^ permalink raw reply related
* [PATCH 11/13] arm/dts: omap4-sdp: Add twl6030, i2c3 and i2c4 devices
From: Benoit Cousson @ 2011-09-26 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317055821-20652-1-git-send-email-b-cousson@ti.com>
Update DTS file with required clock frequencies
for the i2c client devices existing on sdp4430.
Add the twl6030 node inside the i2c1 controller node.
This is the minimal support needed to boot OMAP4 boards
without any crash.
The support for all the features included in this MFD will be
added later.
Add the RTC submodule inside the twl node.
Add tmp105 temperature sensor in i2c3
Add bh1780 Ambient Light Sensor in i2c3
Add hmc5843 3-Axis Digital Compass in i2c4
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
---
arch/arm/boot/dts/omap4-sdp.dts | 62 +++++++++++++++++++++++++++++++++++++++
1 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 066e28c..2990841 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -27,3 +27,65 @@
reg = <0x80000000 0x40000000>; /* 1 GB */
};
};
+
+&i2c1 {
+ clock-frequency = <400000>;
+
+ /*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/twl6030.pdf
+ */
+ twl at 48 {
+ compatible = "ti,twl6030";
+ reg = <0x48>;
+ interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ /* twl is a MFD, so it will contain a bunch of sub-ips */
+ twl_rtc {
+ compatible = "ti,twl4030-rtc";
+ interrupts = <11>;
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+
+ /*
+ * Temperature Sensor
+ * http://www.ti.com/lit/ds/symlink/tmp105.pdf
+ */
+ tmp105 at 48 {
+ compatible = "ti,tmp105";
+ reg = <0x48>;
+ };
+
+ /*
+ * Ambient Light Sensor
+ * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf
+ */
+ bh1780 at 29 {
+ compatible = "rohm,bh1780";
+ reg = <0x29>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+
+ /*
+ * 3-Axis Digital Compass
+ * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
+ */
+ hmc5843 at 1e {
+ compatible = "honeywell,hmc5843";
+ reg = <0x1e>;
+ };
+};
--
1.7.0.4
^ permalink raw reply related
* [PATCH 10/13] arm/dts: omap4-panda: Add twl6030 and i2c EEPROM
From: Benoit Cousson @ 2011-09-26 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317055821-20652-1-git-send-email-b-cousson@ti.com>
Update pandaboard dts file with required clock frequencies
for the i2c client devices existing on pandaboard.
Add the twl6030 node in i2c1 controller.
This is the minimal support needed to boot OMAP4 boards
without any crash.
The support for all the features included in this MFD will be
added later.
Add a generic i2c EEPROM entry.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
---
arch/arm/boot/dts/omap4-panda.dts | 44 +++++++++++++++++++++++++++++++++++++
1 files changed, 44 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index c702657..2c6ce2b 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -27,3 +27,47 @@
reg = <0x80000000 0x40000000>; /* 1 GB */
};
};
+
+&i2c1 {
+ clock-frequency = <400000>;
+
+ /*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/twl6030.pdf
+ */
+ twl at 48 {
+ compatible = "ti,twl6030";
+ reg = <0x48>;
+ interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ /* twl is a MFD, so it will contain a bunch of sub-ips */
+ twl_rtc {
+ compatible = "ti,twl4030-rtc";
+ interrupts = <11>;
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+
+ /*
+ * Display monitor features are burnt in their EEPROM as EDID data.
+ * The EEPROM is connected as I2C slave device.
+ */
+ eeprom at 50 {
+ compatible = "ti,eeprom";
+ reg = <0x50>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+};
--
1.7.0.4
^ permalink raw reply related
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