* [RFC PATCH v3] drivercore: Add driver probe deferral mechanism
From: Grant Likely @ 2011-09-28 23:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110927221308.GA2674@opensource.wolfsonmicro.com>
On Tue, Sep 27, 2011 at 11:13:10PM +0100, Mark Brown wrote:
> On Tue, Sep 27, 2011 at 03:08:49PM -0600, Grant Likely wrote:
>
> > Okay, will do. How does EPROBE_DEFER 518 sound?
>
> Note that I'm not sure this answers the issue I was raising - the issue
> isn't that the caller doesn't know what the error code means, the issue
> is that in some cases the driver needs to take a decision about what
> failure to get a resource means. Does it mean that the driver can work
> fine and be slightly less featureful or should it cause a deferral?
Right. That was answering a different question.
For your question, I still think it is the driver that gets to make
the decision. If it can proceed without a resource, then it should go
ahead and succeed on the probe, and then arrange to either be notified
of new gpio controller (or whatever) registrations, or poll for the
resource to be set up.
g.
^ permalink raw reply
* [PATCH v3 3/6] OMAP3+: use DPLL's round_rate when setting rate
From: Turquette, Mike @ 2011-09-28 22:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1109280059380.4399@utopia.booyaka.com>
On Wed, Sep 28, 2011 at 12:02 AM, Paul Walmsley <paul@pwsan.com> wrote:
> Hi,
>
> On Fri, 16 Sep 2011, Jon Hunter wrote:
>
>> From: Mike Turquette <mturquette@ti.com>
>>
>> omap3_noncore_dpll_set_rate uses omap2_dpll_round_rate explicitly. ?Instead
>> use the struct clk pointer's round_rate function to allow for DPLL's with
>> special needs.
>>
>> Also the rounded rate can differ from target rate, so to better reflect
>> reality set clk->rate equal to the rounded rate when setting DPLL frequency.
>> This avoids issues where the DPLL frequency is slightly different than what
>> debugfs clock tree reports using the old target rate.
>>
>> An example of both of these needs is DPLL_ABE on OMAP4 which can have a 4x
>> multiplier on top of the usual MN dividers depending on register settings.
>> This requires a special round_rate function that might yield a rate
>> different from the initial target.
>>
>> Signed-off-by: Mike Turquette <mturquette@ti.com>
>> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
>
> The two separate changes in this patch have been separated out into two
> patches - both included below. ?Please let me know if you have any
> comments; otherwise, I'll queue for 3.2.
The split patches look good to me. I have another patch which does a
similar thing (converts omap2_get_dpll_rate use to clk->recalc) which
fixes yet more bugs that plague DPLL_ABE. Will send across shortly;
hopefully can make it into 3.2?
Regards,
Mike
^ permalink raw reply
* [PATCH v5 3/3] arm/tegra: device tree support for ventana board
From: Peter De Schrijver @ 2011-09-28 22:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317248978-10829-1-git-send-email-pdeschrijver@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/boot/dts/tegra-ventana.dts | 32 ++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/Kconfig | 6 ++++++
arch/arm/mach-tegra/Makefile.boot | 1 +
arch/arm/mach-tegra/board-dt.c | 26 +++++++++++++++++++++-----
4 files changed, 60 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/boot/dts/tegra-ventana.dts
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
new file mode 100644
index 0000000..9b29a62
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -0,0 +1,32 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ "tegra20.dtsi"
+
+/ {
+ model = "NVIDIA Tegra2 Ventana evaluation board";
+ compatible = "nvidia,ventana", "nvidia,tegra20";
+
+ chosen {
+ bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init";
+ };
+
+ memory {
+ reg = < 0x00000000 0x40000000 >;
+ };
+
+ serial at 70006300 {
+ clock-frequency = < 216000000 >;
+ };
+
+ sdhci at c8000400 {
+ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+ power-gpios = <&gpio 155 0>; /* gpio PT3 */
+ };
+
+ sdhci at c8000600 {
+ power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ support-8bit;
+ };
+};
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index d82ebab..91aff7c 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -69,6 +69,12 @@ config MACH_WARIO
help
Support for the Wario version of Seaboard
+config MACH_VENTANA
+ bool "Ventana board"
+ select MACH_TEGRA_DT
+ help
+ Support for the nVidia Ventana development platform
+
choice
prompt "Low-level debug console UART"
default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 5e870d2..bd12c9f 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -4,3 +4,4 @@ initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb
dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
+dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb
diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c
index 9f47e04..80008e9 100644
--- a/arch/arm/mach-tegra/board-dt.c
+++ b/arch/arm/mach-tegra/board-dt.c
@@ -47,7 +47,7 @@
void harmony_pinmux_init(void);
void seaboard_pinmux_init(void);
-
+void ventana_pinmux_init(void);
struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
@@ -80,9 +80,19 @@ static struct of_device_id tegra_dt_gic_match[] __initdata = {
{}
};
+static struct {
+ char *machine;
+ void (*init)(void);
+} pinmux_configs[] = {
+ { "nvidia,harmony", harmony_pinmux_init() },
+ { "nvidia,seaboard", seaboard_pinmux_init() },
+ { "nvidia,ventana", ventana_pinmux_init() },
+};
+
static void __init tegra_dt_init(void)
{
struct device_node *node;
+ int i;
node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match,
TEGRA_ARM_INT_DIST_BASE);
@@ -91,10 +101,15 @@ static void __init tegra_dt_init(void)
tegra_clk_init_from_table(tegra_dt_clk_init_table);
- if (of_machine_is_compatible("nvidia,harmony"))
- harmony_pinmux_init();
- else if (of_machine_is_compatible("nvidia,seaboard"))
- seaboard_pinmux_init();
+ for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
+ if (of_machine_is_compatible(pinmux_configs[i].name)) {
+ pinmux_configs[i].init();
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(pinmux_configs))
+ printk(KERN_WARNING "Unknown platform! Pinmuxing not initialized\n");
/*
* Finished with the static registrations now; fill in the missing
@@ -106,6 +121,7 @@ static void __init tegra_dt_init(void)
static const char * tegra_dt_board_compat[] = {
"nvidia,harmony",
"nvidia,seaboard",
+ "nvidia,ventana",
NULL
};
--
1.7.0.4
^ permalink raw reply related
* [PATCH v5 2/3] arm/tegra: add support for ventana pinmuxing
From: Peter De Schrijver @ 2011-09-28 22:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317248978-10829-1-git-send-email-pdeschrijver@nvidia.com>
Add support for ventana pinmuxing as a seaboard derivative. This is a cut down
version of work done by Jong Kim <jongk@nvidia.com>.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/board-seaboard-pinmux.c | 49 +++++++++++++++++++++++++-
2 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index f11b910..91a07e1 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -31,6 +31,7 @@ obj-${CONFIG_MACH_SEABOARD} += board-seaboard-pinmux.o
obj-${CONFIG_MACH_TEGRA_DT} += board-dt.o
obj-${CONFIG_MACH_TEGRA_DT} += board-harmony-pinmux.o
+obj-${CONFIG_MACH_TEGRA_DT} += board-seaboard-pinmux.o
obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice.o
obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index b31c765..b62b04d 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -158,8 +158,26 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
};
-
-
+static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
+ {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+};
static struct tegra_gpio_table common_gpio_table[] = {
{ .gpio = TEGRA_GPIO_SD2_CD, .enable = true },
@@ -172,6 +190,26 @@ static struct tegra_gpio_table common_gpio_table[] = {
{ .gpio = TEGRA_GPIO_USB1, .enable = true },
};
+static void __init update_pinmux(struct tegra_pingroup_config *newtbl, int size)
+{
+ int i, j;
+ struct tegra_pingroup_config *new_pingroup, *base_pingroup;
+
+ /* Update base seaboard pinmux table with secondary board
+ * specific pinmux table table.
+ */
+ for (i = 0; i < size; i++) {
+ new_pingroup = &newtbl[i];
+ for (j = 0; j < ARRAY_SIZE(seaboard_pinmux); j++) {
+ base_pingroup = &seaboard_pinmux[j];
+ if (new_pingroup->pingroup == base_pingroup->pingroup) {
+ *base_pingroup = *new_pingroup;
+ break;
+ }
+ }
+ }
+}
+
static void __init seaboard_common_pinmux_init(void)
{
tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux));
@@ -186,3 +224,10 @@ void __init seaboard_pinmux_init(void)
{
seaboard_common_pinmux_init();
}
+
+void __init ventana_pinmux_init(void)
+{
+ update_pinmux(ventana_pinmux, ARRAY_SIZE(ventana_pinmux));
+ seaboard_common_pinmux_init();
+}
+
--
1.7.0.4
^ permalink raw reply related
* [PATCH v5 1/3] arm/tegra: prepare Seaboard pinmux code for derived boards
From: Peter De Schrijver @ 2011-09-28 22:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317248978-10829-1-git-send-email-pdeschrijver@nvidia.com>
This patch splits out the common part of pinmux and GPIO initialization for
seaboard and derived boards. This code is based on work done by Jong Kim
<jongk@nvidia.com>.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/mach-tegra/board-seaboard-pinmux.c | 14 ++++++++++----
1 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 74f78b7..b31c765 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2010 NVIDIA Corporation
+ * Copyright (C) 2010,2011 NVIDIA Corporation
+ * Copyright (C) 2011 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -160,7 +161,7 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
-static struct tegra_gpio_table gpio_table[] = {
+static struct tegra_gpio_table common_gpio_table[] = {
{ .gpio = TEGRA_GPIO_SD2_CD, .enable = true },
{ .gpio = TEGRA_GPIO_SD2_WP, .enable = true },
{ .gpio = TEGRA_GPIO_SD2_POWER, .enable = true },
@@ -171,12 +172,17 @@ static struct tegra_gpio_table gpio_table[] = {
{ .gpio = TEGRA_GPIO_USB1, .enable = true },
};
-void __init seaboard_pinmux_init(void)
+static void __init seaboard_common_pinmux_init(void)
{
tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux));
tegra_drive_pinmux_config_table(seaboard_drive_pinmux,
ARRAY_SIZE(seaboard_drive_pinmux));
- tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
+ tegra_gpio_config(common_gpio_table, ARRAY_SIZE(common_gpio_table));
+}
+
+void __init seaboard_pinmux_init(void)
+{
+ seaboard_common_pinmux_init();
}
--
1.7.0.4
^ permalink raw reply related
* [PATCH v5 0/3] Add support for tegra2 based ventana board
From: Peter De Schrijver @ 2011-09-28 22:29 UTC (permalink / raw)
To: linux-arm-kernel
This patch set adds support for the tegra2 based ventana development board.
Boot tested on ventana.
Uses a table based approach to select the correct init function
Peter De Schrijver (3):
arm/tegra: prepare Seaboard pinmux code for derived boards
arm/tegra: add support for ventana pinmuxing
arm/tegra: device tree support for ventana board
arch/arm/boot/dts/tegra-ventana.dts | 32 ++++++++++++++
arch/arm/mach-tegra/Kconfig | 6 +++
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/Makefile.boot | 1 +
arch/arm/mach-tegra/board-dt.c | 5 ++-
arch/arm/mach-tegra/board-seaboard-pinmux.c | 63 ++++++++++++++++++++++++---
6 files changed, 101 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/boot/dts/tegra-ventana.dts
^ permalink raw reply
* [PATCH v2 2/6] OMAP4: Clock: round_rate and recalc functions for DPLL_ABE
From: Turquette, Mike @ 2011-09-28 22:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1109280056570.4399@utopia.booyaka.com>
On Tue, Sep 27, 2011 at 11:59 PM, Paul Walmsley <paul@pwsan.com> wrote:
> Hi Jon and Mike,
>
> On Fri, 16 Sep 2011, Jon Hunter wrote:
>
>> From: Mike Turquette <mturquette@ti.com>
>>
>> OMAP4 DPLL_ABE can enable a 4X multipler on top of the normal MN multipler
>> and divider. This is achieved by setting CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN
>> bit in CKGEN module of CM1. From the OMAP4 TRM:
>>
>> Fdpll = Fref x 2 x (4 x M/(N+1)) in case REGM4XEN bit field is set (only
>> applicable to DPLL_ABE).
>>
>> Add new round_rate() and recalc() functions for OMAP4, that check the
>> setting of REGM4XEN bit and handle this appropriately. The new functions
>> are a simple wrapper on top of the existing omap2_dpll_round_rate() and
>> omap2_dpll_get_rate() functions to handle the REGM4XEN bit.
>>
>> The REGM4XEN bit is only implemented for the ABE DPLL on OMAP4 and so
>> only dpll_abe_ck uses omap4_dpll_regm4xen_round_rate() and
>> omap4_dpll_regm4xen_recalc() functions.
>>
>> Signed-off-by: Mike Turquette <mturquette@ti.com>
>> Tested-by: Jon Hunter <jon-hunter@ti.com>
>
> Some changes have been made to this patch here, to fix a few minor bugs in
> error paths and to add documentation and Jon's Signed-off-by: (since he's
> in the submittal chain).
>
> Care to review and send any comments? ?Otherwise, I plan to queue this
> revised version for 3.2.
Your changes to the patch look good.
Regards,
Mike
^ permalink raw reply
* [GIT PULL] OMAP: Few sparse/bug fixes and clean-up for 3.2
From: Tony Lindgren @ 2011-09-28 22:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316852520-10377-1-git-send-email-santosh.shilimkar@ti.com>
* Santosh Shilimkar <santosh.shilimkar@ti.com> [110924 00:48]:
> Tony,
>
> Please pull few OMAP sparse/bug fixes and clean-up for 3.2
Thanks I'll pull these into l3 branch for v3.2 merge window and
merge them into l-o master.
Tony
> Thnaks,
> Santosh
>
> The following changes since commit b6fd41e29dea9c6753b1843a77e50433e6123bcb:
>
> Linux 3.1-rc6 (2011-09-12 14:02:02 -0700)
>
> are available in the git repository at:
> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git for_3_2/omap_misc
>
> Santosh Shilimkar (1):
> OMAP4: Fix the emif and dmm virtual mapping
>
> Todd Poynor (2):
> OMAP: Improve register access in L3 Error handler.
> OMAP: Fix a BUG in l3 error handler.
>
> sricharan (3):
> OMAP: Fix indentation issues in l3 error handler.
> OMAP: Fix sparse warnings in l3 error handler.
> OMAP: Print Initiator name for l3 custom error.
>
> arch/arm/mach-omap2/omap_l3_noc.c | 130 ++++++++++----------
> arch/arm/mach-omap2/omap_l3_noc.h | 224 +++++++++++++++++++---------------
> arch/arm/mach-omap2/omap_l3_smx.c | 91 +++++++-------
> arch/arm/mach-omap2/omap_l3_smx.h | 164 ++++++++++++------------
> arch/arm/plat-omap/include/plat/io.h | 4 +-
> 5 files changed, 322 insertions(+), 291 deletions(-)
^ permalink raw reply
* [GIT PULL] dmtimer changes for v3.2 merge window
From: Tony Lindgren @ 2011-09-28 22:02 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd,
Please pull omap dmtimer changes from:
git://github.com/tmlind/linux.git dmtimer
This series completes the system timer separation from the
driver like features. It also adds support for v2 ip that is
available for some timers starting with omap4.
After this series arch/arm/plat-omap/dmtimer.c could be
moved to live under drivers somewhere, but there is still
discussion going on which features should be supported in
a generic way.
This series depends on the cleanup you pulled earlier.
As this series adds some new features like runtime PM suppport,
I've kept it separate from cleanup.
Regards,
Tony
The following changes since commit ceb1c532ba6220900e61ec7073a9234661efa450:
Tony Lindgren (1):
Merge branch 'omap_chip_remove_cleanup_3.2' of git://git.pwsan.com/linux-2.6 into cleanup
are available in the git repository at:
git://github.com/tmlind/linux.git dmtimer
Tarun Kanti DebBarma (8):
ARM: OMAP2+: dmtimer: add device names to flck nodes
ARM: OMAP1: dmtimer: conversion to platform devices
ARM: OMAP2+: dmtimer: convert to platform devices
ARM: OMAP: dmtimer: platform driver
ARM: OMAP: dmtimer: switch-over to platform device driver
ARM: OMAP: dmtimer: pm_runtime support
ARM: OMAP: dmtimer: low-power mode support
ARM: OMAP: dmtimer: add error handling to export APIs
Tony Lindgren (2):
ARM: OMAP: Add support for dmtimer v2 ip
ARM: OMAP: dmtimer: skip reserved timers
arch/arm/mach-omap1/Makefile | 2 +-
arch/arm/mach-omap1/timer.c | 173 +++++++
arch/arm/mach-omap2/clock2420_data.c | 48 ++
arch/arm/mach-omap2/clock2430_data.c | 48 ++
arch/arm/mach-omap2/clock3xxx_data.c | 36 ++
arch/arm/mach-omap2/clock44xx_data.c | 33 ++
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 22 +
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 22 +
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 27 +
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 22 +
arch/arm/mach-omap2/timer.c | 194 +++++++-
arch/arm/plat-omap/dmtimer.c | 713 ++++++++++++++++------------
arch/arm/plat-omap/include/plat/dmtimer.h | 233 +++++++---
13 files changed, 1185 insertions(+), 388 deletions(-)
create mode 100644 arch/arm/mach-omap1/timer.c
^ permalink raw reply
* [PATCH 4/4] ARM: OMAP: irq: loop counter fix in omap_init_irq()
From: Tony Lindgren @ 2011-09-28 21:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110928214707.29263.58095.stgit@kaulin.local>
From: Tapani Utriainen <tapani@technexion.com>
Fixes bug where variable i was redundantly used for counting two nested loops.
Signed-off-by: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/irq.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 3a12f75..65f1be6 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -165,8 +165,8 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
omap_irq_bank_init_one(bank);
- for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20)
- omap_alloc_gc(bank->base_reg + j, i, 32);
+ for (j = 0; j < bank->nr_irqs; j += 32)
+ omap_alloc_gc(bank->base_reg + j, j, 32);
nr_of_irqs += bank->nr_irqs;
nr_banks++;
^ permalink raw reply related
* [PATCH 3/4] ARM: OMAP4: Keyboard: Fix section mismatch in the board file
From: Tony Lindgren @ 2011-09-28 21:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110928214707.29263.58095.stgit@kaulin.local>
From: Bjarne Steinsbo <bsteinsbo@gmail.com>
`keypad_pads' is referred to by `keypad_data' which is
not __initdata, so `keypad_pads' should not be __initdata either.
Signed-off-by: Bjarne Steinsbo <bsteinsbo@gmail.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/board-4430sdp.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index c7cef44..9e423ac 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -129,7 +129,7 @@ static const int sdp4430_keymap[] = {
KEY(7, 6, KEY_OK),
KEY(7, 7, KEY_DOWN),
};
-static struct omap_device_pad keypad_pads[] __initdata = {
+static struct omap_device_pad keypad_pads[] = {
{ .name = "kpd_col1.kpd_col1",
.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
},
^ permalink raw reply related
* [PATCH 2/4] ARM: OMAP: Fix i2c init for twl4030
From: Tony Lindgren @ 2011-09-28 21:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110928214707.29263.58095.stgit@kaulin.local>
Looks like 2600 kHz rate does not work reliably on 2430,
so just use the 100 kHz rate.
Otherwise the system often fails to boot properly with:
omap_i2c omap_i2c.2: timeout waiting for bus ready
omap_i2c omap_i2c.2: timeout waiting for bus ready
twl: i2c_write failed to transfer all messages
omap_i2c omap_i2c.2: timeout waiting for bus ready
twl: i2c_write failed to transfer all messages
omap_i2c omap_i2c.2: timeout waiting for bus ready
twl: i2c_write failed to transfer all messages
twl: clock init err [-110]
omap_i2c omap_i2c.2: timeout waiting for bus ready
twl: i2c_write failed to transfer all messages
TWL4030 Unable to unlock IDCODE registers --110
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/board-2430sdp.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 2028464..f79b7d2 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -193,7 +193,8 @@ static int __init omap2430_i2c_init(void)
{
omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
ARRAY_SIZE(sdp2430_i2c1_boardinfo));
- omap2_pmic_init("twl4030", &sdp2430_twldata);
+ omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
+ &sdp2430_twldata);
return 0;
}
^ permalink raw reply related
* [PATCH 1/4] ARM: OMAP4: MMC: fix power and audio issue, decouple USBC1 from MMC1
From: Tony Lindgren @ 2011-09-28 21:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110928214707.29263.58095.stgit@kaulin.local>
From: Bryan Buckley <bryan.buckley@ti.com>
Remove OMAP4_USBC1_ICUSB_PWRDNZ_MASK during enable/disable PWRDNZ mode for
MMC1_PBIAS and associated extended-drain MMC1 I/O cell. This is in accordance
with the control module programming guide. This fixes a bug where if trying to
use gpio_98 or gpio_99 and MMC1 at the same time the GPIO signal will be
affected by a changing SDMMC1_VDDS.
Software must keep MMC1_PBIAS cell and MMC1_IO cell PWRDNZ signals low whenever
SDMMC1_VDDS ramps up/down or changes for cell protection purposes.
MMC1 is based on SDMMC1_VDDS whereas USBC1 is based on SIM_VDDS therefore
they can operate independently.
Signed-off-by: Bryan Buckley <bryan.buckley@ti.com>
Acked-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
Tested-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/hsmmc.c | 12 ++++--------
1 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index a9b45c7..097a42d 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -137,8 +137,7 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
*/
reg = omap4_ctrl_pad_readl(control_pbias_offset);
reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
- OMAP4_MMC1_PWRDNZ_MASK |
- OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+ OMAP4_MMC1_PWRDNZ_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
}
@@ -156,8 +155,7 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
else
reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
- OMAP4_MMC1_PWRDNZ_MASK |
- OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+ OMAP4_MMC1_PWRDNZ_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
timeout = jiffies + msecs_to_jiffies(5);
@@ -171,16 +169,14 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
pr_err("Pbias Voltage is not same as LDO\n");
/* Caution : On VMODE_ERROR Power Down MMC IO */
- reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
- OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+ reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
}
} else {
reg = omap4_ctrl_pad_readl(control_pbias_offset);
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
OMAP4_MMC1_PWRDNZ_MASK |
- OMAP4_MMC1_PBIASLITE_VMODE_MASK |
- OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+ OMAP4_MMC1_PBIASLITE_VMODE_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
}
}
^ permalink raw reply related
* [PATCH 0/4] Few omap fixes for review
From: Tony Lindgren @ 2011-09-28 21:48 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
Here are some omap fixes for review. Only the first two would
be nice to get into v3.1 during the -rc cycle.
Regards,
Tony
---
Bjarne Steinsbo (1):
ARM: OMAP4: Keyboard: Fix section mismatch in the board file
Bryan Buckley (1):
ARM: OMAP4: MMC: fix power and audio issue, decouple USBC1 from MMC1
Tapani Utriainen (1):
ARM: OMAP: irq: loop counter fix in omap_init_irq()
Tony Lindgren (1):
ARM: OMAP: Fix i2c init for twl4030
arch/arm/mach-omap2/board-2430sdp.c | 3 ++-
arch/arm/mach-omap2/board-4430sdp.c | 2 +-
arch/arm/mach-omap2/hsmmc.c | 12 ++++--------
arch/arm/mach-omap2/irq.c | 4 ++--
4 files changed, 9 insertions(+), 12 deletions(-)
--
Signature
^ permalink raw reply
* [PATCH 02/13] gpio/omap: Adapt GPIO driver to DT
From: Scott Wood @ 2011-09-28 21:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E838A41.8010408@ti.com>
On 09/28/2011 03:57 PM, Cousson, Benoit wrote:
> On 9/28/2011 8:23 PM, Scott Wood wrote:
>> What does "the id" mean, in relation to the actual hardware?
>
> It's true that the description is not super meaningful...
> This is the HW instance number. We have 6 gpios, named gpio1 to gpio6,
> but the pin numbering is global, meaning from 1 to 192, sine only the
> global number is referenced in the pinmuxing control, we have to
> maintain the order to ensure the right number.
I'd either have one node that handles all the banks (with multiple "reg"
resources in the order that they should be mapped to the numberspace),
or avoid using that global numberspace and reference things by
bank/offset (with the bank identified by alias or phandle).
> I still do not know how to use that with the way gpio binding is
> working. Because in theory each gpio controller should be referenced
> with the local number, not the global one. And converting that global
> number from HW spec to a gpio instance + local number seems to me very
> error prone.
You could say the same thing about a chip whose manual is written
assuming a global IRQ numberspace with a certain encoding scheme.
Or in the other direction, Freescale's manuals split up MPIC interrupts
into external/internal/MSI, while they really just map to different
regions of the openpic (hardware standard that Freescale's MPIC is an
instance of) interrupt space. The device trees use the raw openpic
interrupt numbers.
There's certainly potential for confusion, but at least the device tree
representation is internally consistent and doesn't make assumptions
about the overall system.
-Scott
^ permalink raw reply
* [GIT PULL] at91 fixes for 3.1
From: Nicolas FERRE @ 2011-09-28 21:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd,
Here is a couple of fixes that may be included in 3.1-final.
The Kconfig modification will allow to select the PWM driver for SAM9G45
SoC. This will also benefit to stable kernels.
The new defconfig for SAM9G45 family will allow us to better monitor the
health of this port through automatic compilation mechanism. I find it
interesting to have it included the sooner.
The pull is based on the following changes since commit
a102a9ece5489e1718cd7543aa079082450ac3a2:
Linux 3.1-rc8 (2011-09-27 15:48:34 -0700)
are available in the git repository at:
git://github.com/at91linux/linux-at91.git at91-fixes
Nicolas Ferre (2):
ARM: at91: remove dependency for Atmel PWM driver selector in Kconfig
ARM: at91: add defconfig for at91sam9g45 family
arch/arm/configs/at91sam9g45_defconfig | 214 ++++++++++++++++++++++
drivers/misc/Kconfig | 1 -
2 files changed, 214 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/configs/at91sam9g45_defconfig
--
Nicolas Ferre
^ permalink raw reply
* [PATCH 2/2] msm: Support DEBUG_LL on MSM8660 and MSM8960
From: Stephen Boyd @ 2011-09-28 21:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317243959-26383-1-git-send-email-sboyd@codeaurora.org>
Add support for DEBUG_LL on the 8660 and 8960 development boards.
While we're here, cleanup the uncompress.h code a bit.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
arch/arm/Kconfig.debug | 16 ++++++++++++
arch/arm/mach-msm/Kconfig | 3 ++
arch/arm/mach-msm/include/mach/debug-macro.S | 27 ++++++++++++++++++++
arch/arm/mach-msm/include/mach/msm_iomap-8960.h | 5 +++
arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 5 +++
arch/arm/mach-msm/include/mach/uncompress.h | 31 +++++++++++++++++------
arch/arm/mach-msm/io.c | 6 ++++
7 files changed, 85 insertions(+), 8 deletions(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 35eebad..72e7aeb 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -141,6 +141,22 @@ choice
Say Y here if you want the debug print routines to direct
their output to the third serial port on MSM devices.
+ config DEBUG_MSM8660_UART
+ bool "Kernel low-level debugging messages via MSM 8660 UART"
+ depends on ARCH_MSM8X60
+ select MSM_HAS_DEBUG_UART_HS
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the serial port on MSM 8960 devices.
+
+ config DEBUG_MSM8960_UART
+ bool "Kernel low-level debugging messages via MSM 8960 UART"
+ depends on ARCH_MSM8960
+ select MSM_HAS_DEBUG_UART_HS
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the serial port on MSM 8960 devices.
+
endchoice
config EARLY_PRINTK
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 5b07b61..000ddf0 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -60,6 +60,9 @@ config ARCH_MSM8960
endchoice
+config MSM_HAS_DEBUG_UART_HS
+ bool
+
config MSM_SOC_REV_A
bool
config ARCH_MSM_SCORPIONMP
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 3120691..8fa4e87 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -1,6 +1,7 @@
/*
*
* Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@@ -23,15 +24,41 @@
.endm
.macro senduart,rd,rx
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
+ @ Clear TX_READY by writing to the UARTDM_CR register
+ mov r12, #0x300
+ str r12, [\rx, #0x10]
+ @ Write 0x1 to NCF register
+ mov r12, #0x1
+ str r12, [\rx, #0x40]
+ @ UARTDM reg. Read to induce delay
+ ldr r12, [\rx, #0x08]
+ @ Write the 1 character to UARTDM_TF
+ str \rd, [\rx, #0x70]
+#else
teq \rx, #0
strne \rd, [\rx, #0x0C]
+#endif
.endm
.macro waituart,rd,rx
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
+ @ check for TX_EMT in UARTDM_SR
+ ldr \rd, [\rx, #0x08]
+ tst \rd, #0x08
+ bne 1002f
+ @ wait for TXREADY in UARTDM_ISR
+1001: ldreq \rd, [\rx, #0x14]
+ tst \rd, #0x80
+ dsb
+ beq 1001b
+#else
@ wait for TX_READY
1001: ldr \rd, [\rx, #0x08]
tst \rd, #0x04
beq 1001b
+#endif
+1002:
.endm
.macro busyuart,rd,rx
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index 3c9d960..800b557 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -45,4 +45,9 @@
#define MSM8960_TMR0_PHYS 0x0208A000
#define MSM8960_TMR0_SIZE SZ_4K
+#ifdef CONFIG_DEBUG_MSM8960_UART
+#define MSM_DEBUG_UART_BASE 0xE1040000
+#define MSM_DEBUG_UART_PHYS 0x16440000
+#endif
+
#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 3b19b8f..54e12ca 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -62,4 +62,9 @@
#define MSM8X60_TMR0_PHYS 0x02040000
#define MSM8X60_TMR0_SIZE SZ_4K
+#ifdef CONFIG_DEBUG_MSM8660_UART
+#define MSM_DEBUG_UART_BASE 0xE1040000
+#define MSM_DEBUG_UART_PHYS 0x19C40000
+#endif
+
#endif
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
index d94292c..ee906e4 100644
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ b/arch/arm/mach-msm/include/mach/uncompress.h
@@ -1,6 +1,6 @@
-/* arch/arm/mach-msm/include/mach/uncompress.h
- *
+/*
* Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -14,17 +14,32 @@
*/
#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
+#define __ASM_ARCH_MSM_UNCOMPRESS_H
-#include "hardware.h"
-#include "linux/io.h"
-#include "mach/msm_iomap.h"
+#include <linux/io.h>
+#include <asm/processor.h>
+#include <mach/msm_iomap.h>
static void putc(int c)
{
#if defined(MSM_DEBUG_UART_PHYS)
- unsigned base = MSM_DEBUG_UART_PHYS;
- while (!(readl(base + 0x08) & 0x04)) ;
- writel(c, base + 0x0c);
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
+ /*
+ * Wait for TX_READY to be set; but skip it if we have a
+ * TX underrun.
+ */
+ if (readl_relaxed(MSM_DEBUG_UART_PHYS + 0x08) & 0x08)
+ while (!(readl_relaxed(MSM_DEBUG_UART_PHYS + 0x14) & 0x80))
+ cpu_relax();
+
+ writel_relaxed(0x300, MSM_DEBUG_UART_PHYS + 0x10);
+ writel_relaxed(0x1, MSM_DEBUG_UART_PHYS + 0x40);
+ writel_relaxed(c, MSM_DEBUG_UART_PHYS + 0x70);
+#else
+ while (!(readl_relaxed(MSM_DEBUG_UART_PHYS + 0x08) & 0x04))
+ cpu_relax();
+ writel_relaxed(c, MSM_DEBUG_UART_PHYS + 0x0c);
+#endif
#endif
}
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 03036af..578b04e 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -111,6 +111,9 @@ static struct map_desc msm8x60_io_desc[] __initdata = {
MSM_CHIP_DEVICE(TMR0, MSM8X60),
MSM_DEVICE(ACC),
MSM_DEVICE(GCC),
+#ifdef CONFIG_DEBUG_MSM8660_UART
+ MSM_DEVICE(DEBUG_UART),
+#endif
};
void __init msm_map_msm8x60_io(void)
@@ -125,6 +128,9 @@ static struct map_desc msm8960_io_desc[] __initdata = {
MSM_CHIP_DEVICE(QGIC_CPU, MSM8960),
MSM_CHIP_DEVICE(TMR, MSM8960),
MSM_CHIP_DEVICE(TMR0, MSM8960),
+#ifdef CONFIG_DEBUG_MSM8960_UART
+ MSM_DEVICE(DEBUG_UART),
+#endif
};
void __init msm_map_msm8960_io(void)
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply related
* [PATCH 1/2] msm: Consolidate and move DEBUG_LL to generic ARM Kconfig
From: Stephen Boyd @ 2011-09-28 21:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317243959-26383-1-git-send-email-sboyd@codeaurora.org>
Now that DEBUG_LL is a choice, we can move MSM's homegrown choice
menu to DEBUG_LL.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
arch/arm/Kconfig.debug | 21 +++++++++++++++
arch/arm/mach-msm/Kconfig | 32 -----------------------
arch/arm/mach-msm/include/mach/debug-macro.S | 17 +-----------
arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | 12 --------
arch/arm/mach-msm/include/mach/msm_iomap-7x30.h | 12 --------
arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | 12 --------
arch/arm/mach-msm/include/mach/msm_iomap.h | 12 ++++++++
arch/arm/mach-msm/io.c | 9 ++++--
8 files changed, 40 insertions(+), 87 deletions(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 91a82630..35eebad 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -120,6 +120,27 @@ choice
Say Y here if you want the debug print routines to direct
their output to the second serial port on these devices.
+ config DEBUG_MSM_UART1
+ bool "Kernel low-level debugging messages via MSM UART1"
+ depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the first serial port on MSM devices.
+
+ config DEBUG_MSM_UART2
+ bool "Kernel low-level debugging messages via MSM UART2"
+ depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the second serial port on MSM devices.
+
+ config DEBUG_MSM_UART3
+ bool "Kernel low-level debugging messages via MSM UART3"
+ depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the third serial port on MSM devices.
+
endchoice
config EARLY_PRINTK
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index ebde97f..5b07b61 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -13,7 +13,6 @@ config ARCH_MSM7X00A
select CPU_V6
select GPIO_MSM_V1
select MSM_PROC_COMM
- select HAS_MSM_DEBUG_UART_PHYS
config ARCH_MSM7X30
bool "MSM7x30"
@@ -25,7 +24,6 @@ config ARCH_MSM7X30
select MSM_GPIOMUX
select GPIO_MSM_V1
select MSM_PROC_COMM
- select HAS_MSM_DEBUG_UART_PHYS
config ARCH_QSD8X50
bool "QSD8X50"
@@ -37,7 +35,6 @@ config ARCH_QSD8X50
select MSM_GPIOMUX
select GPIO_MSM_V1
select MSM_PROC_COMM
- select HAS_MSM_DEBUG_UART_PHYS
config ARCH_MSM8X60
bool "MSM8X60"
@@ -73,9 +70,6 @@ config ARCH_MSM_ARM11
config ARCH_MSM_SCORPION
bool
-config HAS_MSM_DEBUG_UART_PHYS
- bool
-
config MSM_VIC
bool
@@ -152,32 +146,6 @@ config MACH_MSM8960_RUMI3
endmenu
-config MSM_DEBUG_UART
- int
- default 1 if MSM_DEBUG_UART1
- default 2 if MSM_DEBUG_UART2
- default 3 if MSM_DEBUG_UART3
-
-if HAS_MSM_DEBUG_UART_PHYS
-choice
- prompt "Debug UART"
-
- default MSM_DEBUG_UART_NONE
-
- config MSM_DEBUG_UART_NONE
- bool "None"
-
- config MSM_DEBUG_UART1
- bool "UART1"
-
- config MSM_DEBUG_UART2
- bool "UART2"
-
- config MSM_DEBUG_UART3
- bool "UART3"
-endchoice
-endif
-
config MSM_SMD_PKG3
bool
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 646b99e..3120691 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -1,4 +1,4 @@
-/* arch/arm/mach-msm7200/include/mach/debug-macro.S
+/*
*
* Copyright (C) 2007 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
@@ -14,12 +14,9 @@
*
*/
-
-
#include <mach/hardware.h>
#include <mach/msm_iomap.h>
-#if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE)
.macro addruart, rp, rv
ldr \rp, =MSM_DEBUG_UART_PHYS
ldr \rv, =MSM_DEBUG_UART_BASE
@@ -36,18 +33,6 @@
tst \rd, #0x04
beq 1001b
.endm
-#else
- .macro addruart, rp, rv
- mov \rv, #0xff000000
- orr \rv, \rv, #0x00f00000
- .endm
-
- .macro senduart,rd,rx
- .endm
-
- .macro waituart,rd,rx
- .endm
-#endif
.macro busyuart,rd,rx
.endm
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 94fe9fe..8af4612 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -78,18 +78,6 @@
#define MSM_UART3_PHYS 0xA9C00000
#define MSM_UART3_SIZE SZ_4K
-#ifdef CONFIG_MSM_DEBUG_UART
-#define MSM_DEBUG_UART_BASE 0xE1000000
-#if CONFIG_MSM_DEBUG_UART == 1
-#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 2
-#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 3
-#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
-#endif
-#define MSM_DEBUG_UART_SIZE SZ_4K
-#endif
-
#define MSM_SDC1_PHYS 0xA0400000
#define MSM_SDC1_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 3769444..198202c 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -89,18 +89,6 @@
#define MSM_UART3_PHYS 0xACC00000
#define MSM_UART3_SIZE SZ_4K
-#ifdef CONFIG_MSM_DEBUG_UART
-#define MSM_DEBUG_UART_BASE 0xE1000000
-#if CONFIG_MSM_DEBUG_UART == 1
-#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 2
-#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 3
-#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
-#endif
-#define MSM_DEBUG_UART_SIZE SZ_4K
-#endif
-
#define MSM_MDC_BASE IOMEM(0xE0200000)
#define MSM_MDC_PHYS 0xAA500000
#define MSM_MDC_SIZE SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index d67cd73..0faa894 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -83,18 +83,6 @@
#define MSM_UART3_PHYS 0xA9C00000
#define MSM_UART3_SIZE SZ_4K
-#ifdef CONFIG_MSM_DEBUG_UART
-#define MSM_DEBUG_UART_BASE 0xE1000000
-#if CONFIG_MSM_DEBUG_UART == 1
-#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 2
-#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 3
-#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
-#endif
-#define MSM_DEBUG_UART_SIZE SZ_4K
-#endif
-
#define MSM_MDC_BASE IOMEM(0xE0200000)
#define MSM_MDC_PHYS 0xAA500000
#define MSM_MDC_SIZE SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 4ded152..90682f4 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -55,6 +55,18 @@
#include "msm_iomap-8960.h"
+#define MSM_DEBUG_UART_SIZE SZ_4K
+#if defined(CONFIG_DEBUG_MSM_UART1)
+#define MSM_DEBUG_UART_BASE 0xE1000000
+#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
+#elif defined(CONFIG_DEBUG_MSM_UART2)
+#define MSM_DEBUG_UART_BASE 0xE1000000
+#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
+#elif defined(CONFIG_DEBUG_MSM_UART3)
+#define MSM_DEBUG_UART_BASE 0xE1000000
+#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
+#endif
+
/* Virtual addresses shared across all MSM targets. */
#define MSM_CSR_BASE IOMEM(0xE0001000)
#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000)
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 8759ecf..03036af 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -47,7 +47,8 @@ static struct map_desc msm_io_desc[] __initdata = {
MSM_CHIP_DEVICE(GPIO1, MSM7X00),
MSM_CHIP_DEVICE(GPIO2, MSM7X00),
MSM_DEVICE(CLK_CTL),
-#ifdef CONFIG_MSM_DEBUG_UART
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+ defined(CONFIG_DEBUG_MSM_UART3)
MSM_DEVICE(DEBUG_UART),
#endif
#ifdef CONFIG_ARCH_MSM7X30
@@ -84,7 +85,8 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
MSM_DEVICE(SCPLL),
MSM_DEVICE(AD5),
MSM_DEVICE(MDC),
-#ifdef CONFIG_MSM_DEBUG_UART
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+ defined(CONFIG_DEBUG_MSM_UART3)
MSM_DEVICE(DEBUG_UART),
#endif
{
@@ -146,7 +148,8 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
MSM_DEVICE(SAW),
MSM_DEVICE(GCC),
MSM_DEVICE(TCSR),
-#ifdef CONFIG_MSM_DEBUG_UART
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+ defined(CONFIG_DEBUG_MSM_UART3)
MSM_DEVICE(DEBUG_UART),
#endif
{
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply related
* [PATCH 0/2] Update MSM DEBUG_LL support
From: Stephen Boyd @ 2011-09-28 21:05 UTC (permalink / raw)
To: linux-arm-kernel
These patches consolidate the current DEBUG_LL code in MSM; moving
the configs to the toplevel DEBUG_LL choice. They also add support
for 8660 and 8960 low level debug.
Patches are based on linux-next-20110927
Stephen Boyd (2):
msm: Consolidate and move DEBUG_LL to generic ARM Kconfig
msm: Support DEBUG_LL on MSM8660 and MSM8960
arch/arm/Kconfig.debug | 37 +++++++++++++++++++
arch/arm/mach-msm/Kconfig | 35 ++----------------
arch/arm/mach-msm/include/mach/debug-macro.S | 44 ++++++++++++++--------
arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | 12 ------
arch/arm/mach-msm/include/mach/msm_iomap-7x30.h | 12 ------
arch/arm/mach-msm/include/mach/msm_iomap-8960.h | 5 +++
arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | 12 ------
arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 5 +++
arch/arm/mach-msm/include/mach/msm_iomap.h | 12 ++++++
arch/arm/mach-msm/include/mach/uncompress.h | 31 ++++++++++++----
arch/arm/mach-msm/io.c | 15 ++++++--
11 files changed, 125 insertions(+), 95 deletions(-)
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [PATCH 02/13] gpio/omap: Adapt GPIO driver to DT
From: Cousson, Benoit @ 2011-09-28 20:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E836612.2010709@freescale.com>
On 9/28/2011 8:23 PM, Scott Wood wrote:
> On 09/28/2011 03:15 AM, Cousson, Benoit wrote:
>> On 9/27/2011 7:40 AM, Nayak, Rajendra wrote:
>>> On Monday 26 September 2011 10:20 PM, Benoit Cousson wrote:
>>>> +Required properties:
>>>> +- compatible:
>>>> + - "ti,omap2-gpio" for OMAP2 and OMAP3 controllers
>>>
>>> Would it be more readable to have
>>> "ti,omap2-gpio" for OMAP2 controllers and
>>> "ti,omap3-gpio" for OMAP3 controllers?
>
> Or have OMAP3 say this if it's fully backwards compatible:
>
> compatible = "ti,omap3-gpio", "ti,omap2-gpio";
I saw that several time for other platform, but was wondering if this
was a strong rule or not. In that case, the IP is the same, so should we
still identify it with a different compatible value?
>>>> + - "ti,omap4-gpio" for OMAP4 controller
>>>> +- #gpio-cells : Should be two.
>>>> + - first cell is the pin number
>>>> + - second cell is used to specify optional parameters (unused)
>>>> +- gpio-controller : Marks the device node as a GPIO controller.
>>>> +
>>>> +OMAP specific properties:
>>>> +- ti,hwmods: Name of the hwmod associated to the GPIO
>>>> +- id: 32 bits to identify the id (1 based index)
>
> What does "the id" mean, in relation to the actual hardware?
It's true that the description is not super meaningful...
This is the HW instance number. We have 6 gpios, named gpio1 to gpio6,
but the pin numbering is global, meaning from 1 to 192, sine only the
global number is referenced in the pinmuxing control, we have to
maintain the order to ensure the right number.
I still do not know how to use that with the way gpio binding is
working. Because in theory each gpio controller should be referenced
with the local number, not the global one. And converting that global
number from HW spec to a gpio instance + local number seems to me very
error prone.
> Some existing bindings have such a thing (often called "cell-index"),
> but it should be well-defined what it refers to. Often aliases would be
> a better approach, if it just refers to what the manual calls the device.
The issue is that the manual refer to a global gpio controller.
>>>> +- bank-width: number of pin supported by the controller (16 or 32)
>>>> +- debounce: set if the controller support the debouce funtionnality
>>>> +- bank-count: number of controller support by the SoC. This is a
>>>> temporary
>>>> + hack until the bank_count is removed from the driver.
>>>
>>> Is there a general rule to be followed as to when to use
>>> "ti,<prop-name>" and when to use just"<prop-name>".
>>> Since all these are OMAP specific properties, shouldn't all
>>> of them be "ti,<prop-name>"?
>>
>> To be honest, I was wondering as well about this rule.
>> I think that a property that is not purely OMAP specific and that
>> represents some standard HW information does not have to be prefixed by
>> "ti,XXX".
>> So hwmods must be "ti,hwmods", but bank-witdh and bank-count seems to me
>> quite generic.
>
> It's about where the property is documented. Suppose you use an
> un-prefixed bank-width but define it in the TI-specific binding to mean
> width in bits. Later, someone wants something similar for another
> driver, doesn't look at the TI binding, but says, "This is generic, I'll
> define something in the main gpio binding," but defines it as width in
> bytes (ignore the (de)merits of defining it that way in this case). If
> you had a namespace prefix, it would be clear which binding a node is
> referring to.
Good to know, and that makes sense. So the recommendation is to add that
into the generic gpio as much as possible if this can be reused by
someone else.
> As for bank-count, the description "this is a temporary hack until the
> bank_count is removed from the driver" suggests it shouldn't be there at
> all, much less be part of the generic binding.
That one sucks and will be removed soon since the driver cleanup was
posted and waiting for upstream acceptance.
Thanks for the detailed explanations.
Benoit
^ permalink raw reply
* [PATCHv2 02/10] ARM: vic: MULTI_IRQ_HANDLER handler
From: Grant Likely @ 2011-09-28 20:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317206507-18867-3-git-send-email-jamie@jamieiles.com>
On Wed, Sep 28, 2011 at 11:41:39AM +0100, Jamie Iles wrote:
> Add a handler for the VIC that is suitable for MULTI_IRQ_HANDLER
> platforms. This can replace the ASM entry macros for platforms that use
> the VIC.
>
> v2: - allow the handler be used for !CONFIG_OF
> - use irq_domain_to_irq()
>
> Cc: Rob Herring <robherring2@gmail.com>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
> ---
> arch/arm/common/vic.c | 29 +++++++++++++++++++++++++++++
> arch/arm/include/asm/hardware/vic.h | 4 ++++
> 2 files changed, 33 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
> index 3f9c8f2..71adced 100644
> --- a/arch/arm/common/vic.c
> +++ b/arch/arm/common/vic.c
> @@ -427,3 +427,32 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
> return -EIO;
> }
> #endif /* CONFIG OF */
> +
> +#ifdef CONFIG_MULTI_IRQ_HANDLER
> +static void vic_single_handle_irq(struct vic_device *vic, struct pt_regs *regs)
> +{
> + u32 stat, irq;
> + bool handled = false;
> +
> + while (!handled) {
> + stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
> + if (!stat)
> + break;
> +
> + while (stat) {
> + irq = fls(stat) - 1;
> + handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
> + stat &= ~(1 << irq);
> + handled = true;
> + }
> + }
I don't follow why this is written this way. The way I see it, there
are two conditions:
1) first read will show no irqs pending (!stat), which will break out
of the outer while() loop.
2) or there will be irqs pending, it will enter the second while()
loop, which unconditionally sets the handled flag, and causes the
outer loop to exit immediately after the inner loop exits.
Why isn't it simply written this way:
stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
while (stat) {
irq = fls(stat) - 1;
handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
stat &= ~(1 << irq);
}
g.
^ permalink raw reply
* [PATCHv2 01/10] ARM: vic: device tree binding
From: Grant Likely @ 2011-09-28 20:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317206507-18867-2-git-send-email-jamie@jamieiles.com>
On Wed, Sep 28, 2011 at 11:41:38AM +0100, Jamie Iles wrote:
> This adds a device tree binding for the VIC based on the of_irq_init()
> support. This adds an irqdomain to the vic and always registers all
> vics in the static vic array rather than for pm only to keep track of
> the irq domain. struct irq_data::hwirq is used where appropriate rather
> than runtime masking.
>
> v2: - use irq_domain_simple_ops
> - remove stub implementation of vic_of_init for !CONFIG_OF
> - Make VIC select IRQ_DOMAIN
Looks right to me.
Reviewed-by: Grant Likely <grant.likely@secretlab.ca>
>
> Cc: Rob Herring <robherring2@gmail.com>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
> ---
> Documentation/devicetree/bindings/arm/vic.txt | 29 +++++++
> arch/arm/common/Kconfig | 1 +
> arch/arm/common/vic.c | 106 ++++++++++++++++++-------
> arch/arm/include/asm/hardware/vic.h | 10 ++-
> 4 files changed, 117 insertions(+), 29 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/vic.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/vic.txt b/Documentation/devicetree/bindings/arm/vic.txt
> new file mode 100644
> index 0000000..266716b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/vic.txt
> @@ -0,0 +1,29 @@
> +* ARM Vectored Interrupt Controller
> +
> +One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
> +system for interrupt routing. For multiple controllers they can either be
> +nested or have the outputs wire-OR'd together.
> +
> +Required properties:
> +
> +- compatible : should be one of
> + "arm,pl190-vic"
> + "arm,pl192-vic"
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : The number of cells to define the interrupts. Must be 1 as
> + the VIC has no configuration options for interrupt sources. The cell is a u32
> + and defines the interrupt number.
> +- reg : The register bank for the VIC.
> +
> +Optional properties:
> +
> +- interrupts : Interrupt source for parent controllers if the VIC is nested.
> +
> +Example:
> +
> + vic0: interrupt-controller at 60000 {
> + compatible = "arm,pl192-vic";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + reg = <0x60000 0x1000>;
> + };
> diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
> index 4b71766..43e9d1a 100644
> --- a/arch/arm/common/Kconfig
> +++ b/arch/arm/common/Kconfig
> @@ -2,6 +2,7 @@ config ARM_GIC
> bool
>
> config ARM_VIC
> + select IRQ_DOMAIN
> bool
>
> config ARM_VIC_NR
> diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
> index 7aa4262..3f9c8f2 100644
> --- a/arch/arm/common/vic.c
> +++ b/arch/arm/common/vic.c
> @@ -22,6 +22,10 @@
> #include <linux/init.h>
> #include <linux/list.h>
> #include <linux/io.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> #include <linux/syscore_ops.h>
> #include <linux/device.h>
> #include <linux/amba/bus.h>
> @@ -29,7 +33,6 @@
> #include <asm/mach/irq.h>
> #include <asm/hardware/vic.h>
>
> -#ifdef CONFIG_PM
> /**
> * struct vic_device - VIC PM device
> * @irq: The IRQ number for the base of the VIC.
> @@ -40,6 +43,7 @@
> * @int_enable: Save for VIC_INT_ENABLE.
> * @soft_int: Save for VIC_INT_SOFT.
> * @protect: Save for VIC_PROTECT.
> + * @domain: The IRQ domain for the VIC.
> */
> struct vic_device {
> void __iomem *base;
> @@ -50,13 +54,13 @@ struct vic_device {
> u32 int_enable;
> u32 soft_int;
> u32 protect;
> + struct irq_domain domain;
> };
>
> /* we cannot allocate memory when VICs are initially registered */
> static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
>
> static int vic_id;
> -#endif /* CONFIG_PM */
>
> /**
> * vic_init2 - common initialisation code
> @@ -156,39 +160,50 @@ static int __init vic_pm_init(void)
> return 0;
> }
> late_initcall(vic_pm_init);
> +#endif /* CONFIG_PM */
>
> /**
> - * vic_pm_register - Register a VIC for later power management control
> + * vic_register() - Register a VIC.
> * @base: The base address of the VIC.
> * @irq: The base IRQ for the VIC.
> * @resume_sources: bitmask of interrupts allowed for resume sources.
> + * @node: The device tree node associated with the VIC.
> *
> * Register the VIC with the system device tree so that it can be notified
> * of suspend and resume requests and ensure that the correct actions are
> * taken to re-instate the settings on resume.
> + *
> + * This also configures the IRQ domain for the VIC.
> */
> -static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
> +static void __init vic_register(void __iomem *base, unsigned int irq,
> + u32 resume_sources, struct device_node *node)
> {
> struct vic_device *v;
>
> - if (vic_id >= ARRAY_SIZE(vic_devices))
> + if (vic_id >= ARRAY_SIZE(vic_devices)) {
> printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
> - else {
> - v = &vic_devices[vic_id];
> - v->base = base;
> - v->resume_sources = resume_sources;
> - v->irq = irq;
> - vic_id++;
> + return;
> }
> +
> + v = &vic_devices[vic_id];
> + v->base = base;
> + v->resume_sources = resume_sources;
> + v->irq = irq;
> + vic_id++;
> +
> + v->domain.irq_base = irq;
> + v->domain.nr_irq = 32;
> +#ifdef CONFIG_OF_IRQ
> + v->domain.of_node = of_node_get(node);
> + v->domain.ops = &irq_domain_simple_ops;
> +#endif /* CONFIG_OF */
> + irq_domain_add(&v->domain);
> }
> -#else
> -static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
> -#endif /* CONFIG_PM */
>
> static void vic_ack_irq(struct irq_data *d)
> {
> void __iomem *base = irq_data_get_irq_chip_data(d);
> - unsigned int irq = d->irq & 31;
> + unsigned int irq = d->hwirq;
> writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
> /* moreover, clear the soft-triggered, in case it was the reason */
> writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
> @@ -197,14 +212,14 @@ static void vic_ack_irq(struct irq_data *d)
> static void vic_mask_irq(struct irq_data *d)
> {
> void __iomem *base = irq_data_get_irq_chip_data(d);
> - unsigned int irq = d->irq & 31;
> + unsigned int irq = d->hwirq;
> writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
> }
>
> static void vic_unmask_irq(struct irq_data *d)
> {
> void __iomem *base = irq_data_get_irq_chip_data(d);
> - unsigned int irq = d->irq & 31;
> + unsigned int irq = d->hwirq;
> writel(1 << irq, base + VIC_INT_ENABLE);
> }
>
> @@ -226,7 +241,7 @@ static struct vic_device *vic_from_irq(unsigned int irq)
> static int vic_set_wake(struct irq_data *d, unsigned int on)
> {
> struct vic_device *v = vic_from_irq(d->irq);
> - unsigned int off = d->irq & 31;
> + unsigned int off = d->hwirq;
> u32 bit = 1 << off;
>
> if (!v)
> @@ -331,15 +346,9 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
> vic_set_irq_sources(base, irq_start, vic_sources);
> }
>
> -/**
> - * vic_init - initialise a vectored interrupt controller
> - * @base: iomem base address
> - * @irq_start: starting interrupt number, must be muliple of 32
> - * @vic_sources: bitmask of interrupt sources to allow
> - * @resume_sources: bitmask of interrupt sources to allow for resume
> - */
> -void __init vic_init(void __iomem *base, unsigned int irq_start,
> - u32 vic_sources, u32 resume_sources)
> +static void __init __vic_init(void __iomem *base, unsigned int irq_start,
> + u32 vic_sources, u32 resume_sources,
> + struct device_node *node)
> {
> unsigned int i;
> u32 cellid = 0;
> @@ -375,5 +384,46 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
>
> vic_set_irq_sources(base, irq_start, vic_sources);
>
> - vic_pm_register(base, irq_start, resume_sources);
> + vic_register(base, irq_start, resume_sources, node);
> +}
> +
> +/**
> + * vic_init() - initialise a vectored interrupt controller
> + * @base: iomem base address
> + * @irq_start: starting interrupt number, must be muliple of 32
> + * @vic_sources: bitmask of interrupt sources to allow
> + * @resume_sources: bitmask of interrupt sources to allow for resume
> + */
> +void __init vic_init(void __iomem *base, unsigned int irq_start,
> + u32 vic_sources, u32 resume_sources)
> +{
> + __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
> +}
> +
> +#ifdef CONFIG_OF
> +int __init vic_of_init(struct device_node *node, struct device_node *parent)
> +{
> + void __iomem *regs;
> + int irq_base;
> +
> + if (WARN(parent, "non-root VICs are not supported"))
> + return -EINVAL;
> +
> + regs = of_iomap(node, 0);
> + if (WARN_ON(!regs))
> + return -EIO;
> +
> + irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
> + if (WARN_ON(irq_base < 0))
> + goto out_unmap;
> +
> + __vic_init(regs, irq_base, ~0, ~0, node);
> +
> + return 0;
> +
> + out_unmap:
> + iounmap(regs);
> +
> + return -EIO;
> }
> +#endif /* CONFIG OF */
> diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
> index 5d72550..0135215 100644
> --- a/arch/arm/include/asm/hardware/vic.h
> +++ b/arch/arm/include/asm/hardware/vic.h
> @@ -41,7 +41,15 @@
> #define VIC_PL192_VECT_ADDR 0xF00
>
> #ifndef __ASSEMBLY__
> +#include <linux/compiler.h>
> +#include <linux/types.h>
> +
> +struct device_node;
> void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
> -#endif
>
> +#ifdef CONFIG_OF
> +int vic_of_init(struct device_node *node, struct device_node *parent);
> +#endif /* CONFIG_OF */
> +
> +#endif /* __ASSEMBLY__ */
> #endif
> --
> 1.7.4.1
>
^ permalink raw reply
* [PATCH] S3C2443: Add devname for hsmmc1 pclk
From: Heiko Stübner @ 2011-09-28 19:59 UTC (permalink / raw)
To: linux-arm-kernel
S3C2443 uses hsmmc1 as its only hsmmc device and for S3C2416/2450 it's
the second hsmmc channel with the same PCLKCON bit.
The hsmmc-if clocks on both systems already got a devname, as did the
hsmmc pclk for hsmmc0 on the S3C2416.
So to make it possible to identify the hsmmc1 pclk on S3C2416 add the
correct devname for it. The sclk name on S3C2443 also is s3c-sdhci.1.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/plat-s3c24xx/s3c2443-clock.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index b4b2fa1..6408650 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -416,6 +416,7 @@ static struct clk init_clocks[] = {
.ctrlbit = S3C2443_HCLKCON_DMA5,
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.1",
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_HSMMC,
--
1.7.2.3
^ permalink raw reply related
* [RFC PATCH 3/3] ARM: mm: add l2x0 suspend/resume support
From: Russell King - ARM Linux @ 2011-09-28 19:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E81AC1C.4090405@ti.com>
On Tue, Sep 27, 2011 at 04:27:32PM +0530, Santosh Shilimkar wrote:
> I agree. From various discussion so far, apart MX, nobody complained
> about C-version of the code. Hence the comment. If there are more
> platforms which needs it, then the asm version would be useful and
> should be preferred over C-version.
Santosh,
Can you also look at Barry Song's version of this infrastructure as
well? He posted it a couple of days ago:
Subject: [PATCH v2] ARM: cache-l2x0: add resume entry for l2 in secure mode
Message-ID: <1317007569-31213-1-git-send-email-Baohua.Song@csr.com>
with this diffstat:
4 files changed, 101 insertions(+), 9 deletions(-)
^ permalink raw reply
* [PATCH v4 3/3] arm/tegra: device tree support for ventana board
From: Olof Johansson @ 2011-09-28 18:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201109281516.42513.arnd@arndb.de>
On Wed, Sep 28, 2011 at 6:16 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Wednesday 28 September 2011, Peter De Schrijver wrote:
>> --- a/arch/arm/mach-tegra/board-dt.c
>> +++ b/arch/arm/mach-tegra/board-dt.c
>> @@ -47,7 +47,7 @@
>>
>> ?void harmony_pinmux_init(void);
>> ?void seaboard_pinmux_init(void);
>> -
>> +void ventana_pinmux_init(void);
>>
>> ?struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>> ? ? ? ? OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
>> @@ -95,6 +95,8 @@ static void __init tegra_dt_init(void)
>> ? ? ? ? ? ? ? ? harmony_pinmux_init();
>> ? ? ? ? else if (of_machine_is_compatible("nvidia,seaboard"))
>> ? ? ? ? ? ? ? ? seaboard_pinmux_init();
>> + ? ? ? else if (of_machine_is_compatible("nvidia,ventana"))
>> + ? ? ? ? ? ? ? ventana_pinmux_init();
>
> Are you (Peter, Colin, Olof) confident that this is not getting out
> of hand before it's getting better?
>
> If we are keeping the per-board pinmux configuration in the kernel
> for longer, I think it would be better to do this table-driven than
> having a list of top-level of_machine_is_compatible() statements
> and do something like:
>
> static struct {
> ? ? ? ?const char *machine;
> ? ? ? ?struct tegra_pingroup_config *config[];
> } pinmux_configs[] __initdata = {
> ? ? ? ?{ "nvidia,ventana", &ventana_pinmux },
> ? ? ? ?{ "nvidia,seaboard, &seaboard_pinmux },
> };
That is definitely a nicer solution. I didn't see a strong need to
switch to that model now since it should hopefully be a temporary
thing, but given Stephen's mention of Cardhu, I think it does make
sense.
Peter, care to respin this patch with the above solution instead?
Also, please print a warning if no match is found.
Thanks,
-Olof
^ permalink raw reply
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