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* [PATCH] ARM: EXYNOS: Add ARCH_EXYNOS and reorganize arch/arm/mach-exynos
From: Kyungmin Park @ 2011-10-03  4:02 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <001f01cc80e5$3abd1c80$b0375580$%kim@samsung.com>

Hi,

I'm afraid to change machine directory name again. mach-s5pv310 ->
mach-exynos4 -> mach-exynos.
As I remember linus blamed the renaming the file names are happened
frequently at ARM

Thank you,
Kyungmin Park

2011/10/2 Kukjin Kim <kgene.kim@samsung.com>:
> The arch/arm/mach-exynos4 directory (CONFIG_ARCH_EXYNOS4) has
> made for plaforms based on EXYNOS4 SoCs. But since upcoming
> Samsung's SoCs such as EXYNOS5 (ARM Cortex A15) can reuse most
> codes in current mach-exynos4, one mach-exynos directory will
> be used for them.
>
> This patch changes to CONFIG_ARCH_EXYNOS (arch/arm/mach-exynos)
> but keeps original CONFIG_ARCH_EXYNOS4 in mach-exynos/Kconfig to
> avoid changing in driver side.
>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Russell King <rmk+kernel@arm.linux.org.uk>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> ---
> NOTE: The codes for upcoming SoCs will be implemented soon.
>
> ?arch/arm/Kconfig ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?8 +-
> ?arch/arm/Makefile ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?2 +-
> ?arch/arm/configs/exynos4_defconfig ? ? ? ? ? ? ? ? | ? ?7 +--
> ?arch/arm/{mach-exynos4 => mach-exynos}/Kconfig ? ? | ? 41 +++++++++---
> ?arch/arm/{mach-exynos4 => mach-exynos}/Makefile ? ?| ? ?8 +-
> ?.../{mach-exynos4 => mach-exynos}/Makefile.boot ? ?| ? ?0
> ?.../clock-exynos4210.c ? ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?.../clock-exynos4212.c ? ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/clock.c ? ? | ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/cpu.c ? ? ? | ? 69 +++++++++++---------
> ?arch/arm/{mach-exynos4 => mach-exynos}/cpuidle.c ? | ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/dev-ahci.c ?| ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/dev-audio.c | ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/dev-dwmci.c | ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/dev-pd.c ? ?| ? ?0
> ?.../arm/{mach-exynos4 => mach-exynos}/dev-sysmmu.c | ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/dma.c ? ? ? | ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/headsmp.S ? | ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/hotplug.c ? | ? ?0
> ?.../include/mach/debug-macro.S ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?.../include/mach/dma.h ? ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?.../include/mach/dwmci.h ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?.../include/mach/entry-macro.S ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?.../include/mach/exynos4-clock.h ? ? ? ? ? ? ? ? ? | ? ?0
> ?.../include/mach/gpio.h ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/hardware.h ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/io.h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/irqs.h ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/map.h ? ? ? ? ? ? ? ? ? ? ? ? ? ? | ? 32 ++++++----
> ?.../include/mach/memory.h ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/pm-core.h ? ? ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?.../include/mach/pmu.h ? ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?.../include/mach/regs-audss.h ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/regs-clock.h ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/regs-gpio.h ? ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?.../include/mach/regs-irq.h ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/regs-mct.h ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/regs-mem.h ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/regs-pmu.h ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/regs-sysmmu.h ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?.../include/mach/regs-usb-phy.h ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/sysmmu.h ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/system.h ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/timex.h ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?.../include/mach/uncompress.h ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?.../include/mach/vmalloc.h ? ? ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/init.c ? ? ?| ? ?0
> ?.../{mach-exynos4 => mach-exynos}/irq-combiner.c ? | ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/irq-eint.c ?| ? ?0
> ?.../mach-armlex4210.c ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/mach-nuri.c | ? ?0
> ?.../{mach-exynos4 => mach-exynos}/mach-origen.c ? ?| ? ?0
> ?.../{mach-exynos4 => mach-exynos}/mach-smdk4x12.c ?| ? ?0
> ?.../{mach-exynos4 => mach-exynos}/mach-smdkv310.c ?| ? ?0
> ?.../mach-universal_c210.c ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/mct.c ? ? ? | ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/platsmp.c ? | ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/pm.c ? ? ? ?| ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/pmu.c ? ? ? | ? ?0
> ?.../arm/{mach-exynos4 => mach-exynos}/setup-fimc.c | ? ?0
> ?.../{mach-exynos4 => mach-exynos}/setup-fimd0.c ? ?| ? ?0
> ?.../arm/{mach-exynos4 => mach-exynos}/setup-i2c0.c | ? ?0
> ?.../arm/{mach-exynos4 => mach-exynos}/setup-i2c1.c | ? ?0
> ?.../arm/{mach-exynos4 => mach-exynos}/setup-i2c2.c | ? ?0
> ?.../arm/{mach-exynos4 => mach-exynos}/setup-i2c3.c | ? ?0
> ?.../arm/{mach-exynos4 => mach-exynos}/setup-i2c4.c | ? ?0
> ?.../arm/{mach-exynos4 => mach-exynos}/setup-i2c5.c | ? ?0
> ?.../arm/{mach-exynos4 => mach-exynos}/setup-i2c6.c | ? ?0
> ?.../arm/{mach-exynos4 => mach-exynos}/setup-i2c7.c | ? ?0
> ?.../{mach-exynos4 => mach-exynos}/setup-keypad.c ? | ? ?0
> ?.../setup-sdhci-gpio.c ? ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?0
> ?.../{mach-exynos4 => mach-exynos}/setup-sdhci.c ? ?| ? ?0
> ?.../{mach-exynos4 => mach-exynos}/setup-usb-phy.c ?| ? ?0
> ?arch/arm/{mach-exynos4 => mach-exynos}/sleep.S ? ? | ? ?0
> ?arch/arm/plat-s5p/Kconfig ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?2 +-
> ?arch/arm/plat-s5p/cpu.c ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?6 +-
> ?arch/arm/plat-samsung/include/plat/exynos4.h ? ? ? | ? ?6 +-
> ?77 files changed, 104 insertions(+), 77 deletions(-)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/Kconfig (91%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/Makefile (89%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/Makefile.boot (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/clock-exynos4210.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/clock-exynos4212.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/clock.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/cpu.c (91%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/cpuidle.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/dev-ahci.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/dev-audio.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/dev-dwmci.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/dev-pd.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/dev-sysmmu.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/dma.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/headsmp.S (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/hotplug.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/debug-macro.S (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/dma.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/dwmci.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/entry-macro.S (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/exynos4-clock.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/gpio.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/hardware.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/io.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/irqs.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/map.h (93%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/memory.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/pm-core.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/pmu.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/regs-audss.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/regs-clock.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/regs-gpio.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/regs-irq.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/regs-mct.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/regs-mem.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/regs-pmu.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/regs-sysmmu.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/regs-usb-phy.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/sysmmu.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/system.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/timex.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/uncompress.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/include/mach/vmalloc.h (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/init.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/irq-combiner.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/irq-eint.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/mach-armlex4210.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/mach-nuri.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/mach-origen.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/mach-smdk4x12.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/mach-smdkv310.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/mach-universal_c210.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/mct.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/platsmp.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/pm.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/pmu.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-fimc.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-fimd0.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-i2c0.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-i2c1.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-i2c2.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-i2c3.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-i2c4.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-i2c5.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-i2c6.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-i2c7.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-keypad.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-sdhci-gpio.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-sdhci.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/setup-usb-phy.c (100%)
> ?rename arch/arm/{mach-exynos4 => mach-exynos}/sleep.S (100%)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index bea81d0..21dbf01 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -781,8 +781,8 @@ config ARCH_S5PV210
> ? ? ? ?help
> ? ? ? ? ?Samsung S5PV210/S5PC110 series based systems
>
> -config ARCH_EXYNOS4
> - ? ? ? bool "Samsung EXYNOS4"
> +config ARCH_EXYNOS
> + ? ? ? bool "SAMSUNG EXYNOS"
> ? ? ? ?select CPU_V7
> ? ? ? ?select ARCH_SPARSEMEM_ENABLE
> ? ? ? ?select ARCH_HAS_HOLES_MEMORYMODEL
> @@ -795,7 +795,7 @@ config ARCH_EXYNOS4
> ? ? ? ?select HAVE_S3C2410_I2C if I2C
> ? ? ? ?select HAVE_S3C2410_WATCHDOG if WATCHDOG
> ? ? ? ?help
> - ? ? ? ? Samsung EXYNOS4 series based systems
> + ? ? ? ? Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
>
> ?config ARCH_SHARK
> ? ? ? ?bool "Shark"
> @@ -1021,7 +1021,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
>
> ?source "arch/arm/mach-s5pv210/Kconfig"
>
> -source "arch/arm/mach-exynos4/Kconfig"
> +source "arch/arm/mach-exynos/Kconfig"
>
> ?source "arch/arm/mach-shmobile/Kconfig"
>
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 70c424e..289439e 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -177,7 +177,7 @@ machine-$(CONFIG_ARCH_S3C64XX) ? ? ? ? ? ? ?:= s3c64xx
> ?machine-$(CONFIG_ARCH_S5P64X0) ? ? ? ? := s5p64x0
> ?machine-$(CONFIG_ARCH_S5PC100) ? ? ? ? := s5pc100
> ?machine-$(CONFIG_ARCH_S5PV210) ? ? ? ? := s5pv210
> -machine-$(CONFIG_ARCH_EXYNOS4) ? ? ? ? := exynos4
> +machine-$(CONFIG_ARCH_EXYNOS4) ? ? ? ? := exynos
> ?machine-$(CONFIG_ARCH_SA1100) ? ? ? ? ?:= sa1100
> ?machine-$(CONFIG_ARCH_SHARK) ? ? ? ? ? := shark
> ?machine-$(CONFIG_ARCH_SHMOBILE) ? ? ? ?:= shmobile
> diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig
> index cd40bb5..b0d3c13 100644
> --- a/arch/arm/configs/exynos4_defconfig
> +++ b/arch/arm/configs/exynos4_defconfig
> @@ -4,10 +4,9 @@ CONFIG_KALLSYMS_ALL=y
> ?CONFIG_MODULES=y
> ?CONFIG_MODULE_UNLOAD=y
> ?# CONFIG_BLK_DEV_BSG is not set
> -CONFIG_ARCH_EXYNOS4=y
> +CONFIG_ARCH_EXYNOS=y
> ?CONFIG_S3C_LOWLEVEL_UART_PORT=1
> ?CONFIG_MACH_SMDKC210=y
> -CONFIG_MACH_SMDKV310=y
> ?CONFIG_MACH_ARMLEX4210=y
> ?CONFIG_MACH_UNIVERSAL_C210=y
> ?CONFIG_MACH_NURI=y
> @@ -16,7 +15,6 @@ CONFIG_NO_HZ=y
> ?CONFIG_HIGH_RES_TIMERS=y
> ?CONFIG_SMP=y
> ?CONFIG_NR_CPUS=2
> -CONFIG_HOTPLUG_CPU=y
> ?CONFIG_PREEMPT=y
> ?CONFIG_AEABI=y
> ?CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
> @@ -61,12 +59,9 @@ CONFIG_DETECT_HUNG_TASK=y
> ?CONFIG_DEBUG_RT_MUTEXES=y
> ?CONFIG_DEBUG_SPINLOCK=y
> ?CONFIG_DEBUG_MUTEXES=y
> -CONFIG_DEBUG_SPINLOCK_SLEEP=y
> ?CONFIG_DEBUG_INFO=y
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
> ?CONFIG_SYSCTL_SYSCALL_CHECK=y
> ?CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> ?CONFIG_DEBUG_LL=y
> ?CONFIG_EARLY_PRINTK=y
> ?CONFIG_DEBUG_S3C_UART=1
> diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos/Kconfig
> similarity index 91%
> rename from arch/arm/mach-exynos4/Kconfig
> rename to arch/arm/mach-exynos/Kconfig
> index 6dfde07..999989e 100644
> --- a/arch/arm/mach-exynos4/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -1,4 +1,4 @@
> -# arch/arm/mach-exynos4/Kconfig
> +# arch/arm/mach-exynos/Kconfig
> ?#
> ?# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> ?# ? ? ? ? ? ? ?http://www.samsung.com/
> @@ -7,21 +7,42 @@
>
> ?# Configuration options for the EXYNOS4
>
> -if ARCH_EXYNOS4
> +if ARCH_EXYNOS
> +
> +menu "SAMSUNG EXYNOS SoCs Support"
> +
> +choice
> + ? ? ? prompt "EXYNOS System Type"
> + ? ? ? default ARCH_EXYNOS4
> +
> +config ARCH_EXYNOS4
> + ? ? ? bool "SAMSUNG EXYNOS4"
> + ? ? ? help
> + ? ? ? ? Samsung EXYNOS4 SoCs based systems
> +
> +endchoice
> +
> +comment "EXYNOS SoCs"
>
> ?config CPU_EXYNOS4210
> - ? ? ? bool
> + ? ? ? bool "SAMSUNG EXYNOS4210"
> + ? ? ? default y
> + ? ? ? depends on ARCH_EXYNOS4
> ? ? ? ?select SAMSUNG_DMADEV
> ? ? ? ?help
> ? ? ? ? ?Enable EXYNOS4210 CPU support
>
> ?config SOC_EXYNOS4212
> - ? ? ? bool
> + ? ? ? bool "SAMSUNG EXYNOS4212"
> + ? ? ? default y
> + ? ? ? depends on ARCH_EXYNOS4
> ? ? ? ?help
> ? ? ? ? ?Enable EXYNOS4212 SoC support
>
> ?config SOC_EXYNOS4412
> - ? ? ? bool
> + ? ? ? bool "SAMSUNG EXYNOS4412"
> + ? ? ? default y
> + ? ? ? depends on ARCH_EXYNOS4
> ? ? ? ?help
> ? ? ? ? ?Enable EXYNOS4412 SoC support
>
> @@ -119,7 +140,7 @@ config EXYNOS4_SETUP_USB_PHY
>
> ?# machine support
>
> -menu "EXYNOS4 Machines"
> +if ARCH_EXYNOS4
>
> ?comment "EXYNOS4210 Boards"
>
> @@ -286,12 +307,11 @@ config MACH_SMDK4412
> ? ? ? ?select MACH_SMDK4212
> ? ? ? ?help
> ? ? ? ? ?Machine support for Samsung SMDK4412
> +endif
>
> -endmenu
> -
> -comment "Configuration for HSMMC bus width"
> +if ARCH_EXYNOS4
>
> -menu "Use 8-bit bus width"
> +comment "Configuration for HSMMC 8-bit bus width"
>
> ?config EXYNOS4_SDHCI_CH0_8BIT
> ? ? ? ?bool "Channel 0 with 8-bit bus"
> @@ -304,6 +324,7 @@ config EXYNOS4_SDHCI_CH2_8BIT
> ? ? ? ?help
> ? ? ? ? ?Support HSMMC Channel 2 8-bit bus.
> ? ? ? ? ?If selected, Channel 3 is disabled.
> +endif
>
> ?endmenu
>
> diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos/Makefile
> similarity index 89%
> rename from arch/arm/mach-exynos4/Makefile
> rename to arch/arm/mach-exynos/Makefile
> index c9b2e1f..fa715eb 100644
> --- a/arch/arm/mach-exynos4/Makefile
> +++ b/arch/arm/mach-exynos/Makefile
> @@ -1,4 +1,4 @@
> -# arch/arm/mach-exynos4/Makefile
> +# arch/arm/mach-exynos/Makefile
> ?#
> ?# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> ?# ? ? ? ? ? ? ?http://www.samsung.com/
> @@ -12,8 +12,8 @@ obj- ? ? ? ? ? ? ? ? ? ? ? ? ?:=
>
> ?# Core support for EXYNOS4 system
>
> -obj-$(CONFIG_ARCH_EXYNOS4) ? ? += cpu.o init.o clock.o irq-combiner.o
> -obj-$(CONFIG_ARCH_EXYNOS4) ? ? += setup-i2c0.o irq-eint.o dma.o pmu.o
> +obj-$(CONFIG_ARCH_EXYNOS) ? ? ?+= cpu.o init.o clock.o irq-combiner.o setup-i2c0.o
> +obj-$(CONFIG_ARCH_EXYNOS4) ? ? += irq-eint.o dma.o pmu.o
> ?obj-$(CONFIG_CPU_EXYNOS4210) ? += clock-exynos4210.o
> ?obj-$(CONFIG_SOC_EXYNOS4212) ? += clock-exynos4212.o
> ?obj-$(CONFIG_PM) ? ? ? ? ? ? ? += pm.o sleep.o
> @@ -39,7 +39,7 @@ obj-$(CONFIG_MACH_SMDK4412) ? ? ? ? ? += mach-smdk4x12.o
>
> ?# device support
>
> -obj-y ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?+= dev-audio.o
> +obj-$(CONFIG_ARCH_EXYNOS4) ? ? ? ? ? ? += dev-audio.o
> ?obj-$(CONFIG_EXYNOS4_DEV_AHCI) ? ? ? ? += dev-ahci.o
> ?obj-$(CONFIG_EXYNOS4_DEV_PD) ? ? ? ? ? += dev-pd.o
> ?obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) ? ? ? += dev-sysmmu.o
> diff --git a/arch/arm/mach-exynos4/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
> similarity index 100%
> rename from arch/arm/mach-exynos4/Makefile.boot
> rename to arch/arm/mach-exynos/Makefile.boot
> diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/clock-exynos4210.c
> rename to arch/arm/mach-exynos/clock-exynos4210.c
> diff --git a/arch/arm/mach-exynos4/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/clock-exynos4212.c
> rename to arch/arm/mach-exynos/clock-exynos4212.c
> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos/clock.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/clock.c
> rename to arch/arm/mach-exynos/clock.c
> diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos/cpu.c
> similarity index 91%
> rename from arch/arm/mach-exynos4/cpu.c
> rename to arch/arm/mach-exynos/cpu.c
> index 5b1765b..90ec247 100644
> --- a/arch/arm/mach-exynos4/cpu.c
> +++ b/arch/arm/mach-exynos/cpu.c
> @@ -1,4 +1,4 @@
> -/* linux/arch/arm/mach-exynos4/cpu.c
> +/* linux/arch/arm/mach-exynos/cpu.c
> ?*
> ?* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> ?* ? ? ? ? ? ? http://www.samsung.com
> @@ -40,28 +40,47 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
> ?extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
>
> ?/* Initial IO mappings */
> -static struct map_desc exynos4_iodesc[] __initdata = {
> +static struct map_desc exynos_iodesc[] __initdata = {
> ? ? ? ?{
> ? ? ? ? ? ? ? ?.virtual ? ? ? ?= (unsigned long)S5P_VA_SYSTIMER,
> - ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
> + ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS_PA_SYSTIMER),
> ? ? ? ? ? ? ? ?.length ? ? ? ? = SZ_4K,
> - ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
> - ? ? ? }, {
> - ? ? ? ? ? ? ? .virtual ? ? ? ?= (unsigned long)S5P_VA_CMU,
> - ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS4_PA_CMU),
> - ? ? ? ? ? ? ? .length ? ? ? ? = SZ_128K,
> ? ? ? ? ? ? ? ?.type ? ? ? ? ? = MT_DEVICE,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.virtual ? ? ? ?= (unsigned long)S5P_VA_PMU,
> - ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS4_PA_PMU),
> + ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS_PA_PMU),
> ? ? ? ? ? ? ? ?.length ? ? ? ? = SZ_64K,
> ? ? ? ? ? ? ? ?.type ? ? ? ? ? = MT_DEVICE,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.virtual ? ? ? ?= (unsigned long)S5P_VA_COMBINER_BASE,
> - ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS4_PA_COMBINER),
> + ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS_PA_COMBINER),
> ? ? ? ? ? ? ? ?.length ? ? ? ? = SZ_4K,
> ? ? ? ? ? ? ? ?.type ? ? ? ? ? = MT_DEVICE,
> ? ? ? ?}, {
> + ? ? ? ? ? ? ? .virtual ? ? ? ?= (unsigned long)S5P_VA_GIC_CPU,
> + ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS_PA_GIC_CPU),
> + ? ? ? ? ? ? ? .length ? ? ? ? = SZ_64K,
> + ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
> + ? ? ? }, {
> + ? ? ? ? ? ? ? .virtual ? ? ? ?= (unsigned long)S5P_VA_GIC_DIST,
> + ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS_PA_GIC_DIST),
> + ? ? ? ? ? ? ? .length ? ? ? ? = SZ_64K,
> + ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
> + ? ? ? }, {
> + ? ? ? ? ? ? ? .virtual ? ? ? ?= (unsigned long)S3C_VA_UART,
> + ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(S3C_PA_UART),
> + ? ? ? ? ? ? ? .length ? ? ? ? = SZ_512K,
> + ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
> + ? ? ? },
> +};
> +
> +static struct map_desc exynos4_iodesc[] __initdata = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .virtual ? ? ? ?= (unsigned long)S5P_VA_CMU,
> + ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS4_PA_CMU),
> + ? ? ? ? ? ? ? .length ? ? ? ? = SZ_128K,
> + ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
> + ? ? ? }, {
> ? ? ? ? ? ? ? ?.virtual ? ? ? ?= (unsigned long)S5P_VA_COREPERI_BASE,
> ? ? ? ? ? ? ? ?.pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS4_PA_COREPERI),
> ? ? ? ? ? ? ? ?.length ? ? ? ? = SZ_8K,
> @@ -92,11 +111,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
> ? ? ? ? ? ? ? ?.length ? ? ? ? = SZ_4K,
> ? ? ? ? ? ? ? ?.type ? ? ? ? ? = MT_DEVICE,
> ? ? ? ?}, {
> - ? ? ? ? ? ? ? .virtual ? ? ? ?= (unsigned long)S3C_VA_UART,
> - ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(S3C_PA_UART),
> - ? ? ? ? ? ? ? .length ? ? ? ? = SZ_512K,
> - ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
> - ? ? ? }, {
> ? ? ? ? ? ? ? ?.virtual ? ? ? ?= (unsigned long)S5P_VA_SROMC,
> ? ? ? ? ? ? ? ?.pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS4_PA_SROMC),
> ? ? ? ? ? ? ? ?.length ? ? ? ? = SZ_4K,
> @@ -106,16 +120,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
> ? ? ? ? ? ? ? ?.pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS4_PA_HSPHY),
> ? ? ? ? ? ? ? ?.length ? ? ? ? = SZ_4K,
> ? ? ? ? ? ? ? ?.type ? ? ? ? ? = MT_DEVICE,
> - ? ? ? }, {
> - ? ? ? ? ? ? ? .virtual ? ? ? ?= (unsigned long)S5P_VA_GIC_CPU,
> - ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
> - ? ? ? ? ? ? ? .length ? ? ? ? = SZ_64K,
> - ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
> - ? ? ? }, {
> - ? ? ? ? ? ? ? .virtual ? ? ? ?= (unsigned long)S5P_VA_GIC_DIST,
> - ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
> - ? ? ? ? ? ? ? .length ? ? ? ? = SZ_64K,
> - ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
> ? ? ? ?},
> ?};
>
> @@ -137,7 +141,7 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
> ? ? ? ?},
> ?};
>
> -static void exynos4_idle(void)
> +static void exynos_idle(void)
> ?{
> ? ? ? ?if (!need_resched())
> ? ? ? ? ? ? ? ?cpu_do_idle();
> @@ -151,12 +155,13 @@ static void exynos4_sw_reset(void)
> ?}
>
> ?/*
> - * exynos4_map_io
> + * exynos_map_io
> ?*
> ?* register the standard cpu IO areas
> ?*/
> ?void __init exynos4_map_io(void)
> ?{
> + ? ? ? iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
> ? ? ? ?iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
>
> ? ? ? ?if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
> @@ -250,7 +255,6 @@ static int __init exynos4_core_init(void)
> ?{
> ? ? ? ?return sysdev_class_register(&exynos4_sysclass);
> ?}
> -
> ?core_initcall(exynos4_core_init);
>
> ?#ifdef CONFIG_CACHE_L2X0
> @@ -279,15 +283,16 @@ static int __init exynos4_l2x0_cache_init(void)
> ?early_initcall(exynos4_l2x0_cache_init);
> ?#endif
>
> -int __init exynos4_init(void)
> +int __init exynos_init(void)
> ?{
> - ? ? ? printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
> + ? ? ? printk(KERN_INFO "EXYNOS: Initializing architecture\n");
>
> ? ? ? ?/* set idle function */
> - ? ? ? pm_idle = exynos4_idle;
> + ? ? ? pm_idle = exynos_idle;
>
> ? ? ? ?/* set sw_reset function */
> - ? ? ? s5p_reset_hook = exynos4_sw_reset;
> + ? ? ? if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
> + ? ? ? ? ? ? ? s5p_reset_hook = exynos4_sw_reset;
>
> ? ? ? ?return sysdev_register(&exynos4_sysdev);
> ?}
> diff --git a/arch/arm/mach-exynos4/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/cpuidle.c
> rename to arch/arm/mach-exynos/cpuidle.c
> diff --git a/arch/arm/mach-exynos4/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/dev-ahci.c
> rename to arch/arm/mach-exynos/dev-ahci.c
> diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/dev-audio.c
> rename to arch/arm/mach-exynos/dev-audio.c
> diff --git a/arch/arm/mach-exynos4/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/dev-dwmci.c
> rename to arch/arm/mach-exynos/dev-dwmci.c
> diff --git a/arch/arm/mach-exynos4/dev-pd.c b/arch/arm/mach-exynos/dev-pd.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/dev-pd.c
> rename to arch/arm/mach-exynos/dev-pd.c
> diff --git a/arch/arm/mach-exynos4/dev-sysmmu.c b/arch/arm/mach-exynos/dev-sysmmu.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/dev-sysmmu.c
> rename to arch/arm/mach-exynos/dev-sysmmu.c
> diff --git a/arch/arm/mach-exynos4/dma.c b/arch/arm/mach-exynos/dma.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/dma.c
> rename to arch/arm/mach-exynos/dma.c
> diff --git a/arch/arm/mach-exynos4/headsmp.S b/arch/arm/mach-exynos/headsmp.S
> similarity index 100%
> rename from arch/arm/mach-exynos4/headsmp.S
> rename to arch/arm/mach-exynos/headsmp.S
> diff --git a/arch/arm/mach-exynos4/hotplug.c b/arch/arm/mach-exynos/hotplug.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/hotplug.c
> rename to arch/arm/mach-exynos/hotplug.c
> diff --git a/arch/arm/mach-exynos4/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/debug-macro.S
> rename to arch/arm/mach-exynos/include/mach/debug-macro.S
> diff --git a/arch/arm/mach-exynos4/include/mach/dma.h b/arch/arm/mach-exynos/include/mach/dma.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/dma.h
> rename to arch/arm/mach-exynos/include/mach/dma.h
> diff --git a/arch/arm/mach-exynos4/include/mach/dwmci.h b/arch/arm/mach-exynos/include/mach/dwmci.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/dwmci.h
> rename to arch/arm/mach-exynos/include/mach/dwmci.h
> diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/entry-macro.S
> rename to arch/arm/mach-exynos/include/mach/entry-macro.S
> diff --git a/arch/arm/mach-exynos4/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/include/mach/exynos4-clock.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/exynos4-clock.h
> rename to arch/arm/mach-exynos/include/mach/exynos4-clock.h
> diff --git a/arch/arm/mach-exynos4/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/gpio.h
> rename to arch/arm/mach-exynos/include/mach/gpio.h
> diff --git a/arch/arm/mach-exynos4/include/mach/hardware.h b/arch/arm/mach-exynos/include/mach/hardware.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/hardware.h
> rename to arch/arm/mach-exynos/include/mach/hardware.h
> diff --git a/arch/arm/mach-exynos4/include/mach/io.h b/arch/arm/mach-exynos/include/mach/io.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/io.h
> rename to arch/arm/mach-exynos/include/mach/io.h
> diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/irqs.h
> rename to arch/arm/mach-exynos/include/mach/irqs.h
> diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> similarity index 93%
> rename from arch/arm/mach-exynos4/include/mach/map.h
> rename to arch/arm/mach-exynos/include/mach/map.h
> index 918a979..058541d 100644
> --- a/arch/arm/mach-exynos4/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -1,4 +1,4 @@
> -/* linux/arch/arm/mach-exynos4/include/mach/map.h
> +/* linux/arch/arm/mach-exynos/include/mach/map.h
> ?*
> ?* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> ?* ? ? ? ? ? ? http://www.samsung.com/
> @@ -145,39 +145,45 @@
> ?#define S3C_PA_IIC5 ? ? ? ? ? ? ? ? ? ?EXYNOS4_PA_IIC(5)
> ?#define S3C_PA_IIC6 ? ? ? ? ? ? ? ? ? ?EXYNOS4_PA_IIC(6)
> ?#define S3C_PA_IIC7 ? ? ? ? ? ? ? ? ? ?EXYNOS4_PA_IIC(7)
> -#define SAMSUNG_PA_ADC ? ? ? ? ? ? ? ? EXYNOS4_PA_ADC
> -#define SAMSUNG_PA_ADC1 ? ? ? ? ? ? ? ? ? ? ? ?EXYNOS4_PA_ADC1
> ?#define S3C_PA_RTC ? ? ? ? ? ? ? ? ? ? EXYNOS4_PA_RTC
> ?#define S3C_PA_WDT ? ? ? ? ? ? ? ? ? ? EXYNOS4_PA_WATCHDOG
> +#define S3C_PA_UART ? ? ? ? ? ? ? ? ? ?EXYNOS4_PA_UART
>
> ?#define S5P_PA_CHIPID ? ? ? ? ? ? ? ? ?EXYNOS4_PA_CHIPID
> +#define S5P_PA_EHCI ? ? ? ? ? ? ? ? ? ?EXYNOS4_PA_EHCI
> ?#define S5P_PA_FIMC0 ? ? ? ? ? ? ? ? ? EXYNOS4_PA_FIMC0
> ?#define S5P_PA_FIMC1 ? ? ? ? ? ? ? ? ? EXYNOS4_PA_FIMC1
> ?#define S5P_PA_FIMC2 ? ? ? ? ? ? ? ? ? EXYNOS4_PA_FIMC2
> ?#define S5P_PA_FIMC3 ? ? ? ? ? ? ? ? ? EXYNOS4_PA_FIMC3
> +#define S5P_PA_FIMD0 ? ? ? ? ? ? ? ? ? EXYNOS4_PA_FIMD0
> +#define S5P_PA_HDMI ? ? ? ? ? ? ? ? ? ?EXYNOS4_PA_HDMI
> +#define S5P_PA_IIC_HDMIPHY ? ? ? ? ? ? EXYNOS4_PA_IIC_HDMIPHY
> +#define S5P_PA_MFC ? ? ? ? ? ? ? ? ? ? EXYNOS4_PA_MFC
> ?#define S5P_PA_MIPI_CSIS0 ? ? ? ? ? ? ?EXYNOS4_PA_MIPI_CSIS0
> ?#define S5P_PA_MIPI_CSIS1 ? ? ? ? ? ? ?EXYNOS4_PA_MIPI_CSIS1
> -#define S5P_PA_FIMD0 ? ? ? ? ? ? ? ? ? EXYNOS4_PA_FIMD0
> +#define S5P_PA_MIXER ? ? ? ? ? ? ? ? ? EXYNOS4_PA_MIXER
> ?#define S5P_PA_ONENAND ? ? ? ? ? ? ? ? EXYNOS4_PA_ONENAND
> ?#define S5P_PA_ONENAND_DMA ? ? ? ? ? ? EXYNOS4_PA_ONENAND_DMA
> +#define S5P_PA_SDO ? ? ? ? ? ? ? ? ? ? EXYNOS4_PA_SDO
> ?#define S5P_PA_SDRAM ? ? ? ? ? ? ? ? ? EXYNOS4_PA_SDRAM
> ?#define S5P_PA_SROMC ? ? ? ? ? ? ? ? ? EXYNOS4_PA_SROMC
> -#define S5P_PA_MFC ? ? ? ? ? ? ? ? ? ? EXYNOS4_PA_MFC
> ?#define S5P_PA_SYSCON ? ? ? ? ? ? ? ? ?EXYNOS4_PA_SYSCON
> ?#define S5P_PA_TIMER ? ? ? ? ? ? ? ? ? EXYNOS4_PA_TIMER
> -#define S5P_PA_EHCI ? ? ? ? ? ? ? ? ? ?EXYNOS4_PA_EHCI
> -
> -#define S5P_PA_SDO ? ? ? ? ? ? ? ? ? ? EXYNOS4_PA_SDO
> ?#define S5P_PA_VP ? ? ? ? ? ? ? ? ? ? ?EXYNOS4_PA_VP
> -#define S5P_PA_MIXER ? ? ? ? ? ? ? ? ? EXYNOS4_PA_MIXER
> -#define S5P_PA_HDMI ? ? ? ? ? ? ? ? ? ?EXYNOS4_PA_HDMI
> -#define S5P_PA_IIC_HDMIPHY ? ? ? ? ? ? EXYNOS4_PA_IIC_HDMIPHY
>
> +#define SAMSUNG_PA_ADC ? ? ? ? ? ? ? ? EXYNOS4_PA_ADC
> +#define SAMSUNG_PA_ADC1 ? ? ? ? ? ? ? ? ? ? ? ?EXYNOS4_PA_ADC1
> ?#define SAMSUNG_PA_KEYPAD ? ? ? ? ? ? ?EXYNOS4_PA_KEYPAD
>
> -/* UART */
> +#define EXYNOS_PA_COMBINER ? ? ? ? ? ? EXYNOS4_PA_COMBINER
> +#define EXYNOS_PA_GIC_CPU ? ? ? ? ? ? ?EXYNOS4_PA_GIC_CPU
> +#define EXYNOS_PA_GIC_DIST ? ? ? ? ? ? EXYNOS4_PA_GIC_DIST
> +#define EXYNOS_PA_PMU ? ? ? ? ? ? ? ? ?EXYNOS4_PA_PMU
> +#define EXYNOS_PA_SYSTIMER ? ? ? ? ? ? EXYNOS4_PA_SYSTIMER
>
> -#define S3C_PA_UART ? ? ? ? ? ? ? ? ? ?EXYNOS4_PA_UART
> +/* Compatibility UART */
> +
> +#define S3C_VA_UARTx(x) ? ? ? ? ? ? ? ? ? ? ? ?(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
>
> ?#define S5P_PA_UART(x) ? ? ? ? ? ? ? ? (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
> ?#define S5P_PA_UART0 ? ? ? ? ? ? ? ? ? S5P_PA_UART(0)
> diff --git a/arch/arm/mach-exynos4/include/mach/memory.h b/arch/arm/mach-exynos/include/mach/memory.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/memory.h
> rename to arch/arm/mach-exynos/include/mach/memory.h
> diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/pm-core.h
> rename to arch/arm/mach-exynos/include/mach/pm-core.h
> diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/pmu.h
> rename to arch/arm/mach-exynos/include/mach/pmu.h
> diff --git a/arch/arm/mach-exynos4/include/mach/regs-audss.h b/arch/arm/mach-exynos/include/mach/regs-audss.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/regs-audss.h
> rename to arch/arm/mach-exynos/include/mach/regs-audss.h
> diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/regs-clock.h
> rename to arch/arm/mach-exynos/include/mach/regs-clock.h
> diff --git a/arch/arm/mach-exynos4/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/regs-gpio.h
> rename to arch/arm/mach-exynos/include/mach/regs-gpio.h
> diff --git a/arch/arm/mach-exynos4/include/mach/regs-irq.h b/arch/arm/mach-exynos/include/mach/regs-irq.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/regs-irq.h
> rename to arch/arm/mach-exynos/include/mach/regs-irq.h
> diff --git a/arch/arm/mach-exynos4/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/regs-mct.h
> rename to arch/arm/mach-exynos/include/mach/regs-mct.h
> diff --git a/arch/arm/mach-exynos4/include/mach/regs-mem.h b/arch/arm/mach-exynos/include/mach/regs-mem.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/regs-mem.h
> rename to arch/arm/mach-exynos/include/mach/regs-mem.h
> diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/regs-pmu.h
> rename to arch/arm/mach-exynos/include/mach/regs-pmu.h
> diff --git a/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
> rename to arch/arm/mach-exynos/include/mach/regs-sysmmu.h
> diff --git a/arch/arm/mach-exynos4/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/regs-usb-phy.h
> rename to arch/arm/mach-exynos/include/mach/regs-usb-phy.h
> diff --git a/arch/arm/mach-exynos4/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/sysmmu.h
> rename to arch/arm/mach-exynos/include/mach/sysmmu.h
> diff --git a/arch/arm/mach-exynos4/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/system.h
> rename to arch/arm/mach-exynos/include/mach/system.h
> diff --git a/arch/arm/mach-exynos4/include/mach/timex.h b/arch/arm/mach-exynos/include/mach/timex.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/timex.h
> rename to arch/arm/mach-exynos/include/mach/timex.h
> diff --git a/arch/arm/mach-exynos4/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/uncompress.h
> rename to arch/arm/mach-exynos/include/mach/uncompress.h
> diff --git a/arch/arm/mach-exynos4/include/mach/vmalloc.h b/arch/arm/mach-exynos/include/mach/vmalloc.h
> similarity index 100%
> rename from arch/arm/mach-exynos4/include/mach/vmalloc.h
> rename to arch/arm/mach-exynos/include/mach/vmalloc.h
> diff --git a/arch/arm/mach-exynos4/init.c b/arch/arm/mach-exynos/init.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/init.c
> rename to arch/arm/mach-exynos/init.c
> diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos/irq-combiner.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/irq-combiner.c
> rename to arch/arm/mach-exynos/irq-combiner.c
> diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/irq-eint.c
> rename to arch/arm/mach-exynos/irq-eint.c
> diff --git a/arch/arm/mach-exynos4/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/mach-armlex4210.c
> rename to arch/arm/mach-exynos/mach-armlex4210.c
> diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/mach-nuri.c
> rename to arch/arm/mach-exynos/mach-nuri.c
> diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/mach-origen.c
> rename to arch/arm/mach-exynos/mach-origen.c
> diff --git a/arch/arm/mach-exynos4/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/mach-smdk4x12.c
> rename to arch/arm/mach-exynos/mach-smdk4x12.c
> diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/mach-smdkv310.c
> rename to arch/arm/mach-exynos/mach-smdkv310.c
> diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/mach-universal_c210.c
> rename to arch/arm/mach-exynos/mach-universal_c210.c
> diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos/mct.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/mct.c
> rename to arch/arm/mach-exynos/mct.c
> diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/platsmp.c
> rename to arch/arm/mach-exynos/platsmp.c
> diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos/pm.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/pm.c
> rename to arch/arm/mach-exynos/pm.c
> diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos/pmu.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/pmu.c
> rename to arch/arm/mach-exynos/pmu.c
> diff --git a/arch/arm/mach-exynos4/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-fimc.c
> rename to arch/arm/mach-exynos/setup-fimc.c
> diff --git a/arch/arm/mach-exynos4/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-fimd0.c
> rename to arch/arm/mach-exynos/setup-fimd0.c
> diff --git a/arch/arm/mach-exynos4/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-i2c0.c
> rename to arch/arm/mach-exynos/setup-i2c0.c
> diff --git a/arch/arm/mach-exynos4/setup-i2c1.c b/arch/arm/mach-exynos/setup-i2c1.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-i2c1.c
> rename to arch/arm/mach-exynos/setup-i2c1.c
> diff --git a/arch/arm/mach-exynos4/setup-i2c2.c b/arch/arm/mach-exynos/setup-i2c2.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-i2c2.c
> rename to arch/arm/mach-exynos/setup-i2c2.c
> diff --git a/arch/arm/mach-exynos4/setup-i2c3.c b/arch/arm/mach-exynos/setup-i2c3.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-i2c3.c
> rename to arch/arm/mach-exynos/setup-i2c3.c
> diff --git a/arch/arm/mach-exynos4/setup-i2c4.c b/arch/arm/mach-exynos/setup-i2c4.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-i2c4.c
> rename to arch/arm/mach-exynos/setup-i2c4.c
> diff --git a/arch/arm/mach-exynos4/setup-i2c5.c b/arch/arm/mach-exynos/setup-i2c5.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-i2c5.c
> rename to arch/arm/mach-exynos/setup-i2c5.c
> diff --git a/arch/arm/mach-exynos4/setup-i2c6.c b/arch/arm/mach-exynos/setup-i2c6.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-i2c6.c
> rename to arch/arm/mach-exynos/setup-i2c6.c
> diff --git a/arch/arm/mach-exynos4/setup-i2c7.c b/arch/arm/mach-exynos/setup-i2c7.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-i2c7.c
> rename to arch/arm/mach-exynos/setup-i2c7.c
> diff --git a/arch/arm/mach-exynos4/setup-keypad.c b/arch/arm/mach-exynos/setup-keypad.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-keypad.c
> rename to arch/arm/mach-exynos/setup-keypad.c
> diff --git a/arch/arm/mach-exynos4/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-sdhci-gpio.c
> rename to arch/arm/mach-exynos/setup-sdhci-gpio.c
> diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos/setup-sdhci.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-sdhci.c
> rename to arch/arm/mach-exynos/setup-sdhci.c
> diff --git a/arch/arm/mach-exynos4/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
> similarity index 100%
> rename from arch/arm/mach-exynos4/setup-usb-phy.c
> rename to arch/arm/mach-exynos/setup-usb-phy.c
> diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos/sleep.S
> similarity index 100%
> rename from arch/arm/mach-exynos4/sleep.S
> rename to arch/arm/mach-exynos/sleep.S
> diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
> index f9241a7..4e98f09 100644
> --- a/arch/arm/plat-s5p/Kconfig
> +++ b/arch/arm/plat-s5p/Kconfig
> @@ -7,7 +7,7 @@
>
> ?config PLAT_S5P
> ? ? ? ?bool
> - ? ? ? depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
> + ? ? ? depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
> ? ? ? ?default y
> ? ? ? ?select ARM_VIC if !ARCH_EXYNOS4
> ? ? ? ?select ARM_GIC if ARCH_EXYNOS4
> diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
> index 7b0a28f..a56959e 100644
> --- a/arch/arm/plat-s5p/cpu.c
> +++ b/arch/arm/plat-s5p/cpu.c
> @@ -75,7 +75,7 @@ static struct cpu_table cpu_ids[] __initdata = {
> ? ? ? ? ? ? ? ?.map_io ? ? ? ? = exynos4_map_io,
> ? ? ? ? ? ? ? ?.init_clocks ? ?= exynos4_init_clocks,
> ? ? ? ? ? ? ? ?.init_uarts ? ? = exynos4_init_uarts,
> - ? ? ? ? ? ? ? .init ? ? ? ? ? = exynos4_init,
> + ? ? ? ? ? ? ? .init ? ? ? ? ? = exynos_init,
> ? ? ? ? ? ? ? ?.name ? ? ? ? ? = name_exynos4210,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.idcode ? ? ? ? = EXYNOS4212_CPU_ID,
> @@ -83,7 +83,7 @@ static struct cpu_table cpu_ids[] __initdata = {
> ? ? ? ? ? ? ? ?.map_io ? ? ? ? = exynos4_map_io,
> ? ? ? ? ? ? ? ?.init_clocks ? ?= exynos4_init_clocks,
> ? ? ? ? ? ? ? ?.init_uarts ? ? = exynos4_init_uarts,
> - ? ? ? ? ? ? ? .init ? ? ? ? ? = exynos4_init,
> + ? ? ? ? ? ? ? .init ? ? ? ? ? = exynos_init,
> ? ? ? ? ? ? ? ?.name ? ? ? ? ? = name_exynos4212,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.idcode ? ? ? ? = EXYNOS4412_CPU_ID,
> @@ -91,7 +91,7 @@ static struct cpu_table cpu_ids[] __initdata = {
> ? ? ? ? ? ? ? ?.map_io ? ? ? ? = exynos4_map_io,
> ? ? ? ? ? ? ? ?.init_clocks ? ?= exynos4_init_clocks,
> ? ? ? ? ? ? ? ?.init_uarts ? ? = exynos4_init_uarts,
> - ? ? ? ? ? ? ? .init ? ? ? ? ? = exynos4_init,
> + ? ? ? ? ? ? ? .init ? ? ? ? ? = exynos_init,
> ? ? ? ? ? ? ? ?.name ? ? ? ? ? = name_exynos4412,
> ? ? ? ?},
> ?};
> diff --git a/arch/arm/plat-samsung/include/plat/exynos4.h b/arch/arm/plat-samsung/include/plat/exynos4.h
> index 20d73bf..f546e88 100644
> --- a/arch/arm/plat-samsung/include/plat/exynos4.h
> +++ b/arch/arm/plat-samsung/include/plat/exynos4.h
> @@ -18,8 +18,8 @@ extern void exynos4210_register_clocks(void);
> ?extern void exynos4212_register_clocks(void);
> ?extern void exynos4_setup_clocks(void);
>
> -#ifdef CONFIG_ARCH_EXYNOS4
> -extern ?int exynos4_init(void);
> +#ifdef CONFIG_ARCH_EXYNOS
> +extern ?int exynos_init(void);
> ?extern void exynos4_init_irq(void);
> ?extern void exynos4_map_io(void);
> ?extern void exynos4_init_clocks(int xtal);
> @@ -31,5 +31,5 @@ extern struct sys_timer exynos4_timer;
> ?#define exynos4_init_clocks NULL
> ?#define exynos4_init_uarts NULL
> ?#define exynos4_map_io NULL
> -#define exynos4_init NULL
> +#define exynos_init NULL
> ?#endif
> --
> 1.7.1
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>

^ permalink raw reply

* [PATCH V2 2/2] ARM: SAMSUNG: Cleanup resources by using macro
From: Kyungmin Park @ 2011-10-03  3:53 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <005901cc817e$51a56d00$f4f04700$%kim@samsung.com>

On Mon, Oct 3, 2011 at 12:41 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> This patch adds macro SAMSUNG_RES_MEM, SAMSUNG_RES_IRQ
> and so on to cleanup regarding 'struct resource' by using
> defined helpers at <linux/ioport.h>.
>
> Cc: Ben Dooks <ben-linux@fluff.org>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> ---
> Changes since v1:
> - Address comments from Russell King
> ?Using defined helpers to define resource
>
> ?arch/arm/mach-s3c2410/include/mach/map.h ?| ? ?1 +
> ?arch/arm/plat-samsung/devs.c ? ? ? ? ? ? ?| ?697 +++++------------------------
> ?arch/arm/plat-samsung/include/plat/devs.h | ? 11 +
> ?3 files changed, 129 insertions(+), 580 deletions(-)
>
> diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
> index 4cf495f..78ae807 100644
> --- a/arch/arm/mach-s3c2410/include/mach/map.h
> +++ b/arch/arm/mach-s3c2410/include/mach/map.h
> @@ -149,6 +149,7 @@
> ?#define S3C24XX_PA_RTC ? ? ?S3C2410_PA_RTC
> ?#define S3C24XX_PA_ADC ? ? ?S3C2410_PA_ADC
> ?#define S3C24XX_PA_SPI ? ? ?S3C2410_PA_SPI
> +#define S3C24XX_PA_SPI1 ? ? ? ? ? ? ? ?(S3C2410_PA_SPI + S3C2410_SPI1)
> ?#define S3C24XX_PA_SDI ? ? ?S3C2410_PA_SDI
> ?#define S3C24XX_PA_NAND ? ? ? ? ? ?S3C2410_PA_NAND
>
> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
> index a2112aa..ec14e36 100644
> --- a/arch/arm/plat-samsung/devs.c
> +++ b/arch/arm/plat-samsung/devs.c
> @@ -67,34 +67,11 @@ static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
> ?/* AC97 */
> ?#ifdef CONFIG_CPU_S3C2440
> ?static struct resource s3c_ac97_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C2440_PA_AC97,
> - ? ? ? ? ? ? ? .end ? ?= S3C2440_PA_AC97 + S3C2440_SZ_AC97 - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_S3C244x_AC97,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_S3C244x_AC97,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> - ? ? ? [2] = {
> - ? ? ? ? ? ? ? .name ? = "PCM out",
> - ? ? ? ? ? ? ? .start ?= DMACH_PCM_OUT,
> - ? ? ? ? ? ? ? .end ? ?= DMACH_PCM_OUT,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_DMA,
> - ? ? ? },
> - ? ? ? [3] = {
> - ? ? ? ? ? ? ? .name ? = "PCM in",
> - ? ? ? ? ? ? ? .start ?= DMACH_PCM_IN,
> - ? ? ? ? ? ? ? .end ? ?= DMACH_PCM_IN,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_DMA,
> - ? ? ? },
> - ? ? ? [4] = {
> - ? ? ? ? ? ? ? .name ? = "Mic in",
> - ? ? ? ? ? ? ? .start ?= DMACH_MIC_IN,
> - ? ? ? ? ? ? ? .end ? ?= DMACH_MIC_IN,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_DMA,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C2440, AC97, S3C2440_SZ_AC97),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(S3C244x_AC97),
> + ? ? ? [2] = SAMSUNG_RES_DMA_NAMED(PCM_OUT, "PCM out"),
> + ? ? ? [3] = SAMSUNG_RES_DMA_NAMED(PCM_IN, "PCM in"),
> + ? ? ? [4] = SAMSUNG_RES_DMA_NAMED(MIC_IN, "Mic in"),
> ?};
>
> ?struct platform_device s3c_device_ac97 = {
> @@ -113,21 +90,9 @@ struct platform_device s3c_device_ac97 = {
>
> ?#ifdef CONFIG_PLAT_S3C24XX
> ?static struct resource s3c_adc_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C24XX_PA_ADC,
> - ? ? ? ? ? ? ? .end ? ?= S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_TC,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_TC,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> - ? ? ? [2] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_ADC,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_ADC,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C24XX, ADC, S3C24XX_SZ_ADC),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(TC),
> + ? ? ? [2] = SAMSUNG_RES_IRQ(ADC),
> ?};
>
> ?struct platform_device s3c_device_adc = {
> @@ -140,21 +105,9 @@ struct platform_device s3c_device_adc = {
>
> ?#if defined(CONFIG_SAMSUNG_DEV_ADC)
> ?static struct resource s3c_adc_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= SAMSUNG_PA_ADC,
> - ? ? ? ? ? ? ? .end ? ?= SAMSUNG_PA_ADC + SZ_256 - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_TC,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_TC,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> - ? ? ? [2] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_ADC,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_ADC,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(SAMSUNG, ADC, SZ_256),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(TC),
> + ? ? ? [2] = SAMSUNG_RES_IRQ(ADC),
> ?};
>
> ?struct platform_device s3c_device_adc = {
> @@ -169,16 +122,8 @@ struct platform_device s3c_device_adc = {
>
> ?#ifdef CONFIG_CPU_S3C2440
> ?static struct resource s3c_camif_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C2440_PA_CAMIF,
> - ? ? ? ? ? ? ? .end ? ?= S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_CAM,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_CAM,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C2440, CAMIF, S3C2440_SZ_CAMIF),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(CAM),
> ?};
>
> ?struct platform_device s3c_device_camif = {
> @@ -217,26 +162,10 @@ struct platform_device samsung_asoc_idma = {
>
> ?#ifdef CONFIG_S3C_DEV_FB
> ?static struct resource s3c_fb_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_FB,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_FB + SZ_16K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_LCD_VSYNC,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_LCD_VSYNC,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> - ? ? ? [2] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_LCD_FIFO,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_LCD_FIFO,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> - ? ? ? [3] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_LCD_SYSTEM,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_LCD_SYSTEM,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, FB, SZ_16K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(LCD_VSYNC),
> + ? ? ? [2] = SAMSUNG_RES_IRQ(LCD_FIFO),
> + ? ? ? [3] = SAMSUNG_RES_IRQ(LCD_SYSTEM),
> ?};
>
> ?struct platform_device s3c_device_fb = {
> @@ -261,16 +190,8 @@ void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
>
> ?#ifdef CONFIG_S5P_DEV_FIMC0
> ?static struct resource s5p_fimc0_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_FIMC0,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_FIMC0 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_FIMC0,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_FIMC0,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, FIMC0, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(FIMC0),
> ?};
>
> ?struct platform_device s5p_device_fimc0 = {
> @@ -287,16 +208,8 @@ struct platform_device s5p_device_fimc0 = {
>
> ?#ifdef CONFIG_S5P_DEV_FIMC1
> ?static struct resource s5p_fimc1_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_FIMC1,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_FIMC1 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_FIMC1,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_FIMC1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, FIMC1, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(FIMC1),
> ?};
>
> ?struct platform_device s5p_device_fimc1 = {
> @@ -313,16 +226,8 @@ struct platform_device s5p_device_fimc1 = {
>
> ?#ifdef CONFIG_S5P_DEV_FIMC2
> ?static struct resource s5p_fimc2_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_FIMC2,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_FIMC2 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_FIMC2,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_FIMC2,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, FIMC2, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(FIMC2),
> ?};
>
> ?struct platform_device s5p_device_fimc2 = {
> @@ -339,16 +244,8 @@ struct platform_device s5p_device_fimc2 = {
>
> ?#ifdef CONFIG_S5P_DEV_FIMC3
> ?static struct resource s5p_fimc3_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_FIMC3,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_FIMC3 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_FIMC3,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_FIMC3,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, FIMC3, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(FIMC3),
> ?};
>
> ?struct platform_device s5p_device_fimc3 = {
> @@ -367,26 +264,10 @@ struct platform_device s5p_device_fimc3 = {
>
> ?#ifdef CONFIG_S5P_DEV_FIMD0
> ?static struct resource s5p_fimd0_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_FIMD0,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_FIMD0 + SZ_32K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_FIMD0_VSYNC,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_FIMD0_VSYNC,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> - ? ? ? [2] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_FIMD0_FIFO,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_FIMD0_FIFO,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> - ? ? ? [3] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_FIMD0_SYSTEM,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_FIMD0_SYSTEM,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, FIMD0, SZ_32K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(FIMD0_VSYNC),
> + ? ? ? [2] = SAMSUNG_RES_IRQ(FIMD0_FIFO),
> + ? ? ? [3] = SAMSUNG_RES_IRQ(FIMD0_SYSTEM),
> ?};
>
> ?struct platform_device s5p_device_fimd0 = {
> @@ -425,20 +306,10 @@ void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
>
> ?/* HSMMC */
>
> -#define S3C_SZ_HSMMC ? 0x1000
> -
> ?#ifdef CONFIG_S3C_DEV_HSMMC
> ?static struct resource s3c_hsmmc_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_HSMMC0,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_HSMMC0,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_HSMMC0,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, HSMMC0, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(HSMMC0),
> ?};
>
> ?struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
> @@ -468,16 +339,8 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
>
> ?#ifdef CONFIG_S3C_DEV_HSMMC1
> ?static struct resource s3c_hsmmc1_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_HSMMC1,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_HSMMC1,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_HSMMC1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, HSMMC1, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(HSMMC1),
> ?};
>
> ?struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
> @@ -509,16 +372,8 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
>
> ?#ifdef CONFIG_S3C_DEV_HSMMC2
> ?static struct resource s3c_hsmmc2_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_HSMMC2,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_HSMMC2 + S3C_SZ_HSMMC - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_HSMMC2,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_HSMMC2,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, HSMMC2, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(HSMMC2),
> ?};
>
> ?struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
> @@ -548,16 +403,8 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
>
> ?#ifdef CONFIG_S3C_DEV_HSMMC3
> ?static struct resource s3c_hsmmc3_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_HSMMC3,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_HSMMC3 + S3C_SZ_HSMMC - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_HSMMC3,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_HSMMC3,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, HSMMC3, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(HSMMC3),
> ?};
>
> ?struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
> @@ -588,16 +435,8 @@ void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
> ?/* I2C */
>
> ?static struct resource s3c_i2c0_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_IIC,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_IIC + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_IIC,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_IIC,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, IIC, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(IIC),
> ?};
>
> ?struct platform_device s3c_device_i2c0 = {
> @@ -634,16 +473,8 @@ void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
>
> ?#ifdef CONFIG_S3C_DEV_I2C1
> ?static struct resource s3c_i2c1_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_IIC1,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_IIC1 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_IIC1,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_IIC1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, IIC1, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(IIC1),
> ?};
>
> ?struct platform_device s3c_device_i2c1 = {
> @@ -672,16 +503,8 @@ void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
>
> ?#ifdef CONFIG_S3C_DEV_I2C2
> ?static struct resource s3c_i2c2_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_IIC2,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_IIC2 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_IIC2,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_IIC2,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, IIC2, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(IIC2),
> ?};
>
> ?struct platform_device s3c_device_i2c2 = {
> @@ -710,16 +533,8 @@ void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
>
> ?#ifdef CONFIG_S3C_DEV_I2C3
> ?static struct resource s3c_i2c3_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_IIC3,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_IIC3 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_IIC3,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_IIC3,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, IIC3, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(IIC3),
> ?};
>
> ?struct platform_device s3c_device_i2c3 = {
> @@ -748,16 +563,8 @@ void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
>
> ?#ifdef CONFIG_S3C_DEV_I2C4
> ?static struct resource s3c_i2c4_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_IIC4,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_IIC4 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_IIC4,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_IIC4,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, IIC4, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(IIC4),
> ?};
>
> ?struct platform_device s3c_device_i2c4 = {
> @@ -786,16 +593,8 @@ void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
>
> ?#ifdef CONFIG_S3C_DEV_I2C5
> ?static struct resource s3c_i2c5_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_IIC5,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_IIC5 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_IIC5,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_IIC5,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, IIC5, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(IIC5),
> ?};
>
> ?struct platform_device s3c_device_i2c5 = {
> @@ -824,16 +623,8 @@ void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
>
> ?#ifdef CONFIG_S3C_DEV_I2C6
> ?static struct resource s3c_i2c6_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_IIC6,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_IIC6 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_IIC6,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_IIC6,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, IIC6, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(IIC6),
> ?};
>
> ?struct platform_device s3c_device_i2c6 = {
> @@ -862,16 +653,8 @@ void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
>
> ?#ifdef CONFIG_S3C_DEV_I2C7
> ?static struct resource s3c_i2c7_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_IIC7,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_IIC7 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_IIC7,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_IIC7,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, IIC7, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(IIC7),
> ?};
>
> ?struct platform_device s3c_device_i2c7 = {
> @@ -902,16 +685,8 @@ void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
>
> ?#ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
> ?static struct resource s5p_i2c_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_IIC_HDMIPHY,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_IIC_HDMIPHY + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_IIC_HDMIPHY,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_IIC_HDMIPHY,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, IIC_HDMIPHY, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(IIC_HDMIPHY),
> ?};
>
> ?struct platform_device s5p_device_i2c_hdmiphy = {
> @@ -945,11 +720,7 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
>
> ?#ifdef CONFIG_PLAT_S3C24XX
> ?static struct resource s3c_iis_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C24XX_PA_IIS,
> - ? ? ? ? ? ? ? .end ? ?= S3C24XX_PA_IIS + S3C24XX_SZ_IIS - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C24XX, IIS, S3C24XX_SZ_IIS),
> ?};
>
> ?struct platform_device s3c_device_iis = {
> @@ -979,16 +750,8 @@ struct platform_device s3c2412_device_iis = {
>
> ?#ifdef CONFIG_SAMSUNG_DEV_IDE
> ?static struct resource s3c_cfcon_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= SAMSUNG_PA_CFCON,
> - ? ? ? ? ? ? ? .end ? ?= SAMSUNG_PA_CFCON + SZ_16K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_CFCON,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_CFCON,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(SAMSUNG, CFCON, SZ_16K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(CFCON),
> ?};
>
> ?struct platform_device s3c_device_cfcon = {
> @@ -1008,16 +771,8 @@ void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
>
> ?#ifdef CONFIG_SAMSUNG_DEV_KEYPAD
> ?static struct resource samsung_keypad_resources[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= SAMSUNG_PA_KEYPAD,
> - ? ? ? ? ? ? ? .end ? ?= SAMSUNG_PA_KEYPAD + 0x20 - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_KEYPAD,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_KEYPAD,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(SAMSUNG, KEYPAD, SZ_32),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(KEYPAD),
> ?};
>
> ?struct platform_device samsung_device_keypad = {
> @@ -1043,16 +798,8 @@ void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
>
> ?#ifdef CONFIG_PLAT_S3C24XX
> ?static struct resource s3c_lcd_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C24XX_PA_LCD,
> - ? ? ? ? ? ? ? .end ? ?= S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_LCD,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_LCD,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C24XX, LCD, S3C24XX_SZ_LCD),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(LCD),
> ?};
>
> ?struct platform_device s3c_device_lcd = {
> @@ -1087,16 +834,8 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
>
> ?#ifdef CONFIG_S5P_DEV_MFC
> ?static struct resource s5p_mfc_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_MFC,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_MFC + SZ_64K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_MFC,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_MFC,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, MFC, SZ_64K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(MFC),
> ?};
>
> ?struct platform_device s5p_device_mfc = {
> @@ -1139,16 +878,8 @@ struct platform_device s5p_device_mfc_r = {
>
> ?#ifdef CONFIG_S5P_DEV_CSIS0
> ?static struct resource s5p_mipi_csis0_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_MIPI_CSIS0,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_MIPI_CSIS0 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_MIPI_CSIS0,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_MIPI_CSIS0,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, MIPI_CSIS0, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(MIPI_CSIS0),
> ?};
>
> ?struct platform_device s5p_device_mipi_csis0 = {
> @@ -1161,16 +892,8 @@ struct platform_device s5p_device_mipi_csis0 = {
>
> ?#ifdef CONFIG_S5P_DEV_CSIS1
> ?static struct resource s5p_mipi_csis1_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_MIPI_CSIS1,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_MIPI_CSIS1 + SZ_4K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_MIPI_CSIS1,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_MIPI_CSIS1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, MIPI_CSIS1, SZ_4K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(MIPI_CSIS1),
> ?};
>
> ?struct platform_device s5p_device_mipi_csis1 = {
> @@ -1185,11 +908,7 @@ struct platform_device s5p_device_mipi_csis1 = {
>
> ?#ifdef CONFIG_S3C_DEV_NAND
> ?static struct resource s3c_nand_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_NAND,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_NAND + SZ_1M,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, NAND, SZ_1M),
> ?};
>
> ?struct platform_device s3c_device_nand = {
> @@ -1294,21 +1013,9 @@ void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
>
> ?#ifdef CONFIG_S3C_DEV_ONENAND
> ?static struct resource s3c_onenand_resources[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_ONENAND,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_ONENAND + 0x400 - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_ONENAND_BUF,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_ONENAND_BUF + S3C_SZ_ONENAND_BUF - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [2] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_ONENAND,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_ONENAND,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, ONENAND, SZ_1K),
> + ? ? ? [1] = SAMSUNG_RES_MEM(S3C, ONENAND_BUF, S3C_SZ_ONENAND_BUF),
> + ? ? ? [2] = SAMSUNG_RES_IRQ(ONENAND),
> ?};
>
> ?struct platform_device s3c_device_onenand = {
> @@ -1321,21 +1028,9 @@ struct platform_device s3c_device_onenand = {
>
> ?#ifdef CONFIG_S3C64XX_DEV_ONENAND1
> ?static struct resource s3c64xx_onenand1_resources[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C64XX_PA_ONENAND1,
> - ? ? ? ? ? ? ? .end ? ?= S3C64XX_PA_ONENAND1 + 0x400 - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= S3C64XX_PA_ONENAND1_BUF,
> - ? ? ? ? ? ? ? .end ? ?= S3C64XX_PA_ONENAND1_BUF + S3C64XX_SZ_ONENAND1_BUF - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [2] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_ONENAND1,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_ONENAND1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C64XX, ONENAND1, SZ_1K),
> + ? ? ? [1] = SAMSUNG_RES_MEM(S3C64XX, ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
> + ? ? ? [2] = SAMSUNG_RES_IRQ(ONENAND1),
> ?};
>
> ?struct platform_device s3c64xx_device_onenand1 = {
> @@ -1354,21 +1049,9 @@ void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
>
> ?#ifdef CONFIG_S5P_DEV_ONENAND
> ?static struct resource s5p_onenand_resources[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_ONENAND,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_ONENAND + SZ_128K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_ONENAND_DMA,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_ONENAND_DMA + SZ_8K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [2] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_ONENAND_AUDI,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_ONENAND_AUDI,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, ONENAND, SZ_128K),
> + ? ? ? [1] = SAMSUNG_RES_MEM(S5P, ONENAND_DMA, SZ_8K),
> + ? ? ? [2] = SAMSUNG_RES_IRQ(ONENAND_AUDI),
> ?};
>
> ?struct platform_device s5p_device_onenand = {
> @@ -1382,17 +1065,15 @@ struct platform_device s5p_device_onenand = {
> ?/* PMU */
>
> ?#ifdef CONFIG_PLAT_S5P
> -static struct resource s5p_pmu_resource = {
> - ? ? ? .start ?= IRQ_PMU,
> - ? ? ? .end ? ?= IRQ_PMU,
> - ? ? ? .flags ?= IORESOURCE_IRQ,
> +static struct resource s5p_pmu_resource[] = {
> + ? ? ? SAMSUNG_RES_IRQ(PMU)
> ?};
>
> ?struct platform_device s5p_device_pmu = {
> ? ? ? ?.name ? ? ? ? ? = "arm-pmu",
> ? ? ? ?.id ? ? ? ? ? ? = ARM_PMU_DEVICE_CPU,
> - ? ? ? .num_resources ?= 1,
> - ? ? ? .resource ? ? ? = &s5p_pmu_resource,
> + ? ? ? .num_resources ?= ARRAY_SIZE(s5p_pmu_resource),
> + ? ? ? .resource ? ? ? = s5p_pmu_resource,
> ?};
>
> ?static int __init s5p_pmu_init(void)
> @@ -1442,21 +1123,9 @@ struct platform_device s3c_device_timer[] = {
>
> ?#ifdef CONFIG_PLAT_S3C24XX
> ?static struct resource s3c_rtc_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C24XX_PA_RTC,
> - ? ? ? ? ? ? ? .end ? ?= S3C24XX_PA_RTC + 0xff,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_RTC,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_RTC,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> - ? ? ? [2] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_TICK,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_TICK,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C24XX, RTC, SZ_256),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(RTC),
> + ? ? ? [2] = SAMSUNG_RES_IRQ(TICK),
> ?};
>
> ?struct platform_device s3c_device_rtc = {
> @@ -1469,21 +1138,9 @@ struct platform_device s3c_device_rtc = {
>
> ?#ifdef CONFIG_S3C_DEV_RTC
> ?static struct resource s3c_rtc_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_RTC,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_RTC + 0xff,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_RTC_ALARM,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_RTC_ALARM,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> - ? ? ? [2] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_RTC_TIC,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_RTC_TIC,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, RTC, SZ_256),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(RTC_ALARM),
> + ? ? ? [2] = SAMSUNG_RES_IRQ(RTC_TIC),
> ?};
>
> ?struct platform_device s3c_device_rtc = {
> @@ -1498,16 +1155,8 @@ struct platform_device s3c_device_rtc = {
>
> ?#ifdef CONFIG_PLAT_S3C24XX
> ?static struct resource s3c_sdi_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C24XX_PA_SDI,
> - ? ? ? ? ? ? ? .end ? ?= S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_SDI,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_SDI,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C24XX, SDI, S3C24XX_SZ_SDI),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(SDI),
> ?};
>
> ?struct platform_device s3c_device_sdi = {
> @@ -1528,16 +1177,8 @@ void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
>
> ?#ifdef CONFIG_PLAT_S3C24XX
> ?static struct resource s3c_spi0_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C24XX_PA_SPI,
> - ? ? ? ? ? ? ? .end ? ?= S3C24XX_PA_SPI + 0x1f,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_SPI0,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_SPI0,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C24XX, SPI, SZ_32),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(SPI0),
> ?};
>
> ?struct platform_device s3c_device_spi0 = {
> @@ -1552,16 +1193,8 @@ struct platform_device s3c_device_spi0 = {
> ?};
>
> ?static struct resource s3c_spi1_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C24XX_PA_SPI + S3C2410_SPI1,
> - ? ? ? ? ? ? ? .end ? ?= S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_SPI1,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_SPI1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C24XX, SPI1, SZ_32),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(SPI1),
> ?};
>
> ?struct platform_device s3c_device_spi1 = {
> @@ -1580,17 +1213,8 @@ struct platform_device s3c_device_spi1 = {
>
> ?#ifdef CONFIG_PLAT_S3C24XX
> ?static struct resource s3c_ts_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C24XX_PA_ADC,
> - ? ? ? ? ? ? ? .end ? ?= S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_TC,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_TC,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> -
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C24XX, ADC, S3C24XX_SZ_ADC),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(TC),
> ?};
>
> ?struct platform_device s3c_device_ts = {
> @@ -1610,16 +1234,8 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_
>
> ?#ifdef CONFIG_SAMSUNG_DEV_TS
> ?static struct resource s3c_ts_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= SAMSUNG_PA_ADC,
> - ? ? ? ? ? ? ? .end ? ?= SAMSUNG_PA_ADC + SZ_256 - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_TC,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_TC,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(SAMSUNG, ADC, SZ_256),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(TC),
> ?};
>
> ?static struct s3c2410_ts_mach_info default_ts_data __initdata = {
> @@ -1650,16 +1266,8 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
> ?#ifdef CONFIG_S5P_DEV_TV
>
> ?static struct resource s5p_hdmi_resources[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_HDMI,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_HDMI + SZ_1M - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_HDMI,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_HDMI,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, HDMI, SZ_1M),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(HDMI),
> ?};
>
> ?struct platform_device s5p_device_hdmi = {
> @@ -1670,16 +1278,8 @@ struct platform_device s5p_device_hdmi = {
> ?};
>
> ?static struct resource s5p_sdo_resources[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_SDO,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_SDO + SZ_64K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_SDO,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_SDO,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, SDO, SZ_64K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(SDO),
> ?};
>
> ?struct platform_device s5p_device_sdo = {
> @@ -1690,24 +1290,9 @@ struct platform_device s5p_device_sdo = {
> ?};
>
> ?static struct resource s5p_mixer_resources[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_MIXER,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_MIXER + SZ_64K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? ? ? ? ? .name ? = "mxr"
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_VP,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_VP + SZ_64K - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? ? ? ? ? .name ? = "vp"
> - ? ? ? },
> - ? ? ? [2] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_MIXER,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_MIXER,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? ? ? ? ? .name ? = "irq"
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM_NAMED(S5P, MIXER, SZ_64K, "mxr"),
> + ? ? ? [1] = SAMSUNG_RES_MEM_NAMED(S5P, VP, SZ_64K, "vp"),
> + ? ? ? [2] = SAMSUNG_RES_IRQ_NAMED(MIXER, "irq"),
> ?};
>
> ?struct platform_device s5p_device_mixer = {
> @@ -1726,16 +1311,8 @@ struct platform_device s5p_device_mixer = {
>
> ?#ifdef CONFIG_S3C_DEV_USB_HOST
> ?static struct resource s3c_usb_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_USBHOST,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_USBHOST + 0x100 - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_USBH,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_USBH,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, USBHOST, SZ_256),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(USBH),
> ?};
>
> ?struct platform_device s3c_device_ohci = {
> @@ -1769,16 +1346,8 @@ void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
>
> ?#ifdef CONFIG_PLAT_S3C24XX
> ?static struct resource s3c_usbgadget_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C24XX_PA_USBDEV,
> - ? ? ? ? ? ? ? .end ? ?= S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_USBD,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_USBD,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C24XX, USBDEV, S3C24XX_SZ_USBDEV),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(USBD),
> ?};
>
> ?struct platform_device s3c_device_usbgadget = {
> @@ -1798,16 +1367,8 @@ void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
>
> ?#ifdef CONFIG_S5P_DEV_USB_EHCI
> ?static struct resource s5p_ehci_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S5P_PA_EHCI,
> - ? ? ? ? ? ? ? .end ? ?= S5P_PA_EHCI + SZ_256 - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_USB_HOST,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_USB_HOST,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S5P, EHCI, SZ_256),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(USB_HOST),
> ?};
>
> ?struct platform_device s5p_device_ehci = {
> @@ -1839,16 +1400,8 @@ void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
>
> ?#ifdef CONFIG_S3C_DEV_USB_HSOTG
> ?static struct resource s3c_usb_hsotg_resources[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_USB_HSOTG,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_USB_HSOTG + 0x10000 - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_OTG,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_OTG,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? },
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, USB_HSOTG, SZ_16K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(OTG),
> ?};
>
> ?struct platform_device s3c_device_usb_hsotg = {
> @@ -1867,16 +1420,8 @@ struct platform_device s3c_device_usb_hsotg = {
>
> ?#ifdef CONFIG_PLAT_S3C24XX
> ?static struct resource s3c_hsudc_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C2416_PA_HSUDC,
> - ? ? ? ? ? ? ? .end ? ?= S3C2416_PA_HSUDC + S3C2416_SZ_HSUDC - 1,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_USBD,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_USBD,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C2416, HSUDC, S3C2416_SZ_HSUDC),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(USBD),
> ?};
>
> ?struct platform_device s3c_device_usb_hsudc = {
> @@ -1900,16 +1445,8 @@ void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
>
> ?#ifdef CONFIG_S3C_DEV_WDT
> ?static struct resource s3c_wdt_resource[] = {
> - ? ? ? [0] = {
> - ? ? ? ? ? ? ? .start ?= S3C_PA_WDT,
> - ? ? ? ? ? ? ? .end ? ?= S3C_PA_WDT + SZ_1K,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> - ? ? ? },
> - ? ? ? [1] = {
> - ? ? ? ? ? ? ? .start ?= IRQ_WDT,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_WDT,
> - ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> - ? ? ? }
> + ? ? ? [0] = SAMSUNG_RES_MEM(S3C, WDT, SZ_1K),
> + ? ? ? [1] = SAMSUNG_RES_IRQ(WDT),
> ?};
>
> ?struct platform_device s3c_device_wdt = {
> diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
> index 8f19241..a506831 100644
> --- a/arch/arm/plat-samsung/include/plat/devs.h
> +++ b/arch/arm/plat-samsung/include/plat/devs.h
> @@ -18,6 +18,17 @@
>
> ?#include <linux/platform_device.h>
>
> +#define SAMSUNG_RES_MEM(soc, ip, sz) ? DEFINE_RES_MEM(soc##_PA_##ip, sz)
> +#define SAMSUNG_RES_IRQ(ip) ? ? ? ? ? ?DEFINE_RES_IRQ(IRQ_##ip)
> +
> +#define SAMSUNG_RES_MEM_NAMED(soc, ip, sz, name) ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DEFINE_RES_MEM_NAMED(soc##_PA_##ip, sz, name)
> +#define SAMSUNG_RES_IRQ_NAMED(ip, name) ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DEFINE_RES_IRQ_NAMED(IRQ_##ip, name)
> +#define SAMSUNG_RES_DMA_NAMED(ch, name) ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DEFINE_RES_DMA_NAMED(DMACH_##ch, name)

It's good for readability. but do you think that it's hard to find out
defined macros are used at real place?
e.g., Now I want to find out the S3C_PA_USB_HSOTG. it's difficult if
you use the SAMSUNG_RES_* series macro.
but if you use the DEFINED_RES_* series directly. it's easy to find
out at real codes.

Thank you,
Kyungmin Park
> +
> +
> ?struct s3c24xx_uart_resources {
> ? ? ? ?struct resource ? ? ? ? *resources;
> ? ? ? ?unsigned long ? ? ? ? ? ?nr_resources;
> --
> 1.7.1
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>

^ permalink raw reply

* [PATCH V2 2/2] ARM: SAMSUNG: Cleanup resources by using macro
From: Kukjin Kim @ 2011-10-03  3:41 UTC (permalink / raw)
  To: linux-arm-kernel

This patch adds macro SAMSUNG_RES_MEM, SAMSUNG_RES_IRQ
and so on to cleanup regarding 'struct resource' by using
defined helpers at <linux/ioport.h>.

Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
Changes since v1:
- Address comments from Russell King
 Using defined helpers to define resource

 arch/arm/mach-s3c2410/include/mach/map.h  |    1 +
 arch/arm/plat-samsung/devs.c              |  697 +++++------------------------
 arch/arm/plat-samsung/include/plat/devs.h |   11 +
 3 files changed, 129 insertions(+), 580 deletions(-)

diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 4cf495f..78ae807 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -149,6 +149,7 @@
 #define S3C24XX_PA_RTC      S3C2410_PA_RTC
 #define S3C24XX_PA_ADC      S3C2410_PA_ADC
 #define S3C24XX_PA_SPI      S3C2410_PA_SPI
+#define S3C24XX_PA_SPI1		(S3C2410_PA_SPI + S3C2410_SPI1)
 #define S3C24XX_PA_SDI      S3C2410_PA_SDI
 #define S3C24XX_PA_NAND	    S3C2410_PA_NAND
 
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index a2112aa..ec14e36 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -67,34 +67,11 @@ static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
 /* AC97 */
 #ifdef CONFIG_CPU_S3C2440
 static struct resource s3c_ac97_resource[] = {
-	[0] = {
-		.start	= S3C2440_PA_AC97,
-		.end	= S3C2440_PA_AC97 + S3C2440_SZ_AC97 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_S3C244x_AC97,
-		.end	= IRQ_S3C244x_AC97,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.name	= "PCM out",
-		.start	= DMACH_PCM_OUT,
-		.end	= DMACH_PCM_OUT,
-		.flags	= IORESOURCE_DMA,
-	},
-	[3] = {
-		.name	= "PCM in",
-		.start	= DMACH_PCM_IN,
-		.end	= DMACH_PCM_IN,
-		.flags	= IORESOURCE_DMA,
-	},
-	[4] = {
-		.name	= "Mic in",
-		.start	= DMACH_MIC_IN,
-		.end	= DMACH_MIC_IN,
-		.flags	= IORESOURCE_DMA,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C2440, AC97, S3C2440_SZ_AC97),
+	[1] = SAMSUNG_RES_IRQ(S3C244x_AC97),
+	[2] = SAMSUNG_RES_DMA_NAMED(PCM_OUT, "PCM out"),
+	[3] = SAMSUNG_RES_DMA_NAMED(PCM_IN, "PCM in"),
+	[4] = SAMSUNG_RES_DMA_NAMED(MIC_IN, "Mic in"),
 };
 
 struct platform_device s3c_device_ac97 = {
@@ -113,21 +90,9 @@ struct platform_device s3c_device_ac97 = {
 
 #ifdef CONFIG_PLAT_S3C24XX
 static struct resource s3c_adc_resource[] = {
-	[0] = {
-		.start	= S3C24XX_PA_ADC,
-		.end	= S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_TC,
-		.end	= IRQ_TC,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.start	= IRQ_ADC,
-		.end	= IRQ_ADC,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C24XX, ADC, S3C24XX_SZ_ADC),
+	[1] = SAMSUNG_RES_IRQ(TC),
+	[2] = SAMSUNG_RES_IRQ(ADC),
 };
 
 struct platform_device s3c_device_adc = {
@@ -140,21 +105,9 @@ struct platform_device s3c_device_adc = {
 
 #if defined(CONFIG_SAMSUNG_DEV_ADC)
 static struct resource s3c_adc_resource[] = {
-	[0] = {
-		.start	= SAMSUNG_PA_ADC,
-		.end	= SAMSUNG_PA_ADC + SZ_256 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_TC,
-		.end	= IRQ_TC,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.start	= IRQ_ADC,
-		.end	= IRQ_ADC,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(SAMSUNG, ADC, SZ_256),
+	[1] = SAMSUNG_RES_IRQ(TC),
+	[2] = SAMSUNG_RES_IRQ(ADC),
 };
 
 struct platform_device s3c_device_adc = {
@@ -169,16 +122,8 @@ struct platform_device s3c_device_adc = {
 
 #ifdef CONFIG_CPU_S3C2440
 static struct resource s3c_camif_resource[] = {
-	[0] = {
-		.start	= S3C2440_PA_CAMIF,
-		.end	= S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_CAM,
-		.end	= IRQ_CAM,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C2440, CAMIF, S3C2440_SZ_CAMIF),
+	[1] = SAMSUNG_RES_IRQ(CAM),
 };
 
 struct platform_device s3c_device_camif = {
@@ -217,26 +162,10 @@ struct platform_device samsung_asoc_idma = {
 
 #ifdef CONFIG_S3C_DEV_FB
 static struct resource s3c_fb_resource[] = {
-	[0] = {
-		.start	= S3C_PA_FB,
-		.end	= S3C_PA_FB + SZ_16K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_LCD_VSYNC,
-		.end	= IRQ_LCD_VSYNC,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.start	= IRQ_LCD_FIFO,
-		.end	= IRQ_LCD_FIFO,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[3] = {
-		.start	= IRQ_LCD_SYSTEM,
-		.end	= IRQ_LCD_SYSTEM,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C, FB, SZ_16K),
+	[1] = SAMSUNG_RES_IRQ(LCD_VSYNC),
+	[2] = SAMSUNG_RES_IRQ(LCD_FIFO),
+	[3] = SAMSUNG_RES_IRQ(LCD_SYSTEM),
 };
 
 struct platform_device s3c_device_fb = {
@@ -261,16 +190,8 @@ void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
 
 #ifdef CONFIG_S5P_DEV_FIMC0
 static struct resource s5p_fimc0_resource[] = {
-	[0] = {
-		.start	= S5P_PA_FIMC0,
-		.end	= S5P_PA_FIMC0 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_FIMC0,
-		.end	= IRQ_FIMC0,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S5P, FIMC0, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(FIMC0),
 };
 
 struct platform_device s5p_device_fimc0 = {
@@ -287,16 +208,8 @@ struct platform_device s5p_device_fimc0 = {
 
 #ifdef CONFIG_S5P_DEV_FIMC1
 static struct resource s5p_fimc1_resource[] = {
-	[0] = {
-		.start	= S5P_PA_FIMC1,
-		.end	= S5P_PA_FIMC1 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_FIMC1,
-		.end	= IRQ_FIMC1,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S5P, FIMC1, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(FIMC1),
 };
 
 struct platform_device s5p_device_fimc1 = {
@@ -313,16 +226,8 @@ struct platform_device s5p_device_fimc1 = {
 
 #ifdef CONFIG_S5P_DEV_FIMC2
 static struct resource s5p_fimc2_resource[] = {
-	[0] = {
-		.start	= S5P_PA_FIMC2,
-		.end	= S5P_PA_FIMC2 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_FIMC2,
-		.end	= IRQ_FIMC2,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S5P, FIMC2, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(FIMC2),
 };
 
 struct platform_device s5p_device_fimc2 = {
@@ -339,16 +244,8 @@ struct platform_device s5p_device_fimc2 = {
 
 #ifdef CONFIG_S5P_DEV_FIMC3
 static struct resource s5p_fimc3_resource[] = {
-	[0] = {
-		.start	= S5P_PA_FIMC3,
-		.end	= S5P_PA_FIMC3 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_FIMC3,
-		.end	= IRQ_FIMC3,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S5P, FIMC3, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(FIMC3),
 };
 
 struct platform_device s5p_device_fimc3 = {
@@ -367,26 +264,10 @@ struct platform_device s5p_device_fimc3 = {
 
 #ifdef CONFIG_S5P_DEV_FIMD0
 static struct resource s5p_fimd0_resource[] = {
-	[0] = {
-		.start	= S5P_PA_FIMD0,
-		.end	= S5P_PA_FIMD0 + SZ_32K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_FIMD0_VSYNC,
-		.end	= IRQ_FIMD0_VSYNC,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.start	= IRQ_FIMD0_FIFO,
-		.end	= IRQ_FIMD0_FIFO,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[3] = {
-		.start	= IRQ_FIMD0_SYSTEM,
-		.end	= IRQ_FIMD0_SYSTEM,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S5P, FIMD0, SZ_32K),
+	[1] = SAMSUNG_RES_IRQ(FIMD0_VSYNC),
+	[2] = SAMSUNG_RES_IRQ(FIMD0_FIFO),
+	[3] = SAMSUNG_RES_IRQ(FIMD0_SYSTEM),
 };
 
 struct platform_device s5p_device_fimd0 = {
@@ -425,20 +306,10 @@ void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
 
 /* HSMMC */
 
-#define S3C_SZ_HSMMC	0x1000
-
 #ifdef CONFIG_S3C_DEV_HSMMC
 static struct resource s3c_hsmmc_resource[] = {
-	[0] = {
-		.start	= S3C_PA_HSMMC0,
-		.end	= S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_HSMMC0,
-		.end	= IRQ_HSMMC0,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C, HSMMC0, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(HSMMC0),
 };
 
 struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
@@ -468,16 +339,8 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
 
 #ifdef CONFIG_S3C_DEV_HSMMC1
 static struct resource s3c_hsmmc1_resource[] = {
-	[0] = {
-		.start	= S3C_PA_HSMMC1,
-		.end	= S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_HSMMC1,
-		.end	= IRQ_HSMMC1,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C, HSMMC1, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(HSMMC1),
 };
 
 struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
@@ -509,16 +372,8 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
 
 #ifdef CONFIG_S3C_DEV_HSMMC2
 static struct resource s3c_hsmmc2_resource[] = {
-	[0] = {
-		.start	= S3C_PA_HSMMC2,
-		.end	= S3C_PA_HSMMC2 + S3C_SZ_HSMMC - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_HSMMC2,
-		.end	= IRQ_HSMMC2,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C, HSMMC2, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(HSMMC2),
 };
 
 struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
@@ -548,16 +403,8 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
 
 #ifdef CONFIG_S3C_DEV_HSMMC3
 static struct resource s3c_hsmmc3_resource[] = {
-	[0] = {
-		.start	= S3C_PA_HSMMC3,
-		.end	= S3C_PA_HSMMC3 + S3C_SZ_HSMMC - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_HSMMC3,
-		.end	= IRQ_HSMMC3,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C, HSMMC3, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(HSMMC3),
 };
 
 struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
@@ -588,16 +435,8 @@ void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
 /* I2C */
 
 static struct resource s3c_i2c0_resource[] = {
-	[0] = {
-		.start	= S3C_PA_IIC,
-		.end	= S3C_PA_IIC + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_IIC,
-		.end	= IRQ_IIC,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C, IIC, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(IIC),
 };
 
 struct platform_device s3c_device_i2c0 = {
@@ -634,16 +473,8 @@ void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
 
 #ifdef CONFIG_S3C_DEV_I2C1
 static struct resource s3c_i2c1_resource[] = {
-	[0] = {
-		.start	= S3C_PA_IIC1,
-		.end	= S3C_PA_IIC1 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_IIC1,
-		.end	= IRQ_IIC1,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C, IIC1, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(IIC1),
 };
 
 struct platform_device s3c_device_i2c1 = {
@@ -672,16 +503,8 @@ void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
 
 #ifdef CONFIG_S3C_DEV_I2C2
 static struct resource s3c_i2c2_resource[] = {
-	[0] = {
-		.start	= S3C_PA_IIC2,
-		.end	= S3C_PA_IIC2 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_IIC2,
-		.end	= IRQ_IIC2,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C, IIC2, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(IIC2),
 };
 
 struct platform_device s3c_device_i2c2 = {
@@ -710,16 +533,8 @@ void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
 
 #ifdef CONFIG_S3C_DEV_I2C3
 static struct resource s3c_i2c3_resource[] = {
-	[0] = {
-		.start	= S3C_PA_IIC3,
-		.end	= S3C_PA_IIC3 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_IIC3,
-		.end	= IRQ_IIC3,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C, IIC3, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(IIC3),
 };
 
 struct platform_device s3c_device_i2c3 = {
@@ -748,16 +563,8 @@ void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
 
 #ifdef CONFIG_S3C_DEV_I2C4
 static struct resource s3c_i2c4_resource[] = {
-	[0] = {
-		.start	= S3C_PA_IIC4,
-		.end	= S3C_PA_IIC4 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_IIC4,
-		.end	= IRQ_IIC4,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C, IIC4, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(IIC4),
 };
 
 struct platform_device s3c_device_i2c4 = {
@@ -786,16 +593,8 @@ void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
 
 #ifdef CONFIG_S3C_DEV_I2C5
 static struct resource s3c_i2c5_resource[] = {
-	[0] = {
-		.start	= S3C_PA_IIC5,
-		.end	= S3C_PA_IIC5 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_IIC5,
-		.end	= IRQ_IIC5,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C, IIC5, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(IIC5),
 };
 
 struct platform_device s3c_device_i2c5 = {
@@ -824,16 +623,8 @@ void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
 
 #ifdef CONFIG_S3C_DEV_I2C6
 static struct resource s3c_i2c6_resource[] = {
-	[0] = {
-		.start	= S3C_PA_IIC6,
-		.end	= S3C_PA_IIC6 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_IIC6,
-		.end	= IRQ_IIC6,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C, IIC6, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(IIC6),
 };
 
 struct platform_device s3c_device_i2c6 = {
@@ -862,16 +653,8 @@ void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
 
 #ifdef CONFIG_S3C_DEV_I2C7
 static struct resource s3c_i2c7_resource[] = {
-	[0] = {
-		.start	= S3C_PA_IIC7,
-		.end	= S3C_PA_IIC7 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_IIC7,
-		.end	= IRQ_IIC7,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C, IIC7, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(IIC7),
 };
 
 struct platform_device s3c_device_i2c7 = {
@@ -902,16 +685,8 @@ void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
 
 #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
 static struct resource s5p_i2c_resource[] = {
-	[0] = {
-		.start	= S5P_PA_IIC_HDMIPHY,
-		.end	= S5P_PA_IIC_HDMIPHY + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_IIC_HDMIPHY,
-		.end	= IRQ_IIC_HDMIPHY,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S5P, IIC_HDMIPHY, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(IIC_HDMIPHY),
 };
 
 struct platform_device s5p_device_i2c_hdmiphy = {
@@ -945,11 +720,7 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
 
 #ifdef CONFIG_PLAT_S3C24XX
 static struct resource s3c_iis_resource[] = {
-	[0] = {
-		.start	= S3C24XX_PA_IIS,
-		.end	= S3C24XX_PA_IIS + S3C24XX_SZ_IIS - 1,
-		.flags	= IORESOURCE_MEM,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C24XX, IIS, S3C24XX_SZ_IIS),
 };
 
 struct platform_device s3c_device_iis = {
@@ -979,16 +750,8 @@ struct platform_device s3c2412_device_iis = {
 
 #ifdef CONFIG_SAMSUNG_DEV_IDE
 static struct resource s3c_cfcon_resource[] = {
-	[0] = {
-		.start	= SAMSUNG_PA_CFCON,
-		.end	= SAMSUNG_PA_CFCON + SZ_16K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_CFCON,
-		.end	= IRQ_CFCON,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(SAMSUNG, CFCON, SZ_16K),
+	[1] = SAMSUNG_RES_IRQ(CFCON),
 };
 
 struct platform_device s3c_device_cfcon = {
@@ -1008,16 +771,8 @@ void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
 
 #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
 static struct resource samsung_keypad_resources[] = {
-	[0] = {
-		.start	= SAMSUNG_PA_KEYPAD,
-		.end	= SAMSUNG_PA_KEYPAD + 0x20 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_KEYPAD,
-		.end	= IRQ_KEYPAD,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(SAMSUNG, KEYPAD, SZ_32),
+	[1] = SAMSUNG_RES_IRQ(KEYPAD),
 };
 
 struct platform_device samsung_device_keypad = {
@@ -1043,16 +798,8 @@ void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
 
 #ifdef CONFIG_PLAT_S3C24XX
 static struct resource s3c_lcd_resource[] = {
-	[0] = {
-		.start	= S3C24XX_PA_LCD,
-		.end	= S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_LCD,
-		.end	= IRQ_LCD,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C24XX, LCD, S3C24XX_SZ_LCD),
+	[1] = SAMSUNG_RES_IRQ(LCD),
 };
 
 struct platform_device s3c_device_lcd = {
@@ -1087,16 +834,8 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
 
 #ifdef CONFIG_S5P_DEV_MFC
 static struct resource s5p_mfc_resource[] = {
-	[0] = {
-		.start	= S5P_PA_MFC,
-		.end	= S5P_PA_MFC + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_MFC,
-		.end	= IRQ_MFC,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S5P, MFC, SZ_64K),
+	[1] = SAMSUNG_RES_IRQ(MFC),
 };
 
 struct platform_device s5p_device_mfc = {
@@ -1139,16 +878,8 @@ struct platform_device s5p_device_mfc_r = {
 
 #ifdef CONFIG_S5P_DEV_CSIS0
 static struct resource s5p_mipi_csis0_resource[] = {
-	[0] = {
-		.start	= S5P_PA_MIPI_CSIS0,
-		.end	= S5P_PA_MIPI_CSIS0 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_MIPI_CSIS0,
-		.end	= IRQ_MIPI_CSIS0,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S5P, MIPI_CSIS0, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(MIPI_CSIS0),
 };
 
 struct platform_device s5p_device_mipi_csis0 = {
@@ -1161,16 +892,8 @@ struct platform_device s5p_device_mipi_csis0 = {
 
 #ifdef CONFIG_S5P_DEV_CSIS1
 static struct resource s5p_mipi_csis1_resource[] = {
-	[0] = {
-		.start	= S5P_PA_MIPI_CSIS1,
-		.end	= S5P_PA_MIPI_CSIS1 + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_MIPI_CSIS1,
-		.end	= IRQ_MIPI_CSIS1,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S5P, MIPI_CSIS1, SZ_4K),
+	[1] = SAMSUNG_RES_IRQ(MIPI_CSIS1),
 };
 
 struct platform_device s5p_device_mipi_csis1 = {
@@ -1185,11 +908,7 @@ struct platform_device s5p_device_mipi_csis1 = {
 
 #ifdef CONFIG_S3C_DEV_NAND
 static struct resource s3c_nand_resource[] = {
-	[0] = {
-		.start	= S3C_PA_NAND,
-		.end	= S3C_PA_NAND + SZ_1M,
-		.flags	= IORESOURCE_MEM,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C, NAND, SZ_1M),
 };
 
 struct platform_device s3c_device_nand = {
@@ -1294,21 +1013,9 @@ void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
 
 #ifdef CONFIG_S3C_DEV_ONENAND
 static struct resource s3c_onenand_resources[] = {
-	[0] = {
-		.start	= S3C_PA_ONENAND,
-		.end	= S3C_PA_ONENAND + 0x400 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= S3C_PA_ONENAND_BUF,
-		.end	= S3C_PA_ONENAND_BUF + S3C_SZ_ONENAND_BUF - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[2] = {
-		.start	= IRQ_ONENAND,
-		.end	= IRQ_ONENAND,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C, ONENAND, SZ_1K),
+	[1] = SAMSUNG_RES_MEM(S3C, ONENAND_BUF, S3C_SZ_ONENAND_BUF),
+	[2] = SAMSUNG_RES_IRQ(ONENAND),
 };
 
 struct platform_device s3c_device_onenand = {
@@ -1321,21 +1028,9 @@ struct platform_device s3c_device_onenand = {
 
 #ifdef CONFIG_S3C64XX_DEV_ONENAND1
 static struct resource s3c64xx_onenand1_resources[] = {
-	[0] = {
-		.start	= S3C64XX_PA_ONENAND1,
-		.end	= S3C64XX_PA_ONENAND1 + 0x400 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= S3C64XX_PA_ONENAND1_BUF,
-		.end	= S3C64XX_PA_ONENAND1_BUF + S3C64XX_SZ_ONENAND1_BUF - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[2] = {
-		.start	= IRQ_ONENAND1,
-		.end	= IRQ_ONENAND1,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C64XX, ONENAND1, SZ_1K),
+	[1] = SAMSUNG_RES_MEM(S3C64XX, ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
+	[2] = SAMSUNG_RES_IRQ(ONENAND1),
 };
 
 struct platform_device s3c64xx_device_onenand1 = {
@@ -1354,21 +1049,9 @@ void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
 
 #ifdef CONFIG_S5P_DEV_ONENAND
 static struct resource s5p_onenand_resources[] = {
-	[0] = {
-		.start	= S5P_PA_ONENAND,
-		.end	= S5P_PA_ONENAND + SZ_128K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= S5P_PA_ONENAND_DMA,
-		.end	= S5P_PA_ONENAND_DMA + SZ_8K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[2] = {
-		.start	= IRQ_ONENAND_AUDI,
-		.end	= IRQ_ONENAND_AUDI,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S5P, ONENAND, SZ_128K),
+	[1] = SAMSUNG_RES_MEM(S5P, ONENAND_DMA, SZ_8K),
+	[2] = SAMSUNG_RES_IRQ(ONENAND_AUDI),
 };
 
 struct platform_device s5p_device_onenand = {
@@ -1382,17 +1065,15 @@ struct platform_device s5p_device_onenand = {
 /* PMU */
 
 #ifdef CONFIG_PLAT_S5P
-static struct resource s5p_pmu_resource = {
-	.start	= IRQ_PMU,
-	.end	= IRQ_PMU,
-	.flags	= IORESOURCE_IRQ,
+static struct resource s5p_pmu_resource[] = {
+	SAMSUNG_RES_IRQ(PMU)
 };
 
 struct platform_device s5p_device_pmu = {
 	.name		= "arm-pmu",
 	.id		= ARM_PMU_DEVICE_CPU,
-	.num_resources	= 1,
-	.resource	= &s5p_pmu_resource,
+	.num_resources	= ARRAY_SIZE(s5p_pmu_resource),
+	.resource	= s5p_pmu_resource,
 };
 
 static int __init s5p_pmu_init(void)
@@ -1442,21 +1123,9 @@ struct platform_device s3c_device_timer[] = {
 
 #ifdef CONFIG_PLAT_S3C24XX
 static struct resource s3c_rtc_resource[] = {
-	[0] = {
-		.start	= S3C24XX_PA_RTC,
-		.end	= S3C24XX_PA_RTC + 0xff,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_RTC,
-		.end	= IRQ_RTC,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.start	= IRQ_TICK,
-		.end	= IRQ_TICK,
-		.flags	= IORESOURCE_IRQ
-	}
+	[0] = SAMSUNG_RES_MEM(S3C24XX, RTC, SZ_256),
+	[1] = SAMSUNG_RES_IRQ(RTC),
+	[2] = SAMSUNG_RES_IRQ(TICK),
 };
 
 struct platform_device s3c_device_rtc = {
@@ -1469,21 +1138,9 @@ struct platform_device s3c_device_rtc = {
 
 #ifdef CONFIG_S3C_DEV_RTC
 static struct resource s3c_rtc_resource[] = {
-	[0] = {
-		.start	= S3C_PA_RTC,
-		.end	= S3C_PA_RTC + 0xff,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_RTC_ALARM,
-		.end	= IRQ_RTC_ALARM,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.start	= IRQ_RTC_TIC,
-		.end	= IRQ_RTC_TIC,
-		.flags	= IORESOURCE_IRQ
-	}
+	[0] = SAMSUNG_RES_MEM(S3C, RTC, SZ_256),
+	[1] = SAMSUNG_RES_IRQ(RTC_ALARM),
+	[2] = SAMSUNG_RES_IRQ(RTC_TIC),
 };
 
 struct platform_device s3c_device_rtc = {
@@ -1498,16 +1155,8 @@ struct platform_device s3c_device_rtc = {
 
 #ifdef CONFIG_PLAT_S3C24XX
 static struct resource s3c_sdi_resource[] = {
-	[0] = {
-		.start	= S3C24XX_PA_SDI,
-		.end	= S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_SDI,
-		.end	= IRQ_SDI,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C24XX, SDI, S3C24XX_SZ_SDI),
+	[1] = SAMSUNG_RES_IRQ(SDI),
 };
 
 struct platform_device s3c_device_sdi = {
@@ -1528,16 +1177,8 @@ void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
 
 #ifdef CONFIG_PLAT_S3C24XX
 static struct resource s3c_spi0_resource[] = {
-	[0] = {
-		.start	= S3C24XX_PA_SPI,
-		.end	= S3C24XX_PA_SPI + 0x1f,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_SPI0,
-		.end	= IRQ_SPI0,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C24XX, SPI, SZ_32),
+	[1] = SAMSUNG_RES_IRQ(SPI0),
 };
 
 struct platform_device s3c_device_spi0 = {
@@ -1552,16 +1193,8 @@ struct platform_device s3c_device_spi0 = {
 };
 
 static struct resource s3c_spi1_resource[] = {
-	[0] = {
-		.start	= S3C24XX_PA_SPI + S3C2410_SPI1,
-		.end	= S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_SPI1,
-		.end	= IRQ_SPI1,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C24XX, SPI1, SZ_32),
+	[1] = SAMSUNG_RES_IRQ(SPI1),
 };
 
 struct platform_device s3c_device_spi1 = {
@@ -1580,17 +1213,8 @@ struct platform_device s3c_device_spi1 = {
 
 #ifdef CONFIG_PLAT_S3C24XX
 static struct resource s3c_ts_resource[] = {
-	[0] = {
-		.start	= S3C24XX_PA_ADC,
-		.end	= S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_TC,
-		.end	= IRQ_TC,
-		.flags	= IORESOURCE_IRQ,
-	},
-
+	[0] = SAMSUNG_RES_MEM(S3C24XX, ADC, S3C24XX_SZ_ADC),
+	[1] = SAMSUNG_RES_IRQ(TC),
 };
 
 struct platform_device s3c_device_ts = {
@@ -1610,16 +1234,8 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_
 
 #ifdef CONFIG_SAMSUNG_DEV_TS
 static struct resource s3c_ts_resource[] = {
-	[0] = {
-		.start	= SAMSUNG_PA_ADC,
-		.end	= SAMSUNG_PA_ADC + SZ_256 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_TC,
-		.end	= IRQ_TC,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(SAMSUNG, ADC, SZ_256),
+	[1] = SAMSUNG_RES_IRQ(TC),
 };
 
 static struct s3c2410_ts_mach_info default_ts_data __initdata = {
@@ -1650,16 +1266,8 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
 #ifdef CONFIG_S5P_DEV_TV
 
 static struct resource s5p_hdmi_resources[] = {
-	[0] = {
-		.start	= S5P_PA_HDMI,
-		.end	= S5P_PA_HDMI + SZ_1M - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_HDMI,
-		.end	= IRQ_HDMI,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S5P, HDMI, SZ_1M),
+	[1] = SAMSUNG_RES_IRQ(HDMI),
 };
 
 struct platform_device s5p_device_hdmi = {
@@ -1670,16 +1278,8 @@ struct platform_device s5p_device_hdmi = {
 };
 
 static struct resource s5p_sdo_resources[] = {
-	[0] = {
-		.start	= S5P_PA_SDO,
-		.end	= S5P_PA_SDO + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_SDO,
-		.end	= IRQ_SDO,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S5P, SDO, SZ_64K),
+	[1] = SAMSUNG_RES_IRQ(SDO),
 };
 
 struct platform_device s5p_device_sdo = {
@@ -1690,24 +1290,9 @@ struct platform_device s5p_device_sdo = {
 };
 
 static struct resource s5p_mixer_resources[] = {
-	[0] = {
-		.start	= S5P_PA_MIXER,
-		.end	= S5P_PA_MIXER + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-		.name	= "mxr"
-	},
-	[1] = {
-		.start	= S5P_PA_VP,
-		.end	= S5P_PA_VP + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-		.name	= "vp"
-	},
-	[2] = {
-		.start	= IRQ_MIXER,
-		.end	= IRQ_MIXER,
-		.flags	= IORESOURCE_IRQ,
-		.name	= "irq"
-	}
+	[0] = SAMSUNG_RES_MEM_NAMED(S5P, MIXER, SZ_64K, "mxr"),
+	[1] = SAMSUNG_RES_MEM_NAMED(S5P, VP, SZ_64K, "vp"),
+	[2] = SAMSUNG_RES_IRQ_NAMED(MIXER, "irq"),
 };
 
 struct platform_device s5p_device_mixer = {
@@ -1726,16 +1311,8 @@ struct platform_device s5p_device_mixer = {
 
 #ifdef CONFIG_S3C_DEV_USB_HOST
 static struct resource s3c_usb_resource[] = {
-	[0] = {
-		.start	= S3C_PA_USBHOST,
-		.end	= S3C_PA_USBHOST + 0x100 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_USBH,
-		.end	= IRQ_USBH,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C, USBHOST, SZ_256),
+	[1] = SAMSUNG_RES_IRQ(USBH),
 };
 
 struct platform_device s3c_device_ohci = {
@@ -1769,16 +1346,8 @@ void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
 
 #ifdef CONFIG_PLAT_S3C24XX
 static struct resource s3c_usbgadget_resource[] = {
-	[0] = {
-		.start	= S3C24XX_PA_USBDEV,
-		.end	= S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_USBD,
-		.end	= IRQ_USBD,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C24XX, USBDEV, S3C24XX_SZ_USBDEV),
+	[1] = SAMSUNG_RES_IRQ(USBD),
 };
 
 struct platform_device s3c_device_usbgadget = {
@@ -1798,16 +1367,8 @@ void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
 
 #ifdef CONFIG_S5P_DEV_USB_EHCI
 static struct resource s5p_ehci_resource[] = {
-	[0] = {
-		.start	= S5P_PA_EHCI,
-		.end	= S5P_PA_EHCI + SZ_256 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_USB_HOST,
-		.end	= IRQ_USB_HOST,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S5P, EHCI, SZ_256),
+	[1] = SAMSUNG_RES_IRQ(USB_HOST),
 };
 
 struct platform_device s5p_device_ehci = {
@@ -1839,16 +1400,8 @@ void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
 
 #ifdef CONFIG_S3C_DEV_USB_HSOTG
 static struct resource s3c_usb_hsotg_resources[] = {
-	[0] = {
-		.start	= S3C_PA_USB_HSOTG,
-		.end	= S3C_PA_USB_HSOTG + 0x10000 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_OTG,
-		.end	= IRQ_OTG,
-		.flags	= IORESOURCE_IRQ,
-	},
+	[0] = SAMSUNG_RES_MEM(S3C, USB_HSOTG, SZ_16K),
+	[1] = SAMSUNG_RES_IRQ(OTG),
 };
 
 struct platform_device s3c_device_usb_hsotg = {
@@ -1867,16 +1420,8 @@ struct platform_device s3c_device_usb_hsotg = {
 
 #ifdef CONFIG_PLAT_S3C24XX
 static struct resource s3c_hsudc_resource[] = {
-	[0] = {
-		.start	= S3C2416_PA_HSUDC,
-		.end	= S3C2416_PA_HSUDC + S3C2416_SZ_HSUDC - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_USBD,
-		.end	= IRQ_USBD,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C2416, HSUDC, S3C2416_SZ_HSUDC),
+	[1] = SAMSUNG_RES_IRQ(USBD),
 };
 
 struct platform_device s3c_device_usb_hsudc = {
@@ -1900,16 +1445,8 @@ void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
 
 #ifdef CONFIG_S3C_DEV_WDT
 static struct resource s3c_wdt_resource[] = {
-	[0] = {
-		.start	= S3C_PA_WDT,
-		.end	= S3C_PA_WDT + SZ_1K,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_WDT,
-		.end	= IRQ_WDT,
-		.flags	= IORESOURCE_IRQ,
-	}
+	[0] = SAMSUNG_RES_MEM(S3C, WDT, SZ_1K),
+	[1] = SAMSUNG_RES_IRQ(WDT),
 };
 
 struct platform_device s3c_device_wdt = {
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 8f19241..a506831 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -18,6 +18,17 @@
 
 #include <linux/platform_device.h>
 
+#define SAMSUNG_RES_MEM(soc, ip, sz)	DEFINE_RES_MEM(soc##_PA_##ip, sz)
+#define SAMSUNG_RES_IRQ(ip)		DEFINE_RES_IRQ(IRQ_##ip)
+
+#define SAMSUNG_RES_MEM_NAMED(soc, ip, sz, name)	\
+				DEFINE_RES_MEM_NAMED(soc##_PA_##ip, sz, name)
+#define SAMSUNG_RES_IRQ_NAMED(ip, name)			\
+				DEFINE_RES_IRQ_NAMED(IRQ_##ip, name)
+#define SAMSUNG_RES_DMA_NAMED(ch, name)			\
+				DEFINE_RES_DMA_NAMED(DMACH_##ch, name)
+
+
 struct s3c24xx_uart_resources {
 	struct resource		*resources;
 	unsigned long		 nr_resources;
-- 
1.7.1

^ permalink raw reply related

* [GIT PULL] Samsung devel-2 for v3.2
From: Kukjin Kim @ 2011-10-03  3:27 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20111002192950.GB1005@sirena.org.uk>

Mark Brown wrote:
> 
> On Sun, Oct 02, 2011 at 06:25:36PM +0900, Kukjin Kim wrote:
> 
> >       gpio/samsung: gpio-samsung.c to support Samsung GPIOs
> 
> As I reported the other day this change breaks the boot early on on the
> Cragganmore S3C6410 based systems (I've not actually fired up my
> SMDK6410 but I suspect it may have issues too).  I did make some brief
> attempts to debug but as there's no console output at all and the diff
> is rather large it's not easy to see what's gone wrong.

Hmm, I thought it has no problem when I saw Thomas Abraham's 'serial:
samsung' patches because he said it works fine with my for-next plus his
patches on SMDK6410...Anyway, I need to sort it out.

Arnd, please hold this on, will request again soon.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

^ permalink raw reply

* [PATCH 0/4] ARM: EXYNOS4: Support generic Power domain framework for EXYNOS4210
From: Kukjin Kim @ 2011-10-03  3:27 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <201110022000.56556.rjw@sisk.pl>

Rafael J. Wysocki wrote:
> 
> On Sunday, October 02, 2011, Russell King - ARM Linux wrote:
> > On Sun, Oct 02, 2011 at 03:08:43PM +0200, Rafael J. Wysocki wrote:
> > > On Sunday, October 02, 2011, Russell King - ARM Linux wrote:
> > > > How do these misconceptions start?
> > > >
> > > > The clock API.  Drivers are supposed to get a clock (source) when
they
> > > > initialize.  Drivers then enable and disable the clock as they
_themselves_
> > > > require the use of that clock.
> > >
> > > OK
> > >
> > > Now think of a driver that should handle the same device on both ARM
and
> > > x86-based SoCs.  Is the clock API available on x86?
> >
> > No one's bothered yet.
> 
> Prehaps because x86 doesn't allow us to control device clocks directly.
> They are controlled through PCI PM or through ACPI methods, both of which
> hide the clocks behind abstract low-power states we're supposed to use.
> 
Well, I think Embedded drivers especially ARM sometimes need to control its
own clock directly and each embedded drivers know when clock controlling is
required or not. Actually, Samsung driver stuff have calling clk_enable() in
probe() or open() and clk_disable() when clock is not needed more. But I'm
not sure we _really_ can get some benefits when matching clock and power
control on ARM devices.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

^ permalink raw reply

* [PATCH 2/2] ARM: SAMSUNG: Cleanup resources by using macro
From: Kukjin Kim @ 2011-10-03  3:27 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20111002110724.GT11710@n2100.arm.linux.org.uk>

Russell King - ARM Linux wrote:
> 
> On Sun, Oct 02, 2011 at 06:24:40PM +0900, Kukjin Kim wrote:
> > This patch adds macro SAMSUNG_RES_MEM and SAMSUNG_RES_IRQ to
> cleanup
> > regarding 'struct resource'
> 
> Why not include the braces inside the macro as well?
> 
I thought, if other member such as name is required additionally, can add it
like following.

[0] = { SAMSUNG_RES_MEM(xxx, xxx, xxx), .name = "xxx" },

But below helpers can do it :)

> > diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-
> samsung/include/plat/devs.h
> > index 8f19241..8b8bd1c 100644
> > --- a/arch/arm/plat-samsung/include/plat/devs.h
> > +++ b/arch/arm/plat-samsung/include/plat/devs.h
> > @@ -18,6 +18,16 @@
> >
> >  #include <linux/platform_device.h>
> >
> > +#define SAMSUNG_RES_MEM(soc, ip, sz)			\
> > +		.start	= soc##_PA_##ip,		\
> > +		.end	= soc##_PA_##ip + sz - 1,	\
> > +		.flags	= IORESOURCE_MEM,
> > +
> > +#define SAMSUNG_RES_IRQ(ip)				\
> > +		.start	= IRQ_##ip,			\
> > +		.end	= IRQ_##ip,			\
> > +		.flags	= IORESOURCE_IRQ,
> > +
> 
> How about using DEFINE_RES_MEM and DEFINE_RES_IRQ here?
> 
> #define SAMSUNG_RES_MEM(soc, ip, sz) DEFINE_RES_MEM(soc##_PA_##ip,
> sz)
> #define SAMSUNG_RES_IRQ(ip) DEFINE_RES_IRQ(IRQ_##ip)

Great, I don't know why I couldn't find it and nobody use it now...

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

^ permalink raw reply

* [PATCH v2] ARM: EXYNOS4: Configure MAX8997 PMIC for Origen
From: Kukjin Kim @ 2011-10-03  3:27 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1313995163-31737-1-git-send-email-inderpal.singh@linaro.org>

Kukjin Kim wrote:
> 
> Inderpal Singh wrote:
> >
> > From: Inderpal Singh <inderpal.s@samsung.com>
                                     ^^^^^^^^^^^
> >
> > Configure MAX8997 PMIC and provide platform specific data
> > for origen.
> >
> > Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
                                                  ^^^^^^^^^^

Hi Inderpal,

You need to change your e-mail address of author or sign. Basically they
should be same. Which one do you want to use?
Then you should make sure your .gitconfig has same e-mail address......

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

^ permalink raw reply

* [PATCH v5 8/8] arm/imx: merge i.MX3 and i.MX6
From: Shawn Guo @ 2011-10-03  2:57 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1317610626-24357-1-git-send-email-shawn.guo@linaro.org>

From: Sascha Hauer <s.hauer@pengutronix.de>

The patch merges the build of imx3 and imx6.  The Kconfig symbol
ARCH_IMX_V6_V7 is introduced to replace ARCH_MX3 and ARCH_MX6.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 arch/arm/Makefile               |    3 +--
 arch/arm/mach-imx/Kconfig       |    7 +++----
 arch/arm/mach-imx/Makefile.boot |   10 +++++++---
 arch/arm/mm/Kconfig             |    4 ++--
 arch/arm/plat-mxc/Kconfig       |   18 +++++++-----------
 5 files changed, 20 insertions(+), 22 deletions(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 193439e..4e98937 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -158,9 +158,8 @@ machine-$(CONFIG_ARCH_MMP)		:= mmp
 machine-$(CONFIG_ARCH_MSM)		:= msm
 machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
 machine-$(CONFIG_ARCH_IMX_V4_V5)	:= imx
-machine-$(CONFIG_ARCH_MX3)		:= imx
+machine-$(CONFIG_ARCH_IMX_V6_V7)	:= imx
 machine-$(CONFIG_ARCH_MX5)		:= mx5
-machine-$(CONFIG_ARCH_MX6)		:= imx
 machine-$(CONFIG_ARCH_MXS)		:= mxs
 machine-$(CONFIG_ARCH_NETX)		:= netx
 machine-$(CONFIG_ARCH_NOMADIK)		:= nomadik
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3852f45..27355cb 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -74,6 +74,7 @@ config SOC_IMX31
 	select ARCH_MXC_AUDMUX_V2
 	select ARCH_MX31
 	select MXC_AVIC
+	select SMP_ON_UP if SMP
 
 config SOC_IMX35
 	bool
@@ -83,6 +84,7 @@ config SOC_IMX35
 	select HAVE_EPIT
 	select ARCH_MX35
 	select MXC_AVIC
+	select SMP_ON_UP if SMP
 
 
 if ARCH_IMX_V4_V5
@@ -351,7 +353,7 @@ config MACH_IMX27IPCAM
 
 endif
 
-if ARCH_MX3
+if ARCH_IMX_V6_V7
 
 comment "MX31 platforms:"
 
@@ -601,9 +603,6 @@ config MACH_VPR200
 	  Include support for VPR200 platform. This includes specific
 	  configurations for the board and its peripherals.
 
-endif
-
-if ARCH_MX6
 comment "i.MX6 family:"
 
 config SOC_IMX6Q
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 22d8588..c349a96 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -14,9 +14,13 @@ zreladdr-$(CONFIG_MACH_MX27)	+= 0xA0008000
 params_phys-$(CONFIG_MACH_MX27)	:= 0xA0000100
 initrd_phys-$(CONFIG_MACH_MX27)	:= 0xA0800000
 
-zreladdr-$(CONFIG_ARCH_MX3)	+= 0x80008000
-params_phys-$(CONFIG_ARCH_MX3)	:= 0x80000100
-initrd_phys-$(CONFIG_ARCH_MX3)	:= 0x80800000
+zreladdr-$(CONFIG_SOC_IMX31)	+= 0x80008000
+params_phys-$(CONFIG_SOC_IMX31)	:= 0x80000100
+initrd_phys-$(CONFIG_SOC_IMX31)	:= 0x80800000
+
+zreladdr-$(CONFIG_SOC_IMX35)	+= 0x80008000
+params_phys-$(CONFIG_SOC_IMX35)	:= 0x80000100
+initrd_phys-$(CONFIG_SOC_IMX35)	:= 0x80800000
 
 zreladdr-$(CONFIG_SOC_IMX6Q)	+= 0x10008000
 params_phys-$(CONFIG_SOC_IMX6Q)	:= 0x10000100
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c3ce146..9ab5be0 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -819,10 +819,10 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
 	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-		   REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
+		   REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
 		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
 		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
-		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_MX6
+		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX
 	default y
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 058d1c5..2704951 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -6,7 +6,7 @@ menu "Freescale MXC Implementations"
 
 choice
 	prompt "Freescale CPU family:"
-	default ARCH_MX3
+	default ARCH_IMX_V6_V7
 
 config ARCH_IMX_V4_V5
 	bool "i.MX1, i.MX21, i.MX25, i.MX27"
@@ -16,10 +16,13 @@ config ARCH_IMX_V4_V5
 	  This enables support for systems based on the Freescale i.MX ARMv4
 	  and ARMv5 SoCs
 
-config ARCH_MX3
-	bool "MX3-based"
+config ARCH_IMX_V6_V7
+	bool "i.MX3, i.MX6"
+	select AUTO_ZRELADDR if !ZBOOT_ROM
+	select ARM_PATCH_PHYS_VIRT
 	help
-	  This enables support for systems based on the Freescale i.MX3 family
+	  This enables support for systems based on the Freescale i.MX3 and i.MX6
+	  family.
 
 config ARCH_MX5
 	bool "i.MX50, i.MX51, i.MX53"
@@ -29,13 +32,6 @@ config ARCH_MX5
 	  This enables support for machines using Freescale's i.MX50 and i.MX51
 	  processors.
 
-config ARCH_MX6
-	bool "i.MX6"
-	select AUTO_ZRELADDR if !ZBOOT_ROM
-	select ARM_PATCH_PHYS_VIRT
-	help
-	  This enables support for systems based on the Freescale i.MX6 family
-
 endchoice
 
 source "arch/arm/mach-imx/Kconfig"
-- 
1.7.4.1

^ permalink raw reply related

* [PATCH v5 7/8] arm/imx6q: add suspend/resume support
From: Shawn Guo @ 2011-10-03  2:57 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1317610626-24357-1-git-send-email-shawn.guo@linaro.org>

It adds suspend/resume support for imx6q.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 arch/arm/mach-imx/Makefile              |    2 +-
 arch/arm/mach-imx/head-v7.S             |   28 ++++++++++++
 arch/arm/mach-imx/pm-imx6q.c            |   70 +++++++++++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/common.h |    9 ++++
 4 files changed, 108 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-imx/pm-imx6q.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 994ae82..aba7321 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -70,4 +70,4 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
-obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S
index ede908b..6229efb 100644
--- a/arch/arm/mach-imx/head-v7.S
+++ b/arch/arm/mach-imx/head-v7.S
@@ -12,6 +12,7 @@
 
 #include <linux/linkage.h>
 #include <linux/init.h>
+#include <asm/asm-offsets.h>
 #include <asm/hardware/cache-l2x0.h>
 
 	.section ".text.head", "ax"
@@ -69,3 +70,30 @@ ENTRY(v7_secondary_startup)
 	b	secondary_startup
 ENDPROC(v7_secondary_startup)
 #endif
+
+/*
+ * The following code is located into the .data section.  This is to
+ * allow phys_l2x0_saved_regs to be accessed with a relative load
+ * as we are running on physical address here.
+ */
+	.data
+	.align
+
+	.macro	pl310_resume
+	ldr	r2, phys_l2x0_saved_regs
+	ldr	r0, [r2, #L2X0_R_PHY_BASE]	@ get physical base of l2x0
+	ldr	r1, [r2, #L2X0_R_AUX_CTRL]	@ get aux_ctrl value
+	str	r1, [r0, #L2X0_AUX_CTRL]	@ restore aux_ctrl
+	mov	r1, #0x1
+	str	r1, [r0, #L2X0_CTRL]		@ re-enable L2
+	.endm
+
+ENTRY(v7_cpu_resume)
+	bl	v7_invalidate_l1
+	pl310_resume
+	b	cpu_resume
+ENDPROC(v7_cpu_resume)
+
+	.globl	phys_l2x0_saved_regs
+phys_l2x0_saved_regs:
+        .long   0
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
new file mode 100644
index 0000000..f20f191
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/suspend.h>
+#include <asm/cacheflush.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+
+extern unsigned long phys_l2x0_saved_regs;
+
+static int imx6q_suspend_finish(unsigned long val)
+{
+	cpu_do_idle();
+	return 0;
+}
+
+static int imx6q_pm_enter(suspend_state_t state)
+{
+	switch (state) {
+	case PM_SUSPEND_MEM:
+		imx6q_set_lpm(STOP_POWER_OFF);
+		imx_gpc_pre_suspend();
+		imx_set_cpu_jump(0, v7_cpu_resume);
+		/* Zzz ... */
+		cpu_suspend(0, imx6q_suspend_finish);
+		imx_smp_prepare();
+		imx_gpc_post_resume();
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct platform_suspend_ops imx6q_pm_ops = {
+	.enter = imx6q_pm_enter,
+	.valid = suspend_valid_only_mem,
+};
+
+void __init imx6q_pm_init(void)
+{
+	/*
+	 * The l2x0 core code provides an infrastucture to save and restore
+	 * l2x0 registers across suspend/resume cycle.  But because imx6q
+	 * retains L2 content during suspend and needs to resume L2 before
+	 * MMU is enabled, it can only utilize register saving support and
+	 * have to take care of restoring on its own.  So we save physical
+	 * address of the data structure used by l2x0 core to save registers,
+	 * and later restore the necessary ones in imx6q resume entry.
+	 */
+	phys_l2x0_saved_regs = __pa(&l2x0_saved_regs);
+
+	suspend_set_ops(&imx6q_pm_ops);
+}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 607b462..6a7d993 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -13,6 +13,7 @@
 
 struct platform_device;
 struct clk;
+enum mxc_cpu_pwr_mode;
 
 extern void mx1_map_io(void);
 extern void mx21_map_io(void);
@@ -107,14 +108,22 @@ extern void imx_lluart_map_io(void);
 #else
 static inline void imx_lluart_map_io(void) {}
 #endif
+extern void v7_cpu_resume(void);
+extern u32 *pl310_get_save_ptr(void);
 #ifdef CONFIG_SMP
 extern void v7_secondary_startup(void);
 extern void imx_scu_map_io(void);
+extern void imx_smp_prepare(void);
 #else
 static inline void imx_scu_map_io(void) {}
+static inline void imx_smp_prepare(void) {}
 #endif
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
 extern void imx_src_init(void);
 extern void imx_gpc_init(void);
+extern void imx_gpc_pre_suspend(void);
+extern void imx_gpc_post_resume(void);
+extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
+extern void imx6q_pm_init(void);
 #endif
-- 
1.7.4.1

^ permalink raw reply related

* [PATCH v5 6/8] arm/imx6q: add device tree machine support
From: Shawn Guo @ 2011-10-03  2:57 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1317610626-24357-1-git-send-email-shawn.guo@linaro.org>

It adds generic device tree based machine support for imx6q.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 arch/arm/mach-imx/Makefile              |    2 +-
 arch/arm/mach-imx/mach-imx6q.c          |   84 +++++++++++++++++++++++++++++++
 arch/arm/mm/Kconfig                     |    2 +-
 arch/arm/plat-mxc/include/mach/common.h |   13 +++++
 4 files changed, 99 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-imx/mach-imx6q.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f109850..994ae82 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -70,4 +70,4 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
-obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
new file mode 100644
index 0000000..8bf5fa3
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+
+static void __init imx6q_init_machine(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+
+	imx6q_pm_init();
+}
+
+static void __init imx6q_map_io(void)
+{
+	imx_lluart_map_io();
+	imx_scu_map_io();
+}
+
+static void __init imx6q_gpio_add_irq_domain(struct device_node *np,
+				struct device_node *interrupt_parent)
+{
+	static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
+				   32 * 7; /* imx6q gets 7 gpio ports */
+
+	irq_domain_add_simple(np, gpio_irq_base);
+	gpio_irq_base += 32;
+}
+
+static const struct of_device_id imx6q_irq_match[] __initconst = {
+	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{ .compatible = "fsl,imx6q-gpio", .data = imx6q_gpio_add_irq_domain, },
+	{ /* sentinel */ }
+};
+
+static void __init imx6q_init_irq(void)
+{
+	l2x0_of_init(0, ~0UL);
+	imx_src_init();
+	imx_gpc_init();
+	of_irq_init(imx6q_irq_match);
+}
+
+static void __init imx6q_timer_init(void)
+{
+	mx6q_clocks_init();
+}
+
+static struct sys_timer imx6q_timer = {
+	.init = imx6q_timer_init,
+};
+
+static const char *imx6q_dt_compat[] __initdata = {
+	"fsl,imx6q-sabreauto",
+	NULL,
+};
+
+DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
+	.map_io		= imx6q_map_io,
+	.init_irq	= imx6q_init_irq,
+	.handle_irq	= imx6q_handle_irq,
+	.timer		= &imx6q_timer,
+	.init_machine	= imx6q_init_machine,
+	.dt_compat	= imx6q_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 88633fe..c3ce146 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -822,7 +822,7 @@ config CACHE_L2X0
 		   REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
 		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
 		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
-		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX
+		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_MX6
 	default y
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 6340df2..607b462 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -64,6 +64,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
 			unsigned long ckih1, unsigned long ckih2);
 extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
 			unsigned long ckih1, unsigned long ckih2);
+extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
 	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
@@ -101,7 +102,19 @@ void gic_handle_irq(struct pt_regs *);
 
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+#ifdef CONFIG_DEBUG_LL
+extern void imx_lluart_map_io(void);
+#else
+static inline void imx_lluart_map_io(void) {}
+#endif
 #ifdef CONFIG_SMP
 extern void v7_secondary_startup(void);
+extern void imx_scu_map_io(void);
+#else
+static inline void imx_scu_map_io(void) {}
 #endif
+extern void imx_enable_cpu(int cpu, bool enable);
+extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+extern void imx_src_init(void);
+extern void imx_gpc_init(void);
 #endif
-- 
1.7.4.1

^ permalink raw reply related

* [PATCH v5 5/8] arm/imx6q: add smp and cpu hotplug support
From: Shawn Guo @ 2011-10-03  2:57 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1317610626-24357-1-git-send-email-shawn.guo@linaro.org>

It adds smp and cpu hotplug support for imx6q.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 arch/arm/mach-imx/Kconfig               |    1 +
 arch/arm/mach-imx/Makefile              |    5 ++
 arch/arm/mach-imx/head-v7.S             |   71 ++++++++++++++++++++++++++
 arch/arm/mach-imx/hotplug.c             |   44 ++++++++++++++++
 arch/arm/mach-imx/localtimer.c          |   35 +++++++++++++
 arch/arm/mach-imx/platsmp.c             |   85 +++++++++++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/common.h |    5 ++
 7 files changed, 246 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-imx/head-v7.S
 create mode 100644 arch/arm/mach-imx/hotplug.c
 create mode 100644 arch/arm/mach-imx/localtimer.c
 create mode 100644 arch/arm/mach-imx/platsmp.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 5e87372..3852f45 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -610,6 +610,7 @@ config SOC_IMX6Q
 	bool "i.MX6 Quad support"
 	select ARM_GIC
 	select CPU_V7
+	select HAVE_ARM_SCU
 	select HAVE_IMX_GPC
 	select HAVE_IMX_MMDC
 	select HAVE_IMX_SRC
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 65218d9..f109850 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -65,4 +65,9 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
 obj-$(CONFIG_HAVE_IMX_SRC) += src.o
+obj-$(CONFIG_CPU_V7) += head-v7.o
+AFLAGS_head-v7.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_SMP) += platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
 obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o
diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S
new file mode 100644
index 0000000..ede908b
--- /dev/null
+++ b/arch/arm/mach-imx/head-v7.S
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/hardware/cache-l2x0.h>
+
+	.section ".text.head", "ax"
+	__CPUINIT
+
+/*
+ * The secondary kernel init calls v7_flush_dcache_all before it enables
+ * the L1; however, the L1 comes out of reset in an undefined state, so
+ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ * of cache lines with uninitialized data and uninitialized tags to get
+ * written out to memory, which does really unpleasant things to the main
+ * processor.  We fix this by performing an invalidate, rather than a
+ * clean + invalidate, before jumping into the kernel.
+ *
+ * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
+ * to be called for both secondary cores startup and primary core resume
+ * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
+ */
+ENTRY(v7_invalidate_l1)
+	mov	r0, #0
+	mcr	p15, 2, r0, c0, c0, 0
+	mrc	p15, 1, r0, c0, c0, 0
+
+	ldr	r1, =0x7fff
+	and	r2, r1, r0, lsr #13
+
+	ldr	r1, =0x3ff
+
+	and	r3, r1, r0, lsr #3	@ NumWays - 1
+	add	r2, r2, #1		@ NumSets
+
+	and	r0, r0, #0x7
+	add	r0, r0, #4	@ SetShift
+
+	clz	r1, r3		@ WayShift
+	add	r4, r3, #1	@ NumWays
+1:	sub	r2, r2, #1	@ NumSets--
+	mov	r3, r4		@ Temp = NumWays
+2:	subs	r3, r3, #1	@ Temp--
+	mov	r5, r3, lsl r1
+	mov	r6, r2, lsl r0
+	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+	mcr	p15, 0, r5, c7, c6, 2
+	bgt	2b
+	cmp	r2, #0
+	bgt	1b
+	dsb
+	isb
+	mov	pc, lr
+ENDPROC(v7_invalidate_l1)
+
+#ifdef CONFIG_SMP
+ENTRY(v7_secondary_startup)
+	bl	v7_invalidate_l1
+	b	secondary_startup
+ENDPROC(v7_secondary_startup)
+#endif
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
new file mode 100644
index 0000000..89493ab
--- /dev/null
+++ b/arch/arm/mach-imx/hotplug.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later@the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/errno.h>
+#include <asm/cacheflush.h>
+#include <mach/common.h>
+
+int platform_cpu_kill(unsigned int cpu)
+{
+	return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+	flush_cache_all();
+	imx_enable_cpu(cpu, false);
+	cpu_do_idle();
+
+	/* We should never return from idle */
+	panic("cpu %d unexpectedly exit from shutdown\n", cpu);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+	/*
+	 * we don't allow CPU 0 to be shutdown (it is still too special
+	 * e.g. clock tick interrupts)
+	 */
+	return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-imx/localtimer.c b/arch/arm/mach-imx/localtimer.c
new file mode 100644
index 0000000..3a16351
--- /dev/null
+++ b/arch/arm/mach-imx/localtimer.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/clockchips.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/smp_twd.h>
+
+/*
+ * Setup the local clock events for a CPU.
+ */
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
+	if (!twd_base) {
+		twd_base = of_iomap(np, 0);
+		WARN_ON(!twd_base);
+	}
+	evt->irq = irq_of_parse_and_map(np, 0);
+	twd_timer_setup(evt);
+
+	return 0;
+}
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
new file mode 100644
index 0000000..ab98c6f
--- /dev/null
+++ b/arch/arm/mach-imx/platsmp.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <asm/page.h>
+#include <asm/smp_scu.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+
+static void __iomem *scu_base;
+
+static struct map_desc scu_io_desc __initdata = {
+	/* .virtual and .pfn are run-time assigned */
+	.length		= SZ_4K,
+	.type		= MT_DEVICE,
+};
+
+void __init imx_scu_map_io(void)
+{
+	unsigned long base;
+
+	/* Get SCU base */
+	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+	scu_io_desc.virtual = IMX_IO_P2V(base);
+	scu_io_desc.pfn = __phys_to_pfn(base);
+	iotable_init(&scu_io_desc, 1);
+
+	scu_base = IMX_IO_ADDRESS(base);
+}
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+	/*
+	 * if any interrupts are already enabled for the primary
+	 * core (e.g. timer irq), then they will not have been enabled
+	 * for us: do so
+	 */
+	gic_secondary_init(0);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	imx_set_cpu_jump(cpu, v7_secondary_startup);
+	imx_enable_cpu(cpu, true);
+	return 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+	int i, ncores;
+
+	ncores = scu_get_core_count(scu_base);
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+
+	set_smp_cross_call(gic_raise_softirq);
+}
+
+void imx_smp_prepare(void)
+{
+	scu_enable(scu_base);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+	imx_smp_prepare();
+}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index c225837..6340df2 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -99,4 +99,9 @@ void gic_handle_irq(struct pt_regs *);
 #define imx53_handle_irq tzic_handle_irq
 #define imx6q_handle_irq gic_handle_irq
 
+extern void imx_enable_cpu(int cpu, bool enable);
+extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+#ifdef CONFIG_SMP
+extern void v7_secondary_startup(void);
+#endif
 #endif
-- 
1.7.4.1

^ permalink raw reply related

* [PATCH v5 4/8] arm/imx6q: add core drivers clock, gpc, mmdc and src
From: Shawn Guo @ 2011-10-03  2:57 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1317610626-24357-1-git-send-email-shawn.guo@linaro.org>

It adds a number of core drivers support for imx6q, including clock,
General Power Controller (gpc), Multi Mode DDR Controller(mmdc) and
System Reset Controller (src).

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 arch/arm/mach-imx/Kconfig       |   13 +
 arch/arm/mach-imx/Makefile      |    4 +
 arch/arm/mach-imx/clock-imx6q.c | 2012 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/gpc.c         |  113 +++
 arch/arm/mach-imx/mmdc.c        |   72 ++
 arch/arm/mach-imx/src.c         |   49 +
 6 files changed, 2263 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-imx/clock-imx6q.c
 create mode 100644 arch/arm/mach-imx/gpc.c
 create mode 100644 arch/arm/mach-imx/mmdc.c
 create mode 100644 arch/arm/mach-imx/src.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index be402fa..5e87372 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,5 +1,15 @@
 config IMX_HAVE_DMA_V1
 	bool
+
+config HAVE_IMX_GPC
+	bool
+
+config HAVE_IMX_MMDC
+	bool
+
+config HAVE_IMX_SRC
+	bool
+
 #
 # ARCH_MX31 and ARCH_MX35 are left for compatibility
 # Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
@@ -600,6 +610,9 @@ config SOC_IMX6Q
 	bool "i.MX6 Quad support"
 	select ARM_GIC
 	select CPU_V7
+	select HAVE_IMX_GPC
+	select HAVE_IMX_MMDC
+	select HAVE_IMX_SRC
 	select USE_OF
 
 	help
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index b9ed198..65218d9 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -62,3 +62,7 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
 obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
 
 obj-$(CONFIG_DEBUG_LL) += lluart.o
+obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
+obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
+obj-$(CONFIG_HAVE_IMX_SRC) += src.o
+obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
new file mode 100644
index 0000000..66f4add
--- /dev/null
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -0,0 +1,2012 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/div64.h>
+#include <asm/mach/map.h>
+#include <mach/clock.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+
+#define PLL_BASE		IMX_IO_ADDRESS(MX6Q_ANATOP_BASE_ADDR)
+#define PLL1_SYS		(PLL_BASE + 0x000)
+#define PLL2_BUS		(PLL_BASE + 0x030)
+#define PLL3_USB_OTG		(PLL_BASE + 0x010)
+#define PLL4_AUDIO		(PLL_BASE + 0x070)
+#define PLL5_VIDEO		(PLL_BASE + 0x0a0)
+#define PLL6_MLB		(PLL_BASE + 0x0d0)
+#define PLL7_USB_HOST		(PLL_BASE + 0x020)
+#define PLL8_ENET		(PLL_BASE + 0x0e0)
+#define PFD_480			(PLL_BASE + 0x0f0)
+#define PFD_528			(PLL_BASE + 0x100)
+#define PLL_NUM_OFFSET		0x010
+#define PLL_DENOM_OFFSET	0x020
+
+#define PFD0			7
+#define PFD1			15
+#define PFD2			23
+#define PFD3			31
+#define PFD_FRAC_MASK		0x3f
+
+#define BM_PLL_BYPASS			(0x1 << 16)
+#define BM_PLL_ENABLE			(0x1 << 13)
+#define BM_PLL_POWER_DOWN		(0x1 << 12)
+#define BM_PLL_LOCK			(0x1 << 31)
+#define BP_PLL_SYS_DIV_SELECT		0
+#define BM_PLL_SYS_DIV_SELECT		(0x7f << 0)
+#define BP_PLL_BUS_DIV_SELECT		0
+#define BM_PLL_BUS_DIV_SELECT		(0x1 << 0)
+#define BP_PLL_USB_DIV_SELECT		0
+#define BM_PLL_USB_DIV_SELECT		(0x3 << 0)
+#define BP_PLL_AV_DIV_SELECT		0
+#define BM_PLL_AV_DIV_SELECT		(0x7f << 0)
+#define BP_PLL_ENET_DIV_SELECT		0
+#define BM_PLL_ENET_DIV_SELECT		(0x3 << 0)
+#define BM_PLL_ENET_EN_PCIE		(0x1 << 19)
+#define BM_PLL_ENET_EN_SATA		(0x1 << 20)
+
+#define CCM_BASE	IMX_IO_ADDRESS(MX6Q_CCM_BASE_ADDR)
+#define CCR		(CCM_BASE + 0x00)
+#define CCDR		(CCM_BASE + 0x04)
+#define CSR		(CCM_BASE + 0x08)
+#define CCSR		(CCM_BASE + 0x0c)
+#define CACRR		(CCM_BASE + 0x10)
+#define CBCDR		(CCM_BASE + 0x14)
+#define CBCMR		(CCM_BASE + 0x18)
+#define CSCMR1		(CCM_BASE + 0x1c)
+#define CSCMR2		(CCM_BASE + 0x20)
+#define CSCDR1		(CCM_BASE + 0x24)
+#define CS1CDR		(CCM_BASE + 0x28)
+#define CS2CDR		(CCM_BASE + 0x2c)
+#define CDCDR		(CCM_BASE + 0x30)
+#define CHSCCDR		(CCM_BASE + 0x34)
+#define CSCDR2		(CCM_BASE + 0x38)
+#define CSCDR3		(CCM_BASE + 0x3c)
+#define CSCDR4		(CCM_BASE + 0x40)
+#define CWDR		(CCM_BASE + 0x44)
+#define CDHIPR		(CCM_BASE + 0x48)
+#define CDCR		(CCM_BASE + 0x4c)
+#define CTOR		(CCM_BASE + 0x50)
+#define CLPCR		(CCM_BASE + 0x54)
+#define CISR		(CCM_BASE + 0x58)
+#define CIMR		(CCM_BASE + 0x5c)
+#define CCOSR		(CCM_BASE + 0x60)
+#define CGPR		(CCM_BASE + 0x64)
+#define CCGR0		(CCM_BASE + 0x68)
+#define CCGR1		(CCM_BASE + 0x6c)
+#define CCGR2		(CCM_BASE + 0x70)
+#define CCGR3		(CCM_BASE + 0x74)
+#define CCGR4		(CCM_BASE + 0x78)
+#define CCGR5		(CCM_BASE + 0x7c)
+#define CCGR6		(CCM_BASE + 0x80)
+#define CCGR7		(CCM_BASE + 0x84)
+#define CMEOR		(CCM_BASE + 0x88)
+
+#define CG0		0
+#define CG1		2
+#define CG2		4
+#define CG3		6
+#define CG4		8
+#define CG5		10
+#define CG6		12
+#define CG7		14
+#define CG8		16
+#define CG9		18
+#define CG10		20
+#define CG11		22
+#define CG12		24
+#define CG13		26
+#define CG14		28
+#define CG15		30
+
+#define BM_CCSR_PLL1_SW_SEL		(0x1 << 2)
+#define BM_CCSR_STEP_SEL		(0x1 << 8)
+
+#define BP_CACRR_ARM_PODF		0
+#define BM_CACRR_ARM_PODF		(0x7 << 0)
+
+#define BP_CBCDR_PERIPH2_CLK2_PODF	0
+#define BM_CBCDR_PERIPH2_CLK2_PODF	(0x7 << 0)
+#define BP_CBCDR_MMDC_CH1_AXI_PODF	3
+#define BM_CBCDR_MMDC_CH1_AXI_PODF	(0x7 << 3)
+#define BP_CBCDR_AXI_SEL		6
+#define BM_CBCDR_AXI_SEL		(0x3 << 6)
+#define BP_CBCDR_IPG_PODF		8
+#define BM_CBCDR_IPG_PODF		(0x3 << 8)
+#define BP_CBCDR_AHB_PODF		10
+#define BM_CBCDR_AHB_PODF		(0x7 << 10)
+#define BP_CBCDR_AXI_PODF		16
+#define BM_CBCDR_AXI_PODF		(0x7 << 16)
+#define BP_CBCDR_MMDC_CH0_AXI_PODF	19
+#define BM_CBCDR_MMDC_CH0_AXI_PODF	(0x7 << 19)
+#define BP_CBCDR_PERIPH_CLK_SEL		25
+#define BM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
+#define BP_CBCDR_PERIPH2_CLK_SEL	26
+#define BM_CBCDR_PERIPH2_CLK_SEL	(0x1 << 26)
+#define BP_CBCDR_PERIPH_CLK2_PODF	27
+#define BM_CBCDR_PERIPH_CLK2_PODF	(0x7 << 27)
+
+#define BP_CBCMR_GPU2D_AXI_SEL		0
+#define BM_CBCMR_GPU2D_AXI_SEL		(0x1 << 0)
+#define BP_CBCMR_GPU3D_AXI_SEL		1
+#define BM_CBCMR_GPU3D_AXI_SEL		(0x1 << 1)
+#define BP_CBCMR_GPU3D_CORE_SEL		4
+#define BM_CBCMR_GPU3D_CORE_SEL		(0x3 << 4)
+#define BP_CBCMR_GPU3D_SHADER_SEL	8
+#define BM_CBCMR_GPU3D_SHADER_SEL	(0x3 << 8)
+#define BP_CBCMR_PCIE_AXI_SEL		10
+#define BM_CBCMR_PCIE_AXI_SEL		(0x1 << 10)
+#define BP_CBCMR_VDO_AXI_SEL		11
+#define BM_CBCMR_VDO_AXI_SEL		(0x1 << 11)
+#define BP_CBCMR_PERIPH_CLK2_SEL	12
+#define BM_CBCMR_PERIPH_CLK2_SEL	(0x3 << 12)
+#define BP_CBCMR_VPU_AXI_SEL		14
+#define BM_CBCMR_VPU_AXI_SEL		(0x3 << 14)
+#define BP_CBCMR_GPU2D_CORE_SEL		16
+#define BM_CBCMR_GPU2D_CORE_SEL		(0x3 << 16)
+#define BP_CBCMR_PRE_PERIPH_CLK_SEL	18
+#define BM_CBCMR_PRE_PERIPH_CLK_SEL	(0x3 << 18)
+#define BP_CBCMR_PERIPH2_CLK2_SEL	20
+#define BM_CBCMR_PERIPH2_CLK2_SEL	(0x1 << 20)
+#define BP_CBCMR_PRE_PERIPH2_CLK_SEL	21
+#define BM_CBCMR_PRE_PERIPH2_CLK_SEL	(0x3 << 21)
+#define BP_CBCMR_GPU2D_CORE_PODF	23
+#define BM_CBCMR_GPU2D_CORE_PODF	(0x7 << 23)
+#define BP_CBCMR_GPU3D_CORE_PODF	26
+#define BM_CBCMR_GPU3D_CORE_PODF	(0x7 << 26)
+#define BP_CBCMR_GPU3D_SHADER_PODF	29
+#define BM_CBCMR_GPU3D_SHADER_PODF	(0x7 << 29)
+
+#define BP_CSCMR1_PERCLK_PODF		0
+#define BM_CSCMR1_PERCLK_PODF		(0x3f << 0)
+#define BP_CSCMR1_SSI1_SEL		10
+#define BM_CSCMR1_SSI1_SEL		(0x3 << 10)
+#define BP_CSCMR1_SSI2_SEL		12
+#define BM_CSCMR1_SSI2_SEL		(0x3 << 12)
+#define BP_CSCMR1_SSI3_SEL		14
+#define BM_CSCMR1_SSI3_SEL		(0x3 << 14)
+#define BP_CSCMR1_USDHC1_SEL		16
+#define BM_CSCMR1_USDHC1_SEL		(0x1 << 16)
+#define BP_CSCMR1_USDHC2_SEL		17
+#define BM_CSCMR1_USDHC2_SEL		(0x1 << 17)
+#define BP_CSCMR1_USDHC3_SEL		18
+#define BM_CSCMR1_USDHC3_SEL		(0x1 << 18)
+#define BP_CSCMR1_USDHC4_SEL		19
+#define BM_CSCMR1_USDHC4_SEL		(0x1 << 19)
+#define BP_CSCMR1_EMI_PODF		20
+#define BM_CSCMR1_EMI_PODF		(0x7 << 20)
+#define BP_CSCMR1_EMI_SLOW_PODF		23
+#define BM_CSCMR1_EMI_SLOW_PODF		(0x7 << 23)
+#define BP_CSCMR1_EMI_SEL		27
+#define BM_CSCMR1_EMI_SEL		(0x3 << 27)
+#define BP_CSCMR1_EMI_SLOW_SEL		29
+#define BM_CSCMR1_EMI_SLOW_SEL		(0x3 << 29)
+
+#define BP_CSCMR2_CAN_PODF		2
+#define BM_CSCMR2_CAN_PODF		(0x3f << 2)
+#define BM_CSCMR2_LDB_DI0_IPU_DIV	(0x1 << 10)
+#define BM_CSCMR2_LDB_DI1_IPU_DIV	(0x1 << 11)
+#define BP_CSCMR2_ESAI_SEL		19
+#define BM_CSCMR2_ESAI_SEL		(0x3 << 19)
+
+#define BP_CSCDR1_UART_PODF		0
+#define BM_CSCDR1_UART_PODF		(0x3f << 0)
+#define BP_CSCDR1_USDHC1_PODF		11
+#define BM_CSCDR1_USDHC1_PODF		(0x7 << 11)
+#define BP_CSCDR1_USDHC2_PODF		16
+#define BM_CSCDR1_USDHC2_PODF		(0x7 << 16)
+#define BP_CSCDR1_USDHC3_PODF		19
+#define BM_CSCDR1_USDHC3_PODF		(0x7 << 19)
+#define BP_CSCDR1_USDHC4_PODF		22
+#define BM_CSCDR1_USDHC4_PODF		(0x7 << 22)
+#define BP_CSCDR1_VPU_AXI_PODF		25
+#define BM_CSCDR1_VPU_AXI_PODF		(0x7 << 25)
+
+#define BP_CS1CDR_SSI1_PODF		0
+#define BM_CS1CDR_SSI1_PODF		(0x3f << 0)
+#define BP_CS1CDR_SSI1_PRED		6
+#define BM_CS1CDR_SSI1_PRED		(0x7 << 6)
+#define BP_CS1CDR_ESAI_PRED		9
+#define BM_CS1CDR_ESAI_PRED		(0x7 << 9)
+#define BP_CS1CDR_SSI3_PODF		16
+#define BM_CS1CDR_SSI3_PODF		(0x3f << 16)
+#define BP_CS1CDR_SSI3_PRED		22
+#define BM_CS1CDR_SSI3_PRED		(0x7 << 22)
+#define BP_CS1CDR_ESAI_PODF		25
+#define BM_CS1CDR_ESAI_PODF		(0x7 << 25)
+
+#define BP_CS2CDR_SSI2_PODF		0
+#define BM_CS2CDR_SSI2_PODF		(0x3f << 0)
+#define BP_CS2CDR_SSI2_PRED		6
+#define BM_CS2CDR_SSI2_PRED		(0x7 << 6)
+#define BP_CS2CDR_LDB_DI0_SEL		9
+#define BM_CS2CDR_LDB_DI0_SEL		(0x7 << 9)
+#define BP_CS2CDR_LDB_DI1_SEL		12
+#define BM_CS2CDR_LDB_DI1_SEL		(0x7 << 12)
+#define BP_CS2CDR_ENFC_SEL		16
+#define BM_CS2CDR_ENFC_SEL		(0x3 << 16)
+#define BP_CS2CDR_ENFC_PRED		18
+#define BM_CS2CDR_ENFC_PRED		(0x7 << 18)
+#define BP_CS2CDR_ENFC_PODF		21
+#define BM_CS2CDR_ENFC_PODF		(0x3f << 21)
+
+#define BP_CDCDR_ASRC_SERIAL_SEL	7
+#define BM_CDCDR_ASRC_SERIAL_SEL	(0x3 << 7)
+#define BP_CDCDR_ASRC_SERIAL_PODF	9
+#define BM_CDCDR_ASRC_SERIAL_PODF	(0x7 << 9)
+#define BP_CDCDR_ASRC_SERIAL_PRED	12
+#define BM_CDCDR_ASRC_SERIAL_PRED	(0x7 << 12)
+#define BP_CDCDR_SPDIF_SEL		20
+#define BM_CDCDR_SPDIF_SEL		(0x3 << 20)
+#define BP_CDCDR_SPDIF_PODF		22
+#define BM_CDCDR_SPDIF_PODF		(0x7 << 22)
+#define BP_CDCDR_SPDIF_PRED		25
+#define BM_CDCDR_SPDIF_PRED		(0x7 << 25)
+#define BP_CDCDR_HSI_TX_PODF		29
+#define BM_CDCDR_HSI_TX_PODF		(0x7 << 29)
+#define BP_CDCDR_HSI_TX_SEL		28
+#define BM_CDCDR_HSI_TX_SEL		(0x1 << 28)
+
+#define BP_CHSCCDR_IPU1_DI0_SEL		0
+#define BM_CHSCCDR_IPU1_DI0_SEL		(0x7 << 0)
+#define BP_CHSCCDR_IPU1_DI0_PRE_PODF	3
+#define BM_CHSCCDR_IPU1_DI0_PRE_PODF	(0x7 << 3)
+#define BP_CHSCCDR_IPU1_DI0_PRE_SEL	6
+#define BM_CHSCCDR_IPU1_DI0_PRE_SEL	(0x7 << 6)
+#define BP_CHSCCDR_IPU1_DI1_SEL		9
+#define BM_CHSCCDR_IPU1_DI1_SEL		(0x7 << 9)
+#define BP_CHSCCDR_IPU1_DI1_PRE_PODF	12
+#define BM_CHSCCDR_IPU1_DI1_PRE_PODF	(0x7 << 12)
+#define BP_CHSCCDR_IPU1_DI1_PRE_SEL	15
+#define BM_CHSCCDR_IPU1_DI1_PRE_SEL	(0x7 << 15)
+
+#define BP_CSCDR2_IPU2_DI0_SEL		0
+#define BM_CSCDR2_IPU2_DI0_SEL		(0x7)
+#define BP_CSCDR2_IPU2_DI0_PRE_PODF	3
+#define BM_CSCDR2_IPU2_DI0_PRE_PODF	(0x7 << 3)
+#define BP_CSCDR2_IPU2_DI0_PRE_SEL	6
+#define BM_CSCDR2_IPU2_DI0_PRE_SEL	(0x7 << 6)
+#define BP_CSCDR2_IPU2_DI1_SEL		9
+#define BM_CSCDR2_IPU2_DI1_SEL		(0x7 << 9)
+#define BP_CSCDR2_IPU2_DI1_PRE_PODF	12
+#define BM_CSCDR2_IPU2_DI1_PRE_PODF	(0x7 << 12)
+#define BP_CSCDR2_IPU2_DI1_PRE_SEL	15
+#define BM_CSCDR2_IPU2_DI1_PRE_SEL	(0x7 << 15)
+#define BP_CSCDR2_ECSPI_CLK_PODF	19
+#define BM_CSCDR2_ECSPI_CLK_PODF	(0x3f << 19)
+
+#define BP_CSCDR3_IPU1_HSP_SEL		9
+#define BM_CSCDR3_IPU1_HSP_SEL		(0x3 << 9)
+#define BP_CSCDR3_IPU1_HSP_PODF		11
+#define BM_CSCDR3_IPU1_HSP_PODF		(0x7 << 11)
+#define BP_CSCDR3_IPU2_HSP_SEL		14
+#define BM_CSCDR3_IPU2_HSP_SEL		(0x3 << 14)
+#define BP_CSCDR3_IPU2_HSP_PODF		16
+#define BM_CSCDR3_IPU2_HSP_PODF		(0x7 << 16)
+
+#define BM_CDHIPR_AXI_PODF_BUSY		(0x1 << 0)
+#define BM_CDHIPR_AHB_PODF_BUSY		(0x1 << 1)
+#define BM_CDHIPR_MMDC_CH1_PODF_BUSY	(0x1 << 2)
+#define BM_CDHIPR_PERIPH2_SEL_BUSY	(0x1 << 3)
+#define BM_CDHIPR_MMDC_CH0_PODF_BUSY	(0x1 << 4)
+#define BM_CDHIPR_PERIPH_SEL_BUSY	(0x1 << 5)
+#define BM_CDHIPR_ARM_PODF_BUSY		(0x1 << 16)
+
+#define BP_CLPCR_LPM			0
+#define BM_CLPCR_LPM			(0x3 << 0)
+#define BM_CLPCR_BYPASS_PMIC_READY	(0x1 << 2)
+#define BM_CLPCR_ARM_CLK_DIS_ON_LPM	(0x1 << 5)
+#define BM_CLPCR_SBYOS			(0x1 << 6)
+#define BM_CLPCR_DIS_REF_OSC		(0x1 << 7)
+#define BM_CLPCR_VSTBY			(0x1 << 8)
+#define BP_CLPCR_STBY_COUNT		9
+#define BM_CLPCR_STBY_COUNT		(0x3 << 9)
+#define BM_CLPCR_COSC_PWRDOWN		(0x1 << 11)
+#define BM_CLPCR_WB_PER_AT_LPM		(0x1 << 16)
+#define BM_CLPCR_WB_CORE_AT_LPM		(0x1 << 17)
+#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS	(0x1 << 19)
+#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS	(0x1 << 21)
+#define BM_CLPCR_MASK_CORE0_WFI		(0x1 << 22)
+#define BM_CLPCR_MASK_CORE1_WFI		(0x1 << 23)
+#define BM_CLPCR_MASK_CORE2_WFI		(0x1 << 24)
+#define BM_CLPCR_MASK_CORE3_WFI		(0x1 << 25)
+#define BM_CLPCR_MASK_SCU_IDLE		(0x1 << 26)
+#define BM_CLPCR_MASK_L2CC_IDLE		(0x1 << 27)
+
+#define FREQ_480M	480000000
+#define FREQ_528M	528000000
+#define FREQ_594M	594000000
+#define FREQ_650M	650000000
+#define FREQ_1300M	1300000000
+
+static struct clk pll1_sys;
+static struct clk pll2_bus;
+static struct clk pll3_usb_otg;
+static struct clk pll4_audio;
+static struct clk pll5_video;
+static struct clk pll6_mlb;
+static struct clk pll7_usb_host;
+static struct clk pll8_enet;
+static struct clk apbh_dma_clk;
+static struct clk arm_clk;
+static struct clk ipg_clk;
+static struct clk ahb_clk;
+static struct clk axi_clk;
+static struct clk mmdc_ch0_axi_clk;
+static struct clk mmdc_ch1_axi_clk;
+static struct clk periph_clk;
+static struct clk periph_pre_clk;
+static struct clk periph_clk2_clk;
+static struct clk periph2_clk;
+static struct clk periph2_pre_clk;
+static struct clk periph2_clk2_clk;
+static struct clk gpu2d_core_clk;
+static struct clk gpu3d_core_clk;
+static struct clk gpu3d_shader_clk;
+static struct clk ipg_perclk;
+static struct clk emi_clk;
+static struct clk emi_slow_clk;
+static struct clk can1_clk;
+static struct clk uart_clk;
+static struct clk usdhc1_clk;
+static struct clk usdhc2_clk;
+static struct clk usdhc3_clk;
+static struct clk usdhc4_clk;
+static struct clk vpu_clk;
+static struct clk hsi_tx_clk;
+static struct clk ipu1_di0_pre_clk;
+static struct clk ipu1_di1_pre_clk;
+static struct clk ipu2_di0_pre_clk;
+static struct clk ipu2_di1_pre_clk;
+static struct clk ipu1_clk;
+static struct clk ipu2_clk;
+static struct clk ssi1_clk;
+static struct clk ssi3_clk;
+static struct clk esai_clk;
+static struct clk ssi2_clk;
+static struct clk spdif_clk;
+static struct clk asrc_serial_clk;
+static struct clk gpu2d_axi_clk;
+static struct clk gpu3d_axi_clk;
+static struct clk pcie_clk;
+static struct clk vdo_axi_clk;
+static struct clk ldb_di0_clk;
+static struct clk ldb_di1_clk;
+static struct clk ipu1_di0_clk;
+static struct clk ipu1_di1_clk;
+static struct clk ipu2_di0_clk;
+static struct clk ipu2_di1_clk;
+static struct clk enfc_clk;
+static struct clk dummy_clk = {};
+
+static unsigned long external_high_reference;
+static unsigned long external_low_reference;
+static unsigned long oscillator_reference;
+
+static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
+{
+	return oscillator_reference;
+}
+
+static unsigned long get_high_reference_clock_rate(struct clk *clk)
+{
+	return external_high_reference;
+}
+
+static unsigned long get_low_reference_clock_rate(struct clk *clk)
+{
+	return external_low_reference;
+}
+
+static struct clk ckil_clk = {
+	.get_rate = get_low_reference_clock_rate,
+};
+
+static struct clk ckih_clk = {
+	.get_rate = get_high_reference_clock_rate,
+};
+
+static struct clk osc_clk = {
+	.get_rate = get_oscillator_reference_clock_rate,
+};
+
+static inline void __iomem *pll_get_reg_addr(struct clk *pll)
+{
+	if (pll == &pll1_sys)
+		return PLL1_SYS;
+	else if (pll == &pll2_bus)
+		return PLL2_BUS;
+	else if (pll == &pll3_usb_otg)
+		return PLL3_USB_OTG;
+	else if (pll == &pll4_audio)
+		return PLL4_AUDIO;
+	else if (pll == &pll5_video)
+		return PLL5_VIDEO;
+	else if (pll == &pll6_mlb)
+		return PLL6_MLB;
+	else if (pll == &pll7_usb_host)
+		return PLL7_USB_HOST;
+	else if (pll == &pll8_enet)
+		return PLL8_ENET;
+	else
+		BUG();
+
+	return NULL;
+}
+
+static int pll_enable(struct clk *clk)
+{
+	int timeout = 0x100000;
+	void __iomem *reg;
+	u32 val;
+
+	reg = pll_get_reg_addr(clk);
+	val = readl_relaxed(reg);
+	val &= ~BM_PLL_BYPASS;
+	val &= ~BM_PLL_POWER_DOWN;
+	/* 480MHz PLLs have the opposite definition for power bit */
+	if (clk == &pll3_usb_otg || clk == &pll7_usb_host)
+		val |= BM_PLL_POWER_DOWN;
+	writel_relaxed(val, reg);
+
+	/* Wait for PLL to lock */
+	while (!(readl_relaxed(reg) & BM_PLL_LOCK) && --timeout)
+		cpu_relax();
+
+	if (unlikely(!timeout))
+		return -EBUSY;
+
+	/* Enable the PLL output now */
+	val = readl_relaxed(reg);
+	val |= BM_PLL_ENABLE;
+	writel_relaxed(val, reg);
+
+	return 0;
+}
+
+static void pll_disable(struct clk *clk)
+{
+	void __iomem *reg;
+	u32 val;
+
+	reg = pll_get_reg_addr(clk);
+	val = readl_relaxed(reg);
+	val &= ~BM_PLL_ENABLE;
+	val |= BM_PLL_BYPASS;
+	val |= BM_PLL_POWER_DOWN;
+	if (clk == &pll3_usb_otg || clk == &pll7_usb_host)
+		val &= ~BM_PLL_POWER_DOWN;
+	writel_relaxed(val, reg);
+}
+
+static unsigned long pll1_sys_get_rate(struct clk *clk)
+{
+	u32 div = (readl_relaxed(PLL1_SYS) & BM_PLL_SYS_DIV_SELECT) >>
+		  BP_PLL_SYS_DIV_SELECT;
+
+	return clk_get_rate(clk->parent) * div / 2;
+}
+
+static int pll1_sys_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 val, div;
+
+	if (rate < FREQ_650M || rate > FREQ_1300M)
+		return -EINVAL;
+
+	div = rate * 2 / clk_get_rate(clk->parent);
+	val = readl_relaxed(PLL1_SYS);
+	val &= ~BM_PLL_SYS_DIV_SELECT;
+	val |= div << BP_PLL_SYS_DIV_SELECT;
+	writel_relaxed(val, PLL1_SYS);
+
+	return 0;
+}
+
+static unsigned long pll8_enet_get_rate(struct clk *clk)
+{
+	u32 div = (readl_relaxed(PLL8_ENET) & BM_PLL_ENET_DIV_SELECT) >>
+		  BP_PLL_ENET_DIV_SELECT;
+
+	switch (div) {
+	case 0:
+		return 25000000;
+	case 1:
+		return 50000000;
+	case 2:
+		return 100000000;
+	case 3:
+		return 125000000;
+	}
+
+	return 0;
+}
+
+static int pll8_enet_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 val, div;
+
+	switch (rate) {
+	case 25000000:
+		div = 0;
+		break;
+	case 50000000:
+		div = 1;
+		break;
+	case 100000000:
+		div = 2;
+		break;
+	case 125000000:
+		div = 3;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	val = readl_relaxed(PLL8_ENET);
+	val &= ~BM_PLL_ENET_DIV_SELECT;
+	val |= div << BP_PLL_ENET_DIV_SELECT;
+	writel_relaxed(val, PLL8_ENET);
+
+	return 0;
+}
+
+static unsigned long pll_av_get_rate(struct clk *clk)
+{
+	void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
+	unsigned long parent_rate = clk_get_rate(clk->parent);
+	u32 mfn = readl_relaxed(reg + PLL_NUM_OFFSET);
+	u32 mfd = readl_relaxed(reg + PLL_DENOM_OFFSET);
+	u32 div = (readl_relaxed(reg) & BM_PLL_AV_DIV_SELECT) >>
+		  BP_PLL_AV_DIV_SELECT;
+
+	return (parent_rate * div) + ((parent_rate / mfd) * mfn);
+}
+
+static int pll_av_set_rate(struct clk *clk, unsigned long rate)
+{
+	void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
+	unsigned int parent_rate = clk_get_rate(clk->parent);
+	u32 val, div;
+	u32 mfn, mfd = 1000000;
+	s64 temp64;
+
+	if (rate < FREQ_650M || rate > FREQ_1300M)
+		return -EINVAL;
+
+	div = rate / parent_rate;
+	temp64 = (u64) (rate - div * parent_rate);
+	temp64 *= mfd;
+	do_div(temp64, parent_rate);
+	mfn = temp64;
+
+	val = readl_relaxed(reg);
+	val &= ~BM_PLL_AV_DIV_SELECT;
+	val |= div << BP_PLL_AV_DIV_SELECT;
+	writel_relaxed(val, reg);
+	writel_relaxed(mfn, reg + PLL_NUM_OFFSET);
+	writel_relaxed(mfd, reg + PLL_DENOM_OFFSET);
+
+	return 0;
+}
+
+static void __iomem *pll_get_div_reg_bit(struct clk *clk, u32 *bp, u32 *bm)
+{
+	void __iomem *reg;
+
+	if (clk == &pll2_bus) {
+		reg = PLL2_BUS;
+		*bp = BP_PLL_BUS_DIV_SELECT;
+		*bm = BM_PLL_BUS_DIV_SELECT;
+	} else if (clk == &pll3_usb_otg) {
+		reg = PLL3_USB_OTG;
+		*bp = BP_PLL_USB_DIV_SELECT;
+		*bm = BM_PLL_USB_DIV_SELECT;
+	} else if (clk == &pll7_usb_host) {
+		reg = PLL7_USB_HOST;
+		*bp = BP_PLL_USB_DIV_SELECT;
+		*bm = BM_PLL_USB_DIV_SELECT;
+	} else {
+		BUG();
+	}
+
+	return reg;
+}
+
+static unsigned long pll_get_rate(struct clk *clk)
+{
+	void __iomem *reg;
+	u32 div, bp, bm;
+
+	reg = pll_get_div_reg_bit(clk, &bp, &bm);
+	div = (readl_relaxed(reg) & bm) >> bp;
+
+	return (div == 1) ? clk_get_rate(clk->parent) * 22 :
+			    clk_get_rate(clk->parent) * 20;
+}
+
+static int pll_set_rate(struct clk *clk, unsigned long rate)
+{
+	void __iomem *reg;
+	u32 val, div, bp, bm;
+
+	if (rate == FREQ_528M)
+		div = 1;
+	else if (rate == FREQ_480M)
+		div = 0;
+	else
+		return -EINVAL;
+
+	reg = pll_get_div_reg_bit(clk, &bp, &bm);
+	val = readl_relaxed(reg);
+	val &= ~bm;
+	val |= div << bp;
+	writel_relaxed(val, reg);
+
+	return 0;
+}
+
+#define pll2_bus_get_rate	pll_get_rate
+#define pll2_bus_set_rate	pll_set_rate
+#define pll3_usb_otg_get_rate	pll_get_rate
+#define pll3_usb_otg_set_rate	pll_set_rate
+#define pll7_usb_host_get_rate	pll_get_rate
+#define pll7_usb_host_set_rate	pll_set_rate
+#define pll4_audio_get_rate	pll_av_get_rate
+#define pll4_audio_set_rate	pll_av_set_rate
+#define pll5_video_get_rate	pll_av_get_rate
+#define pll5_video_set_rate	pll_av_set_rate
+#define pll6_mlb_get_rate	NULL
+#define pll6_mlb_set_rate	NULL
+
+#define DEF_PLL(name)					\
+	static struct clk name = {			\
+		.enable		= pll_enable,		\
+		.disable	= pll_disable,		\
+		.get_rate	= name##_get_rate,	\
+		.set_rate	= name##_set_rate,	\
+		.parent		= &osc_clk,		\
+	}
+
+DEF_PLL(pll1_sys);
+DEF_PLL(pll2_bus);
+DEF_PLL(pll3_usb_otg);
+DEF_PLL(pll4_audio);
+DEF_PLL(pll5_video);
+DEF_PLL(pll6_mlb);
+DEF_PLL(pll7_usb_host);
+DEF_PLL(pll8_enet);
+
+static unsigned long pfd_get_rate(struct clk *clk)
+{
+	u64 tmp = (u64) clk_get_rate(clk->parent) * 18;
+	u32 frac, bp_frac;
+
+	if (apbh_dma_clk.usecount == 0)
+		apbh_dma_clk.enable(&apbh_dma_clk);
+
+	bp_frac = clk->enable_shift - 7;
+	frac = readl_relaxed(clk->enable_reg) >> bp_frac & PFD_FRAC_MASK;
+	do_div(tmp, frac);
+
+	return tmp;
+}
+
+static int pfd_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 val, frac, bp_frac;
+	u64 tmp = (u64) clk_get_rate(clk->parent) * 18;
+
+	if (apbh_dma_clk.usecount == 0)
+		apbh_dma_clk.enable(&apbh_dma_clk);
+
+	/*
+	 * Round up the divider so that we don't set a rate
+	 * higher than what is requested
+	 */
+	tmp += rate / 2;
+	do_div(tmp, rate);
+	frac = tmp;
+	frac = (frac < 12) ? 12 : frac;
+	frac = (frac > 35) ? 35 : frac;
+
+	/*
+	 * The frac field always starts from 7 bits lower
+	 * position of enable bit
+	 */
+	bp_frac = clk->enable_shift - 7;
+	val = readl_relaxed(clk->enable_reg);
+	val &= ~(PFD_FRAC_MASK << bp_frac);
+	val |= frac << bp_frac;
+	writel_relaxed(val, clk->enable_reg);
+
+	tmp = (u64) clk_get_rate(clk->parent) * 18;
+	do_div(tmp, frac);
+
+	if (apbh_dma_clk.usecount == 0)
+		apbh_dma_clk.disable(&apbh_dma_clk);
+
+	return 0;
+}
+
+static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
+{
+	u32 frac;
+	u64 tmp;
+
+	tmp = (u64) clk_get_rate(clk->parent) * 18;
+	tmp += rate / 2;
+	do_div(tmp, rate);
+	frac = tmp;
+	frac = (frac < 12) ? 12 : frac;
+	frac = (frac > 35) ? 35 : frac;
+	tmp = (u64) clk_get_rate(clk->parent) * 18;
+	do_div(tmp, frac);
+
+	return tmp;
+}
+
+static int pfd_enable(struct clk *clk)
+{
+	u32 val;
+
+	if (apbh_dma_clk.usecount == 0)
+		apbh_dma_clk.enable(&apbh_dma_clk);
+
+	val = readl_relaxed(clk->enable_reg);
+	val &= ~(1 << clk->enable_shift);
+	writel_relaxed(val, clk->enable_reg);
+
+	if (apbh_dma_clk.usecount == 0)
+		apbh_dma_clk.disable(&apbh_dma_clk);
+
+	return 0;
+}
+
+static void pfd_disable(struct clk *clk)
+{
+	u32 val;
+
+	if (apbh_dma_clk.usecount == 0)
+		apbh_dma_clk.enable(&apbh_dma_clk);
+
+	val = readl_relaxed(clk->enable_reg);
+	val |= 1 << clk->enable_shift;
+	writel_relaxed(val, clk->enable_reg);
+
+	if (apbh_dma_clk.usecount == 0)
+		apbh_dma_clk.disable(&apbh_dma_clk);
+}
+
+#define DEF_PFD(name, er, es, p)			\
+	static struct clk name = {			\
+		.enable_reg	= er,			\
+		.enable_shift	= es,			\
+		.enable		= pfd_enable,		\
+		.disable	= pfd_disable,		\
+		.get_rate	= pfd_get_rate,		\
+		.set_rate	= pfd_set_rate,		\
+		.round_rate	= pfd_round_rate,	\
+		.parent		= p,			\
+	}
+
+DEF_PFD(pll2_pfd_352m, PFD_528, PFD0, &pll2_bus);
+DEF_PFD(pll2_pfd_594m, PFD_528, PFD1, &pll2_bus);
+DEF_PFD(pll2_pfd_400m, PFD_528, PFD2, &pll2_bus);
+DEF_PFD(pll3_pfd_720m, PFD_480, PFD0, &pll3_usb_otg);
+DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg);
+DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg);
+DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg);
+
+static unsigned long pll2_200m_get_rate(struct clk *clk)
+{
+	return clk_get_rate(clk->parent) / 2;
+}
+
+static struct clk pll2_200m = {
+	.parent = &pll2_pfd_400m,
+	.get_rate = pll2_200m_get_rate,
+};
+
+static unsigned long pll3_120m_get_rate(struct clk *clk)
+{
+	return clk_get_rate(clk->parent) / 4;
+}
+
+static struct clk pll3_120m = {
+	.parent = &pll3_usb_otg,
+	.get_rate = pll3_120m_get_rate,
+};
+
+static unsigned long pll3_80m_get_rate(struct clk *clk)
+{
+	return clk_get_rate(clk->parent) / 6;
+}
+
+static struct clk pll3_80m = {
+	.parent = &pll3_usb_otg,
+	.get_rate = pll3_80m_get_rate,
+};
+
+static unsigned long pll3_60m_get_rate(struct clk *clk)
+{
+	return clk_get_rate(clk->parent) / 8;
+}
+
+static struct clk pll3_60m = {
+	.parent = &pll3_usb_otg,
+	.get_rate = pll3_60m_get_rate,
+};
+
+static int pll1_sw_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 val = readl_relaxed(CCSR);
+
+	if (parent == &pll1_sys) {
+		val &= ~BM_CCSR_PLL1_SW_SEL;
+		val &= ~BM_CCSR_STEP_SEL;
+	} else if (parent == &osc_clk) {
+		val |= BM_CCSR_PLL1_SW_SEL;
+		val &= ~BM_CCSR_STEP_SEL;
+	} else if (parent == &pll2_pfd_400m) {
+		val |= BM_CCSR_PLL1_SW_SEL;
+		val |= BM_CCSR_STEP_SEL;
+	} else {
+		return -EINVAL;
+	}
+
+	writel_relaxed(val, CCSR);
+
+	return 0;
+}
+
+static struct clk pll1_sw_clk = {
+	.parent = &pll1_sys,
+	.set_parent = pll1_sw_clk_set_parent,
+};
+
+static void calc_pred_podf_dividers(u32 div, u32 *pred, u32 *podf)
+{
+	u32 min_pred, temp_pred, old_err, err;
+
+	if (div >= 512) {
+		*pred = 8;
+		*podf = 64;
+	} else if (div >= 8) {
+		min_pred = (div - 1) / 64 + 1;
+		old_err = 8;
+		for (temp_pred = 8; temp_pred >= min_pred; temp_pred--) {
+			err = div % temp_pred;
+			if (err == 0) {
+				*pred = temp_pred;
+				break;
+			}
+			err = temp_pred - err;
+			if (err < old_err) {
+				old_err = err;
+				*pred = temp_pred;
+			}
+		}
+		*podf = (div + *pred - 1) / *pred;
+	} else if (div < 8) {
+		*pred = div;
+		*podf = 1;
+	}
+}
+
+static int _clk_enable(struct clk *clk)
+{
+	u32 reg;
+	reg = readl_relaxed(clk->enable_reg);
+	reg |= 0x3 << clk->enable_shift;
+	writel_relaxed(reg, clk->enable_reg);
+
+	return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+	u32 reg;
+	reg = readl_relaxed(clk->enable_reg);
+	reg &= ~(0x3 << clk->enable_shift);
+	writel_relaxed(reg, clk->enable_reg);
+}
+
+struct divider {
+	struct clk *clk;
+	void __iomem *reg;
+	u32 bp_pred;
+	u32 bm_pred;
+	u32 bp_podf;
+	u32 bm_podf;
+};
+
+#define DEF_CLK_DIV1(d, c, r, b)				\
+	static struct divider d = {				\
+		.clk = c,					\
+		.reg = r,					\
+		.bp_podf = BP_##r##_##b##_PODF,			\
+		.bm_podf = BM_##r##_##b##_PODF,			\
+	}
+
+DEF_CLK_DIV1(arm_div,		&arm_clk,		CACRR,	ARM);
+DEF_CLK_DIV1(ipg_div,		&ipg_clk,		CBCDR,	IPG);
+DEF_CLK_DIV1(ahb_div,		&ahb_clk,		CBCDR,	AHB);
+DEF_CLK_DIV1(axi_div,		&axi_clk,		CBCDR,	AXI);
+DEF_CLK_DIV1(mmdc_ch0_axi_div,	&mmdc_ch0_axi_clk,	CBCDR,	MMDC_CH0_AXI);
+DEF_CLK_DIV1(mmdc_ch1_axi_div,	&mmdc_ch1_axi_clk,	CBCDR,	MMDC_CH1_AXI);
+DEF_CLK_DIV1(periph_clk2_div,	&periph_clk2_clk,	CBCDR,	PERIPH_CLK2);
+DEF_CLK_DIV1(periph2_clk2_div,	&periph2_clk2_clk,	CBCDR,	PERIPH2_CLK2);
+DEF_CLK_DIV1(gpu2d_core_div,	&gpu2d_core_clk,	CBCMR,	GPU2D_CORE);
+DEF_CLK_DIV1(gpu3d_core_div,	&gpu3d_core_clk,	CBCMR,	GPU3D_CORE);
+DEF_CLK_DIV1(gpu3d_shader_div,	&gpu3d_shader_clk,	CBCMR,	GPU3D_SHADER);
+DEF_CLK_DIV1(ipg_perclk_div,	&ipg_perclk,		CSCMR1,	PERCLK);
+DEF_CLK_DIV1(emi_div,		&emi_clk,		CSCMR1,	EMI);
+DEF_CLK_DIV1(emi_slow_div,	&emi_slow_clk,		CSCMR1,	EMI_SLOW);
+DEF_CLK_DIV1(can_div,		&can1_clk,		CSCMR2,	CAN);
+DEF_CLK_DIV1(uart_div,		&uart_clk,		CSCDR1,	UART);
+DEF_CLK_DIV1(usdhc1_div,	&usdhc1_clk,		CSCDR1,	USDHC1);
+DEF_CLK_DIV1(usdhc2_div,	&usdhc2_clk,		CSCDR1,	USDHC2);
+DEF_CLK_DIV1(usdhc3_div,	&usdhc3_clk,		CSCDR1,	USDHC3);
+DEF_CLK_DIV1(usdhc4_div,	&usdhc4_clk,		CSCDR1,	USDHC4);
+DEF_CLK_DIV1(vpu_div,		&vpu_clk,		CSCDR1,	VPU_AXI);
+DEF_CLK_DIV1(hsi_tx_div,	&hsi_tx_clk,		CDCDR,	HSI_TX);
+DEF_CLK_DIV1(ipu1_di0_pre_div,	&ipu1_di0_pre_clk,	CHSCCDR, IPU1_DI0_PRE);
+DEF_CLK_DIV1(ipu1_di1_pre_div,	&ipu1_di1_pre_clk,	CHSCCDR, IPU1_DI1_PRE);
+DEF_CLK_DIV1(ipu2_di0_pre_div,	&ipu2_di0_pre_clk,	CSCDR2,	IPU2_DI0_PRE);
+DEF_CLK_DIV1(ipu2_di1_pre_div,	&ipu2_di1_pre_clk,	CSCDR2,	IPU2_DI1_PRE);
+DEF_CLK_DIV1(ipu1_div,		&ipu1_clk,		CSCDR3,	IPU1_HSP);
+DEF_CLK_DIV1(ipu2_div,		&ipu2_clk,		CSCDR3,	IPU2_HSP);
+
+#define DEF_CLK_DIV2(d, c, r, b)				\
+	static struct divider d = {				\
+		.clk = c,					\
+		.reg = r,					\
+		.bp_pred = BP_##r##_##b##_PRED,			\
+		.bm_pred = BM_##r##_##b##_PRED,			\
+		.bp_podf = BP_##r##_##b##_PODF,			\
+		.bm_podf = BM_##r##_##b##_PODF,			\
+	}
+
+DEF_CLK_DIV2(ssi1_div,		&ssi1_clk,		CS1CDR,	SSI1);
+DEF_CLK_DIV2(ssi3_div,		&ssi3_clk,		CS1CDR,	SSI3);
+DEF_CLK_DIV2(esai_div,		&esai_clk,		CS1CDR,	ESAI);
+DEF_CLK_DIV2(ssi2_div,		&ssi2_clk,		CS2CDR,	SSI2);
+DEF_CLK_DIV2(enfc_div,		&enfc_clk,		CS2CDR,	ENFC);
+DEF_CLK_DIV2(spdif_div,		&spdif_clk,		CDCDR,	SPDIF);
+DEF_CLK_DIV2(asrc_serial_div,	&asrc_serial_clk,	CDCDR,	ASRC_SERIAL);
+
+static struct divider *dividers[] = {
+	&arm_div,
+	&ipg_div,
+	&ahb_div,
+	&axi_div,
+	&mmdc_ch0_axi_div,
+	&mmdc_ch1_axi_div,
+	&periph_clk2_div,
+	&periph2_clk2_div,
+	&gpu2d_core_div,
+	&gpu3d_core_div,
+	&gpu3d_shader_div,
+	&ipg_perclk_div,
+	&emi_div,
+	&emi_slow_div,
+	&can_div,
+	&uart_div,
+	&usdhc1_div,
+	&usdhc2_div,
+	&usdhc3_div,
+	&usdhc4_div,
+	&vpu_div,
+	&hsi_tx_div,
+	&ipu1_di0_pre_div,
+	&ipu1_di1_pre_div,
+	&ipu2_di0_pre_div,
+	&ipu2_di1_pre_div,
+	&ipu1_div,
+	&ipu2_div,
+	&ssi1_div,
+	&ssi3_div,
+	&esai_div,
+	&ssi2_div,
+	&enfc_div,
+	&spdif_div,
+	&asrc_serial_div,
+};
+
+static unsigned long ldb_di_clk_get_rate(struct clk *clk)
+{
+	u32 val = readl_relaxed(CSCMR2);
+
+	val &= (clk == &ldb_di0_clk) ? BM_CSCMR2_LDB_DI0_IPU_DIV :
+				       BM_CSCMR2_LDB_DI1_IPU_DIV;
+	if (val)
+		return clk_get_rate(clk->parent) / 7;
+	else
+		return clk_get_rate(clk->parent) * 2 / 7;
+}
+
+static int ldb_di_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long parent_rate = clk_get_rate(clk->parent);
+	u32 val = readl_relaxed(CSCMR2);
+
+	if (rate * 7 <= parent_rate + parent_rate / 20)
+		val |= BM_CSCMR2_LDB_DI0_IPU_DIV;
+	else
+		val &= ~BM_CSCMR2_LDB_DI0_IPU_DIV;
+
+	writel_relaxed(val, CSCMR2);
+
+	return 0;
+}
+
+static unsigned long ldb_di_clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long parent_rate = clk_get_rate(clk->parent);
+
+	if (rate * 7 <= parent_rate + parent_rate / 20)
+		return parent_rate / 7;
+	else
+		return 2 * parent_rate / 7;
+}
+
+static unsigned long _clk_get_rate(struct clk *clk)
+{
+	struct divider *d;
+	u32 val, pred, podf;
+	int i, num;
+
+	if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
+		return ldb_di_clk_get_rate(clk);
+
+	num = ARRAY_SIZE(dividers);
+	for (i = 0; i < num; i++)
+		if (dividers[i]->clk == clk) {
+			d = dividers[i];
+			break;
+		}
+	if (i == num)
+		return clk_get_rate(clk->parent);
+
+	val = readl_relaxed(d->reg);
+	pred = ((val & d->bm_pred) >> d->bp_pred) + 1;
+	podf = ((val & d->bm_podf) >> d->bp_podf) + 1;
+
+	return clk_get_rate(clk->parent) / (pred * podf);
+}
+
+static int clk_busy_wait(struct clk *clk)
+{
+	int timeout = 0x100000;
+	u32 bm;
+
+	if (clk == &axi_clk)
+		bm = BM_CDHIPR_AXI_PODF_BUSY;
+	else if (clk == &ahb_clk)
+		bm = BM_CDHIPR_AHB_PODF_BUSY;
+	else if (clk == &mmdc_ch0_axi_clk)
+		bm = BM_CDHIPR_MMDC_CH0_PODF_BUSY;
+	else if (clk == &periph_clk)
+		bm = BM_CDHIPR_PERIPH_SEL_BUSY;
+	else if (clk == &arm_clk)
+		bm = BM_CDHIPR_ARM_PODF_BUSY;
+	else
+		return -EINVAL;
+
+	while ((readl_relaxed(CDHIPR) & bm) && --timeout)
+		cpu_relax();
+
+	if (unlikely(!timeout))
+		return -EBUSY;
+
+	return 0;
+}
+
+static int _clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long parent_rate = clk_get_rate(clk->parent);
+	struct divider *d;
+	u32 val, div, max_div, pred = 0, podf;
+	int i, num;
+
+	if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
+		return ldb_di_clk_set_rate(clk, rate);
+
+	num = ARRAY_SIZE(dividers);
+	for (i = 0; i < num; i++)
+		if (dividers[i]->clk == clk) {
+			d = dividers[i];
+			break;
+		}
+	if (i == num)
+		return -EINVAL;
+
+	max_div = ((d->bm_pred >> d->bp_pred) + 1) *
+		  ((d->bm_pred >> d->bp_pred) + 1);
+
+	div = parent_rate / rate;
+	if (div == 0)
+		div++;
+
+	if ((parent_rate / div != rate) || div > max_div)
+		return -EINVAL;
+
+	if (d->bm_pred) {
+		calc_pred_podf_dividers(div, &pred, &podf);
+	} else {
+		pred = 1;
+		podf = div;
+	}
+
+	val = readl_relaxed(d->reg);
+	val &= ~(d->bm_pred | d->bm_podf);
+	val |= (pred - 1) << d->bp_pred | (podf - 1) << d->bp_podf;
+	writel_relaxed(val, d->reg);
+
+	if (clk == &axi_clk || clk == &ahb_clk ||
+	    clk == &mmdc_ch0_axi_clk || clk == &arm_clk)
+		return clk_busy_wait(clk);
+
+	return 0;
+}
+
+static unsigned long _clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long parent_rate = clk_get_rate(clk->parent);
+	u32 div = parent_rate / rate;
+	u32 div_max, pred = 0, podf;
+	struct divider *d;
+	int i, num;
+
+	if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
+		return ldb_di_clk_round_rate(clk, rate);
+
+	num = ARRAY_SIZE(dividers);
+	for (i = 0; i < num; i++)
+		if (dividers[i]->clk == clk) {
+			d = dividers[i];
+			break;
+		}
+	if (i == num)
+		return -EINVAL;
+
+	if (div == 0 || parent_rate % rate)
+		div++;
+
+	if (d->bm_pred) {
+		calc_pred_podf_dividers(div, &pred, &podf);
+		div = pred * podf;
+	} else {
+		div_max = (d->bm_podf >> d->bp_podf) + 1;
+		if (div > div_max)
+			div = div_max;
+	}
+
+	return parent_rate / div;
+}
+
+struct multiplexer {
+	struct clk *clk;
+	void __iomem *reg;
+	u32 bp;
+	u32 bm;
+	int pnum;
+	struct clk *parents[];
+};
+
+static struct multiplexer axi_mux = {
+	.clk = &axi_clk,
+	.reg = CBCDR,
+	.bp = BP_CBCDR_AXI_SEL,
+	.bm = BM_CBCDR_AXI_SEL,
+	.parents = {
+		&periph_clk,
+		&pll2_pfd_400m,
+		&pll3_pfd_540m,
+		NULL
+	},
+};
+
+static struct multiplexer periph_mux = {
+	.clk = &periph_clk,
+	.reg = CBCDR,
+	.bp = BP_CBCDR_PERIPH_CLK_SEL,
+	.bm = BM_CBCDR_PERIPH_CLK_SEL,
+	.parents = {
+		&periph_pre_clk,
+		&periph_clk2_clk,
+		NULL
+	},
+};
+
+static struct multiplexer periph_pre_mux = {
+	.clk = &periph_pre_clk,
+	.reg = CBCMR,
+	.bp = BP_CBCMR_PRE_PERIPH_CLK_SEL,
+	.bm = BM_CBCMR_PRE_PERIPH_CLK_SEL,
+	.parents = {
+		&pll2_bus,
+		&pll2_pfd_400m,
+		&pll2_pfd_352m,
+		&pll2_200m,
+		NULL
+	},
+};
+
+static struct multiplexer periph_clk2_mux = {
+	.clk = &periph_clk2_clk,
+	.reg = CBCMR,
+	.bp = BP_CBCMR_PERIPH_CLK2_SEL,
+	.bm = BM_CBCMR_PERIPH_CLK2_SEL,
+	.parents = {
+		&pll3_usb_otg,
+		&osc_clk,
+		NULL
+	},
+};
+
+static struct multiplexer periph2_mux = {
+	.clk = &periph2_clk,
+	.reg = CBCDR,
+	.bp = BP_CBCDR_PERIPH2_CLK_SEL,
+	.bm = BM_CBCDR_PERIPH2_CLK_SEL,
+	.parents = {
+		&periph2_pre_clk,
+		&periph2_clk2_clk,
+		NULL
+	},
+};
+
+static struct multiplexer periph2_pre_mux = {
+	.clk = &periph2_pre_clk,
+	.reg = CBCMR,
+	.bp = BP_CBCMR_PRE_PERIPH2_CLK_SEL,
+	.bm = BM_CBCMR_PRE_PERIPH2_CLK_SEL,
+	.parents = {
+		&pll2_bus,
+		&pll2_pfd_400m,
+		&pll2_pfd_352m,
+		&pll2_200m,
+		NULL
+	},
+};
+
+static struct multiplexer periph2_clk2_mux = {
+	.clk = &periph2_clk2_clk,
+	.reg = CBCMR,
+	.bp = BP_CBCMR_PERIPH2_CLK2_SEL,
+	.bm = BM_CBCMR_PERIPH2_CLK2_SEL,
+	.parents = {
+		&pll3_usb_otg,
+		&osc_clk,
+		NULL
+	},
+};
+
+static struct multiplexer gpu2d_axi_mux = {
+	.clk = &gpu2d_axi_clk,
+	.reg = CBCMR,
+	.bp = BP_CBCMR_GPU2D_AXI_SEL,
+	.bm = BM_CBCMR_GPU2D_AXI_SEL,
+	.parents = {
+		&axi_clk,
+		&ahb_clk,
+		NULL
+	},
+};
+
+static struct multiplexer gpu3d_axi_mux = {
+	.clk = &gpu3d_axi_clk,
+	.reg = CBCMR,
+	.bp = BP_CBCMR_GPU3D_AXI_SEL,
+	.bm = BM_CBCMR_GPU3D_AXI_SEL,
+	.parents = {
+		&axi_clk,
+		&ahb_clk,
+		NULL
+	},
+};
+
+static struct multiplexer gpu3d_core_mux = {
+	.clk = &gpu3d_core_clk,
+	.reg = CBCMR,
+	.bp = BP_CBCMR_GPU3D_CORE_SEL,
+	.bm = BM_CBCMR_GPU3D_CORE_SEL,
+	.parents = {
+		&mmdc_ch0_axi_clk,
+		&pll3_usb_otg,
+		&pll2_pfd_594m,
+		&pll2_pfd_400m,
+		NULL
+	},
+};
+
+static struct multiplexer gpu3d_shader_mux = {
+	.clk = &gpu3d_shader_clk,
+	.reg = CBCMR,
+	.bp = BP_CBCMR_GPU3D_SHADER_SEL,
+	.bm = BM_CBCMR_GPU3D_SHADER_SEL,
+	.parents = {
+		&mmdc_ch0_axi_clk,
+		&pll3_usb_otg,
+		&pll2_pfd_594m,
+		&pll3_pfd_720m,
+		NULL
+	},
+};
+
+static struct multiplexer pcie_axi_mux = {
+	.clk = &pcie_clk,
+	.reg = CBCMR,
+	.bp = BP_CBCMR_PCIE_AXI_SEL,
+	.bm = BM_CBCMR_PCIE_AXI_SEL,
+	.parents = {
+		&axi_clk,
+		&ahb_clk,
+		NULL
+	},
+};
+
+static struct multiplexer vdo_axi_mux = {
+	.clk = &vdo_axi_clk,
+	.reg = CBCMR,
+	.bp = BP_CBCMR_VDO_AXI_SEL,
+	.bm = BM_CBCMR_VDO_AXI_SEL,
+	.parents = {
+		&axi_clk,
+		&ahb_clk,
+		NULL
+	},
+};
+
+static struct multiplexer vpu_axi_mux = {
+	.clk = &vpu_clk,
+	.reg = CBCMR,
+	.bp = BP_CBCMR_VPU_AXI_SEL,
+	.bm = BM_CBCMR_VPU_AXI_SEL,
+	.parents = {
+		&axi_clk,
+		&pll2_pfd_400m,
+		&pll2_pfd_352m,
+		NULL
+	},
+};
+
+static struct multiplexer gpu2d_core_mux = {
+	.clk = &gpu2d_core_clk,
+	.reg = CBCMR,
+	.bp = BP_CBCMR_GPU2D_CORE_SEL,
+	.bm = BM_CBCMR_GPU2D_CORE_SEL,
+	.parents = {
+		&axi_clk,
+		&pll3_usb_otg,
+		&pll2_pfd_352m,
+		&pll2_pfd_400m,
+		NULL
+	},
+};
+
+#define DEF_SSI_MUX(id)							\
+	static struct multiplexer ssi##id##_mux = {			\
+		.clk = &ssi##id##_clk,					\
+		.reg = CSCMR1,						\
+		.bp = BP_CSCMR1_SSI##id##_SEL,				\
+		.bm = BM_CSCMR1_SSI##id##_SEL,				\
+		.parents = {						\
+			&pll3_pfd_508m,					\
+			&pll3_pfd_454m,					\
+			&pll4_audio,					\
+			NULL						\
+		},							\
+	}
+
+DEF_SSI_MUX(1);
+DEF_SSI_MUX(2);
+DEF_SSI_MUX(3);
+
+#define DEF_USDHC_MUX(id)						\
+	static struct multiplexer usdhc##id##_mux = {			\
+		.clk = &usdhc##id##_clk,				\
+		.reg = CSCMR1,						\
+		.bp = BP_CSCMR1_USDHC##id##_SEL,			\
+		.bm = BM_CSCMR1_USDHC##id##_SEL,			\
+		.parents = {						\
+			&pll2_pfd_400m,					\
+			&pll2_pfd_352m,					\
+			NULL						\
+		},							\
+	}
+
+DEF_USDHC_MUX(1);
+DEF_USDHC_MUX(2);
+DEF_USDHC_MUX(3);
+DEF_USDHC_MUX(4);
+
+static struct multiplexer emi_mux = {
+	.clk = &emi_clk,
+	.reg = CSCMR1,
+	.bp = BP_CSCMR1_EMI_SEL,
+	.bm = BM_CSCMR1_EMI_SEL,
+	.parents = {
+		&axi_clk,
+		&pll3_usb_otg,
+		&pll2_pfd_400m,
+		&pll2_pfd_352m,
+		NULL
+	},
+};
+
+static struct multiplexer emi_slow_mux = {
+	.clk = &emi_slow_clk,
+	.reg = CSCMR1,
+	.bp = BP_CSCMR1_EMI_SLOW_SEL,
+	.bm = BM_CSCMR1_EMI_SLOW_SEL,
+	.parents = {
+		&axi_clk,
+		&pll3_usb_otg,
+		&pll2_pfd_400m,
+		&pll2_pfd_352m,
+		NULL
+	},
+};
+
+static struct multiplexer esai_mux = {
+	.clk = &esai_clk,
+	.reg = CSCMR2,
+	.bp = BP_CSCMR2_ESAI_SEL,
+	.bm = BM_CSCMR2_ESAI_SEL,
+	.parents = {
+		&pll4_audio,
+		&pll3_pfd_508m,
+		&pll3_pfd_454m,
+		&pll3_usb_otg,
+		NULL
+	},
+};
+
+#define DEF_LDB_DI_MUX(id)						\
+	static struct multiplexer ldb_di##id##_mux = {			\
+		.clk = &ldb_di##id##_clk,				\
+		.reg = CS2CDR,						\
+		.bp = BP_CS2CDR_LDB_DI##id##_SEL,			\
+		.bm = BM_CS2CDR_LDB_DI##id##_SEL,			\
+		.parents = {						\
+			&pll5_video,					\
+			&pll2_pfd_352m,					\
+			&pll2_pfd_400m,					\
+			&pll3_pfd_540m,					\
+			&pll3_usb_otg,					\
+			NULL						\
+		},							\
+	}
+
+DEF_LDB_DI_MUX(0);
+DEF_LDB_DI_MUX(1);
+
+static struct multiplexer enfc_mux = {
+	.clk = &enfc_clk,
+	.reg = CS2CDR,
+	.bp = BP_CS2CDR_ENFC_SEL,
+	.bm = BM_CS2CDR_ENFC_SEL,
+	.parents = {
+		&pll2_pfd_352m,
+		&pll2_bus,
+		&pll3_usb_otg,
+		&pll2_pfd_400m,
+		NULL
+	},
+};
+
+static struct multiplexer spdif_mux = {
+	.clk = &spdif_clk,
+	.reg = CDCDR,
+	.bp = BP_CDCDR_SPDIF_SEL,
+	.bm = BM_CDCDR_SPDIF_SEL,
+	.parents = {
+		&pll4_audio,
+		&pll3_pfd_508m,
+		&pll3_pfd_454m,
+		&pll3_usb_otg,
+		NULL
+	},
+};
+
+static struct multiplexer asrc_serial_mux = {
+	.clk = &asrc_serial_clk,
+	.reg = CDCDR,
+	.bp = BP_CDCDR_ASRC_SERIAL_SEL,
+	.bm = BM_CDCDR_ASRC_SERIAL_SEL,
+	.parents = {
+		&pll4_audio,
+		&pll3_pfd_508m,
+		&pll3_pfd_454m,
+		&pll3_usb_otg,
+		NULL
+	},
+};
+
+static struct multiplexer hsi_tx_mux = {
+	.clk = &hsi_tx_clk,
+	.reg = CDCDR,
+	.bp = BP_CDCDR_HSI_TX_SEL,
+	.bm = BM_CDCDR_HSI_TX_SEL,
+	.parents = {
+		&pll3_120m,
+		&pll2_pfd_400m,
+		NULL
+	},
+};
+
+#define DEF_IPU_DI_PRE_MUX(r, i, d)					\
+	static struct multiplexer ipu##i##_di##d##_pre_mux = {		\
+		.clk = &ipu##i##_di##d##_pre_clk,			\
+		.reg = r,						\
+		.bp = BP_##r##_IPU##i##_DI##d##_PRE_SEL,		\
+		.bm = BM_##r##_IPU##i##_DI##d##_PRE_SEL,		\
+		.parents = {						\
+			&mmdc_ch0_axi_clk,				\
+			&pll3_usb_otg,					\
+			&pll5_video,					\
+			&pll2_pfd_352m,					\
+			&pll2_pfd_400m,					\
+			&pll3_pfd_540m,					\
+			NULL						\
+		},							\
+	}
+
+DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 0);
+DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 1);
+DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 0);
+DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 1);
+
+#define DEF_IPU_DI_MUX(r, i, d)						\
+	static struct multiplexer ipu##i##_di##d##_mux = {		\
+		.clk = &ipu##i##_di##d##_clk,				\
+		.reg = r,						\
+		.bp = BP_##r##_IPU##i##_DI##d##_SEL,			\
+		.bm = BM_##r##_IPU##i##_DI##d##_SEL,			\
+		.parents = {						\
+			&ipu##i##_di##d##_pre_clk,			\
+			&dummy_clk,					\
+			&dummy_clk,					\
+			&ldb_di0_clk,					\
+			&ldb_di1_clk,					\
+			NULL						\
+		},							\
+	}
+
+DEF_IPU_DI_MUX(CHSCCDR, 1, 0);
+DEF_IPU_DI_MUX(CHSCCDR, 1, 1);
+DEF_IPU_DI_MUX(CSCDR2, 2, 0);
+DEF_IPU_DI_MUX(CSCDR2, 2, 1);
+
+#define DEF_IPU_MUX(id)							\
+	static struct multiplexer ipu##id##_mux = {			\
+		.clk = &ipu##id##_clk,					\
+		.reg = CSCDR3,						\
+		.bp = BP_CSCDR3_IPU##id##_HSP_SEL,			\
+		.bm = BM_CSCDR3_IPU##id##_HSP_SEL,			\
+		.parents = {						\
+			&mmdc_ch0_axi_clk,				\
+			&pll2_pfd_400m,					\
+			&pll3_120m,					\
+			&pll3_pfd_540m,					\
+			NULL						\
+		},							\
+	}
+
+DEF_IPU_MUX(1);
+DEF_IPU_MUX(2);
+
+static struct multiplexer *multiplexers[] = {
+	&axi_mux,
+	&periph_mux,
+	&periph_pre_mux,
+	&periph_clk2_mux,
+	&periph2_mux,
+	&periph2_pre_mux,
+	&periph2_clk2_mux,
+	&gpu2d_axi_mux,
+	&gpu3d_axi_mux,
+	&gpu3d_core_mux,
+	&gpu3d_shader_mux,
+	&pcie_axi_mux,
+	&vdo_axi_mux,
+	&vpu_axi_mux,
+	&gpu2d_core_mux,
+	&ssi1_mux,
+	&ssi2_mux,
+	&ssi3_mux,
+	&usdhc1_mux,
+	&usdhc2_mux,
+	&usdhc3_mux,
+	&usdhc4_mux,
+	&emi_mux,
+	&emi_slow_mux,
+	&esai_mux,
+	&ldb_di0_mux,
+	&ldb_di1_mux,
+	&enfc_mux,
+	&spdif_mux,
+	&asrc_serial_mux,
+	&hsi_tx_mux,
+	&ipu1_di0_pre_mux,
+	&ipu1_di0_mux,
+	&ipu1_di1_pre_mux,
+	&ipu1_di1_mux,
+	&ipu2_di0_pre_mux,
+	&ipu2_di0_mux,
+	&ipu2_di1_pre_mux,
+	&ipu2_di1_mux,
+	&ipu1_mux,
+	&ipu2_mux,
+};
+
+static int _clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct multiplexer *m;
+	int i, num;
+	u32 val;
+
+	num = ARRAY_SIZE(multiplexers);
+	for (i = 0; i < num; i++)
+		if (multiplexers[i]->clk == clk) {
+			m = multiplexers[i];
+			break;
+		}
+	if (i == num)
+		return -EINVAL;
+
+	i = 0;
+	while (m->parents[i]) {
+		if (parent == m->parents[i])
+			break;
+		i++;
+	}
+	if (!m->parents[i])
+		return -EINVAL;
+
+	val = readl_relaxed(m->reg);
+	val &= ~m->bm;
+	val |= i << m->bp;
+	writel_relaxed(val, m->reg);
+
+	if (clk == &periph_clk)
+		return clk_busy_wait(clk);
+
+	return 0;
+}
+
+#define DEF_NG_CLK(name, p)				\
+	static struct clk name = {			\
+		.get_rate	= _clk_get_rate,	\
+		.set_rate	= _clk_set_rate,	\
+		.round_rate	= _clk_round_rate,	\
+		.set_parent	= _clk_set_parent,	\
+		.parent		= p,			\
+	}
+
+DEF_NG_CLK(periph_clk2_clk,	&osc_clk);
+DEF_NG_CLK(periph_pre_clk,	&pll2_bus);
+DEF_NG_CLK(periph_clk,		&periph_pre_clk);
+DEF_NG_CLK(periph2_clk2_clk,	&osc_clk);
+DEF_NG_CLK(periph2_pre_clk,	&pll2_bus);
+DEF_NG_CLK(periph2_clk,		&periph2_pre_clk);
+DEF_NG_CLK(axi_clk,		&periph_clk);
+DEF_NG_CLK(emi_clk,		&axi_clk);
+DEF_NG_CLK(arm_clk,		&pll1_sw_clk);
+DEF_NG_CLK(ahb_clk,		&periph_clk);
+DEF_NG_CLK(ipg_clk,		&ahb_clk);
+DEF_NG_CLK(ipg_perclk,		&ipg_clk);
+DEF_NG_CLK(ipu1_di0_pre_clk,	&pll3_pfd_540m);
+DEF_NG_CLK(ipu1_di1_pre_clk,	&pll3_pfd_540m);
+DEF_NG_CLK(ipu2_di0_pre_clk,	&pll3_pfd_540m);
+DEF_NG_CLK(ipu2_di1_pre_clk,	&pll3_pfd_540m);
+DEF_NG_CLK(asrc_serial_clk,	&pll3_usb_otg);
+
+#define DEF_CLK(name, er, es, p, s)			\
+	static struct clk name = {			\
+		.enable_reg	= er,			\
+		.enable_shift	= es,			\
+		.enable		= _clk_enable,		\
+		.disable	= _clk_disable,		\
+		.get_rate	= _clk_get_rate,	\
+		.set_rate	= _clk_set_rate,	\
+		.round_rate	= _clk_round_rate,	\
+		.set_parent	= _clk_set_parent,	\
+		.parent		= p,			\
+		.secondary	= s,			\
+	}
+
+DEF_CLK(aips_tz1_clk,	  CCGR0, CG0,  &ahb_clk,	  NULL);
+DEF_CLK(aips_tz2_clk,	  CCGR0, CG1,  &ahb_clk,	  NULL);
+DEF_CLK(apbh_dma_clk,	  CCGR0, CG2,  &ahb_clk,	  NULL);
+DEF_CLK(asrc_clk,	  CCGR0, CG3,  &pll4_audio,	  NULL);
+DEF_CLK(can1_serial_clk,  CCGR0, CG8,  &pll3_usb_otg,	  NULL);
+DEF_CLK(can1_clk,	  CCGR0, CG7,  &pll3_usb_otg,	  &can1_serial_clk);
+DEF_CLK(can2_serial_clk,  CCGR0, CG10, &pll3_usb_otg,	  NULL);
+DEF_CLK(can2_clk,	  CCGR0, CG9,  &pll3_usb_otg,	  &can2_serial_clk);
+DEF_CLK(ecspi1_clk,	  CCGR1, CG0,  &pll3_60m,	  NULL);
+DEF_CLK(ecspi2_clk,	  CCGR1, CG1,  &pll3_60m,	  NULL);
+DEF_CLK(ecspi3_clk,	  CCGR1, CG2,  &pll3_60m,	  NULL);
+DEF_CLK(ecspi4_clk,	  CCGR1, CG3,  &pll3_60m,	  NULL);
+DEF_CLK(ecspi5_clk,	  CCGR1, CG4,  &pll3_60m,	  NULL);
+DEF_CLK(enet_clk,	  CCGR1, CG5,  &ipg_clk,	  NULL);
+DEF_CLK(esai_clk,	  CCGR1, CG8,  &pll3_usb_otg,	  NULL);
+DEF_CLK(gpt_serial_clk,	  CCGR1, CG11, &ipg_perclk,	  NULL);
+DEF_CLK(gpt_clk,	  CCGR1, CG10, &ipg_perclk,	  &gpt_serial_clk);
+DEF_CLK(gpu2d_core_clk,	  CCGR1, CG12, &pll2_pfd_352m,	  &gpu2d_axi_clk);
+DEF_CLK(gpu3d_core_clk,	  CCGR1, CG13, &pll2_pfd_594m,	  &gpu3d_axi_clk);
+DEF_CLK(gpu3d_shader_clk, CCGR1, CG13, &pll3_pfd_720m,	  &gpu3d_axi_clk);
+DEF_CLK(hdmi_iahb_clk,	  CCGR2, CG0,  &ahb_clk,	  NULL);
+DEF_CLK(hdmi_isfr_clk,	  CCGR2, CG2,  &pll3_pfd_540m,	  &hdmi_iahb_clk);
+DEF_CLK(i2c1_clk,	  CCGR2, CG3,  &ipg_perclk,	  NULL);
+DEF_CLK(i2c2_clk,	  CCGR2, CG4,  &ipg_perclk,	  NULL);
+DEF_CLK(i2c3_clk,	  CCGR2, CG5,  &ipg_perclk,	  NULL);
+DEF_CLK(iim_clk,	  CCGR2, CG6,  &ipg_clk,	  NULL);
+DEF_CLK(enfc_clk,	  CCGR2, CG7,  &pll2_pfd_352m,	  NULL);
+DEF_CLK(ipu1_clk,	  CCGR3, CG0,  &mmdc_ch0_axi_clk, NULL);
+DEF_CLK(ipu1_di0_clk,	  CCGR3, CG1,  &ipu1_di0_pre_clk, NULL);
+DEF_CLK(ipu1_di1_clk,	  CCGR3, CG2,  &ipu1_di1_pre_clk, NULL);
+DEF_CLK(ipu2_clk,	  CCGR3, CG3,  &mmdc_ch0_axi_clk, NULL);
+DEF_CLK(ipu2_di0_clk,	  CCGR3, CG4,  &ipu2_di0_pre_clk, NULL);
+DEF_CLK(ipu2_di1_clk,	  CCGR3, CG5,  &ipu2_di1_pre_clk, NULL);
+DEF_CLK(ldb_di0_clk,	  CCGR3, CG6,  &pll3_pfd_540m,	  NULL);
+DEF_CLK(ldb_di1_clk,	  CCGR3, CG7,  &pll3_pfd_540m,	  NULL);
+DEF_CLK(hsi_tx_clk,	  CCGR3, CG8,  &pll2_pfd_400m,	  NULL);
+DEF_CLK(mlb_clk,	  CCGR3, CG9,  &pll6_mlb,	  NULL);
+DEF_CLK(mmdc_ch0_ipg_clk, CCGR3, CG12, &ipg_clk,	  NULL);
+DEF_CLK(mmdc_ch0_axi_clk, CCGR3, CG10, &periph_clk,	  &mmdc_ch0_ipg_clk);
+DEF_CLK(mmdc_ch1_ipg_clk, CCGR3, CG13, &ipg_clk,	  NULL);
+DEF_CLK(mmdc_ch1_axi_clk, CCGR3, CG11, &periph2_clk,	  &mmdc_ch1_ipg_clk);
+DEF_CLK(openvg_axi_clk,   CCGR3, CG13, &axi_clk,	  NULL);
+DEF_CLK(pwm1_clk,	  CCGR4, CG8,  &ipg_perclk,	  NULL);
+DEF_CLK(pwm2_clk,	  CCGR4, CG9,  &ipg_perclk,	  NULL);
+DEF_CLK(pwm3_clk,	  CCGR4, CG10, &ipg_perclk,	  NULL);
+DEF_CLK(pwm4_clk,	  CCGR4, CG11, &ipg_perclk,	  NULL);
+DEF_CLK(gpmi_bch_apb_clk, CCGR4, CG12, &usdhc3_clk,	  NULL);
+DEF_CLK(gpmi_bch_clk,	  CCGR4, CG13, &usdhc4_clk,	  &gpmi_bch_apb_clk);
+DEF_CLK(gpmi_apb_clk,	  CCGR4, CG15, &usdhc3_clk,	  &gpmi_bch_clk);
+DEF_CLK(gpmi_io_clk,	  CCGR4, CG14, &enfc_clk,	  &gpmi_apb_clk);
+DEF_CLK(sdma_clk,	  CCGR5, CG3,  &ahb_clk,	  NULL);
+DEF_CLK(spba_clk,	  CCGR5, CG6,  &ipg_clk,	  NULL);
+DEF_CLK(spdif_clk,	  CCGR5, CG7,  &pll3_usb_otg,	  &spba_clk);
+DEF_CLK(ssi1_clk,	  CCGR5, CG9,  &pll3_pfd_508m,	  NULL);
+DEF_CLK(ssi2_clk,	  CCGR5, CG10, &pll3_pfd_508m,	  NULL);
+DEF_CLK(ssi3_clk,	  CCGR5, CG11, &pll3_pfd_508m,	  NULL);
+DEF_CLK(uart_serial_clk,  CCGR5, CG13, &pll3_usb_otg,	  NULL);
+DEF_CLK(uart_clk,	  CCGR5, CG12, &pll3_80m,	  &uart_serial_clk);
+DEF_CLK(usboh3_clk,	  CCGR6, CG0,  &ipg_clk,	  NULL);
+DEF_CLK(usdhc1_clk,	  CCGR6, CG1,  &pll2_pfd_400m,	  NULL);
+DEF_CLK(usdhc2_clk,	  CCGR6, CG2,  &pll2_pfd_400m,	  NULL);
+DEF_CLK(usdhc3_clk,	  CCGR6, CG3,  &pll2_pfd_400m,	  NULL);
+DEF_CLK(usdhc4_clk,	  CCGR6, CG4,  &pll2_pfd_400m,	  NULL);
+DEF_CLK(emi_slow_clk,	  CCGR6, CG5,  &axi_clk,	  NULL);
+DEF_CLK(vdo_axi_clk,	  CCGR6, CG6,  &axi_clk,	  NULL);
+DEF_CLK(vpu_clk,	  CCGR6, CG7,  &axi_clk,	  NULL);
+
+static int pcie_clk_enable(struct clk *clk)
+{
+	u32 val;
+
+	val = readl_relaxed(PLL8_ENET);
+	val |= BM_PLL_ENET_EN_PCIE;
+	writel_relaxed(val, PLL8_ENET);
+
+	return _clk_enable(clk);
+}
+
+static void pcie_clk_disable(struct clk *clk)
+{
+	u32 val;
+
+	_clk_disable(clk);
+
+	val = readl_relaxed(PLL8_ENET);
+	val &= BM_PLL_ENET_EN_PCIE;
+	writel_relaxed(val, PLL8_ENET);
+}
+
+static struct clk pcie_clk = {
+	.enable_reg = CCGR4,
+	.enable_shift = CG0,
+	.enable = pcie_clk_enable,
+	.disable = pcie_clk_disable,
+	.set_parent = _clk_set_parent,
+	.parent = &axi_clk,
+	.secondary = &pll8_enet,
+};
+
+static int sata_clk_enable(struct clk *clk)
+{
+	u32 val;
+
+	val = readl_relaxed(PLL8_ENET);
+	val |= BM_PLL_ENET_EN_SATA;
+	writel_relaxed(val, PLL8_ENET);
+
+	return _clk_enable(clk);
+}
+
+static void sata_clk_disable(struct clk *clk)
+{
+	u32 val;
+
+	_clk_disable(clk);
+
+	val = readl_relaxed(PLL8_ENET);
+	val &= BM_PLL_ENET_EN_SATA;
+	writel_relaxed(val, PLL8_ENET);
+}
+
+static struct clk sata_clk = {
+	.enable_reg = CCGR5,
+	.enable_shift = CG2,
+	.enable = sata_clk_enable,
+	.disable = sata_clk_disable,
+	.parent = &ipg_clk,
+	.secondary = &pll8_enet,
+};
+
+#define _REGISTER_CLOCK(d, n, c) \
+	{ \
+		.dev_id = d, \
+		.con_id = n, \
+		.clk = &c, \
+	}
+
+static struct clk_lookup lookups[] = {
+	_REGISTER_CLOCK("2020000.uart", NULL, uart_clk),
+	_REGISTER_CLOCK("21e8000.uart", NULL, uart_clk),
+	_REGISTER_CLOCK("21ec000.uart", NULL, uart_clk),
+	_REGISTER_CLOCK("21f0000.uart", NULL, uart_clk),
+	_REGISTER_CLOCK("21f4000.uart", NULL, uart_clk),
+	_REGISTER_CLOCK("2188000.enet", NULL, enet_clk),
+	_REGISTER_CLOCK("2190000.usdhc", NULL, usdhc1_clk),
+	_REGISTER_CLOCK("2194000.usdhc", NULL, usdhc2_clk),
+	_REGISTER_CLOCK("2198000.usdhc", NULL, usdhc3_clk),
+	_REGISTER_CLOCK("219c000.usdhc", NULL, usdhc4_clk),
+	_REGISTER_CLOCK("21a0000.i2c", NULL, i2c1_clk),
+	_REGISTER_CLOCK("21a4000.i2c", NULL, i2c2_clk),
+	_REGISTER_CLOCK("21a8000.i2c", NULL, i2c3_clk),
+	_REGISTER_CLOCK("2008000.ecspi", NULL, ecspi1_clk),
+	_REGISTER_CLOCK("200c000.ecspi", NULL, ecspi2_clk),
+	_REGISTER_CLOCK("2010000.ecspi", NULL, ecspi3_clk),
+	_REGISTER_CLOCK("2014000.ecspi", NULL, ecspi4_clk),
+	_REGISTER_CLOCK("2018000.ecspi", NULL, ecspi5_clk),
+	_REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk),
+	_REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk),
+	_REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk),
+	_REGISTER_CLOCK(NULL, "ckih", ckih_clk),
+	_REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk),
+	_REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk),
+	_REGISTER_CLOCK(NULL, "aips_tz2_clk", aips_tz2_clk),
+	_REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk),
+	_REGISTER_CLOCK(NULL, "can2_clk", can2_clk),
+	_REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_isfr_clk),
+	_REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
+	_REGISTER_CLOCK(NULL, "mlb_clk", mlb_clk),
+	_REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
+	_REGISTER_CLOCK(NULL, "pwm1_clk", pwm1_clk),
+	_REGISTER_CLOCK(NULL, "pwm2_clk", pwm2_clk),
+	_REGISTER_CLOCK(NULL, "pwm3_clk", pwm3_clk),
+	_REGISTER_CLOCK(NULL, "pwm4_clk", pwm4_clk),
+	_REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk),
+	_REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
+	_REGISTER_CLOCK(NULL, "sata_clk", sata_clk),
+};
+
+int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
+{
+	u32 val = readl_relaxed(CLPCR);
+
+	val &= ~BM_CLPCR_LPM;
+	switch (mode) {
+	case WAIT_CLOCKED:
+		break;
+	case WAIT_UNCLOCKED:
+		val |= 0x1 << BP_CLPCR_LPM;
+		break;
+	case STOP_POWER_ON:
+		val |= 0x2 << BP_CLPCR_LPM;
+		break;
+	case WAIT_UNCLOCKED_POWER_OFF:
+		val |= 0x1 << BP_CLPCR_LPM;
+		val &= ~BM_CLPCR_VSTBY;
+		val &= ~BM_CLPCR_SBYOS;
+		val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+		break;
+	case STOP_POWER_OFF:
+		val |= 0x2 << BP_CLPCR_LPM;
+		val |= 0x3 << BP_CLPCR_STBY_COUNT;
+		val |= BM_CLPCR_VSTBY;
+		val |= BM_CLPCR_SBYOS;
+		val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+		break;
+	default:
+		return -EINVAL;
+	}
+	writel_relaxed(val, CLPCR);
+
+	return 0;
+}
+
+static struct map_desc imx6q_clock_desc[] = {
+	imx_map_entry(MX6Q, CCM, MT_DEVICE),
+	imx_map_entry(MX6Q, ANATOP, MT_DEVICE),
+};
+
+int __init mx6q_clocks_init(void)
+{
+	struct device_node *np;
+	void __iomem *base;
+	int i, irq;
+
+	iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc));
+
+	/* retrieve the freqency of fixed clocks from device tree */
+	for_each_compatible_node(np, NULL, "fixed-clock") {
+		u32 rate;
+		if (of_property_read_u32(np, "clock-frequency", &rate))
+			continue;
+
+		if (of_device_is_compatible(np, "fsl,imx6q-clkl"))
+			external_low_reference = rate;
+		else if (of_device_is_compatible(np, "fsl,imx6q-clkh"))
+			external_high_reference = rate;
+		else if (of_device_is_compatible(np, "fsl,imx6q-osc"))
+			oscillator_reference = rate;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(lookups); i++)
+		clkdev_add(&lookups[i]);
+
+	/* only keep necessary clocks on */
+	writel_relaxed(0x3 << CG0  | 0x3 << CG1  | 0x3 << CG2,	CCGR0);
+	writel_relaxed(0x3 << CG8  | 0x3 << CG9  | 0x3 << CG10,	CCGR2);
+	writel_relaxed(0x3 << CG10 | 0x3 << CG12,		CCGR3);
+	writel_relaxed(0x3 << CG4  | 0x3 << CG6  | 0x3 << CG7,	CCGR4);
+	writel_relaxed(0x3 << CG0,				CCGR5);
+	writel_relaxed(0,					CCGR6);
+	writel_relaxed(0,					CCGR7);
+
+	clk_enable(&uart_clk);
+	clk_enable(&mmdc_ch0_axi_clk);
+
+	clk_set_rate(&pll4_audio, FREQ_650M);
+	clk_set_rate(&pll5_video, FREQ_650M);
+	clk_set_parent(&ipu1_di0_clk, &ipu1_di0_pre_clk);
+	clk_set_parent(&ipu1_di0_pre_clk, &pll5_video);
+	clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594m);
+	clk_set_rate(&gpu3d_shader_clk, FREQ_594M);
+	clk_set_parent(&gpu3d_core_clk, &mmdc_ch0_axi_clk);
+	clk_set_rate(&gpu3d_core_clk, FREQ_528M);
+	clk_set_parent(&asrc_serial_clk, &pll3_usb_otg);
+	clk_set_rate(&asrc_serial_clk, 1500000);
+	clk_set_rate(&enfc_clk, 11000000);
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
+	base = of_iomap(np, 0);
+	WARN_ON(!base);
+	irq = irq_of_parse_and_map(np, 0);
+	mxc_timer_init(&gpt_clk, base, irq);
+
+	return 0;
+}
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
new file mode 100644
index 0000000..e1537f9
--- /dev/null
+++ b/arch/arm/mach-imx/gpc.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later@the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/hardware/gic.h>
+
+#define GPC_IMR1		0x008
+#define GPC_PGC_CPU_PDN		0x2a0
+
+#define IMR_NUM			4
+
+static void __iomem *gpc_base;
+static u32 gpc_wake_irqs[IMR_NUM];
+static u32 gpc_saved_imrs[IMR_NUM];
+
+void imx_gpc_pre_suspend(void)
+{
+	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
+	int i;
+
+	/* Tell GPC to power off ARM core when suspend */
+	writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
+
+	for (i = 0; i < IMR_NUM; i++) {
+		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
+		writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
+	}
+}
+
+void imx_gpc_post_resume(void)
+{
+	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
+	int i;
+
+	/* Keep ARM core powered on for other low-power modes */
+	writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
+
+	for (i = 0; i < IMR_NUM; i++)
+		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
+}
+
+static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+	unsigned int idx = d->irq / 32 - 1;
+	u32 mask;
+
+	/* Sanity check for SPI irq */
+	if (d->irq < 32)
+		return -EINVAL;
+
+	mask = 1 << d->irq % 32;
+	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
+				  gpc_wake_irqs[idx] & ~mask;
+
+	return 0;
+}
+
+static void imx_gpc_irq_unmask(struct irq_data *d)
+{
+	void __iomem *reg;
+	u32 val;
+
+	/* Sanity check for SPI irq */
+	if (d->irq < 32)
+		return;
+
+	reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
+	val = readl_relaxed(reg);
+	val &= ~(1 << d->irq % 32);
+	writel_relaxed(val, reg);
+}
+
+static void imx_gpc_irq_mask(struct irq_data *d)
+{
+	void __iomem *reg;
+	u32 val;
+
+	/* Sanity check for SPI irq */
+	if (d->irq < 32)
+		return;
+
+	reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
+	val = readl_relaxed(reg);
+	val |= 1 << (d->irq % 32);
+	writel_relaxed(val, reg);
+}
+
+void __init imx_gpc_init(void)
+{
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
+	gpc_base = of_iomap(np, 0);
+	WARN_ON(!gpc_base);
+
+	/* Register GPC as the secondary interrupt controller behind GIC */
+	gic_arch_extn.irq_mask = imx_gpc_irq_mask;
+	gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
+	gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
+}
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
new file mode 100644
index 0000000..c461e98
--- /dev/null
+++ b/arch/arm/mach-imx/mmdc.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+
+#define MMDC_MAPSR		0x404
+#define BP_MMDC_MAPSR_PSD	0
+#define BP_MMDC_MAPSR_PSS	4
+
+static int __devinit imx_mmdc_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	void __iomem *mmdc_base, *reg;
+	u32 val;
+	int timeout = 0x400;
+
+	mmdc_base = of_iomap(np, 0);
+	WARN_ON(!mmdc_base);
+
+	reg = mmdc_base + MMDC_MAPSR;
+
+	/* Enable automatic power saving */
+	val = readl_relaxed(reg);
+	val &= ~(1 << BP_MMDC_MAPSR_PSD);
+	writel_relaxed(val, reg);
+
+	/* Ensure it's successfully enabled */
+	while (!(readl_relaxed(reg) & 1 << BP_MMDC_MAPSR_PSS) && --timeout)
+		cpu_relax();
+
+	if (unlikely(!timeout)) {
+		pr_warn("%s: failed to enable automatic power saving\n",
+			__func__);
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+static struct of_device_id imx_mmdc_dt_ids[] = {
+	{ .compatible = "fsl,imx6q-mmdc", },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver imx_mmdc_driver = {
+	.driver		= {
+		.name	= "imx-mmdc",
+		.owner	= THIS_MODULE,
+		.of_match_table = imx_mmdc_dt_ids,
+	},
+	.probe		= imx_mmdc_probe,
+};
+
+static int __init imx_mmdc_init(void)
+{
+	return platform_driver_register(&imx_mmdc_driver);
+}
+postcore_initcall(imx_mmdc_init);
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
new file mode 100644
index 0000000..36cacbd
--- /dev/null
+++ b/arch/arm/mach-imx/src.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later@the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <asm/unified.h>
+
+#define SRC_SCR				0x000
+#define SRC_GPR1			0x020
+#define BP_SRC_SCR_CORE1_RST		14
+#define BP_SRC_SCR_CORE1_ENABLE		22
+
+static void __iomem *src_base;
+
+void imx_enable_cpu(int cpu, bool enable)
+{
+	u32 mask, val;
+
+	mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
+	val = readl_relaxed(src_base + SRC_SCR);
+	val = enable ? val | mask : val & ~mask;
+	writel_relaxed(val, src_base + SRC_SCR);
+}
+
+void imx_set_cpu_jump(int cpu, void *jump_addr)
+{
+	writel_relaxed(BSYM(virt_to_phys(jump_addr)),
+		       src_base + SRC_GPR1 + cpu * 8);
+}
+
+void __init imx_src_init(void)
+{
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
+	src_base = of_iomap(np, 0);
+	WARN_ON(!src_base);
+}
-- 
1.7.4.1

^ permalink raw reply related

* [PATCH v5 3/8] arm/imx: add gic_handle_irq function
From: Shawn Guo @ 2011-10-03  2:57 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1317610626-24357-1-git-send-email-shawn.guo@linaro.org>

This is a plain translation of assembly gic irq handler to C function
for CONFIG_MULTI_IRQ_HANDLER support on imx family.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 arch/arm/plat-mxc/Makefile                   |    2 +-
 arch/arm/plat-mxc/gic.c                      |   47 ++++++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/common.h      |    2 +
 arch/arm/plat-mxc/include/mach/entry-macro.S |    6 +++
 4 files changed, 56 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/plat-mxc/gic.c

diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index d53c35f..b9f0f5f 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -5,7 +5,7 @@
 # Common support
 obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
 
-# MX51 uses the TZIC interrupt controller, older platforms use AVIC
+obj-$(CONFIG_ARM_GIC) += gic.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
 
diff --git a/arch/arm/plat-mxc/gic.c b/arch/arm/plat-mxc/gic.c
new file mode 100644
index 0000000..aed9d70
--- /dev/null
+++ b/arch/arm/plat-mxc/gic.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <asm/localtimer.h>
+#include <asm/hardware/gic.h>
+#ifdef CONFIG_SMP
+#include <asm/smp.h>
+#endif
+
+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+	u32 irqstat, irqnr;
+
+	do {
+		irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
+		irqnr = irqstat & 0x3ff;
+		if (irqnr == 1023)
+			break;
+
+		if (irqnr > 29 && irqnr < 1021)
+			handle_IRQ(irqnr, regs);
+#ifdef CONFIG_SMP
+		else if (irqnr < 16) {
+			writel_relaxed(irqstat, gic_cpu_base_addr +
+						GIC_CPU_EOI);
+			handle_IPI(irqnr, regs);
+		}
+#endif
+#ifdef CONFIG_LOCAL_TIMERS
+		else if (irqnr == 29) {
+			writel_relaxed(irqstat, gic_cpu_base_addr +
+						GIC_CPU_EOI);
+			handle_local_timer(regs);
+		}
+#endif
+	} while (1);
+}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index ace4bb5..c225837 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -86,6 +86,7 @@ extern void imx_print_silicon_rev(const char *cpu, int srev);
 
 void avic_handle_irq(struct pt_regs *);
 void tzic_handle_irq(struct pt_regs *);
+void gic_handle_irq(struct pt_regs *);
 
 #define imx1_handle_irq avic_handle_irq
 #define imx21_handle_irq avic_handle_irq
@@ -96,5 +97,6 @@ void tzic_handle_irq(struct pt_regs *);
 #define imx50_handle_irq tzic_handle_irq
 #define imx51_handle_irq tzic_handle_irq
 #define imx53_handle_irq tzic_handle_irq
+#define imx6q_handle_irq gic_handle_irq
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 842fbcb..9fe0dfc 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -22,3 +22,9 @@
 
 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 	.endm
+
+	.macro test_for_ipi, irqnr, irqstat, base, tmp
+	.endm
+
+	.macro test_for_ltirq, irqnr, irqstat, base, tmp
+	.endm
-- 
1.7.4.1

^ permalink raw reply related

* [PATCH v5 2/8] arm/imx6q: add core definitions and low-level debug uart
From: Shawn Guo @ 2011-10-03  2:57 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1317610626-24357-1-git-send-email-shawn.guo@linaro.org>

It adds the core definitions and low-level debug uart support
for imx6q.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 arch/arm/Kconfig                             |    2 +-
 arch/arm/Kconfig.debug                       |    7 +++++
 arch/arm/Makefile                            |    1 +
 arch/arm/mach-imx/Kconfig                    |   14 +++++++++++
 arch/arm/mach-imx/Makefile                   |    2 +
 arch/arm/mach-imx/Makefile.boot              |    4 +++
 arch/arm/mach-imx/lluart.c                   |   32 +++++++++++++++++++++++++
 arch/arm/plat-mxc/Kconfig                    |    7 +++++
 arch/arm/plat-mxc/include/mach/debug-macro.S |    2 +
 arch/arm/plat-mxc/include/mach/hardware.h    |    6 ++++
 arch/arm/plat-mxc/include/mach/irqs.h        |   10 ++++++-
 arch/arm/plat-mxc/include/mach/mx6q.h        |   33 ++++++++++++++++++++++++++
 12 files changed, 117 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-imx/lluart.c
 create mode 100644 arch/arm/plat-mxc/include/mach/mx6q.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2b9578c..03dd6b0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1407,7 +1407,7 @@ config SMP
 	depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
 		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
 		 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
-		 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
+		 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || SOC_IMX6Q
 	select USE_GENERIC_SMP_HELPERS
 	select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
 	help
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 961ce3c..0c82ccd 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -176,6 +176,13 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on i.MX50 or i.MX53.
 
+	config DEBUG_IMX6Q_UART
+		bool "i.MX6Q Debug UART"
+		depends on SOC_IMX6Q
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on i.MX6Q.
+
 	config DEBUG_S3C_UART0
 		depends on PLAT_SAMSUNG
 		bool "Use S3C UART 0 for low-level debug"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 8904caa..193439e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -160,6 +160,7 @@ machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
 machine-$(CONFIG_ARCH_IMX_V4_V5)	:= imx
 machine-$(CONFIG_ARCH_MX3)		:= imx
 machine-$(CONFIG_ARCH_MX5)		:= mx5
+machine-$(CONFIG_ARCH_MX6)		:= imx
 machine-$(CONFIG_ARCH_MXS)		:= mxs
 machine-$(CONFIG_ARCH_NETX)		:= netx
 machine-$(CONFIG_ARCH_NOMADIK)		:= nomadik
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index b4e1bf8..be402fa 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -592,3 +592,17 @@ config MACH_VPR200
 	  configurations for the board and its peripherals.
 
 endif
+
+if ARCH_MX6
+comment "i.MX6 family:"
+
+config SOC_IMX6Q
+	bool "i.MX6 Quad support"
+	select ARM_GIC
+	select CPU_V7
+	select USE_OF
+
+	help
+	  This enables support for Freescale i.MX6 Quad processor.
+
+endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 116d4b2..b9ed198 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -60,3 +60,5 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
 obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
+
+obj-$(CONFIG_DEBUG_LL) += lluart.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index dbe6120..22d8588 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -17,3 +17,7 @@ initrd_phys-$(CONFIG_MACH_MX27)	:= 0xA0800000
 zreladdr-$(CONFIG_ARCH_MX3)	+= 0x80008000
 params_phys-$(CONFIG_ARCH_MX3)	:= 0x80000100
 initrd_phys-$(CONFIG_ARCH_MX3)	:= 0x80800000
+
+zreladdr-$(CONFIG_SOC_IMX6Q)	+= 0x10008000
+params_phys-$(CONFIG_SOC_IMX6Q)	:= 0x10000100
+initrd_phys-$(CONFIG_SOC_IMX6Q)	:= 0x10800000
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
new file mode 100644
index 0000000..d4ab6f2
--- /dev/null
+++ b/arch/arm/mach-imx/lluart.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <asm/page.h>
+#include <asm/sizes.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+
+static struct map_desc imx_lluart_desc = {
+#ifdef CONFIG_DEBUG_IMX6Q_UART
+	.virtual	= MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR),
+	.pfn		= __phys_to_pfn(MX6Q_UART4_BASE_ADDR),
+	.length		= MX6Q_UART4_SIZE,
+	.type		= MT_DEVICE,
+#endif
+};
+
+void __init imx_lluart_map_io(void)
+{
+	if (imx_lluart_desc.virtual)
+		iotable_init(&imx_lluart_desc, 1);
+}
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 502e45f..058d1c5 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -29,6 +29,13 @@ config ARCH_MX5
 	  This enables support for machines using Freescale's i.MX50 and i.MX51
 	  processors.
 
+config ARCH_MX6
+	bool "i.MX6"
+	select AUTO_ZRELADDR if !ZBOOT_ROM
+	select ARM_PATCH_PHYS_VIRT
+	help
+	  This enables support for systems based on the Freescale i.MX6 family
+
 endchoice
 
 source "arch/arm/mach-imx/Kconfig"
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 7298601..6e192c4 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -24,6 +24,8 @@
 #define UART_PADDR	MX51_UART1_BASE_ADDR
 #elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
 #define UART_PADDR	MX53_UART1_BASE_ADDR
+#elif defined (CONFIG_DEBUG_IMX6Q_UART)
+#define UART_PADDR	MX6Q_UART4_BASE_ADDR
 #endif
 
 #define UART_VADDR	IMX_IO_ADDRESS(UART_PADDR)
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index eba3118..a599f01 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -91,6 +91,11 @@
  *	SPBA0	0x50000000+0x100000	->	0xf5400000+0x100000
  *	AIPS1	0x53f00000+0x100000	->	0xf5700000+0x100000
  *	AIPS2	0x63f00000+0x100000	->	0xf5300000+0x100000
+ * mx6q:
+ *	SCU	0x00a00000+0x001000	->	0xf4000000+0x001000
+ *	CCM	0x020c4000+0x004000	->	0xf42c4000+0x004000
+ *	ANATOP	0x020c8000+0x001000	->	0xf42c8000+0x001000
+ *	UART4	0x021f0000+0x004000	->	0xf42f0000+0x004000
  */
 #define IMX_IO_P2V(x)	(						\
 			0xf4000000 +					\
@@ -102,6 +107,7 @@
 
 #include <mach/mxc.h>
 
+#include <mach/mx6q.h>
 #include <mach/mx50.h>
 #include <mach/mx51.h>
 #include <mach/mx53.h>
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 00e812b..fd9efb0 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -14,9 +14,15 @@
 #include <asm-generic/gpio.h>
 
 /*
- * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
+ * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
+ * have 128 IRQs, and those with AVIC have 64.
+ *
+ * To support single image, the biggest number should be defined on
+ * top of the list.
  */
-#ifdef CONFIG_MXC_TZIC
+#if defined CONFIG_ARM_GIC
+#define MXC_INTERNAL_IRQS	160
+#elif defined CONFIG_MXC_TZIC
 #define MXC_INTERNAL_IRQS	128
 #else
 #define MXC_INTERNAL_IRQS	64
diff --git a/arch/arm/plat-mxc/include/mach/mx6q.h b/arch/arm/plat-mxc/include/mach/mx6q.h
new file mode 100644
index 0000000..254a561
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx6q.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MACH_MX6Q_H__
+#define __MACH_MX6Q_H__
+
+#define MX6Q_IO_P2V(x)			IMX_IO_P2V(x)
+#define MX6Q_IO_ADDRESS(x)		IOMEM(MX6Q_IO_P2V(x))
+
+/*
+ * The following are the blocks that need to be statically mapped.
+ * For other blocks, the base address really should be retrieved from
+ * device tree.
+ */
+#define MX6Q_SCU_BASE_ADDR		0x00a00000
+#define MX6Q_SCU_SIZE			0x1000
+#define MX6Q_CCM_BASE_ADDR		0x020c4000
+#define MX6Q_CCM_SIZE			0x4000
+#define MX6Q_ANATOP_BASE_ADDR		0x020c8000
+#define MX6Q_ANATOP_SIZE		0x1000
+#define MX6Q_UART4_BASE_ADDR		0x021f0000
+#define MX6Q_UART4_SIZE			0x4000
+
+#endif	/* __MACH_MX6Q_H__ */
-- 
1.7.4.1

^ permalink raw reply related

* [PATCH v5 1/8] arm/imx6q: add device tree source
From: Shawn Guo @ 2011-10-03  2:56 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1317610626-24357-1-git-send-email-shawn.guo@linaro.org>

It adds device tree source and documentation for imx6q platform.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 Documentation/devicetree/bindings/arm/fsl.txt |    6 +
 arch/arm/boot/dts/imx6q-sabreauto.dts         |   82 ++++
 arch/arm/boot/dts/imx6q.dtsi                  |  555 +++++++++++++++++++++++++
 3 files changed, 643 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/fsl.txt
 create mode 100644 arch/arm/boot/dts/imx6q-sabreauto.dts
 create mode 100644 arch/arm/boot/dts/imx6q.dtsi

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
new file mode 100644
index 0000000..345bfc0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -0,0 +1,6 @@
+Freescale i.MX Platforms Device Tree Bindings
+-----------------------------------------------
+
+i.MX6 Quad SABRE Automotive Board
+Required root node properties:
+    - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
new file mode 100644
index 0000000..7dd93e8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx6q.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad SABRE Automotive Board";
+	compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+
+	chosen {
+		bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
+	};
+
+	memory {
+		reg = <0x10000000 0x80000000>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clkl {
+			compatible = "fsl,imx6q-clkl", "fixed-clock";
+			clock-frequency = <32768>;
+		};
+
+		clkh {
+			compatible = "fsl,imx6q-clkh", "fixed-clock";
+			clock-frequency = <0>;
+		};
+
+		osc {
+			compatible = "fsl,imx6q-osc", "fixed-clock";
+			clock-frequency = <24000000>;
+		};
+	};
+
+	soc {
+		aips-bus at 02100000 { /* AIPS2 */
+			enet at 02188000 {
+				phy-mode = "rgmii";
+				local-mac-address = [00 04 9F 01 1B 61];
+				status = "okay";
+			};
+
+			usdhc at 02198000 { /* uSDHC3 */
+				cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */
+				wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */
+				status = "okay";
+			};
+
+			usdhc at 0219c000 { /* uSDHC4 */
+				fsl,card-wired;
+				status = "okay";
+			};
+
+			uart3: uart at 021f0000 { /* UART4 */
+				status = "okay";
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		debug-led {
+			label = "Heartbeat";
+			gpios = <&gpio2 25 0>; /* GPIO3_25 */
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
new file mode 100644
index 0000000..843e545
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -0,0 +1,555 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu at 1 {
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu at 2 {
+			compatible = "arm,cortex-a9";
+			reg = <2>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu at 3 {
+			compatible = "arm,cortex-a9";
+			reg = <3>;
+			next-level-cache = <&L2>;
+		};
+	};
+
+	intc: interrupt-controller at 00a01000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-controller;
+		reg = <0x00a01000 0x1000>,
+		      <0x00a00100 0x100>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		timer at 00a00600 {
+			compatible = "arm,smp-twd";
+			reg = <0x00a00600 0x100>;
+			interrupts = <1 13 0xf4>;
+		};
+
+		L2: l2-cache at 00a02000 {
+			compatible = "arm,pl310-cache";
+			reg = <0x00a02000 0x1000>;
+			interrupts = <0 92 0x04>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		aips-bus at 02000000 { /* AIPS1 */
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x02000000 0x100000>;
+			ranges;
+
+			spba-bus at 02000000 {
+				compatible = "fsl,spba-bus", "simple-bus";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x02000000 0x40000>;
+				ranges;
+
+				spdif at 02004000 {
+					reg = <0x02004000 0x4000>;
+					interrupts = <0 52 0x04>;
+				};
+
+				ecspi at 02008000 { /* eCSPI1 */
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+					reg = <0x02008000 0x4000>;
+					interrupts = <0 31 0x04>;
+					status = "disabled";
+				};
+
+				ecspi at 0200c000 { /* eCSPI2 */
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+					reg = <0x0200c000 0x4000>;
+					interrupts = <0 32 0x04>;
+					status = "disabled";
+				};
+
+				ecspi at 02010000 { /* eCSPI3 */
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+					reg = <0x02010000 0x4000>;
+					interrupts = <0 33 0x04>;
+					status = "disabled";
+				};
+
+				ecspi at 02014000 { /* eCSPI4 */
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+					reg = <0x02014000 0x4000>;
+					interrupts = <0 34 0x04>;
+					status = "disabled";
+				};
+
+				ecspi at 02018000 { /* eCSPI5 */
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+					reg = <0x02018000 0x4000>;
+					interrupts = <0 35 0x04>;
+					status = "disabled";
+				};
+
+				uart0: uart at 02020000 { /* UART1 */
+					compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+					reg = <0x02020000 0x4000>;
+					interrupts = <0 26 0x04>;
+					status = "disabled";
+				};
+
+				esai at 02024000 {
+					reg = <0x02024000 0x4000>;
+					interrupts = <0 51 0x04>;
+				};
+
+				ssi at 02028000 { /* SSI1 */
+					reg = <0x02028000 0x4000>;
+					interrupts = <0 46 0x04>;
+				};
+
+				ssi at 0202c000 { /* SSI2 */
+					reg = <0x0202c000 0x4000>;
+					interrupts = <0 47 0x04>;
+				};
+
+				ssi at 02030000 { /* SSI3 */
+					reg = <0x02030000 0x4000>;
+					interrupts = <0 48 0x04>;
+				};
+
+				asrc at 02034000 {
+					reg = <0x02034000 0x4000>;
+					interrupts = <0 50 0x04>;
+				};
+
+				spba at 0203c000 {
+					reg = <0x0203c000 0x4000>;
+				};
+			};
+
+			vpu at 02040000 {
+				reg = <0x02040000 0x3c000>;
+				interrupts = <0 3 0x04 0 12 0x04>;
+			};
+
+			aipstz at 0207c000 { /* AIPSTZ1 */
+				reg = <0x0207c000 0x4000>;
+			};
+
+			pwm at 02080000 { /* PWM1 */
+				reg = <0x02080000 0x4000>;
+				interrupts = <0 83 0x04>;
+			};
+
+			pwm at 02084000 { /* PWM2 */
+				reg = <0x02084000 0x4000>;
+				interrupts = <0 84 0x04>;
+			};
+
+			pwm at 02088000 { /* PWM3 */
+				reg = <0x02088000 0x4000>;
+				interrupts = <0 85 0x04>;
+			};
+
+			pwm at 0208c000 { /* PWM4 */
+				reg = <0x0208c000 0x4000>;
+				interrupts = <0 86 0x04>;
+			};
+
+			flexcan at 02090000 { /* CAN1 */
+				reg = <0x02090000 0x4000>;
+				interrupts = <0 110 0x04>;
+			};
+
+			flexcan at 02094000 { /* CAN2 */
+				reg = <0x02094000 0x4000>;
+				interrupts = <0 111 0x04>;
+			};
+
+			gpt at 02098000 {
+				compatible = "fsl,imx6q-gpt";
+				reg = <0x02098000 0x4000>;
+				interrupts = <0 55 0x04>;
+			};
+
+			gpio0: gpio at 0209c000 { /* GPIO1 */
+				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+				reg = <0x0209c000 0x4000>;
+				interrupts = <0 66 0x04 0 67 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			gpio1: gpio at 020a0000 { /* GPIO2 */
+				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+				reg = <0x020a0000 0x4000>;
+				interrupts = <0 68 0x04 0 69 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			gpio2: gpio at 020a4000 { /* GPIO3 */
+				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+				reg = <0x020a4000 0x4000>;
+				interrupts = <0 70 0x04 0 71 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			gpio3: gpio at 020a8000 { /* GPIO4 */
+				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+				reg = <0x020a8000 0x4000>;
+				interrupts = <0 72 0x04 0 73 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			gpio4: gpio at 020ac000 { /* GPIO5 */
+				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+				reg = <0x020ac000 0x4000>;
+				interrupts = <0 74 0x04 0 75 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			gpio5: gpio at 020b0000 { /* GPIO6 */
+				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+				reg = <0x020b0000 0x4000>;
+				interrupts = <0 76 0x04 0 77 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			gpio6: gpio at 020b4000 { /* GPIO7 */
+				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+				reg = <0x020b4000 0x4000>;
+				interrupts = <0 78 0x04 0 79 0x04>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			kpp at 020b8000 {
+				reg = <0x020b8000 0x4000>;
+				interrupts = <0 82 0x04>;
+			};
+
+			wdog at 020bc000 { /* WDOG1 */
+				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+				reg = <0x020bc000 0x4000>;
+				interrupts = <0 80 0x04>;
+				status = "disabled";
+			};
+
+			wdog at 020c0000 { /* WDOG2 */
+				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+				reg = <0x020c0000 0x4000>;
+				interrupts = <0 81 0x04>;
+				status = "disabled";
+			};
+
+			ccm at 020c4000 {
+				compatible = "fsl,imx6q-ccm";
+				reg = <0x020c4000 0x4000>;
+				interrupts = <0 87 0x04 0 88 0x04>;
+			};
+
+			anatop at 020c8000 {
+				compatible = "fsl,imx6q-anatop";
+				reg = <0x020c8000 0x1000>;
+				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+			};
+
+			usbphy at 020c9000 { /* USBPHY1 */
+				reg = <0x020c9000 0x1000>;
+				interrupts = <0 44 0x04>;
+			};
+
+			usbphy at 020ca000 { /* USBPHY2 */
+				reg = <0x020ca000 0x1000>;
+				interrupts = <0 45 0x04>;
+			};
+
+			snvs at 020cc000 {
+				reg = <0x020cc000 0x4000>;
+				interrupts = <0 19 0x04 0 20 0x04>;
+			};
+
+			epit at 020d0000 { /* EPIT1 */
+				reg = <0x020d0000 0x4000>;
+				interrupts = <0 56 0x04>;
+			};
+
+			epit at 020d4000 { /* EPIT2 */
+				reg = <0x020d4000 0x4000>;
+				interrupts = <0 57 0x04>;
+			};
+
+			src at 020d8000 {
+				compatible = "fsl,imx6q-src";
+				reg = <0x020d8000 0x4000>;
+				interrupts = <0 91 0x04 0 96 0x04>;
+			};
+
+			gpc at 020dc000 {
+				compatible = "fsl,imx6q-gpc";
+				reg = <0x020dc000 0x4000>;
+				interrupts = <0 89 0x04 0 90 0x04>;
+			};
+
+			iomuxc at 020e0000 {
+				reg = <0x020e0000 0x4000>;
+			};
+
+			dcic at 020e4000 { /* DCIC1 */
+				reg = <0x020e4000 0x4000>;
+				interrupts = <0 124 0x04>;
+			};
+
+			dcic at 020e8000 { /* DCIC2 */
+				reg = <0x020e8000 0x4000>;
+				interrupts = <0 125 0x04>;
+			};
+
+			sdma at 020ec000 {
+				compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
+				reg = <0x020ec000 0x4000>;
+				interrupts = <0 2 0x04>;
+			};
+		};
+
+		aips-bus at 02100000 { /* AIPS2 */
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x02100000 0x100000>;
+			ranges;
+
+			caam at 02100000 {
+				reg = <0x02100000 0x40000>;
+				interrupts = <0 105 0x04 0 106 0x04>;
+			};
+
+			aipstz at 0217c000 { /* AIPSTZ2 */
+				reg = <0x0217c000 0x4000>;
+			};
+
+			enet at 02188000 {
+				compatible = "fsl,imx6q-fec";
+				reg = <0x02188000 0x4000>;
+				interrupts = <0 118 0x04 0 119 0x04>;
+				status = "disabled";
+			};
+
+			mlb at 0218c000 {
+				reg = <0x0218c000 0x4000>;
+				interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
+			};
+
+			usdhc at 02190000 { /* uSDHC1 */
+				compatible = "fsl,imx6q-usdhc";
+				reg = <0x02190000 0x4000>;
+				interrupts = <0 22 0x04>;
+				status = "disabled";
+			};
+
+			usdhc at 02194000 { /* uSDHC2 */
+				compatible = "fsl,imx6q-usdhc";
+				reg = <0x02194000 0x4000>;
+				interrupts = <0 23 0x04>;
+				status = "disabled";
+			};
+
+			usdhc at 02198000 { /* uSDHC3 */
+				compatible = "fsl,imx6q-usdhc";
+				reg = <0x02198000 0x4000>;
+				interrupts = <0 24 0x04>;
+				status = "disabled";
+			};
+
+			usdhc at 0219c000 { /* uSDHC4 */
+				compatible = "fsl,imx6q-usdhc";
+				reg = <0x0219c000 0x4000>;
+				interrupts = <0 25 0x04>;
+				status = "disabled";
+			};
+
+			i2c at 021a0000 { /* I2C1 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+				reg = <0x021a0000 0x4000>;
+				interrupts = <0 36 0x04>;
+				status = "disabled";
+			};
+
+			i2c at 021a4000 { /* I2C2 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+				reg = <0x021a4000 0x4000>;
+				interrupts = <0 37 0x04>;
+				status = "disabled";
+			};
+
+			i2c at 021a8000 { /* I2C3 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+				reg = <0x021a8000 0x4000>;
+				interrupts = <0 38 0x04>;
+				status = "disabled";
+			};
+
+			romcp at 021ac000 {
+				reg = <0x021ac000 0x4000>;
+			};
+
+			mmdc at 021b0000 { /* MMDC0 */
+				compatible = "fsl,imx6q-mmdc";
+				reg = <0x021b0000 0x4000>;
+			};
+
+			mmdc at 021b4000 { /* MMDC1 */
+				reg = <0x021b4000 0x4000>;
+			};
+
+			weim at 021b8000 {
+				reg = <0x021b8000 0x4000>;
+				interrupts = <0 14 0x04>;
+			};
+
+			ocotp at 021bc000 {
+				reg = <0x021bc000 0x4000>;
+			};
+
+			ocotp at 021c0000 {
+				reg = <0x021c0000 0x4000>;
+				interrupts = <0 21 0x04>;
+			};
+
+			tzasc at 021d0000 { /* TZASC1 */
+				reg = <0x021d0000 0x4000>;
+				interrupts = <0 108 0x04>;
+			};
+
+			tzasc at 021d4000 { /* TZASC2 */
+				reg = <0x021d4000 0x4000>;
+				interrupts = <0 109 0x04>;
+			};
+
+			audmux at 021d8000 {
+				reg = <0x021d8000 0x4000>;
+			};
+
+			mipi at 021dc000 { /* MIPI-CSI */
+				reg = <0x021dc000 0x4000>;
+			};
+
+			mipi at 021e0000 { /* MIPI-DSI */
+				reg = <0x021e0000 0x4000>;
+			};
+
+			vdoa at 021e4000 {
+				reg = <0x021e4000 0x4000>;
+				interrupts = <0 18 0x04>;
+			};
+
+			uart1: uart at 021e8000 { /* UART2 */
+				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+				reg = <0x021e8000 0x4000>;
+				interrupts = <0 27 0x04>;
+				status = "disabled";
+			};
+
+			uart2: uart at 021ec000 { /* UART3 */
+				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+				reg = <0x021ec000 0x4000>;
+				interrupts = <0 28 0x04>;
+				status = "disabled";
+			};
+
+			uart3: uart at 021f0000 { /* UART4 */
+				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+				reg = <0x021f0000 0x4000>;
+				interrupts = <0 29 0x04>;
+				status = "disabled";
+			};
+
+			uart4: uart at 021f4000 { /* UART5 */
+				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+				reg = <0x021f4000 0x4000>;
+				interrupts = <0 30 0x04>;
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
1.7.4.1

^ permalink raw reply related

* [PATCH v5 0/8] add initial imx6q support
From: Shawn Guo @ 2011-10-03  2:56 UTC (permalink / raw)
  To: linux-arm-kernel

This patch series adds the initial support for imx6q, which is a
Cortex-A9 Quad Core based SoC.

It's based on v3.1-rc8 with the following branches merged.

* rmk's for-next branch with the following additional patches wait for
  rmk to apply:
  - ARM: l2x0: add empty l2x0_of_init (Rob Herring)
  - ARM: cache-l2x0: add resume entry for l2 in secure mode (Barry Song)
  - ARM: localtimer: add header linux/errno.h explicitly (Shawn Guo)
  - ARM: smp: Add an IPI handler callable from C code (Marc Zyngier)
  - ARM: smp: Add a localtimer handler callable from C code (Shawn Guo)

* Rob Herring's "GIC OF bindings" series, currently on

    git://git.jdl.com/software/linux-3.0.git gic-v2

  tglx has picked up the two that are irq core related.  And I'm not
  sure about the branch that Rob will push others to.

* Branches that will be merged into arm-soc
  - Sascha's imx-cleanup
  - Sascha's imx-features
  - [GIT PULL] DEBUG_LL platform updates for 3.2 (Will Deacon)

Regards,
Shawn

Changes since v4:
 * Address Russell's comments, do not call do_IPI() and do_local_timer()
   from C code.
 * Change to 'select AUTO_ZRELADDR if !ZBOOT_ROM'
 * Rebase to Barry's L2 suspend infrastructure
 * Fold Sascha's merge-imx3-imx6 patch to get single zImage support for
   imx3 and imx6 family

Changes since v3:
 * Fold the gic_handle_irq (local to imx) support patch in the series.
   It can be replaced by Marc Zyngier's global gic_handle_irq support
   with a little rework if his PPI and MULTI_IRQ_HANDLER series gets
   merged.

Changes since v2:
 * Refine the L2 register save/restore implementation per Lorenzo's
   suggestion
 * Rebase to Rob's latest GIC OF bindings series
 * Rebase to Sascha's MULTI_IRQ_HANDLER support series

Changes since v1:
 * Use the existing IMX_IO_P2V for static mapping
 * Fix the MXC_INTERNAL_IRQS breakage introduced by GIC definition
 * Retrieve clock frequency for fixed clocks from device tree
 * Drop early_initcall from imx_src_init() and call it from imx6q
   platform initialization
 * Use readl_relaxed/writel_relaxed rather than __raw_readl/__raw_writel
   as suggested by Arnd
 * Kill unnecessary imx_local_timer_pre_suspend/resume functions
 * Kill Kconfig symbol MACH_IMX6Q
 * Rebase to rmk's "Add L2 cache cleaning to generic CPU suspend" series
   so that we can retain L2 cache with necessary L2 register
   save/restore across suspend/resume cycle
 * Rebase to Rob's new "GIC OF bindings" series

Sascha Hauer (1):
      arm/imx: merge i.MX3 and i.MX6

Shawn Guo (7):
      arm/imx6q: add device tree source
      arm/imx6q: add core definitions and low-level debug uart
      arm/imx: add gic_handle_irq function
      arm/imx6q: add core drivers clock, gpc, mmdc and src
      arm/imx6q: add smp and cpu hotplug support
      arm/imx6q: add device tree machine support
      arm/imx6q: add suspend/resume support

 Documentation/devicetree/bindings/arm/fsl.txt |    6 +
 arch/arm/Kconfig                              |    2 +-
 arch/arm/Kconfig.debug                        |    7 +
 arch/arm/Makefile                             |    2 +-
 arch/arm/boot/dts/imx6q-sabreauto.dts         |   82 +
 arch/arm/boot/dts/imx6q.dtsi                  |  555 +++++++
 arch/arm/mach-imx/Kconfig                     |   29 +-
 arch/arm/mach-imx/Makefile                    |   11 +
 arch/arm/mach-imx/Makefile.boot               |   14 +-
 arch/arm/mach-imx/clock-imx6q.c               | 2012 +++++++++++++++++++++++++
 arch/arm/mach-imx/gpc.c                       |  113 ++
 arch/arm/mach-imx/head-v7.S                   |   99 ++
 arch/arm/mach-imx/hotplug.c                   |   44 +
 arch/arm/mach-imx/lluart.c                    |   32 +
 arch/arm/mach-imx/localtimer.c                |   35 +
 arch/arm/mach-imx/mach-imx6q.c                |   84 +
 arch/arm/mach-imx/mmdc.c                      |   72 +
 arch/arm/mach-imx/platsmp.c                   |   85 ++
 arch/arm/mach-imx/pm-imx6q.c                  |   70 +
 arch/arm/mach-imx/src.c                       |   49 +
 arch/arm/mm/Kconfig                           |    2 +-
 arch/arm/plat-mxc/Kconfig                     |   11 +-
 arch/arm/plat-mxc/Makefile                    |    2 +-
 arch/arm/plat-mxc/gic.c                       |   47 +
 arch/arm/plat-mxc/include/mach/common.h       |   29 +
 arch/arm/plat-mxc/include/mach/debug-macro.S  |    2 +
 arch/arm/plat-mxc/include/mach/entry-macro.S  |    6 +
 arch/arm/plat-mxc/include/mach/hardware.h     |    6 +
 arch/arm/plat-mxc/include/mach/irqs.h         |   10 +-
 arch/arm/plat-mxc/include/mach/mx6q.h         |   33 +
 30 files changed, 3537 insertions(+), 14 deletions(-)

^ permalink raw reply

* [PATCH v4 0/7] add initial imx6q support
From: Shawn Guo @ 2011-10-03  2:40 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <201109302304.26953.arnd@arndb.de>

On Fri, Sep 30, 2011 at 11:04:26PM +0200, Arnd Bergmann wrote:
> On Wednesday 28 September 2011, Shawn Guo wrote:
> > 
> > This patch series adds the initial support for imx6q, which is a
> > Cortex-A9 Quad Core based SoC.
> > 
> > We chose to add imx6q support into mach-imx other than mach-mx5 or
> > a new mach-mx6, because we intend to merge mach-mx5 into mach-imx, so
> > that we have only mach-imx for imx family.
> > 
> > It's based on linux-next-20110926 with some prerequisite patches
> > not showing up on linux-next applied.
> 
> How should we best proceed on this series? Sascha, do you want to
> take the next version into your tree once Shawn has addressed the
> remaining comments, or should I just take the patches with your
> Ack?
> 
> Shawn, what are the current dependencies? I will have to pull
> in the other branches that this depends on into the next/soc
> tree and then wait for those to get merged first before I send
> this to Linus.
> 
Thanks for asking, Arnd.

The latest version (v5) of this series that I will send shortly has
the dependencies on the following branches.

* rmk's for-next branch with the following additional patches wait for
  rmk to apply:
  - ARM: l2x0: add empty l2x0_of_init (Rob Herring)
  - ARM: cache-l2x0: add resume entry for l2 in secure mode (Barry Song)
  - ARM: localtimer: add header linux/errno.h explicitly (Shawn Guo)
  - ARM: smp: Add an IPI handler callable from C code (Marc Zyngier)
  - ARM: smp: Add a localtimer handler callable from C code (Shawn Guo)

* Rob Herring's "GIC OF bindings" series, currently on

    git://git.jdl.com/software/linux-3.0.git gic-v2

  tglx has picked up the two that are irq core related.  And I'm not
  sure about the branch that Rob will push others to.

* Branches that will be merged into arm-soc
  - Sascha's imx-cleanup
  - Sascha's imx-features
  - [GIT PULL] DEBUG_LL platform updates for 3.2 (Will Deacon)

-- 
Regards,
Shawn

^ permalink raw reply

* [PATCH 2/3] define ARM-specific dma_coherent_write_sync
From: Jon Masters @ 2011-10-03  1:40 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1315321331.2313.10.camel@deneb.redhat.com>

On Sep 6, 2011, at 11:02 AM, Mark Salter wrote:
> 
> In any case, the current thinking is that the original problem with
> the USB performance seen on cortex A9 multicore is probably something
> more than just write buffer delays. Once the original problem is better
> understood, we can take another look at this patch if it is still
> needed.


Thanks again for looking into this Mark. My understanding is that this is still being investigated. I'll followup with ARM to see how that's going since I've heard nothing recently :) Meanwhile, we're continuing to carry a hack based on these patches in Fedora ARM kernels.

Jon.

^ permalink raw reply

* [PATCH 08/30] ARM: omap2+: fix building without i2c
From: Paul Walmsley @ 2011-10-03  1:31 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1317566760-25681-9-git-send-email-arnd@arndb.de>

Hello Arnd,

On Sun, 2 Oct 2011, Arnd Bergmann wrote:

> A trivial typo causes build breakage when I2C is disabled
> and omap_i2c_reset is set to NULL on OMAP:
> 
> omap_hwmod_44xx_data.c:2287:11: error: lvalue required as unary '&' operand
> 
> Removing the '&' character solves this.
> 
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Cc: Avinash.H.M <avinashhm@ti.com>
> Cc: Paul Walmsley <paul@pwsan.com>

Nice catch.  I think the bug is different, though.  omap_i2c_reset should 
never be NULL: that code is intended to execute even when 
CONFIG_I2C_OMAP=n.  The idea is to prevent the IP block from interfering 
with the rest of the kernel even if the driver is not compiled in, no 
matter how the bootloader or previous OS programmed the IP block.

I'd suggest something like the following patch instead.


- Paul

From: Paul Walmsley <paul@pwsan.com>
Date: Sun, 2 Oct 2011 19:15:10 -0600
Subject: [PATCH] ARM: omap2+: fix build breakage when CONFIG_I2C_OMAP=n

arch/arm/mach-omap2/Makefile incorrectly skips compilation of the I2C
IP block reset code when CONFIG_I2C_OMAP=n.  Fix by unconditionally
compiling arch/arm/mach-omap2/i2c.o, which is needed on all OMAP2+ platforms.

Problem noted by Arnd Bergmann <arnd@arndb.de>.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Avinash.H.M <avinashhm@ti.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/Makefile |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f343365..0951986 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-	 common.o gpio.o dma.o wd_timer.o
+	 common.o gpio.o dma.o wd_timer.o i2c.o
 
 omap-2-3-common				= irq.o sdrc.o
 hwmod-common				= omap_hwmod.o \
@@ -175,9 +175,6 @@ obj-$(CONFIG_OMAP_IOMMU)		+= iommu2.o
 iommu-$(CONFIG_OMAP_IOMMU)		:= omap-iommu.o
 obj-y					+= $(iommu-m) $(iommu-y)
 
-i2c-omap-$(CONFIG_I2C_OMAP)		:= i2c.o
-obj-y					+= $(i2c-omap-m) $(i2c-omap-y)
-
 ifneq ($(CONFIG_TIDSPBRIDGE),)
 obj-y					+= dsp.o
 endif
-- 
1.7.6.3

^ permalink raw reply related

* [PATCH 1/1] ARM: Make debug UART optional for S3C devices
From: Thiago A. Correa @ 2011-10-03  0:32 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <yes>

This patch makes serial debug messages optional on
Samsung SoC s3c devices making all UART ports available
for other uses.

Signed-off-by: Thiago A. Correa <thiago.correa@gmail.com>
---
 arch/arm/boot/compressed/head.S                 |    2 +-
 arch/arm/plat-samsung/Kconfig                   |   11 +++++++++++
 arch/arm/plat-samsung/include/plat/uncompress.h |    9 +++++++++
 3 files changed, 21 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 9f5ac11..3afb755 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -58,7 +58,7 @@
 		add	\rb, \rb, #0x00010000	@ Ser1
 #endif
 		.endm
-#elif defined(CONFIG_ARCH_S3C2410)
+#elif defined(CONFIG_ARCH_S3C2410) && CONFIG_ENABLE_DEBUG_S3C_UART
 		.macro loadsp, rb, tmp
 		mov	\rb, #0x50000000
 		add	\rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index b3e1065..c2183f0 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -33,7 +33,17 @@ config S3C_BOOT_ERROR_RESET
 	  Say y here to use the watchdog to reset the system if the
 	  kernel decompressor detects an error during decompression.
 
+
+config ENABLE_DEBUG_S3C_UART
+	bool "Enable S3C Debug UART"
+	help
+	  Say Y here if you want debug print of low level kernel messages
+	  using S3C UARTS.
+
+	  If in doubt, say N.
+
 config S3C_BOOT_UART_FORCE_FIFO
+       depends on ENABLE_DEBUG_S3C_UART
        bool "Force UART FIFO on during boot process"
        default y
        help
@@ -42,6 +52,7 @@ config S3C_BOOT_UART_FORCE_FIFO
 
 
 config S3C_LOWLEVEL_UART_PORT
+	depends on ENABLE_DEBUG_S3C_UART
 	int "S3C UART to use for low-level messages"
 	default 0
 	help
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index ee48e12..778c2df 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -37,6 +37,7 @@ static void arch_detect_cpu(void);
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX	 (14)
 
+#if defined(CONFIG_ENABLE_DEBUG_S3C_UART)
 #define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
 
 static __inline__ void
@@ -85,11 +86,19 @@ static void putc(int ch)
 	/* write byte to transmission register */
 	uart_wr(S3C2410_UTXH, ch);
 }
+#else
+static inline void putc(int ch)
+{
+}
+
+
+#endif
 
 static inline void flush(void)
 {
 }
 
+
 #define __raw_writel(d, ad)			\
 	do {							\
 		*((volatile unsigned int __force *)(ad)) = (d); \
-- 
1.7.3.4

^ permalink raw reply related

* [PATCH 15/30] usb/musb: use a Kconfig choice to pick the right DMA method
From: Felipe Balbi @ 2011-10-02 22:10 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1546914.88vcgxkfJf@wuerfel>

Hi,

On Sun, Oct 02, 2011 at 09:44:26PM +0200, Arnd Bergmann wrote:
> > that's how MUSB works now and that's what I have been discussing with
> > Alan Stern for the past month or so, wrt to *HCI. There are even patches
> > floating on linux-usb right now trying to hash out the problems.
> 
> Ah, glad to see that is happening. I can probably get rid of a bunch
> of randconfig patches I have for those then.

glad to hear you're sorting out randconfig :-)

> > Maybe you should have consulted the maintainers of those drivers before
> > making such statements.
> >
> > MUSB is not the best example because of its history. I understand the
> > DMA part is still really messy, but we have been working very hard to
> > hash the problems and still allow new glue layers to be merged.
> 
> Sorry if I have made my statement sound like an accusation, it wasn't
> meant as one, merely as a sigh at having identified yet another area
> that needs to be changed in order to have cross-platform ARM kernels
> working in every case.

no big deal ;-)

> > How about taking a sneak pick at what the code does right now ? As of
> > today, I can even even have all UDC controller drivers into one kernel
> > and I generally compile x86 with all controllers available. There's some
> > very small work that has to be done on each of the UDC drivers to remove
> > any references to <arch/..> <asm/..> and <plat/..> headers but that work
> > in in progress.
> 
> I didn't really see any problems with UDC at all. What I saw were a lot
> of build problems with the musb host side, and I rewrote this patch half
> a dozen times before I ended up with a version that consistently built
> without making the code look worse.

I understand.

> I also agree that the musb implementation is less of a problem than
> ohci/ehci in its current form, as it already is layered in the right
> way. I did not attempt to turn the Kconfig 'choice' statement there
> into a flat list though, so I wouldn't know what problems to expect.

Actually, MUSB still has lots of goofage from the original mentor
release but that's another story.

Anyway, I'll take your patches in, but their too late for this merge
window :-( I already sent my last pull to Greg.

-- 
balbi
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^ permalink raw reply

* [PATCH 5/6] ASoC: samsung: fix Kconfig dependencies
From: Mark Brown @ 2011-10-02 21:29 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <3289863.m6ULFZUV3p@wuerfel>

On Sun, Oct 02, 2011 at 11:14:55PM +0200, Arnd Bergmann wrote:

> So should SND_SOC_WM8994 instead select MFD_WM8994? That would mean adding
> the select only in one place.

select ignores the dependencies of the things it selects which isn't
enormously helpful for this sort of stuff.

^ permalink raw reply

* [PATCH v2 0/5] ARM: pxa: move gpio driver into drivers directory
From: Linus Walleij @ 2011-10-02 21:27 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20111001165105.GM11710@n2100.arm.linux.org.uk>

2011/10/1 Russell King - ARM Linux <linux@arm.linux.org.uk>:
> On Sat, Oct 01, 2011 at 05:42:41PM +0100, Russell King - ARM Linux wrote:
>> On Fri, Sep 30, 2011 at 06:19:15PM +0800, Haojian Zhuang wrote:
>> > Changelog:
>> > v2:
>> > ? ? 1. Remove gpio.c from mach-pxa & mach-mmp that is introduced from v1.
>> > ? ? 2. Remove init function in gpio.c. Move the platfrom_device_register()
>> > ? ? ? ?into platform driver.
>> > ? ? 3. Initialize pxa_gpio_regs in gpio-pxa.c
>> > ? ? 4. Simplify code of identifing pxa gpio series or mmp gpio series.
>> > ? ? 5. Use linux/io.h instead of asm/io.h.
>>
>> This series looks fine to me. ?You don't mention what it's based upon -
>> should I assume my gpio patch series? ?If so, it looks fine to be
>> submitted to the patch system.
>>
>> It would be nice to have a few acks from people against it first though.
>
> I assume this clashes with patches 7103/1 and 7104/1 in the patch system.
> Should I ignore those two for the meantime?

This series includes the stuff in those patches so if these are cleared
feel free to drop 7103/1 + 7104/1 and apply these instead, they do
the same thing and some more.

Yours,
Linus Walleij

^ permalink raw reply

* [PATCH 2/6] ASoC: codecs: AK4641 depends on GPIOLIB
From: Mark Brown @ 2011-10-02 21:27 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <2726393.3Oc3SrGyN4@wuerfel>

On Sun, Oct 02, 2011 at 10:53:24PM +0200, Arnd Bergmann wrote:
> On Sunday 02 October 2011 21:41:07 Mark Brown wrote:

> > No, gpiolib is one implementation of the GPIO API but if platforms want
> > to go and define their own that's currently OK (personally I think at

> Thanks for the explanation!

> Is there any other symbol that I can test then?

You shouldn't be testing anything - the client side GPIO API (which is
what this driver is using) is supposed to stub itself out when not in
use so drivers should just be able to use it without worrying about
dependencies.  You didn't report the problem but I'd expect that
whatever you saw will be an issue in whatever platform you were trying
to build for (I'm guessing it hasn't provided gpio_request_one()),
though it could be a problem in the gpiolib stubs if that's being used.

> I noticed that a lot of places use 'depends on GPIOLIB' or
> '#ifdef CONFIG_GPIOLIB', are those usually wrong, too?

Checks for gpiolib in drivers providing GPIOs are sensible, if a
platform hasn't used gpiolib then it's generally not even got an
interface for drivers to provide GPIOs.

On the user side these are usually due to people making the sort of
changes you're making here due to a random build coverage issue - it
seems unfortunately common for people to just shove a dependency in
Kconfig when they run into a build coverage issue without looking at
what's going on.  For a lot of the stuff you see on PCs it's going to
make sense but for some of the "service" APIs like GPIOs that are more
commonly used only in embedded contexts the use of the API is usually
completely optional (eg, in this case the driver is controlling power
and reset lines which could easily just be strapped in the hardware with
no soft control and are supplied as optional platform data) so for many
systems the driver is going to work completely happily without doing
anything with GPIOs.

Adding dependencies to all the users needlessly restricts which systems
can use the drivers.  Adding ifdefs to the drivers is repetitive and
isn't great for legiblity, having the header stub itself out is simpler
and easier to use on the driver side.

^ permalink raw reply

* [PATCH 1/2 v2] plat-pxa: move PXA GPIO driver to GPIO subsystem
From: Linus Walleij @ 2011-10-02 21:24 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20111001224421.GQ11710@n2100.arm.linux.org.uk>

2011/10/2 Russell King - ARM Linux <linux@arm.linux.org.uk>:
> On Tue, Sep 27, 2011 at 12:56:45PM +0200, Linus Walleij wrote:
>> ?obj-$(CONFIG_GPIO_PL061) ? ? += gpio-pl061.o
>> +obj-$(CONFIG_PLAT_PXA) ? ? ? ? ? ? ? += gpio-pxa.o
>> ?obj-$(CONFIG_GPIO_RDC321X) ? += gpio-rdc321x.o
>
> This is not what my drivers/gpio/Makefile contains. ?I've applied this
> patch with GNU patch with fuzz 2, resulting in:
>
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 84bc738..19c5d27 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -40,6 +40,7 @@ obj-$(CONFIG_GPIO_PCA953X) ? ?+= gpio-pca953x.o
> ?obj-$(CONFIG_GPIO_PCF857X) ? ? += gpio-pcf857x.o
> ?obj-$(CONFIG_GPIO_PCH) ? ? ? ? += gpio-pch.o
> ?obj-$(CONFIG_GPIO_PL061) ? ? ? += gpio-pl061.o
> +obj-$(CONFIG_PLAT_PXA) ? ? ? ? += gpio-pxa.o
> ?obj-$(CONFIG_GPIO_RDC321X) ? ? += gpio-rdc321x.o
>
> ?obj-$(CONFIG_GPIO_PLAT_SAMSUNG) ? ? ? ?+= gpio-plat-samsung.o
>
> This will probably conflict with Grant's tree.

Yes luckily it looks pretty trivial.

Haojioan is working on cleanups to this driver that need to be rebased
on top of this and submitted through your branch in order for us not
to create even more conflicts.

Feel free to drop any of this stuff if it's just causing trouble, it can
surely wait until the next merge window if need be.

Yours,
Linus Walleij

^ permalink raw reply

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