* [PATCH 2/7] s3c-adc: describe features via quirk constants
From: Kukjin Kim @ 2011-10-04 12:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201110021318.42131.heiko@sntech.de>
Heiko St?bner wrote:
>
> Hi Kgene,
>
> Am Sonntag 02 Oktober 2011, 09:38:18 schrieb Kukjin Kim:
> > How about following? I think following is also not bad...
> ok, I don't claim to have the right solution, so if keeping the TYPE_xxx
enum
> is better, I will do a rework of the series according to your solution and
> resend it.
>
Thanks for your understanding and please re-send it :)
> Could I meanwhile interest you in the patches for the S3C2416 armclk and
hsmmc
> (from 28 Sep 2011) :-) ?
>
Sure, will check it soon, maybe tomorrow?
Anyway, if any problems, let you know.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [PATCH 2/9] regulator: helper routine to extract regulator_init_data
From: Nayak, Rajendra @ 2011-10-04 12:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111004121152.GB6934@opensource.wolfsonmicro.com>
On Tue, Oct 4, 2011 at 5:41 PM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:
>
> On Tue, Oct 04, 2011 at 05:32:47PM +0530, Rajendra Nayak wrote:
> > On Tuesday 04 October 2011 05:21 PM, Mark Brown wrote:
>
> > >I wouldn't expect it done through DT (except for things like the fixed
> > >voltage regulator) - the driver should just know.
>
> > something like a
> > int regulator_set_supply(struct regulator_dev *rdev, char *supply_name);
> > to be called from drivers makes sense?
>
> Just put a member in the driver struct, much simpler that way, no code
> in the individual drivers.
okay, makes sense. I will add it to struct regulator_desc.
Thanks.
^ permalink raw reply
* [PATCH v4 06/10] ARM: SoC: convert Exynos4 to SoC descriptor
From: Marc Zyngier @ 2011-10-04 12:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAH9JG2ULZgHbnVBcO-QTqsO9iMPjDWqF4S23YQYW6fcPRSQRYw@mail.gmail.com>
On 04/10/11 12:01, Kyungmin Park wrote:
> On Tue, Oct 4, 2011 at 2:35 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> Convert Exynos4 to use the SoC descriptor to provide its SMP
>> and CPU hotplug operations.
>>
>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>> arch/arm/mach-exynos4/core.h | 9 +++++++++
>> arch/arm/mach-exynos4/cpu.c | 8 ++++++++
>> arch/arm/mach-exynos4/hotplug.c | 8 +++++---
>> arch/arm/mach-exynos4/mach-armlex4210.c | 3 +++
>> arch/arm/mach-exynos4/mach-nuri.c | 3 +++
>> arch/arm/mach-exynos4/mach-origen.c | 3 +++
>> arch/arm/mach-exynos4/mach-smdk4212.c | 3 +++
>> arch/arm/mach-exynos4/mach-smdkv310.c | 4 ++++
>> arch/arm/mach-exynos4/mach-universal_c210.c | 3 +++
>> arch/arm/mach-exynos4/platsmp.c | 25 +++++++++++++++++++++----
>> 10 files changed, 62 insertions(+), 7 deletions(-)
>> create mode 100644 arch/arm/mach-exynos4/core.h
>>
>> diff --git a/arch/arm/mach-exynos4/core.h b/arch/arm/mach-exynos4/core.h
>> new file mode 100644
>> index 0000000..ba9fcc8
>> --- /dev/null
>> +++ b/arch/arm/mach-exynos4/core.h
>> @@ -0,0 +1,9 @@
>
> It's helpful to add header guard
>
> #ifndef __EXYNOS4_CORE_H
> #define __EXYNOS4_CORE_H
Yep, will add.
>> +#include <asm/soc.h>
>> +
>> +extern struct arm_soc_smp_init_ops exynos4_soc_smp_init_ops;
>> +extern struct arm_soc_smp_ops exynos4_soc_smp_ops;
>> +extern struct arm_soc_desc exynos4_soc_desc;
>> +
>> +extern int exynos4_cpu_kill(unsigned int cpu);
>> +extern void exynos4_cpu_die(unsigned int cpu);
>> +extern int exynos4_cpu_disable(unsigned int cpu);
> #endif
>
> Tested-by: Kyungmin Park <kyungmin.park@samsung.com>
Thanks for testing.
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH 2/9] regulator: helper routine to extract regulator_init_data
From: Mark Brown @ 2011-10-04 12:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8AF5E7.8050402@ti.com>
On Tue, Oct 04, 2011 at 05:32:47PM +0530, Rajendra Nayak wrote:
> On Tuesday 04 October 2011 05:21 PM, Mark Brown wrote:
> >I wouldn't expect it done through DT (except for things like the fixed
> >voltage regulator) - the driver should just know.
> something like a
> int regulator_set_supply(struct regulator_dev *rdev, char *supply_name);
> to be called from drivers makes sense?
Just put a member in the driver struct, much simpler that way, no code
in the individual drivers.
^ permalink raw reply
* [PATCH 2/9] regulator: helper routine to extract regulator_init_data
From: Rajendra Nayak @ 2011-10-04 12:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111004115153.GL3250@opensource.wolfsonmicro.com>
On Tuesday 04 October 2011 05:21 PM, Mark Brown wrote:
> On Tue, Oct 04, 2011 at 05:10:00PM +0530, Rajendra Nayak wrote:
>> On Tuesday 04 October 2011 03:48 PM, Mark Brown wrote:
>
>>> This seems fairly straightforward though it will require some changes
>>> within Linux, all we have to do is have the regulators name their
>>> supplies.
>
>> through dt? thats what the original bindings was doing.
>
> I wouldn't expect it done through DT (except for things like the fixed
> voltage regulator) - the driver should just know.
something like a
int regulator_set_supply(struct regulator_dev *rdev, char *supply_name);
to be called from drivers makes sense?
^ permalink raw reply
* please add MACH_APF9328 to mach-types
From: gwenhael.goavec @ 2011-10-04 11:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110727082754.GT16561@pengutronix.de>
Hi,
This issue still does not seem fixed. Should I send a patch?
Gwenhael
On Wed, 27 Jul 2011 10:27:54 +0200
Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de> wrote:
> On Wed, Jul 27, 2011 at 09:23:03AM +0100, Russell King - ARM Linux wrote:
> > On Mon, Jul 25, 2011 at 11:08:59PM +0200, Uwe Kleine-K?nig wrote:
> > > mx1_defconfig currently fails to build because MACH_APF9328 is missing
> > > in arch/arm/tools/mach-types.
> > >
> > > Can you please add it back?
> >
> > Most people tell me the number.
> I'll interpret this as an hit to give it to you. The complete line to
> add is:
>
> apf9328 MACH_APF9328 APF9328 906
>
> Thanks,
> Uwe
>
> --
> Pengutronix e.K. | Uwe Kleine-K?nig |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH 2/9] regulator: helper routine to extract regulator_init_data
From: Mark Brown @ 2011-10-04 11:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8AF090.4070304@ti.com>
On Tue, Oct 04, 2011 at 05:10:00PM +0530, Rajendra Nayak wrote:
> On Tuesday 04 October 2011 03:48 PM, Mark Brown wrote:
> >This seems fairly straightforward though it will require some changes
> >within Linux, all we have to do is have the regulators name their
> >supplies.
> through dt? thats what the original bindings was doing.
I wouldn't expect it done through DT (except for things like the fixed
voltage regulator) - the driver should just know.
^ permalink raw reply
* [PATCH 2/9] regulator: helper routine to extract regulator_init_data
From: Rajendra Nayak @ 2011-10-04 11:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111004101846.GD3250@opensource.wolfsonmicro.com>
On Tuesday 04 October 2011 03:48 PM, Mark Brown wrote:
> On Tue, Oct 04, 2011 at 10:58:40AM +0530, Rajendra Nayak wrote:
>
>> The problem is I don't know if the property in the regulator dt
>> node is called "vin-supply" or "vxyz-supply" and hence I
>> can parse the property based on a substring alone, which is
>> "-supply" because all I know is the property name is expected
>> to end with a "-supply".
>
> This seems fairly straightforward though it will require some changes
> within Linux, all we have to do is have the regulators name their
> supplies.
through dt? thats what the original bindings was doing.
^ permalink raw reply
* [PATCH v4 06/10] ARM: SoC: convert Exynos4 to SoC descriptor
From: Kyungmin Park @ 2011-10-04 11:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317663356-5114-7-git-send-email-marc.zyngier@arm.com>
On Tue, Oct 4, 2011 at 2:35 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> Convert Exynos4 to use the SoC descriptor to provide its SMP
> and CPU hotplug operations.
>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> ?arch/arm/mach-exynos4/core.h ? ? ? ? ? ? ? ?| ? ?9 +++++++++
> ?arch/arm/mach-exynos4/cpu.c ? ? ? ? ? ? ? ? | ? ?8 ++++++++
> ?arch/arm/mach-exynos4/hotplug.c ? ? ? ? ? ? | ? ?8 +++++---
> ?arch/arm/mach-exynos4/mach-armlex4210.c ? ? | ? ?3 +++
> ?arch/arm/mach-exynos4/mach-nuri.c ? ? ? ? ? | ? ?3 +++
> ?arch/arm/mach-exynos4/mach-origen.c ? ? ? ? | ? ?3 +++
> ?arch/arm/mach-exynos4/mach-smdk4212.c ? ? ? | ? ?3 +++
> ?arch/arm/mach-exynos4/mach-smdkv310.c ? ? ? | ? ?4 ++++
> ?arch/arm/mach-exynos4/mach-universal_c210.c | ? ?3 +++
> ?arch/arm/mach-exynos4/platsmp.c ? ? ? ? ? ? | ? 25 +++++++++++++++++++++----
> ?10 files changed, 62 insertions(+), 7 deletions(-)
> ?create mode 100644 arch/arm/mach-exynos4/core.h
>
> diff --git a/arch/arm/mach-exynos4/core.h b/arch/arm/mach-exynos4/core.h
> new file mode 100644
> index 0000000..ba9fcc8
> --- /dev/null
> +++ b/arch/arm/mach-exynos4/core.h
> @@ -0,0 +1,9 @@
It's helpful to add header guard
#ifndef __EXYNOS4_CORE_H
#define __EXYNOS4_CORE_H
> +#include <asm/soc.h>
> +
> +extern struct arm_soc_smp_init_ops ? ? exynos4_soc_smp_init_ops;
> +extern struct arm_soc_smp_ops ? ? ? ? ?exynos4_soc_smp_ops;
> +extern struct arm_soc_desc ? ? ? ? ? ? exynos4_soc_desc;
> +
> +extern int ?exynos4_cpu_kill(unsigned int cpu);
> +extern void exynos4_cpu_die(unsigned int cpu);
> +extern int ?exynos4_cpu_disable(unsigned int cpu);
#endif
Tested-by: Kyungmin Park <kyungmin.park@samsung.com>
> diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
> index 2aa3df0..a15dce8 100644
> --- a/arch/arm/mach-exynos4/cpu.c
> +++ b/arch/arm/mach-exynos4/cpu.c
> @@ -33,6 +33,8 @@
> ?#include <mach/regs-irq.h>
> ?#include <mach/regs-pmu.h>
>
> +#include "core.h"
> +
> ?extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
> ? ? ? ? ? ? ? ? ? ? ? ? unsigned int irq_start);
> ?extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
> @@ -282,3 +284,9 @@ int __init exynos4_init(void)
>
> ? ? ? ?return sysdev_register(&exynos4_sysdev);
> ?}
> +
> +struct arm_soc_desc exynos4_soc_desc __initdata = {
> + ? ? ? .name ? ? ? ? ? = "Samsung Exynos4",
> + ? ? ? soc_smp_init_ops(exynos4_soc_smp_init_ops)
> + ? ? ? soc_smp_ops(exynos4_soc_smp_ops)
> +};
> diff --git a/arch/arm/mach-exynos4/hotplug.c b/arch/arm/mach-exynos4/hotplug.c
> index da70e7e..15fe884 100644
> --- a/arch/arm/mach-exynos4/hotplug.c
> +++ b/arch/arm/mach-exynos4/hotplug.c
> @@ -19,6 +19,8 @@
>
> ?#include <mach/regs-pmu.h>
>
> +#include "core.h"
> +
> ?extern volatile int pen_release;
>
> ?static inline void cpu_enter_lowpower(void)
> @@ -93,7 +95,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
> ? ? ? ?}
> ?}
>
> -int platform_cpu_kill(unsigned int cpu)
> +int exynos4_cpu_kill(unsigned int cpu)
> ?{
> ? ? ? ?return 1;
> ?}
> @@ -103,7 +105,7 @@ int platform_cpu_kill(unsigned int cpu)
> ?*
> ?* Called with IRQs disabled
> ?*/
> -void platform_cpu_die(unsigned int cpu)
> +void exynos4_cpu_die(unsigned int cpu)
> ?{
> ? ? ? ?int spurious = 0;
>
> @@ -123,7 +125,7 @@ void platform_cpu_die(unsigned int cpu)
> ? ? ? ? ? ? ? ?pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
> ?}
>
> -int platform_cpu_disable(unsigned int cpu)
> +int exynos4_cpu_disable(unsigned int cpu)
> ?{
> ? ? ? ?/*
> ? ? ? ? * we don't allow CPU 0 to be shutdown (it is still too special
> diff --git a/arch/arm/mach-exynos4/mach-armlex4210.c b/arch/arm/mach-exynos4/mach-armlex4210.c
> index f0ca6c1..8c82c6b 100644
> --- a/arch/arm/mach-exynos4/mach-armlex4210.c
> +++ b/arch/arm/mach-exynos4/mach-armlex4210.c
> @@ -28,6 +28,8 @@
>
> ?#include <mach/map.h>
>
> +#include "core.h"
> +
> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
> ?#define ARMLEX4210_UCON_DEFAULT ? ? ? ?(S3C2410_UCON_TXILEVEL | ? ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? S3C2410_UCON_RXILEVEL | ? ? ? ?\
> @@ -208,6 +210,7 @@ static void __init armlex4210_machine_init(void)
> ?MACHINE_START(ARMLEX4210, "ARMLEX4210")
> ? ? ? ?/* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
> ? ? ? ?.atag_offset ? ?= 0x100,
> + ? ? ? .soc ? ? ? ? ? ?= &exynos4_soc_desc,
> ? ? ? ?.init_irq ? ? ? = exynos4_init_irq,
> ? ? ? ?.map_io ? ? ? ? = armlex4210_map_io,
> ? ? ? ?.init_machine ? = armlex4210_machine_init,
> diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
> index 2204911..5780ee3 100644
> --- a/arch/arm/mach-exynos4/mach-nuri.c
> +++ b/arch/arm/mach-exynos4/mach-nuri.c
> @@ -48,6 +48,8 @@
>
> ?#include <mach/map.h>
>
> +#include <asm/soc.h>
> +
> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
> ?#define NURI_UCON_DEFAULT ? ? ?(S3C2410_UCON_TXILEVEL | ? ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? S3C2410_UCON_RXILEVEL | ? ? ? ?\
> @@ -1187,6 +1189,7 @@ static void __init nuri_machine_init(void)
> ?MACHINE_START(NURI, "NURI")
> ? ? ? ?/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
> ? ? ? ?.atag_offset ? ?= 0x100,
> + ? ? ? .soc ? ? ? ? ? ?= &exynos4_soc_desc,
> ? ? ? ?.init_irq ? ? ? = exynos4_init_irq,
> ? ? ? ?.map_io ? ? ? ? = nuri_map_io,
> ? ? ? ?.init_machine ? = nuri_machine_init,
> diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c
> index 421294b..06250fc 100644
> --- a/arch/arm/mach-exynos4/mach-origen.c
> +++ b/arch/arm/mach-exynos4/mach-origen.c
> @@ -33,6 +33,8 @@
>
> ?#include <mach/map.h>
>
> +#include "core.h"
> +
> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
> ?#define ORIGEN_UCON_DEFAULT ? ?(S3C2410_UCON_TXILEVEL | ? ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? S3C2410_UCON_RXILEVEL | ? ? ? ?\
> @@ -210,6 +212,7 @@ static void __init origen_machine_init(void)
> ?MACHINE_START(ORIGEN, "ORIGEN")
> ? ? ? ?/* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
> ? ? ? ?.atag_offset ? ?= 0x100,
> + ? ? ? .soc ? ? ? ? ? ?= &exynos4_soc_desc,
> ? ? ? ?.init_irq ? ? ? = exynos4_init_irq,
> ? ? ? ?.map_io ? ? ? ? = origen_map_io,
> ? ? ? ?.init_machine ? = origen_machine_init,
> diff --git a/arch/arm/mach-exynos4/mach-smdk4212.c b/arch/arm/mach-exynos4/mach-smdk4212.c
> index 8c41ae1..cf92514 100644
> --- a/arch/arm/mach-exynos4/mach-smdk4212.c
> +++ b/arch/arm/mach-exynos4/mach-smdk4212.c
> @@ -36,6 +36,8 @@
>
> ?#include <mach/map.h>
>
> +#include "core.h"
> +
> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
> ?#define SMDK4212_UCON_DEFAULT ?(S3C2410_UCON_TXILEVEL | ? ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? S3C2410_UCON_RXILEVEL | ? ? ? ?\
> @@ -285,6 +287,7 @@ static void __init smdk4212_machine_init(void)
> ?MACHINE_START(SMDK4212, "SMDK4212")
> ? ? ? ?/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
> ? ? ? ?.atag_offset ? ?= 0x100,
> + ? ? ? .soc ? ? ? ? ? ?= &exynos4_soc_desc,
> ? ? ? ?.init_irq ? ? ? = exynos4_init_irq,
> ? ? ? ?.map_io ? ? ? ? = smdk4212_map_io,
> ? ? ? ?.init_machine ? = smdk4212_machine_init,
> diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
> index cec2afa..525b042 100644
> --- a/arch/arm/mach-exynos4/mach-smdkv310.c
> +++ b/arch/arm/mach-exynos4/mach-smdkv310.c
> @@ -43,6 +43,8 @@
>
> ?#include <mach/map.h>
>
> +#include "core.h"
> +
> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
> ?#define SMDKV310_UCON_DEFAULT ?(S3C2410_UCON_TXILEVEL | ? ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? S3C2410_UCON_RXILEVEL | ? ? ? ?\
> @@ -373,6 +375,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
> ? ? ? ?/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
> ? ? ? ?/* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
> ? ? ? ?.atag_offset ? ?= 0x100,
> + ? ? ? .soc ? ? ? ? ? ?= &exynos4_soc_desc,
> ? ? ? ?.init_irq ? ? ? = exynos4_init_irq,
> ? ? ? ?.map_io ? ? ? ? = smdkv310_map_io,
> ? ? ? ?.init_machine ? = smdkv310_machine_init,
> @@ -383,6 +386,7 @@ MACHINE_END
> ?MACHINE_START(SMDKC210, "SMDKC210")
> ? ? ? ?/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
> ? ? ? ?.atag_offset ? ?= 0x100,
> + ? ? ? .soc ? ? ? ? ? ?= &exynos4_soc_desc,
> ? ? ? ?.init_irq ? ? ? = exynos4_init_irq,
> ? ? ? ?.map_io ? ? ? ? = smdkv310_map_io,
> ? ? ? ?.init_machine ? = smdkv310_machine_init,
> diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
> index a023faa..0c94673 100644
> --- a/arch/arm/mach-exynos4/mach-universal_c210.c
> +++ b/arch/arm/mach-exynos4/mach-universal_c210.c
> @@ -47,6 +47,8 @@
> ?#include <media/s5p_fimc.h>
> ?#include <media/m5mols.h>
>
> +#include "core.h"
> +
> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
> ?#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | ? ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? S3C2410_UCON_RXILEVEL | ? ? ? ?\
> @@ -1061,6 +1063,7 @@ static void __init universal_machine_init(void)
> ?MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
> ? ? ? ?/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
> ? ? ? ?.atag_offset ? ?= 0x100,
> + ? ? ? .soc ? ? ? ? ? ?= &exynos4_soc_desc,
> ? ? ? ?.init_irq ? ? ? = exynos4_init_irq,
> ? ? ? ?.map_io ? ? ? ? = universal_map_io,
> ? ? ? ?.init_machine ? = universal_machine_init,
> diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
> index 500453f..1f419fa 100644
> --- a/arch/arm/mach-exynos4/platsmp.c
> +++ b/arch/arm/mach-exynos4/platsmp.c
> @@ -32,6 +32,8 @@
>
> ?#include <plat/cpu.h>
>
> +#include "core.h"
> +
> ?extern void exynos4_secondary_startup(void);
>
> ?#define CPU1_BOOT_REG ? ? ? ? ?(samsung_rev() == EXYNOS4210_REV_1_1 ? \
> @@ -89,7 +91,7 @@ static void __cpuinit exynos4_gic_secondary_init(void)
> ? ? ? ?__raw_writel(1, cpu_base + GIC_CPU_CTRL);
> ?}
>
> -void __cpuinit platform_secondary_init(unsigned int cpu)
> +static void __cpuinit exynos4_secondary_init(unsigned int cpu)
> ?{
> ? ? ? ?/*
> ? ? ? ? * if any interrupts are already enabled for the primary
> @@ -113,7 +115,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
> ? ? ? ?set_cpu_online(cpu, true);
> ?}
>
> -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> +static int __cpuinit exynos4_boot_secondary(unsigned int cpu, struct task_struct *idle)
> ?{
> ? ? ? ?unsigned long timeout;
>
> @@ -188,7 +190,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> ?* which may be present or become present in the system.
> ?*/
>
> -void __init smp_init_cpus(void)
> +static void __init exynos4_smp_init_cpus(void)
> ?{
> ? ? ? ?void __iomem *scu_base = scu_base_addr();
> ? ? ? ?unsigned int i, ncores;
> @@ -210,7 +212,7 @@ void __init smp_init_cpus(void)
> ? ? ? ?set_smp_cross_call(gic_raise_softirq);
> ?}
>
> -void __init platform_smp_prepare_cpus(unsigned int max_cpus)
> +static void __init exynos4_smp_prepare_cpus(unsigned int max_cpus)
> ?{
>
> ? ? ? ?scu_enable(scu_base_addr());
> @@ -224,3 +226,18 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
> ? ? ? ?__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
> ? ? ? ? ? ? ? ? ? ? ? ?CPU1_BOOT_REG);
> ?}
> +
> +struct arm_soc_smp_init_ops exynos4_soc_smp_init_ops __initdata = {
> + ? ? ? .smp_init_cpus ? ? ? ? ?= exynos4_smp_init_cpus,
> + ? ? ? .smp_prepare_cpus ? ? ? = exynos4_smp_prepare_cpus,
> +};
> +
> +struct arm_soc_smp_ops exynos4_soc_smp_ops __initdata = {
> + ? ? ? .smp_secondary_init ? ? = exynos4_secondary_init,
> + ? ? ? .smp_boot_secondary ? ? = exynos4_boot_secondary,
> +#ifdef CONFIG_HOTPLUG_CPU
> + ? ? ? .cpu_kill ? ? ? ? ? ? ? = exynos4_cpu_kill,
> + ? ? ? .cpu_die ? ? ? ? ? ? ? ?= exynos4_cpu_die,
> + ? ? ? .cpu_disable ? ? ? ? ? ?= exynos4_cpu_disable,
> +#endif
> +};
> --
> 1.7.0.4
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply
* [PATCH 18/30] omap-usb: automatically select MFD_OMAP_USB_HOST
From: Samuel Ortiz @ 2011-10-04 11:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317566760-25681-19-git-send-email-arnd@arndb.de>
Hi Arnd,
On Sun, Oct 02, 2011 at 04:45:48PM +0200, Arnd Bergmann wrote:
> The ehci-omap and ohci-omap3 drivers both depend on the
> omap-usb-host MFD support driver. By default, this is
> automatically turned on, but it is possible to disable
> the driver, which results in a link error.
I don't see the Kconfig entry for e.g. the ohci-omap3 driver, but shouldn't
the dependency be handled there ?
If ohci-omap3 depends on omap-usb-host, then we should not be able to disable
the latter while the former is selected.
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* [PATCH 22/30] mfd: build twl6030 only on omap2
From: Samuel Ortiz @ 2011-10-04 10:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317566760-25681-23-git-send-email-arnd@arndb.de>
Hi Arnd,
On Sun, Oct 02, 2011 at 04:45:52PM +0200, Arnd Bergmann wrote:
> We can only have one pwm driver built into the kernel,
I seem to remember that Bill Gatliff was working on a PWM subsystem that would
get rid of the current pwm.h ugliness. Do we have any updates on this one ?
The patch below looks like a hack to me, trying to work around the current
lack of such subsystem.
Cheers,
Samuel.
> so make sure
> that this one is only available on omap2 to avoid conflicts with
> pwm drivers of other platforms.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Cc: Samuel Ortiz <sameo@linux.intel.com>
> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
> Cc: Balaji T K <balajitk@ti.com>
> Cc: Hemanth V <hemanthv@ti.com>
> ---
> drivers/mfd/Kconfig | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 48cce35..26bebe8 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -256,8 +256,8 @@ config MFD_TWL4030_AUDIO
> default n
>
> config TWL6030_PWM
> - tristate "TWL6030 PWM (Pulse Width Modulator) Support"
> - depends on TWL4030_CORE
> + bool "TWL6030 PWM (Pulse Width Modulator) Support"
> + depends on TWL4030_CORE && ARCH_OMAP2
> select HAVE_PWM
> default n
> help
> --
> 1.7.5.4
>
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* [PATCH] arm: mm: Fix infinite looping issue
From: Girish K S @ 2011-10-04 10:38 UTC (permalink / raw)
To: linux-arm-kernel
This patch fixes the problem of infinite looping while booting.
The bne instruction expects the z flag to be set to break the loop.
The (mov r1, r1, lsr #1) doesn't behave in the expected way. If
replaced with the movs instruction then the execution will exit
the loop.
Signed-off-by: Girish K S <girish.shivananjappa@linaro.org>
---
arch/arm/mm/proc-arm740.S | 4 ++--
arch/arm/mm/proc-arm940.S | 4 ++--
arch/arm/mm/proc-arm946.S | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 4506be3..9284f10 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -77,7 +77,7 @@ __arm740_setup:
ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
mov r2, #10 @ 11 is the minimum (4KB)
1: add r2, r2, #1 @ area size *= 2
- mov r1, r1, lsr #1
+ movs r1, r1, lsr #1 @ set zero bit if r1=0
bne 1b @ count not zero r-shift
orr r0, r0, r2, lsl #1 @ the area register value
orr r0, r0, #1 @ set enable bit
@@ -87,7 +87,7 @@ __arm740_setup:
ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
mov r2, #10 @ 11 is the minimum (4KB)
1: add r2, r2, #1 @ area size *= 2
- mov r1, r1, lsr #1
+ movs r1, r1, lsr #1 @ set zero bit if r1=0
bne 1b @ count not zero r-shift
orr r0, r0, r2, lsl #1 @ the area register value
orr r0, r0, #1 @ set enable bit
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index ac750d5..e639034 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -296,7 +296,7 @@ __arm940_setup:
ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
mov r2, #10 @ 11 is the minimum (4KB)
1: add r2, r2, #1 @ area size *= 2
- mov r1, r1, lsr #1
+ movs r1, r1, lsr #1 @ set zero bit if r1=0
bne 1b @ count not zero r-shift
orr r0, r0, r2, lsl #1 @ the area register value
orr r0, r0, #1 @ set enable bit
@@ -307,7 +307,7 @@ __arm940_setup:
ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
mov r2, #10 @ 11 is the minimum (4KB)
1: add r2, r2, #1 @ area size *= 2
- mov r1, r1, lsr #1
+ movs r1, r1, lsr #1 @ set zero bit if r1=0
bne 1b @ count not zero r-shift
orr r0, r0, r2, lsl #1 @ the area register value
orr r0, r0, #1 @ set enable bit
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 683af3a..731388a 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -341,7 +341,7 @@ __arm946_setup:
ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
mov r2, #10 @ 11 is the minimum (4KB)
1: add r2, r2, #1 @ area size *= 2
- mov r1, r1, lsr #1
+ movs r1, r1, lsr #1 @ set zero bit if r1=0
bne 1b @ count not zero r-shift
orr r0, r0, r2, lsl #1 @ the region register value
orr r0, r0, #1 @ set enable bit
@@ -351,7 +351,7 @@ __arm946_setup:
ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
mov r2, #10 @ 11 is the minimum (4KB)
1: add r2, r2, #1 @ area size *= 2
- mov r1, r1, lsr #1
+ movs r1, r1, lsr #1 @ set zero bit if r1=0
bne 1b @ count not zero r-shift
orr r0, r0, r2, lsl #1 @ the region register value
orr r0, r0, #1 @ set enable bit
--
1.7.1
^ permalink raw reply related
* [PATCH v4 02/10] ARM: SoC: Add per SoC SMP and CPU hotplug operations
From: Kyungmin Park @ 2011-10-04 10:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAH9JG2UpQqy8w8qbze9KHBAkSrP_5jAeTTg9obb63F9Kz=fRqA@mail.gmail.com>
On Tue, Oct 4, 2011 at 7:30 PM, Kyungmin Park <kmpark@infradead.org> wrote:
> On Tue, Oct 4, 2011 at 2:35 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> Populate the SoC descriptor structure with the SMP and CPU hotplug
>> operations. To allow the kernel to continue building, the platform
>> hooks are defined as weak symbols which are overrided by the
>> platform code. Once all platforms are converted, the "weak" attribute
>> will be removed and the function made static.
>>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Nicolas Pitre <nico@fluxnic.net>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>> ?arch/arm/include/asm/soc.h | ? 48 ++++++++++++++++++++++++++++++++++++++++++-
>> ?arch/arm/kernel/setup.c ? ?| ? 29 ++++++++++++++++++++++---
>> ?arch/arm/kernel/smp.c ? ? ?| ? 47 +++++++++++++++++++++++++++++++++++++++++++
>> ?3 files changed, 118 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/soc.h b/arch/arm/include/asm/soc.h
>> index ce92784..f1dd657 100644
>> --- a/arch/arm/include/asm/soc.h
>> +++ b/arch/arm/include/asm/soc.h
>> @@ -12,10 +12,54 @@
>> ?#ifndef __ASM_ARM_SOC_H
>> ?#define __ASM_ARM_SOC_H
>>
>> +struct task_struct;
>> +
>> +struct arm_soc_smp_init_ops {
>> + ? ? ? /*
>> + ? ? ? ?* Setup the set of possible CPUs (via set_cpu_possible)
>> + ? ? ? ?*/
>> + ? ? ? void (*smp_init_cpus)(void);
>> + ? ? ? /*
>> + ? ? ? ?* Initialize cpu_possible map, and enable coherency
>> + ? ? ? ?*/
>> + ? ? ? void (*smp_prepare_cpus)(unsigned int max_cpus);
>> +};
>> +
>> +struct arm_soc_smp_ops {
>> + ? ? ? /*
>> + ? ? ? ?* Perform platform specific initialisation of the specified CPU.
>> + ? ? ? ?*/
>> + ? ? ? void (*smp_secondary_init)(unsigned int cpu);
>> + ? ? ? /*
>> + ? ? ? ?* Boot a secondary CPU, and assign it the specified idle task.
>> + ? ? ? ?* This also gives us the initial stack to use for this CPU.
>> + ? ? ? ?*/
>> + ? ? ? int ?(*smp_boot_secondary)(unsigned int cpu, struct task_struct *idle);
>> +#ifdef CONFIG_HOTPLUG_CPU
>> + ? ? ? int ?(*cpu_kill)(unsigned int cpu);
>> + ? ? ? void (*cpu_die)(unsigned int cpu);
>> + ? ? ? int ?(*cpu_disable)(unsigned int cpu);
>> +#endif
>> +};
>> +
>> ?struct arm_soc_desc {
>> - ? ? ? const char ? ? ? ? ? ? ?*name;
>> + ? ? ? const char ? ? ? ? ? ? ? ? ? ? ?*name;
>> +#ifdef CONFIG_SMP
>> + ? ? ? struct arm_soc_smp_init_ops ? ? *smp_init_ops;
>> + ? ? ? struct arm_soc_smp_ops ? ? ? ? ?*smp_ops;
>> +#endif
>> ?};
>>
>> -extern const struct arm_soc_desc ? ? ? *soc_desc;
>> +#ifdef CONFIG_SMP
>> +#define soc_smp_init_ops(ops) ?.smp_init_ops = &(ops),
>> +#define soc_smp_ops(ops) ? ? ? .smp_ops = &(ops),
>> +#else
>> +#define soc_smp_init_ops(ops) ?/* empty */
>> +#define soc_smp_ops(ops) ? ? ? /* empty */
>> +#endif
>> +
>> +extern const struct arm_soc_desc ? ? ? ? ? ? ? *soc_desc;
>> +extern const struct arm_soc_smp_init_ops ? ? ? *soc_smp_init_ops;
>> +extern const struct arm_soc_smp_ops ? ? ? ? ? ?*soc_smp_ops;
>>
>> ?#endif /* __ASM_ARM_SOC_H */
>> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
>> index 34ffb2e..351ae18 100644
>> --- a/arch/arm/kernel/setup.c
>> +++ b/arch/arm/kernel/setup.c
>> @@ -141,8 +141,12 @@ static const char *cpu_name;
>> ?static const char *machine_name;
>> ?static char __initdata cmd_line[COMMAND_LINE_SIZE];
>> ?struct machine_desc *machine_desc __initdata;
>> -const struct arm_soc_desc *soc_desc;
>> -static struct arm_soc_desc __soc_desc __read_mostly;
>> +const struct arm_soc_desc *soc_desc __initdata;
>> +#ifdef CONFIG_SMP
>> +const struct arm_soc_smp_init_ops *soc_smp_init_ops ?__initdata;
>> +const struct arm_soc_smp_ops *soc_smp_ops ?__cpuinitdata;
>> +static struct arm_soc_smp_ops __soc_smp_ops __cpuinitdata;
>> +#endif
>>
>> ?static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
>> ?static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
>> @@ -917,11 +921,28 @@ void __init setup_arch(char **cmdline_p)
>> ? ? ? ?machine_desc = mdesc;
>> ? ? ? ?machine_name = mdesc->name;
>> ? ? ? ?if (mdesc->soc) {
>> - ? ? ? ? ? ? ? __soc_desc = *mdesc->soc;
>> - ? ? ? ? ? ? ? soc_desc = &__soc_desc;
>> + ? ? ? ? ? ? ? soc_desc = mdesc->soc;
>> ? ? ? ? ? ? ? ?pr_info("SoC: %s\n", soc_desc->name);
>> ? ? ? ?} else
>> ? ? ? ? ? ? ? ?soc_desc = NULL;
>> +#ifdef CONFIG_SMP
>> + ? ? ? if (soc_desc && soc_desc->smp_init_ops)
>> + ? ? ? ? ? ? ? soc_smp_init_ops = soc_desc->smp_init_ops;
>> + ? ? ? else
>> + ? ? ? ? ? ? ? soc_smp_ops = NULL;
> It should be "soc_smp_init_ops = NULL;"
>
> Thank you,
> Kyungmin Park
>> +
>> + ? ? ? /*
>> + ? ? ? ?* Warning: we're copying an __initdata structure into a
>> + ? ? ? ?* __cpuinitdata structure. We *know* it is valid because only
>> + ? ? ? ?* __cpuinit (or more persistant) functions should be pointed
>> + ? ? ? ?* to by soc_smp_ops. Still, this is borderline ugly.
>> + ? ? ? ?*/
>> + ? ? ? if (soc_desc && soc_desc->smp_ops) {
>> + ? ? ? ? ? ? ? __soc_smp_ops = *soc_desc->smp_ops;
>> + ? ? ? ? ? ? ? soc_smp_ops = &__soc_smp_ops;
>> + ? ? ? } else
>> + ? ? ? ? ? ? ? soc_smp_ops = NULL;
>> +#endif
>>
>> ? ? ? ?if (mdesc->soft_reboot)
>> ? ? ? ? ? ? ? ?reboot_setup("s");
>> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
>> index 8bb30c2..e08d2e8 100644
>> --- a/arch/arm/kernel/smp.c
>> +++ b/arch/arm/kernel/smp.c
>> @@ -28,6 +28,7 @@
>> ?#include <linux/completion.h>
>>
>> ?#include <linux/atomic.h>
>> +#include <asm/soc.h>
>> ?#include <asm/cacheflush.h>
>> ?#include <asm/cpu.h>
>> ?#include <asm/cputype.h>
>> @@ -155,9 +156,55 @@ int __cpuinit __cpu_up(unsigned int cpu)
>> ? ? ? ?return ret;
>> ?}
>>
>> +/* SoC helpers */
>> +void __attribute__((weak)) __init smp_init_cpus(void)
>> +{
>> + ? ? ? if (soc_smp_init_ops && soc_smp_init_ops->smp_init_cpus)
>> + ? ? ? ? ? ? ? soc_smp_init_ops->smp_init_cpus();
>> +}
>> +
>> +void __attribute__((weak)) __init platform_smp_prepare_cpus(unsigned int max_cpus)
>> +{
>> + ? ? ? if (soc_smp_ops && soc_smp_init_ops->smp_prepare_cpus)
>> + ? ? ? ? ? ? ? soc_smp_init_ops->smp_prepare_cpus(max_cpus);
>> +}
One more, if (soc_smp_init_ops && ...)
>> +
>> +void __attribute__((weak)) __cpuinit platform_secondary_init(unsigned int cpu)
>> +{
>> + ? ? ? if (soc_smp_ops && soc_smp_ops->smp_secondary_init)
>> + ? ? ? ? ? ? ? soc_smp_ops->smp_secondary_init(cpu);
>> +}
>> +
>> +int __attribute__((weak)) __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
>> +{
>> + ? ? ? if (soc_smp_ops && soc_smp_ops->smp_boot_secondary)
>> + ? ? ? ? ? ? ? return soc_smp_ops->smp_boot_secondary(cpu, idle);
>> + ? ? ? return -ENOSYS;
>> +}
>> +
>> ?#ifdef CONFIG_HOTPLUG_CPU
>> ?static void percpu_timer_stop(void);
>>
>> +int __attribute__((weak)) __cpuinit platform_cpu_kill(unsigned int cpu)
>> +{
>> + ? ? ? if (soc_smp_ops && soc_smp_ops->cpu_kill)
>> + ? ? ? ? ? ? ? return soc_smp_ops->cpu_kill(cpu);
>> + ? ? ? return 0;
>> +}
>> +
>> +void __attribute__((weak)) __cpuinit platform_cpu_die(unsigned int cpu)
>> +{
>> + ? ? ? if (soc_smp_ops && soc_smp_ops->cpu_die)
>> + ? ? ? ? ? ? ? soc_smp_ops->cpu_die(cpu);
>> +}
>> +
>> +int __attribute__((weak)) __cpuinit platform_cpu_disable(unsigned int cpu)
>> +{
>> + ? ? ? if (soc_smp_ops && soc_smp_ops->cpu_disable)
>> + ? ? ? ? ? ? ? return soc_smp_ops->cpu_disable(cpu);
>> + ? ? ? return -EPERM;
>> +}
>> +
>> ?/*
>> ?* __cpu_disable runs on the processor to be shutdown.
>> ?*/
>> --
>> 1.7.0.4
>>
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>
^ permalink raw reply
* [PATCH v4 02/10] ARM: SoC: Add per SoC SMP and CPU hotplug operations
From: Kyungmin Park @ 2011-10-04 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317663356-5114-3-git-send-email-marc.zyngier@arm.com>
On Tue, Oct 4, 2011 at 2:35 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> Populate the SoC descriptor structure with the SMP and CPU hotplug
> operations. To allow the kernel to continue building, the platform
> hooks are defined as weak symbols which are overrided by the
> platform code. Once all platforms are converted, the "weak" attribute
> will be removed and the function made static.
>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Nicolas Pitre <nico@fluxnic.net>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> ?arch/arm/include/asm/soc.h | ? 48 ++++++++++++++++++++++++++++++++++++++++++-
> ?arch/arm/kernel/setup.c ? ?| ? 29 ++++++++++++++++++++++---
> ?arch/arm/kernel/smp.c ? ? ?| ? 47 +++++++++++++++++++++++++++++++++++++++++++
> ?3 files changed, 118 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/include/asm/soc.h b/arch/arm/include/asm/soc.h
> index ce92784..f1dd657 100644
> --- a/arch/arm/include/asm/soc.h
> +++ b/arch/arm/include/asm/soc.h
> @@ -12,10 +12,54 @@
> ?#ifndef __ASM_ARM_SOC_H
> ?#define __ASM_ARM_SOC_H
>
> +struct task_struct;
> +
> +struct arm_soc_smp_init_ops {
> + ? ? ? /*
> + ? ? ? ?* Setup the set of possible CPUs (via set_cpu_possible)
> + ? ? ? ?*/
> + ? ? ? void (*smp_init_cpus)(void);
> + ? ? ? /*
> + ? ? ? ?* Initialize cpu_possible map, and enable coherency
> + ? ? ? ?*/
> + ? ? ? void (*smp_prepare_cpus)(unsigned int max_cpus);
> +};
> +
> +struct arm_soc_smp_ops {
> + ? ? ? /*
> + ? ? ? ?* Perform platform specific initialisation of the specified CPU.
> + ? ? ? ?*/
> + ? ? ? void (*smp_secondary_init)(unsigned int cpu);
> + ? ? ? /*
> + ? ? ? ?* Boot a secondary CPU, and assign it the specified idle task.
> + ? ? ? ?* This also gives us the initial stack to use for this CPU.
> + ? ? ? ?*/
> + ? ? ? int ?(*smp_boot_secondary)(unsigned int cpu, struct task_struct *idle);
> +#ifdef CONFIG_HOTPLUG_CPU
> + ? ? ? int ?(*cpu_kill)(unsigned int cpu);
> + ? ? ? void (*cpu_die)(unsigned int cpu);
> + ? ? ? int ?(*cpu_disable)(unsigned int cpu);
> +#endif
> +};
> +
> ?struct arm_soc_desc {
> - ? ? ? const char ? ? ? ? ? ? ?*name;
> + ? ? ? const char ? ? ? ? ? ? ? ? ? ? ?*name;
> +#ifdef CONFIG_SMP
> + ? ? ? struct arm_soc_smp_init_ops ? ? *smp_init_ops;
> + ? ? ? struct arm_soc_smp_ops ? ? ? ? ?*smp_ops;
> +#endif
> ?};
>
> -extern const struct arm_soc_desc ? ? ? *soc_desc;
> +#ifdef CONFIG_SMP
> +#define soc_smp_init_ops(ops) ?.smp_init_ops = &(ops),
> +#define soc_smp_ops(ops) ? ? ? .smp_ops = &(ops),
> +#else
> +#define soc_smp_init_ops(ops) ?/* empty */
> +#define soc_smp_ops(ops) ? ? ? /* empty */
> +#endif
> +
> +extern const struct arm_soc_desc ? ? ? ? ? ? ? *soc_desc;
> +extern const struct arm_soc_smp_init_ops ? ? ? *soc_smp_init_ops;
> +extern const struct arm_soc_smp_ops ? ? ? ? ? ?*soc_smp_ops;
>
> ?#endif /* __ASM_ARM_SOC_H */
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index 34ffb2e..351ae18 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -141,8 +141,12 @@ static const char *cpu_name;
> ?static const char *machine_name;
> ?static char __initdata cmd_line[COMMAND_LINE_SIZE];
> ?struct machine_desc *machine_desc __initdata;
> -const struct arm_soc_desc *soc_desc;
> -static struct arm_soc_desc __soc_desc __read_mostly;
> +const struct arm_soc_desc *soc_desc __initdata;
> +#ifdef CONFIG_SMP
> +const struct arm_soc_smp_init_ops *soc_smp_init_ops ?__initdata;
> +const struct arm_soc_smp_ops *soc_smp_ops ?__cpuinitdata;
> +static struct arm_soc_smp_ops __soc_smp_ops __cpuinitdata;
> +#endif
>
> ?static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
> ?static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
> @@ -917,11 +921,28 @@ void __init setup_arch(char **cmdline_p)
> ? ? ? ?machine_desc = mdesc;
> ? ? ? ?machine_name = mdesc->name;
> ? ? ? ?if (mdesc->soc) {
> - ? ? ? ? ? ? ? __soc_desc = *mdesc->soc;
> - ? ? ? ? ? ? ? soc_desc = &__soc_desc;
> + ? ? ? ? ? ? ? soc_desc = mdesc->soc;
> ? ? ? ? ? ? ? ?pr_info("SoC: %s\n", soc_desc->name);
> ? ? ? ?} else
> ? ? ? ? ? ? ? ?soc_desc = NULL;
> +#ifdef CONFIG_SMP
> + ? ? ? if (soc_desc && soc_desc->smp_init_ops)
> + ? ? ? ? ? ? ? soc_smp_init_ops = soc_desc->smp_init_ops;
> + ? ? ? else
> + ? ? ? ? ? ? ? soc_smp_ops = NULL;
It should be "soc_smp_init_ops = NULL;"
Thank you,
Kyungmin Park
> +
> + ? ? ? /*
> + ? ? ? ?* Warning: we're copying an __initdata structure into a
> + ? ? ? ?* __cpuinitdata structure. We *know* it is valid because only
> + ? ? ? ?* __cpuinit (or more persistant) functions should be pointed
> + ? ? ? ?* to by soc_smp_ops. Still, this is borderline ugly.
> + ? ? ? ?*/
> + ? ? ? if (soc_desc && soc_desc->smp_ops) {
> + ? ? ? ? ? ? ? __soc_smp_ops = *soc_desc->smp_ops;
> + ? ? ? ? ? ? ? soc_smp_ops = &__soc_smp_ops;
> + ? ? ? } else
> + ? ? ? ? ? ? ? soc_smp_ops = NULL;
> +#endif
>
> ? ? ? ?if (mdesc->soft_reboot)
> ? ? ? ? ? ? ? ?reboot_setup("s");
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index 8bb30c2..e08d2e8 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -28,6 +28,7 @@
> ?#include <linux/completion.h>
>
> ?#include <linux/atomic.h>
> +#include <asm/soc.h>
> ?#include <asm/cacheflush.h>
> ?#include <asm/cpu.h>
> ?#include <asm/cputype.h>
> @@ -155,9 +156,55 @@ int __cpuinit __cpu_up(unsigned int cpu)
> ? ? ? ?return ret;
> ?}
>
> +/* SoC helpers */
> +void __attribute__((weak)) __init smp_init_cpus(void)
> +{
> + ? ? ? if (soc_smp_init_ops && soc_smp_init_ops->smp_init_cpus)
> + ? ? ? ? ? ? ? soc_smp_init_ops->smp_init_cpus();
> +}
> +
> +void __attribute__((weak)) __init platform_smp_prepare_cpus(unsigned int max_cpus)
> +{
> + ? ? ? if (soc_smp_ops && soc_smp_init_ops->smp_prepare_cpus)
> + ? ? ? ? ? ? ? soc_smp_init_ops->smp_prepare_cpus(max_cpus);
> +}
> +
> +void __attribute__((weak)) __cpuinit platform_secondary_init(unsigned int cpu)
> +{
> + ? ? ? if (soc_smp_ops && soc_smp_ops->smp_secondary_init)
> + ? ? ? ? ? ? ? soc_smp_ops->smp_secondary_init(cpu);
> +}
> +
> +int __attribute__((weak)) __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> + ? ? ? if (soc_smp_ops && soc_smp_ops->smp_boot_secondary)
> + ? ? ? ? ? ? ? return soc_smp_ops->smp_boot_secondary(cpu, idle);
> + ? ? ? return -ENOSYS;
> +}
> +
> ?#ifdef CONFIG_HOTPLUG_CPU
> ?static void percpu_timer_stop(void);
>
> +int __attribute__((weak)) __cpuinit platform_cpu_kill(unsigned int cpu)
> +{
> + ? ? ? if (soc_smp_ops && soc_smp_ops->cpu_kill)
> + ? ? ? ? ? ? ? return soc_smp_ops->cpu_kill(cpu);
> + ? ? ? return 0;
> +}
> +
> +void __attribute__((weak)) __cpuinit platform_cpu_die(unsigned int cpu)
> +{
> + ? ? ? if (soc_smp_ops && soc_smp_ops->cpu_die)
> + ? ? ? ? ? ? ? soc_smp_ops->cpu_die(cpu);
> +}
> +
> +int __attribute__((weak)) __cpuinit platform_cpu_disable(unsigned int cpu)
> +{
> + ? ? ? if (soc_smp_ops && soc_smp_ops->cpu_disable)
> + ? ? ? ? ? ? ? return soc_smp_ops->cpu_disable(cpu);
> + ? ? ? return -EPERM;
> +}
> +
> ?/*
> ?* __cpu_disable runs on the processor to be shutdown.
> ?*/
> --
> 1.7.0.4
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply
* [PATCH v2 0/4] Fixes to twl4030-madc and add BeagleBoard support
From: Samuel Ortiz @ 2011-10-04 10:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110928183230.GD6324@atomide.com>
Hi Tony,
On Wed, Sep 28, 2011 at 11:32:31AM -0700, Tony Lindgren wrote:
> * Samuel Ortiz <sameo@linux.intel.com> [110822 06:20]:
> > Hi Kyle,
> >
> > On Thu, Aug 11, 2011 at 10:33:11PM -0500, Kyle Manna wrote:
> > > These patches add basic functionality to the twl4030-madc driver to make
> > > it work on the BeagleBoard xM.
> > >
> > > Version 2 adds fixes per Grazvydas Ignotas and the check for NULL pointer patch.
> > >
> > > Kyle Manna (4):
> > > mfd: twl4030-madc: copy the device pointer
> > > mfd: twl4030-madc: turn on the MADC clock
> > > mfd: twl4030-madc: check for NULL pointer
> > > arm: BeagleBoard: add support for the twl4030-madc
> > Tony, are you ok with the BeagleBoard changes ?
> > The MFD ones look fine to me, I'd like to apply them.
>
> Yes sorry for the delay in replying. I acked it, maybe
> you can just copy the subject to have a proper description
> for the patch.
I actually pushed the 3 MFD patches already.
I think you can safely take the beagle one through your tree.
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* [PATCH 2/9] regulator: helper routine to extract regulator_init_data
From: Mark Brown @ 2011-10-04 10:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8A9988.3080907@ti.com>
On Tue, Oct 04, 2011 at 10:58:40AM +0530, Rajendra Nayak wrote:
> The problem is I don't know if the property in the regulator dt
> node is called "vin-supply" or "vxyz-supply" and hence I
> can parse the property based on a substring alone, which is
> "-supply" because all I know is the property name is expected
> to end with a "-supply".
This seems fairly straightforward though it will require some changes
within Linux, all we have to do is have the regulators name their
supplies.
^ permalink raw reply
* [PATCH v4 05/10] ARM: SoC: convert Tegra to SoC descriptor
From: Marc Zyngier @ 2011-10-04 9:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF173A2C6DD0@HQMAIL01.nvidia.com>
On 03/10/11 21:52, Stephen Warren wrote:
> Marc Zyngier wrote at Monday, October 03, 2011 11:36 AM:
>> Convert Tegra to use the SoC descriptor to provide its SMP
>> and CPU hotplug operations.
>
>> diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
> ...
>> +struct arm_soc_desc tegra_soc_desc __initdata = {
>> + .name = "nVIDIA Tegra",
>
> Technically, we're supposed to say "NVIDIA" not "nVIDIA", but no need to
> respin just for that! So,
Ah! I'll fix that in my tree. There's a pending respin anyway...
> Acked-by: Stephen Warren <swarren@nvidia.com>
Thanks Stephen.
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v4 04/10] ARM: SoC: convert OMAP4 to SoC descriptor
From: Marc Zyngier @ 2011-10-04 9:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMQu2gzg9B0ABaay9DSfNvfT6R3tLRW9DfgUuNphy3+y5PxH2Q@mail.gmail.com>
On 04/10/11 07:32, Shilimkar, Santosh wrote:
> Marc,
>
> On Mon, Oct 3, 2011 at 11:05 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> Convert OMAP4 to use the SoC descriptor to provide its SMP
>> and CPU hotplug operations.
>>
>> Tested on both Panda and IGEPv2 (MULTI_OMAP kernel)
>>
>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
> The changes very trivial and they look fine to me.
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Thanks Santosh.
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v4 02/10] ARM: SoC: Add per SoC SMP and CPU hotplug operations
From: Marc Zyngier @ 2011-10-04 9:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1110031508270.9106@xanadu.home>
On 03/10/11 20:12, Nicolas Pitre wrote:
> On Mon, 3 Oct 2011, Marc Zyngier wrote:
>
>> Populate the SoC descriptor structure with the SMP and CPU hotplug
>> operations. To allow the kernel to continue building, the platform
>> hooks are defined as weak symbols which are overrided by the
>> platform code. Once all platforms are converted, the "weak" attribute
>> will be removed and the function made static.
>>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Nicolas Pitre <nico@fluxnic.net>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
> [...]
>> --- a/arch/arm/kernel/setup.c
>> +++ b/arch/arm/kernel/setup.c
>> @@ -141,8 +141,12 @@ static const char *cpu_name;
>> static const char *machine_name;
>> static char __initdata cmd_line[COMMAND_LINE_SIZE];
>> struct machine_desc *machine_desc __initdata;
>> -const struct arm_soc_desc *soc_desc;
>> -static struct arm_soc_desc __soc_desc __read_mostly;
>> +const struct arm_soc_desc *soc_desc __initdata;
>
> Does the above belong in this patch?
Looks like a leftover from a previous rework. Will fix.
>> +#ifdef CONFIG_SMP
>> +const struct arm_soc_smp_init_ops *soc_smp_init_ops __initdata;
>> +const struct arm_soc_smp_ops *soc_smp_ops __cpuinitdata;
>> +static struct arm_soc_smp_ops __soc_smp_ops __cpuinitdata;
>> +#endif
>
> Maybe those could be moved in smp.c instead.
Good point, this actually makes a nice cleanup (the assignment of these
variables can also move to smp.c, making them static).
I'll repost the 3 affected patches shortly.
Thanks for reviewing,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v3 3/3] ARM: OMAP: TI814X: Create board support and enable build for TI8148 EVM
From: Pedanekar, Hemant @ 2011-10-04 9:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8ACB3C.6020401@compulab.co.il>
Igor Grinberg wrote on Tuesday, October 04, 2011 2:31 PM:
> On 10/03/11 18:45, Pedanekar, Hemant wrote:
>> Hi Igor,
>>
>> Igor Grinberg wrote on Sunday, October 02, 2011 5:38 PM:
>>
>>> Hi Hemant,
>>>
>>> On 09/29/11 04:09, Hemant Pedanekar wrote:
>>>> This patch adds minimal support and build configuration for TI8148 EVM.
>>>> Also adds support for low level debugging on UART1 console on the EVM.
>>>>
>>>> Note that existing TI8168 EVM file (board-ti8168evm.c) is updated with
>>>> machine info for TI8148 EVM and renamed as board-ti81xxevm.c.
>>>
>>> Should we really rename the existing file?
>>> Shouldn't we just stick to the name of the file submitted first?
>>> (e.g. board-ti8168evm.c) and just add the support for the new
>>> TI8148 EVM in to the existing file?
>>
>> But won't this be misleading?
>
> Misleading? For whom?
> Actually, I don't really care how you call that file.
> What I care (and I think not just me) is uniformity, so
> if we decide to rename all those files that have multiple
> boards supported in them, I'm fine with it.
>
> So pros for my proposed approach would be:
> 1) Currently, there are already board files with multiple boards
> supported in them that follow the approach and renaming them is
> really unnecessary. 2) git log will not break.
> 3) boards that cannot be named after the convention like 81xx
> but can be added to the same file will not require further renaming
> (like 82x8 - I don't really know if that will exist, just wondering).
> 4) This renaming is really what Linus likes ;)
>
> cons:
> 1) Misleading?
>
> Currently, I don't think this renaming is good for anything,
> especially that majority of the board stuff should be transformed
> to the DT descriptors.
Igor,
I agree on the DT part and also understand the "pros" you mentioned.
I can submit the v4 of patches with TI8148 EVM support added in exisitng
board-ti8168evm.c.
Tony,
Are you OK with the above approach?
Thanks.
Hemant
^ permalink raw reply
* [RFC PATCH 5/5] ARM: OMAP: TI81xx: add clockdomain data
From: Paul Walmsley @ 2011-10-04 9:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111004092947.9657.16166.stgit@dusk>
From: Hemant Pedanekar <hemantp@ti.com>
Add clockdomain data for the TI816x and TI814x SoCs.
This patch is a collaboration between Hemant Pedanekar <hemantp@ti.com>
and Paul Walmsley <paul@pwsan.com>.
---
arch/arm/mach-omap2/Makefile | 3
arch/arm/mach-omap2/clockdomain.h | 2
arch/arm/mach-omap2/clockdomains81xx_data.c | 223 +++++++++++++++++++++++++++
arch/arm/mach-omap2/io.c | 1
4 files changed, 228 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/clockdomains81xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 6962c5c..d0a66a2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -130,7 +130,8 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
clockdomain44xx.o \
clockdomains44xx_data.o
obj-$(CONFIG_SOC_OMAPTI81XX) += clockdomain.o \
- clockdomain81xx.o
+ clockdomain81xx.o \
+ clockdomains81xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 9c7c5e9..3f1b310 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -196,6 +196,8 @@ extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
+extern void __init ti81xx_clockdomains_init(void);
+
extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
new file mode 100644
index 0000000..53a95eb
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
@@ -0,0 +1,223 @@
+/*
+ * TI816X Clock Domain data.
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ * Hemant Pedanekar
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "cm.h"
+#include "prcm81xx.h"
+#include "prcm814x.h"
+#include "prcm816x.h"
+#include "prcm-regbits-81xx.h"
+
+static struct clockdomain alwon_mpu_81xx_clkdm = {
+ .name = "alwon_mpu_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI816X_CM_ALWON_MPU_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_l3_slow_814x_clkdm = {
+ .name = "alwon_l3_slow_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI814X_CM_ALWON_L3_SLOW_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_l3_med_814x_clkdm = {
+ .name = "alwon_l3_med_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI814X_CM_ALWON_L3_MED_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_l3_fast_81xx_clkdm = {
+ .name = "alwon_l3_fast_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI81XX_CM_ALWON_L3_FAST_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_ethernet_81xx_clkdm = {
+ .name = "alwon_ethernet_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI81XX_CM_ETHERNET_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mmu_81xx_clkdm = {
+ .name = "mmu_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI81XX_CM_MMU_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mmu_cfg_81xx_clkdm = {
+ .name = "mmu_cfg_clkdm",
+ .pwrdm = { .name = "alwon_pwrdm" },
+ .cm_inst = TI81XX_CM_ALWON_INST,
+ .clkdm_offs = TI81XX_CM_MMUCFG_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain active_gem_81xx_clkdm = {
+ .name = "active_gem_clkdm",
+ .pwrdm = { .name = "active_pwrdm" },
+ .cm_inst = TI81XX_CM_ACTIVE_INST,
+ .clkdm_offs = TI81XX_CM_ACTIVE_GEM_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain hdvicp_814x_clkdm = {
+ .name = "hdvicp_clkdm",
+ .pwrdm = { .name = "hdvicp_pwrdm" },
+ .cm_inst = TI814X_CM_HDVICP_INST,
+ .clkdm_offs = TI814X_CM_HDVICP_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain isp_814x_clkdm = {
+ .name = "isp_clkdm",
+ .pwrdm = { .name = "isp_pwrdm" },
+ .cm_inst = TI814X_CM_ISP_INST,
+ .clkdm_offs = TI814X_CM_ISP_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dss_814x_clkdm = {
+ .name = "dss_clkdm",
+ .pwrdm = { .name = "dss_pwrdm" },
+ .cm_inst = TI814X_CM_DSS_INST,
+ .clkdm_offs = TI814X_CM_DSS_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain sgx_81xx_clkdm = {
+ .name = "sgx_clkdm",
+ .pwrdm = { .name = "sgx_pwrdm" },
+ .cm_inst = TI81XX_CM_SGX_INST,
+ .clkdm_offs = TI81XX_CM_SGX_SGX_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_l3_slow_816x_clkdm = {
+ .name = "default_l3_slow_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_tppss_814x_clkdm = {
+ .name = "default_tppss_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI814X_CM_DEFAULT_TPPSS_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_l3_med_816x_clkdm = {
+ .name = "default_l3_med_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_ducati_814x_clkdm = {
+ .name = "default_ducati_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI814X_CM_DEFAULT_DUCATI_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_ducati_816x_clkdm = {
+ .name = "default_ducati_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_pcie_814x_clkdm = {
+ .name = "default_pcie_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI814X_CM_DEFAULT_PCI_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain default_pcie_816x_clkdm = {
+ .name = "default_pcie_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_INST,
+ .clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKSTCTRL_OFFSET,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain *clockdomains_ti81xx[] __initdata = {
+ &alwon_mpu_81xx_clkdm,
+ &alwon_l3_fast_81xx_clkdm,
+ &alwon_ethernet_81xx_clkdm,
+ &mmu_81xx_clkdm,
+ &mmu_cfg_81xx_clkdm,
+ &active_gem_81xx_clkdm,
+ &sgx_81xx_clkdm,
+ NULL,
+};
+
+static struct clockdomain *clockdomains_ti814x[] __initdata = {
+ &hdvicp_814x_clkdm,
+ &isp_814x_clkdm,
+ &dss_814x_clkdm,
+ &alwon_l3_med_814x_clkdm,
+ &alwon_l3_slow_814x_clkdm,
+ &default_tppss_814x_clkdm,
+ &default_ducati_814x_clkdm,
+ &default_pcie_814x_clkdm,
+ NULL,
+};
+
+static struct clockdomain *clockdomains_ti816x[] __initdata = {
+ &default_l3_med_816x_clkdm,
+ &default_l3_slow_816x_clkdm,
+ &default_ducati_816x_clkdm,
+ &default_pcie_816x_clkdm,
+ NULL,
+};
+
+void __init ti81xx_clockdomains_init(void)
+{
+ if (!cpu_is_ti81xx())
+ return;
+
+ clkdm_register_platform_funcs(&ti81xx_clkdm_operations);
+ clkdm_register_clkdms(clockdomains_ti81xx);
+ if (cpu_is_ti814x())
+ clkdm_register_clkdms(clockdomains_ti814x);
+ if (cpu_is_ti816x())
+ clkdm_register_clkdms(clockdomains_ti816x);
+ clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index bad2edb..2d26820 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -352,6 +352,7 @@ void __init omap2_init_common_infrastructure(void)
omap3xxx_powerdomains_init();
ti81xx_powerdomains_init();
omap3xxx_clockdomains_init();
+ ti81xx_clockdomains_init();
omap3xxx_hwmod_init();
} else if (cpu_is_omap44xx()) {
omap44xx_powerdomains_init();
^ permalink raw reply related
* [RFC PATCH 4/5] ARM: OMAP: TI81xx: add clockdomain control code
From: Paul Walmsley @ 2011-10-04 9:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111004092947.9657.16166.stgit@dusk>
Add clockdomain control code for the TI816x and TI814x SoCs.
This patch is a collaboration between Hemant Pedanekar <hemantp@ti.com>
and Paul Walmsley <paul@pwsan.com>.
---
arch/arm/mach-omap2/Makefile | 2 +
arch/arm/mach-omap2/clockdomain.h | 1
arch/arm/mach-omap2/clockdomain81xx.c | 77 +++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/prcm81xx.c | 59 +++++++++++++++++++++++++
arch/arm/mach-omap2/prcm81xx.h | 5 ++
5 files changed, 144 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/clockdomain81xx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 4f728a1..6962c5c 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -129,6 +129,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
clockdomain44xx.o \
clockdomains44xx_data.o
+obj-$(CONFIG_SOC_OMAPTI81XX) += clockdomain.o \
+ clockdomain81xx.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index f7b5860..9c7c5e9 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -202,6 +202,7 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
extern struct clkdm_ops omap2_clkdm_operations;
extern struct clkdm_ops omap3_clkdm_operations;
extern struct clkdm_ops omap4_clkdm_operations;
+extern struct clkdm_ops ti81xx_clkdm_operations;
extern struct clkdm_dep gfx_24xx_wkdeps[];
extern struct clkdm_dep dsp_24xx_wkdeps[];
diff --git a/arch/arm/mach-omap2/clockdomain81xx.c b/arch/arm/mach-omap2/clockdomain81xx.c
new file mode 100644
index 0000000..eab50f8
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain81xx.c
@@ -0,0 +1,77 @@
+/*
+ * TI81XX clockdomain control
+ *
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ * Hemant Pedanekar
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+
+#include <plat/prcm.h>
+
+#include "prcm81xx.h"
+#include "prm.h"
+#include "clockdomain.h"
+
+static int ti81xx_clkdm_sleep(struct clockdomain *clkdm)
+{
+ ti81xx_prcm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
+ return 0;
+}
+
+static int ti81xx_clkdm_wakeup(struct clockdomain *clkdm)
+{
+ ti81xx_prcm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
+ return 0;
+}
+
+static void ti81xx_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+ ti81xx_prcm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static void ti81xx_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+ ti81xx_prcm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static int ti81xx_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+ bool hwsup;
+
+ hwsup = ti81xx_prcm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+
+ if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+ ti81xx_clkdm_wakeup(clkdm);
+
+ return 0;
+}
+
+static int ti81xx_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+ bool hwsup;
+
+ hwsup = ti81xx_prcm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+
+ if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+ ti81xx_clkdm_sleep(clkdm);
+
+ return 0;
+}
+
+struct clkdm_ops ti81xx_clkdm_operations = {
+ .clkdm_sleep = ti81xx_clkdm_sleep,
+ .clkdm_wakeup = ti81xx_clkdm_wakeup,
+ .clkdm_allow_idle = ti81xx_clkdm_allow_idle,
+ .clkdm_deny_idle = ti81xx_clkdm_deny_idle,
+ .clkdm_clk_enable = ti81xx_clkdm_clk_enable,
+ .clkdm_clk_disable = ti81xx_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/prcm81xx.c b/arch/arm/mach-omap2/prcm81xx.c
index 5846969..523b594 100644
--- a/arch/arm/mach-omap2/prcm81xx.c
+++ b/arch/arm/mach-omap2/prcm81xx.c
@@ -2,6 +2,8 @@
* TI81XX PRCM register access functions
*
* Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ * Hemant Pedanekar
+ * Paul Walmsley
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -27,6 +29,9 @@
#include "prm-regbits-44xx.h"
+#include "cm-regbits-34xx.h"
+#include "cm-regbits-44xx.h"
+
/* prm_base = cm_base on TI81xx, so either is fine */
static u32 ti81xx_prcm_inst_read(u16 inst, u16 offs)
@@ -123,3 +128,57 @@ int ti81xx_prcm_pwrdm_wait_transition(u16 offs)
return (c <= PWRDM_TRANSITION_BAILOUT) ? c : -ETIMEDOUT;
}
+
+void ti81xx_prcm_clkdm_enable_hwsup(s16 inst, u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(inst, offs);
+ v &= ~OMAP4430_CLKTRCTRL_MASK;
+ v |= OMAP34XX_CLKSTCTRL_ENABLE_AUTO << OMAP4430_CLKTRCTRL_SHIFT;
+ ti81xx_prcm_inst_write(v, inst, offs);
+
+}
+
+void ti81xx_prcm_clkdm_disable_hwsup(s16 inst, u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(inst, offs);
+ v &= ~OMAP4430_CLKTRCTRL_MASK;
+ v |= OMAP34XX_CLKSTCTRL_DISABLE_AUTO << OMAP4430_CLKTRCTRL_SHIFT;
+ ti81xx_prcm_inst_write(v, inst, offs);
+}
+
+void ti81xx_prcm_clkdm_force_sleep(s16 inst, u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(inst, offs);
+ v &= ~OMAP4430_CLKTRCTRL_MASK;
+ v |= OMAP34XX_CLKSTCTRL_FORCE_SLEEP << OMAP4430_CLKTRCTRL_SHIFT;
+ ti81xx_prcm_inst_write(v, inst, offs);
+}
+
+void ti81xx_prcm_clkdm_force_wakeup(s16 inst, u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(inst, offs);
+ v &= ~OMAP4430_CLKTRCTRL_MASK;
+ v |= OMAP34XX_CLKSTCTRL_FORCE_WAKEUP << OMAP4430_CLKTRCTRL_SHIFT;
+ ti81xx_prcm_inst_write(v, inst, offs);
+}
+
+bool ti81xx_prcm_is_clkdm_in_hwsup(s16 inst, u16 offs)
+{
+ u32 v;
+ bool ret = 0;
+
+ v = ti81xx_prcm_inst_read(inst, offs);
+ v &= OMAP4430_CLKTRCTRL_MASK;
+ v >>= OMAP4430_CLKTRCTRL_SHIFT;
+ ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
+
+ return ret;
+}
diff --git a/arch/arm/mach-omap2/prcm81xx.h b/arch/arm/mach-omap2/prcm81xx.h
index e0c20b9..19a7b40 100644
--- a/arch/arm/mach-omap2/prcm81xx.h
+++ b/arch/arm/mach-omap2/prcm81xx.h
@@ -203,5 +203,10 @@ extern u8 ti81xx_prcm_pwrdm_read_logicstatest(u16 offs);
extern u8 ti81xx_prcm_pwrdm_read_mem_statest(u16 offs);
extern void ti81xx_prcm_pwrdm_set_lowpowerstatechange(u16 offs);
extern int ti81xx_prcm_pwrdm_wait_transition(u16 offs);
+extern void ti81xx_prcm_clkdm_enable_hwsup(s16 inst, u16 offs);
+extern void ti81xx_prcm_clkdm_disable_hwsup(s16 inst, u16 offs);
+extern void ti81xx_prcm_clkdm_force_sleep(s16 inst, u16 offs);
+extern void ti81xx_prcm_clkdm_force_wakeup(s16 inst, u16 offs);
+extern bool ti81xx_prcm_is_clkdm_in_hwsup(s16 inst, u16 offs);
#endif
^ permalink raw reply related
* [RFC PATCH 3/5] ARM: OMAP: TI81xx: add powerdomain data
From: Paul Walmsley @ 2011-10-04 9:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111004092947.9657.16166.stgit@dusk>
From: Hemant Pedanekar <hemantp@ti.com>
Add powerdomain data for the TI81xx family of SoCs.
This patch is a collaboration between Hemant Pedanekar <hemantp@ti.com>
and Paul Walmsley <paul@pwsan.com>.
---
arch/arm/mach-omap2/Makefile | 3 +
arch/arm/mach-omap2/io.c | 1
arch/arm/mach-omap2/powerdomain.h | 1
arch/arm/mach-omap2/powerdomain81xx_data.c | 91 ++++++++++++++++++++++++++++
4 files changed, 95 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/powerdomain81xx_data.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 292941d..4f728a1 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -113,7 +113,8 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
powerdomain44xx.o \
powerdomains44xx_data.o
obj-$(CONFIG_SOC_OMAPTI81XX) += $(powerdomain-common) \
- powerdomain81xx.o
+ powerdomain81xx.o \
+ powerdomain81xx_data.o \
# PRCM clockdomain control
obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index d59feec..bad2edb 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -350,6 +350,7 @@ void __init omap2_init_common_infrastructure(void)
omap2430_hwmod_init();
} else if (cpu_is_omap34xx()) {
omap3xxx_powerdomains_init();
+ ti81xx_powerdomains_init();
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
} else if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index b3d51f2..b9e7ab2 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -214,6 +214,7 @@ extern void omap242x_powerdomains_init(void);
extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
+extern void ti81xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomain81xx_data.c b/arch/arm/mach-omap2/powerdomain81xx_data.c
new file mode 100644
index 0000000..1b363ec
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain81xx_data.c
@@ -0,0 +1,91 @@
+/*
+ * TI81XX Power Domain data.
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ * Hemant Pedanekar
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+
+#include "powerdomain.h"
+#include "prcm81xx.h"
+#include "prcm814x.h"
+#include "prcm816x.h"
+
+static struct powerdomain alwon_814x_pwrdm = {
+ .name = "alwon_pwrdm",
+ .prcm_offs = TI814X_PRM_ALWON_INST,
+};
+
+static struct powerdomain active_81xx_pwrdm = {
+ .name = "active_pwrdm",
+ .prcm_offs = TI81XX_PRM_ACTIVE_INST,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain default_81xx_pwrdm = {
+ .name = "default_pwrdm",
+ .prcm_offs = TI81XX_PRM_DEFAULT_INST,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain hdvicp_814x_pwrdm = {
+ .name = "hdvicp_pwrdm",
+ .prcm_offs = TI814X_PRM_HDVICP_INST,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain isp_814x_pwrdm = {
+ .name = "isp_pwrdm",
+ .prcm_offs = TI814X_PRM_ISP_INST,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain dss_814x_pwrdm = {
+ .name = "dss_pwrdm",
+ .prcm_offs = TI814X_PRM_DSS_INST,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain sgx_81xx_pwrdm = {
+ .name = "sgx_pwrdm",
+ .prcm_offs = TI81XX_PRM_SGX_INST,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain *powerdomains_ti81xx[] __initdata = {
+ &active_81xx_pwrdm,
+ &default_81xx_pwrdm,
+ &sgx_81xx_pwrdm,
+ NULL
+};
+
+static struct powerdomain *powerdomains_ti814x[] __initdata = {
+ &alwon_814x_pwrdm,
+ &hdvicp_814x_pwrdm,
+ &isp_814x_pwrdm,
+ &dss_814x_pwrdm,
+ NULL
+};
+
+void __init ti81xx_powerdomains_init(void)
+{
+ if (!cpu_is_ti81xx())
+ return;
+
+ pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
+ pwrdm_register_pwrdms(powerdomains_ti81xx);
+ if (cpu_is_ti814x())
+ pwrdm_register_pwrdms(powerdomains_ti814x);
+ pwrdm_complete_init();
+}
^ permalink raw reply related
* [RFC PATCH 2/5] ARM: OMAP: TI81xx: add powerdomain code
From: Paul Walmsley @ 2011-10-04 9:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111004092947.9657.16166.stgit@dusk>
TI81xx uses a novel PRCM register layout. It most closely resembles
the OMAP4 PRCM, but with a few changes. These devices also have
limited power management functionality.
Add powerdomain & PRCM implementation code for the TI81xx chips.
This patch is a collaboration between Hemant Pedanekar <hemantp@ti.com>
and Paul Walmsley <paul@pwsan.com>.
---
arch/arm/mach-omap2/Makefile | 2 +
arch/arm/mach-omap2/powerdomain.h | 1
arch/arm/mach-omap2/powerdomain81xx.c | 81 +++++++++++++++++++++++++++
arch/arm/mach-omap2/prcm-regbits-81xx.h | 23 ++++++++
arch/arm/mach-omap2/prcm81xx.c | 93 +++++++++++++++++++++++++++++++
arch/arm/mach-omap2/prcm81xx.h | 14 +++++
6 files changed, 214 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/powerdomain81xx.c
create mode 100644 arch/arm/mach-omap2/prcm-regbits-81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9c6b185..292941d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -112,6 +112,8 @@ obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) \
obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
powerdomain44xx.o \
powerdomains44xx_data.o
+obj-$(CONFIG_SOC_OMAPTI81XX) += $(powerdomain-common) \
+ powerdomain81xx.o
# PRCM clockdomain control
obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 8febd84..b3d51f2 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -218,6 +218,7 @@ extern void omap44xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
extern struct pwrdm_ops omap4_pwrdm_operations;
+extern struct pwrdm_ops ti81xx_pwrdm_operations;
/* Common Internal functions used across OMAP rev's */
extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
diff --git a/arch/arm/mach-omap2/powerdomain81xx.c b/arch/arm/mach-omap2/powerdomain81xx.c
new file mode 100644
index 0000000..c78db22
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain81xx.c
@@ -0,0 +1,81 @@
+/*
+ * TI81xx powerdomain control
+ *
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Rajendra Nayak <rnayak@ti.com>
+ * Paul Walmsley
+ * Hemant Pedanekar
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include <plat/prcm.h>
+
+#include "powerdomain.h"
+#include "prcm81xx.h"
+
+static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+ ti81xx_prcm_pwrdm_set_powerstate(pwrdm->prcm_offs, pwrst);
+ return 0;
+}
+
+static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+ return ti81xx_prcm_pwrdm_read_powerstate(pwrdm->prcm_offs);
+}
+
+static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+ return ti81xx_prcm_pwrdm_read_powerstatest(pwrdm->prcm_offs);
+}
+
+static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+ return ti81xx_prcm_pwrdm_read_logicstatest(pwrdm->prcm_offs);
+}
+
+static int ti81xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+ return ti81xx_prcm_pwrdm_read_mem_statest(pwrdm->prcm_offs);
+}
+
+static int ti81xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+ ti81xx_prcm_pwrdm_set_lowpowerstatechange(pwrdm->prcm_offs);
+ return 0;
+}
+
+static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+ int r;
+
+ r = ti81xx_prcm_pwrdm_wait_transition(pwrdm->prcm_offs);
+ if (r == -ETIMEDOUT) {
+ pr_err("powerdomain: waited too long for powerdomain %s to complete transition\n",
+ pwrdm->name);
+ return -EAGAIN;
+ }
+
+ pr_debug("powerdomain: completed transition in %d loops\n", r);
+
+ return 0;
+}
+
+struct pwrdm_ops ti81xx_pwrdm_operations = {
+ .pwrdm_set_next_pwrst = ti81xx_pwrdm_set_next_pwrst,
+ .pwrdm_read_next_pwrst = ti81xx_pwrdm_read_next_pwrst,
+ .pwrdm_read_pwrst = ti81xx_pwrdm_read_pwrst,
+ .pwrdm_set_lowpwrstchange = ti81xx_pwrdm_set_lowpwrstchange,
+ .pwrdm_read_logic_pwrst = ti81xx_pwrdm_read_logic_pwrst,
+ .pwrdm_read_mem_pwrst = ti81xx_pwrdm_read_mem_pwrst,
+ .pwrdm_wait_transition = ti81xx_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/prcm-regbits-81xx.h b/arch/arm/mach-omap2/prcm-regbits-81xx.h
new file mode 100644
index 0000000..8eda6b0
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm-regbits-81xx.h
@@ -0,0 +1,23 @@
+/*
+ * OMAP81xx PRCM register bits
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_REGBITS_81XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_REGBITS_81XX_H
+
+/*
+ * Used by PM_ACTIVE_PWRSTST, PM_HDVICP_PWRSTST, PM_ISP_PWRSTST,
+ * PM_DSS_PWRSTST, PM_SGX_PWRSTST
+ */
+#define TI81XX_MEM_STATEST_SHIFT 4
+#define TI81XX_MEM_STATEST_MASK (0x3 << 4)
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm81xx.c b/arch/arm/mach-omap2/prcm81xx.c
index d48e5fc..5846969 100644
--- a/arch/arm/mach-omap2/prcm81xx.c
+++ b/arch/arm/mach-omap2/prcm81xx.c
@@ -17,7 +17,17 @@
#include <linux/errno.h>
#include <linux/io.h>
+#include <plat/common.h>
+
+#include "powerdomain.h"
+
#include "prcm81xx.h"
+#include "prcm-regbits-81xx.h"
+#include "prm.h"
+
+#include "prm-regbits-44xx.h"
+
+/* prm_base = cm_base on TI81xx, so either is fine */
static u32 ti81xx_prcm_inst_read(u16 inst, u16 offs)
{
@@ -29,4 +39,87 @@ static void ti81xx_prcm_inst_write(u32 v, u16 inst, u16 offs)
__raw_writel(v, prm_base + inst + offs);
}
+void ti81xx_prcm_pwrdm_set_powerstate(u16 offs, u8 pwrst)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(offs, TI81XX_PM_PWRSTCTRL_OFFSET);
+ v &= ~OMAP_POWERSTATE_MASK;
+ v |= pwrst << OMAP_POWERSTATE_SHIFT;
+ ti81xx_prcm_inst_write(v, offs, TI81XX_PM_PWRSTCTRL_OFFSET);
+}
+
+u8 ti81xx_prcm_pwrdm_read_powerstate(u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(offs, TI81XX_PM_PWRSTCTRL_OFFSET);
+ v &= OMAP_POWERSTATE_MASK;
+ v >>= OMAP_POWERSTATE_SHIFT;
+
+ return v;
+}
+
+u8 ti81xx_prcm_pwrdm_read_powerstatest(u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(offs, TI81XX_PM_PWRSTST_OFFSET);
+ v &= OMAP_POWERSTATEST_MASK;
+ v >>= OMAP_POWERSTATEST_SHIFT;
+
+ return v;
+}
+
+u8 ti81xx_prcm_pwrdm_read_logicstatest(u16 offs)
+{
+ u32 v;
+ v = ti81xx_prcm_inst_read(offs, TI81XX_PM_PWRSTCTRL_OFFSET);
+ v &= OMAP4430_LOGICSTATEST_MASK;
+ v >>= OMAP4430_LOGICSTATEST_SHIFT;
+
+ return v;
+}
+
+u8 ti81xx_prcm_pwrdm_read_mem_statest(u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(offs, TI81XX_PM_PWRSTST_OFFSET);
+ v &= TI81XX_MEM_STATEST_MASK;
+ v >>= TI81XX_MEM_STATEST_SHIFT;
+
+ return v;
+}
+
+void ti81xx_prcm_pwrdm_set_lowpowerstatechange(u16 offs)
+{
+ u32 v;
+
+ v = ti81xx_prcm_inst_read(offs, TI81XX_PM_PWRSTCTRL_OFFSET);
+ v &= ~OMAP4430_LOWPOWERSTATECHANGE_MASK;
+ v |= 1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT;
+ ti81xx_prcm_inst_write(v, offs, TI81XX_PM_PWRSTCTRL_OFFSET);
+}
+
+int ti81xx_prcm_pwrdm_wait_transition(u16 offs)
+{
+ u32 c = 0;
+
+ /*
+ * REVISIT: pwrdm_wait_transition() may be better implemented
+ * via a callback and a periodic timer check -- how long do we expect
+ * powerdomain transitions to take?
+ */
+
+ omap_test_timeout((ti81xx_prcm_inst_read(offs,
+ TI81XX_PM_PWRSTST_OFFSET) &
+ OMAP_INTRANSITION_MASK),
+ PWRDM_TRANSITION_BAILOUT, c);
+
+ if (c > INT_MAX)
+ c = INT_MAX;
+
+ return (c <= PWRDM_TRANSITION_BAILOUT) ? c : -ETIMEDOUT;
+}
diff --git a/arch/arm/mach-omap2/prcm81xx.h b/arch/arm/mach-omap2/prcm81xx.h
index fd0a174..e0c20b9 100644
--- a/arch/arm/mach-omap2/prcm81xx.h
+++ b/arch/arm/mach-omap2/prcm81xx.h
@@ -188,6 +188,20 @@
#define TI81XX_CM_ALWON_SR_1_CLKCTRL_OFFSET 0x020C
#define TI81XX_CM_ALWON_SR_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x020C)
+/*
+ * Register offset aliases (for clearer code,@least in theory)
+ */
+#define TI81XX_PM_PWRSTCTRL_OFFSET TI81XX_PRM_ACTIVE_PM_PWRSTCTRL_OFFSET
+#define TI81XX_PM_PWRSTST_OFFSET TI81XX_PRM_ACTIVE_PM_PWRSTST_OFFSET
+
/* Function prototypes */
+extern void ti81xx_prcm_pwrdm_set_powerstate(u16 offs, u8 pwrst);
+extern u8 ti81xx_prcm_pwrdm_read_powerstate(u16 offs);
+extern u8 ti81xx_prcm_pwrdm_read_powerstatest(u16 offs);
+extern u8 ti81xx_prcm_pwrdm_read_logicstatest(u16 offs);
+extern u8 ti81xx_prcm_pwrdm_read_mem_statest(u16 offs);
+extern void ti81xx_prcm_pwrdm_set_lowpowerstatechange(u16 offs);
+extern int ti81xx_prcm_pwrdm_wait_transition(u16 offs);
+
#endif
^ permalink raw reply related
* [RFC PATCH 1/5] ARM: OMAP: TI81XX: prcm: Add module and register offsets
From: Paul Walmsley @ 2011-10-04 9:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111004092947.9657.16166.stgit@dusk>
From: Hemant Pedanekar <hemantp@ti.com>
This patch adds some of the PRCM register offsets for the TI814X and
TI816X devices as required for the clockdomain, powerdomain, clock, and
hwmod data.
This patch is a collaboration between Hemant Pedanekar <hemantp@ti.com>
and Paul Walmsley <paul@pwsan.com>.
---
arch/arm/mach-omap2/Makefile | 1
arch/arm/mach-omap2/prcm814x.h | 62 +++++++++++++
arch/arm/mach-omap2/prcm816x.h | 186 +++++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/prcm81xx.c | 32 +++++++
arch/arm/mach-omap2/prcm81xx.h | 193 ++++++++++++++++++++++++++++++++++++++++
5 files changed, 474 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/prcm814x.h
create mode 100644 arch/arm/mach-omap2/prcm816x.h
create mode 100644 arch/arm/mach-omap2/prcm81xx.c
create mode 100644 arch/arm/mach-omap2/prcm81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4918ca..9c6b185 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
cm44xx.o prcm_mpu44xx.o \
prminst44xx.o vc44xx_data.o \
vp44xx_data.o
+obj-$(CONFIG_SOC_OMAPTI81XX) += prcm81xx.o
# OMAP voltage domains
ifeq ($(CONFIG_PM),y)
diff --git a/arch/arm/mach-omap2/prcm814x.h b/arch/arm/mach-omap2/prcm814x.h
new file mode 100644
index 0000000..82ea300
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm814x.h
@@ -0,0 +1,62 @@
+/*
+ * TI814X-specific PRCM register access macros
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM814X_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM814X_H
+
+#include "prcm81xx.h"
+
+/* TI814X-specific PRCM instances */
+#define TI814X_CM_HDVICP_INST 0x0600 /* 256B */
+#define TI814X_CM_ISP_INST 0x0700 /* 256B */
+#define TI814X_CM_DSS_INST 0x0800 /* 256B */
+#define TI814X_PRM_HDVICP_INST 0x0c00 /* 256B */
+#define TI814X_PRM_ISP_INST 0x0d00 /* 256B */
+#define TI814X_PRM_DSS_INST 0x0e00 /* 256B */
+#define TI814X_PRM_ALWON_INST 0x1800 /* 1KiB */
+
+
+/*
+ * TI814x-specific PRCM registers offsets. The offsets below are
+ * relative to the PRCM instance base.
+ */
+
+/* CM_ALWON */
+#define TI814X_CM_ALWON_L3_SLOW_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_ALWON_L3_SLOW_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0000)
+#define TI814X_CM_ALWON_L3_MED_CLKSTCTRL_OFFSET 0x0008
+#define TI814X_CM_ALWON_L3_MED_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0008)
+
+/* CM_HDVICP */
+#define TI814X_CM_HDVICP_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_HDVICP_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_HDVICP_INST, 0x0000)
+
+/* CM_ISP */
+#define TI814X_CM_ISP_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_ISP_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ISP_INST, 0x0000)
+
+/* CM_DSS */
+#define TI814X_CM_DSS_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_DSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ISP_INST, 0x0000)
+
+/* CM_DEFAULT */
+#define TI814X_CM_DEFAULT_TPPSS_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_DEFAULT_TPPSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0000)
+#define TI814X_CM_DEFAULT_PCI_CLKSTCTRL_OFFSET 0x0004
+#define TI814X_CM_DEFAULT_PCI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0004)
+#define TI814X_CM_DEFAULT_DUCATI_CLKSTCTRL_OFFSET 0x000c
+#define TI814X_CM_DEFAULT_DUCATI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x000c)
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm816x.h b/arch/arm/mach-omap2/prcm816x.h
new file mode 100644
index 0000000..74491d9
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm816x.h
@@ -0,0 +1,186 @@
+/*
+ * TI816X-specific PRCM register access macros
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM816X_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM816X_H
+
+#include "prcm81xx.h"
+
+/*
+ * TI816x-specific PRCM registers offsets. The offsets below are
+ * relative to the PRCM instance base.
+ */
+
+/* CM_DPLL */
+#define TI816X_CM_DPLL_SYSCLK1_CLKSEL_OFFSET 0x0000
+#define TI816X_CM_DPLL_SYSCLK1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0000)
+#define TI816X_CM_DPLL_SYSCLK2_CLKSEL_OFFSET 0x0004
+#define TI816X_CM_DPLL_SYSCLK2_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0004)
+#define TI816X_CM_DPLL_SYSCLK3_CLKSEL_OFFSET 0x0008
+#define TI816X_CM_DPLL_SYSCLK3_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0008)
+#define TI816X_CM_DPLL_SYSCLK4_CLKSEL_OFFSET 0x000C
+#define TI816X_CM_DPLL_SYSCLK4_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x000C)
+#define TI816X_CM_DPLL_SYSCLK5_CLKSEL_OFFSET 0x0010
+#define TI816X_CM_DPLL_SYSCLK5_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0010)
+#define TI816X_CM_DPLL_SYSCLK6_CLKSEL_OFFSET 0x0014
+#define TI816X_CM_DPLL_SYSCLK6_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0014)
+#define TI816X_CM_DPLL_SYSCLK7_CLKSEL_OFFSET 0x0018
+#define TI816X_CM_DPLL_SYSCLK7_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0018)
+#define TI816X_CM_DPLL_SYSCLK10_CLKSEL_OFFSET 0x0024
+#define TI816X_CM_DPLL_SYSCLK10_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0024)
+#define TI816X_CM_DPLL_SYSCLK11_CLKSEL_OFFSET 0x002C
+#define TI816X_CM_DPLL_SYSCLK11_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x002C)
+#define TI816X_CM_DPLL_SYSCLK12_CLKSEL_OFFSET 0x0030
+#define TI816X_CM_DPLL_SYSCLK12_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0030)
+#define TI816X_CM_DPLL_SYSCLK13_CLKSEL_OFFSET 0x0034
+#define TI816X_CM_DPLL_SYSCLK13_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0034)
+#define TI816X_CM_DPLL_SYSCLK15_CLKSEL_OFFSET 0x0038
+#define TI816X_CM_DPLL_SYSCLK15_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0038)
+#define TI816X_CM_DPLL_VPB3_CLKSEL_OFFSET 0x0040
+#define TI816X_CM_DPLL_VPB3_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0040)
+#define TI816X_CM_DPLL_VPC1_CLKSEL_OFFSET 0x0044
+#define TI816X_CM_DPLL_VPC1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0044)
+#define TI816X_CM_DPLL_VPD1_CLKSEL_OFFSET 0x0048
+#define TI816X_CM_DPLL_VPD1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0048)
+#define TI816X_CM_DPLL_SYSCLK19_CLKSEL_OFFSET 0x004C
+#define TI816X_CM_DPLL_SYSCLK19_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x004C)
+#define TI816X_CM_DPLL_SYSCLK20_CLKSEL_OFFSET 0x0050
+#define TI816X_CM_DPLL_SYSCLK20_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0050)
+#define TI816X_CM_DPLL_SYSCLK21_CLKSEL_OFFSET 0x0054
+#define TI816X_CM_DPLL_SYSCLK21_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0054)
+#define TI816X_CM_DPLL_SYSCLK22_CLKSEL_OFFSET 0x0058
+#define TI816X_CM_DPLL_SYSCLK22_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0058)
+#define TI816X_CM_DPLL_APA_CLKSEL_OFFSET 0x005C
+#define TI816X_CM_DPLL_APA_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x005C)
+#define TI816X_CM_DPLL_SYSCLK14_CLKSEL_OFFSET 0x0070
+#define TI816X_CM_DPLL_SYSCLK14_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0070)
+#define TI816X_CM_DPLL_SYSCLK16_CLKSEL_OFFSET 0x0074
+#define TI816X_CM_DPLL_SYSCLK16_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0074)
+#define TI816X_CM_DPLL_SYSCLK18_CLKSEL_OFFSET 0x0078
+#define TI816X_CM_DPLL_SYSCLK18_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0078)
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP0_CLKSEL_OFFSET 0x007C
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP0_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x007C)
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP1_CLKSEL_OFFSET 0x0080
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0080)
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP2_CLKSEL_OFFSET 0x0084
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP2_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0084)
+#define TI816X_CM_DPLL_AUDIOCLK_MCBSP_CLKSEL_OFFSET 0x0088
+#define TI816X_CM_DPLL_AUDIOCLK_MCBSP_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0088)
+#define TI816X_CM_DPLL_TIMER1_CLKSEL_OFFSET 0x0090
+#define TI816X_CM_DPLL_TIMER1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0090)
+#define TI816X_CM_DPLL_TIMER2_CLKSEL_OFFSET 0x0094
+#define TI816X_CM_DPLL_TIMER2_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0094)
+#define TI816X_CM_DPLL_TIMER3_CLKSEL_OFFSET 0x0098
+#define TI816X_CM_DPLL_TIMER3_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0098)
+#define TI816X_CM_DPLL_TIMER4_CLKSEL_OFFSET 0x009C
+#define TI816X_CM_DPLL_TIMER4_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x009C)
+#define TI816X_CM_DPLL_TIMER5_CLKSEL_OFFSET 0x00A0
+#define TI816X_CM_DPLL_TIMER5_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00A0)
+#define TI816X_CM_DPLL_TIMER6_CLKSEL_OFFSET 0x00A4
+#define TI816X_CM_DPLL_TIMER6_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00A4)
+#define TI816X_CM_DPLL_TIMER7_CLKSEL_OFFSET 0x00A8
+#define TI816X_CM_DPLL_TIMER7_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00A8)
+#define TI816X_CM_DPLL_HDMI_CLKSEL_OFFSET 0x00AC
+#define TI816X_CM_DPLL_HDMI_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00AC)
+#define TI816X_CM_DPLL_SYSCLK23_CLKSEL_OFFSET 0x00B0
+#define TI816X_CM_DPLL_SYSCLK23_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00B0)
+#define TI816X_CM_DPLL_SYSCLK24_CLKSEL_OFFSET 0x00B4
+#define TI816X_CM_DPLL_SYSCLK24_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00B4)
+
+/* CM_DEFAULT */
+#define TI816X_CM_DEFAULT_L3_MED_CLKSTCTRL_OFFSET 0x0004
+#define TI816X_CM_DEFAULT_L3_MED_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0004)
+#define TI816X_CM_DEFAULT_L3_FAST_CLKSTCTRL_OFFSET 0x0008
+#define TI816X_CM_DEFAULT_L3_FAST_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0008)
+#define TI816X_CM_DEFAULT_TPPSS_CLKSTCTRL_OFFSET 0x000C
+#define TI816X_CM_DEFAULT_TPPSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x000C)
+#define TI816X_CM_DEFAULT_PCI_CLKSTCTRL_OFFSET 0x0010
+#define TI816X_CM_DEFAULT_PCI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0010)
+#define TI816X_CM_DEFAULT_L3_SLOW_CLKSTCTRL_OFFSET 0x0014
+#define TI816X_CM_DEFAULT_L3_SLOW_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0014)
+#define TI816X_CM_DEFAULT_DUCATI_CLKSTCTRL_OFFSET 0x0018
+#define TI816X_CM_DEFAULT_DUCATI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0018)
+#define TI816X_CM_DEFAULT_EMIF_0_CLKCTRL_OFFSET 0x0020
+#define TI816X_CM_DEFAULT_EMIF_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0020)
+#define TI816X_CM_DEFAULT_EMIF_1_CLKCTRL_OFFSET 0x0024
+#define TI816X_CM_DEFAULT_EMIF_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0024)
+#define TI816X_CM_DEFAULT_DMM_CLKCTRL_OFFSET 0x0028
+#define TI816X_CM_DEFAULT_DMM_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0028)
+#define TI816X_CM_DEFAULT_FW_CLKCTRL_OFFSET 0x002C
+#define TI816X_CM_DEFAULT_FW_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x002C)
+#define TI816X_CM_DEFAULT_TPPSS_CLKCTRL_OFFSET 0x0054
+#define TI816X_CM_DEFAULT_TPPSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0054)
+#define TI816X_CM_DEFAULT_USB_CLKCTRL_OFFSET 0x0058
+#define TI816X_CM_DEFAULT_USB_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0058)
+#define TI816X_CM_DEFAULT_SATA_CLKCTRL_OFFSET 0x0060
+#define TI816X_CM_DEFAULT_SATA_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0060)
+#define TI816X_CM_DEFAULT_DUCATI_CLKCTRL_OFFSET 0x0074
+#define TI816X_CM_DEFAULT_DUCATI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0074)
+#define TI816X_CM_DEFAULT_PCI_CLKCTRL_OFFSET 0x0078
+#define TI816X_CM_DEFAULT_PCI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0078)
+
+/* CM_ALWON */
+#define TI816X_CM_ALWON_OCMC_1_CLKSTCTRL_OFFSET 0x0018
+#define TI816X_CM_ALWON_OCMC_1_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0018)
+#define TI816X_CM_ALWON_MPU_CLKSTCTRL_OFFSET 0x001C
+#define TI816X_CM_ALWON_MPU_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x001C)
+#define TI816X_CM_ALWON_TIMER_0_CLKCTRL_OFFSET 0x016C
+#define TI816X_CM_ALWON_TIMER_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x016C)
+#define TI816X_CM_ALWON_TIMER_1_CLKCTRL_OFFSET 0x0170
+#define TI816X_CM_ALWON_TIMER_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0170)
+#define TI816X_CM_ALWON_TIMER_2_CLKCTRL_OFFSET 0x0174
+#define TI816X_CM_ALWON_TIMER_2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0174)
+#define TI816X_CM_ALWON_TIMER_3_CLKCTRL_OFFSET 0x0178
+#define TI816X_CM_ALWON_TIMER_3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0178)
+#define TI816X_CM_ALWON_TIMER_5_CLKCTRL_OFFSET 0x0180
+#define TI816X_CM_ALWON_TIMER_5_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0180)
+#define TI816X_CM_ALWON_TIMER_6_CLKCTRL_OFFSET 0x0184
+#define TI816X_CM_ALWON_TIMER_6_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0184)
+#define TI816X_CM_ALWON_TIMER_7_CLKCTRL_OFFSET 0x0188
+#define TI816X_CM_ALWON_TIMER_7_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0188)
+#define TI816X_CM_ALWON_OCMC_1_CLKCTRL_OFFSET 0x01B8
+#define TI816X_CM_ALWON_OCMC_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01B8)
+#define TI816X_CM_ALWON_SMARTCARD_0_CLKCTR_OFFSET 0x01BC
+#define TI816X_CM_ALWON_SMARTCARD_0_CLKCTR TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01BC)
+#define TI816X_CM_ALWON_SMARTCARD_1_CLKCTR_OFFSET 0x01C0
+#define TI816X_CM_ALWON_SMARTCARD_1_CLKCTR TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01C0)
+#define TI816X_CM_ALWON_SECSS_CLKCTRL_OFFSET 0x01C8
+#define TI816X_CM_ALWON_SECSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01C8)
+#define TI816X_CM_ALWON_SR_2_CLKCTRL_OFFSET 0x0210
+#define TI816X_CM_ALWON_SR_2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0210)
+#define TI816X_CM_ALWON_SR_3_CLKCTRL_OFFSET 0x0214
+#define TI816X_CM_ALWON_SR_3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0214)
+#define TI816X_CM_ALWON_SR_4_CLKCTRL_OFFSET 0x0218
+#define TI816X_CM_ALWON_SR_4_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0218)
+#define TI816X_CM_ALWON_SR_5_CLKCTRL_OFFSET 0x021C
+#define TI816X_CM_ALWON_SR_5_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x021C)
+#define TI816X_CM_ALWON_SR_6_CLKCTRL_OFFSET 0x0220
+#define TI816X_CM_ALWON_SR_6_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0220)
+#define TI816X_CM_ALWON_SR_7_CLKCTRL_OFFSET 0x0224
+#define TI816X_CM_ALWON_SR_7_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0224)
+#define TI816X_CM_ALWON_CUST_EFUSE_CLKCTRL_OFFSET 0x0228
+#define TI816X_CM_ALWON_CUST_EFUSE_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0228)
+
+/* CM_ACTIVE */
+#define TI816X_CM_ACTIVE_HDDSS_CLKSTCTRL_OFFSET 0x0004
+#define TI816X_CM_ACTIVE_HDDSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0004)
+#define TI816X_CM_ACTIVE_HDMI_CLKSTCTRL_OFFSET 0x0008
+#define TI816X_CM_ACTIVE_HDMI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0008)
+#define TI816X_CM_ACTIVE_HDDSS_CLKCTRL_OFFSET 0x0024
+#define TI816X_CM_ACTIVE_HDDSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0024)
+#define TI816X_CM_ACTIVE_HDMI_CLKCTRL_OFFSET 0x0028
+#define TI816X_CM_ACTIVE_HDMI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0028)
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm81xx.c b/arch/arm/mach-omap2/prcm81xx.c
new file mode 100644
index 0000000..d48e5fc
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm81xx.c
@@ -0,0 +1,32 @@
+/*
+ * TI81XX PRCM register access functions
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#include "prcm81xx.h"
+
+static u32 ti81xx_prcm_inst_read(u16 inst, u16 offs)
+{
+ return __raw_readl(prm_base + inst + offs);
+}
+
+static void ti81xx_prcm_inst_write(u32 v, u16 inst, u16 offs)
+{
+ __raw_writel(v, prm_base + inst + offs);
+}
+
+
diff --git a/arch/arm/mach-omap2/prcm81xx.h b/arch/arm/mach-omap2/prcm81xx.h
new file mode 100644
index 0000000..fd0a174
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm81xx.h
@@ -0,0 +1,193 @@
+/*
+ * TI81XX PRCM register access macros and module offsets
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM81XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM81XX_H
+
+#include "prcm-common.h"
+
+#define TI81XX_PRCM_REGADDR(instance, reg) \
+ OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE + (instance) + (reg))
+
+/*
+ * TI81XX-common PRM/CM instance offsets
+ */
+#define TI81XX_PRM_DEVICE_INST 0x0000 /* 256B */
+#define TI81XX_CM_DEVICE_INST 0x0100 /* 256B */
+#define TI81XX_PRM_OCP_SOCKET_INST 0x0200 /* 256B */
+#define TI81XX_CM_DPLL_INST 0x0300 /* 256B */
+#define TI81XX_CM_ACTIVE_INST 0x0400 /* 256B */
+#define TI81XX_CM_DEFAULT_INST 0x0500 /* 256B */
+#define TI81XX_CM_SGX_INST 0x0900 /* 256B */
+#define TI81XX_PRM_ACTIVE_INST 0x0a00 /* 256B */
+#define TI81XX_PRM_DEFAULT_INST 0x0b00 /* 256B */
+#define TI81XX_PRM_SGX_INST 0x0f00 /* 256B */
+#define TI81XX_CM_ALWON_INST 0x1400 /* 1KB */
+
+/*
+ * TI81xx-common register offsets
+ */
+
+/* PRM_DEVICE */
+#define TI81XX_PRM_DEVICE_RSTCTRL_OFFSET 0x0000
+#define TI81XX_PRM_DEVICE_RSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_DEVICE_INST, 0x0000)
+#define TI81XX_PRM_DEVICE_RSTTIME_OFFSET 0x0004
+#define TI81XX_PRM_DEVICE_RSTTIME TI81XX_PRCM_REGADDR(TI81XX_PRM_DEVICE_INST, 0x0004)
+#define TI81XX_PRM_DEVICE_RSTST_OFFSET 0x0008
+#define TI81XX_PRM_DEVICE_RSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_DEVICE_INST, 0x0008)
+
+/* CM_DEVICE */
+#define TI81XX_CM_DEVICE_CLKOUT_CTRL_OFFSET 0x0000
+#define TI81XX_CM_DEVICE_CLKOUT_CTRL TI81XX_PRCM_REGADDR(TI81XX_CM_DEVICE_INST, 0x0000)
+
+/* OCP_SOCKET_PRM */
+#define TI81XX_PRM_OCP_SOCKET_REVISION_OFFSET 0x0000
+#define TI81XX_PRM_OCP_SOCKET_REVISION TI81XX_PRCM_REGADDR(TI81XX_PRM_OCP_SOCKET_INST, 0x0000)
+
+/* CM_ACTIVE */
+#define TI81XX_CM_ACTIVE_GEM_CLKSTCTRL_OFFSET 0x0000
+#define TI81XX_CM_ACTIVE_GEM_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0000)
+#define TI81XX_CM_ACTIVE_GEM_CLKCTRL_OFFSET 0x0020
+#define TI81XX_CM_ACTIVE_GEM_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0020)
+
+/* CM_SGX */
+#define TI81XX_CM_SGX_SGX_CLKSTCTRL_OFFSET 0x0000
+#define TI81XX_CM_SGX_SGX_CLKSTCTRL TI81XX_PRCM_REGADDR(TI81XX_CM_SGX_INST, 0x0000)
+#define TI81XX_CM_SGX_SGX_SGX_CLKCTRL_OFFSET 0x0020
+#define TI81XX_CM_SGX_SGX_SGX_CLKCTRL TI81XX_PRCM_REGADDR(TI81XX_CM_SGX_INST, 0x0020)
+
+/* PRM_ACTIVE */
+#define TI81XX_PRM_ACTIVE_PM_PWRSTCTRL_OFFSET 0x0000
+#define TI81XX_PRM_ACTIVE_PM_PWRSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0000)
+#define TI81XX_PRM_ACTIVE_PM_PWRSTST_OFFSET 0x0004
+#define TI81XX_PRM_ACTIVE_PM_PWRSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0004)
+#define TI81XX_PRM_ACTIVE_RM_RSTCTRL_OFFSET 0x0010
+#define TI81XX_PRM_ACTIVE_RM_RSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0010)
+#define TI81XX_PRM_ACTIVE_RM_RSTST_OFFSET 0x0014
+#define TI81XX_PRM_ACTIVE_RM_RSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0014)
+
+/* PRM_SGX */
+#define TI81XX_PRM_SGX_PM_PWRSTCTRL_OFFSET 0x0000
+#define TI81XX_PRM_SGX_PM_PWRSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0000)
+#define TI81XX_PRM_SGX_PM_PWRSTST_OFFSET 0x0004
+#define TI81XX_PRM_SGX_PM_PWRSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0004)
+#define TI81XX_PRM_SGX_RM_RSTCTRL_OFFSET 0x0010
+#define TI81XX_PRM_SGX_RM_RSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0010)
+#define TI81XX_PRM_SGX_RM_RSTST_OFFSET 0x0014
+#define TI81XX_PRM_SGX_RM_RSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0014)
+
+/* CM_ALWON */
+#define TI81XX_CM_ALWON_L3_SLOW_CLKSTCTRL_OFFSET 0x0000
+#define TI81XX_CM_ALWON_L3_SLOW_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0000)
+#define TI81XX_CM_ETHERNET_CLKSTCTRL_OFFSET 0x0004
+#define TI81XX_CM_ETHERNET_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0004)
+#define TI81XX_CM_ALWON_L3_MED_CLKSTCTRL_OFFSET 0x0008
+#define TI81XX_CM_ALWON_L3_MED_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0008)
+#define TI81XX_CM_MMU_CLKSTCTRL_OFFSET 0x000C
+#define TI81XX_CM_MMU_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x000C)
+#define TI81XX_CM_MMUCFG_CLKSTCTRL_OFFSET 0x0010
+#define TI81XX_CM_MMUCFG_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0010)
+#define TI81XX_CM_ALWON_OCMC_0_CLKSTCTRL_OFFSET 0x0014
+#define TI81XX_CM_ALWON_OCMC_0_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0014)
+#define TI81XX_CM_ALWON_SYSCLK4_CLKSTCTRL_OFFSET 0x0020
+#define TI81XX_CM_ALWON_SYSCLK4_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0020)
+#define TI81XX_CM_ALWON_SYSCLK5_CLKSTCTRL_OFFSET 0x0024
+#define TI81XX_CM_ALWON_SYSCLK5_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0024)
+#define TI81XX_CM_ALWON_SYSCLK6_CLKSTCTRL_OFFSET 0x0028
+#define TI81XX_CM_ALWON_SYSCLK6_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0028)
+#define TI81XX_CM_ALWON_RTC_CLKSTCTRL_OFFSET 0x002C
+#define TI81XX_CM_ALWON_RTC_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x002C)
+#define TI81XX_CM_ALWON_L3_FAST_CLKSTCTRL_OFFSET 0x0030
+#define TI81XX_CM_ALWON_L3_FAST_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0030)
+#define TI81XX_CM_ALWON_MCASP0_CLKCTRL_OFFSET 0x0140
+#define TI81XX_CM_ALWON_MCASP0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0140)
+#define TI81XX_CM_ALWON_MCASP1_CLKCTRL_OFFSET 0x0144
+#define TI81XX_CM_ALWON_MCASP1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0144)
+#define TI81XX_CM_ALWON_MCASP2_CLKCTRL_OFFSET 0x0148
+#define TI81XX_CM_ALWON_MCASP2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0148)
+#define TI81XX_CM_ALWON_MCBSP_CLKCTRL_OFFSET 0x014C
+#define TI81XX_CM_ALWON_MCBSP_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x014C)
+#define TI81XX_CM_ALWON_UART_0_CLKCTRL_OFFSET 0x0150
+#define TI81XX_CM_ALWON_UART_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0150)
+#define TI81XX_CM_ALWON_UART_1_CLKCTRL_OFFSET 0x0154
+#define TI81XX_CM_ALWON_UART_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0154)
+#define TI81XX_CM_ALWON_UART_2_CLKCTRL_OFFSET 0x0158
+#define TI81XX_CM_ALWON_UART_2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0158)
+#define TI81XX_CM_ALWON_GPIO_0_CLKCTRL_OFFSET 0x015C
+#define TI81XX_CM_ALWON_GPIO_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x015C)
+#define TI81XX_CM_ALWON_GPIO_1_CLKCTRL_OFFSET 0x0160
+#define TI81XX_CM_ALWON_GPIO_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0160)
+#define TI81XX_CM_ALWON_I2C_0_CLKCTRL_OFFSET 0x0164
+#define TI81XX_CM_ALWON_I2C_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0164)
+#define TI81XX_CM_ALWON_I2C_1_CLKCTRL_OFFSET 0x0168
+#define TI81XX_CM_ALWON_I2C_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0168)
+#define TI81XX_CM_ALWON_TIMER_4_CLKCTRL_OFFSET 0x017C
+#define TI81XX_CM_ALWON_TIMER_4_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x017C)
+#define TI81XX_CM_ALWON_WDTIMER_CLKCTRL_OFFSET 0x018C
+#define TI81XX_CM_ALWON_WDTIMER_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x018C)
+#define TI81XX_CM_ALWON_SPI_CLKCTRL_OFFSET 0x0190
+#define TI81XX_CM_ALWON_SPI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0190)
+#define TI81XX_CM_ALWON_MAILBOX_CLKCTRL_OFFSET 0x0194
+#define TI81XX_CM_ALWON_MAILBOX_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0194)
+#define TI81XX_CM_ALWON_SPINBOX_CLKCTRL_OFFSET 0x0198
+#define TI81XX_CM_ALWON_SPINBOX_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0198)
+#define TI81XX_CM_ALWON_MMUDATA_CLKCTRL_OFFSET 0x019C
+#define TI81XX_CM_ALWON_MMUDATA_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x019C)
+#define TI81XX_CM_ALWON_VLYNQ_CLKCTRL_OFFSET 0x01A0
+#define TI81XX_CM_ALWON_VLYNQ_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01A0)
+#define TI81XX_CM_ALWON_MMUCFG_CLKCTRL_OFFSET 0x01A8
+#define TI81XX_CM_ALWON_MMUCFG_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01A8)
+#define TI81XX_CM_ALWON_SDIO_CLKCTRL_OFFSET 0x01B0
+#define TI81XX_CM_ALWON_SDIO_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01B0)
+#define TI81XX_CM_ALWON_OCMC_0_CLKCTRL_OFFSET 0x01B4
+#define TI81XX_CM_ALWON_OCMC_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01B4)
+#define TI81XX_CM_ALWON_CONTROL_CLKCTRL_OFFSET 0x01C4
+#define TI81XX_CM_ALWON_CONTROL_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01C4)
+#define TI81XX_CM_ALWON_GPMC_CLKCTRL_OFFSET 0x01D0
+#define TI81XX_CM_ALWON_GPMC_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01D0)
+#define TI81XX_CM_ALWON_ETHERNET_0_CLKCTRL_OFFSET 0x01D4
+#define TI81XX_CM_ALWON_ETHERNET_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01D4)
+#define TI81XX_CM_ALWON_ETHERNET_1_CLKCTRL_OFFSET 0x01D8
+#define TI81XX_CM_ALWON_ETHERNET_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01D8)
+#define TI81XX_CM_ALWON_MPU_CLKCTRL_OFFSET 0x01DC
+#define TI81XX_CM_ALWON_MPU_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01DC)
+#define TI81XX_CM_ALWON_DEBUGSS_CLKCTRL_OFFSET 0x01E0
+#define TI81XX_CM_ALWON_DEBUGSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01E0)
+#define TI81XX_CM_ALWON_L3_CLKCTRL_OFFSET 0x01E4
+#define TI81XX_CM_ALWON_L3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01E4)
+#define TI81XX_CM_ALWON_L4HS_CLKCTRL_OFFSET 0x01E8
+#define TI81XX_CM_ALWON_L4HS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01E8)
+#define TI81XX_CM_ALWON_L4LS_CLKCTRL_OFFSET 0x01EC
+#define TI81XX_CM_ALWON_L4LS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01EC)
+#define TI81XX_CM_ALWON_RTC_CLKCTRL_OFFSET 0x01F0
+#define TI81XX_CM_ALWON_RTC_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01F0)
+#define TI81XX_CM_ALWON_TPCC_CLKCTRL_OFFSET 0x01F4
+#define TI81XX_CM_ALWON_TPCC_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01F4)
+#define TI81XX_CM_ALWON_TPTC0_CLKCTRL_OFFSET 0x01F8
+#define TI81XX_CM_ALWON_TPTC0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01F8)
+#define TI81XX_CM_ALWON_TPTC1_CLKCTRL_OFFSET 0x01FC
+#define TI81XX_CM_ALWON_TPTC1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01FC)
+#define TI81XX_CM_ALWON_TPTC2_CLKCTRL_OFFSET 0x0200
+#define TI81XX_CM_ALWON_TPTC2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0200)
+#define TI81XX_CM_ALWON_TPTC3_CLKCTRL_OFFSET 0x0204
+#define TI81XX_CM_ALWON_TPTC3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0204)
+#define TI81XX_CM_ALWON_SR_0_CLKCTRL_OFFSET 0x0208
+#define TI81XX_CM_ALWON_SR_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0208)
+#define TI81XX_CM_ALWON_SR_1_CLKCTRL_OFFSET 0x020C
+#define TI81XX_CM_ALWON_SR_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x020C)
+
+/* Function prototypes */
+
+#endif
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