* [PATCH 1/3 v3] ARM Realview PCIX map include file changes
From: Arnd Bergmann @ 2011-10-07 12:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHkRjk5MQUWiF3jmZJ_SBHdtmunoajR4eHftwdnFCKjeDxQDKA@mail.gmail.com>
On Friday 07 October 2011, Catalin Marinas wrote:
> > However, after changing both __io() and pcibios_min_io as Arnd suggested the boot still hangs after " Uncompressing Linux... done, booting the kernel."
>
> I haven't followed the patch series in detail but the __io() is also
> used by __io_address() in the RealView code and the former is just
> expected to do some type casting. By doing some arithmetic on the
> pointer, the static mappings for various peripherals (GIC etc.) are
> wrong.
>
> So if you convert __io() as per Arnd's suggestion, make sure that
> __io_address() is redefined, something like below:
>
> #define __io_address(n) __typesafe_io(IO_ADDRESS(n))
Ah, right. That definitely explains why it would not boot.
> Alternatively we could leave __io() as in the original kernel and
> define RealView specific in*/out* macros.
I wouldn't recommend that, since that would just have to be reverted
as we get closer to having a single zimage across platforms.
Your suggested fix above should be enough.
Arnd
^ permalink raw reply
* [PATCH v2 5/7] ARM: highbank: add SMP support
From: Shawn Guo @ 2011-10-07 12:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8C7F10.8070903@gmail.com>
On Wed, Oct 05, 2011 at 11:00:16AM -0500, Rob Herring wrote:
> Shawn,
>
> On 09/05/2011 08:01 PM, Shawn Guo wrote:
> > On Wed, Aug 31, 2011 at 08:44:04PM -0500, Rob Herring wrote:
> >> From: Rob Herring <rob.herring@calxeda.com>
> >>
> >> This enables SMP support on highbank processor.
> >>
> >> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
> >> ---
> >> Changes in v2:
> >> - drop NULL check of scu_base
> >> - use IPI #0 instead of #1 to boot secondary
> >> - s/a9_base_addr/scu_base_addr/
> >> - fix muliple mapping of twd registers
> >>
> >> arch/arm/Kconfig | 2 +-
> >> arch/arm/mach-highbank/Makefile | 2 +
> >> arch/arm/mach-highbank/localtimer.c | 38 +++++++++++++++++
> >> arch/arm/mach-highbank/platsmp.c | 78 +++++++++++++++++++++++++++++++++++
> >> 4 files changed, 119 insertions(+), 1 deletions(-)
> >> create mode 100644 arch/arm/mach-highbank/localtimer.c
> >> create mode 100644 arch/arm/mach-highbank/platsmp.c
> >>
> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> >> index 9019a56..6d2add5 100644
> >> --- a/arch/arm/Kconfig
> >> +++ b/arch/arm/Kconfig
> >> @@ -1372,7 +1372,7 @@ config SMP
> >> depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
> >> MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
> >> ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
> >> - ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
> >> + ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK
> >> select USE_GENERIC_SMP_HELPERS
> >> select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
> >> help
> >> diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
> >> index 11d4010..311c0e8e 100644
> >> --- a/arch/arm/mach-highbank/Makefile
> >> +++ b/arch/arm/mach-highbank/Makefile
> >> @@ -1,2 +1,4 @@
> >> obj-y := clock.o highbank.o system.o
> >> obj-$(CONFIG_DEBUG_LL) += lluart.o
> >> +obj-$(CONFIG_SMP) += platsmp.o
> >> +obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
> >> diff --git a/arch/arm/mach-highbank/localtimer.c b/arch/arm/mach-highbank/localtimer.c
> >> new file mode 100644
> >> index 0000000..344ea29
> >> --- /dev/null
> >> +++ b/arch/arm/mach-highbank/localtimer.c
> >> @@ -0,0 +1,38 @@
> >> +/*
> >> + * Copyright 2010-2011 Calxeda, Inc.
> >> + * Based on localtimer.c, Copyright (C) 2002 ARM Ltd.
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify it
> >> + * under the terms and conditions of the GNU General Public License,
> >> + * version 2, as published by the Free Software Foundation.
> >> + *
> >> + * This program is distributed in the hope it will be useful, but WITHOUT
> >> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> >> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> >> + * more details.
> >> + *
> >> + * You should have received a copy of the GNU General Public License along with
> >> + * this program. If not, see <http://www.gnu.org/licenses/>.
> >> + */
> >> +#include <linux/init.h>
> >> +#include <linux/clockchips.h>
> >> +#include <linux/of.h>
> >> +#include <linux/of_address.h>
> >> +#include <linux/of_irq.h>
> >> +
> >> +#include <asm/smp_twd.h>
> >> +
> >> +/*
> >> + * Setup the local clock events for a CPU.
> >> + */
> >> +int __cpuinit local_timer_setup(struct clock_event_device *evt)
> >> +{
> >> + struct device_node *np;
> >> +
> >> + np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
> >> + if (!twd_base)
> >> + twd_base = of_iomap(np, 0);
> >
> > WARN_ON(!twd_base)?
> >
>
> Okay, will add it. Can I add your Reviewed-by for the series?
>
Yes, if you'd like to ;)
--
Regards,
Shawn
^ permalink raw reply
* [PATCH V9 2/5] ahci_plt Add the board_ids and pi refer to different features
From: Sascha Hauer @ 2011-10-07 12:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8D4909.9030603@pobox.com>
On Thu, Oct 06, 2011 at 02:22:01AM -0400, Jeff Garzik wrote:
>
> Looks good... I queued this one.
Ok, I'll take care for the rest of this series.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH V2] AT91: dt: at91sam9g45 family and board device tree files
From: Nicolas Ferre @ 2011-10-07 12:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8C54DC.6040700@gmail.com>
On 10/05/2011 03:00 PM, Rob Herring :
> Nicolas,
>
> On 10/03/2011 05:00 AM, Nicolas Ferre wrote:
>> Create a new device tree source file for Atmel at91sam9g45 SoC family.
>> The Evaluation Kit at91sam9m10g45ek includes it.
>> This first basic support will be populated as drivers and boards will be
>> converted to device tree.
>> Contains serial, dma and interrupt controllers.
>>
>> The generic board file still takes advantage of platform data for early serial
>> init. As we need a storage media and the NAND flash driver is not converted to
>> DT yet, we keep old initialization for it.
>>
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>> ---
>> V2: foundation for AT91SAM generic support
>> - device tree focused board file
>> - inclusion of USART DT support
>> - early USART and NAND still using platform data
>>
>> arch/arm/boot/dts/at91sam9g45.dtsi | 103 +++++++++++++++++++++++++
>> arch/arm/boot/dts/at91sam9m10g45ek.dts | 37 +++++++++
>> arch/arm/mach-at91/Kconfig | 11 +++
>> arch/arm/mach-at91/Makefile | 3 +
>> arch/arm/mach-at91/Makefile.boot | 2 +
>> arch/arm/mach-at91/at91sam9g45_devices.c | 24 +++++--
>> arch/arm/mach-at91/board-dt.c | 122 ++++++++++++++++++++++++++++++
>> 7 files changed, 296 insertions(+), 6 deletions(-)
>> create mode 100644 arch/arm/boot/dts/at91sam9g45.dtsi
>> create mode 100644 arch/arm/boot/dts/at91sam9m10g45ek.dts
>> create mode 100644 arch/arm/mach-at91/board-dt.c
>>
>> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
>> new file mode 100644
>> index 0000000..7d3341f
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
>> @@ -0,0 +1,103 @@
>> +/*
>> + * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
>> + * applies to AT91SAM9G45, AT91SAM9M10,
>> + * AT91SAM9G46, AT91SAM9M11 SoC
>> + *
>> + * Copyright (C) 2011 Atmel,
>> + * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
>> + *
>> + * Licensed under GPLv2 or later.
>> + */
>> +
>> +/include/ "skeleton.dtsi"
>> +
>> +/ {
>> + model = "Atmel AT91SAM9G45 family SoC";
>> + compatible = "atmel,at91sam9g45";
>> + interrupt-parent = <&aic>;
>> +
>> + aliases {
>> + serial0 = &dbgu;
>> + serial1 = &usart0;
>> + serial2 = &usart1;
>> + serial3 = &usart2;
>> + serial4 = &usart3;
>> + };
>> + cpus {
>> + cpu at 0 {
>> + compatible = "arm,arm926ejs";
>> + };
>> + };
>> +
>> + memory {
>
> Should be memory at 0x70000000
>
>> + reg = <0x70000000 0x10000000>;
>> + };
>> +
>> + ahb {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + apb {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + aic: interrupt-controller at fffff000 {
>> + #interrupt-cells = <1>;
>> + compatible = "atmel,at91rm9200-aic";
>> + interrupt-controller;
>
> Add "interrupt-parent;" so that the aic is not the parent of itself.
>
>> + reg = <0xfffff000 0x200>;
>> + };
>> +
>> + dma: dma-controller at ffffec00 {
>> + compatible = "atmel,at91sam9g45-hdmac";
>> + reg = <0xffffec00 0x200>;
>> + interrupts = <21>;
>> + atmel,hdmac-nr-channels = <8>;
>> + atmel,hdmac-cap-memcpy;
>> + atmel,hdmac-cap-slave;
>> + };
>> +
>> + dbgu: serial at ffffee00 {
>> + compatible = "atmel,at91sam9260-usart";
>> + reg = <0xffffee00 0x200>;
>> + interrupts = <1>;
>> + };
>> +
>> + usart0: serial at fff8c000 {
>> + compatible = "atmel,at91sam9260-usart";
>> + reg = <0xfff8c000 0x4000>;
>
> Is 16K really used? I would set to 4K so your not wasting virtual space
> (probably not an issue yet on Atmel parts).
Yes, I can adapt this value to the real size of register bank. The
memory map on the datasheet is not precise about this and I have to
refer to the IP documentation itself. But anyway, if it has an interest,
I can adapt this to real values.
>> + interrupts = <7>;
>> + atmel,use-dma-rx;
>> + atmel,use-dma-tx;
>> + };
>> +
>> + usart1: serial at fff90000 {
>> + compatible = "atmel,at91sam9260-usart";
>> + reg = <0xfff90000 0x4000>;
>> + interrupts = <8>;
>> + atmel,use-dma-rx;
>> + atmel,use-dma-tx;
>> + };
>> +
>> + usart2: serial at fff94000 {
>> + compatible = "atmel,at91sam9260-usart";
>> + reg = <0xfff94000 0x4000>;
>> + interrupts = <9>;
>> + atmel,use-dma-rx;
>> + atmel,use-dma-tx;
>> + };
>> +
>> + usart3: serial at fff98000 {
>> + compatible = "atmel,at91sam9260-usart";
>> + reg = <0xfff98000 0x4000>;
>> + interrupts = <10>;
>> + atmel,use-dma-rx;
>> + atmel,use-dma-tx;
>> + };
>> + };
>> + };
>> +};
>> diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
>> new file mode 100644
>> index 0000000..cf743de
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
>> @@ -0,0 +1,37 @@
>> +/*
>> + * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
>> + *
>> + * Copyright (C) 2011 Atmel,
>> + * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
>> + *
>> + * Licensed under GPLv2 or later.
>> + */
>> +/dts-v1/;
>> +/include/ "at91sam9g45.dtsi"
>> +
>> +/ {
>> + model = "Atmel AT91SAM9M10G45-EK";
>> + compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
>> +
>> + chosen {
>> + bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,60M(rootfs),-(data) root=/dev/mtdblock1 rw rootfstype=jffs2";
>> + };
>> +
>> + memory {
>> + reg = <0x70000000 0x4000000>;
>> + };
>> +
>> + ahb {
>> + apb {
>> + usart0: serial at fff8c000 {
>> + status = "disabled";
>> + };
>> + usart2: serial at fff94000 {
>> + status = "disabled";
>> + };
>> + usart3: serial at fff98000 {
>> + status = "disabled";
>> + };
>> + };
>> + };
>> +};
>> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
>> index 2248467..4b59d96 100644
>> --- a/arch/arm/mach-at91/Kconfig
>> +++ b/arch/arm/mach-at91/Kconfig
>> @@ -442,6 +442,17 @@ endif
>>
>> # ----------------------------------------------------------
>>
>> +comment "Generic Board Type"
>> +
>> +config MACH_AT91SAM_DT
>> + bool "Atmel AT91SAM Evaluation Kits with device-tree support"
>> + select USE_OF
>> + help
>> + Select this if you want to experiment device-tree with
>> + an Atmel Evaluation Kit.
>> +
>> +# ----------------------------------------------------------
>> +
>> comment "AT91 Board Options"
>>
>> config MTD_AT91_DATAFLASH_CARD
>> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
>> index bf57e8b..3ff245e 100644
>> --- a/arch/arm/mach-at91/Makefile
>> +++ b/arch/arm/mach-at91/Makefile
>> @@ -74,6 +74,9 @@ obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
>> # AT91SAM9G45 board-specific support
>> obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
>>
>> +# AT91SAM board with device-tree
>> +obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
>> +
>> # AT91CAP9 board-specific support
>> obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
>>
>> diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
>> index 3462b81..d278863 100644
>> --- a/arch/arm/mach-at91/Makefile.boot
>> +++ b/arch/arm/mach-at91/Makefile.boot
>> @@ -16,3 +16,5 @@ else
>> params_phys-y := 0x20000100
>> initrd_phys-y := 0x20410000
>> endif
>> +
>> +dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
>> diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
>> index bb84040..27276b8 100644
>> --- a/arch/arm/mach-at91/at91sam9g45_devices.c
>> +++ b/arch/arm/mach-at91/at91sam9g45_devices.c
>> @@ -69,9 +69,16 @@ static struct platform_device at_hdmac_device = {
>>
>> void __init at91_add_device_hdmac(void)
>> {
>> - dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
>> - dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
>> - platform_device_register(&at_hdmac_device);
>> + struct device_node *of_node =
>> + of_find_node_by_name(NULL, "dma-controller");
>
> You should really search by the compatible string.
>
>> +
>> + if (of_node) {
>> + of_node_put(of_node);
>> + } else {
>> + dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
>> + dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
>
> This really should be in the driver.
Yes, I will try to find a way to get rid of those platform data.
>> + platform_device_register(&at_hdmac_device);
>> + }
>> }
>> #else
>> void __init at91_add_device_hdmac(void) {}
>> @@ -1556,10 +1563,15 @@ void __init at91_set_serial_console(unsigned portnr)
>> void __init at91_add_device_serial(void)
>> {
>> int i;
>> + struct device_node *of_node = of_find_node_by_name(NULL, "serial");
>>
>> - for (i = 0; i < ATMEL_MAX_UART; i++) {
>> - if (at91_uarts[i])
>> - platform_device_register(at91_uarts[i]);
>> + if (of_node) {
>> + of_node_put(of_node);
>> + } else {
>> + for (i = 0; i < ATMEL_MAX_UART; i++) {
>> + if (at91_uarts[i])
>> + platform_device_register(at91_uarts[i]);
>> + }
>
> Why can't you only call these init functions when booting non-DT?
For the dma driver function: this init function is called as an
arch_initcall().
But for the 91_add_device_serial() function, I can simply avoid calling
it, like you suggest.
>> }
>>
>> if (!atmel_default_console_device)
>> diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
>> new file mode 100644
>> index 0000000..7bcb9a9
>> --- /dev/null
>> +++ b/arch/arm/mach-at91/board-dt.c
>> @@ -0,0 +1,122 @@
>> +/*
>> + * Setup code for AT91SAM Evaluation Kits with Device Tree support
>> + *
>> + * Covers: * AT91SAM9G45-EKES board
>> + * * AT91SAM9M10-EKES board
>> + * * AT91SAM9M10G45-EK board
>> + *
>> + * Copyright (C) 2011 Atmel,
>> + * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
>> + *
>> + * Licensed under GPLv2 or later.
>> + */
>> +
>> +#include <linux/types.h>
>> +#include <linux/init.h>
>> +#include <linux/module.h>
>> +#include <linux/irqdomain.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_platform.h>
>> +
>> +#include <mach/hardware.h>
>> +#include <mach/board.h>
>> +#include <mach/gpio.h>
>> +#include <mach/system_rev.h>
>> +#include <mach/at91sam9_smc.h>
>> +
>> +#include <asm/setup.h>
>> +#include <asm/irq.h>
>> +#include <asm/mach/arch.h>
>> +#include <asm/mach/map.h>
>> +#include <asm/mach/irq.h>
>> +
>> +#include "sam9_smc.h"
>> +#include "generic.h"
>> +
>> +
>> +static void __init ek_init_early(void)
>> +{
>> + /* Initialize processor: 12.000 MHz crystal */
>> + at91_initialize(12000000);
>> +
>> + /* DGBU on ttyS0. (Rx & Tx only) */
>> + at91_register_uart(0, 0, 0);
>> +
>> + /* USART0 not connected on the -EK board */
>> + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
>> + at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
>> +
>> + /* set serial console to ttyS0 (ie, DBGU) */
>> + at91_set_serial_console(0);
>> +}
>> +
>> +/* det_pin is not connected */
>> +static struct atmel_nand_data __initdata ek_nand_data = {
>> + .ale = 21,
>> + .cle = 22,
>> + .rdy_pin = AT91_PIN_PC8,
>> + .enable_pin = AT91_PIN_PC14,
>> +};
>> +
>> +static struct sam9_smc_config __initdata ek_nand_smc_config = {
>> + .ncs_read_setup = 0,
>> + .nrd_setup = 2,
>> + .ncs_write_setup = 0,
>> + .nwe_setup = 2,
>> +
>> + .ncs_read_pulse = 4,
>> + .nrd_pulse = 4,
>> + .ncs_write_pulse = 4,
>> + .nwe_pulse = 4,
>> +
>> + .read_cycle = 7,
>> + .write_cycle = 7,
>> +
>> + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
>> + .tdf_cycles = 3,
>> +};
>> +
>> +static void __init ek_add_device_nand(void)
>> +{
>> + ek_nand_data.bus_width_16 = board_have_nand_16bit();
>> + /* setup bus-width (8 or 16) */
>> + if (ek_nand_data.bus_width_16)
>> + ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
>> + else
>> + ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
>> +
>> + /* configure chip-select 3 (NAND) */
>> + sam9_smc_configure(3, &ek_nand_smc_config);
>> +
>> + at91_add_device_nand(&ek_nand_data);
>> +}
>> +
>> +static const struct of_device_id aic_of_match[] __initconst = {
>> + { .compatible = "atmel,at91rm9200-aic", },
>> + {},
>> +};
>> +
>> +static void __init at91_dt_device_init(void)
>> +{
>> + irq_domain_generate_simple(aic_of_match, 0xfffff000, 0);
>
> Why is this not in the .init_irq function? I'm surprised your timer
> interrupt even works.
Ok, I will add an .init_irq function in my v3 patch.
BTW, as I am a little bit confused about the "early" serial
initialization, what is the proper way to address this?
So, can you tell me or give me a pointer to an update on this topic: I
know that it is moving a lot those days...
Thanks a lot for your review.
Best regards,
--
Nicolas Ferre
^ permalink raw reply
* [PATCH v3 2/3] ARM: OMAP: TI814X: Add cpu type macros and detection support
From: Pedanekar, Hemant @ 2011-10-07 13:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2A3DCF3DA181AD40BDE86A3150B27B6B03B4EC56A8@dbde02.ent.ti.com>
Hi Paul,
linux-arm-kernel-bounces at lists.infradead.org wrote on :
> macros and detection support
>
> Hi Paul,
>
> Paul Walmsley wrote on Friday, September 30, 2011 2:17 AM:
>
>> Hello Hemant,
>>
>> a few comments:
>>
>> On Thu, 29 Sep 2011, Hemant Pedanekar wrote:
>>
[...]
>>> Note that following update to common OMAP data structures is made:
>>>
>>> cpu_mask and RATE_IN_XXX flags have crossed 8 bit hence struct
>>> clksel_rate.flags, struct prcm_config.flags and cpu_mask are changed to
>>> u16 from u8.
>>>
>>> Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
>>
>> Also, the opp2xxx.h change looks spurious, is that really needed?
>>
I will be removing the above mentioned code changes from v4 since the same
were added in "arm:omap:am33xx: Update common omap platform files" patch and
as per Tony's reply today ([1]) the am33xx patch will be added to SoC branch.
Thanks.
Hemant
[1] http://www.spinics.net/lists/linux-omap/msg58853.html
> I changed prcm_config.flags to accommodate cpu_mask change,
> as cpu_mask
> is used with prcm_config.flags (mostly) in clkt2xxx_virt_prcm_set.c as
> below:
>
> prcm->flags & cpu_mask
>
> And flags is assigned in opp2420_data.c (e.g., RATE_IN_242X)
>
> But yes, these are already defined RATE_INs and do not cross 8-bits,
> so no warnings even if flags is 8-bit and cpu_mask changed to 16-bit.
>
> What is your suggestion?
>
> I see you mentioned "Also" in the above comment, but didn't see any comment
> preceeding.
>
>> Could you please split the clock-related changes into a
>> separate patch?
>> Then this patch would just be the id.c and cpu.h changes.
>>
>> Other than that, the patch looks okay to me.
>>
>>
>> - Paul
>
> Will do that.
>
> Thanks.
> Hemant
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Long stalls during boot with -next
From: Thomas Abraham @ 2011-10-07 13:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111007115047.GC24534@sirena.org.uk>
Hi Mark,
On 7 October 2011 17:20, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Thu, Sep 29, 2011 at 01:50:36PM +0100, Mark Brown wrote:
>> Since Tuesday I've been experiencing stalls on boot with -next kernels.
>> The boot appears to proceed normally but there appears to be a good ten
>> second delay somewhere around the late_initcall() stage with no
>> indication in the logs:
>
> I identified the problem here, the behaviour of LL_DEBUG was changed to
> make it select DEBUG_ICEDCC by default which is unfortunate if one
> doesn't have an EmbeddedICE connected.
Thanks for your suggestion. The long stall during boot problem occurs
on Samsung boards as well with linux-next. As per your suggestion, the
following diff fixes this issue.
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 65cf8c6..035f5cd 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -120,6 +120,15 @@ choice
Say Y here if you want the debug print routines to direct
their output to the second serial port on these devices.
+ config DEBUG_SAMSUNG_UART
+ bool "Kernel low-level debugging messages via samsung serial port"
+ depends on PLAT_SAMSUNG
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the serial port for Samsung platforms. Choose
+ the uart port with the "S3C UART to use for low-level debug"
+ config option.
+
endchoice
config EARLY_PRINTK
@@ -139,7 +148,7 @@ config OC_ETM
kernel code.
config DEBUG_S3C_UART
- depends on PLAT_SAMSUNG
+ depends on DEBUG_SAMSUNG_UART
int "S3C UART to use for low-level debug"
default "0"
help
Thanks,
Thomas.
^ permalink raw reply related
* [PATCH 1/4] mmc: mmci: Bugfix in pio read for small packets
From: Ulf Hansson @ 2011-10-07 13:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E895F6A.9070203@stericsson.com>
Stefan NILSSON9 wrote:
> Hi Russel,
>
> On 10/01/2011 06:09 PM, Russell King - ARM Linux wrote:
>> Does this even work? From the MMCI spec, I see no way for the MMCI
>> peripheral to know the size of the read/write on the APB bus.
>>
>> The APB bus signals the MMCI uses are:
>>
>> PCLK - APB bus clock
>> PRESETn - APB bus reset
>> PADDR[11:2] - APB bus address
>> PSEL - APB bus peripheral select
>> PENABLE - APB bus enable
>> PWRITE - APB bus write signal
>> PWDATA[31:0] - APB bus write data
>> PRDATA[31:0] - APB bus read data
>>
>> As you can see, nothing in that set indicates whether it's an 8-bit,
>> 16-bit or 32-bit access.
>
>> Moreover, if you read the MMCIFifoCnt register writeup:
>>
>> The MMCIFifoCnt register contains the remaining number of words to be
>> written to or read from the FIFO. The FIFO counter loads the value
>> from the data length register (see Data length register, MMCIDataLength
>> on page 3-11) when the Enable bit is set in the data control register.
>> If the data length is not word aligned (multiple of 4), the remaining
>> 1 to 3 bytes are regarded as a word.
>>
>> This suggests that we should be reading a 32-bit word and then storing
>> the relevant bytes from it.
>
> Hmm, that is true. I will try to rework the patch to skip the case and
> only do 32 bit reads. We do however need a patch since the current
> "count" calculation is wrong (more info below). But it does in fact work.
>
>> The other thing which concerns me is that the MMCI (ARM Ltd one at least)
>> only supports power-of-two block sizes. So requesting a transfer of a
>> single block with a block size of 3 bytes is not supported by the ARM Ltd
>> MMCI. (The way you end up with 1 to 3 bytes being received with ARM's
>> MMCI is if you're using a streaming transfer.)
>
> This is true for the standard ARM block. We have however done some
> modifications of the standard block and added support for SDIO which
> also implies streaming transfers which can be non power of 2. So with
> the current implementation:
>
> readsl(base + MMCIFIFO, ptr, count >> 2);
>
> when we get a request to read 3, 2 or 1 bytes (which our WLAN driver
> actually requests from time to time), this will result in reading 0
> words which is not correct. This was the original problem, but I might
> have "overdone" the solution a bit. I will upload a new patch which
> solves the original problem in a better way.
>
>> The last thing I don't like about this patch is that this code is in a
>> really hot path - one which is absolutely critical for things to work -
>> and the need for the condition to be dealt with is only at the end of a
>> transfer, not each time the FIFO needs emptying.
In this hot path we already do a read of the FIFOCNT register for every
loop in pio_read, won't this sometimes cause caches to flush and
similar, thus cost quite a lot - at least a lot more than executing a
switch/if sentence like Stefan added? Or do I miss something?
I were also thinking of a possible optimization of minimizing the total
numbers of reads of the FIFOCNT register in pio_read. Basically we can
make use of the RXFIFOHALFFULL irq/status to know when there is a
"burst" available in the FIFO. Do you think this will be feasible for
the ARM MMCI Pl18x IP as well? I mean the consequence of using
RXFIFOHALFFULL will be less numbers of IRQ raised and then when reading
data from the FIFO it will be done in larger chunks.
>>
>> Bear in mind that there are platforms with the ARM MMCI which must read
>> the data within a certain time or suffer overruns, and which have either
>> totally broken and useless DMA or no DMA capability at all (which are
>> the only platforms I have with a MMCI on.)
We could make use of the "likely" makro to make compiler optimizations
of the code, is that a way forward do you think?
>
> I will keep this in mind. We are fortunately blessed with a working DMA
> in our platform, but for small SDIO transfers there is no point in
> setting up a DMA job which is when we fall back to PIO mode.
>
> Best Regards
>
> Stefan Nilsson
>
^ permalink raw reply
* [PATCH 1/4] mmc: mmci: Bugfix in pio read for small packets
From: Ulf Hansson @ 2011-10-07 13:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111001160937.GF11710@n2100.arm.linux.org.uk>
Russell King - ARM Linux wrote:
> On Tue, Sep 27, 2011 at 09:46:08AM +0200, Ulf Hansson wrote:
>> From: Stefan Nilsson XK <stefan.xk.nilsson@stericsson.com>
>>
>> Corrects a bug in pio read when reading packets < 4 bytes. These
>> small packets are only relevant for SDIO transfers.
>
> Does this even work? From the MMCI spec, I see no way for the MMCI
> peripheral to know the size of the read/write on the APB bus.
>
Hi Russel,
My feeling is that since discussing this patch, the rest of the patches
in this serie and are kind of "put on hold". The reason for keeping them
together is more of functional purpose. I hope you can have a look at
them anyway, they shall be possible to apply without this one.
If you prefer we can split up this patchserie...
BR
Ulf Hansson
^ permalink raw reply
* [PATCH] ARM: EXYNOS4: Add support for M-5MOLS camera on Nuri board
From: Sylwester Nawrocki @ 2011-10-07 13:53 UTC (permalink / raw)
To: linux-arm-kernel
Add voltage regulator and platform data definition for M-5MOLS sensor
and MIPI-CSI receiver drivers. Add CAM power domain dependencies for
FIMC device and set up camera port A GPIO. Configure I2C0 bus timings.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
This is to enable M-5MOLS camera on Exynos4 Nuri board. The patch is
based of off git://github.com/kgene/linux-samsung.git for-next.
Thanks,
Sylwester
---
arch/arm/mach-exynos4/Kconfig | 8 ++
arch/arm/mach-exynos4/mach-nuri.c | 158 +++++++++++++++++++++++++++++++++++++
2 files changed, 166 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index dd660eb..afa6cb5 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -215,9 +215,15 @@ config MACH_UNIVERSAL_C210
config MACH_NURI
bool "Mobile NURI Board"
select CPU_EXYNOS4210
+ select S5P_GPIO_INT
select S3C_DEV_WDT
select S3C_DEV_RTC
select S5P_DEV_FIMD0
+ select S5P_DEV_FIMC0
+ select S5P_DEV_FIMC1
+ select S5P_DEV_FIMC2
+ select S5P_DEV_FIMC3
+ select S5P_DEV_CSIS0
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
@@ -233,6 +239,8 @@ config MACH_NURI
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
+ select EXYNOS4_SETUP_FIMC
+ select S5P_SETUP_MIPIPHY
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_ADC
help
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index bbd13f4..62c18ab 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -45,9 +45,16 @@
#include <plat/iic.h>
#include <plat/mfc.h>
#include <plat/pd.h>
+#include <plat/fimc-core.h>
+#include <plat/camport.h>
+#include <plat/mipi_csis.h>
#include <mach/map.h>
+#include <media/m5mols.h>
+#include <media/s5p_fimc.h>
+#include <media/v4l2-mediabus.h>
+
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
@@ -65,6 +72,8 @@
enum fixed_regulator_id {
FIXED_REG_ID_MMC = 0,
FIXED_REG_ID_MAX8903,
+ FIXED_REG_ID_CAM_A28V,
+ FIXED_REG_ID_CAM_12V,
};
static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
@@ -1117,10 +1126,146 @@ static void __init nuri_ehci_init(void)
s5p_ehci_set_platdata(pdata);
}
+/* CAMERA */
+static struct regulator_consumer_supply cam_vdda_supply[] = {
+ REGULATOR_SUPPLY("a_sensor", "0-001f"),
+};
+
+static struct regulator_init_data cam_vdda_reg_init_data = {
+ .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+ .num_consumer_supplies = ARRAY_SIZE(cam_vdda_supply),
+ .consumer_supplies = cam_vdda_supply,
+};
+
+static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
+ .supply_name = "CAM_IO_EN",
+ .microvolts = 2800000,
+ .gpio = EXYNOS4_GPE2(1), /* CAM_IO_EN */
+ .enable_high = 1,
+ .init_data = &cam_vdda_reg_init_data,
+};
+
+static struct platform_device cam_vdda_fixed_rdev = {
+ .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_A28V,
+ .dev = { .platform_data = &cam_vdda_fixed_voltage_cfg },
+};
+
+static struct regulator_consumer_supply camera_8m_12v_supply =
+ REGULATOR_SUPPLY("dig_12", "0-001f");
+
+static struct regulator_init_data cam_8m_12v_reg_init_data = {
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &camera_8m_12v_supply,
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS
+ },
+};
+
+static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
+ .supply_name = "8M_1.2V",
+ .microvolts = 1200000,
+ .gpio = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
+ .enable_high = 1,
+ .init_data = &cam_8m_12v_reg_init_data,
+};
+
+static struct platform_device cam_8m_12v_fixed_rdev = {
+ .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_12V,
+ .dev = { .platform_data = &cam_8m_12v_fixed_voltage_cfg },
+};
+
+static struct s5p_platform_mipi_csis mipi_csis_platdata = {
+ .clk_rate = 166000000UL,
+ .lanes = 2,
+ .alignment = 32,
+ .hs_settle = 12,
+ .phy_enable = s5p_csis_phy_enable,
+};
+
+#define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */
+#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPL2(5)
+
+static struct m5mols_platform_data m5mols_platdata = {
+ .gpio_reset = GPIO_CAM_MEGA_RST,
+};
+
+static struct i2c_board_info m5mols_board_info = {
+ I2C_BOARD_INFO("M5MOLS", 0x1F),
+ .platform_data = &m5mols_platdata,
+};
+
+static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
+ {
+ .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
+ V4L2_MBUS_VSYNC_ACTIVE_LOW,
+ .bus_type = FIMC_MIPI_CSI2,
+ .board_info = &m5mols_board_info,
+ .clk_frequency = 24000000UL,
+ .csi_data_align = 32,
+ },
+};
+
+static struct s5p_platform_fimc fimc_md_platdata = {
+ .isp_info = nuri_camera_sensors,
+ .num_clients = ARRAY_SIZE(nuri_camera_sensors),
+};
+
+struct platform_device s5p_device_fimc_md = {
+ .name = "s5p-fimc-md",
+ .id = -1,
+};
+
+static struct gpio nuri_camera_gpios[] = {
+ { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
+ { GPIO_CAM_MEGA_RST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
+};
+
+static void nuri_camera_init(void)
+{
+ s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
+ &s5p_device_mipi_csis0);
+ s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata),
+ &s5p_device_fimc_md);
+
+ if (gpio_request_array(nuri_camera_gpios,
+ ARRAY_SIZE(nuri_camera_gpios))) {
+ pr_err("%s: GPIO request failed\n", __func__);
+ return;
+ }
+
+ m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT);
+ if (!IS_ERR_VALUE(m5mols_board_info.irq))
+ s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF));
+ else
+ pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
+
+ /* Free GPIOs controlled directly by the sensor drivers. */
+ gpio_free(GPIO_CAM_MEGA_RST);
+ gpio_free(GPIO_CAM_8M_ISP_INT);
+
+ if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
+ pr_err("%s: Camera port A setup failed\n", __func__);
+ return;
+ }
+ /* Increase drive strength of the sensor clock output */
+ s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
+}
+
+static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
+ .frequency = 400000U,
+ .sda_delay = 200,
+};
+
static struct platform_device *nuri_devices[] __initdata = {
/* Samsung Platform Devices */
&s3c_device_i2c5, /* PMIC should initialize first */
+ &s3c_device_i2c0,
&emmc_fixed_voltage,
+ &s5p_device_mipi_csis0,
+ &s5p_device_fimc0,
+ &s5p_device_fimc1,
+ &s5p_device_fimc2,
+ &s5p_device_fimc3,
&s5p_device_fimd0,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
@@ -1137,6 +1282,8 @@ static struct platform_device *nuri_devices[] __initdata = {
&s5p_device_mfc_r,
&exynos4_device_pd[PD_MFC],
&exynos4_device_pd[PD_LCD0],
+ &exynos4_device_pd[PD_CAM],
+ &s5p_device_fimc_md,
/* NURI Devices */
&nuri_gpio_keys,
@@ -1144,6 +1291,8 @@ static struct platform_device *nuri_devices[] __initdata = {
&nuri_backlight_device,
&max8903_fixed_reg_dev,
&nuri_max8903_device,
+ &cam_vdda_fixed_rdev,
+ &cam_8m_12v_fixed_rdev,
};
static void __init nuri_map_io(void)
@@ -1164,6 +1313,7 @@ static void __init nuri_machine_init(void)
nuri_tsp_init();
nuri_power_init();
+ s3c_i2c0_set_platdata(&nuri_i2c0_platdata);
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
s3c_i2c3_set_platdata(&i2c3_data);
i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
@@ -1175,6 +1325,8 @@ static void __init nuri_machine_init(void)
s5p_fimd0_set_platdata(&nuri_fb_pdata);
+ nuri_camera_init();
+
nuri_ehci_init();
clk_xusbxti.rate = 24000000;
@@ -1182,6 +1334,12 @@ static void __init nuri_machine_init(void)
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+
+ s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+ s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+ s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+ s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+ s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
}
MACHINE_START(NURI, "NURI")
--
1.7.6.3
^ permalink raw reply related
* [patch] ARM: smpboot: Enable interrupts after marking CPU online/active
From: Amit Kachhap @ 2011-10-07 14:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1110071354310.3240@ionos>
On 7 October 2011 17:47, Thomas Gleixner <tglx@linutronix.de> wrote:
> On Fri, 7 Oct 2011, Kukjin Kim wrote:
>> I think, basically, if SPIs in GIC are used in local timer, the routing
>> interrupt like calling irq_set_affinity() to offline CPUs should be
>> available when boot time before calling set_cpu_online() because as you know
>> the local_timer_setup() which includes setup interrupt is called in
>> percpu_timer_setup() now...
>>
>> Is there any way to get the flags of struct irqaction from struct irq_data
>> in gic_set_affinity()? Or?
>
> No, and you should not even think about it at all.
>
> The problem I can see from all this discussion is related to the early
> enabling of interrupts and the per cpu timer setup before the cpu is
> marked online. I really do not understand at all why this needs to be
> done in order to call calibrate_delay().
>
> calibrate_delay() monitors jiffies, which are updated from the CPU
> which is waiting for the new CPU to set the online bit.
>
> So you simply can call calibrate_delay() on the new CPU just from the
> interrupt disabled region and move the local timer setup after you
> stored the cpu data and before enabling interrupts.
>
> This solves both the cpu_online vs. cpu_active problem and the
> affinity setting of the per cpu timers.
>
> Thanks,
>
> ? ? ? ?tglx
> ----
> Index: linux-2.6/arch/arm/kernel/smp.c
> ===================================================================
> --- linux-2.6.orig/arch/arm/kernel/smp.c
> +++ linux-2.6/arch/arm/kernel/smp.c
> @@ -301,17 +301,7 @@ asmlinkage void __cpuinit secondary_star
> ? ? ? ? */
> ? ? ? ?platform_secondary_init(cpu);
>
> - ? ? ? /*
> - ? ? ? ?* Enable local interrupts.
> - ? ? ? ?*/
> ? ? ? ?notify_cpu_starting(cpu);
> - ? ? ? local_irq_enable();
> - ? ? ? local_fiq_enable();
> -
> - ? ? ? /*
> - ? ? ? ?* Setup the percpu timer for this CPU.
> - ? ? ? ?*/
> - ? ? ? percpu_timer_setup();
>
> ? ? ? ?calibrate_delay();
>
> @@ -323,10 +313,23 @@ asmlinkage void __cpuinit secondary_star
> ? ? ? ? * before we continue.
> ? ? ? ? */
> ? ? ? ?set_cpu_online(cpu, true);
> +
> + ? ? ? /*
> + ? ? ? ?* Setup the percpu timer for this CPU.
> + ? ? ? ?*/
> + ? ? ? percpu_timer_setup();
I tested these modifications on samsung exynos4 platform and they work
fine with almost same bogomips. I also enabled cpu topology patches
and they also don't create any race conditions. Looks like a good
approach.
> +
> ? ? ? ?while (!cpu_active(cpu))
> ? ? ? ? ? ? ? ?cpu_relax();
>
> ? ? ? ?/*
> + ? ? ? ?* cpu_active bit is set, so it's safe to enable interrupts
> + ? ? ? ?* now.
> + ? ? ? ?*/
> + ? ? ? local_irq_enable();
> + ? ? ? local_fiq_enable();
> +
> + ? ? ? /*
> ? ? ? ? * OK, it's off to the idle thread for us
> ? ? ? ? */
> ? ? ? ?cpu_idle();
>
^ permalink raw reply
* Long stalls during boot with -next
From: Mark Brown @ 2011-10-07 14:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJuYYwTeAwZ-zRDyQwB73bHWn+NkoT2zxmuJkFW6Oph1CUijqA@mail.gmail.com>
On Fri, Oct 07, 2011 at 06:57:19PM +0530, Thomas Abraham wrote:
> On 7 October 2011 17:20, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> > I identified the problem here, the behaviour of LL_DEBUG was changed to
> > make it select DEBUG_ICEDCC by default which is unfortunate if one
> > doesn't have an EmbeddedICE connected.
> Thanks for your suggestion. The long stall during boot problem occurs
> on Samsung boards as well with linux-next. As per your suggestion, the
> following diff fixes this issue.
Excellent, I'm using this now - please add my
Tested-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
when you send it out properly!
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index 65cf8c6..035f5cd 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -120,6 +120,15 @@ choice
> Say Y here if you want the debug print routines to direct
> their output to the second serial port on these devices.
>
> + config DEBUG_SAMSUNG_UART
> + bool "Kernel low-level debugging messages via samsung serial port"
> + depends on PLAT_SAMSUNG
> + help
> + Say Y here if you want the debug print routines to direct
> + their output to the serial port for Samsung platforms. Choose
> + the uart port with the "S3C UART to use for low-level debug"
> + config option.
> +
> endchoice
>
> config EARLY_PRINTK
> @@ -139,7 +148,7 @@ config OC_ETM
> kernel code.
>
> config DEBUG_S3C_UART
> - depends on PLAT_SAMSUNG
> + depends on DEBUG_SAMSUNG_UART
> int "S3C UART to use for low-level debug"
> default "0"
> help
^ permalink raw reply
* [PATCH 0/5 v4] ARM Realview PCIX patch series
From: Colin Tuckley @ 2011-10-07 14:27 UTC (permalink / raw)
To: linux-arm-kernel
This is a resend of patches that were posted before with various
comments addressed and rebased to 3.1.0-rc9.
The following series implements adding PCI
support to the ARM Realview family of boards.
---
Colin Tuckley (5):
ARM Realview PCIX build file changes
Realview PCIX support - add main support module code
ARM Realview PCIX board file changes
ARM Realview PCIX IRQ include file changes
ARM Realview PCIX map include file changes
arch/arm/Kconfig | 3
arch/arm/mach-realview/Makefile | 5
arch/arm/mach-realview/include/mach/board-pb11mp.h | 11
arch/arm/mach-realview/include/mach/board-pba8.h | 11
arch/arm/mach-realview/include/mach/board-pbx.h | 11
arch/arm/mach-realview/include/mach/hardware.h | 22 +
arch/arm/mach-realview/include/mach/io.h | 8
arch/arm/mach-realview/include/mach/irqs-pb11mp.h | 11
arch/arm/mach-realview/include/mach/irqs-pba8.h | 7
arch/arm/mach-realview/include/mach/irqs-pbx.h | 7
arch/arm/mach-realview/include/mach/platform.h | 15 -
arch/arm/mach-realview/pcix.c | 472 ++++++++++++++++++++
arch/arm/mach-realview/realview_pb11mp.c | 18 +
arch/arm/mach-realview/realview_pba8.c | 18 +
arch/arm/mach-realview/realview_pbx.c | 16 +
15 files changed, 577 insertions(+), 58 deletions(-)
create mode 100755 arch/arm/mach-realview/pcix.c
--
^ permalink raw reply
* [PATCH 1/5 v4] ARM Realview PCIX map include file changes
From: Colin Tuckley @ 2011-10-07 14:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111007142310.19554.17204.stgit@e102602-lin.cambridge.arm.com>
This patch adds the memory map PCI support to the include
files for the Realview Northbridge based boards.
Signed-off-by: Colin Tuckley <colin.tuckley@arm.com>
---
arch/arm/mach-realview/include/mach/board-pb11mp.h | 11 ----------
arch/arm/mach-realview/include/mach/board-pba8.h | 11 ----------
arch/arm/mach-realview/include/mach/board-pbx.h | 11 ----------
arch/arm/mach-realview/include/mach/hardware.h | 22 +++++++++++++++++++-
arch/arm/mach-realview/include/mach/io.h | 8 +++++--
arch/arm/mach-realview/include/mach/platform.h | 15 ++------------
6 files changed, 29 insertions(+), 49 deletions(-)
diff --git a/arch/arm/mach-realview/include/mach/board-pb11mp.h b/arch/arm/mach-realview/include/mach/board-pb11mp.h
index 7abf918..0114edb 100644
--- a/arch/arm/mach-realview/include/mach/board-pb11mp.h
+++ b/arch/arm/mach-realview/include/mach/board-pb11mp.h
@@ -62,17 +62,6 @@
#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74
/*
- * PB11MPCore PCI regions
- */
-#define REALVIEW_PB11MP_PCI_BASE 0x90040000 /* PCI-X Unit base */
-#define REALVIEW_PB11MP_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
-#define REALVIEW_PB11MP_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
-
-#define REALVIEW_PB11MP_PCI_BASE_SIZE 0x10000 /* 16 Kb */
-#define REALVIEW_PB11MP_PCI_IO_SIZE 0x1000 /* 4 Kb */
-#define REALVIEW_PB11MP_PCI_MEM_SIZE 0x20000000 /* 512 MB */
-
-/*
* Testchip peripheral and fpga gic regions
*/
#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */
diff --git a/arch/arm/mach-realview/include/mach/board-pba8.h b/arch/arm/mach-realview/include/mach/board-pba8.h
index 4dfc67a..f8ad328 100644
--- a/arch/arm/mach-realview/include/mach/board-pba8.h
+++ b/arch/arm/mach-realview/include/mach/board-pba8.h
@@ -59,15 +59,4 @@
#define REALVIEW_PBA8_SYS_PLD_CTRL1 0x74
-/*
- * PBA8 PCI regions
- */
-#define REALVIEW_PBA8_PCI_BASE 0x90040000 /* PCI-X Unit base */
-#define REALVIEW_PBA8_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
-#define REALVIEW_PBA8_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
-
-#define REALVIEW_PBA8_PCI_BASE_SIZE 0x10000 /* 16 Kb */
-#define REALVIEW_PBA8_PCI_IO_SIZE 0x1000 /* 4 Kb */
-#define REALVIEW_PBA8_PCI_MEM_SIZE 0x20000000 /* 512 MB */
-
#endif /* __ASM_ARCH_BOARD_PBA8_H */
diff --git a/arch/arm/mach-realview/include/mach/board-pbx.h b/arch/arm/mach-realview/include/mach/board-pbx.h
index 848bfff..93a975e 100644
--- a/arch/arm/mach-realview/include/mach/board-pbx.h
+++ b/arch/arm/mach-realview/include/mach/board-pbx.h
@@ -70,17 +70,6 @@
#define REALVIEW_PBX_SYS_PLD_CTRL1 0x74
/*
- * PBX PCI regions
- */
-#define REALVIEW_PBX_PCI_BASE 0x90040000 /* PCI-X Unit base */
-#define REALVIEW_PBX_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
-#define REALVIEW_PBX_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
-
-#define REALVIEW_PBX_PCI_BASE_SIZE 0x10000 /* 16 Kb */
-#define REALVIEW_PBX_PCI_IO_SIZE 0x1000 /* 4 Kb */
-#define REALVIEW_PBX_PCI_MEM_SIZE 0x20000000 /* 512 MB */
-
-/*
* Core tile identification (REALVIEW_SYS_PROCID)
*/
#define REALVIEW_PBX_PROC_MASK 0xFF000000
diff --git a/arch/arm/mach-realview/include/mach/hardware.h b/arch/arm/mach-realview/include/mach/hardware.h
index 8a638d1..d7d01f2 100644
--- a/arch/arm/mach-realview/include/mach/hardware.h
+++ b/arch/arm/mach-realview/include/mach/hardware.h
@@ -24,6 +24,26 @@
#include <asm/sizes.h>
+/*
+ * PCI space virtual addresses
+ */
+#define REALVIEW_PCI_VIRT_BASE (void __iomem *)0xF8000000ul
+#define REALVIEW_PCI_CFG_VIRT_BASE (void __iomem *)0xF9000000ul
+#define PCIX_UNIT_BASE (void __iomem *)0xF8000000ul
+#define REALVIEW_PCI_IO_VBASE (void __iomem *)0xFA000000ul
+/*
+ * PCI space physical addresses and sizes
+ */
+#define REALVIEW_PB_PCI_BASE 0x90040000 /* PCI-X Unit base */
+#define REALVIEW_PB_PCI_BASE_SIZE 0x00010000 /* 4 Kb + 60Kb reserved */
+#define REALVIEW_PB_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
+#define REALVIEW_PB_PCI_IO_SIZE 0x00010000 /* 64 Kb */
+#define REALVIEW_PB_PCI_IO_LIMIT (REALVIEW_PB_PCI_IO_BASE + REALVIEW_PB_PCI_IO_SIZE - 1)
+#define REALVIEW_PB_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
+#define REALVIEW_PB_PCI_MEM_SIZE 0x20000000 /* 512 MB */
+
+#define REALVIEW_ISSP_REG_BASE 0x100E3000
+
/* macro to get at IO space when running virtually */
#ifdef CONFIG_MMU
/*
@@ -37,6 +57,6 @@
#else
#define IO_ADDRESS(x) (x)
#endif
-#define __io_address(n) __io(IO_ADDRESS(n))
+#define __io_address(n) __typesafe_io(IO_ADDRESS(n))
#endif
diff --git a/arch/arm/mach-realview/include/mach/io.h b/arch/arm/mach-realview/include/mach/io.h
index f05bcdf..016f294 100644
--- a/arch/arm/mach-realview/include/mach/io.h
+++ b/arch/arm/mach-realview/include/mach/io.h
@@ -20,9 +20,13 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
-#define IO_SPACE_LIMIT 0xffffffff
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0x0000ffff
+
+#define __io(a) (REALVIEW_PCI_IO_VBASE + (a & IO_SPACE_LIMIT))
-#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif
diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h
index 1b77a27..75bddc4 100644
--- a/arch/arm/mach-realview/include/mach/platform.h
+++ b/arch/arm/mach-realview/include/mach/platform.h
@@ -77,6 +77,7 @@
#define REALVIEW_SYS_BOOTCS_OFFSET 0x58
#define REALVIEW_SYS_24MHz_OFFSET 0x5C
#define REALVIEW_SYS_MISC_OFFSET 0x60
+#define REALVIEW_SYS_PCI_STAT_OFFSET 0x6C
#define REALVIEW_SYS_IOSEL_OFFSET 0x70
#define REALVIEW_SYS_PROCID_OFFSET 0x84
#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
@@ -111,6 +112,7 @@
#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
+#define REALVIEW_SYS_PCI_STAT (REALVIEW_SYS_BASE + REALVIEW_SYS_PCI_STAT_OFFSET)
#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
@@ -174,19 +176,6 @@
#define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */
#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
-/* PCI space */
-#define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */
-#define REALVIEW_PCI_CFG_BASE 0x42000000
-#define REALVIEW_PCI_MEM_BASE0 0x44000000
-#define REALVIEW_PCI_MEM_BASE1 0x50000000
-#define REALVIEW_PCI_MEM_BASE2 0x60000000
-/* Sizes of above maps */
-#define REALVIEW_PCI_BASE_SIZE 0x01000000
-#define REALVIEW_PCI_CFG_BASE_SIZE 0x02000000
-#define REALVIEW_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
-#define REALVIEW_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
-#define REALVIEW_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
-
#define REALVIEW_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
#define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */
^ permalink raw reply related
* [PATCH 2/5 v4] ARM Realview PCIX IRQ include file changes
From: Colin Tuckley @ 2011-10-07 14:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111007142310.19554.17204.stgit@e102602-lin.cambridge.arm.com>
This patch adds the Interrupt definitions for the PCI
support on the Realview boards.
Signed-off-by: Colin Tuckley <colin.tuckley@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm/mach-realview/include/mach/irqs-pb11mp.h | 11 +++++++++++
arch/arm/mach-realview/include/mach/irqs-pba8.h | 7 ++++++-
arch/arm/mach-realview/include/mach/irqs-pbx.h | 7 ++++++-
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-realview/include/mach/irqs-pb11mp.h b/arch/arm/mach-realview/include/mach/irqs-pb11mp.h
index 34e255a..cd3e3e6 100644
--- a/arch/arm/mach-realview/include/mach/irqs-pb11mp.h
+++ b/arch/arm/mach-realview/include/mach/irqs-pb11mp.h
@@ -95,6 +95,17 @@
#define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */
#define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */
+/* These PCI/PCIe IRQ definitions are here as placeholders
+ * The PCI code actually calculates the irq used at runtime */
+#define IRQ_PB11MP_PCI0 (IRQ_PB11MP_GIC_START + 50)
+#define IRQ_PB11MP_PCI1 (IRQ_PB11MP_GIC_START + 51)
+#define IRQ_PB11MP_PCI2 (IRQ_PB11MP_GIC_START + 52)
+#define IRQ_PB11MP_PCI3 (IRQ_PB11MP_GIC_START + 53)
+#define IRQ_PB11MP_PCIE0 (IRQ_PB11MP_GIC_START + 54)
+#define IRQ_PB11MP_PCIE1 (IRQ_PB11MP_GIC_START + 55)
+#define IRQ_PB11MP_PCIE2 (IRQ_PB11MP_GIC_START + 56)
+#define IRQ_PB11MP_PCIE3 (IRQ_PB11MP_GIC_START + 57)
+
#define IRQ_PB11MP_SMC -1
#define IRQ_PB11MP_SCTL -1
diff --git a/arch/arm/mach-realview/include/mach/irqs-pba8.h b/arch/arm/mach-realview/include/mach/irqs-pba8.h
index 4a88a4e..da6d583 100644
--- a/arch/arm/mach-realview/include/mach/irqs-pba8.h
+++ b/arch/arm/mach-realview/include/mach/irqs-pba8.h
@@ -61,11 +61,16 @@
#define IRQ_PBA8_PMU (IRQ_PBA8_GIC_START + 47) /* Cortex-A8 PMU */
-/* ... */
+/* These PCI/PCIe IRQ definitions are here as placeholders
+ * The PCI code actually calculates the irq used at runtime */
#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50)
#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51)
#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52)
#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53)
+#define IRQ_PBA8_PCIE0 (IRQ_PBA8_GIC_START + 54)
+#define IRQ_PBA8_PCIE1 (IRQ_PBA8_GIC_START + 55)
+#define IRQ_PBA8_PCIE2 (IRQ_PBA8_GIC_START + 56)
+#define IRQ_PBA8_PCIE3 (IRQ_PBA8_GIC_START + 57)
#define IRQ_PBA8_SMC -1
#define IRQ_PBA8_SCTL -1
diff --git a/arch/arm/mach-realview/include/mach/irqs-pbx.h b/arch/arm/mach-realview/include/mach/irqs-pbx.h
index 206a300..f661702 100644
--- a/arch/arm/mach-realview/include/mach/irqs-pbx.h
+++ b/arch/arm/mach-realview/include/mach/irqs-pbx.h
@@ -76,11 +76,16 @@
#define IRQ_PBX_PMU_CPU2 (IRQ_PBX_GIC_START + 46)
#define IRQ_PBX_PMU_CPU3 (IRQ_PBX_GIC_START + 47)
-/* ... */
+/* These PCI/PCIe IRQ definitions are here as placeholders
+ * The PCI code actually calculates the irq used at runtime */
#define IRQ_PBX_PCI0 (IRQ_PBX_GIC_START + 50)
#define IRQ_PBX_PCI1 (IRQ_PBX_GIC_START + 51)
#define IRQ_PBX_PCI2 (IRQ_PBX_GIC_START + 52)
#define IRQ_PBX_PCI3 (IRQ_PBX_GIC_START + 53)
+#define IRQ_PBX_PCIE0 (IRQ_PBX_GIC_START + 54)
+#define IRQ_PBX_PCIE1 (IRQ_PBX_GIC_START + 55)
+#define IRQ_PBX_PCIE2 (IRQ_PBX_GIC_START + 56)
+#define IRQ_PBX_PCIE3 (IRQ_PBX_GIC_START + 57)
#define IRQ_PBX_SMC -1
#define IRQ_PBX_SCTL -1
^ permalink raw reply related
* [PATCH 3/5 v4] ARM Realview PCIX board file changes
From: Colin Tuckley @ 2011-10-07 14:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111007142310.19554.17204.stgit@e102602-lin.cambridge.arm.com>
This patch adds the PCI support to the board files
for the Realview Northbridge boards.
Signed-off-by: Colin Tuckley <colin.tuckley@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm/mach-realview/realview_pb11mp.c | 18 ++++++++++++++++++
arch/arm/mach-realview/realview_pba8.c | 18 ++++++++++++++----
arch/arm/mach-realview/realview_pbx.c | 16 +++++++++++++---
3 files changed, 45 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index b43644b..17a3340 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -95,6 +95,24 @@ static struct map_desc realview_pb11mp_io_desc[] __initdata = {
.length = SZ_8K,
.type = MT_DEVICE,
},
+#ifdef CONFIG_PCI
+ {
+ .virtual = (unsigned long)PCIX_UNIT_BASE,
+ .pfn = __phys_to_pfn(REALVIEW_PB_PCI_BASE),
+ .length = REALVIEW_PB_PCI_BASE_SIZE,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)REALVIEW_PCI_IO_VBASE,
+ .pfn = __phys_to_pfn(REALVIEW_PB_PCI_IO_BASE),
+ .length = REALVIEW_PB_PCI_IO_SIZE,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_ISSP_REG_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_ISSP_REG_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+#endif
#ifdef CONFIG_DEBUG_LL
{
.virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 763e8f3..1ed9dd8 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -79,10 +79,20 @@ static struct map_desc realview_pba8_io_desc[] __initdata = {
},
#ifdef CONFIG_PCI
{
- .virtual = PCIX_UNIT_BASE,
- .pfn = __phys_to_pfn(REALVIEW_PBA8_PCI_BASE),
- .length = REALVIEW_PBA8_PCI_BASE_SIZE,
- .type = MT_DEVICE
+ .virtual = (unsigned long)PCIX_UNIT_BASE,
+ .pfn = __phys_to_pfn(REALVIEW_PB_PCI_BASE),
+ .length = REALVIEW_PB_PCI_BASE_SIZE,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)REALVIEW_PCI_IO_VBASE,
+ .pfn = __phys_to_pfn(REALVIEW_PB_PCI_IO_BASE),
+ .length = REALVIEW_PB_PCI_IO_SIZE,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_ISSP_REG_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_ISSP_REG_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
},
#endif
#ifdef CONFIG_DEBUG_LL
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 363b0ab..1d7d191 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -80,9 +80,19 @@ static struct map_desc realview_pbx_io_desc[] __initdata = {
},
#ifdef CONFIG_PCI
{
- .virtual = PCIX_UNIT_BASE,
- .pfn = __phys_to_pfn(REALVIEW_PBX_PCI_BASE),
- .length = REALVIEW_PBX_PCI_BASE_SIZE,
+ .virtual = (unsigned long)PCIX_UNIT_BASE,
+ .pfn = __phys_to_pfn(REALVIEW_PB_PCI_BASE),
+ .length = REALVIEW_PB_PCI_BASE_SIZE,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)REALVIEW_PCI_IO_VBASE,
+ .pfn = __phys_to_pfn(REALVIEW_PB_PCI_IO_BASE),
+ .length = REALVIEW_PB_PCI_IO_SIZE,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_ISSP_REG_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_ISSP_REG_BASE),
+ .length = SZ_4K,
.type = MT_DEVICE,
},
#endif
^ permalink raw reply related
* [PATCH 4/5 v4] Realview PCIX support - add main support module code
From: Colin Tuckley @ 2011-10-07 14:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111007142310.19554.17204.stgit@e102602-lin.cambridge.arm.com>
This patch adds pcix.c - the main pci sub-system code for
the RealView boards which have PCI and PCIe interfaces
via a custom NEC northbridge chip and two bridges.
Signed-off-by: Colin Tuckley <colin.tuckley@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm/mach-realview/pcix.c | 472 +++++++++++++++++++++++++++++++++++++++++
1 files changed, 472 insertions(+), 0 deletions(-)
create mode 100755 arch/arm/mach-realview/pcix.c
diff --git a/arch/arm/mach-realview/pcix.c b/arch/arm/mach-realview/pcix.c
new file mode 100755
index 0000000..44e8bda
--- /dev/null
+++ b/arch/arm/mach-realview/pcix.c
@@ -0,0 +1,472 @@
+/*
+ * Realview PCI-X Support
+ *
+ * Copyright (C) 2007-2011 ARM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <mach/platform.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/mach/pci.h>
+
+#define PCIX_READ_ACCESS 0x06000000
+#define PCIX_WRITE_ACCESS 0x07000000
+
+/* PCI-X Configuration registers */
+#define PCI_PTBADDR0L 0x10
+#define PCI_PTBADDR0M 0x14
+#define PCI_PTBADDR1L 0x18
+#define PCI_PTBADDR1M 0x1C
+#define PCI_CFGADDR 0x40
+#define PCI_CFGDATA 0x44
+#define PCI_CFGATTR 0x48
+#define PCI_PINTACNT 0x50
+#define PCI_PINTXSTAT 0x54
+#define PCI_PINTXMASK 0x58
+#define PCI_SERRSTAT 0x5C
+#define PCI_PERRADDRL 0x60
+#define PCI_PERRADDRH 0x64
+#define PCI_PERRSTAT 0x68
+#define PCI_PERRMASK 0x6C
+#define PCI_OCBERRSTAT 0x78
+#define PCI_OCBERRMASK 0x7C
+#define PCI_MSICAPID 0x80
+#define PCI_MSINXTCAP 0x81
+#define PCI_MSGCNT 0x82
+#define PCI_MSGADDR 0x84
+#define PCI_MSGUPADDR 0x88
+#define PCI_MSGDATA 0x8C
+#define PCI_PCIXCAPID 0x90
+#define PCI_PCIXNXTCAP 0x91
+#define PCI_PCIXCOMMAND 0x92
+#define PCI_PCIXSTAT 0x94
+#define PCI_SPCMPERRMSG 0x98
+#define PCI_PTMEMSEG0 0xA0
+#define PCI_PTMEMMSK0 0xA4
+#define PCI_PTMEMENSW0 0xA8
+#define PCI_PTMEMSEG1 0xB0
+#define PCI_PTMEMMSK1 0xB4
+#define PCI_PTMEMENSW1 0xB8
+#define PCI_PMSEGL 0xC0
+#define PCI_PMSEGH 0xC4
+#define PCI_DRSTCNT 0xEC
+#define PCI_PRST 0xF0
+#define PCI_UNITCNT 0xF4
+#define PCI_CNTOTIMER 0xF8
+#define PCI_PSLADAFLASH 0xFC
+
+static int irq_gic_start;
+
+/*
+ * Software is exposed to downstream half of the PCI-X bridge registers
+ * rather than a real PCI interface. Therefore there's no config memory
+ * region as such.
+ *
+ * PCI Regions:
+ * MEM 0xA0000000 - 0xBFFFFFFF
+ * IO 0x00000000 - 0x0000FFFF
+ * CONFIG -
+ */
+
+static void realview_pb_pcix_sync(void)
+{
+ readl(PCIX_UNIT_BASE + PCI_VENDOR_ID);
+}
+
+static void realview_pb_pcix_unit_init(void)
+{
+ u32 data = readl(PCIX_UNIT_BASE + PCI_UNITCNT);
+
+ if (data & 0x10)
+ writel(0x00000000, PCIX_UNIT_BASE + PCI_PRST); /* Assert PCI reset */
+ else {
+ printk(KERN_ERR "Error: PCI-X unit not in PCI-X mode.\n");
+ writel(data | 0x80000000, PCIX_UNIT_BASE + PCI_UNITCNT);
+ }
+
+ writew(0x0006, PCIX_UNIT_BASE + PCI_COMMAND); /* Master-Memory enable */
+ writew(0xfb30, PCIX_UNIT_BASE + PCI_STATUS); /* Error bit clear */
+
+ writeb(0x08, PCIX_UNIT_BASE + PCI_CACHE_LINE_SIZE); /* Cache line size */
+ writeb(0x40, PCIX_UNIT_BASE + PCI_LATENCY_TIMER); /* Latency Timer */
+
+ /* Master Segment Address[31:24] */
+ writel(0x00000003, PCIX_UNIT_BASE + PCI_PMSEGL); /* no swap */
+ /* Master Segment Address[63:32] */
+ writel(0x00000000, PCIX_UNIT_BASE + PCI_PMSEGH);
+
+ /* Data endian swap mode */
+ writel(0x00000003, PCIX_UNIT_BASE + PCI_PTMEMENSW0); /* no swap */
+ writel(0x00000003, PCIX_UNIT_BASE + PCI_PTMEMENSW1); /* no swap */
+
+#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
+ /* 512MB of DMA capable RAM is available - mapped at 0x70000000
+ * Note :- 0x70000000 is *not* on a 512MB boundary so it
+ * must be mapped in two parts */
+ /* Window#0 256MB and enable */
+ writel(0x0fff0001, PCIX_UNIT_BASE + PCI_PTMEMMSK0);
+ /* Window#1 256MB and enable */
+ writel(0x0fff0001, PCIX_UNIT_BASE + PCI_PTMEMMSK1);
+
+ /* Window base address setting */
+ /* Memory Base Address, Ptrefetch Disable, 64bit */
+ writel(0x70000004, PCIX_UNIT_BASE + PCI_PTBADDR0L);
+ /* Memory Base Address[63:32] */
+ writel(0x00000000, PCIX_UNIT_BASE + PCI_PTBADDR0M);
+
+ /* Memory Base Address, Ptrefetch Disable, 64bit */
+ writel(0x80000004, PCIX_UNIT_BASE + PCI_PTBADDR1L);
+ /* Memory Base Address[63:32] */
+ writel(0x00000000, PCIX_UNIT_BASE + PCI_PTBADDR1M);
+#else
+ /* Only 256MB of RAM is available - mapped at zero */
+ /* Window#0 256MB and enable */
+ writel(0x0fff0001, PCIX_UNIT_BASE + PCI_PTMEMMSK0);
+ /* Window#1 Disable */
+ writel(0x00000000, PCIX_UNIT_BASE + PCI_PTMEMMSK1);
+
+ /* Window base address setting */
+ /* Memory Base Address, Ptrefetch Disable, 64bit */
+ writel(0x00000004, PCIX_UNIT_BASE + PCI_PTBADDR0L);
+ /* Memory Base Address[63:32] */
+ writel(0x00000000, PCIX_UNIT_BASE + PCI_PTBADDR0M);
+
+ /* Memory Base Address, Ptrefetch Disable, 64bit */
+ writel(0x00000004, PCIX_UNIT_BASE + PCI_PTBADDR1L);
+ /* Memory Base Address[63:32] */
+ writel(0x00000000, PCIX_UNIT_BASE + PCI_PTBADDR1M);
+#endif
+
+ /* OnChipBus Address#0[35:24] */
+ writel(0x00000000, PCIX_UNIT_BASE + PCI_PTMEMSEG0);
+ /* OnChipBus Address#1[35:24] */
+ writel(0x00000000, PCIX_UNIT_BASE + PCI_PTMEMSEG1);
+
+ /* 66MHz, 64bit device */
+ writel(0x00010000, PCIX_UNIT_BASE + PCI_PCIXSTAT);
+ /* Interrupt Mask */
+ writel(0x00000000, PCIX_UNIT_BASE + PCI_PINTXMASK);
+ /* Enable PCI error status */
+ writel(0x000307f7, PCIX_UNIT_BASE + PCI_PERRMASK);
+ /* Clear PCI error status */
+ writel(0x000307f7, PCIX_UNIT_BASE + PCI_PERRSTAT);
+ /* Enable count out */
+ writel(0x10FFFFFF, PCIX_UNIT_BASE + PCI_CNTOTIMER);
+
+ realview_pb_pcix_sync();
+ udelay(1500); /* Allow hardware to settle as per NEC docs and example */
+
+ /* Deassert PCI reset */
+ writel(0x00000001, PCIX_UNIT_BASE + PCI_PRST);
+ /* Initial end, Enable arbiter */
+ writel(data | 0x80000020, PCIX_UNIT_BASE + PCI_UNITCNT);
+ realview_pb_pcix_sync();
+ udelay(1500); /* Allow hardware to settle as per NEC docs and example */
+
+ /* Enable bursts on PCI-X */
+ writel(0x1, __io_address(REALVIEW_ISSP_REG_BASE + 0x18));
+}
+
+static void realview_pb_pcix_set_attr(unsigned int tag)
+{
+ /* Get Device and Funcion number */
+ u32 data = readl(PCIX_UNIT_BASE + PCI_PCIXSTAT) & 0x0ff;
+ /* attribute set */
+ writel(tag | (data << 8), PCIX_UNIT_BASE + PCI_CFGATTR);
+}
+
+static int realview_pb_pcix_set_config(u32 bus, u32 dev, u32 func, int offset)
+{
+ u32 mode;
+ u32 config_addr;
+
+ writel(0x000307F7, PCIX_UNIT_BASE + PCI_PERRSTAT); /* clear error bit */
+ writew(0xfb30, PCIX_UNIT_BASE + PCI_STATUS); /* error bit clear */
+
+ if (bus == 0) {
+ /* Type0 Configuration cycle */
+ mode = readl(PCIX_UNIT_BASE + PCI_UNITCNT);
+ if (mode & 0x1) {
+ /* check PCI mode */
+ printk(KERN_ERR "PCI mode detected during config cycle"
+ "attempt. Should really be in PCI-X mode.\n");
+ BUG();
+ } else {
+ /* PCI-X Mode
+ *
+ * Note that the root complex appears as id 0x1f
+ * since we don't want to allocate this as a device
+ * we stop scanning before we find it.
+ */
+ if (dev < 0x10 || dev > 0x1e) {
+ realview_pb_pcix_sync();
+ return -1;
+ }
+ config_addr = (1 << dev) | ((dev & 0x1f) << 11) |
+ ((func & 0x7) << 8) | (offset & 0xfc);
+ writel(config_addr, PCIX_UNIT_BASE + PCI_CFGADDR);
+ }
+ } else {
+ config_addr = ((bus & 0xff) << 16) | ((dev & 0x1f) << 11) |
+ ((func & 0x7) << 8) | (offset & 0xfc) | 0x1;
+ /* Type1 Configuration cycle */
+ writel(config_addr, PCIX_UNIT_BASE + PCI_CFGADDR);
+ }
+ realview_pb_pcix_sync();
+ return 0;
+}
+
+int realview_pb_pcix_check_error(void)
+{
+ u32 data;
+ realview_pb_pcix_sync();
+ data = readl(PCIX_UNIT_BASE + PCI_PERRSTAT);
+ if (data) {
+ writel(data, PCIX_UNIT_BASE + PCI_PERRSTAT);
+ return data;
+ }
+ return 0;
+}
+
+int realview_pb_pcix_read_config(struct pci_bus *pbus, u32 devfn,
+ int offset, int size, u32 *data)
+{
+ u32 bus = pbus->number;
+ u32 slot = PCI_SLOT(devfn);
+ u32 function = PCI_FUNC(devfn);
+
+ realview_pb_pcix_set_attr(PCIX_READ_ACCESS);
+ if (realview_pb_pcix_set_config(bus, slot, function, offset) != 0) {
+ *data = ((size == 1) ? 0xFF : ((size == 2) ? 0xFFFF : 0xFFFFFFFF));
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+ switch (size) {
+ case 1:
+ *data = (readl(PCIX_UNIT_BASE + PCI_CFGDATA) >>
+ (8 * (offset & 3))) & 0xff;
+ break;
+ case 2:
+ *data = (u32)readw(PCIX_UNIT_BASE + PCI_CFGDATA +
+ (offset & 3));
+ break;
+ default:
+ *data = readl(PCIX_UNIT_BASE + PCI_CFGDATA);
+ }
+ /* Error codes from downstream bus don't mean much for software. */
+ if (!realview_pb_pcix_check_error())
+ return PCIBIOS_SUCCESSFUL;
+
+ return PCIBIOS_DEVICE_NOT_FOUND;
+}
+
+int realview_pb_pcix_write_config(struct pci_bus *pbus, u32 devfn,
+ int offset, int size, u32 data)
+{
+ u32 slot = PCI_SLOT(devfn);
+ u32 function = PCI_FUNC(devfn);
+ u32 bus = pbus->number;
+ int err;
+
+ realview_pb_pcix_set_attr(PCIX_WRITE_ACCESS);
+ if (realview_pb_pcix_set_config(bus, slot, function, offset) != 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ switch (size) {
+ case 1:
+ writeb(data, PCIX_UNIT_BASE + PCI_CFGDATA + (offset & 3));
+ break;
+ case 2:
+ writew(data, PCIX_UNIT_BASE + PCI_CFGDATA + (offset & 3));
+ break;
+ default:
+ writel(data, PCIX_UNIT_BASE + PCI_CFGDATA);
+ break;
+ }
+ /* Write errors don't really matter */
+ err = realview_pb_pcix_check_error();
+ realview_pb_pcix_set_attr(PCIX_READ_ACCESS);
+ return err;
+}
+
+static struct pci_ops pci_realview_pb_ops = {
+ .read = realview_pb_pcix_read_config,
+ .write = realview_pb_pcix_write_config,
+};
+
+static int __init pci_realview_pb_setup(int nr, struct pci_sys_data *sys)
+{
+ if (machine_is_realview_pb11mp())
+ irq_gic_start = IRQ_PB11MP_GIC_START;
+ else
+ irq_gic_start = IRQ_PBA8_GIC_START;
+
+ realview_pb_pcix_unit_init();
+
+ /* set bus->cpu mapping */
+ sys->mem_offset = 0;
+ sys->io_offset = REALVIEW_PB_PCI_IO_BASE;
+
+ /* Note: we don't reserve the addresses for PCI space here because the
+ * window allocator won't be able to get any if we do.
+ */
+
+ return 1;
+}
+
+
+static struct pci_bus *pci_realview_pb_scan_bus(int nr, struct pci_sys_data *sys)
+{
+ return pci_scan_bus(sys->busnr, &pci_realview_pb_ops, sys);
+}
+
+static void __init pci_realview_pb_preinit(void)
+{
+ pcibios_min_io = 0x1000;
+ pcibios_min_mem = REALVIEW_PB_PCI_MEM_BASE;
+
+ u32 data = readl(__io_address(REALVIEW_SYS_PCI_STAT));
+ data &= ~0x00000100; /* Clear the Clock Control bit */
+ writel(data, __io_address(REALVIEW_SYS_PCI_STAT));
+ udelay(1500); /* Allow hardware to settle as per NEC docs and example */
+}
+
+static struct pci_dev *pcie_bridge;
+
+/* Maps scrambled IRQ pins to IRQ lines. Scrambling depends on device slot. */
+static int __init pci_realview_pb_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ int irq;
+ int devslot = PCI_SLOT(dev->devfn);
+
+ /* Upstream port of 8518 device */
+ if (unlikely(dev->device == 0x8518 && dev->bus->primary == 0)) {
+ BUG_ON(pcie_bridge); /* Can't be already assigned */
+ pcie_bridge = dev;
+ }
+
+ if (pcie_bridge) {
+ if (dev->bus->primary >= pcie_bridge->bus->secondary &&
+ dev->bus->primary <= pcie_bridge->bus->subordinate) {
+ /*
+ * The problem is that in PCIE in different slots a device
+ * could still get the same slot/pin/devslot triplet. Therefore
+ * we check the slot/pin/devslot triplet of an underlying PCIE port.
+ *
+ * pin slot: 0 1 2 3 4
+ * #A(1) 56 55 54 57 56
+ * #B(2) 57 56 55 54 57
+ * #C(3) 54 57 56 55 54
+ * #D(4) 55 54 57 56 55
+ */
+
+ if (dev->bus->self) {
+ /* We do have a bus above us
+ * Device is right behind a PCIE hub port, and its not a PCIE
+ * hub port itself. */
+ if (dev->bus->self->device == 0x8518 &&
+ dev->device != 0x8518) {
+ /* Depend on devslot of 8518 port we're connected to */
+ devslot = PCI_SLOT(dev->bus->self->devfn);
+ /* These are the two cases for PCIE ports on PB boards.
+ * Any other downstream bus topology (e.g. with further
+ * PCIE bridges) does not scramble, and get the same
+ * irq number as the upstream bus. */
+ irq = irq_gic_start + 54 + ((devslot & 3) + (pin - 1)) % 4;
+ } else if ((dev->bus->self->class & 0xff0000) == 0x060000 &&
+ (dev->class & 0xff0000) != 0x060000) {
+ /* It's a device behind a bridge that isn't an 8518 */
+ irq = irq_gic_start + 54 + ((devslot & 3) + pin +
+ PCI_SLOT(dev->bus->self->bus->self->devfn) - 1) % 4;
+ } else {
+ /* It's another bridge */
+ irq = dev->bus->self->irq;
+ }
+ } else
+ irq = 0;
+
+ printk(KERN_INFO "PCI Express irq mapping: device: 0x%x, slot %d, pin %d, devslot %d, irq: %d\n",
+ dev->device, slot, pin, devslot, irq);
+
+ return irq;
+ }
+ }
+
+ /*
+ * pin slot: 0 1 2 3
+ * #A 53 52 51 50
+ * #B 50 53 52 51
+ * #C 51 50 53 52
+ * #D 52 51 50 53
+ */
+
+ irq = irq_gic_start + 50 + (((pin - 1) + 3 - (devslot & 3)) & 3);
+
+ printk(KERN_INFO "PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",
+ slot, pin, devslot, irq);
+
+ return irq;
+
+}
+
+static struct hw_pci realview_pb_pcix __initdata = {
+ .swizzle = NULL,
+ .map_irq = pci_realview_pb_map_irq,
+ .nr_controllers = 1,
+ .setup = pci_realview_pb_setup,
+ .scan = pci_realview_pb_scan_bus,
+ .preinit = pci_realview_pb_preinit
+};
+
+static int __init realview_pb_pcix_init(void)
+{
+ if (machine_is_realview_pb11mp() ||
+ machine_is_realview_pba8() || machine_is_realview_pbx())
+ pci_common_init(&realview_pb_pcix);
+ return 0;
+}
+
+subsys_initcall(realview_pb_pcix_init);
+
+static int max_rrq __devinitdata = 4096;
+
+static void __devinit find_max_rrq(struct pci_dev *dev)
+{
+ /* Set the max read request size for all devices to the
+ * smallest in the tree and limit it to 4096.
+ * This is a workaround for a root complex
+ * bug. So far, the only device we've seen
+ * that fails without this is the Marvell Yukon 88E8053 but
+ * this may fix other devices too.
+ */
+ int rrq = pcie_get_readrq(dev);
+ if (rrq > 0 && rrq < max_rrq)
+ max_rrq = rrq;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, find_max_rrq);
+
+static void __devinit set_max_rrq(struct pci_dev *dev)
+{
+ pcie_set_readrq(dev, max_rrq);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, set_max_rrq);
^ permalink raw reply related
* [PATCH 5/5 v4] ARM Realview PCIX build file changes
From: Colin Tuckley @ 2011-10-07 14:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111007142310.19554.17204.stgit@e102602-lin.cambridge.arm.com>
This patch adds PCI support for the Realview boards
to the mach-realview build system.
Signed-off-by: Colin Tuckley <colin.tuckley@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm/Kconfig | 3 +++
arch/arm/mach-realview/Makefile | 5 +++++
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3146ed3..3157f65 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -261,6 +261,7 @@ config ARCH_REALVIEW
select PLAT_VERSATILE_CLCD
select ARM_TIMER_SP804
select GPIO_PL061 if GPIOLIB
+ select MIGHT_HAVE_PCI
help
This enables support for ARM Ltd RealView boards.
@@ -1359,6 +1360,8 @@ config PCI_HOST_ITE8152
source "drivers/pci/Kconfig"
+source "drivers/pci/pcie/Kconfig"
+
source "drivers/pcmcia/Kconfig"
endmenu
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index 541fa4c..1d4fea0 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -10,3 +10,8 @@ obj-$(CONFIG_MACH_REALVIEW_PBA8) += realview_pba8.o
obj-$(CONFIG_MACH_REALVIEW_PBX) += realview_pbx.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+ifeq ($(CONFIG_PCI),y)
+obj-$(CONFIG_MACH_REALVIEW_PB11MP) += pcix.o
+obj-$(CONFIG_MACH_REALVIEW_PBA8) += pcix.o
+obj-$(CONFIG_MACH_REALVIEW_PBX) += pcix.o
+endif
^ permalink raw reply related
* [PATCH 1/4] ARM: Add __arm_ioremap_exec for mapping external memory as MT_MEMORY
From: Tony Lindgren @ 2011-10-07 14:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8E9EE8.8010106@ti.com>
* Santosh Shilimkar <santosh.shilimkar@ti.com> [111006 23:06]:
> On Thursday 06 October 2011 03:36 AM, Tony Lindgren wrote:
> > * Nicolas Pitre <nico@fluxnic.net> [111004 17:26]:
> >> On Tue, 4 Oct 2011, Tony Lindgren wrote:
> > +void __iomem *
> > +__arm_ioremap_exec(unsigned long phys_addr, size_t size, int cached)
> > +{
> > + unsigned int mtype;
> > +
> > + if (cached)
> > + mtype = MT_MEMORY;
> > + else
> > + mtype = MT_MEMORY_NONCACHED;
> > +
> Why don't we allow user to pass the mtype here ?
Well we want to keep the MT_MEMORY types out of asm/io.h.
> We do have a need also to map a page of DDR and SRAM as
> strongly ordered for errata fix and this interface can be
> used for that.
Yeah..
> Ofcourse, SO memory type is not executable memories, so the
> API name might be miss-leading.
..so I think we should just have a separate static mapping for
the omap4 errata fix SO page, and just limit the memory available
for SRAM code to ioremap.
How does that sounds to you?
Tony
^ permalink raw reply
* [PATCH 0/4] initialize omap SRAM later on with __arm_ioremap_exec()
From: Tony Lindgren @ 2011-10-07 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8EA35E.6050100@ti.com>
* Santosh Shilimkar <santosh.shilimkar@ti.com> [111006 23:25]:
> On Thursday 06 October 2011 07:12 AM, Tony Lindgren wrote:
> > * Santosh Shilimkar <santosh.shilimkar@ti.com> [111004 23:29]:
> >>
> >> Will look at this series in next couple of days and do some testing.
> >
> > Thanks, turns out there were a few issues with early ioremap
> > that I fixed. Care to check the L4_IO_ADDRESS changes?
> >
> They look ok to me.
Thanks for testing.
> > It's all pushed now into sram-map-io branch at:
> >
> > https://github.com/tmlind/linux/tree/sram-map-io
> >
> > It seems it's booting now on all omaps I've tried, so will merge
> > it into linux-omap master branch as well for testing.
> >
> I have reviewed and tested this series. No problems seen.
> As asked on other thread, if you are targeting this one for
> 3.2, then sram changes would have a small conflict with
> OMAP4 errata patch. If it is for 3.3, we should be able to
> sort out that conflict easily.
Yeah let's if we can map the errata fix page separately.
Regards,
Tony
^ permalink raw reply
* [PATCH 5/4] ARM: OMAP: Move set_globals initialization to happen in init_early
From: Tony Lindgren @ 2011-10-07 14:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8EA2A4.5070301@ti.com>
* Santosh Shilimkar <santosh.shilimkar@ti.com> [111006 23:22]:
> The changes looks fine to me. Though the ugly hard-coding
> is back with it, it's a step towards generic_io, so hopefully
> it won't have to stay for long time.
Nico please correct me if I'm wrong, but I think that with
generic map_io we have static mappings in place after map_io,
and then ioremap should work for the static mappings right
after map_io except without the need for __arch_ioremap.
Regards,
Tony
^ permalink raw reply
* [PATCH 4/4] ARM: OMAP: Map SRAM later on with ioremap_exec()
From: Tony Lindgren @ 2011-10-07 14:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8EA1A1.5070508@ti.com>
* Santosh Shilimkar <santosh.shilimkar@ti.com> [111006 23:18]:
>
> Are you considering this change for 3.2?
I think we should as this is blocking development for
generic map_io and genalloc changes for SRAM code.
> OMAP4 errata WA would have a conflict with the
> change is sram code and hence the question ?
Right, let's see if we can fix that with a static mapping.
Regards,
Tony
^ permalink raw reply
* [PATCH 1/4] ARM: Add __arm_ioremap_exec for mapping external memory as MT_MEMORY
From: Santosh Shilimkar @ 2011-10-07 15:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111007144349.GE6324@atomide.com>
On Friday 07 October 2011 08:13 PM, Tony Lindgren wrote:
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [111006 23:06]:
>> On Thursday 06 October 2011 03:36 AM, Tony Lindgren wrote:
>>> * Nicolas Pitre <nico@fluxnic.net> [111004 17:26]:
>>>> On Tue, 4 Oct 2011, Tony Lindgren wrote:
>>> +void __iomem *
>>> +__arm_ioremap_exec(unsigned long phys_addr, size_t size, int cached)
>>> +{
>>> + unsigned int mtype;
>>> +
>>> + if (cached)
>>> + mtype = MT_MEMORY;
>>> + else
>>> + mtype = MT_MEMORY_NONCACHED;
>>> +
>> Why don't we allow user to pass the mtype here ?
>
> Well we want to keep the MT_MEMORY types out of asm/io.h.
>
ok.
>> We do have a need also to map a page of DDR and SRAM as
>> strongly ordered for errata fix and this interface can be
>> used for that.
>
> Yeah..
>
>> Ofcourse, SO memory type is not executable memories, so the
>> API name might be miss-leading.
>
> ..so I think we should just have a separate static mapping for
> the omap4 errata fix SO page, and just limit the memory available
> for SRAM code to ioremap.
>
> How does that sounds to you?
>
That's more or less what the patch is already doing.
Instead of static mapping, I was dynamically stealing one
page ( SZ_4K) and mapping it as MT_MEMORY_SO and rest
of the memory as MT_MEMORY for OMAP4.
It should be doable with your updates as well,
I guess with or without static mapping since the only
requisite is to keep one page of SRAM free on OMAP4 and
them map them using iotable_init() with MT_MEMORY_SO.
Regards
Santosh
^ permalink raw reply
* [PATCH] MAINTAINERS: add ARM/FREESCALE IMX6 entry
From: Shawn Guo @ 2011-10-07 15:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317610626-24357-1-git-send-email-shawn.guo@linaro.org>
It adds maintainer for ARM/FREESCALE IMX6.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
MAINTAINERS | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 65ca7ea..05e4d69 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -786,6 +786,13 @@ L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-mx5/
+ARM/FREESCALE IMX6
+M: Shawn Guo <shawn.guo@linaro.org>
+L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+T: git git://git.linaro.org/people/shawnguo/linux-2.6.git
+F: arch/arm/mach-imx/*imx6*
+
ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
--
1.7.4.1
^ permalink raw reply related
* [PATCH 1/4] ARM: Add __arm_ioremap_exec for mapping external memory as MT_MEMORY
From: Tony Lindgren @ 2011-10-07 15:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8F14A6.5050402@ti.com>
* Santosh Shilimkar <santosh.shilimkar@ti.com> [111007 07:29]:
> On Friday 07 October 2011 08:13 PM, Tony Lindgren wrote:
> >
> > ..so I think we should just have a separate static mapping for
> > the omap4 errata fix SO page, and just limit the memory available
> > for SRAM code to ioremap.
> >
> > How does that sounds to you?
> >
> That's more or less what the patch is already doing.
> Instead of static mapping, I was dynamically stealing one
> page ( SZ_4K) and mapping it as MT_MEMORY_SO and rest
> of the memory as MT_MEMORY for OMAP4.
Yeah cool.
> It should be doable with your updates as well,
> I guess with or without static mapping since the only
> requisite is to keep one page of SRAM free on OMAP4 and
> them map them using iotable_init() with MT_MEMORY_SO.
How about something like the following, this won't compile
without at least moving the defines around a bit, but shows
what I had in mind:
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -238,6 +238,14 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
.length = L4_EMU_44XX_SIZE,
.type = MT_DEVICE,
},
+#ifdef CONFIG_OMAP4_ERRATA_I688
+ {
+ .virtual = OMAP4_SRAM_VA,
+ .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
+ .length = PAGE_SIZE,
+ .type = MT_MEMORY_SO,
+ },
+#endif
};
#endif
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -125,6 +125,9 @@ static void __init omap_detect_sram(void)
omap_sram_size = 0x10000; /* 64K */
} else if (cpu_is_omap44xx()) {
omap_sram_start = OMAP4_SRAM_PA;
+#ifdef CONFIG_OMAP4_ERRATA_I688
+ omap_sram_start += PAGE_SIZE;
+#endif
omap_sram_size = 0xe000; /* 56K */
} else {
omap_sram_start = OMAP2_SRAM_PA;
Eventually the SRAM code will be a generic driver, so let's try
to keep the errata fix out of the SRAM code.
Tony
^ permalink raw reply
* [PATCH 5/7] ARM: EXYNOS4: Add support external GIC
From: Will Deacon @ 2011-10-07 15:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8ECA1B.5010005@arm.com>
Hi Marc,
On Fri, Oct 07, 2011 at 10:44:59AM +0100, Marc Zyngier wrote:
> So to make my suggestion completely clear, here's a patch I'm now
> carrying in my tree. It's only been test compiled on EXYNOS4, but works
> nicely on my 11MP. It turns both dist_base and cpu_base into per-cpu
> variables, removes these callbacks, removes your private copy of
> gic_cpu_init, and makes struct gic_chip_data private again.
>
> What do you think?
This looks like the right sort of idea, although I'm deeply suspicious about
per-cpu base addresses for the GIC distributor. It would be nice if the
Samsung guys can elaborate on what's going on here. Few comments inline.
> Subject: [PATCH] ARM: gic: allow GIC to support non-banked setups
>
> The GIC support code is heavily using the fact that hardware
> implementations are exposing banked registers. Unfortunately, it
> looks like at least one GIC implementation (EXYNOS4) offers both
> the distributor and the CPU interfaces at different addresses,
> depending on the CPU.
>
> This problem is solved by turning the distributor and CPU interface
> addresses into per-cpu variables. The EXYNOS4 code is updated not
> to mess with the GIC internals while handling interrupts, and
> struct gic_chip_data is back to being private.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> arch/arm/common/gic.c | 76 +++++++++++++++++++++++++++--------
> arch/arm/include/asm/hardware/gic.h | 17 +------
> arch/arm/mach-exynos4/cpu.c | 14 ------
> arch/arm/mach-exynos4/platsmp.c | 28 ++-----------
> 4 files changed, 66 insertions(+), 69 deletions(-)
>
> diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
> index b574931..c7521dd 100644
> --- a/arch/arm/common/gic.c
> +++ b/arch/arm/common/gic.c
> @@ -37,6 +37,20 @@
> #include <asm/mach/irq.h>
> #include <asm/hardware/gic.h>
>
> +struct gic_chip_data {
> + unsigned int irq_offset;
> + void __percpu __iomem **dist_base;
> + void __percpu __iomem **cpu_base;
> +#ifdef CONFIG_CPU_PM
> + u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
> + u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
> + u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
> + u32 __percpu *saved_ppi_enable;
> + u32 __percpu *saved_ppi_conf;
> +#endif
> + unsigned int gic_irqs;
> +};
I think you can use DECLARE_PER_CPU(void __iomem *dist_base) etc. instead.
> +static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
> +{
> + return *__this_cpu_ptr(data->dist_base);
> +}
Then you can use __get_cpu_var here (same applies throughout).
> +static void __cpuinit exynos4_secondary_init(unsigned int cpu)
> {
> void __iomem *dist_base = S5P_VA_GIC_DIST +
> - (gic_bank_offset * smp_processor_id());
> + (gic_bank_offset * cpu_logical_map(cpu));
Again, I'm deeply suspicious of this code :) Is there not a common memory
alias for the distributor across all of the CPUs?
Will
^ permalink raw reply
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