* [PATCH 0/4] Implement device tree support for ab8500 BM Devices
From: Rajanikanth H.V @ 2012-10-01 4:08 UTC (permalink / raw)
To: linux-arm-kernel
From: "Rajanikanth H.V" <rajanikanth.hv@stericsson.com>
This patch-set adds device tree support for ab8500 battery-managed
devices. This removes the redundant platform structure maintained
across bm devices and implements common DT probe routine across all the
modules.
Rajanikanth H.V (4):
mfd: ab8500: add devicetree support for fuelgauge
mfd: ab8500: add devicetree support for Btemp
mfd: ab8500: add devicetree support for charger
mfd: ab8500: add devicetree support for charging algorithm
Documentation/devicetree/bindings/mfd/ab8500.txt | 27 +-
.../bindings/power_supply/ab8500/btemp.txt | 29 ++
.../bindings/power_supply/ab8500/chargalg.txt | 36 ++
.../bindings/power_supply/ab8500/charger.txt | 44 ++
.../devicetree/bindings/power_supply/ab8500/fg.txt | 86 +++
arch/arm/boot/dts/dbx5x0.dtsi | 40 +-
drivers/mfd/ab8500-core.c | 4 +
drivers/power/Kconfig | 6 -
drivers/power/Makefile | 2 +-
drivers/power/ab8500_bmdata.c | 549 ++++++++++++++++++++
drivers/power/ab8500_btemp.c | 57 +-
drivers/power/ab8500_charger.c | 65 ++-
drivers/power/ab8500_fg.c | 76 ++-
drivers/power/abx500_chargalg.c | 62 ++-
include/linux/mfd/abx500.h | 37 +-
include/linux/mfd/abx500/ab8500-bm.h | 7 +
16 files changed, 1028 insertions(+), 99 deletions(-)
create mode 100644 Documentation/devicetree/bindings/power_supply/ab8500/btemp.txt
create mode 100644 Documentation/devicetree/bindings/power_supply/ab8500/chargalg.txt
create mode 100644 Documentation/devicetree/bindings/power_supply/ab8500/charger.txt
create mode 100644 Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
create mode 100644 drivers/power/ab8500_bmdata.c
--
1.7.9.5
^ permalink raw reply
* [RFC] arm/mm: add a protection when flushing anonymous pages
From: Jason Lin @ 2012-10-01 3:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGCDX1mY4wbMq4qDJ9vCazShxdWQXVYyWkpLd5u8_xqbEC2BWQ@mail.gmail.com>
Dear all:
By the way, I used the CPU with VIPT cache.
Thanks.
2012/10/1 Jason Lin <kernel.jason@gmail.com>:
> Dear all:
> When I do LTP direct I/O tests, it produced a cache coherence issue
> caused by flush_pfn_alias() (arch/arm/mm/flush.c).
> I think we should to disable preemption or lock before setting page
> table and enable preemption or unlock after flushing pages
>
> Any comments are appreciated.
> Thanks.
^ permalink raw reply
* [RFC] arm/mm: add a protection when flushing anonymous pages
From: Jason Lin @ 2012-10-01 3:08 UTC (permalink / raw)
To: linux-arm-kernel
Dear all:
When I do LTP direct I/O tests, it produced a cache coherence issue
caused by flush_pfn_alias() (arch/arm/mm/flush.c).
I think we should to disable preemption or lock before setting page
table and enable preemption or unlock after flushing pages
Any comments are appreciated.
Thanks.
^ permalink raw reply
* [PATCH] [ARM] Build failure CONFIG_ARCH_KIRKWOOD_DT relies on CACHE_FEROCEON_L2
From: Olof Johansson @ 2012-10-01 2:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120930232253.GD30637@obsidianresearch.com>
Hi,
On Sun, Sep 30, 2012 at 4:22 PM, Jason Gunthorpe
<jgunthorpe@obsidianresearch.com> wrote:
> Move the CACHE_FEROCEON_L2 test to kirkwood_l2_init, since linking
> fails on the reference to feroceon_l2_init.
>
> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
> ---
> arch/arm/mach-kirkwood/board-dt.c | 2 --
> arch/arm/mach-kirkwood/common.c | 4 ++--
> 2 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index e4eb450..d00223e 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -50,9 +50,7 @@ static void __init kirkwood_dt_init(void)
>
> kirkwood_setup_cpu_mbus();
>
> -#ifdef CONFIG_CACHE_FEROCEON_L2
> kirkwood_l2_init();
> -#endif
>
> /* Setup root of clk tree */
> kirkwood_clk_init();
> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> index 1201191..4177304 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -645,6 +645,7 @@ char * __init kirkwood_id(void)
>
> void __init kirkwood_l2_init(void)
> {
> +#ifdef CONFIG_CACHE_FEROCEON_L2
> #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
Aren't these added ifdefs completely redundant? L2_WRITETHROUGH is
dependent on the outer options anyway.
-Olof
^ permalink raw reply
* [PATCH 03/15] ARM: Section based HYP idmap
From: Christoffer Dall @ 2012-10-01 2:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120918130012.GL32204@mudshark.cambridge.arm.com>
[snip]
>> +
>> +static int __init hyp_init_static_idmap(void)
>> +{
>> + hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
>> + if (!hyp_pgd)
>> + return -ENOMEM;
>> +
>> + hyp_idmap_setup();
>> +
>> + return 0;
>> +}
>> +early_initcall(hyp_init_static_idmap);
>> +#endif
>
> I'd rather the alloc/free functions for the hyp pgd were somewhere else,
> like they are for standard pgds. Then we can just call them here without
> having to encode knowledge of PGD size etc in the mapping code.
>
this used to be the case, but Marc changed it iirc., so just cc'ing
him. The following is an attempt at what you're looking for if I
understand you correctly:
diff --git a/arch/arm/include/asm/idmap.h b/arch/arm/include/asm/idmap.h
index a1ab8d6..36708ba 100644
--- a/arch/arm/include/asm/idmap.h
+++ b/arch/arm/include/asm/idmap.h
@@ -12,10 +12,8 @@ extern pgd_t *idmap_pgd;
void setup_mm_for_reboot(void);
#ifdef CONFIG_ARM_VIRT_EXT
-extern pgd_t *hyp_pgd;
-
-void hyp_idmap_teardown(void);
-void hyp_idmap_setup(void);
+void hyp_idmap_teardown(pgd_t *hyp_pgd);
+void hyp_idmap_setup(pgd_t *hyp_pgd);
#endif
#endif /* __ASM_IDMAP_H */
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index c3f90b0..ecfaaf0 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -43,4 +43,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu,
struct kvm_run *run);
void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
+unsigned long kvm_mmu_get_httbr(void);
+int kvm_mmu_init(void);
+void kvm_mmu_exit(void);
#endif /* __ARM_KVM_MMU_H__ */
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 7e11280..d64ce2a 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -35,7 +35,6 @@
#include <asm/ptrace.h>
#include <asm/mman.h>
#include <asm/cputype.h>
-#include <asm/idmap.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
#include <asm/virt.h>
@@ -887,7 +886,7 @@ static void cpu_init_hyp_mode(void *vector)
/* Switch from the HYP stub to our own HYP init vector */
__hyp_set_vectors((unsigned long)vector);
- pgd_ptr = virt_to_phys(hyp_pgd);
+ pgd_ptr = kvm_mmu_get_httbr();
stack_page = __get_cpu_var(kvm_arm_hyp_stack_page);
hyp_stack_ptr = stack_page + PAGE_SIZE;
vector_ptr = (unsigned long)__kvm_hyp_vector;
@@ -918,6 +917,13 @@ static int init_hyp_mode(void)
int err = 0;
/*
+ * Allocate Hyp PGD and setup Hyp identity mapping
+ */
+ err = kvm_mmu_init();
+ if (err)
+ return err;
+
+ /*
* It is probably enough to obtain the default on one
* CPU. It's unlikely to be different on the others.
*/
@@ -954,7 +960,7 @@ static int init_hyp_mode(void)
/*
* Unmap the identity mapping
*/
- hyp_idmap_teardown();
+ kvm_mmu_exit();
/*
* Map the Hyp-code called directly from the host
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 9499d4d..a35a8a9 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -34,6 +34,7 @@
#include "trace.h"
static DEFINE_MUTEX(kvm_hyp_pgd_mutex);
+static pgd_t *hyp_pgd;
static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
int min, int max)
@@ -994,3 +995,23 @@ void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu)
{
mmu_free_memory_cache(&vcpu->arch.mmu_page_cache);
}
+
+unsigned long kvm_mmu_get_httbr(void)
+{
+ return virt_to_phys(hyp_pgd);
+}
+
+int kvm_mmu_init(void)
+{
+ hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
+ if (!hyp_pgd)
+ return -ENOMEM;
+
+ hyp_idmap_setup(hyp_pgd);
+ return 0;
+}
+
+void kvm_mmu_exit(void)
+{
+ hyp_idmap_teardown(hyp_pgd);
+}
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index f0ab339..ea7430e 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -102,9 +102,6 @@ static int __init init_static_idmap(void)
early_initcall(init_static_idmap);
#if defined(CONFIG_ARM_VIRT_EXT) && defined(CONFIG_ARM_LPAE)
-pgd_t *hyp_pgd;
-EXPORT_SYMBOL_GPL(hyp_pgd);
-
static void hyp_idmap_del_pmd(pgd_t *pgd, unsigned long addr)
{
pud_t *pud;
@@ -123,7 +120,7 @@ extern char __hyp_idmap_text_start[],
__hyp_idmap_text_end[];
* This version actually frees the underlying pmds for all pgds in range and
* clear the pgds themselves afterwards.
*/
-void hyp_idmap_teardown(void)
+void hyp_idmap_teardown(pgd_t *hyp_pgd)
{
unsigned long addr, end;
unsigned long next;
@@ -141,27 +138,12 @@ void hyp_idmap_teardown(void)
}
EXPORT_SYMBOL_GPL(hyp_idmap_teardown);
-void hyp_idmap_setup(void)
+void hyp_idmap_setup(pgd_t *hyp_pgd)
{
identity_mapping_add(hyp_pgd, __hyp_idmap_text_start,
__hyp_idmap_text_end, PMD_SECT_AP1);
}
EXPORT_SYMBOL_GPL(hyp_idmap_setup);
-
-static int __init hyp_init_static_idmap(void)
-{
- if (!is_hyp_mode_available())
- return 0;
-
- hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
- if (!hyp_pgd)
- return -ENOMEM;
-
- hyp_idmap_setup();
-
- return 0;
-}
-early_initcall(hyp_init_static_idmap);
#endif
/*
^ permalink raw reply related
* [GIT PULL] ARM: Kirkwood: build fix CACHE_FEROCEON_L2
From: Jason Cooper @ 2012-10-01 1:49 UTC (permalink / raw)
To: linux-arm-kernel
Arnd, Olof,
Depends:
- Based on arm-soc/late/kirkwood
Adds:
- Better #ifdef logic for CACHE_FEROCEON_L2 to prevent linker errors
The following changes since commit 46f2007c1efadfa4071c17e75f140c47f09293de:
ARM: mvebu: fix build breaks from multi-platform conversion (2012-09-28 22:27:07 +0200)
are available in the git repository at:
git://git.infradead.org/users/jcooper/linux.git kirkwood/cache-build-fix
Jason Gunthorpe (1):
Build failure CONFIG_ARCH_KIRKWOOD_DT relies on CACHE_FEROCEON_L2
arch/arm/mach-kirkwood/board-dt.c | 2 --
arch/arm/mach-kirkwood/common.c | 4 ++--
2 files changed, 2 insertions(+), 4 deletions(-)
^ permalink raw reply
* [GIT PULL] ARM: mvebu: gpio fix for v3.7
From: Jason Cooper @ 2012-10-01 1:25 UTC (permalink / raw)
To: linux-arm-kernel
Arnd, Olof,
Depends:
- Based on arm-soc/late/kirkwood
Adds:
- missing break;s from converting if{}s to switch{}
The following changes since commit 46f2007c1efadfa4071c17e75f140c47f09293de:
ARM: mvebu: fix build breaks from multi-platform conversion (2012-09-28 22:27:07 +0200)
are available in the git repository at:
git://git.infradead.org/users/jcooper/linux.git mvebu/gpio-fixes
Axel Lin (1):
gpio: mvebu: Add missing breaks in mvebu_gpio_irq_set_type
drivers/gpio/gpio-mvebu.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
^ permalink raw reply
* [GIT PULL] ARM: mvebu: cache-l2x0 DT for v3.7
From: Jason Cooper @ 2012-10-01 0:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120930080136.GE6933@n2100.arm.linux.org.uk>
Russell,
On Sun, Sep 30, 2012 at 09:01:36AM +0100, Russell King - ARM Linux wrote:
> On Sat, Sep 29, 2012 at 08:55:03PM -0700, Olof Johansson wrote:
> > On Sat, Sep 29, 2012 at 09:50:12PM -0400, Jason Cooper wrote:
> > > Depends:
> > > - Based on arm-soc/late/kirkwood
> > > - Patches going through rmk's patch tracker:
> > > - arm: cache-l2x0: make outer_cache_fns a field of l2x0_of_data
> > > - arm: cache-l2x0: add an optional register to save/restore
> > > - arm: cache-l2x0: add support for Aurora L2 cache ctrl
> > >
> > > - feature-use dependency only. No build breakage or failed boot
> > > should occur. Until patches from rmk's tracker land, driver
> > > won't know about compatible property, so it's like the driver
> > > isn't there.
> > >
> > > Adds:
> > > - cache-l2x0 DT entry for Marvell Armada (mvebu) SoCs
> >
> > Hi Jason,
> >
> > I'd prefer to hold off on this until we know that Russell is happy with
> > the l2x0 changes, just in case this part of the series might need revising
> > (i.e. bindings changes). Please resend when he has picked them up!
>
> Well, there's no patches ever existing in the patch tracker with a
> summary line as you list above - here are the last three containing
> "l2x0":
>
> 7398/1? l2x0: only write to debug 3.4-rc3? 20 Apr Applied?
> registers on PL310 2012?
> 7429/1? cache-l2x0: add a const qualifier 3.4? 22 Jun Discarded?
> 2012?
> 7507/1? cache-l2x0.c: save the final aux 3.6-rc4? 03 Sep Applied?
> ctrl value for resuming 2012?
>
> and it's probably now too late as I'm not going to be able to apply
> any patches for the rest of the week, and as the -rc's have been
> released over the weekend, we could see -final today.
Yes, I responded to Gregory (the author) in the thread with the patches
asking him to push them into your tracker. Unfortunately, he doesn't
seem to be available. So, yes, this is v3.8.
Once I see these first three patches make it in, I'll resubmit the
pullrq.
thx,
Jason.
^ permalink raw reply
* [GIT PULL] Renesas ARM-based SoC: KZM-9A-GT for 3.7
From: Simon Horman @ 2012-10-01 0:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201209282002.28445.arnd@arndb.de>
On Fri, Sep 28, 2012 at 08:02:28PM +0000, Arnd Bergmann wrote:
> On Tuesday 28 August 2012, Simon Horman wrote:
> > ----------------------------------------------------------------
> > Tetsuyuki Kobayashi (1):
> > ARM: shmobile: kzm9g: enable restarting
> >
> > arch/arm/mach-shmobile/board-kzm9g.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
>
> This patch ended up causing a new build warning in combination
> with the io.h changes in Russell's tree.
>
> I've just applied this patch on top, which is the same thing we
> did to all the other open-coded mmio locations.
Thanks, sorry for missing that.
^ permalink raw reply
* [GIT PULL] ARM: mvebu: cache-l2x0 DT for v3.7
From: Jason Cooper @ 2012-10-01 0:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120930035503.GB477@quad.lixom.net>
On Sat, Sep 29, 2012 at 08:55:03PM -0700, Olof Johansson wrote:
> On Sat, Sep 29, 2012 at 09:50:12PM -0400, Jason Cooper wrote:
> > Depends:
> > - Based on arm-soc/late/kirkwood
> > - Patches going through rmk's patch tracker:
> > - arm: cache-l2x0: make outer_cache_fns a field of l2x0_of_data
> > - arm: cache-l2x0: add an optional register to save/restore
> > - arm: cache-l2x0: add support for Aurora L2 cache ctrl
> >
> > - feature-use dependency only. No build breakage or failed boot
> > should occur. Until patches from rmk's tracker land, driver
> > won't know about compatible property, so it's like the driver
> > isn't there.
> >
> > Adds:
> > - cache-l2x0 DT entry for Marvell Armada (mvebu) SoCs
>
> I'd prefer to hold off on this until we know that Russell is happy with
> the l2x0 changes, just in case this part of the series might need revising
> (i.e. bindings changes). Please resend when he has picked them up!
Will do. These are on ice.
thx,
Jason.
^ permalink raw reply
* [PATCH V5] Add support for Aurora L2 Cache Controller
From: Jason Cooper @ 2012-09-30 23:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1348675370-16359-1-git-send-email-gregory.clement@free-electrons.com>
Gregory,
Unfortunately, this series is slipping to v3.8. Please put patches 1,2
and 3 into Russell's patch tracker. Once I see that he takes them in,
I'll resubmit my pullrq for the last three.
Sorry for all the confusion.
thx,
Jason.
On Wed, Sep 26, 2012 at 06:02:44PM +0200, Gregory CLEMENT wrote:
> Hello,
>
> This a the 5th version of the patch set (the sixth if we include the
> RFC). This last series add the ultimate change asked by Russell after
> his review. See the end of this email for the changelog.
>
> The purpose of this patch set is to add support for Aurora L2 Cache
> Controller used by Armada 370 and Armada XP SoCs. As it was initially
> designed by Marvell engineer to be compatible with the ARM L2 Cache
> Controller, we chose to reuse the existing code and to just extend it
> to support the differences and improvements brought by the Aurora
> controller.The diffstat looks like:
>
> Documentation/devicetree/bindings/arm/l2cc.txt | 9 +
> arch/arm/boot/dts/armada-370.dtsi | 6 +
> arch/arm/boot/dts/armada-xp.dtsi | 7 +
> arch/arm/include/asm/hardware/cache-l2x0.h | 5 +
> arch/arm/mach-mvebu/Kconfig | 1 +
> arch/arm/mach-mvebu/irq-armada-370-xp.c | 4 +
> arch/arm/mm/cache-aurora-l2.h | 55 +++++
> arch/arm/mm/cache-l2x0.c | 277 +++++++++++++++++++++---
> 8 files changed, 336 insertions(+), 28 deletions(-)
>
> The main differences and improvements are:
>
> - no cache id part number available through hardware (need to get it
> by the DT).
> - always write through mode available.
> - two flavors of the controller 'outer cache' and 'system cache' (the
> last one meaning maintenance operations on L1 are broadcasted to the
> L2 and L2 performs the same operation).
> - in outer cache mode, the cache maintenance operations are improved
> and can be done on a range inside a page and are not limited to a
> cache line.
> - during resume the controller need to restore the ctrl register.
>
> The first patch adds some modifications in the driver
> infrastructure. As most of the outer cache functions can use the
> Aurora improvements, we had to introduce new functions. So we thought
> it was better to use a outer_cache_fns field inside l2x0_of_data and
> just memcopy it into outer_cache depending of the type of the l2x0
> cache.
>
> Changelog:
> V4 -> V5:
> - Rebased L2 pach set onto v3.6-rc7.
> - The header file cache-aurora-l2.h was co-located with its only user:
> moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
> - Removed additional unnecessary blank lines in cache-l2x0.c.
>
> V3 -> V4:
> - Rebased L2 pach set onto v3.6-rc6.
> - The assignment of outer_cache in l2x0_init, don't depend of
> CONFIG_OF but of variable. The value of this boolean variable is
> changed in l2x0_of_init. Then, if a system enable CONFIG_OF don't
> supply a DT file, relying on the old way to initialize the L2 cache,
> the assignment won't be disable.
> - Removed unnecessary check in calc_range_end(). The alignment tested
> was already made before calling this function.
>
> V2 -> V3:
> - Use define instead of literal value for AURORA_CTRL_FW,
> AURORA_WAY_SIZE_SHIFT, L2X0_WAY_SIZE_SHIFT and L2X0_CTRL_EN.
> - Used ALIGN, IS_ALUGNED and PAGE_ALIGN macro instead of bitwise
> operation.
> - Calculate the number of way for Aurora instead of using a switch
> case.
> - removed inaccurate BUG() call and replaced them by a pr_warn if
> needed.
> - In aurora_inv_range round the start and end addresses to cache line
> size. The initial code was supposed to invalidate partial line cache
> but actually invalidate the full line, so there was no point to do
> it outside the aurora_pa_range call.
> - Removed the dsb call in the aurora_*_range function: the
> cache_sync() call inside aurora_pa_range() is enough.
> - And as usual tested on Armada 370 and Armada XP boards and ran
> benchmark without seeing any regression. Results are updated on the
> wiki page.
>
> V1 -> V2:
> - Rebased L2 pach set onto v3.6-rc4.
> - Changed the compatible names to be more explicit, from
> aurora-cache-with-outer to aurora-outer-cache , and from
> aurora-cache-without-outer to aurora-system-cache.
> - Add an isb() after the call to mcr in aurora_broadcast_l2_commands().
> - Added the tested and reviewed-by from Lior Amsalem and Yehuda
> Yitschak.
> - Tested on Armada 370 and Armada XP boards and ran benchmark without
> seeing any regression.
>
> RFC -> V1:
> - Rebased the series on to V3.6-rc3
> - Added missing Signed-off-by
> - Corrected a compilation warning that I have missed
> - Ran benchmarks without seeing any regression
>
> Benchmarks results are visible here:
> https://github.com/MISL-EBU-System-SW/mainline-public/wiki/Non-official-cache-bench-results-on-the-mainline-Linux-port-%28-kernels-3.6-rcX%29-of-Armada-XP-and-Armada-370
>
> The git branch aurora-L2-cache-ctrl is visible at
> https://github.com/MISL-EBU-System-SW/mainline-public.git
>
> Regards,
>
> Gregory
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] [ARM] Build failure CONFIG_ARCH_KIRKWOOD_DT relies on CACHE_FEROCEON_L2
From: Jason Gunthorpe @ 2012-09-30 23:22 UTC (permalink / raw)
To: linux-arm-kernel
Move the CACHE_FEROCEON_L2 test to kirkwood_l2_init, since linking
fails on the reference to feroceon_l2_init.
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
---
arch/arm/mach-kirkwood/board-dt.c | 2 --
arch/arm/mach-kirkwood/common.c | 4 ++--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450..d00223e 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -50,9 +50,7 @@ static void __init kirkwood_dt_init(void)
kirkwood_setup_cpu_mbus();
-#ifdef CONFIG_CACHE_FEROCEON_L2
kirkwood_l2_init();
-#endif
/* Setup root of clk tree */
kirkwood_clk_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 1201191..4177304 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -645,6 +645,7 @@ char * __init kirkwood_id(void)
void __init kirkwood_l2_init(void)
{
+#ifdef CONFIG_CACHE_FEROCEON_L2
#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
feroceon_l2_init(1);
@@ -652,6 +653,7 @@ void __init kirkwood_l2_init(void)
writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
feroceon_l2_init(0);
#endif
+#endif
}
void __init kirkwood_init(void)
@@ -669,9 +671,7 @@ void __init kirkwood_init(void)
kirkwood_setup_cpu_mbus();
-#ifdef CONFIG_CACHE_FEROCEON_L2
kirkwood_l2_init();
-#endif
/* Setup root of clk tree */
kirkwood_clk_init();
--
1.7.4.1
^ permalink raw reply related
* [PATCH] [ARM] Use AT() in the linker script to create correct program headers
From: Jason Gunthorpe @ 2012-09-30 23:21 UTC (permalink / raw)
To: linux-arm-kernel
The standard linux asm-generic/vmlinux.lds.h already supports this,
and it seems other architectures do as well.
The goal is to create an ELF file that has correct program headers. We
want to see the VirtAddr be the runtime address of the kernel with the
MMU turned on, and PhysAddr be the physical load address for the section
with no MMU.
This allows ELF based boot loaders to properly load vmlinux:
$ readelf -l vmlinux
Entry point 0x8000
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x008000 0xc0008000 0x00008000 0x372244 0x3a4310 RWE 0x8000
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
---
arch/arm/include/asm/memory.h | 2 +-
arch/arm/kernel/vmlinux.lds.S | 47 ++++++++++++++++++++++++----------------
2 files changed, 29 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 5f6ddcc..4ce5b6d 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -283,7 +283,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
#define arch_is_coherent() 0
#endif
-#endif
+#endif /* __ASSEMBLY__ */
#include <asm-generic/memory_model.h>
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 36ff15b..07942b6 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -3,6 +3,13 @@
* Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>
*/
+/* If we have a known, fixed physical load address then set LOAD_OFFSET
+ and generate an ELF that has the physical load address in the program
+ headers. */
+#ifndef CONFIG_ARM_PATCH_PHYS_VIRT
+#define LOAD_OFFSET (PAGE_OFFSET - PHYS_OFFSET)
+#endif
+
#include <asm-generic/vmlinux.lds.h>
#include <asm/cache.h>
#include <asm/thread_info.h>
@@ -39,7 +46,7 @@
#endif
OUTPUT_ARCH(arm)
-ENTRY(stext)
+ENTRY(phys_start)
#ifndef __ARMEB__
jiffies = jiffies_64;
@@ -86,11 +93,13 @@ SECTIONS
#else
. = PAGE_OFFSET + TEXT_OFFSET;
#endif
- .head.text : {
+ .head.text : AT(ADDR(.head.text) - LOAD_OFFSET) {
_text = .;
+ phys_start = . - LOAD_OFFSET;
HEAD_TEXT
}
- .text : { /* Real text segment */
+ /* Real text segment */
+ .text : AT(ADDR(.text) - LOAD_OFFSET) {
_stext = .; /* Text and read-only data */
__exception_text_start = .;
*(.exception.text)
@@ -119,12 +128,12 @@ SECTIONS
* Stack unwinding tables
*/
. = ALIGN(8);
- .ARM.unwind_idx : {
+ .ARM.unwind_idx : AT(ADDR(.ARM.unwind_idx) - LOAD_OFFSET) {
__start_unwind_idx = .;
*(.ARM.exidx*)
__stop_unwind_idx = .;
}
- .ARM.unwind_tab : {
+ .ARM.unwind_tab : AT(ADDR(.ARM.unwind_tab) - LOAD_OFFSET) {
__start_unwind_tab = .;
*(.ARM.extab*)
__stop_unwind_tab = .;
@@ -139,35 +148,35 @@ SECTIONS
#endif
INIT_TEXT_SECTION(8)
- .exit.text : {
+ .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) {
ARM_EXIT_KEEP(EXIT_TEXT)
}
- .init.proc.info : {
+ .init.proc.info : AT(ADDR(.init.proc.info) - LOAD_OFFSET) {
ARM_CPU_DISCARD(PROC_INFO)
}
- .init.arch.info : {
+ .init.arch.info : AT(ADDR(.init.arch.info) - LOAD_OFFSET) {
__arch_info_begin = .;
*(.arch.info.init)
__arch_info_end = .;
}
- .init.tagtable : {
+ .init.tagtable : AT(ADDR(.init.tagtable) - LOAD_OFFSET) {
__tagtable_begin = .;
*(.taglist.init)
__tagtable_end = .;
}
#ifdef CONFIG_SMP_ON_UP
- .init.smpalt : {
+ .init.smpalt : AT(ADDR(.init.smpalt) - LOAD_OFFSET) {
__smpalt_begin = .;
*(.alt.smp.init)
__smpalt_end = .;
}
#endif
- .init.pv_table : {
+ .init.pv_table : AT(ADDR(.init.pv_table) - LOAD_OFFSET) {
__pv_table_begin = .;
*(.pv_table)
__pv_table_end = .;
}
- .init.data : {
+ .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) {
#ifndef CONFIG_XIP_KERNEL
INIT_DATA
#endif
@@ -178,7 +187,7 @@ SECTIONS
INIT_RAM_FS
}
#ifndef CONFIG_XIP_KERNEL
- .exit.data : {
+ .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) {
ARM_EXIT_KEEP(EXIT_DATA)
}
#endif
@@ -196,7 +205,7 @@ SECTIONS
__data_loc = .;
#endif
- .data : AT(__data_loc) {
+ .data : AT(__data_loc - LOAD_OFFSET) {
_data = .; /* address in memory */
_sdata = .;
@@ -245,7 +254,7 @@ SECTIONS
* free it after init has commenced and TCM contents have
* been copied to its destination.
*/
- .tcm_start : {
+ .tcm_start : AT(ADDR(.tcm_start) - LOAD_OFFSET) {
. = ALIGN(PAGE_SIZE);
__tcm_start = .;
__itcm_start = .;
@@ -257,7 +266,7 @@ SECTIONS
* and we'll upload the contents from RAM to TCM and free
* the used RAM after that.
*/
- .text_itcm ITCM_OFFSET : AT(__itcm_start)
+ .text_itcm ITCM_OFFSET : AT(__itcm_start - LOAD_OFFSET)
{
__sitcm_text = .;
*(.tcm.text)
@@ -272,12 +281,12 @@ SECTIONS
*/
. = ADDR(.tcm_start) + SIZEOF(.tcm_start) + SIZEOF(.text_itcm);
- .dtcm_start : {
+ .dtcm_start : AT(ADDR(.dtcm_start) - LOAD_OFFSET) {
__dtcm_start = .;
}
/* TODO: add remainder of ITCM as well, that can be used for data! */
- .data_dtcm DTCM_OFFSET : AT(__dtcm_start)
+ .data_dtcm DTCM_OFFSET : AT(__dtcm_start - LOAD_OFFSET)
{
. = ALIGN(4);
__sdtcm_data = .;
@@ -290,7 +299,7 @@ SECTIONS
. = ADDR(.dtcm_start) + SIZEOF(.data_dtcm);
/* End marker for freeing TCM copy in linked object */
- .tcm_end : AT(ADDR(.dtcm_start) + SIZEOF(.data_dtcm)){
+ .tcm_end : AT(ADDR(.dtcm_start) + SIZEOF(.data_dtcm) - LOAD_OFFSET){
. = ALIGN(PAGE_SIZE);
__tcm_end = .;
}
--
1.7.4.1
^ permalink raw reply related
* [PATCH 14/15] KVM: ARM: Handle I/O aborts
From: Christoffer Dall @ 2012-09-30 21:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120927151108.GM25916@mudshark.cambridge.arm.com>
On Thu, Sep 27, 2012 at 11:11 AM, Will Deacon <will.deacon@arm.com> wrote:
> On Sat, Sep 15, 2012 at 04:35:59PM +0100, Christoffer Dall wrote:
>> When the guest accesses I/O memory this will create data abort
>> exceptions and they are handled by decoding the HSR information
>> (physical address, read/write, length, register) and forwarding reads
>> and writes to QEMU which performs the device emulation.
>>
>> Certain classes of load/store operations do not support the syndrome
>> information provided in the HSR and we therefore must be able to fetch
>> the offending instruction from guest memory and decode it manually.
>>
>> We only support instruction decoding for valid reasonable MMIO operations
>> where trapping them do not provide sufficient information in the HSR (no
>> 16-bit Thumb instructions provide register writeback that we care about).
>>
>> The following instruciton types are NOT supported for MMIO operations
>> despite the HSR not containing decode info:
>> - any Load/Store multiple
>> - any load/store exclusive
>> - any load/store dual
>> - anything with the PC as the dest register
>
> [...]
>
>> +
>> +/******************************************************************************
>> + * Load-Store instruction emulation
>> + *****************************************************************************/
>> +
>> +/*
>> + * Must be ordered with LOADS first and WRITES afterwards
>> + * for easy distinction when doing MMIO.
>> + */
>> +#define NUM_LD_INSTR 9
>> +enum INSTR_LS_INDEXES {
>> + INSTR_LS_LDRBT, INSTR_LS_LDRT, INSTR_LS_LDR, INSTR_LS_LDRB,
>> + INSTR_LS_LDRD, INSTR_LS_LDREX, INSTR_LS_LDRH, INSTR_LS_LDRSB,
>> + INSTR_LS_LDRSH,
>> + INSTR_LS_STRBT, INSTR_LS_STRT, INSTR_LS_STR, INSTR_LS_STRB,
>> + INSTR_LS_STRD, INSTR_LS_STREX, INSTR_LS_STRH,
>> + NUM_LS_INSTR
>> +};
>> +
>> +static u32 ls_instr[NUM_LS_INSTR][2] = {
>> + {0x04700000, 0x0d700000}, /* LDRBT */
>> + {0x04300000, 0x0d700000}, /* LDRT */
>> + {0x04100000, 0x0c500000}, /* LDR */
>> + {0x04500000, 0x0c500000}, /* LDRB */
>> + {0x000000d0, 0x0e1000f0}, /* LDRD */
>> + {0x01900090, 0x0ff000f0}, /* LDREX */
>> + {0x001000b0, 0x0e1000f0}, /* LDRH */
>> + {0x001000d0, 0x0e1000f0}, /* LDRSB */
>> + {0x001000f0, 0x0e1000f0}, /* LDRSH */
>> + {0x04600000, 0x0d700000}, /* STRBT */
>> + {0x04200000, 0x0d700000}, /* STRT */
>> + {0x04000000, 0x0c500000}, /* STR */
>> + {0x04400000, 0x0c500000}, /* STRB */
>> + {0x000000f0, 0x0e1000f0}, /* STRD */
>> + {0x01800090, 0x0ff000f0}, /* STREX */
>> + {0x000000b0, 0x0e1000f0} /* STRH */
>> +};
>> +
>> +static inline int get_arm_ls_instr_index(u32 instr)
>> +{
>> + return kvm_instr_index(instr, ls_instr, NUM_LS_INSTR);
>> +}
>> +
>> +/*
>> + * Load-Store instruction decoding
>> + */
>> +#define INSTR_LS_TYPE_BIT 26
>> +#define INSTR_LS_RD_MASK 0x0000f000
>> +#define INSTR_LS_RD_SHIFT 12
>> +#define INSTR_LS_RN_MASK 0x000f0000
>> +#define INSTR_LS_RN_SHIFT 16
>> +#define INSTR_LS_RM_MASK 0x0000000f
>> +#define INSTR_LS_OFFSET12_MASK 0x00000fff
>
> I'm afraid you're not going to thank me much for this, but it's high time we
> unified the various instruction decoding functions we have under arch/arm/
> and this seems like a good opportunity for that. For example, look at the
> following snippets (there is much more in the files I list) in addition to
> what you have:
>
I think it would be great if we had a set of unified decoding functions!
However, I think it's a shame if we can't merge KVM because we want to
clean up this code. There would be nothing in the way of breaking API
or anything like that preventing us from cleaning this up after the
code has been merged.
Please consider reviewing the code for correctness and consider if the
code could be merged as is.
On the other hand, if you or Dave or anyone else wants to create a set
of patches that cleans this up in a timely manner, I will be happy to
merge them for my code as well ;)
>
> asm/ptrace.h
> -------------
> #define PSR_T_BIT 0x00000020
> #define PSR_F_BIT 0x00000040
> #define PSR_I_BIT 0x00000080
> #define PSR_A_BIT 0x00000100
> #define PSR_E_BIT 0x00000200
> #define PSR_J_BIT 0x01000000
> #define PSR_Q_BIT 0x08000000
> #define PSR_V_BIT 0x10000000
> #define PSR_C_BIT 0x20000000
> #define PSR_Z_BIT 0x40000000
> #define PSR_N_BIT 0x80000000
>
> mm/alignment.c
> --------------
> #define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
> #define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
> #define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */
> #define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */
> #define LDST_L_BIT(i) (i & (1 << 20)) /* Load */
>
> kernel/kprobes*.c
> -----------------
> static void __kprobes
> emulate_ldr(struct kprobe *p, struct pt_regs *regs)
> {
> kprobe_opcode_t insn = p->opcode;
> unsigned long pc = (unsigned long)p->addr + 8;
> int rt = (insn >> 12) & 0xf;
> int rn = (insn >> 16) & 0xf;
> int rm = insn & 0xf;
>
> kernel/opcodes.c
> ----------------
> static const unsigned short cc_map[16] = {
> 0xF0F0, /* EQ == Z set */
> 0x0F0F, /* NE */
> 0xCCCC, /* CS == C set */
> 0x3333, /* CC */
> 0xFF00, /* MI == N set */
> 0x00FF, /* PL */
> 0xAAAA, /* VS == V set */
> 0x5555, /* VC */
> 0x0C0C, /* HI == C set && Z clear */
> 0xF3F3, /* LS == C clear || Z set */
> 0xAA55, /* GE == (N==V) */
> 0x55AA, /* LT == (N!=V) */
> 0x0A05, /* GT == (!Z && (N==V)) */
> 0xF5FA, /* LE == (Z || (N!=V)) */
> 0xFFFF, /* AL always */
> 0 /* NV */
> };
>
> kernel/swp_emulate.c
> --------------------
> #define EXTRACT_REG_NUM(instruction, offset) \
> (((instruction) & (0xf << (offset))) >> (offset))
> #define RN_OFFSET 16
> #define RT_OFFSET 12
> #define RT2_OFFSET 0
>
>
> There are also bits and pieces with the patching frameworks and module
> relocations that could benefit from some code sharing. Now, I think Dave had
> some ideas about moving a load of this code into a common disassembler under
> arch/arm/ so it would be great to tie that in here and implement that for
> load/store instructions. Then other users can augment the number of
> supported instruction classes as and when it is required.
>
^ permalink raw reply
* [PATCH 3/3] spi: spi-pl022: Minor simplification for runtime pm
From: Linus Walleij @ 2012-09-30 21:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1348831266-16721-4-git-send-email-ulf.hansson@stericsson.com>
On Fri, Sep 28, 2012 at 1:21 PM, Ulf Hansson <ulf.hansson@stericsson.com> wrote:
> From: Ulf Hansson <ulf.hansson@linaro.org>
>
> In probe pm_runtime_put_autosuspend has the same effect as doing
> pm_runtime_put. This due to upper layer in driver core is preventing
> the device from being runtime suspended by a pm_runtime_get*.
>
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 2/3] Revert "spi/pl022: enable runtime PM"
From: Linus Walleij @ 2012-09-30 21:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1348831266-16721-3-git-send-email-ulf.hansson@stericsson.com>
On Fri, Sep 28, 2012 at 1:21 PM, Ulf Hansson <ulf.hansson@stericsson.com> wrote:
> From: Ulf Hansson <ulf.hansson@linaro.org>
>
> This reverts commit 2fb30d1147c599f5657e8c62c862f9a0f58d9d99.
>
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Thanks for fixing my stupid mistakes ...
Linus Walleij
^ permalink raw reply
* [PATCH 1/3] Revert "spi/pl022: fix spi-pl022 pm enable at probe"
From: Linus Walleij @ 2012-09-30 21:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120930101418.GF6933@n2100.arm.linux.org.uk>
On Sun, Sep 30, 2012 at 12:14 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> The real answer is to revert both commits to get the driver back to a
> sane state, before then progressing with the driver in a sane manner.
> This is what Ulf is doing.
Aha, mea culpa.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
For all of them, I'll read up on this exploding backlog and then Ulf
will hammer me at the office until I understand this stuff properly...
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 10/12] gpio: pcf857x: select IRQ_DOMAIN
From: Linus Walleij @ 2012-09-30 21:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1348868177-21205-11-git-send-email-arnd@arndb.de>
On Fri, Sep 28, 2012 at 11:36 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> Patch 6e20a0a4 "gpio: pcf857x: enable gpio_to_irq() support"
> added IRQ domain support to the pcf857x driver, but some configurations
> (e.g. davinci_all_defconfig) don't already enable CONFIG_IRQ_DOMAIN.
Excellent patch Arnd thanks for this!
Applied to my GPIO tree (where the offending patch is queued).
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 06/15] KVM: ARM: Initial skeleton to compile KVM support
From: Christoffer Dall @ 2012-09-30 19:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120927141314.GK25916@mudshark.cambridge.arm.com>
On Thu, Sep 27, 2012 at 10:13 AM, Will Deacon <will.deacon@arm.com> wrote:
> On Wed, Sep 26, 2012 at 02:43:14AM +0100, Christoffer Dall wrote:
>> On 09/25/2012 11:20 AM, Will Deacon wrote:
>> >> +/* Multiprocessor Affinity Register */
>> >> +#define MPIDR_CPUID (0x3 << 0)
>> >
>> > I'm fairly sure we already have code under arch/arm/ for dealing with the
>> > mpidr. Let's re-use that rather than reinventing it here.
>> >
>>
>> I see some defines in topology.c - do you want some of these factored
>> out into a header file that we can then also use from kvm? If so, where?
>
> I guess either in topology.h or a new header (topology-bits.h).
>
>> >> +#define EXCEPTION_NONE 0
>> >> +#define EXCEPTION_RESET 0x80
>> >> +#define EXCEPTION_UNDEFINED 0x40
>> >> +#define EXCEPTION_SOFTWARE 0x20
>> >> +#define EXCEPTION_PREFETCH 0x10
>> >> +#define EXCEPTION_DATA 0x08
>> >> +#define EXCEPTION_IMPRECISE 0x04
>> >> +#define EXCEPTION_IRQ 0x02
>> >> +#define EXCEPTION_FIQ 0x01
>> >
>> > Why the noise?
>> >
>>
>> these are simply cruft from a previous life of KVM/ARM.
>
> Ok, then please get rid of them.
>
>> >> +static inline enum vcpu_mode vcpu_mode(struct kvm_vcpu *vcpu)
>> >> +{
>> >> + u8 mode = __vcpu_mode(vcpu->arch.regs.cpsr);
>> >> + BUG_ON(mode == 0xf);
>> >> + return mode;
>> >> +}
>> >
>> > I noticed that you have a fair few BUG_ONs throughout the series. Fair
>> > enough, but for hyp code is that really the right thing to do? Killing the
>> > guest could make more sense, perhaps?
>>
>> the idea is to have BUG_ONs that are indeed BUG_ONs that we want to
>> catch explicitly on the host. We have had a pass over the code to change
>> all the BUG_ONs that can be provoked by the guest and inject the proper
>> exceptions into the guest in this case. If you find places where this is
>> not the case, it should be changed, and do let me know.
>
> Ok, so are you saying that a BUG_ON due to some detected inconsistency with
> one guest may not necessarily terminate the other guests? BUG_ONs in the
> host seem like a bad idea if the host is able to continue with a subset of
> guests.
>
No, I'm saying a BUG_ON is an actual BUG, it should not happen and
there should be nowhere where a guest can cause a BUG_ON to occur in
the host, because that would be a bug.
We basically never kill a guest unless really extreme things happen
(like we cannot allocate a pte, in which case we return -ENOMEM). If a
guest does something really weird, that guest will receive the
appropriate exception (undefined, prefetch abort, ...)
>> >
>> >> +static inline u32 *vcpu_pc(struct kvm_vcpu *vcpu)
>> >> +{
>> >> + return vcpu_reg(vcpu, 15);
>> >> +}
>> >
>> > If you stick a struct pt_regs into struct kvm_regs, you could reuse ARM_pc
>> > here etc.
>> >
>>
>> I prefer not to, because we'd have those registers presumably for usr
>> mode and then we only define the others explicit. I think it's much
>> clearer to look at kvm_regs today.
>
> I disagree and think that you should reuse as much of the arch/arm/ code as
> possible. Not only does it make it easier to read by people who are familiar
> with that code (and in turn get you more reviewers) but it also means that
> we limit the amount of duplication that we have.
Reusing a struct just for the sake of reusing is not necessarily an
improvement. Some times it complicates things, and some times it's
misleading. To me, pt_regs carry the meaning that these are the
registers for a user space process that traps into the kernel - in KVM
we emulate a virtual CPU and that current definition is quite clear.
The argument that more people will review the code if the struct
contains a pt_regs field rather than a usr_regs field is completely
invalid, because I'm sure everyone that reviews virtualization code
will know that user mode is a mode on the cpu and it has some
registers and this is the state we store when we context switch a VM -
pt_regs could be read as the regs that we stored in the mode that the
VM happened to be in when we took an exception, which I would think is
crazy, and probably not what you suggest.
Writing the literal 15 for the PC register is not really a problem in
terms of duplication - it's nothing that requires separate
maintenance.
At this point the priority should really be correctness, readability,
and performance, imho.
>
> I think Marc (CC'd) had a go at this with some success.
>
great, if this improves the code, then I suggest someone rebases an
appropriate patch and sends it to the kvmarm mailing list so we can
have a look at it, but there are users out there looking to try
kvm/arm and we should try to give it to them.
>> >> +#ifndef __ARM_KVM_HOST_H__
>> >> +#define __ARM_KVM_HOST_H__
>> >> +
>> >> +#include <asm/kvm.h>
>> >> +
>> >> +#define KVM_MAX_VCPUS 4
>> >
>> > NR_CPUS?
>> >
>>
>> well this is defined by KVM generic code, and is common for other
>> architecture.
>
> I mean #define KVM_MAX_CPUS NR_CPUS. The 4 seems arbitrary.
>
>> >> +int __attribute_const__ kvm_target_cpu(void)
>> >> +{
>> >> + unsigned int midr;
>> >> +
>> >> + midr = read_cpuid_id();
>> >> + switch ((midr >> 4) & 0xfff) {
>> >> + case KVM_ARM_TARGET_CORTEX_A15:
>> >> + return KVM_ARM_TARGET_CORTEX_A15;
>> >
>> > I have this code already in perf_event.c. Can we move it somewhere common
>> > and share it? You should also check that the implementor field is 0x41.
>> >
>>
>> by all means, you can probably suggest a good place better than I can...
>
> cputype.h?
>
>> >> +#include <linux/module.h>
>> >> +
>> >> +EXPORT_SYMBOL_GPL(smp_send_reschedule);
>> >
>> > Erm...
>> >
>> > We already have arch/arm/kernel/armksyms.c for exports -- please use that.
>> > However, exporting such low-level operations sounds like a bad idea. How
>> > realistic is kvm-as-a-module on ARM anyway?
>> >
>>
>> at this point it's broken, so I'll just remove this and leave this for a
>> fun project for some poor soul at some point if anyone ever needs half
>> the code outside the kernel as a module (the other half needs to be
>> compiled in anyway)
>
> Ok, that suits me. If it's broken, let's not include it in the initial
> submission.
>
>> >> +int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
>> >> +{
>> >> + return -EINVAL;
>> >> +}
>> >> +
>> >> +int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
>> >> +{
>> >> + return -EINVAL;
>> >> +}
>> >
>> > Again, all looks like this should be implemented using regsets from what I
>> > can tell.
>> >
>>
>> this API has been discussed to death on the KVM lists, and we can of
>> course revive that if the regset makes it nicer - I'd prefer getting
>> this upstream the way that it is now though, where GET_REG / SET_REG
>> seems to be the way forward from a KVM perspective.
>
> I'm sure the API has been discussed, but I've not seen that conversation and
> I'm also not aware about whether or not regsets were considered as a
> possibility for this stuff. The advantages of using them are:
>
> 1. It's less code for the arch to implement (and most of what you
> need, you already have).
>
> 2. You can move the actual copying code into core KVM, like we have
> for ptrace.
>
> 3. New KVM ports (e.g. arm64) can reuse the core copying code
> easily.
>
> Furthermore, some registers (typically) floating point and GPRs will already
> have regsets for the ptrace code, so that can be reused if you share the
> datatypes.
>
> The big problem with getting things upstream and then changing it later is
> that you will break the ABI. I highly doubt that's feasible, so can we not
> just use regsets from the start for ARM?
>
>> >> +int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
>> >> +{
>> >> + struct kvm_regs *cpu_reset;
>> >> +
>> >> + switch (vcpu->arch.target) {
>> >> + case KVM_ARM_TARGET_CORTEX_A15:
>> >> + if (vcpu->vcpu_id > a15_max_cpu_idx)
>> >> + return -EINVAL;
>> >> + cpu_reset = &a15_regs_reset;
>> >> + vcpu->arch.midr = read_cpuid_id();
>> >> + break;
>> >> + default:
>> >> + return -ENODEV;
>> >> + }
>> >> +
>> >> + /* Reset core registers */
>> >> + memcpy(&vcpu->arch.regs, cpu_reset, sizeof(vcpu->arch.regs));
>> >> +
>> >> + /* Reset CP15 registers */
>> >> + kvm_reset_coprocs(vcpu);
>> >> +
>> >> + return 0;
>> >> +}
>> >
>> > This is a nice way to plug in new CPUs but the way the rest of the code is
>> > currently written, all the ARMv7 and Cortex-A15 code is merged together. I
>> > *strongly* suggest you isolate this from the start, as it will help you see
>> > what is architected and what is implementation-specific.
>> >
>>
>> not entirely sure what you mean. You want a separate coproc.c file for
>> Cortex-A15 specific stuff like coproc_a15.c?
>
> Indeed. I think it will make adding new CPUs a lot clearer and separate the
> architecture from the implementation.
>
> Cheers,
>
> Will
^ permalink raw reply
* Booting vanilla kernel on the beaglebone
From: Tim Sander @ 2012-09-30 19:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120930082802.GA15392@netboy.at.omicron.at>
Hi Richard
> Does any vanilla kernel even boot on this board?
> If so, which ones, and how?
http://processors.wiki.ti.com/index.php/Sitara_Linux_Upstream_Status#AM335x_Linux_Status
It seems we are not there yet :-(.
Best regards
Tim
^ permalink raw reply
* [GIT PULL 2/3] omap platform and board related late patches for v3.7 merge window
From: Tony Lindgren @ 2012-09-30 18:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120929210324.GC12999@quad.lixom.net>
* Olof Johansson <olof@lixom.net> [120929 14:04]:
>
> Thanks, pulled this on top of the previous cleanup-headers.
>
> In the future, feel free to remove the tag that you don't want me to pull from
> the repo so I don't accidentally pull it anyway.
OK thanks will do.
Tony
^ permalink raw reply
* [PATCH 3/4] ARM: OMAP: Move omap_reserve() locally to mach-omap1/2
From: Tony Lindgren @ 2012-09-30 18:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMQu2gxN=gW_Gxr4awuJ4VT6RkZi_qHiTvmjwqbLKvCqb4RoyQ@mail.gmail.com>
* Shilimkar, Santosh <santosh.shilimkar@ti.com> [120930 01:21]:
> On Sun, Sep 30, 2012 at 1:09 AM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
> >
> > On Fri, Sep 28, 2012 at 07:10:08PM +0530, Lokesh Vutla wrote:
> > > omap_reserve() is a stub for omap1. So creating a
> > > stub locally in mach-omap1. And moving the definition
> > > to mach-omap2.
> > > This helps in moving plat/omap_secure.h local to
> > > mach-omap2
> > >
> > > Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> > > Acked-by : Santosh Shilimkar <santosh.shilimkar@ti.com>
> > > ---
> > > arch/arm/mach-omap1/common.h | 3 +++
> > > arch/arm/mach-omap2/common.c | 20 ++++++++++++++++++++
> > > arch/arm/mach-omap2/common.h | 1 +
> > > arch/arm/plat-omap/common.c | 17 -----------------
> > > arch/arm/plat-omap/include/plat/common.h | 1 -
> > > 5 files changed, 24 insertions(+), 18 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
> > > index c2552b2..f7b01f1 100644
> > > --- a/arch/arm/mach-omap1/common.h
> > > +++ b/arch/arm/mach-omap1/common.h
> > > @@ -90,4 +90,7 @@ extern int ocpi_enable(void);
> > > static inline int ocpi_enable(void) { return 0; }
> > > #endif
> > >
> > > +static inline void omap_reserve(void)
> > > +{ }
> >
> > This is the wrong approach. If OMAP1 doesn't need to do any reservation,
> > then OMAP1 platforms should not be calling omap_reserve() and OMAP1 should
> > not have this defined.
> >
> > Just because OMAP2 does something one way does not mean OMAP1 needs to
> > copy it in every detail.
>
> This patch just updated the code as is. I mean the empty reserve
> callback already
> exist before this patch.
>
> But I do agree with you. I think we can drop the reserve callback completly from
> OMAP1 board files and then its easier to just make the omap_reserve() local to
> OMAP2+ machines.
>
> Tony,
> Are you ok in dropping OMAP1 reserve callback from all OMAP1 machines ?
Sure if it's not doing anything.
Regards,
Tony
^ permalink raw reply
* [PATCH 10/15] KVM: ARM: World-switch implementation
From: Christoffer Dall @ 2012-09-30 17:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120925170031.GF28728@mudshark.cambridge.arm.com>
On Tue, Sep 25, 2012 at 1:00 PM, Will Deacon <will.deacon@arm.com> wrote:
> On Sat, Sep 15, 2012 at 04:35:33PM +0100, Christoffer Dall wrote:
>> diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
>> index 1429d89..cd8fc86 100644
>> --- a/arch/arm/kernel/asm-offsets.c
>> +++ b/arch/arm/kernel/asm-offsets.c
>> @@ -13,6 +13,7 @@
>> #include <linux/sched.h>
>> #include <linux/mm.h>
>> #include <linux/dma-mapping.h>
>> +#include <linux/kvm_host.h>
>> #include <asm/cacheflush.h>
>> #include <asm/glue-df.h>
>> #include <asm/glue-pf.h>
>> @@ -144,5 +145,48 @@ int main(void)
>> DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
>> DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
>> DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
>> +#ifdef CONFIG_KVM_ARM_HOST
>> + DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
>> + DEFINE(VCPU_MIDR, offsetof(struct kvm_vcpu, arch.midr));
>> + DEFINE(VCPU_MPIDR, offsetof(struct kvm_vcpu, arch.cp15[c0_MPIDR]));
>> + DEFINE(VCPU_CSSELR, offsetof(struct kvm_vcpu, arch.cp15[c0_CSSELR]));
>> + DEFINE(VCPU_SCTLR, offsetof(struct kvm_vcpu, arch.cp15[c1_SCTLR]));
>> + DEFINE(VCPU_CPACR, offsetof(struct kvm_vcpu, arch.cp15[c1_CPACR]));
>> + DEFINE(VCPU_TTBR0, offsetof(struct kvm_vcpu, arch.cp15[c2_TTBR0]));
>> + DEFINE(VCPU_TTBR1, offsetof(struct kvm_vcpu, arch.cp15[c2_TTBR1]));
>> + DEFINE(VCPU_TTBCR, offsetof(struct kvm_vcpu, arch.cp15[c2_TTBCR]));
>> + DEFINE(VCPU_DACR, offsetof(struct kvm_vcpu, arch.cp15[c3_DACR]));
>> + DEFINE(VCPU_DFSR, offsetof(struct kvm_vcpu, arch.cp15[c5_DFSR]));
>> + DEFINE(VCPU_IFSR, offsetof(struct kvm_vcpu, arch.cp15[c5_IFSR]));
>> + DEFINE(VCPU_ADFSR, offsetof(struct kvm_vcpu, arch.cp15[c5_ADFSR]));
>> + DEFINE(VCPU_AIFSR, offsetof(struct kvm_vcpu, arch.cp15[c5_AIFSR]));
>> + DEFINE(VCPU_DFAR, offsetof(struct kvm_vcpu, arch.cp15[c6_DFAR]));
>> + DEFINE(VCPU_IFAR, offsetof(struct kvm_vcpu, arch.cp15[c6_IFAR]));
>> + DEFINE(VCPU_PRRR, offsetof(struct kvm_vcpu, arch.cp15[c10_PRRR]));
>> + DEFINE(VCPU_NMRR, offsetof(struct kvm_vcpu, arch.cp15[c10_NMRR]));
>> + DEFINE(VCPU_VBAR, offsetof(struct kvm_vcpu, arch.cp15[c12_VBAR]));
>> + DEFINE(VCPU_CID, offsetof(struct kvm_vcpu, arch.cp15[c13_CID]));
>> + DEFINE(VCPU_TID_URW, offsetof(struct kvm_vcpu, arch.cp15[c13_TID_URW]));
>> + DEFINE(VCPU_TID_URO, offsetof(struct kvm_vcpu, arch.cp15[c13_TID_URO]));
>> + DEFINE(VCPU_TID_PRIV, offsetof(struct kvm_vcpu, arch.cp15[c13_TID_PRIV]));
>
> Could you instead define an offset for arch.cp15, then use scaled offsets
> from that in the assembly code?
>
that would require changing the enum in kvm_host.h to defines and
either wrap that whole file in #ifndef __ASSEMBLY__ or move those
defines to kvm_asm.h, not sure which I think is the most pretty:
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
index 5315c69..99c0faf 100644
--- a/arch/arm/include/asm/kvm_asm.h
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -19,6 +19,34 @@
#ifndef __ARM_KVM_ASM_H__
#define __ARM_KVM_ASM_H__
+/* 0 is reserved as an invalid value. */
+#define c0_MPIDR 1 /* MultiProcessor ID Register */
+#define c0_CSSELR 2 /* Cache Size Selection Register */
+#define c1_SCTLR 3 /* System Control Register */
+#define c1_ACTLR 4 /* Auxilliary Control Register */
+#define c1_CPACR 5 /* Coprocessor Access Control */
+#define c2_TTBR0 6 /* Translation Table Base Register 0 */
+#define c2_TTBR0_high 7 /* TTBR0 top 32 bits */
+#define c2_TTBR1 8 /* Translation Table Base Register 1 */
+#define c2_TTBR1_high 9 /* TTBR1 top 32 bits */
+#define c2_TTBCR 10 /* Translation Table Base Control R. */
+#define c3_DACR 11 /* Domain Access Control Register */
+#define c5_DFSR 12 /* Data Fault Status Register */
+#define c5_IFSR 13 /* Instruction Fault Status Register */
+#define c5_ADFSR 14 /* Auxilary Data Fault Status R */
+#define c5_AIFSR 15 /* Auxilary Instrunction Fault Status R */
+#define c6_DFAR 16 /* Data Fault Address Register */
+#define c6_IFAR 17 /* Instruction Fault Address Register */
+#define c9_L2CTLR 18 /* Cortex A15 L2 Control Register */
+#define c10_PRRR 19 /* Primary Region Remap Register */
+#define c10_NMRR 20 /* Normal Memory Remap Register */
+#define c12_VBAR 21 /* Vector Base Address Register */
+#define c13_CID 22 /* Context ID Register */
+#define c13_TID_URW 23 /* Thread ID, User R/W */
+#define c13_TID_URO 24 /* Thread ID, User R/O */
+#define c13_TID_PRIV 25 /* Thread ID, Priveleged */
+#define NR_CP15_REGS 26 /* Number of regs (incl. invalid) */
+
#define ARM_EXCEPTION_RESET 0
#define ARM_EXCEPTION_UNDEFINED 1
#define ARM_EXCEPTION_SOFTWARE 2
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 9c4fbd4..f9b2ca6 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -21,6 +21,7 @@
#include <asm/kvm.h>
#include <asm/fpstate.h>
+#include <asm/kvm_asm.h>
#define KVM_MAX_VCPUS NR_CPUS
#define KVM_MEMORY_SLOTS 32
@@ -73,37 +74,6 @@ struct kvm_mmu_memory_cache {
void *objects[KVM_NR_MEM_OBJS];
};
-/* 0 is reserved as an invalid value. */
-enum cp15_regs {
- c0_MPIDR=1, /* MultiProcessor ID Register */
- c0_CSSELR, /* Cache Size Selection Register */
- c1_SCTLR, /* System Control Register */
- c1_ACTLR, /* Auxilliary Control Register */
- c1_CPACR, /* Coprocessor Access Control */
- c2_TTBR0, /* Translation Table Base Register 0 */
- c2_TTBR0_high, /* TTBR0 top 32 bits */
- c2_TTBR1, /* Translation Table Base Register 1 */
- c2_TTBR1_high, /* TTBR1 top 32 bits */
- c2_TTBCR, /* Translation Table Base Control R. */
- c3_DACR, /* Domain Access Control Register */
- c5_DFSR, /* Data Fault Status Register */
- c5_IFSR, /* Instruction Fault Status Register */
- c5_ADFSR, /* Auxilary Data Fault Status Register */
- c5_AIFSR, /* Auxilary Instruction Fault Status Register */
- c6_DFAR, /* Data Fault Address Register */
- c6_IFAR, /* Instruction Fault Address Register */
- c9_L2CTLR, /* Cortex A15 L2 Control Register */
- c10_PRRR, /* Primary Region Remap Register */
- c10_NMRR, /* Normal Memory Remap Register */
- c12_VBAR, /* Vector Base Address Register */
- c13_CID, /* Context ID Register */
- c13_TID_URW, /* Thread ID, User R/W */
- c13_TID_URO, /* Thread ID, User R/O */
- c13_TID_PRIV, /* Thread ID, Priveleged */
-
- nr_cp15_regs
-};
-
struct kvm_vcpu_arch {
struct kvm_regs regs;
@@ -111,7 +81,7 @@ struct kvm_vcpu_arch {
DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
/* System control coprocessor (cp15) */
- u32 cp15[nr_cp15_regs];
+ u32 cp15[NR_CP15_REGS];
/* The CPU type we expose to the VM */
u32 midr;
@@ -203,4 +173,5 @@ unsigned long kvm_arm_num_coproc_regs(struct
kvm_vcpu *vcpu);
struct kvm_one_reg;
int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+
#endif /* __ARM_KVM_HOST_H__ */
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index cf0b50e..1c4181e 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -148,27 +148,7 @@ int main(void)
#ifdef CONFIG_KVM_ARM_HOST
DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
DEFINE(VCPU_MIDR, offsetof(struct kvm_vcpu, arch.midr));
- DEFINE(VCPU_MPIDR, offsetof(struct kvm_vcpu, arch.cp15[c0_MPIDR]));
- DEFINE(VCPU_CSSELR, offsetof(struct kvm_vcpu, arch.cp15[c0_CSSELR]));
- DEFINE(VCPU_SCTLR, offsetof(struct kvm_vcpu, arch.cp15[c1_SCTLR]));
- DEFINE(VCPU_CPACR, offsetof(struct kvm_vcpu, arch.cp15[c1_CPACR]));
- DEFINE(VCPU_TTBR0, offsetof(struct kvm_vcpu, arch.cp15[c2_TTBR0]));
- DEFINE(VCPU_TTBR1, offsetof(struct kvm_vcpu, arch.cp15[c2_TTBR1]));
- DEFINE(VCPU_TTBCR, offsetof(struct kvm_vcpu, arch.cp15[c2_TTBCR]));
- DEFINE(VCPU_DACR, offsetof(struct kvm_vcpu, arch.cp15[c3_DACR]));
- DEFINE(VCPU_DFSR, offsetof(struct kvm_vcpu, arch.cp15[c5_DFSR]));
- DEFINE(VCPU_IFSR, offsetof(struct kvm_vcpu, arch.cp15[c5_IFSR]));
- DEFINE(VCPU_ADFSR, offsetof(struct kvm_vcpu, arch.cp15[c5_ADFSR]));
- DEFINE(VCPU_AIFSR, offsetof(struct kvm_vcpu, arch.cp15[c5_AIFSR]));
- DEFINE(VCPU_DFAR, offsetof(struct kvm_vcpu, arch.cp15[c6_DFAR]));
- DEFINE(VCPU_IFAR, offsetof(struct kvm_vcpu, arch.cp15[c6_IFAR]));
- DEFINE(VCPU_PRRR, offsetof(struct kvm_vcpu, arch.cp15[c10_PRRR]));
- DEFINE(VCPU_NMRR, offsetof(struct kvm_vcpu, arch.cp15[c10_NMRR]));
- DEFINE(VCPU_VBAR, offsetof(struct kvm_vcpu, arch.cp15[c12_VBAR]));
- DEFINE(VCPU_CID, offsetof(struct kvm_vcpu, arch.cp15[c13_CID]));
- DEFINE(VCPU_TID_URW, offsetof(struct kvm_vcpu, arch.cp15[c13_TID_URW]));
- DEFINE(VCPU_TID_URO, offsetof(struct kvm_vcpu, arch.cp15[c13_TID_URO]));
- DEFINE(VCPU_TID_PRIV, offsetof(struct kvm_vcpu, arch.cp15[c13_TID_PRIV]));
+ DEFINE(VCPU_CP15, offsetof(struct kvm_vcpu, arch.cp15));
DEFINE(VCPU_VFP_GUEST, offsetof(struct kvm_vcpu, arch.vfp_guest));
DEFINE(VCPU_VFP_HOST, offsetof(struct kvm_vcpu, arch.vfp_host));
DEFINE(VCPU_REGS, offsetof(struct kvm_vcpu, arch.regs));
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 15977a6..759396a 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -61,7 +61,7 @@ struct coproc_reg {
void (*reset)(struct kvm_vcpu *, const struct coproc_reg *);
/* Index into vcpu->arch.cp15[], or 0 if we don't need to save it. */
- enum cp15_regs reg;
+ unsigned long reg;
/* Value (usually reset value) */
u64 val;
@@ -1097,7 +1097,7 @@ void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
table = get_target_table(vcpu->arch.target, &num);
reset_coproc_regs(vcpu, table, num);
- for (num = 1; num < nr_cp15_regs; num++)
+ for (num = 1; num < NR_CP15_REGS; num++)
if (vcpu->arch.cp15[num] == 0x42424242)
panic("Didn't reset vcpu->arch.cp15[%zi]", num);
}
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
index f32e2f7..2839afa 100644
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -29,6 +29,7 @@
#define VCPU_USR_SP (VCPU_USR_REG(13))
#define VCPU_FIQ_REG(_reg_nr) (VCPU_FIQ_REGS + (_reg_nr * 4))
#define VCPU_FIQ_SPSR (VCPU_FIQ_REG(7))
+#define CP15_OFFSET(_cp15_reg_idx) (VCPU_CP15 + (_cp15_reg_idx * 4))
.text
.align PAGE_SHIFT
@@ -202,18 +203,18 @@ ENDPROC(__kvm_flush_vm_context)
.if \vcpu == 0
push {r2-r12} @ Push CP15 registers
.else
- str r2, [\vcpup, #VCPU_SCTLR]
- str r3, [\vcpup, #VCPU_CPACR]
- str r4, [\vcpup, #VCPU_TTBCR]
- str r5, [\vcpup, #VCPU_DACR]
- add \vcpup, \vcpup, #VCPU_TTBR0
+ str r2, [\vcpup, #CP15_OFFSET(c1_SCTLR)]
+ str r3, [\vcpup, #CP15_OFFSET(c1_CPACR)]
+ str r4, [\vcpup, #CP15_OFFSET(c2_TTBCR)]
+ str r5, [\vcpup, #CP15_OFFSET(c3_DACR)]
+ add \vcpup, \vcpup, #CP15_OFFSET(c2_TTBR0)
strd r6, r7, [\vcpup]
- add \vcpup, \vcpup, #(VCPU_TTBR1 - VCPU_TTBR0)
+ add \vcpup, \vcpup, #CP15_OFFSET(c2_TTBR1) - CP15_OFFSET(c2_TTBR0)
strd r8, r9, [\vcpup]
- sub \vcpup, \vcpup, #(VCPU_TTBR1)
- str r10, [\vcpup, #VCPU_PRRR]
- str r11, [\vcpup, #VCPU_NMRR]
- str r12, [\vcpup, #VCPU_CSSELR]
+ sub \vcpup, \vcpup, #CP15_OFFSET(c2_TTBR1)
+ str r10, [\vcpup, #CP15_OFFSET(c10_PRRR)]
+ str r11, [\vcpup, #CP15_OFFSET(c10_NMRR)]
+ str r12, [\vcpup, #CP15_OFFSET(c0_CSSELR)]
.endif
mrc p15, 0, r2, c13, c0, 1 @ CID
@@ -231,17 +232,17 @@ ENDPROC(__kvm_flush_vm_context)
.if \vcpu == 0
push {r2-r12} @ Push CP15 registers
.else
- str r2, [\vcpup, #VCPU_CID]
- str r3, [\vcpup, #VCPU_TID_URW]
- str r4, [\vcpup, #VCPU_TID_URO]
- str r5, [\vcpup, #VCPU_TID_PRIV]
- str r6, [\vcpup, #VCPU_DFSR]
- str r7, [\vcpup, #VCPU_IFSR]
- str r8, [\vcpup, #VCPU_ADFSR]
- str r9, [\vcpup, #VCPU_AIFSR]
- str r10, [\vcpup, #VCPU_DFAR]
- str r11, [\vcpup, #VCPU_IFAR]
- str r12, [\vcpup, #VCPU_VBAR]
+ str r2, [\vcpup, #CP15_OFFSET(c13_CID)]
+ str r3, [\vcpup, #CP15_OFFSET(c13_TID_URW)]
+ str r4, [\vcpup, #CP15_OFFSET(c13_TID_URO)]
+ str r5, [\vcpup, #CP15_OFFSET(c13_TID_PRIV)]
+ str r6, [\vcpup, #CP15_OFFSET(c5_DFSR)]
+ str r7, [\vcpup, #CP15_OFFSET(c5_IFSR)]
+ str r8, [\vcpup, #CP15_OFFSET(c5_ADFSR)]
+ str r9, [\vcpup, #CP15_OFFSET(c5_AIFSR)]
+ str r10, [\vcpup, #CP15_OFFSET(c6_DFAR)]
+ str r11, [\vcpup, #CP15_OFFSET(c6_IFAR)]
+ str r12, [\vcpup, #CP15_OFFSET(c12_VBAR)]
.endif
.endm
@@ -254,17 +255,17 @@ ENDPROC(__kvm_flush_vm_context)
.if \vcpu == 0
pop {r2-r12}
.else
- ldr r2, [\vcpup, #VCPU_CID]
- ldr r3, [\vcpup, #VCPU_TID_URW]
- ldr r4, [\vcpup, #VCPU_TID_URO]
- ldr r5, [\vcpup, #VCPU_TID_PRIV]
- ldr r6, [\vcpup, #VCPU_DFSR]
- ldr r7, [\vcpup, #VCPU_IFSR]
- ldr r8, [\vcpup, #VCPU_ADFSR]
- ldr r9, [\vcpup, #VCPU_AIFSR]
- ldr r10, [\vcpup, #VCPU_DFAR]
- ldr r11, [\vcpup, #VCPU_IFAR]
- ldr r12, [\vcpup, #VCPU_VBAR]
+ ldr r2, [\vcpup, #CP15_OFFSET(c13_CID)]
+ ldr r3, [\vcpup, #CP15_OFFSET(c13_TID_URW)]
+ ldr r4, [\vcpup, #CP15_OFFSET(c13_TID_URO)]
+ ldr r5, [\vcpup, #CP15_OFFSET(c13_TID_PRIV)]
+ ldr r6, [\vcpup, #CP15_OFFSET(c5_DFSR)]
+ ldr r7, [\vcpup, #CP15_OFFSET(c5_IFSR)]
+ ldr r8, [\vcpup, #CP15_OFFSET(c5_ADFSR)]
+ ldr r9, [\vcpup, #CP15_OFFSET(c5_AIFSR)]
+ ldr r10, [\vcpup, #CP15_OFFSET(c6_DFAR)]
+ ldr r11, [\vcpup, #CP15_OFFSET(c6_IFAR)]
+ ldr r12, [\vcpup, #CP15_OFFSET(c12_VBAR)]
.endif
mcr p15, 0, r2, c13, c0, 1 @ CID
@@ -282,18 +283,18 @@ ENDPROC(__kvm_flush_vm_context)
.if \vcpu == 0
pop {r2-r12}
.else
- ldr r2, [\vcpup, #VCPU_SCTLR]
- ldr r3, [\vcpup, #VCPU_CPACR]
- ldr r4, [\vcpup, #VCPU_TTBCR]
- ldr r5, [\vcpup, #VCPU_DACR]
- add \vcpup, \vcpup, #VCPU_TTBR0
+ ldr r2, [\vcpup, #CP15_OFFSET(c1_SCTLR)]
+ ldr r3, [\vcpup, #CP15_OFFSET(c1_CPACR)]
+ ldr r4, [\vcpup, #CP15_OFFSET(c2_TTBCR)]
+ ldr r5, [\vcpup, #CP15_OFFSET(c3_DACR)]
+ add \vcpup, \vcpup, #CP15_OFFSET(c2_TTBR0)
ldrd r6, r7, [\vcpup]
- add \vcpup, \vcpup, #(VCPU_TTBR1 - VCPU_TTBR0)
+ add \vcpup, \vcpup, #CP15_OFFSET(c2_TTBR1) - CP15_OFFSET(c2_TTBR0)
ldrd r8, r9, [\vcpup]
- sub \vcpup, \vcpup, #(VCPU_TTBR1)
- ldr r10, [\vcpup, #VCPU_PRRR]
- ldr r11, [\vcpup, #VCPU_NMRR]
- ldr r12, [\vcpup, #VCPU_CSSELR]
+ sub \vcpup, \vcpup, #CP15_OFFSET(c2_TTBR1)
+ ldr r10, [\vcpup, #CP15_OFFSET(c10_PRRR)]
+ ldr r11, [\vcpup, #CP15_OFFSET(c10_NMRR)]
+ ldr r12, [\vcpup, #CP15_OFFSET(c0_CSSELR)]
.endif
mcr p15, 0, r2, c1, c0, 0 @ SCTLR
@@ -556,7 +557,7 @@ ENTRY(__kvm_vcpu_run)
mcr p15, 4, r1, c0, c0, 0
@ Write guest view of MPIDR into VMPIDR
- ldr r1, [r0, #VCPU_MPIDR]
+ ldr r1, [r0, #CP15_OFFSET(c0_MPIDR)]
mcr p15, 4, r1, c0, c0, 5
@ Load guest registers
>> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
>> index 8a87fc7..087f9d1 100644
>> --- a/arch/arm/kvm/arm.c
>> +++ b/arch/arm/kvm/arm.c
>> @@ -41,6 +41,7 @@
>> #include <asm/kvm_arm.h>
>> #include <asm/kvm_asm.h>
>> #include <asm/kvm_mmu.h>
>> +#include <asm/kvm_emulate.h>
>>
>> #ifdef REQUIRES_VIRT
>> __asm__(".arch_extension virt");
>> @@ -50,6 +51,10 @@ static DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_page);
>> static struct vfp_hard_struct __percpu *kvm_host_vfp_state;
>> static unsigned long hyp_default_vectors;
>>
>> +/* The VMID used in the VTTBR */
>> +static atomic64_t kvm_vmid_gen = ATOMIC64_INIT(1);
>> +static u8 kvm_next_vmid;
>> +static DEFINE_SPINLOCK(kvm_vmid_lock);
>>
>> int kvm_arch_hardware_enable(void *garbage)
>> {
>> @@ -273,6 +278,7 @@ void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
>> void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
>> {
>> vcpu->cpu = cpu;
>> + vcpu->arch.vfp_host = this_cpu_ptr(kvm_host_vfp_state);
>> }
>>
>> void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
>> @@ -305,12 +311,169 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
>>
>> int kvm_arch_vcpu_in_guest_mode(struct kvm_vcpu *v)
>> {
>> + return v->mode == IN_GUEST_MODE;
>> +}
>> +
>> +static void reset_vm_context(void *info)
>> +{
>> + __kvm_flush_vm_context();
>> +}
>> +
>> +/**
>> + * need_new_vmid_gen - check that the VMID is still valid
>> + * @kvm: The VM's VMID to checkt
>> + *
>> + * return true if there is a new generation of VMIDs being used
>> + *
>> + * The hardware supports only 256 values with the value zero reserved for the
>> + * host, so we check if an assigned value belongs to a previous generation,
>> + * which which requires us to assign a new value. If we're the first to use a
>> + * VMID for the new generation, we must flush necessary caches and TLBs on all
>> + * CPUs.
>> + */
>> +static bool need_new_vmid_gen(struct kvm *kvm)
>> +{
>> + return unlikely(kvm->arch.vmid_gen != atomic64_read(&kvm_vmid_gen));
>> +}
>> +
>> +/**
>> + * update_vttbr - Update the VTTBR with a valid VMID before the guest runs
>> + * @kvm The guest that we are about to run
>> + *
>> + * Called from kvm_arch_vcpu_ioctl_run before entering the guest to ensure the
>> + * VM has a valid VMID, otherwise assigns a new one and flushes corresponding
>> + * caches and TLBs.
>> + */
>> +static void update_vttbr(struct kvm *kvm)
>> +{
>> + phys_addr_t pgd_phys;
>> +
>> + if (!need_new_vmid_gen(kvm))
>> + return;
>> +
>> + spin_lock(&kvm_vmid_lock);
>> +
>> + /* First user of a new VMID generation? */
>> + if (unlikely(kvm_next_vmid == 0)) {
>> + atomic64_inc(&kvm_vmid_gen);
>> + kvm_next_vmid = 1;
>> +
>> + /*
>> + * On SMP we know no other CPUs can use this CPU's or
>> + * each other's VMID since the kvm_vmid_lock blocks
>> + * them from reentry to the guest.
>> + */
>> + on_each_cpu(reset_vm_context, NULL, 1);
>
> Why on_each_cpu? The maintenance operations should be broadcast, right?
>
we need each cpu (that runs guests) to exit guests and pick up the new
vmid in their vttbr.
>> + }
>> +
>> + kvm->arch.vmid_gen = atomic64_read(&kvm_vmid_gen);
>> + kvm->arch.vmid = kvm_next_vmid;
>> + kvm_next_vmid++;
>> +
>> + /* update vttbr to be used with the new vmid */
>> + pgd_phys = virt_to_phys(kvm->arch.pgd);
>> + kvm->arch.vttbr = pgd_phys & ((1LLU << 40) - 1)
>> + & ~((2 << VTTBR_X) - 1);
>> + kvm->arch.vttbr |= (u64)(kvm->arch.vmid) << 48;
>> +
>> + spin_unlock(&kvm_vmid_lock);
>> +}
>
> This smells like a watered-down version of the ASID allocator. Now, I can't
> really see much code sharing going on here, but perhaps your case is
> simpler... do you anticipate running more than 255 VMs in parallel? If not,
> then you could just invalidate the relevant TLB entries on VM shutdown and
> avoid the rollover case.
>
I want to support running more than 255 VMs in parallel. I think
trying to share code with the ASID allocator complicates things
without any real benefit.
>> diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
>> index edf9ed5..cc9448b 100644
>> --- a/arch/arm/kvm/interrupts.S
>> +++ b/arch/arm/kvm/interrupts.S
>> @@ -23,6 +23,12 @@
>> #include <asm/asm-offsets.h>
>> #include <asm/kvm_asm.h>
>> #include <asm/kvm_arm.h>
>> +#include <asm/vfpmacros.h>
>> +
>> +#define VCPU_USR_REG(_reg_nr) (VCPU_USR_REGS + (_reg_nr * 4))
>> +#define VCPU_USR_SP (VCPU_USR_REG(13))
>> +#define VCPU_FIQ_REG(_reg_nr) (VCPU_FIQ_REGS + (_reg_nr * 4))
>> +#define VCPU_FIQ_SPSR (VCPU_FIQ_REG(7))
>>
>> .text
>> .align PAGE_SHIFT
>> @@ -34,7 +40,33 @@ __kvm_hyp_code_start:
>> @ Flush per-VMID TLBs
>> @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
>
> This comment syntax crops up a few times in your .S files but doesn't match
> anything currently under arch/arm/. Please can you follow what we do there
> and use /* */ ?
>
sure
>> ENTRY(__kvm_tlb_flush_vmid)
>> + hvc #0 @ Switch to Hyp mode
>> + push {r2, r3}
>> +
>> + add r0, r0, #KVM_VTTBR
>> + ldrd r2, r3, [r0]
>> + mcrr p15, 6, r2, r3, c2 @ Write VTTBR
>> + isb
>> + mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS (rt ignored)
>> + dsb
>> + isb
>> + mov r2, #0
>> + mov r3, #0
>> + mcrr p15, 6, r2, r3, c2 @ Back to VMID #0
>> + isb
>
> Do you need this isb, given that you're about to do an hvc?
>
they're gone
>> + pop {r2, r3}
>> + hvc #0 @ Back to SVC
>> bx lr
>> ENDPROC(__kvm_tlb_flush_vmid)
>>
>> @@ -42,26 +74,702 @@ ENDPROC(__kvm_tlb_flush_vmid)
>> @ Flush TLBs and instruction caches of current CPU for all VMIDs
>> @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
>>
>> +/*
>> + * void __kvm_flush_vm_context(void);
>> + */
>> ENTRY(__kvm_flush_vm_context)
>> + hvc #0 @ switch to hyp-mode
>> +
>> + mov r0, #0 @ rn parameter for c15 flushes is SBZ
>> + mcr p15, 4, r0, c8, c7, 4 @ Invalidate Non-secure Non-Hyp TLB
>> + mcr p15, 0, r0, c7, c5, 0 @ Invalidate instruction caches
>> + dsb
>> + isb
>
> Likewise.
>
ditto
>> + hvc #0 @ switch back to svc-mode, see hyp_svc
>> bx lr
>> ENDPROC(__kvm_flush_vm_context)
>>
>> +/* These are simply for the macros to work - value don't have meaning */
>> +.equ usr, 0
>> +.equ svc, 1
>> +.equ abt, 2
>> +.equ und, 3
>> +.equ irq, 4
>> +.equ fiq, 5
>> +
>> +.macro store_mode_state base_reg, mode
>> + .if \mode == usr
>> + mrs r2, SP_usr
>> + mov r3, lr
>> + stmdb \base_reg!, {r2, r3}
>> + .elseif \mode != fiq
>> + mrs r2, SP_\mode
>> + mrs r3, LR_\mode
>> + mrs r4, SPSR_\mode
>> + stmdb \base_reg!, {r2, r3, r4}
>> + .else
>> + mrs r2, r8_fiq
>> + mrs r3, r9_fiq
>> + mrs r4, r10_fiq
>> + mrs r5, r11_fiq
>> + mrs r6, r12_fiq
>> + mrs r7, SP_fiq
>> + mrs r8, LR_fiq
>> + mrs r9, SPSR_fiq
>> + stmdb \base_reg!, {r2-r9}
>> + .endif
>> +.endm
>
> Perhaps you could stick the assembly macros into a separate file, like we do
> in assembler.h, so the code is more readable and they can be reused if
> need-be?
>
This is a lot of code to stick in a header file (hard to read within C
constructs, no assembly syntax highlighting, cannot use @ for
end-of-line comments), but I factored it out to interrupts_header.S,
which makes it nicer to read interrupts.S and it should be easy to
factor out pieces if ever needed anywhere else.
-Christoffer
^ permalink raw reply related
* [PATCH 2/3] iommu/omap: Merge iommu2.h into iommu.h
From: Ido Yariv @ 2012-09-30 17:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120927195526.GP4840@atomide.com>
On Thu, Sep 27, 2012 at 12:55:26PM -0700, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [120927 12:54]:
> > Hi Ido,
> >
> > * Ido Yariv <ido@wizery.com> [120920 22:15]:
> > > Since iommu is not currently supported on OMAP1, merge plat/iommu2.h into
> > > iommu.h so only one file would have to move to platform_data/ as part of the
> > > single zImage effort.
> >
> > Looks like you need patch 2.5/3 in this series too that
> > makes some of the things defined in iommu.h local.
> >
> > We should only have platform data in include/linux/platform_data,
> > so things that are private to drivers should be defined in the
> > driver, and things that are private to arch/arm/mach-omap2 should
> > defined locally there.
> >
> > Based on a quick grepping of files, looks like these should be
> > defined in omap-iommu.c driver and not in the platform_data header:
> >
> > struct iotlb_lock
> > struct iotlb_lock
> > dev_to_omap_iommu
> > various register defines
> > omap_iommu_arch_version
> > omap_iotlb_cr_to_e
> > omap_iopgtable_store_entry
> > omap_iommu_save_ctx
> > omap_iommu_restore_ctx
> > omap_foreach_iommu_device
> > omap_iommu_dump_ctx
> > omap_dump_tlb_entries
>
> And looks like while at it, you can also move plat/iopgtable.h
> and put it in some drivers/iommu/*.h file that's shared by
> omap-iommu*.c and omap-iovmm.c drivers ;)
Sure thing, I'll post a v2 shortly.
Thanks,
Ido.
^ permalink raw reply
* ARM SoC tree, Was: Re: [PATCH 05/12] ARM: ixp4xx: use __iomem for MMIO
From: Krzysztof Halasa @ 2012-09-30 17:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120929215355.GD6933@n2100.arm.linux.org.uk>
Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
>> Note I'm not only doing ARM, but also X86 and MIPS, with additional code
>> shared between them, and the "stable" part of it is what I'm paid for.
>> I can't simply work with arm-soc, none of my platforms will even boot
>> with pure arm-soc.
>
> I'm assuming that Linus' -rc kernels work for you, yes?
No, but it's OK :-)
I meant I need additional code for a) ARM and MIPS-based boards (off the
shelf by Ubiquity, Gateworks etc., support ported mostly from OpenWRT),
b) custom hardware used only by us.
I hope to eventually submit a) upstream, then arm-soc and Linus' trees
would work for me. I know it's a mess, but for now I have no options.
BTW the situation with hardware supported only by OpenWRT is a part of
the equation.
--
Krzysztof Halasa
^ permalink raw reply
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