* [PATCH 07/10] input: Enable STMPE keypad driver for Device Tree
From: Dmitry Torokhov @ 2012-10-10 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349451107-8009-8-git-send-email-lee.jones@linaro.org>
Hi Lee,
On Fri, Oct 05, 2012 at 04:31:43PM +0100, Lee Jones wrote:
> This patch allows the STMPE driver to be successfully probed and
> initialised when Device Tree support is enabled. Besides the usual
> platform data changes, we also separate the process of filling in
> the 'in use' pin bitmap, as we have to extract the information from
> Device Tree in the DT boot case.
This generally looks OK although I wonder if we could not unify DT and
non-DT case by doing:
for (row = 0; row < STMPE_KEYPAD_MAX_ROWS; row++) {
if (col = 0; col < STMPE_KEYPAD_MAX_COLS; col++) {
int code = MATRIX_SCAN_CODE(row, col,
STMPE_KEYPAD_ROW_SHIFT);
if (keypad->keymap[code] != KEY_RESERVED) {
keypad->rows |= 1 << row;
keypad->cols |= 1 << col;
}
}
}
BTW, am I supposed to merge it or ack it?
Thanks!
>
> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
> Cc: linux-input at vger.kernel.org
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Lee Jones <lee.jones@linaro.org>
> ---
> drivers/input/keyboard/stmpe-keypad.c | 67 ++++++++++++++++++++++++++++-----
> drivers/mfd/stmpe.c | 1 +
> 2 files changed, 59 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/input/keyboard/stmpe-keypad.c b/drivers/input/keyboard/stmpe-keypad.c
> index 470a877..c722d23 100644
> --- a/drivers/input/keyboard/stmpe-keypad.c
> +++ b/drivers/input/keyboard/stmpe-keypad.c
> @@ -257,19 +257,73 @@ static int __devinit stmpe_keypad_chip_init(struct stmpe_keypad *keypad)
> (plat->debounce_ms << 1));
> }
>
> +static int stmpe_keypad_fill_used_pins(struct platform_device *pdev,
> + struct stmpe_keypad *keypad,
> + struct stmpe_keypad_platform_data *plat)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + unsigned int proplen;
> + const __be32 *prop;
> + int i;
> +
> + if (np) {
> + prop = of_get_property(np, "linux,keymap", &proplen);
> + if (!prop) {
> + dev_err(&pdev->dev,
> + "linux,keymap property not defined\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < proplen / sizeof(u32); i++) {
> + unsigned int key = be32_to_cpup(prop + i);
> +
> + keypad->cols |= 1 << KEY_COL(key);
> + keypad->rows |= 1 << KEY_ROW(key);
> + }
> + } else {
> + for (i = 0; i < plat->keymap_data->keymap_size; i++) {
> + unsigned int key = plat->keymap_data->keymap[i];
> +
> + keypad->cols |= 1 << KEY_COL(key);
> + keypad->rows |= 1 << KEY_ROW(key);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void __devinit stmpe_keypad_of_probe(struct device_node *np,
> + struct stmpe_keypad_platform_data *plat)
> +{
> + of_property_read_u32(np, "debounce-interval", &plat->debounce_ms);
> + of_property_read_u32(np, "stericsson,scan-count", &plat->scan_count);
> +
> + if (of_get_property(np, "stericsson,no-autorepeat", NULL))
> + plat->no_autorepeat = true;
> +}
> +
> static int __devinit stmpe_keypad_probe(struct platform_device *pdev)
> {
> struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
> struct stmpe_keypad_platform_data *plat;
> + struct device_node *np = pdev->dev.of_node;
> struct stmpe_keypad *keypad;
> struct input_dev *input;
> int ret;
> int irq;
> - int i;
>
> plat = stmpe->pdata->keypad;
> - if (!plat)
> - return -ENODEV;
> + if (!plat) {
> + if (np) {
> + plat = devm_kzalloc(&pdev->dev,
> + sizeof(*plat), GFP_KERNEL);
> + if (!plat)
> + return -ENOMEM;
> +
> + stmpe_keypad_of_probe(np, plat);
> + } else
> + return -ENODEV;
> + }
>
> irq = platform_get_irq(pdev, 0);
> if (irq < 0)
> @@ -300,12 +354,7 @@ static int __devinit stmpe_keypad_probe(struct platform_device *pdev)
> if (!plat->no_autorepeat)
> __set_bit(EV_REP, input->evbit);
>
> - for (i = 0; i < plat->keymap_data->keymap_size; i++) {
> - unsigned int key = plat->keymap_data->keymap[i];
> -
> - keypad->cols |= 1 << KEY_COL(key);
> - keypad->rows |= 1 << KEY_ROW(key);
> - }
> + stmpe_keypad_fill_used_pins(pdev, keypad, plat);
>
> keypad->stmpe = stmpe;
> keypad->plat = plat;
> diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c
> index ba157d4..b03cc64 100644
> --- a/drivers/mfd/stmpe.c
> +++ b/drivers/mfd/stmpe.c
> @@ -321,6 +321,7 @@ static struct resource stmpe_keypad_resources[] = {
>
> static struct mfd_cell stmpe_keypad_cell = {
> .name = "stmpe-keypad",
> + .of_compatible = "st,stmpe-keypad",
> .resources = stmpe_keypad_resources,
> .num_resources = ARRAY_SIZE(stmpe_keypad_resources),
> };
> --
> 1.7.9.5
>
--
Dmitry
^ permalink raw reply
* [PATCH 01/11] fsmc/nand:FIX: Change the type for regs to void __iomem *
From: Linus Walleij @ 2012-10-10 16:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c30a9228d4bff7dbedd5d011f84c79c324736452.1349778820.git.vipin.kumar@st.com>
On Tue, Oct 9, 2012 at 12:44 PM, Vipin Kumar <vipin.kumar@st.com> wrote:
> Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 00/14] OMAP-GPMC related cleanup for common zImage
From: Ivan Djelic @ 2012-10-10 16:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A93E9F7B0A@DBDE01.ent.ti.com>
On Mon, Oct 08, 2012 at 07:08:08AM +0100, Mohammed, Afzal wrote:
> Hi Ivan,
>
> On Mon, Oct 08, 2012 at 11:05:56, Mohammed, Afzal wrote:
>
> > This series cleans up omap-gpmc related code so that omap can
> > be a part of common zImage.
>
> > This series moves gpmc.h from plat-omap/include/plat to mach-omap2
> > so that header file is local.
>
> > Patches 7 & 8 cleans up the already moved platform data header files
> > to contain only platform data. Also gpmc-nand information is moved
> > to nand platform data header.
> >
> > Patches 9-13 makes nand driver independent of gpmc header file
> >
> > And the final patch localizes gpmc header.
>
> BCH[48] support that you have added on OMAP using gpmc exported
> symbols has been changed such that nand driver now takes care
> of BCH support without relying on gpmc exported symbols.
>
> This is more or less a cut & paste of your implementation, which was
> necessitated now due to common ARM zImage cleanup w.r.t header files.
>
> Please verify that BCH[48] works as earlier with this series.
Hi Afzal,
I ran several mtd regression tests on a Beagle Board on your gpmc-czimage-v2 tag.
All BCH error correcting tests passed successfully.
I occasionally had weird read errors though, especially when reading blank pages:
the omap driver returned 512-byte sectors containing something like:
30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff
30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff
30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff
30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff
30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff
30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ff30ffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
instead of:
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
I was able to reproduce the problem also on l2-mtd tip, albeit less often.
The problem seems to occur quite randomly, it may be a hardware issue on
my board...
Anyway, the ECC handling part looks OK to me.
Best regards,
--
Ivan
^ permalink raw reply
* [PATCH 2/6] ARM: EXYNOS5: DT Support for SATA and SATA PHY
From: Olof Johansson @ 2012-10-10 16:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK1UHiyjyp8u-nFwU-19dds1uF7T1kkFNHyYQ6pWLFtUwGtR1w@mail.gmail.com>
Hi,
On Wed, Oct 10, 2012 at 02:08:31PM +0530, Vasanth Ananthan wrote:
> > > +
> > > + sataphy at 70 {
> >
> > sata-phy would be a more conventional name.
> >
> > > + compatible = "samsung,i2c-phy";
> >
> > i2c-phy? Seems like an odd choice of name. What is this device?
> >
>
> The SATA physical layer controller is both a platform device and a i2c
> slave device.
> This compatible string is for the i2c client driver. Hence I have used
> i2c-phy here.
Ok, but samsung,i2c-phy is much too generic. Maybe something like
samsung,exynos5-sata-phy (and rename the MMIO-controlled phy controls
to ...sata-phy-controller below).
> > > + };
> > > +
> > > + sata-phy at 12170000 {
> > > + compatible = "samsung,exynos-sata-phy";
> > > + reg = <0x12170000 0x1ff>;
> > > + };
> >
> > Should have binding too. How does this relate to the i2c device above.
> >
>
> As mentioned earlier SATA physical layer controller is both a platform
> device and also an i2c slave device.
> This Node is for the SATA physical layer platform device, the previous node
> is for i2c slave device.
> Certain initialization settings done directly and other settings has to be
> done through i2c.
Wow, that's quite awkward. What needs to be done over i2c? I think I have
seen use of SATA without touching the i2c side but it might have been for
a simple setup.
> > > +
> > > i2c at 12C60000 {
> > > compatible = "samsung,s3c2440-i2c";
> > > reg = <0x12C60000 0x100>;
> > > @@ -152,6 +164,13 @@
> > > #size-cells = <0>;
> > > };
> > >
> > > + i2c at 121D0000 {
> > > + compatible = "samsung,s3c2440-sataphy-i2c";
> >
> > Is this a unique i2c controller, or is it just another one like the others
> > on
> > the chip? If it's the latter, it should use the regular compatible string.
> >
>
> Yes, its a unique i2c controller which lacks an interrupt line while others
> are interrupt driven.
> Hence I have used a distinct compatible string for the driver to
> distinguish the controller.
It would be better to just make the i2c bus driver handle the case where there
is no interrupt specifier and just use polling in those cases, especially if
the rest of the device is identical and doesn't need special handling.
As a matter of fact, if that had been done for the hdmi phy, then you could
have done this patch without modifying the driver at all, just device tree
contents. And the same would go for the next time down the road when
a "special" i2c bus is added.
-Olof
^ permalink raw reply
* [PATCH 01/16] ARM: dts: exynos4210: Replace legacy GPIO bank nodes with pinctrl bank nodes
From: Stephen Warren @ 2012-10-10 16:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdZgH9TSr2uWQW+-8-U7BxJCscQgStVOndGixGmRz74TWw@mail.gmail.com>
On 10/10/2012 01:26 AM, Linus Walleij wrote:
> On Mon, Oct 8, 2012 at 10:39 AM, Tomasz Figa <t.figa@samsung.com> wrote:
>
>> Seuqential patches from this series introduce SoC-specific data parsing
>> from device tree.
>>
>> This patch removes legacy GPIO bank nodes from exynos4210.dtsi and
>> replaces them with nodes and properties required for these patches.
>
> So to be clear:
>
>> + pinctrl-bank-types {
>> + bank_off: bank-off {
>> + samsung,reg-names = "func", "dat", "pud",
>> + "drv", "conpdn", "pudpdn";
>> + samsung,reg-params = <0x00 4>, <0x04 1>, <0x08 2>,
>> + <0x0C 2>, <0x10 2>, <0x14 2>;
>> + };
>
> This is starting to look like a firmware language, I have mixed
> feelings about this. Shall this be read:
>
> "Poke 4 into 0x00, poke 1 into 0x04, poke 2 into 0x08" etc?
>
> We really need to discuss this, Grant has already NACK:ed
> such approaches once.
Well, I don't think he NACK'd Tony Lindgren's generic pinctrl driver,
which is doing this exact same thing. I did raise the same point about
Tony's driver when he posted it, but nobody seemed inclined to NACK it
based on that at the time, IIRC...
BTW, the idea here is IIRC to create a generic Samsung pinctrl driver
that works across N different Samsung SoCs, each with different register
layout, without having to encode the register layout into tables in the
kernel.
> If you're still going to do this, it is mandatory
> to NOT use magic hex numbers anymore, because Stephen has
> merged preprocessor support to the DTC compiler so you
> can use #defined macros.
>
> See commit:
> cd296721a9645f9f28800a072490fa15458d1fb7
That feature isn't enabled yet. While dtc has been modified to be able
to accept input that's been generated/processed by cpp, there is still
ongoing discussion about how/whether to actually enable *.dts to use
that feature.
^ permalink raw reply
* [PATCH v2 0/6] ARM: EXYNOS: Add secure firmware support
From: Olof Johansson @ 2012-10-10 16:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAH9JG2V56eLCCX+9id1EWhKfZ-6qW-3O0j0mVpzOjz5S8QGQ7g@mail.gmail.com>
Hi,
On Thu, Oct 11, 2012 at 12:35:54AM +0900, Kyungmin Park wrote:
> Hi Arnd or Olof,
>
> Can you pick up for v3.7?
>
> To Tomasz,
> Can you rebase it on the latest arm-soc tree?
This code should have been in arm-soc by the beginning of the merge window
(and in linux-next) to be merged for 3.7, but we will be happy to queue
it up for 3.8 once 3.7-rc1 is out. I have one outstanding comment on
the DT binding but the rest looks OK to me.
Tomasz, please rebase and send this to Kukjin so he can queue it up with other
Samsung code.
Thanks!
-Olof
^ permalink raw reply
* [PATCH v2 0/6] ARM: EXYNOS: Add secure firmware support
From: Olof Johansson @ 2012-10-10 16:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1348496913-25422-1-git-send-email-t.figa@samsung.com>
On Mon, Sep 24, 2012 at 04:28:27PM +0200, Tomasz Figa wrote:
> Some Exynos-based boards are running with secure firmware running in
> TrustZone secure world, which changes the way some things have to be
> initialized.
>
> This series adds support for specifying firmware operations, implements
> some firmware operations for Exynos secure firmware and adds a method of
> enabling secure firmware operations on Exynos-based boards through board
> file and device tree.
>
> Changes since v1
> http://thread.gmane.org/gmane.linux.kernel.samsung-soc/12583/focus=12820
> - Changed return types of all operations to int
> - Defined all operations to return 0 on success, -ENOSYS when not
> implemented or appropriate error code on error
>
> Tomasz Figa (6):
> ARM: Add interface for registering and calling firmware-specific
> operations
> ARM: EXYNOS: Add support for secure monitor calls
> ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
> ARM: EXYNOS: Add IO mapping for non-secure SYSRAM.
> ARM: EXYNOS: Add support for Exynos secure firmware
> ARM: EXYNOS: Add secure firmware support to secondary CPU bring-up
Besides the open comment on the device-tree binding, the other patches are:
Reviewed-by: Olof Johansson <olof@lixom.net>
^ permalink raw reply
* [PATCH 6/6] ARM: EXYNOS: Add secure firmware support to secondary CPU bring-up
From: Olof Johansson @ 2012-10-10 16:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1348496913-25422-7-git-send-email-t.figa@samsung.com>
On Mon, Sep 24, 2012 at 04:28:33PM +0200, Tomasz Figa wrote:
> Boards using secure firmware must use different CPU boot registers and
> call secure firmware to boot the CPU.
>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> ---
> arch/arm/mach-exynos/platsmp.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index a7f4031..4a18250 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -25,6 +25,7 @@
> #include <asm/hardware/gic.h>
> #include <asm/smp_plat.h>
> #include <asm/smp_scu.h>
> +#include <asm/firmware.h>
>
> #include <mach/hardware.h>
> #include <mach/regs-clock.h>
> @@ -44,6 +45,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
> static inline void __iomem *cpu_boot_reg(int cpu)
> {
> void __iomem *boot_reg;
> + if (!call_firmware_op(cpu_boot_reg, cpu, &boot_reg))
> + return boot_reg;
Nit: new lines between variable declaration and code.
-Olof
^ permalink raw reply
* [RESEND PATCH 2/2] mmc: mmci: Switching off HWFC for SDIO depends on MCLK
From: Ulf Hansson @ 2012-10-10 16:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349885000-22887-1-git-send-email-ulf.hansson@stericsson.com>
From: Ulf Hansson <ulf.hansson@linaro.org>
For writes, HWFC shall be switched off when transfer size <= 8
bytes and when MCLK rate is above 50 MHz. For 50MHz and below
it shall be switched off when transfer size < 8 bytes.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
drivers/mmc/host/mmci.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 877079e..cd0fbee 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -664,12 +664,14 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
datactrl |= MCI_ST_DPSM_SDIOEN;
/*
- * The ST Micro variant for SDIO transfer sizes
- * less then 8 bytes should have clock H/W flow
- * control disabled.
+ * The ST Micro variant for SDIO small write transfers
+ * needs to have clock H/W flow control disabled,
+ * otherwise the transfer will not start. The threshold
+ * depends on the rate of MCLK.
*/
- if ((host->size < 8) &&
- (data->flags & MMC_DATA_WRITE))
+ if (data->flags & MMC_DATA_WRITE &&
+ (host->size < 8 ||
+ (host->size <= 8 && host->mclk > 50000000)))
clk = host->clk_reg & ~variant->clkreg_enable;
else
clk = host->clk_reg | variant->clkreg_enable;
--
1.7.10
^ permalink raw reply related
* [RESEND PATCH 1/2] mmc: mmci: Fix incorrect handling of HW flow control for SDIO
From: Ulf Hansson @ 2012-10-10 16:03 UTC (permalink / raw)
To: linux-arm-kernel
From: Ulf Hansson <ulf.hansson@linaro.org>
For data writes <= 8 bytes, HW flow control was disabled but
never re-enabled when the transfer was completed. This meant
that a following read request would give buffer overrun errors.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
drivers/mmc/host/mmci.c | 38 +++++++++++++++++++++-----------------
1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index edc3e9b..877079e 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -654,9 +654,29 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
/* The ST Micro variants has a special bit to enable SDIO */
if (variant->sdio && host->mmc->card)
- if (mmc_card_sdio(host->mmc->card))
+ if (mmc_card_sdio(host->mmc->card)) {
+ /*
+ * The ST Micro variants has a special bit
+ * to enable SDIO.
+ */
+ u32 clk;
+
datactrl |= MCI_ST_DPSM_SDIOEN;
+ /*
+ * The ST Micro variant for SDIO transfer sizes
+ * less then 8 bytes should have clock H/W flow
+ * control disabled.
+ */
+ if ((host->size < 8) &&
+ (data->flags & MMC_DATA_WRITE))
+ clk = host->clk_reg & ~variant->clkreg_enable;
+ else
+ clk = host->clk_reg | variant->clkreg_enable;
+
+ mmci_write_clkreg(host, clk);
+ }
+
/*
* Attempt to use DMA operation mode, if this
* should fail, fall back to PIO mode
@@ -877,22 +897,6 @@ static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int rem
count = min(remain, maxcnt);
/*
- * The ST Micro variant for SDIO transfer sizes
- * less then 8 bytes should have clock H/W flow
- * control disabled.
- */
- if (variant->sdio &&
- mmc_card_sdio(host->mmc->card)) {
- u32 clk;
- if (count < 8)
- clk = host->clk_reg & ~variant->clkreg_enable;
- else
- clk = host->clk_reg | variant->clkreg_enable;
-
- mmci_write_clkreg(host, clk);
- }
-
- /*
* SDIO especially may want to send something that is
* not divisible by 4 (as opposed to card sectors
* etc), and the FIFO only accept full 32-bit writes.
--
1.7.10
^ permalink raw reply related
* [Xen-devel] [PATCH 5/9] ARM: Xen: fix initial build problems:
From: Stefano Stabellini @ 2012-10-10 16:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349880826.10070.41.camel@zakaz.uk.xensource.com>
On Wed, 10 Oct 2012, Ian Campbell wrote:
> On Wed, 2012-10-10 at 15:47 +0100, Stefano Stabellini wrote:
> > On Wed, 10 Oct 2012, Ian Campbell wrote:
> > > On Tue, 2012-10-09 at 19:21 +0100, Arnd Bergmann wrote:
> > > > On Tuesday 09 October 2012, Stefano Stabellini wrote:
> > > > > > config XEN
> > > > > > bool "Xen guest support on ARM (EXPERIMENTAL)"
> > > > > > depends on EXPERIMENTAL && ARM && OF
> > > > > > + depends on !CPU_V6
> > > > > > help
> > > > > > Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
> > > > >
> > > > > Considering that we rely on the virtualization extensions, this one can
> > > > > be:
> > > > >
> > > > > depends on CPU_V7
> > > > >
> > > > > The rest looks fine. I can submit a second patch to change !CPU_V6 into
> > > > > CPU_V7 later, if you prefer.
> > > >
> > > > CPU_V6 and CPU_V7 are not exclusive, I saw the problem when building a
> > > > combined kernel for both V6 and V7. The code also needs to depend on ARMv7
> > > > with virtualization extensions, but that is a different issue. We don't
> > > > actually have a configuration symbol for that yet, as far as I can tell.
> > >
> > > I don't think the guest kernels (including dom0) need the extensions to
> > > run under Xen, they are only need by Xen itself. The guests should just
> > > see a relatively normal v7 processor.
> > >
> > > Stefano, does that sound right?
> >
> > Keep in mind that we are using HVC to issue hypercalls, and HVC has been
> > introduced with the virtualization extensions, if I am not mistaken.
>
> I think we can ignore that in this context since it is only used by bits
> which are already virtualisation aware -- i.e. you wouldn't want to add
> it to the Kconfig as a dependency for Xen.
Considering that ARM CPU_V* symbols are not mutually exclusive, if Linux
had a CPU_V7_VIRTEXT symbol I don't see why we shouldn't add it to our
list of dependencies. It is more accurate than CPU_V7 after all.
But I don't think that it is necessary to introduce one now only for
Xen, because like you said, we only need HVC and that is only used in
virtualization aware code.
^ permalink raw reply
* [PATCH 5/6] ARM: EXYNOS: Add support for Exynos secure firmware
From: Olof Johansson @ 2012-10-10 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1348496913-25422-6-git-send-email-t.figa@samsung.com>
Hi,
On Mon, Sep 24, 2012 at 04:28:32PM +0200, Tomasz Figa wrote:
> Some Exynos-based boards contain secure firmware and must use firmware
> operations to set up some hardware.
>
> This patch adds firmware operations for Exynos secure firmware and a way
> for board code and device tree to specify that they must be used.
>
> Example of use:
>
> In board code:
>
> ...MACHINE_START(...)
> /* ... */
> .init_early = exynos_firmware_init,
> /* ... */
> MACHINE_END
>
> In device tree:
>
> / {
> /* ... */
>
> firmware {
> compatible = "samsung,secure-firmware";
> };
>
> /* ... */
> };
>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> ---
> .../devicetree/bindings/arm/samsung-boards.txt | 8 ++++
> arch/arm/mach-exynos/Makefile | 1 +
> arch/arm/mach-exynos/common.h | 2 +
> arch/arm/mach-exynos/firmware.c | 54 ++++++++++++++++++++++
> arch/arm/mach-exynos/mach-exynos4-dt.c | 1 +
> 5 files changed, 66 insertions(+)
> create mode 100644 arch/arm/mach-exynos/firmware.c
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung-boards.txt
> index 0bf68be..f447059 100644
> --- a/Documentation/devicetree/bindings/arm/samsung-boards.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung-boards.txt
> @@ -6,3 +6,11 @@ Required root node properties:
> - compatible = should be one or more of the following.
> (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
> (b) "samsung,exynos4210" - for boards based on Exynos4210 SoC.
> +
> +Optional:
> + - firmware node, specifying presence and type of secure firmware, currently
> + supported value of compatible property is "samsung,secure-firmware":
> +
> + firmware {
> + compatible = "samsung,secure-firmware";
> + };
If you require the binding to specify the memory area, then you at least allow
for future work to move to a dynamic mapping without updating the binding and
all device trees. So, please do that even if the code is hardcoded to the
static address today.
For extra credit, make sure that the reg property is matching the static mapping
when you setup your firmware interface on your platform.
[...]
> +static int exynos_cpu_boot_reg(int cpu, void __iomem **ptr)
> +{
> + *ptr = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
> + return 0;
> +}
It would be nice to get a memory map for the SMC area in documentation
somewhere, but that can be done separately later.
-Olof
^ permalink raw reply
* [PATCH 0/3] ARM: dts: EMIF and LPDDR2 device tree data for OMAP5 boards
From: Benoit Cousson @ 2012-10-10 15:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349870716-25511-1-git-send-email-lokeshvutla@ti.com>
You should CC devicetree-discuss at lists.ozlabs.org for any Device tree
patches. This is applicable for the whole series.
On 10/10/2012 02:05 PM, Lokesh Vutla wrote:
> Patch 1:
> Renaming elpida_ecb240abacn.dtsi as lpddr2_data.dtsi
> Patch 2:
> Correcting size of memory defined for omap5
> Patch 3:
> EMIF and LPDDR2 device tree data for OMAP5 boards
>
There is not point to list the patch subject in a cover letter.
You should just introduce the series and ideally give details about the
test like you have done below.
The cover letter should mostly be written like an email.
Benoit
> Testing:
> - Boot tested on omap5-sevm board
> - Built emif as a module
>
> Lokesh Vutla (3):
> ARM: dts: Renaming elpida_ecb240abacn.dts as lpddr2_data.dtsi
> ARM: dts: Correcting size of memory defined for omap5
> ARM: dts: EMIF and LPDDR2 device tree data for OMAP5 boards
>
> arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 ---------------
> arch/arm/boot/dts/lpddr2_data.dtsi | 129 +++++++++++++++++++++++++++++
> arch/arm/boot/dts/omap4-panda.dts | 2 +-
> arch/arm/boot/dts/omap4-sdp.dts | 2 +-
> arch/arm/boot/dts/omap5-evm.dts | 13 ++-
> arch/arm/boot/dts/omap5.dtsi | 18 ++++
> 6 files changed, 161 insertions(+), 70 deletions(-)
> delete mode 100644 arch/arm/boot/dts/elpida_ecb240abacn.dtsi
> create mode 100644 arch/arm/boot/dts/lpddr2_data.dtsi
>
^ permalink raw reply
* [PATCH 7/7] ARM: clps711x: merge files related to EDB7211-board into one
From: Alexander Shiyan @ 2012-10-10 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349883933-8881-1-git-send-email-shc_work@mail.ru>
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/mach-clps711x/Makefile | 2 +-
arch/arm/mach-clps711x/edb7211-arch.c | 66 ------------------------
arch/arm/mach-clps711x/edb7211-mm.c | 82 ------------------------------
arch/arm/mach-clps711x/edb7211.c | 88 +++++++++++++++++++++++++++++++++
4 files changed, 89 insertions(+), 149 deletions(-)
delete mode 100644 arch/arm/mach-clps711x/edb7211-arch.c
delete mode 100644 arch/arm/mach-clps711x/edb7211-mm.c
create mode 100644 arch/arm/mach-clps711x/edb7211.c
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 6da6940..9cf2d1c 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -12,6 +12,6 @@ obj- :=
obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o
obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o
obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
-obj-$(CONFIG_ARCH_EDB7211) += edb7211-arch.o edb7211-mm.o
+obj-$(CONFIG_ARCH_EDB7211) += edb7211.o
obj-$(CONFIG_ARCH_FORTUNET) += fortunet.o
obj-$(CONFIG_ARCH_P720T) += p720t.o
diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c
deleted file mode 100644
index 5fad0b4..0000000
--- a/arch/arm/mach-clps711x/edb7211-arch.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * linux/arch/arm/mach-clps711x/arch-edb7211.c
- *
- * Copyright (C) 2000, 2001 Blue Mug, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/init.h>
-#include <linux/memblock.h>
-#include <linux/types.h>
-#include <linux/string.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-
-extern void edb7211_map_io(void);
-
-/* Reserve screen memory region at the start of main system memory. */
-static void __init edb7211_reserve(void)
-{
- memblock_reserve(PHYS_OFFSET, 0x00020000);
-}
-
-static void __init
-fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
-{
- /*
- * Bank start addresses are not present in the information
- * passed in from the boot loader. We could potentially
- * detect them, but instead we hard-code them.
- *
- * Banks sizes _are_ present in the param block, but we're
- * not using that information yet.
- */
- mi->bank[0].start = 0xc0000000;
- mi->bank[0].size = 8*1024*1024;
- mi->bank[1].start = 0xc1000000;
- mi->bank[1].size = 8*1024*1024;
- mi->nr_banks = 2;
-}
-
-MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
- /* Maintainer: Jon McClintock */
- .atag_offset = 0x20100, /* 0xc0000000 - 0xc001ffff can be video RAM */
- .fixup = fixup_edb7211,
- .map_io = edb7211_map_io,
- .reserve = edb7211_reserve,
- .init_irq = clps711x_init_irq,
- .timer = &clps711x_timer,
- .restart = clps711x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-clps711x/edb7211-mm.c b/arch/arm/mach-clps711x/edb7211-mm.c
deleted file mode 100644
index 054eaa0..0000000
--- a/arch/arm/mach-clps711x/edb7211-mm.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * linux/arch/arm/mach-clps711x/mm.c
- *
- * Extra MM routines for the EDB7211 board
- *
- * Copyright (C) 2000, 2001 Blue Mug, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/bug.h>
-
-#include <mach/hardware.h>
-#include <asm/page.h>
-#include <asm/sizes.h>
-
-#include <asm/mach/map.h>
-
-extern void clps711x_map_io(void);
-
-/*
- * The on-chip registers are given a size of 1MB so that a section can
- * be used to map them; this saves a page table. This is the place to
- * add mappings for ROM, expansion memory, PCMCIA, etc. (if static
- * mappings are chosen for those areas).
- *
- * Here is a physical memory map (to be fleshed out later):
- *
- * Physical Address Size Description
- * ----------------- ----- ---------------------------------
- * c0000000-c001ffff 128KB reserved for video RAM [1]
- * c0020000-c0023fff 16KB parameters (see Documentation/arm/Setup)
- * c0024000-c0027fff 16KB swapper_pg_dir (task 0 page directory)
- * c0028000-... kernel image (TEXTADDR)
- *
- * [1] Unused pages should be given back to the VM; they are not yet.
- * The parameter block should also be released (not sure if this
- * happens).
- */
-static struct map_desc edb7211_io_desc[] __initdata = {
- { /* Memory-mapped extra keyboard row */
- .virtual = IO_ADDRESS(EP7211_PHYS_EXTKBD),
- .pfn = __phys_to_pfn(EP7211_PHYS_EXTKBD),
- .length = SZ_1M,
- .type = MT_DEVICE,
- }, { /* CS8900A Ethernet chip */
- .virtual = IO_ADDRESS(EP7211_PHYS_CS8900A),
- .pfn = __phys_to_pfn(EP7211_PHYS_CS8900A),
- .length = SZ_1M,
- .type = MT_DEVICE,
- }, { /* Flash bank 0 */
- .virtual = IO_ADDRESS(EP7211_PHYS_FLASH1),
- .pfn = __phys_to_pfn(EP7211_PHYS_FLASH1),
- .length = SZ_8M,
- .type = MT_DEVICE,
- }, { /* Flash bank 1 */
- .virtual = IO_ADDRESS(EP7211_PHYS_FLASH2),
- .pfn = __phys_to_pfn(EP7211_PHYS_FLASH2),
- .length = SZ_8M,
- .type = MT_DEVICE,
- }
-};
-
-void __init edb7211_map_io(void)
-{
- clps711x_map_io();
- iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc));
-}
-
diff --git a/arch/arm/mach-clps711x/edb7211.c b/arch/arm/mach-clps711x/edb7211.c
new file mode 100644
index 0000000..88f4690
--- /dev/null
+++ b/arch/arm/mach-clps711x/edb7211.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2000, 2001 Blue Mug, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/memblock.h>
+#include <linux/types.h>
+
+#include <asm/setup.h>
+#include <asm/mach/map.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+
+#include "common.h"
+
+#define VIDEORAM_SIZE SZ_128K
+
+static struct map_desc edb7211_io_desc[] __initdata = {
+ { /* Memory-mapped extra keyboard row */
+ .virtual = IO_ADDRESS(EP7211_PHYS_EXTKBD),
+ .pfn = __phys_to_pfn(EP7211_PHYS_EXTKBD),
+ .length = SZ_1M,
+ .type = MT_DEVICE,
+ }, { /* CS8900A Ethernet chip */
+ .virtual = IO_ADDRESS(EP7211_PHYS_CS8900A),
+ .pfn = __phys_to_pfn(EP7211_PHYS_CS8900A),
+ .length = SZ_1M,
+ .type = MT_DEVICE,
+ }, { /* Flash bank 0 */
+ .virtual = IO_ADDRESS(EP7211_PHYS_FLASH1),
+ .pfn = __phys_to_pfn(EP7211_PHYS_FLASH1),
+ .length = SZ_8M,
+ .type = MT_DEVICE,
+ }, { /* Flash bank 1 */
+ .virtual = IO_ADDRESS(EP7211_PHYS_FLASH2),
+ .pfn = __phys_to_pfn(EP7211_PHYS_FLASH2),
+ .length = SZ_8M,
+ .type = MT_DEVICE,
+ },
+};
+
+void __init edb7211_map_io(void)
+{
+ clps711x_map_io();
+ iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc));
+}
+
+/* Reserve screen memory region at the start of main system memory. */
+static void __init edb7211_reserve(void)
+{
+ memblock_reserve(PHYS_OFFSET, VIDEORAM_SIZE);
+}
+
+static void __init
+fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
+{
+ /*
+ * Bank start addresses are not present in the information
+ * passed in from the boot loader. We could potentially
+ * detect them, but instead we hard-code them.
+ *
+ * Banks sizes _are_ present in the param block, but we're
+ * not using that information yet.
+ */
+ mi->bank[0].start = 0xc0000000;
+ mi->bank[0].size = SZ_8M;
+ mi->bank[1].start = 0xc1000000;
+ mi->bank[1].size = SZ_8M;
+ mi->nr_banks = 2;
+}
+
+MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
+ /* Maintainer: Jon McClintock */
+ .atag_offset = VIDEORAM_SIZE + 0x100,
+ .fixup = fixup_edb7211,
+ .map_io = edb7211_map_io,
+ .reserve = edb7211_reserve,
+ .init_irq = clps711x_init_irq,
+ .timer = &clps711x_timer,
+ .restart = clps711x_restart,
+MACHINE_END
--
1.7.8.6
^ permalink raw reply related
* [PATCH 6/7] ARM: clps711x: merge all CLPS711X-defconfigs into one
From: Alexander Shiyan @ 2012-10-10 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349883933-8881-1-git-send-email-shc_work@mail.ru>
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/configs/clps711x_defconfig | 78 +++++++++++++++++++++++++++++++++++
arch/arm/configs/edb7211_defconfig | 27 ------------
arch/arm/configs/fortunet_defconfig | 28 ------------
3 files changed, 78 insertions(+), 55 deletions(-)
create mode 100644 arch/arm/configs/clps711x_defconfig
delete mode 100644 arch/arm/configs/edb7211_defconfig
delete mode 100644 arch/arm/configs/fortunet_defconfig
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
new file mode 100644
index 0000000..86209d1
--- /dev/null
+++ b/arch/arm/configs/clps711x_defconfig
@@ -0,0 +1,78 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_MSDOS_PARTITION is not set
+CONFIG_ARCH_CLPS711X=y
+CONFIG_ARCH_AUTCPU12=y
+CONFIG_ARCH_CDB89712=y
+CONFIG_ARCH_CLEP7312=y
+CONFIG_ARCH_EDB7211=y
+CONFIG_ARCH_P720T=y
+CONFIG_ARCH_FORTUNET=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+CONFIG_IRDA=y
+CONFIG_IRTTY_SIR=y
+CONFIG_EP7211_DONGLE=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CDB89712=y
+CONFIG_MTD_AUTCPU12=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+CONFIG_CS89x0=y
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_FUJITSU is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_CLPS711X_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+CONFIG_FB_CLPS711X=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_MINIX_FS=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/edb7211_defconfig b/arch/arm/configs/edb7211_defconfig
deleted file mode 100644
index d52ded35..0000000
--- a/arch/arm/configs/edb7211_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_HOTPLUG is not set
-CONFIG_ARCH_CLPS711X=y
-CONFIG_ARCH_EDB7211=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_VT is not set
-CONFIG_SERIAL_CLPS711X=y
-CONFIG_SERIAL_CLPS711X_CONSOLE=y
-CONFIG_EXT2_FS=y
-CONFIG_MINIX_FS=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_MSDOS_PARTITION is not set
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/fortunet_defconfig b/arch/arm/configs/fortunet_defconfig
deleted file mode 100644
index 840fced..0000000
--- a/arch/arm/configs/fortunet_defconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_HOTPLUG is not set
-CONFIG_ARCH_CLPS711X=y
-CONFIG_ARCH_FORTUNET=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_FASTFPE=y
-CONFIG_BINFMT_AOUT=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_CLPS711X=y
-CONFIG_SERIAL_CLPS711X_CONSOLE=y
-CONFIG_EXT2_FS=y
-CONFIG_DEBUG_USER=y
--
1.7.8.6
^ permalink raw reply related
* [PATCH 5/7] ARM: clps711x: make all virtual addresses definition via one macro
From: Alexander Shiyan @ 2012-10-10 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349883933-8881-1-git-send-email-shc_work@mail.ru>
This patch make all virtual addresses definition via one macro.
This modification allows to avoid warning "BUG: mapping for 0x80000000
at 0xff000000 out of vmalloc space".
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/mach-clps711x/autcpu12.c | 15 +-----
arch/arm/mach-clps711x/cdb89712.c | 4 +-
arch/arm/mach-clps711x/common.c | 2 +-
arch/arm/mach-clps711x/edb7211-mm.c | 16 +++---
arch/arm/mach-clps711x/include/mach/autcpu12.h | 14 ++----
arch/arm/mach-clps711x/include/mach/hardware.h | 56 ++++++------------------
arch/arm/mach-clps711x/include/mach/syspld.h | 9 +---
arch/arm/mach-clps711x/p720t.c | 16 ++-----
8 files changed, 38 insertions(+), 94 deletions(-)
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 3287191..214547b 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -39,19 +39,10 @@
#include "common.h"
-/*
- * The on-chip registers are given a size of 1MB so that a section can
- * be used to map them; this saves a page table. This is the place to
- * add mappings for ROM, expansion memory, PCMCIA, etc. (if static
- * mappings are chosen for those areas).
- *
-*/
-
static struct map_desc autcpu12_io_desc[] __initdata = {
- /* memory-mapped extra io and CS8900A Ethernet chip */
- /* ethernet chip */
- {
- .virtual = AUTCPU12_VIRT_CS8900A,
+ /* Memory-mapped extra io and CS8900A Ethernet chip */
+ {
+ .virtual = IO_ADDRESS(AUTCPU12_PHYS_CS8900A),
.pfn = __phys_to_pfn(AUTCPU12_PHYS_CS8900A),
.length = SZ_1M,
.type = MT_DEVICE
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
index c314f49..d90d25c 100644
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ b/arch/arm/mach-clps711x/cdb89712.c
@@ -40,8 +40,8 @@
*/
static struct map_desc cdb89712_io_desc[] __initdata = {
{
- .virtual = ETHER_BASE,
- .pfn =__phys_to_pfn(ETHER_START),
+ .virtual = IO_ADDRESS(ETHER_PHYS_BASE),
+ .pfn = __phys_to_pfn(ETHER_PHYS_BASE),
.length = ETHER_SIZE,
.type = MT_DEVICE
}
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 38a18ee..0918591 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -45,7 +45,7 @@ static struct map_desc clps711x_io_desc[] __initdata = {
{
.virtual = (unsigned long)CLPS711X_VIRT_BASE,
.pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
- .length = SZ_1M,
+ .length = SZ_64K,
.type = MT_DEVICE
}
};
diff --git a/arch/arm/mach-clps711x/edb7211-mm.c b/arch/arm/mach-clps711x/edb7211-mm.c
index 4372f06..054eaa0 100644
--- a/arch/arm/mach-clps711x/edb7211-mm.c
+++ b/arch/arm/mach-clps711x/edb7211-mm.c
@@ -51,23 +51,23 @@ extern void clps711x_map_io(void);
* happens).
*/
static struct map_desc edb7211_io_desc[] __initdata = {
- { /* memory-mapped extra keyboard row */
- .virtual = EP7211_VIRT_EXTKBD,
+ { /* Memory-mapped extra keyboard row */
+ .virtual = IO_ADDRESS(EP7211_PHYS_EXTKBD),
.pfn = __phys_to_pfn(EP7211_PHYS_EXTKBD),
.length = SZ_1M,
.type = MT_DEVICE,
- }, { /* and CS8900A Ethernet chip */
- .virtual = EP7211_VIRT_CS8900A,
+ }, { /* CS8900A Ethernet chip */
+ .virtual = IO_ADDRESS(EP7211_PHYS_CS8900A),
.pfn = __phys_to_pfn(EP7211_PHYS_CS8900A),
.length = SZ_1M,
.type = MT_DEVICE,
- }, { /* flash banks */
- .virtual = EP7211_VIRT_FLASH1,
+ }, { /* Flash bank 0 */
+ .virtual = IO_ADDRESS(EP7211_PHYS_FLASH1),
.pfn = __phys_to_pfn(EP7211_PHYS_FLASH1),
.length = SZ_8M,
.type = MT_DEVICE,
- }, {
- .virtual = EP7211_VIRT_FLASH2,
+ }, { /* Flash bank 1 */
+ .virtual = IO_ADDRESS(EP7211_PHYS_FLASH2),
.pfn = __phys_to_pfn(EP7211_PHYS_FLASH2),
.length = SZ_8M,
.type = MT_DEVICE,
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
index 1588a36..f95ce6f 100644
--- a/arch/arm/mach-clps711x/include/mach/autcpu12.h
+++ b/arch/arm/mach-clps711x/include/mach/autcpu12.h
@@ -20,12 +20,8 @@
#ifndef __ASM_ARCH_AUTCPU12_H
#define __ASM_ARCH_AUTCPU12_H
-/*
- * The CS8900A ethernet chip has its I/O registers wired to chip select 2
- * (nCS2). This is the mapping for it.
- */
-#define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE /* physical */
-#define AUTCPU12_VIRT_CS8900A (0xfe000000) /* virtual */
+/* The CS8900A ethernet chip has its I/O registers wired to chip select 2 */
+#define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE
/*
* The flash bank is wired to chip select 0
@@ -34,11 +30,9 @@
/* offset for device specific information structure */
#define AUTCPU12_LCDINFO_OFFS (0x00010000)
-/*
-* Videomemory is the internal SRAM (CS 6)
-*/
+
+/* Videomemory in the internal SRAM (CS 6) */
#define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE
-#define AUTCPU12_VIRT_VIDEO (0xfd000000)
/*
* All special IO's are tied to CS1
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 8497775..0a3df25 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -24,7 +24,10 @@
#include <mach/clps711x.h>
-#define CLPS711X_VIRT_BASE IOMEM(0xff000000)
+#define IO_ADDRESS(x) (0xdc000000 + (((x) & 0x03ffffff) | \
+ (((x) >> 2) & 0x3c000000)))
+
+#define CLPS711X_VIRT_BASE IOMEM(IO_ADDRESS(CLPS711X_PHYS_BASE))
#ifndef __ASSEMBLY__
#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off))
@@ -61,58 +64,25 @@
#define CS7_PHYS_BASE (0x00000000)
#endif
-#define SYSPLD_VIRT_BASE 0xfe000000
-#define SYSPLD_BASE SYSPLD_VIRT_BASE
-
#if defined (CONFIG_ARCH_CDB89712)
-#define ETHER_START 0x20000000
-#define ETHER_SIZE 0x1000
-#define ETHER_BASE 0xfe000000
+#define ETHER_PHYS_BASE CS2_PHYS_BASE
+#define ETHER_SIZE 0x1000
#endif
#if defined (CONFIG_ARCH_EDB7211)
-/*
- * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3)
- * and repeat across it. This is the mapping for it.
- *
- * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This
- * was cause for much consternation and headscratching. This should probably
- * be made a compile/run time kernel option.
- */
-#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */
-
-#define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */
-
-
-/*
- * The CS8900A ethernet chip has its I/O registers wired to chip select 2
- * (nCS2). This is the mapping for it.
- *
- * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This
- * was cause for much consternation and headscratching. This should probably
- * be made a compile/run time kernel option.
- */
-#define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */
-
-#define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */
+/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
+#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE
+/* The CS8900A ethernet chip has its I/O registers wired to chip select 2 */
+#define EP7211_PHYS_CS8900A CS2_PHYS_BASE
-/*
- * The two flash banks are wired to chip selects 0 and 1. This is the mapping
- * for them.
- *
- * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
- * in jumpered boot mode.
- */
-#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
-#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
-
-#define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */
-#define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */
+/* The two flash banks are wired to chip selects 0 and 1 */
+#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE
+#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE
#endif /* CONFIG_ARCH_EDB7211 */
diff --git a/arch/arm/mach-clps711x/include/mach/syspld.h b/arch/arm/mach-clps711x/include/mach/syspld.h
index f7f4c12..9a43315 100644
--- a/arch/arm/mach-clps711x/include/mach/syspld.h
+++ b/arch/arm/mach-clps711x/include/mach/syspld.h
@@ -23,14 +23,9 @@
#define __ASM_ARCH_SYSPLD_H
#define SYSPLD_PHYS_BASE (0x10000000)
+#define SYSPLD_VIRT_BASE IO_ADDRESS(SYSPLD_PHYS_BASE)
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-#define SYSPLD_REG(type,off) (*(volatile type *)(SYSPLD_BASE + off))
-#else
-#define SYSPLD_REG(type,off) (off)
-#endif
+#define SYSPLD_REG(type, off) (*(volatile type *)(SYSPLD_VIRT_BASE + (off)))
#define PLD_INT SYSPLD_REG(u32, 0x000000)
#define PLD_INT_PENIRQ (1 << 5)
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index 7680bea..dd89950 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -39,22 +39,16 @@
#include "common.h"
/*
- * Map the P720T system PLD. It occupies two address spaces:
- * SYSPLD_PHYS_BASE and SYSPLD_PHYS_BASE + 0x00400000
- * We map both here.
+ * Map the P720T system PLD. It occupies two address spaces:
+ * 0x10000000 and 0x10400000. We map both regions as one.
*/
static struct map_desc p720t_io_desc[] __initdata = {
{
.virtual = SYSPLD_VIRT_BASE,
.pfn = __phys_to_pfn(SYSPLD_PHYS_BASE),
- .length = SZ_1M,
- .type = MT_DEVICE
- }, {
- .virtual = 0xfe400000,
- .pfn = __phys_to_pfn(0x10400000),
- .length = SZ_1M,
- .type = MT_DEVICE
- }
+ .length = SZ_8M,
+ .type = MT_DEVICE,
+ },
};
static void __init
--
1.7.8.6
^ permalink raw reply related
* [PATCH 4/7] ARM: clps711x: added missing definitions
From: Alexander Shiyan @ 2012-10-10 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349883933-8881-1-git-send-email-shc_work@mail.ru>
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/mach-clps711x/include/mach/clps711x.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index c82e21c..aee352c 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -257,6 +257,9 @@
#define MEMCFG_BUS_WIDTH_16 (0)
#define MEMCFG_BUS_WIDTH_8 (3)
+#define MEMCFG_SQAEN (1 << 6)
+#define MEMCFG_CLKENB (1 << 7)
+
#define MEMCFG_WAITSTATE_8_3 (0 << 2)
#define MEMCFG_WAITSTATE_7_3 (1 << 2)
#define MEMCFG_WAITSTATE_6_3 (2 << 2)
--
1.7.8.6
^ permalink raw reply related
* [PATCH 3/7] ARM: clps711x: rework IRQ sybsustem initialization
From: Alexander Shiyan @ 2012-10-10 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349883933-8881-1-git-send-email-shc_work@mail.ru>
Reworked IRQ subsystem to be able to use some interrupts
with "End of interrupt" handler.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/mach-clps711x/common.c | 91 +++++++++++++++++++---------
arch/arm/mach-clps711x/include/mach/irqs.h | 4 -
2 files changed, 62 insertions(+), 33 deletions(-)
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 218684f..38a18ee 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -66,6 +66,10 @@ static void int1_mask(struct irq_data *d)
static void int1_ack(struct irq_data *d)
{
+}
+
+static void int1_eoi(struct irq_data *d)
+{
switch (d->irq) {
case IRQ_CSINT: clps_writel(0, COEOI); break;
case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
@@ -86,7 +90,9 @@ static void int1_unmask(struct irq_data *d)
}
static struct irq_chip int1_chip = {
+ .name = "Interrupt Vector 1 ",
.irq_ack = int1_ack,
+ .irq_eoi = int1_eoi,
.irq_mask = int1_mask,
.irq_unmask = int1_unmask,
};
@@ -102,6 +108,10 @@ static void int2_mask(struct irq_data *d)
static void int2_ack(struct irq_data *d)
{
+}
+
+static void int2_eoi(struct irq_data *d)
+{
switch (d->irq) {
case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
}
@@ -117,45 +127,68 @@ static void int2_unmask(struct irq_data *d)
}
static struct irq_chip int2_chip = {
+ .name = "Interrupt Vector 2 ",
.irq_ack = int2_ack,
+ .irq_eoi = int2_eoi,
.irq_mask = int2_mask,
.irq_unmask = int2_unmask,
};
+struct clps711x_irqdesc {
+ int nr;
+ struct irq_chip *chip;
+ irq_flow_handler_t handle;
+};
+
+static struct clps711x_irqdesc clps711x_irqdescs[] __initdata = {
+ { IRQ_CSINT, &int1_chip, handle_fasteoi_irq, },
+ { IRQ_EINT1, &int1_chip, handle_level_irq, },
+ { IRQ_EINT2, &int1_chip, handle_level_irq, },
+ { IRQ_EINT3, &int1_chip, handle_level_irq, },
+ { IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, },
+ { IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, },
+ { IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, },
+ { IRQ_TINT, &int1_chip, handle_fasteoi_irq, },
+ { IRQ_UTXINT1, &int1_chip, handle_level_irq, },
+ { IRQ_URXINT1, &int1_chip, handle_level_irq, },
+ { IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, },
+ { IRQ_SSEOTI, &int1_chip, handle_level_irq, },
+ { IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, },
+ { IRQ_SS2RX, &int2_chip, handle_level_irq, },
+ { IRQ_SS2TX, &int2_chip, handle_level_irq, },
+ { IRQ_UTXINT2, &int2_chip, handle_level_irq, },
+ { IRQ_URXINT2, &int2_chip, handle_level_irq, },
+};
+
void __init clps711x_init_irq(void)
{
unsigned int i;
- for (i = 0; i < NR_IRQS; i++) {
- if (INT1_IRQS & (1 << i)) {
- irq_set_chip_and_handler(i, &int1_chip,
- handle_level_irq);
- set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
- }
- if (INT2_IRQS & (1 << i)) {
- irq_set_chip_and_handler(i, &int2_chip,
- handle_level_irq);
- set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
- }
+ /* Disable interrupts */
+ clps_writel(0, INTMR1);
+ clps_writel(0, INTMR2);
+ clps_writel(0, INTMR3);
+
+ /* Clear down any pending interrupts */
+ clps_writel(0, BLEOI);
+ clps_writel(0, MCEOI);
+ clps_writel(0, COEOI);
+ clps_writel(0, TC1EOI);
+ clps_writel(0, TC2EOI);
+ clps_writel(0, RTCEOI);
+ clps_writel(0, TEOI);
+ clps_writel(0, UMSEOI);
+ clps_writel(0, KBDEOI);
+ clps_writel(0, SRXEOF);
+ clps_writel(0xffffffff, DAISR);
+
+ for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) {
+ irq_set_chip_and_handler(clps711x_irqdescs[i].nr,
+ clps711x_irqdescs[i].chip,
+ clps711x_irqdescs[i].handle);
+ set_irq_flags(clps711x_irqdescs[i].nr,
+ IRQF_VALID | IRQF_PROBE);
}
-
- /*
- * Disable interrupts
- */
- clps_writel(0, INTMR1);
- clps_writel(0, INTMR2);
-
- /*
- * Clear down any pending interrupts
- */
- clps_writel(0, COEOI);
- clps_writel(0, TC1EOI);
- clps_writel(0, TC2EOI);
- clps_writel(0, RTCEOI);
- clps_writel(0, TEOI);
- clps_writel(0, UMSEOI);
- clps_writel(0, SYNCIO);
- clps_writel(0, KBDEOI);
}
static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
diff --git a/arch/arm/mach-clps711x/include/mach/irqs.h b/arch/arm/mach-clps711x/include/mach/irqs.h
index 14d215f..1ea56db 100644
--- a/arch/arm/mach-clps711x/include/mach/irqs.h
+++ b/arch/arm/mach-clps711x/include/mach/irqs.h
@@ -34,8 +34,6 @@
#define IRQ_UMSINT 14
#define IRQ_SSEOTI 15
-#define INT1_IRQS (0x0000fff0)
-
/*
* Interrupts from INTSR2
*/
@@ -45,6 +43,4 @@
#define IRQ_UTXINT2 (16+12) /* bit 12 */
#define IRQ_URXINT2 (16+13) /* bit 13 */
-#define INT2_IRQS (0x30070000)
-
#define NR_IRQS 30
--
1.7.8.6
^ permalink raw reply related
* [PATCH 2/7] ARM: clps711x: p720t: remove missing #include
From: Alexander Shiyan @ 2012-10-10 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349883933-8881-1-git-send-email-shc_work@mail.ru>
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/mach-clps711x/p720t.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index b752b58..7680bea 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -36,8 +36,6 @@
#include <asm/mach/map.h>
#include <mach/syspld.h>
-#include <asm/hardware/clps7111.h>
-
#include "common.h"
/*
--
1.7.8.6
^ permalink raw reply related
* [PATCH 1/7] ARM: clps711x: convert to clockevents
From: Alexander Shiyan @ 2012-10-10 15:45 UTC (permalink / raw)
To: linux-arm-kernel
This patch converts CLPS711X-platform to use modern clockevent API.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-clps711x/common.c | 38 +++++++++++++++++---------------------
2 files changed, 18 insertions(+), 22 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3ebe71c..1d43127 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -354,9 +354,9 @@ config ARCH_BCM2835
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select CPU_ARM720T
- select ARCH_USES_GETTIMEOFFSET
select COMMON_CLK
select CLKDEV_LOOKUP
+ select GENERIC_CLOCKEVENTS
select NEED_MACH_MEMORY_H
help
Support for Cirrus Logic 711x/721x/731x based boards.
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 509243d..218684f 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -21,13 +21,14 @@
*/
#include <linux/io.h>
#include <linux/init.h>
+#include <linux/sizes.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
+#include <linux/clockchips.h>
#include <linux/clk-provider.h>
-#include <asm/sizes.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/system_misc.h>
@@ -36,7 +37,6 @@
static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
*clk_tint, *clk_spi;
-static unsigned long latch;
/*
* This maps the generic CLPS711x registers
@@ -158,32 +158,29 @@ void __init clps711x_init_irq(void)
clps_writel(0, KBDEOI);
}
-/*
- * gettimeoffset() returns time since last timer tick, in usecs.
- *
- * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
- * 'tick' is usecs per jiffy.
- */
-static unsigned long clps711x_gettimeoffset(void)
+static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
{
- unsigned long hwticks;
- hwticks = latch - (clps_readl(TC2D) & 0xffff);
- return (hwticks * (tick_nsec / 1000)) / latch;
}
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t p720t_timer_interrupt(int irq, void *dev_id)
+static struct clock_event_device clockevent_clps711x = {
+ .name = "CLPS711x Clockevents",
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_PERIODIC,
+ .set_mode = clps711x_clockevent_set_mode,
+};
+
+static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
{
- timer_tick();
+ clockevent_clps711x.event_handler(&clockevent_clps711x);
+
return IRQ_HANDLED;
}
static struct irqaction clps711x_timer_irq = {
.name = "CLPS711x Timer Tick",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = p720t_timer_interrupt,
+ .handler = clps711x_timer_interrupt,
};
static void add_fixed_clk(struct clk *clk, const char *name, int rate)
@@ -244,20 +241,19 @@ static void __init clps711x_timer_init(void)
pr_info("CPU frequency set at %i Hz.\n", cpu);
- latch = (timh + HZ / 2) / HZ;
+ clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
tmp = clps_readl(SYSCON1);
tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
clps_writel(tmp, SYSCON1);
- clps_writel(latch - 1, TC2D);
+ clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff);
setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
}
struct sys_timer clps711x_timer = {
.init = clps711x_timer_init,
- .offset = clps711x_gettimeoffset,
};
void clps711x_restart(char mode, const char *cmd)
--
1.7.8.6
^ permalink raw reply related
* [PATCH 2/2] mmc: mmci: Switching off HWFC for SDIO depends on MCLK
From: Ulf Hansson @ 2012-10-10 15:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349883825-22517-1-git-send-email-ulf.hansson@stericsson.com>
For writes, HWFC shall be switched off when transfer size <= 8
bytes and when MCLK rate is above 50 MHz. For 50MHz and below
it shall be switched off when transfer size < 8 bytes.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
drivers/mmc/host/mmci.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 877079e..cd0fbee 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -664,12 +664,14 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
datactrl |= MCI_ST_DPSM_SDIOEN;
/*
- * The ST Micro variant for SDIO transfer sizes
- * less then 8 bytes should have clock H/W flow
- * control disabled.
+ * The ST Micro variant for SDIO small write transfers
+ * needs to have clock H/W flow control disabled,
+ * otherwise the transfer will not start. The threshold
+ * depends on the rate of MCLK.
*/
- if ((host->size < 8) &&
- (data->flags & MMC_DATA_WRITE))
+ if (data->flags & MMC_DATA_WRITE &&
+ (host->size < 8 ||
+ (host->size <= 8 && host->mclk > 50000000)))
clk = host->clk_reg & ~variant->clkreg_enable;
else
clk = host->clk_reg | variant->clkreg_enable;
--
1.7.10
^ permalink raw reply related
* [PATCH 1/2] mmc: mmci: Fix incorrect handling of HW flow control for SDIO
From: Ulf Hansson @ 2012-10-10 15:43 UTC (permalink / raw)
To: linux-arm-kernel
From: Ulf Hansson <(address hidden)>
For data writes <= 8 bytes, HW flow control was disabled but
never re-enabled when the transfer was completed. This meant
that a following read request would give buffer overrun errors.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
drivers/mmc/host/mmci.c | 38 +++++++++++++++++++++-----------------
1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index edc3e9b..877079e 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -654,9 +654,29 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
/* The ST Micro variants has a special bit to enable SDIO */
if (variant->sdio && host->mmc->card)
- if (mmc_card_sdio(host->mmc->card))
+ if (mmc_card_sdio(host->mmc->card)) {
+ /*
+ * The ST Micro variants has a special bit
+ * to enable SDIO.
+ */
+ u32 clk;
+
datactrl |= MCI_ST_DPSM_SDIOEN;
+ /*
+ * The ST Micro variant for SDIO transfer sizes
+ * less then 8 bytes should have clock H/W flow
+ * control disabled.
+ */
+ if ((host->size < 8) &&
+ (data->flags & MMC_DATA_WRITE))
+ clk = host->clk_reg & ~variant->clkreg_enable;
+ else
+ clk = host->clk_reg | variant->clkreg_enable;
+
+ mmci_write_clkreg(host, clk);
+ }
+
/*
* Attempt to use DMA operation mode, if this
* should fail, fall back to PIO mode
@@ -877,22 +897,6 @@ static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int rem
count = min(remain, maxcnt);
/*
- * The ST Micro variant for SDIO transfer sizes
- * less then 8 bytes should have clock H/W flow
- * control disabled.
- */
- if (variant->sdio &&
- mmc_card_sdio(host->mmc->card)) {
- u32 clk;
- if (count < 8)
- clk = host->clk_reg & ~variant->clkreg_enable;
- else
- clk = host->clk_reg | variant->clkreg_enable;
-
- mmci_write_clkreg(host, clk);
- }
-
- /*
* SDIO especially may want to send something that is
* not divisible by 4 (as opposed to card sectors
* etc), and the FIFO only accept full 32-bit writes.
--
1.7.10
^ permalink raw reply related
* [RFC] Samsung SoC camera DT bindings
From: Sylwester Nawrocki @ 2012-10-10 15:42 UTC (permalink / raw)
To: linux-arm-kernel
Hi All,
The following is a brief description of Samsung SoC architecture from the
camera point of view and a corresponding device tree structure. It is based
on the media devices DT bindings design from Guennadi [1]. I incorporated
some changes proposed during reviews (e.g. s/link/endpoint). It seems the
common media bindings are more or less settled now and the discussions are
mostly about implementation of the common parsers and core code.
This RFC is just about an example of the media bindings for fairly complex
SoC architecture. I would be happy to get any feedback on that, while I'm
about to start adding support for this at the driver.
In Samsung SoCs there are multiple capture interfaces that can be attached
to each physical camera port, either parallel video bus or serial MIPI CSI-2.
c02 +-------------+
c01 | | | | |
------o----->+ CAM_IF.0 |--> memory
+---------------------+ +--------+ | | | | |
| sensor A (MIPI CSI2)| | CSI-RX | | | | +-------------+
+---------------------+>-+--------+->-|---o- |
| | o------<----------- from ISP
+----------------------+ | | |
| sensor B (parallel) | | | |
+----------------------+------->------o- | |
| | | +-------------+
c11 | | c12 | |
----------o->+ CAM_IF.1 |--> memory
| | | | |
| | | +-------------+
. . .
| | | +-------------+
c21 | |c22| | | to ISP
--o--------->+ CAM_IF_L.0 |--> (SoC
| | | | | internal
+-------------+ data bus)
As in the above figure, each external sensor can be connected to any of the
CAM_IFs at run-time. It's also possible to connect two CAM_IFs to a single
sensor in parallel. CSI-RX devices and parallel video bus port are connected
to CAM_IF.N devices internally through some sort of crossbar interconnect.
On some SoCs there is also an ISP, which can use one of the two limited
capture interfaces (CAM_IF_L.0) as front-ends and return video data to
a CAM_IF.N that acts as a DMA engine. Following configurations are possible:
sensor A -> mipi-csi2 slave (CSI-RX) -> CAM_IF.? -> memory
sensor B -> CAM_IF.? -> memory
sensor A -> mipi-csi2 slave (CSI-RX) -> CAM_IF_LITE.? -> memory
sensor B -> CAM_IF_LITE.? -> memory
sensor B -> CAM_IF_LITE.? -> ISP -> CAM_IF.? -> memory
sensor A -> mipi-csi2 slave (CSI-RX) -> CAM_IF_LITE.? -> ISP -> CAM_IF.?
-> memory
Describing all these possible links by our port/endpoint convention would
result in unnecessarily complex structure. These SoC's internal data routing
could well be coded in the driver, depending on the available hardware
entities and based only on the compatible property.
On the other hand it would be useful to specify certain initial active link
configurations, so the device is in known and valid state after the driver
has initialized. I chose to specify only those default internal SoC links
in DT, leaving sorting out all possible routes for the driver.
The below device tree structure contains two camera sensors controlled over
an I2C bus, where m5mols is connected to the SoC through MIPI CSI-2 bus
and s5k5bafx is on a parallel video bus. There are following default links
specified there:
1) m5mols -> csis0 -> fimc0,
2) s5k4bafx -> fimc1.
Any comments and suggestions are welcome.
/*===========================================================================*/
/* Aliases for assigning platform entity indexes at the drivers */
aliases {
csis0 = &csis_0;
csis1 = &csis_1;
fimc0 = &fimc_0;
fimc1 = &fimc_1;
fimc2 = &fimc_2;
fimc3 = &fimc_3;
fimc_lite0 = &fimc_lite_0;
fimc_lite1 = &fimc_lite_1;
};
i2c0: i2c at 0xfff20000 {
...
/* Parallel bus IF sensor */
s5k5bafx: sensor at 0x21 {
compatible = "samsung,s5k5bafx";
reg = <0x21>;
vddio-supply = <®ulator1>;
vddcore-supply = <®ulator2>;
clock-frequency = <20000000>;
clocks = <&mclk0>;
clock-names = "mclk";
port {
s5k5bafx_1: endpoint {
remote-endpoint = <&cam_a_endpoint>;
bus-width = <8>;
hsync-active = <0>;
hsync-active = <1>;
pclk-sample = <1>;
};
};
};
/* MIPI CSI-2 bus IF sensor */
m5mols: sensor at 0x1a {
compatible = "samsung,m5mols";
reg = <0x1a>;
vddio-supply = <®ulator1>;
vddcore-supply = <®ulator2>;
clock-frequency = <30000000>; /* shared clock with ov772x_1 */
clocks = <&mclk0>;
clock-names = "mclk"; /* assuming this is the name in the datasheet */
port {
m5mols_1: endpoint {
data-lanes = <1>, <2>, <3>, <4>;
remote-endpoint = <&csis0_cam_endpoint>;
};
};
};
};
/* An aggregate node to gather properties common and shared among
all the SoC camera devices. */
camera {
compatible = "samsung,fimc";
/* These two clocks are common for all fimc and fimc_lite devices */
mclk0: sclk_cam at 0 {
#clock-cells = <0>;
/* the sclk_cam_0 phandle comes from clock bindings not shown here */
clocks = <&sclk_cam_0>;
clock-output-names = "fimc_sclk_cam0";
};
mclk1: sclk_cam at 1 {
#clock-cells = <0>;
clocks = <&sclk_cam_1>;
clock-output-names = "fimc_sclk_cam1";
};
/* parallel video port A */
parallel_camera_port at 1 {
cam_port_a: port at 1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>; /* reg also determines FIMC input type: port = { A, B, C, D }
<=> reg = { 1, 2 , 3, 4 }. A, B are parallel, C is serial
from CSIS, D is internal FIFO link from an internal SoC
processing block. */
cam_a_endpoint: endpoint {
remote-endpoint = <&s5k5bafx_1>; /* remote endpoint phandle */
bus-width = <8>; /* used data lines */
hsync-active = <1>; /* active high */
vsync-active = <0>; /* active low */
pclk-sample = <1>; /* rising */
};
};
/* SoC internal port for the physical parallel camera port A */
port at 0 {
reg = <0>; /* 0 always indicates SoC internal port */
cam_a_soc_endpoint: endpoint {
/* There is more possible remote endpoints, we just specify
the one default that will be seen active. This remote endpoint
can be switched over at run-time. The list of endpoints possible
to select is hard coded in the driver, depending on the
compatible property.
*/
remote-endpoint = <&fimc0_endpoint>;
};
};
};
/* The camera ports (pinmux) configuration, these are common for all
fimc and fimc_lite devices */
pinctrl-names = "default";
pinctrl-0 = <&camera_port_a &camera_port_c>;
/* MIPI-CSIS.0 */
csis0: csis at 11880000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11880000 0x1000>;
interrupts = <0 78 0>;
cam_port_c: port at 2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>; /* (MIPI CSI-2) LVDS port C */
csis0_cam_endpoint: endpoint {
remote-endpoint = <&m5mols_1>;
data-lanes = <1>, <2>, <3>, <4>;
};
};
/* SoC internal port for the physical parallel camera port A */
port at 0 {
reg = <0>;
csis0_endpoint: endpoint {
/* There is more possible remote endpoints, we just
specify the one default that will be seen active.
This remote endpoint can be switched over at run-time.
The list of endpoints possible to select is hard coded
in the driver, depending on the compatible property.
*/
remote-endpoint = <&fimc1_endpoint>;
};
};
};
/* MIPI-CSIS.1 */
csis1: csis at 11890000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11890000 0x1000>;
interrupts = <0 79 0>;
};
/* FIMC.0 (CAM_IF.0) */
fimc0: fimc at 11800000 {
compatible = "samsung,exynos4x12-fimc";
reg = <0x11800000 0x1000>;
interrupts = <0 84 0>;
port {
/* Link to the physical parallel camera port A */
fimc0_endpoint: endpoint {
remote-endpoint = <&cam_a_soc_endpoint>;
};
};
};
fimc1: fimc at 11900000 {
compatible = "samsung,exynos4x12-fimc";
reg = <0x11900000 0x1000>;
interrupts = <0 85 0>;
port {
/* Link to the MIPI CSI-2 front-end (csis0) */
fimc1_endpoint: endpoint {
remote-endpoint = <&csis0_cam_endpoint>;
};
};
};
fimc2: fimc at 11a00000 {
compatible = "samsung,exynos4x12-fimc";
reg = <0x11a00000 0x1000>;
interrupts = <0 86 0>;
};
fimc3: fimc at 11b00000 {
compatible = "samsung,exynos4x12-fimc";
reg = <0x11b00000 0x1000>;
interrupts = <0 87 0>;
};
/* FIMC-LITE.0 (CAM_IF_LITE.0) */
fimc_lite0: fimc_lite at 12000000 {
compatible = "samsung,exynos4x12-fimc";
reg = <0x12000000 0x1000>;
interrupts = <0 90 0>;
};
fimc_lite1: fimc_lite at 12100000 {
compatible = "samsung,exynos4x12-fimc";
reg = <0x12100000 0x1000>;
interrupts = <0 91 0>;
};
};
/*===========================================================================*/
---
Regards,
Sylwester
[1] http://www.spinics.net/lists/linux-media/msg54023.html
^ permalink raw reply
* [PATCH v2 0/6] ARM: EXYNOS: Add secure firmware support
From: Kyungmin Park @ 2012-10-10 15:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1647638.5fBfDOzz0u@amdc1227>
Hi Arnd or Olof,
Can you pick up for v3.7?
To Tomasz,
Can you rebase it on the latest arm-soc tree?
Thank you,
Kyungmin Park
On Tue, Oct 2, 2012 at 6:13 PM, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi,
>
> On Monday 24 of September 2012 16:28:27 Tomasz Figa wrote:
>> Some Exynos-based boards are running with secure firmware running in
>> TrustZone secure world, which changes the way some things have to be
>> initialized.
>>
>> This series adds support for specifying firmware operations, implements
>> some firmware operations for Exynos secure firmware and adds a method of
>> enabling secure firmware operations on Exynos-based boards through board
>> file and device tree.
>>
>> Changes since v1
>> http://thread.gmane.org/gmane.linux.kernel.samsung-soc/12583/focus=12820
>> - Changed return types of all operations to int
>> - Defined all operations to return 0 on success, -ENOSYS when not
>> implemented or appropriate error code on error
>>
>> Tomasz Figa (6):
>> ARM: Add interface for registering and calling firmware-specific
>> operations
>> ARM: EXYNOS: Add support for secure monitor calls
>> ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
>> ARM: EXYNOS: Add IO mapping for non-secure SYSRAM.
>> ARM: EXYNOS: Add support for Exynos secure firmware
>> ARM: EXYNOS: Add secure firmware support to secondary CPU bring-up
>>
>> .../devicetree/bindings/arm/samsung-boards.txt | 8 ++++
>> arch/arm/common/Makefile | 2 +
>> arch/arm/common/firmware.c | 18 ++++++++
>> arch/arm/include/asm/firmware.h | 31 +++++++++++++
>> arch/arm/mach-exynos/Makefile | 6 +++
>> arch/arm/mach-exynos/common.c | 34 ++++++++++++++
>> arch/arm/mach-exynos/common.h | 2 +
>> arch/arm/mach-exynos/exynos-smc.S | 22 +++++++++
>> arch/arm/mach-exynos/firmware.c | 54
>> ++++++++++++++++++++++ arch/arm/mach-exynos/include/mach/map.h
>> | 3 ++
>> arch/arm/mach-exynos/mach-exynos4-dt.c | 1 +
>> arch/arm/mach-exynos/platsmp.c | 36 ++++++++++++---
>> arch/arm/mach-exynos/smc.h | 31 +++++++++++++
>> arch/arm/plat-samsung/include/plat/map-s5p.h | 1 +
>> 14 files changed, 243 insertions(+), 6 deletions(-)
>> create mode 100644 arch/arm/common/firmware.c
>> create mode 100644 arch/arm/include/asm/firmware.h
>> create mode 100644 arch/arm/mach-exynos/exynos-smc.S
>> create mode 100644 arch/arm/mach-exynos/firmware.c
>> create mode 100644 arch/arm/mach-exynos/smc.h
>
> Any comments, nitpicks or acks on this patchset?
>
> Best regards,
> --
> Tomasz Figa
> Samsung Poland R&D Center
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 00/16] pinctrl: samsung: Usability and extensibiltiy improvements
From: Tomasz Figa @ 2012-10-10 15:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdbUmM2=vhjhCq_qN2v=8RUDeWV4b8A8oXXPE4e8Z9C7zg@mail.gmail.com>
On Wednesday 10 of October 2012 09:46:28 Linus Walleij wrote:
> On Mon, Oct 8, 2012 at 10:39 AM, Tomasz Figa <t.figa@samsung.com> wrote:
> > This patch series is a work on improving usability and extensibiltiy of
> > the>
> > pinctrl-samsung driver. It consists of three main parts:
> > - moving SoC-specific data to device tree
> > - converting the driver to use one GPIO chip and one IRQ domain per
> > pin bank - introducing generic wake-up interrupt capability
> > description
>
> So can you prepare a patch series which does all but the first
> bullet to begin with, and a SoC-and register offset patch
> on top of that as a separate series, because it is controversial?
>
> I don't like that these two things are mingled together like this
> in an all-or-nothing manner.
>
> So I'm OK with a patch series for bulle (2) and (3) but not (1).
>
> And I'd like to have Thomas A:s ACK on the series too.
>
I have managed to rework the changes to drop (1). I will send next version
of patches tomorrow. It would be nice to have them merged for 3.7, as they
are rather important for further work.
Moving data from the driver to device tree is not as important, so it might
be discussed later.
Best regards,
--
Tomasz Figa
Samsung Poland R&D Center
^ permalink raw reply
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