* [PATCH 4/5] net: cpsw: Add parent<->child relation support between cpsw and mdio
From: Richard Cochran @ 2012-10-15 19:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1350327320.git.richardcochran@gmail.com>
From: Vaibhav Hiremath <hvaibhav@ti.com>
CPGMAC SubSystem consist of various sub-modules, like, mdio, cpdma,
cpsw, etc... These sub-modules are also used in some of Davinci family
of devices. Now based on requirement, use-case and available technology
nodes the integration of these sub-modules varies across devices.
So coming back to Linux net driver, currently separate and independent
platform devices & drivers for CPSW and MDIO is implemented. In case of
Davinci they both has separate control, from resources perspective,
like clock.
In case of AM33XX, the resources are shared and only one register
bit-field is provided to control module/clock enable/disable, makes it
difficult to handle common resource.
So the solution here implemented in this patch is,
Create parent<->child relationship between both the drivers, making
CPSW as a parent and MDIO as its child and enumerate all the child nodes
under cpsw module.
Both the drivers will function exactly the way it was operating before,
including runtime-pm functionality. No change is required in MDIO driver
(for that matter to any child driver).
As this is only supported during DT boot, the parent<->child relationship
is created and populated in DT execution flow. The only required change
is inside DTS file, making MDIO as a child to CPSW node.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
---
drivers/net/ethernet/ti/cpsw.c | 16 ++++++++++++++--
1 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index df55e24..fb1a692 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -827,7 +827,7 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
}
data->mac_control = prop;
- for_each_child_of_node(node, slave_node) {
+ for_each_node_by_name(slave_node, "slave") {
struct cpsw_slave_data *slave_data = data->slave_data + i;
const char *phy_id = NULL;
const void *mac_addr = NULL;
@@ -862,6 +862,14 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
i++;
}
+ /*
+ * Populate all the child nodes here...
+ */
+ ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
+ /* We do not want to force this, as in some cases may not have child */
+ if (ret)
+ pr_warn("Doesn't have any child node\n");
+
return 0;
error_ret:
@@ -895,6 +903,11 @@ static int __devinit cpsw_probe(struct platform_device *pdev)
priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
priv->rx_packet_max = max(rx_packet_max, 128);
+ /*
+ * This may be required here for child devices.
+ */
+ pm_runtime_enable(&pdev->dev);
+
if (cpsw_probe_dt(&priv->data, pdev)) {
pr_err("cpsw: platform data missing\n");
ret = -ENODEV;
@@ -921,7 +934,6 @@ static int __devinit cpsw_probe(struct platform_device *pdev)
for (i = 0; i < data->slaves; i++)
priv->slaves[i].slave_num = i;
- pm_runtime_enable(&pdev->dev);
priv->clk = clk_get(&pdev->dev, "fck");
if (IS_ERR(priv->clk)) {
dev_err(&pdev->dev, "fck is not found\n");
--
1.7.2.5
^ permalink raw reply related
* [PATCH 3/5] net: davinci_mdio: Fix type mistake in calling runtime-pm api
From: Richard Cochran @ 2012-10-15 19:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1350327320.git.richardcochran@gmail.com>
From: Vaibhav Hiremath <hvaibhav@ti.com>
By mistake (most likely a copy-paste), instead of pm_runtime_get_sync()
api, driver is calling pm_runtime_put_sync() api in resume callback
function. The bug was introduced by commit id (ae2c07aaf74:
davinci_mdio: runtime PM support).
Now, the reason why it didn't impact functionality is, the patch has
been tested on AM335x-EVM and BeagleBone platform while submitting;
and in case of AM335x the MDIO driver doesn't control the module
enable/disable part, which is handled by CPSW driver.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
---
drivers/net/ethernet/ti/davinci_mdio.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index 51a96db..ae74280 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -465,7 +465,7 @@ static int davinci_mdio_resume(struct device *dev)
u32 ctrl;
spin_lock(&data->lock);
- pm_runtime_put_sync(data->dev);
+ pm_runtime_get_sync(data->dev);
/* restart the scan state machine */
ctrl = __raw_readl(&data->regs->control);
--
1.7.2.5
^ permalink raw reply related
* [PATCH 2/5] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for davinci_mdio
From: Richard Cochran @ 2012-10-15 19:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1350327320.git.richardcochran@gmail.com>
From: Mugunthan V N <mugunthanvnm@ti.com>
This patch adds minimal hwmod support for davinci mdio driver. This patch
requires rework on parent child relation between cpsw and davinci mdio
hwmod data to support runtime PM.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 34 ++++++++++++++++++++++++++-
1 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 59d5c1c..f96bbc0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -650,8 +650,7 @@ static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x8,
.syss_offs = 0x4,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
- SYSS_HAS_RESET_STATUS),
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
MSTANDBY_NO),
.sysc_fields = &omap_hwmod_sysc_type3,
@@ -682,6 +681,8 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+ HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE),
};
/*
@@ -2510,6 +2511,34 @@ static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
{ }
};
+/* mdio class */
+static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
+ .name = "davinci_mdio",
+};
+
+struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
+ {
+ .pa_start = 0x4A101000,
+ .pa_end = 0x4A101000 + SZ_256 - 1,
+ .flags = ADDR_MAP_ON_INIT,
+ },
+ { }
+};
+
+static struct omap_hwmod am33xx_mdio_hwmod = {
+ .name = "davinci_mdio",
+ .class = &am33xx_mdio_hwmod_class,
+ .clkdm_name = "cpsw_125mhz_clkdm",
+ .main_clk = "cpsw_125mhz_gclk",
+};
+
+struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
+ .master = &am33xx_cpgmac0_hwmod,
+ .slave = &am33xx_mdio_hwmod,
+ .addr = am33xx_mdio_addr_space,
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_elm_hwmod,
@@ -3371,6 +3400,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__tptc2,
&am33xx_l3_s__usbss,
&am33xx_l4_hs__cpgmac0,
+ &am33xx_cpgmac0__mdio,
NULL,
};
--
1.7.2.5
^ permalink raw reply related
* [PATCH 1/5] ARM: OMAP2+: gpmc: Fix kernel BUG for DT boot mode
From: Richard Cochran @ 2012-10-15 19:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1350327320.git.richardcochran@gmail.com>
From: hvaibhav@ti.com <hvaibhav@ti.com>
With recent changes in omap gpmc driver code, in case of DT
boot mode, where bootloader does not configure gpmc cs space
will result into kernel BUG() inside gpmc_mem_init() function,
as gpmc cs0 gpmc_config7[0].csvalid bit is set to '1' and
gpmc_config7[0].baseaddress is set to '0' on reset.
This use-case is applicable for any board/EVM which doesn't have
any peripheral connected to gpmc cs0, for example BeagleXM and
BeagleBone, so DT boot mode fails.
This patch adds of_have_populated_dt() check before creating
device, so that for DT boot mode, gpmc probe will not be called
which is expected behavior, as gpmc is not supported yet from DT.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Afzal Mohammed <afzal@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/gpmc.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 5ac5cf3..90b033e 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -981,6 +981,10 @@ static int __init omap_gpmc_init(void)
struct platform_device *pdev;
char *oh_name = "gpmc";
+ /* If dtb is there, the devices will be created dynamically */
+ if (of_have_populated_dt())
+ return -ENODEV;
+
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
--
1.7.2.5
^ permalink raw reply related
* [PATCH 0/5] am335x fixes for 3.7-rc2
From: Richard Cochran @ 2012-10-15 19:16 UTC (permalink / raw)
To: linux-arm-kernel
This series contains patches required to let the kernel run on a TI
am335x, like the popular BeagleBone. None of these patches are from
me, yet all of them are essential fixes. For net-next I have prepared
a cpsw driver extension that enables time stamping and a PTP clock,
but in order to be useful, the kernel must boot and the MAC driver
must be working.
The first patch was supposed to have made -rc1, but it seems to have
been forgotten. The other four patches are for the cpsw MAC driver,
which has not worked since the migration to device tree. Actually, I
am not sure if the cpsw ever did work, but in any case these patches
let the driver work (again), rather than being a lifeless derelict.
Thanks,
Richard
Mugunthan V N (2):
ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for davinci_mdio
arm/dts: am33xx: Add cpsw and mdio module nodes for AM33XX
Vaibhav Hiremath (2):
net: davinci_mdio: Fix type mistake in calling runtime-pm api
net: cpsw: Add parent<->child relation support between cpsw and mdio
hvaibhav at ti.com (1):
ARM: OMAP2+: gpmc: Fix kernel BUG for DT boot mode
arch/arm/boot/dts/am335x-bone.dts | 8 ++++
arch/arm/boot/dts/am335x-evm.dts | 8 ++++
arch/arm/boot/dts/am33xx.dtsi | 50 ++++++++++++++++++++++++++++
arch/arm/mach-omap2/gpmc.c | 4 ++
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 34 ++++++++++++++++++-
drivers/net/ethernet/ti/cpsw.c | 16 ++++++++-
drivers/net/ethernet/ti/davinci_mdio.c | 2 +-
7 files changed, 117 insertions(+), 5 deletions(-)
--
1.7.2.5
^ permalink raw reply
* [PATCH 0/4] Add DT support for Network Space v2 and parents
From: Jason Cooper @ 2012-10-15 19:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121015185037.GA28384@kw.sim.vm.gnt>
On Mon, Oct 15, 2012 at 08:50:37PM +0200, Simon Guinot wrote:
> On Mon, Oct 15, 2012 at 01:01:44PM -0400, Jason Cooper wrote:
> > I'm pretty sure this isn't the first version of this patch series ;-)
> > No need to resend, but could you attach a version number and changelog?
>
> Yes, you are right. For the second patch, it is the second version.
> But all the other patches are at their first version. Then the whole
> patch series is more a v1 than a v2. I am always embarrassed when the
> patches versions are not the same within a series...
Yes, it makes my skin crawl when I send something out like that as well.
My rule of thumb is that if the patch subject matter is still identical
to the previous version, then I only increment that patch. If suggested
changes cause a reshuffle of the whole series, then I just increment the
version number across the board.
In this case, incrementing the first patch would have been fine.
> If you agree, I will reply against the second patch in order to
> underline the changes.
Perfect.
thx,
Jason.
^ permalink raw reply
* [PATCH 1/4] leds: leds-ns2: add device tree binding
From: Simon Guinot @ 2012-10-15 19:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121015174144.GH20922@titan.lakedaemon.net>
On Mon, Oct 15, 2012 at 01:41:44PM -0400, Jason Cooper wrote:
> On Mon, Oct 15, 2012 at 05:34:52PM +0200, Simon Guinot wrote:
> > Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
> > ---
> > .../devicetree/bindings/gpio/leds-ns2.txt | 26 ++++++
> > drivers/leds/leds-ns2.c | 84 +++++++++++++++++++-
> > 2 files changed, 107 insertions(+), 3 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/gpio/leds-ns2.txt
> >
> > diff --git a/Documentation/devicetree/bindings/gpio/leds-ns2.txt b/Documentation/devicetree/bindings/gpio/leds-ns2.txt
> > new file mode 100644
> > index 0000000..1a84969
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/gpio/leds-ns2.txt
> > @@ -0,0 +1,26 @@
> > +Binding for dual-GPIO LED found on Network Space v2 (and parents).
> > +
> > +Required properties:
> > +- compatible: "ns2-leds".
> > +
> > +Each LED is represented as a sub-node of the ns2-leds device.
> > +
> > +Required sub-node properties:
> > +- cmd-gpio: Command LED GPIO. See OF device-tree GPIO specification.
> > +- slow-gpio: Slow LED GPIO. See OF device-tree GPIO specification.
> > +
> > +Optional sub-node properties:
> > +- label: Name for this LED. If omitted, the label is taken from the node name.
> > +- linux,default-trigger: Trigger assigned to the LED.
> > +
> > +Example:
> > +
> > +ns2-leds {
> > + compatible = "ns2-leds";
> > +
> > + blue-sata {
> > + label = "ns2:blue:sata";
> > + slow-gpio = <&gpio0 29 0>;
> > + cmd-gpio = <&gpio0 30 0>;
> > + };
> > +};
> > diff --git a/drivers/leds/leds-ns2.c b/drivers/leds/leds-ns2.c
> > index d176ec8..55d199b 100644
> > --- a/drivers/leds/leds-ns2.c
> > +++ b/drivers/leds/leds-ns2.c
> > @@ -30,6 +30,7 @@
> > #include <linux/leds.h>
> > #include <linux/module.h>
> > #include <linux/platform_data/leds-kirkwood-ns2.h>
> > +#include <linux/of_gpio.h>
> >
> > /*
> > * The Network Space v2 dual-GPIO LED is wired to a CPLD and can blink in
> > @@ -263,6 +264,68 @@ static void delete_ns2_led(struct ns2_led_data *led_dat)
> > gpio_free(led_dat->slow);
> > }
> >
> > +#ifdef CONFIG_OF_GPIO
> > +/*
> > + * Translate OpenFirmware node properties into platform_data.
> > + */
> > +static int __devinit
> > +ns2_leds_get_of_pdata(struct device *dev, struct ns2_led_platform_data *pdata)
> > +{
> > + struct device_node *np = dev->of_node;
> > + struct device_node *child;
> > + struct ns2_led *leds;
> > + int num_leds = 0;
> > + int i = 0;
> > +
> > + num_leds = of_get_child_count(np);
> > + if (!num_leds)
> > + return -ENODEV;
> > +
> > + leds = devm_kzalloc(dev, num_leds * sizeof(struct ns2_led),
> > + GFP_KERNEL);
> > + if (!leds)
> > + return -ENOMEM;
> > +
> > + for_each_child_of_node(np, child) {
> > + const char *string;
> > + int ret;
> > +
> > + ret = of_get_named_gpio(child, "cmd-gpio", 0);
> > + if (ret < 0)
> > + return ret;
>
> free leds?
Maybe I missed something but I though it was the purpose of using devres
function as devm_kzalloc.
>
> > + leds[i].cmd = ret;
> > + ret = of_get_named_gpio(child, "slow-gpio", 0);
> > + if (ret < 0)
> > + return ret;
>
> same here.
>
> > + leds[i].slow = ret;
> > + ret = of_property_read_string(child, "label", &string);
> > + leds[i].name = (ret == 0) ? string : child->name;
> > + ret = of_property_read_string(child, "linux,default-trigger",
> > + &string);
> > + if (ret == 0)
> > + leds[i].default_trigger = string;
> > +
> > + i++;
> > + }
> > +
> > + pdata->leds = leds;
> > + pdata->num_leds = num_leds;
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id of_ns2_leds_match[] = {
> > + { .compatible = "ns2-leds", },
>
> Is this LaCie-specific? eg "lacie,ns2-leds"?
Yes I think it is LaCie specific.
>
> > + {},
> > +};
> > +#else
> > +static int __devinit
> > +ns2_leds_get_of_pdata(struct device *dev, struct ns2_led_platform_data *pdata)
> > +{
> > + return -ENODEV;
> > +}
> > +#endif /* CONFIG_OF_GPIO */
>
> The above doesn't look right to me. The only time
> ns2_leds_get_of_pdata() gets called is when OF_GPIO is enabled. You
> should be able to remove the #else block.
Yes you are right.
>
> > +
> > static int __devinit ns2_led_probe(struct platform_device *pdev)
> > {
> > struct ns2_led_platform_data *pdata = pdev->dev.platform_data;
> > @@ -270,11 +333,25 @@ static int __devinit ns2_led_probe(struct platform_device *pdev)
> > int i;
> > int ret;
> >
> > +#ifdef CONFIG_OF_GPIO
> > + if (!pdata) {
> > + pdata = devm_kzalloc(&pdev->dev,
> > + sizeof(struct ns2_led_platform_data),
> > + GFP_KERNEL);
> > + if (!pdata)
> > + return -ENOMEM;
> > +
> > + ret = ns2_leds_get_of_pdata(&pdev->dev, pdata);
> > + if (ret)
> > + return ret;
> > + }
> > +#else
> > if (!pdata)
> > return -EINVAL;
> > +#endif /* CONFIG_OF_GPIO */
> >
> > leds_data = devm_kzalloc(&pdev->dev, sizeof(struct ns2_led_data) *
> > - pdata->num_leds, GFP_KERNEL);
> > + pdata->num_leds, GFP_KERNEL);
> > if (!leds_data)
> > return -ENOMEM;
> >
> > @@ -312,8 +389,9 @@ static struct platform_driver ns2_led_driver = {
> > .probe = ns2_led_probe,
> > .remove = __devexit_p(ns2_led_remove),
> > .driver = {
> > - .name = "leds-ns2",
> > - .owner = THIS_MODULE,
> > + .name = "leds-ns2",
> > + .owner = THIS_MODULE,
>
> nit. whitespace before '=', above two lines.
Sorry I don't get it. For the two lines before, I used two tabs before
'='. As a result, this lines are aligned with the next one. I got no
warnings and no errors from checkpatch.pl.
>
> > + .of_match_table = of_match_ptr(of_ns2_leds_match),
>
> Have you tried this with OF_GPIO=n? of_match_ptr() handles CONFIG_OF
> being enabled/disabled. Which means the case of CONFIG_OF=y,
> CONFIG_OF_GPIO=n appears to be unhandled.
Good caught. I guess I have just copied a bug from the driver gpio-fan.
Thank you for the review.
Simon
>
> thx,
>
> Jason.
>
> > },
> > };
> >
> > --
> > 1.7.10
> >
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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^ permalink raw reply
* [PATCH V2 3/3] ARM: tegra: move debug-macro.S to include/debug
From: Stephen Warren @ 2012-10-15 19:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350328024-30485-1-git-send-email-swarren@wwwdotorg.org>
From: Stephen Warren <swarren@nvidia.com>
Move Tegra's debug-macro.S over to the common debug macro directory.
Move Tegra's debug UART selection menu into ARM's Kconfig.debug, so that
all related options are selected in the same place.
Tegra's uncompress.h is left in mach-tegra/include/mach; it will be
removed whenever Tegra is converted to multi-platform.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
Rob, Arnd, Olof, I'd particularly like feedback on whether the following:
#include "../../mach-tegra/iomap.h"
in arch/arm/include/debug/tegra.S is acceptable. I'd really like to
continue to #include a header to share the defines to Tegra physical
memory layout and virtual based addresses with Tegra's io.c's struct
map_desc entries, so they can't get out of sync. So, the include can
either use the relative path as quoted above (which I don't think will
cause any significant maintenance issue), or Tegra's iomap.h would have
to be moved somewhere public so e.g. <tegra-iomap.h> could be included.
Second, is the Kconfig.debug change reasonable? I guess I could remove
the second choice menu I added, and just put all the options in the main
"Kernel low-level debugging port" choice. However, that would make the
"if" statements in "config DEBUG_LL_INCLUDE" rather more unwieldy.
v2:
* Remove redundant default selection in Kconfig.debug, fix indentation
there.
* Rebase on iomap.h/irammap.h moves
arch/arm/Kconfig.debug | 38 +++++
arch/arm/include/debug/tegra.S | 209 +++++++++++++++++++++++
arch/arm/mach-tegra/Kconfig | 29 ----
arch/arm/mach-tegra/include/mach/debug-macro.S | 211 ------------------------
4 files changed, 247 insertions(+), 240 deletions(-)
create mode 100644 arch/arm/include/debug/tegra.S
delete mode 100644 arch/arm/mach-tegra/include/mach/debug-macro.S
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b0f3857..96b9425 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -345,6 +345,13 @@ choice
Say Y here if you want kernel low-level debugging support
on SOCFPGA based platforms.
+ config DEBUG_TEGRA_UART
+ depends on ARCH_TEGRA
+ bool "Use Tegra UART for low-level debug"
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Tegra based platforms.
+
config DEBUG_VEXPRESS_UART0_DETECT
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -409,6 +416,36 @@ choice
endchoice
+choice
+ prompt "Low-level debug console UART"
+ depends on DEBUG_LL && DEBUG_TEGRA_UART
+
+ config TEGRA_DEBUG_UART_AUTO_ODMDATA
+ bool "Via ODMDATA"
+ help
+ Automatically determines which UART to use for low-level debug based
+ on the ODMDATA value. This value is part of the BCT, and is written
+ to the boot memory device using nvflash, or other flashing tool.
+ When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
+ 0/1/2/3/4 are UART A/B/C/D/E.
+
+ config TEGRA_DEBUG_UARTA
+ bool "UART A"
+
+ config TEGRA_DEBUG_UARTB
+ bool "UART B"
+
+ config TEGRA_DEBUG_UARTC
+ bool "UART C"
+
+ config TEGRA_DEBUG_UARTD
+ bool "UART D"
+
+ config TEGRA_DEBUG_UARTE
+ bool "UART E"
+
+endchoice
+
config DEBUG_LL_INCLUDE
string
default "debug/icedcc.S" if DEBUG_ICEDCC
@@ -418,6 +455,7 @@ config DEBUG_LL_INCLUDE
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
+ default "debug/tegra.S" if DEBUG_TEGRA_UART
default "mach/debug-macro.S"
config EARLY_PRINTK
diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
new file mode 100644
index 0000000..b957abb
--- /dev/null
+++ b/arch/arm/include/debug/tegra.S
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2010,2011 Google, Inc.
+ * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
+ *
+ * Author:
+ * Colin Cross <ccross@google.com>
+ * Erik Gilling <konkers@google.com>
+ * Doug Anderson <dianders@chromium.org>
+ * Stephen Warren <swarren@nvidia.com>
+ *
+ * Portions based on mach-omap2's debug-macro.S
+ * Copyright (C) 1994-1999 Russell King
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/serial_reg.h>
+
+#include "../../mach-tegra/iomap.h"
+
+#define UART_SHIFT 2
+
+#define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
+#define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
+#define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c)
+#define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10)
+#define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14)
+#define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18)
+#define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0)
+#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
+
+#define checkuart(rp, rv, lhu, bit, uart) \
+ /* Load address of CLK_RST register */ \
+ movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
+ movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
+ /* Load value from CLK_RST register */ \
+ ldr rp, [rp, #0] ; \
+ /* Test UART's reset bit */ \
+ tst rp, #(1 << bit) ; \
+ /* If set, can't use UART; jump to save no UART */ \
+ bne 90f ; \
+ /* Load address of CLK_OUT_ENB register */ \
+ movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
+ movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
+ /* Load value from CLK_OUT_ENB register */ \
+ ldr rp, [rp, #0] ; \
+ /* Test UART's clock enable bit */ \
+ tst rp, #(1 << bit) ; \
+ /* If clear, can't use UART; jump to save no UART */ \
+ beq 90f ; \
+ /* Passed all tests, load address of UART registers */ \
+ movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
+ movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \
+ /* Jump to save UART address */ \
+ b 91f
+
+ .macro addruart, rp, rv, tmp
+ adr \rp, 99f @ actual addr of 99f
+ ldr \rv, [\rp] @ linked addr is stored there
+ sub \rv, \rv, \rp @ offset between the two
+ ldr \rp, [\rp, #4] @ linked tegra_uart_config
+ sub \tmp, \rp, \rv @ actual tegra_uart_config
+ ldr \rp, [\tmp] @ Load tegra_uart_config
+ cmp \rp, #1 @ needs initialization?
+ bne 100f @ no; go load the addresses
+ mov \rv, #0 @ yes; record init is done
+ str \rv, [\tmp]
+
+#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
+ /* Check ODMDATA */
+10: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
+ movt \rp, #TEGRA_PMC_SCRATCH20 >> 16
+ ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
+ ubfx \rv, \rp, #18, #2 @ 19:18 are console type
+ cmp \rv, #2 @ 2 and 3 mean DCC, UART
+ beq 11f @ some boards swap the meaning
+ cmp \rv, #3 @ so accept either
+ bne 90f
+11: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID
+ cmp \rv, #0 @ UART 0?
+ beq 20f
+ cmp \rv, #1 @ UART 1?
+ beq 21f
+ cmp \rv, #2 @ UART 2?
+ beq 22f
+ cmp \rv, #3 @ UART 3?
+ beq 23f
+ cmp \rv, #4 @ UART 4?
+ beq 24f
+ b 90f @ invalid
+#endif
+
+#if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
+ defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+ /* Check UART A validity */
+20: checkuart(\rp, \rv, L, 6, A)
+#endif
+
+#if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
+ defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+ /* Check UART B validity */
+21: checkuart(\rp, \rv, L, 7, B)
+#endif
+
+#if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
+ defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+ /* Check UART C validity */
+22: checkuart(\rp, \rv, H, 23, C)
+#endif
+
+#if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
+ defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+ /* Check UART D validity */
+23: checkuart(\rp, \rv, U, 1, D)
+#endif
+
+#if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
+ defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+ /* Check UART E validity */
+24:
+ checkuart(\rp, \rv, U, 2, E)
+#endif
+
+ /* No valid UART found */
+90: mov \rp, #0
+ /* fall through */
+
+ /* Record whichever UART we chose */
+91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
+ cmp \rp, #0 @ Valid UART address?
+ bne 92f @ Yes, go process it
+ str \rp, [\tmp, #8] @ Store 0 in tegra_uart_phys
+ b 100f @ Done
+92: sub \rv, \rp, #IO_APB_PHYS @ Calculate virt address
+ add \rv, \rv, #IO_APB_VIRT
+ str \rv, [\tmp, #8] @ Store in tegra_uart_virt
+ movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
+ movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
+ ldr \rv, [\rv, #0] @ Load HIDREV
+ ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version
+ cmp \rv, #0x20 @ Tegra20?
+ moveq \rv, #0x75 @ Tegra20 divisor
+ movne \rv, #0xdd @ Tegra30 divisor
+ str \rv, [\tmp, #12] @ Save divisor to scratch
+ /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
+ mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
+ str \rv, [\rp, #UART_LCR << UART_SHIFT]
+ /* uart[UART_DLL] = div & 0xff; */
+ ldr \rv, [\tmp, #12]
+ and \rv, \rv, #0xff
+ str \rv, [\rp, #UART_DLL << UART_SHIFT]
+ /* uart[UART_DLM] = div >> 8; */
+ ldr \rv, [\tmp, #12]
+ lsr \rv, \rv, #8
+ str \rv, [\rp, #UART_DLM << UART_SHIFT]
+ /* uart[UART_LCR] = UART_LCR_WLEN8; */
+ mov \rv, #UART_LCR_WLEN8
+ str \rv, [\rp, #UART_LCR << UART_SHIFT]
+ b 100f
+
+ .align
+99: .word .
+ .word tegra_uart_config
+ .ltorg
+
+ /* Load previously selected UART address */
+100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
+ ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
+ .endm
+
+/*
+ * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
+ * check to make sure that the UART address is actually valid.
+ */
+
+ .macro senduart, rd, rx
+ cmp \rx, #0
+ strneb \rd, [\rx, #UART_TX << UART_SHIFT]
+1001:
+ .endm
+
+ .macro busyuart, rd, rx
+ cmp \rx, #0
+ beq 1002f
+1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
+ and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ bne 1001b
+1002:
+ .endm
+
+ .macro waituart, rd, rx
+#ifdef FLOW_CONTROL
+ cmp \rx, #0
+ beq 1002f
+1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
+ tst \rd, #UART_MSR_CTS
+ beq 1001b
+1002:
+#endif
+ .endm
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 97fcd16..e426d1b 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -57,35 +57,6 @@ config TEGRA_AHB
which controls AHB bus master arbitration and some
perfomance parameters(priority, prefech size).
-choice
- prompt "Low-level debug console UART"
-
-config TEGRA_DEBUG_UART_AUTO_ODMDATA
- bool "Via ODMDATA"
- help
- Automatically determines which UART to use for low-level debug based
- on the ODMDATA value. This value is part of the BCT, and is written
- to the boot memory device using nvflash, or other flashing tool.
- When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
- 0/1/2/3/4 are UART A/B/C/D/E.
-
-config TEGRA_DEBUG_UARTA
- bool "UART-A"
-
-config TEGRA_DEBUG_UARTB
- bool "UART-B"
-
-config TEGRA_DEBUG_UARTC
- bool "UART-C"
-
-config TEGRA_DEBUG_UARTD
- bool "UART-D"
-
-config TEGRA_DEBUG_UARTE
- bool "UART-E"
-
-endchoice
-
config TEGRA_EMC_SCALING_ENABLE
bool "Enable scaling the memory frequency"
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
deleted file mode 100644
index d4c23d6..0000000
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/debug-macro.S
- *
- * Copyright (C) 2010,2011 Google, Inc.
- * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
- *
- * Author:
- * Colin Cross <ccross@google.com>
- * Erik Gilling <konkers@google.com>
- * Doug Anderson <dianders@chromium.org>
- * Stephen Warren <swarren@nvidia.com>
- *
- * Portions based on mach-omap2's debug-macro.S
- * Copyright (C) 1994-1999 Russell King
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/serial_reg.h>
-
-#include "../../iomap.h"
-
-#define UART_SHIFT 2
-
-#define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
-#define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
-#define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c)
-#define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10)
-#define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14)
-#define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18)
-#define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0)
-#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
-
-#define checkuart(rp, rv, lhu, bit, uart) \
- /* Load address of CLK_RST register */ \
- movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
- movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
- /* Load value from CLK_RST register */ \
- ldr rp, [rp, #0] ; \
- /* Test UART's reset bit */ \
- tst rp, #(1 << bit) ; \
- /* If set, can't use UART; jump to save no UART */ \
- bne 90f ; \
- /* Load address of CLK_OUT_ENB register */ \
- movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
- movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
- /* Load value from CLK_OUT_ENB register */ \
- ldr rp, [rp, #0] ; \
- /* Test UART's clock enable bit */ \
- tst rp, #(1 << bit) ; \
- /* If clear, can't use UART; jump to save no UART */ \
- beq 90f ; \
- /* Passed all tests, load address of UART registers */ \
- movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
- movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \
- /* Jump to save UART address */ \
- b 91f
-
- .macro addruart, rp, rv, tmp
- adr \rp, 99f @ actual addr of 99f
- ldr \rv, [\rp] @ linked addr is stored there
- sub \rv, \rv, \rp @ offset between the two
- ldr \rp, [\rp, #4] @ linked tegra_uart_config
- sub \tmp, \rp, \rv @ actual tegra_uart_config
- ldr \rp, [\tmp] @ Load tegra_uart_config
- cmp \rp, #1 @ needs initialization?
- bne 100f @ no; go load the addresses
- mov \rv, #0 @ yes; record init is done
- str \rv, [\tmp]
-
-#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
- /* Check ODMDATA */
-10: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
- movt \rp, #TEGRA_PMC_SCRATCH20 >> 16
- ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
- ubfx \rv, \rp, #18, #2 @ 19:18 are console type
- cmp \rv, #2 @ 2 and 3 mean DCC, UART
- beq 11f @ some boards swap the meaning
- cmp \rv, #3 @ so accept either
- bne 90f
-11: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID
- cmp \rv, #0 @ UART 0?
- beq 20f
- cmp \rv, #1 @ UART 1?
- beq 21f
- cmp \rv, #2 @ UART 2?
- beq 22f
- cmp \rv, #3 @ UART 3?
- beq 23f
- cmp \rv, #4 @ UART 4?
- beq 24f
- b 90f @ invalid
-#endif
-
-#if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
- defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
- /* Check UART A validity */
-20: checkuart(\rp, \rv, L, 6, A)
-#endif
-
-#if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
- defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
- /* Check UART B validity */
-21: checkuart(\rp, \rv, L, 7, B)
-#endif
-
-#if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
- defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
- /* Check UART C validity */
-22: checkuart(\rp, \rv, H, 23, C)
-#endif
-
-#if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
- defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
- /* Check UART D validity */
-23: checkuart(\rp, \rv, U, 1, D)
-#endif
-
-#if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
- defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
- /* Check UART E validity */
-24:
- checkuart(\rp, \rv, U, 2, E)
-#endif
-
- /* No valid UART found */
-90: mov \rp, #0
- /* fall through */
-
- /* Record whichever UART we chose */
-91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
- cmp \rp, #0 @ Valid UART address?
- bne 92f @ Yes, go process it
- str \rp, [\tmp, #8] @ Store 0 in tegra_uart_phys
- b 100f @ Done
-92: sub \rv, \rp, #IO_APB_PHYS @ Calculate virt address
- add \rv, \rv, #IO_APB_VIRT
- str \rv, [\tmp, #8] @ Store in tegra_uart_virt
- movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
- movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
- ldr \rv, [\rv, #0] @ Load HIDREV
- ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version
- cmp \rv, #0x20 @ Tegra20?
- moveq \rv, #0x75 @ Tegra20 divisor
- movne \rv, #0xdd @ Tegra30 divisor
- str \rv, [\tmp, #12] @ Save divisor to scratch
- /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
- mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
- str \rv, [\rp, #UART_LCR << UART_SHIFT]
- /* uart[UART_DLL] = div & 0xff; */
- ldr \rv, [\tmp, #12]
- and \rv, \rv, #0xff
- str \rv, [\rp, #UART_DLL << UART_SHIFT]
- /* uart[UART_DLM] = div >> 8; */
- ldr \rv, [\tmp, #12]
- lsr \rv, \rv, #8
- str \rv, [\rp, #UART_DLM << UART_SHIFT]
- /* uart[UART_LCR] = UART_LCR_WLEN8; */
- mov \rv, #UART_LCR_WLEN8
- str \rv, [\rp, #UART_LCR << UART_SHIFT]
- b 100f
-
- .align
-99: .word .
- .word tegra_uart_config
- .ltorg
-
- /* Load previously selected UART address */
-100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
- ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
- .endm
-
-/*
- * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
- * check to make sure that the UART address is actually valid.
- */
-
- .macro senduart, rd, rx
- cmp \rx, #0
- strneb \rd, [\rx, #UART_TX << UART_SHIFT]
-1001:
- .endm
-
- .macro busyuart, rd, rx
- cmp \rx, #0
- beq 1002f
-1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
- and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
- teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
- bne 1001b
-1002:
- .endm
-
- .macro waituart, rd, rx
-#ifdef FLOW_CONTROL
- cmp \rx, #0
- beq 1002f
-1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
- tst \rd, #UART_MSR_CTS
- beq 1001b
-1002:
-#endif
- .endm
--
1.7.0.4
^ permalink raw reply related
* [PATCH V2 2/3] ARM: tegra: make debug-macro.S work standalone
From: Stephen Warren @ 2012-10-15 19:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350328024-30485-1-git-send-email-swarren@wwwdotorg.org>
From: Stephen Warren <swarren@nvidia.com>
Prior to this change, Tegra's debug-macro.S relied on uncompress.h having
determined which UART to use, and whether it was safe to use the UART
(i.e. is it not in reset, and clocked). This determination was
communicated from uncompress.h to debug-macro.S using a few bytes of
Tegra's IRAM (an on-SoC RAM). This had the disadvantage that uncompress.h
was a required part of the kernel boot process; booting a non-compressed
kernel would not allow earlyprintk to operate.
This change duplicates the UART selection and validation logic into
debug-macro.S so that the reliance on uncompress.h is removed.
This also helps out with single-zImage work, since there is currently no
support for using any uncompress with single-zImage.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Rebase on iomap.h/irammap.h moves
arch/arm/mach-tegra/common.c | 4 +-
arch/arm/mach-tegra/include/mach/debug-macro.S | 151 ++++++++++++++++++++---
arch/arm/mach-tegra/include/mach/uncompress.h | 13 --
arch/arm/mach-tegra/irammap.h | 9 --
4 files changed, 134 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index b493d64..a57dd7a 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -44,13 +44,15 @@
* kernel is loaded. The data is declared here rather than debug-macro.S so
* that multiple inclusions of debug-macro.S point at the same data.
*/
-u32 tegra_uart_config[3] = {
+u32 tegra_uart_config[4] = {
/* Debug UART initialization required */
1,
/* Debug UART physical address */
0,
/* Debug UART virtual address */
0,
+ /* Scratch space for debug macro */
+ 0,
};
#ifdef CONFIG_OF
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
index 44ca7b1..d4c23d6 100644
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -27,7 +27,42 @@
#include <linux/serial_reg.h>
#include "../../iomap.h"
-#include "../../irammap.h"
+
+#define UART_SHIFT 2
+
+#define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
+#define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
+#define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c)
+#define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10)
+#define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14)
+#define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18)
+#define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0)
+#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
+
+#define checkuart(rp, rv, lhu, bit, uart) \
+ /* Load address of CLK_RST register */ \
+ movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
+ movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
+ /* Load value from CLK_RST register */ \
+ ldr rp, [rp, #0] ; \
+ /* Test UART's reset bit */ \
+ tst rp, #(1 << bit) ; \
+ /* If set, can't use UART; jump to save no UART */ \
+ bne 90f ; \
+ /* Load address of CLK_OUT_ENB register */ \
+ movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
+ movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
+ /* Load value from CLK_OUT_ENB register */ \
+ ldr rp, [rp, #0] ; \
+ /* Test UART's clock enable bit */ \
+ tst rp, #(1 << bit) ; \
+ /* If clear, can't use UART; jump to save no UART */ \
+ beq 90f ; \
+ /* Passed all tests, load address of UART registers */ \
+ movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
+ movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \
+ /* Jump to save UART address */ \
+ b 91f
.macro addruart, rp, rv, tmp
adr \rp, 99f @ actual addr of 99f
@@ -36,22 +71,101 @@
ldr \rp, [\rp, #4] @ linked tegra_uart_config
sub \tmp, \rp, \rv @ actual tegra_uart_config
ldr \rp, [\tmp] @ Load tegra_uart_config
- cmp \rp, #1 @ needs intitialization?
+ cmp \rp, #1 @ needs initialization?
bne 100f @ no; go load the addresses
mov \rv, #0 @ yes; record init is done
str \rv, [\tmp]
- mov \rp, #TEGRA_IRAM_BASE @ See if cookie is in IRAM
- ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET]
- movw \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE & 0xffff
- movt \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE >> 16
- cmp \rv, \rp @ Cookie present?
- bne 100f @ No, use default UART
- mov \rp, #TEGRA_IRAM_BASE @ Load UART address from IRAM
- ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET + 4]
- str \rv, [\tmp, #4] @ Store in tegra_uart_phys
- sub \rv, \rv, #IO_APB_PHYS @ Calculate virt address
+
+#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
+ /* Check ODMDATA */
+10: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
+ movt \rp, #TEGRA_PMC_SCRATCH20 >> 16
+ ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
+ ubfx \rv, \rp, #18, #2 @ 19:18 are console type
+ cmp \rv, #2 @ 2 and 3 mean DCC, UART
+ beq 11f @ some boards swap the meaning
+ cmp \rv, #3 @ so accept either
+ bne 90f
+11: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID
+ cmp \rv, #0 @ UART 0?
+ beq 20f
+ cmp \rv, #1 @ UART 1?
+ beq 21f
+ cmp \rv, #2 @ UART 2?
+ beq 22f
+ cmp \rv, #3 @ UART 3?
+ beq 23f
+ cmp \rv, #4 @ UART 4?
+ beq 24f
+ b 90f @ invalid
+#endif
+
+#if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
+ defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+ /* Check UART A validity */
+20: checkuart(\rp, \rv, L, 6, A)
+#endif
+
+#if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
+ defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+ /* Check UART B validity */
+21: checkuart(\rp, \rv, L, 7, B)
+#endif
+
+#if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
+ defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+ /* Check UART C validity */
+22: checkuart(\rp, \rv, H, 23, C)
+#endif
+
+#if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
+ defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+ /* Check UART D validity */
+23: checkuart(\rp, \rv, U, 1, D)
+#endif
+
+#if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
+ defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+ /* Check UART E validity */
+24:
+ checkuart(\rp, \rv, U, 2, E)
+#endif
+
+ /* No valid UART found */
+90: mov \rp, #0
+ /* fall through */
+
+ /* Record whichever UART we chose */
+91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
+ cmp \rp, #0 @ Valid UART address?
+ bne 92f @ Yes, go process it
+ str \rp, [\tmp, #8] @ Store 0 in tegra_uart_phys
+ b 100f @ Done
+92: sub \rv, \rp, #IO_APB_PHYS @ Calculate virt address
add \rv, \rv, #IO_APB_VIRT
str \rv, [\tmp, #8] @ Store in tegra_uart_virt
+ movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
+ movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
+ ldr \rv, [\rv, #0] @ Load HIDREV
+ ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version
+ cmp \rv, #0x20 @ Tegra20?
+ moveq \rv, #0x75 @ Tegra20 divisor
+ movne \rv, #0xdd @ Tegra30 divisor
+ str \rv, [\tmp, #12] @ Save divisor to scratch
+ /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
+ mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
+ str \rv, [\rp, #UART_LCR << UART_SHIFT]
+ /* uart[UART_DLL] = div & 0xff; */
+ ldr \rv, [\tmp, #12]
+ and \rv, \rv, #0xff
+ str \rv, [\rp, #UART_DLL << UART_SHIFT]
+ /* uart[UART_DLM] = div >> 8; */
+ ldr \rv, [\tmp, #12]
+ lsr \rv, \rv, #8
+ str \rv, [\rp, #UART_DLM << UART_SHIFT]
+ /* uart[UART_LCR] = UART_LCR_WLEN8; */
+ mov \rv, #UART_LCR_WLEN8
+ str \rv, [\rp, #UART_LCR << UART_SHIFT]
b 100f
.align
@@ -59,27 +173,24 @@
.word tegra_uart_config
.ltorg
+ /* Load previously selected UART address */
100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
.endm
-#define UART_SHIFT 2
-
/*
* Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
- * check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case.
- * We use the fact that all 5 valid UART addresses all have something in the
- * 2nd-to-lowest byte.
+ * check to make sure that the UART address is actually valid.
*/
.macro senduart, rd, rx
- tst \rx, #0x0000ff00
+ cmp \rx, #0
strneb \rd, [\rx, #UART_TX << UART_SHIFT]
1001:
.endm
.macro busyuart, rd, rx
- tst \rx, #0x0000ff00
+ cmp \rx, #0
beq 1002f
1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
@@ -90,7 +201,7 @@
.macro waituart, rd, rx
#ifdef FLOW_CONTROL
- tst \rx, #0x0000ff00
+ cmp \rx, #0
beq 1002f
1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
tst \rd, #UART_MSR_CTS
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 4150c71..485003f 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -29,7 +29,6 @@
#include <linux/serial_reg.h>
#include "../../iomap.h"
-#include "../../irammap.h"
#define BIT(x) (1 << (x))
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
@@ -52,17 +51,6 @@ static inline void flush(void)
{
}
-static inline void save_uart_address(void)
-{
- u32 *buf = (u32 *)(TEGRA_IRAM_BASE + TEGRA_IRAM_DEBUG_UART_OFFSET);
-
- if (uart) {
- buf[0] = TEGRA_IRAM_DEBUG_UART_COOKIE;
- buf[1] = (u32)uart;
- } else
- buf[0] = 0;
-}
-
static const struct {
u32 base;
u32 reset_reg;
@@ -169,7 +157,6 @@ static inline void arch_decomp_setup(void)
else
uart = (volatile u8 *)uarts[uart_id].base;
- save_uart_address();
if (uart == NULL)
return;
diff --git a/arch/arm/mach-tegra/irammap.h b/arch/arm/mach-tegra/irammap.h
index 0cbe632..501952a 100644
--- a/arch/arm/mach-tegra/irammap.h
+++ b/arch/arm/mach-tegra/irammap.h
@@ -23,13 +23,4 @@
#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
-/*
- * These locations are written to by uncompress.h, and read by debug-macro.S.
- * The first word holds the cookie value if the data is valid. The second
- * word holds the UART physical address.
- */
-#define TEGRA_IRAM_DEBUG_UART_OFFSET SZ_1K
-#define TEGRA_IRAM_DEBUG_UART_SIZE 8
-#define TEGRA_IRAM_DEBUG_UART_COOKIE 0x55415254
-
#endif
--
1.7.0.4
^ permalink raw reply related
* [PATCH V2 1/3] ARM: tegra: simplify DEBUG_LL UART selection options
From: Stephen Warren @ 2012-10-15 19:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
Delete CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH; it's not useful any more:
* No upstream bootloader currently or will ever support this option.
* CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA is a much more direct alternative.
Merge the fixed and automatic UART selection menus into a single choice
for simplicity; now you either pick AUTO_ODMDATA or a single fixed UART,
rather than potentially having an AUTO option override whatever fixed
option was chosen.
Remove TEGRA_DEBUG_UART_NONE; if you don't want a Tegra DEBUG_LL UART,
simply don't turn on DEBUG_LL. NONE used to be the default option, so
pick AUTO_ODMDATA as the new default.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Remove redundant default selection in mach-tegra/Kconfig
* Rebase on iomap.h/irammap.h moves
arch/arm/mach-tegra/Kconfig | 40 ++++---------------
arch/arm/mach-tegra/common.c | 5 +-
arch/arm/mach-tegra/include/mach/uncompress.h | 52 ++-----------------------
arch/arm/mach-tegra/iomap.h | 14 -------
4 files changed, 15 insertions(+), 96 deletions(-)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 9ff6f6e..97fcd16 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -58,11 +58,16 @@ config TEGRA_AHB
perfomance parameters(priority, prefech size).
choice
- prompt "Default low-level debug console UART"
- default TEGRA_DEBUG_UART_NONE
+ prompt "Low-level debug console UART"
-config TEGRA_DEBUG_UART_NONE
- bool "None"
+config TEGRA_DEBUG_UART_AUTO_ODMDATA
+ bool "Via ODMDATA"
+ help
+ Automatically determines which UART to use for low-level debug based
+ on the ODMDATA value. This value is part of the BCT, and is written
+ to the boot memory device using nvflash, or other flashing tool.
+ When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
+ 0/1/2/3/4 are UART A/B/C/D/E.
config TEGRA_DEBUG_UARTA
bool "UART-A"
@@ -81,33 +86,6 @@ config TEGRA_DEBUG_UARTE
endchoice
-choice
- prompt "Automatic low-level debug console UART"
- default TEGRA_DEBUG_UART_AUTO_NONE
-
-config TEGRA_DEBUG_UART_AUTO_NONE
- bool "None"
-
-config TEGRA_DEBUG_UART_AUTO_ODMDATA
- bool "Via ODMDATA"
- help
- Automatically determines which UART to use for low-level debug based
- on the ODMDATA value. This value is part of the BCT, and is written
- to the boot memory device using nvflash, or other flashing tool.
- When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
- 0/1/2/3/4 are UART A/B/C/D/E.
-
-config TEGRA_DEBUG_UART_AUTO_SCRATCH
- bool "Via UART scratch register"
- help
- Automatically determines which UART to use for low-level debug based
- on the UART scratch register value. Some bootloaders put ASCII 'D'
- in this register when they initialize their own console UART output.
- Using this option allows the kernel to automatically pick the same
- UART.
-
-endchoice
-
config TEGRA_EMC_SCALING_ENABLE
bool "Enable scaling the memory frequency"
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index f688daa..b493d64 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -44,14 +44,13 @@
* kernel is loaded. The data is declared here rather than debug-macro.S so
* that multiple inclusions of debug-macro.S point at the same data.
*/
-#define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
u32 tegra_uart_config[3] = {
/* Debug UART initialization required */
1,
/* Debug UART physical address */
- (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
+ 0,
/* Debug UART virtual address */
- (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
+ 0,
};
#ifdef CONFIG_OF
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 2772575..4150c71 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -139,51 +139,19 @@ int auto_odmdata(void)
}
#endif
-#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH
-int auto_scratch(void)
-{
- int i;
-
- /*
- * Look for the first UART that:
- * a) Is not in reset.
- * b) Is clocked.
- * c) Has a 'D' in the scratchpad register.
- *
- * Note that on Tegra30, the first two conditions are required, since
- * if not true, accesses to the UART scratch register will hang.
- * Tegra20 doesn't have this issue.
- *
- * The intent is that the bootloader will tell the kernel which UART
- * to use by setting up those conditions. If nothing found, we'll fall
- * back to what's specified in TEGRA_DEBUG_UART_BASE.
- */
- for (i = 0; i < ARRAY_SIZE(uarts); i++) {
- if (!uart_clocked(i))
- continue;
-
- uart = (volatile u8 *)uarts[i].base;
- if (uart[UART_SCR << DEBUG_UART_SHIFT] != 'D')
- continue;
-
- return i;
- }
-
- return -1;
-}
-#endif
-
/*
* Setup before decompression. This is where we do UART selection for
* earlyprintk and init the uart_base register.
*/
static inline void arch_decomp_setup(void)
{
- int uart_id, auto_uart_id;
+ int uart_id;
volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
u32 chip, div;
-#if defined(CONFIG_TEGRA_DEBUG_UARTA)
+#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+ uart_id = auto_odmdata();
+#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
uart_id = 0;
#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
uart_id = 1;
@@ -193,19 +161,7 @@ static inline void arch_decomp_setup(void)
uart_id = 3;
#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
uart_id = 4;
-#else
- uart_id = -1;
-#endif
-
-#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
- auto_uart_id = auto_odmdata();
-#elif defined(CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH)
- auto_uart_id = auto_scratch();
-#else
- auto_uart_id = -1;
#endif
- if (auto_uart_id != -1)
- uart_id = auto_uart_id;
if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) ||
!uart_clocked(uart_id))
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 5315103..db8be51 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -261,20 +261,6 @@
#define TEGRA_SDMMC4_BASE 0xC8000600
#define TEGRA_SDMMC4_SIZE SZ_512
-#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
-# define TEGRA_DEBUG_UART_BASE 0
-#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
-#endif
-
/* On TEGRA, many peripherals are very closely packed in
* two 256MB io windows (that actually only use about 64KB
* at the start of each).
--
1.7.0.4
^ permalink raw reply related
* [PATCH 1/4] mtd: nand: omap2: Update nerrors using ecc.strength
From: Peter Korsgaard @ 2012-10-15 18:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349274589-11389-2-git-send-email-avinashphilip@ti.com>
>>>>> Philip, Avinash <avinashphilip@ti.com> writes:
> Update number of errors using nand ecc strength.
> Also add macro definitions BCH8_ERROR_MAX & BCH4_ERROR_MAX
> Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
> ---
> :100644 100644 5b31386... af511a9... M drivers/mtd/nand/omap2.c
> drivers/mtd/nand/omap2.c | 12 ++++++++----
> 1 files changed, 8 insertions(+), 4 deletions(-)
> diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
> index 5b31386..af511a9 100644
> --- a/drivers/mtd/nand/omap2.c
> +++ b/drivers/mtd/nand/omap2.c
> @@ -111,6 +111,9 @@
> #define ECCCLEAR 0x100
> #define ECC1 0x1
> +#define BCH8_MAX_ERROR 8 /* upto 8 bit coorectable */
> +#define BCH4_MAX_ERROR 4 /* upto 4 bit correctable */
First 'correctable' misspelled.
I don't personally think these defines improve readability very much
compared to to just using 4/8, though.
--
Bye, Peter Korsgaard
^ permalink raw reply
* [PATCH 0/4] Add DT support for Network Space v2 and parents
From: Simon Guinot @ 2012-10-15 18:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121015170144.GG20922@titan.lakedaemon.net>
On Mon, Oct 15, 2012 at 01:01:44PM -0400, Jason Cooper wrote:
> Hey Simon,
Hi Jason,
>
> On Mon, Oct 15, 2012 at 05:34:51PM +0200, Simon Guinot wrote:
> > This patch series provides DT support for LaCie NAS Network Space v2 and
> > parents. This includes the following machines:
> > - Internet Space v2
> > - Network Space v2
> > - Network Space Max v2
> > - Network Space Lite v2
> > - Network Space Mini v2
> >
> > Note that the three first boards are already supported by the Linux
> > kernel via an "old-fashion" board setup. The two lasts (Lite and Mini)
> > are new boards.
>
> Have you checked building support for the old and new in one kernel? On
> a quick check, it looks okay, but I only checked that ns2_init() wasn't
> the _init function for the legacy board files.
Yes, I have checked building with both old and DT board setups.
>
> > Also note that the first patch of the series is related with the LED
> > subsystem. It adds device tree binding to the driver leds-ns2.
> >
> > Simon Guinot (4):
> > leds: leds-ns2: add device tree binding
> > ARM: kirkwood: DT board setup for Network Space v2 and parents
> > ARM: kirkwood: DT board setup for Network Space Lite v2
> > ARM: kirkwood: DT board setup for Network Space Mini v2
>
> I'm pretty sure this isn't the first version of this patch series ;-)
> No need to resend, but could you attach a version number and changelog?
Yes, you are right. For the second patch, it is the second version.
But all the other patches are at their first version. Then the whole
patch series is more a v1 than a v2. I am always embarrassed when the
patches versions are not the same within a series...
If you agree, I will reply against the second patch in order to
underline the changes.
Thanks,
Simon
>
> thx,
>
> Jason.
>
> >
> > .../devicetree/bindings/gpio/leds-ns2.txt | 26 ++++++
> > arch/arm/boot/dts/Makefile | 5 ++
> > arch/arm/boot/dts/kirkwood-is2.dts | 30 +++++++
> > arch/arm/boot/dts/kirkwood-ns2-common.dtsi | 63 ++++++++++++++
> > arch/arm/boot/dts/kirkwood-ns2.dts | 30 +++++++
> > arch/arm/boot/dts/kirkwood-ns2lite.dts | 30 +++++++
> > arch/arm/boot/dts/kirkwood-ns2max.dts | 49 +++++++++++
> > arch/arm/boot/dts/kirkwood-ns2mini.dts | 49 +++++++++++
> > arch/arm/mach-kirkwood/Kconfig | 36 ++++++++
> > arch/arm/mach-kirkwood/Makefile | 5 ++
> > arch/arm/mach-kirkwood/board-dt.c | 12 +++
> > arch/arm/mach-kirkwood/board-ns2.c | 87 ++++++++++++++++++++
> > arch/arm/mach-kirkwood/common.h | 10 +++
> > drivers/leds/Kconfig | 4 +-
> > drivers/leds/leds-ns2.c | 84 ++++++++++++++++++-
> > 15 files changed, 516 insertions(+), 4 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/gpio/leds-ns2.txt
> > create mode 100644 arch/arm/boot/dts/kirkwood-is2.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ns2-common.dtsi
> > create mode 100644 arch/arm/boot/dts/kirkwood-ns2.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ns2lite.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ns2max.dts
> > create mode 100644 arch/arm/boot/dts/kirkwood-ns2mini.dts
> > create mode 100644 arch/arm/mach-kirkwood/board-ns2.c
> >
> > --
> > 1.7.10
> >
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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^ permalink raw reply
* [PATCH 3/4] ARM: OMAP2: gpmc: Add support for BCH ECC scheme
From: Peter Korsgaard @ 2012-10-15 18:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349274589-11389-4-git-send-email-avinashphilip@ti.com>
>>>>> Philip, Avinash <avinashphilip@ti.com> writes:
> Add support for BCH ECC scheme to gpmc driver and also enabling multi
> sector read/write. This helps in doing single shot NAND page read and
> write.
> ECC engine configurations
> BCH 4 bit support
> 1. write => ECC engine configured in wrap mode 6 and with ecc_size0 as 32.
> 2. read => ECC engine configured in wrap mode 1 and with ecc_size0 as
> 13 and ecc_size1 as 1.
> BCH 8 bit support
> 1. write => ECC engine configured in wrap mode 6 and with ecc_size0 as 32.
> 2. read => ECC engine configured in wrap mode 1 and with ecc_size0 as
> 26 and ecc_size1 as 2.
> Note: For BCH8 ECC bytes set to 14 to make compatible with RBL.
On what device? In the am335x TRM (spruh73f.pdf) figure 26-15 (pg 4273)
the rom code is documented to not use any padding on the ECC bytes
(E.G. oob 2..53):
http://www.ti.com/litv/pdf/spruh73f
I see the driver in the u-boot-am33x tree (ti81xx_nand.c) seems to use
4x14 bytes as well though, so perhaps that's a bug in the documentation
instead?
--
Bye, Peter Korsgaard
^ permalink raw reply
* [PATCH 2/2] ARM: tegra: move irammap.h to mach-tegra
From: Stephen Warren @ 2012-10-15 18:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350326249-18405-1-git-send-email-swarren@wwwdotorg.org>
From: Stephen Warren <swarren@nvidia.com>
Nothing outside mach-tegra uses this file, so there's no need for it to
be in <mach/>.
Since uncompress.h and debug-macro.S remain in include/mach, they need
to include "../../irammap.h" becaue of this change. Both these usages
will be removed shortly, when Tegra's DEBUG_LL implementation is updated
not to pass information through IRAM.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/mach-tegra/include/mach/debug-macro.S | 2 +-
arch/arm/mach-tegra/include/mach/irammap.h | 35 ------------------------
arch/arm/mach-tegra/include/mach/uncompress.h | 3 +-
arch/arm/mach-tegra/irammap.h | 35 ++++++++++++++++++++++++
arch/arm/mach-tegra/reset.c | 3 +-
5 files changed, 38 insertions(+), 40 deletions(-)
delete mode 100644 arch/arm/mach-tegra/include/mach/irammap.h
create mode 100644 arch/arm/mach-tegra/irammap.h
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
index 58a7fa8..44ca7b1 100644
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -27,7 +27,7 @@
#include <linux/serial_reg.h>
#include "../../iomap.h"
-#include <mach/irammap.h>
+#include "../../irammap.h"
.macro addruart, rp, rv, tmp
adr \rp, 99f @ actual addr of 99f
diff --git a/arch/arm/mach-tegra/include/mach/irammap.h b/arch/arm/mach-tegra/include/mach/irammap.h
deleted file mode 100644
index 0cbe632..0000000
--- a/arch/arm/mach-tegra/include/mach/irammap.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __MACH_TEGRA_IRAMMAP_H
-#define __MACH_TEGRA_IRAMMAP_H
-
-#include <asm/sizes.h>
-
-/* The first 1K of IRAM is permanently reserved for the CPU reset handler */
-#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
-#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
-
-/*
- * These locations are written to by uncompress.h, and read by debug-macro.S.
- * The first word holds the cookie value if the data is valid. The second
- * word holds the UART physical address.
- */
-#define TEGRA_IRAM_DEBUG_UART_OFFSET SZ_1K
-#define TEGRA_IRAM_DEBUG_UART_SIZE 8
-#define TEGRA_IRAM_DEBUG_UART_COOKIE 0x55415254
-
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 095216c..2772575 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -28,9 +28,8 @@
#include <linux/types.h>
#include <linux/serial_reg.h>
-#include <mach/irammap.h>
-
#include "../../iomap.h"
+#include "../../irammap.h"
#define BIT(x) (1 << (x))
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
diff --git a/arch/arm/mach-tegra/irammap.h b/arch/arm/mach-tegra/irammap.h
new file mode 100644
index 0000000..0cbe632
--- /dev/null
+++ b/arch/arm/mach-tegra/irammap.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_IRAMMAP_H
+#define __MACH_TEGRA_IRAMMAP_H
+
+#include <asm/sizes.h>
+
+/* The first 1K of IRAM is permanently reserved for the CPU reset handler */
+#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
+#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
+
+/*
+ * These locations are written to by uncompress.h, and read by debug-macro.S.
+ * The first word holds the cookie value if the data is valid. The second
+ * word holds the UART physical address.
+ */
+#define TEGRA_IRAM_DEBUG_UART_OFFSET SZ_1K
+#define TEGRA_IRAM_DEBUG_UART_SIZE 8
+#define TEGRA_IRAM_DEBUG_UART_COOKIE 0x55415254
+
+#endif
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 28e51b7..e05da7d 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -22,9 +22,8 @@
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
-#include <mach/irammap.h>
-
#include "iomap.h"
+#include "irammap.h"
#include "reset.h"
#include "fuse.h"
--
1.7.0.4
^ permalink raw reply related
* [PATCH 1/2] ARM: tegra: move iomap.h to mach-tegra
From: Stephen Warren @ 2012-10-15 18:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
Nothing outside mach-tegra uses this file, so there's no need for it to
be in <mach/>.
Since uncompress.h and debug-macro.S remain in include/mach, they need
to include "../../iomap.h" becaue of this change. uncompress.h will soon
be deleted in later multi-platform/single-zImage patches. debug-macro.S
will need to continue to include this header using an explicit relative
path, to avoid duplicating the physical->virtual address mapping that
iomap.h dictates.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/mach-tegra/apbio.c | 2 +-
arch/arm/mach-tegra/board-dt-tegra20.c | 3 +-
arch/arm/mach-tegra/board-dt-tegra30.c | 3 +-
arch/arm/mach-tegra/common.c | 2 +-
arch/arm/mach-tegra/flowctrl.c | 3 +-
arch/arm/mach-tegra/fuse.c | 3 +-
arch/arm/mach-tegra/headsmp.S | 3 +-
arch/arm/mach-tegra/include/mach/debug-macro.S | 2 +-
arch/arm/mach-tegra/include/mach/iomap.h | 325 ------------------------
arch/arm/mach-tegra/include/mach/uncompress.h | 3 +-
arch/arm/mach-tegra/io.c | 2 +-
arch/arm/mach-tegra/iomap.h | 323 +++++++++++++++++++++++
arch/arm/mach-tegra/irq.c | 3 +-
arch/arm/mach-tegra/pcie.c | 2 +-
arch/arm/mach-tegra/platsmp.c | 2 +-
arch/arm/mach-tegra/pmc.c | 2 +-
arch/arm/mach-tegra/powergate.c | 2 +-
arch/arm/mach-tegra/reset.c | 2 +-
arch/arm/mach-tegra/sleep.S | 2 +-
arch/arm/mach-tegra/sleep.h | 2 +-
arch/arm/mach-tegra/tegra20_clocks.c | 3 +-
arch/arm/mach-tegra/tegra30_clocks.c | 3 +-
arch/arm/mach-tegra/timer.c | 3 +-
23 files changed, 345 insertions(+), 355 deletions(-)
delete mode 100644 arch/arm/mach-tegra/include/mach/iomap.h
create mode 100644 arch/arm/mach-tegra/iomap.h
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index bc949fb..d091675 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -15,7 +15,6 @@
#include <linux/kernel.h>
#include <linux/io.h>
-#include <mach/iomap.h>
#include <linux/of.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
@@ -25,6 +24,7 @@
#include <linux/mutex.h>
#include "apbio.h"
+#include "iomap.h"
#if defined(CONFIG_TEGRA20_APB_DMA)
static DEFINE_MUTEX(tegra_apb_dma_lock);
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 76497e0..6eef907 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -40,11 +40,10 @@
#include <asm/mach/time.h>
#include <asm/setup.h>
-#include <mach/iomap.h>
-
#include "board.h"
#include "clock.h"
#include "common.h"
+#include "iomap.h"
struct tegra_ehci_platform_data tegra_ehci1_pdata = {
.operating_mode = TEGRA_USB_OTG,
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index e4a676d..5fc34fb 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -33,11 +33,10 @@
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
-#include <mach/iomap.h>
-
#include "board.h"
#include "clock.h"
#include "common.h"
+#include "iomap.h"
struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 0b0a5f5..f688daa 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -26,13 +26,13 @@
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
-#include <mach/iomap.h>
#include <mach/powergate.h>
#include "board.h"
#include "clock.h"
#include "common.h"
#include "fuse.h"
+#include "iomap.h"
#include "pmc.h"
#include "apbio.h"
#include "sleep.h"
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index f07488e..ffaa286 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -22,9 +22,8 @@
#include <linux/kernel.h>
#include <linux/io.h>
-#include <mach/iomap.h>
-
#include "flowctrl.h"
+#include "iomap.h"
u8 flowctrl_offset_halt_cpu[] = {
FLOW_CTRL_HALT_CPU0_EVENTS,
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 0b7db17..6c752e8 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -21,9 +21,8 @@
#include <linux/io.h>
#include <linux/export.h>
-#include <mach/iomap.h>
-
#include "fuse.h"
+#include "iomap.h"
#include "apbio.h"
#define FUSE_UID_LOW 0x108
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 6addc78..93f0370 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -3,9 +3,8 @@
#include <asm/cache.h>
-#include <mach/iomap.h>
-
#include "flowctrl.h"
+#include "iomap.h"
#include "reset.h"
#include "sleep.h"
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
index 8ce0661..58a7fa8 100644
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -26,7 +26,7 @@
#include <linux/serial_reg.h>
-#include <mach/iomap.h>
+#include "../../iomap.h"
#include <mach/irammap.h>
.macro addruart, rp, rv, tmp
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
deleted file mode 100644
index fee3a94..0000000
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/iomap.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- * Colin Cross <ccross@google.com>
- * Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_IOMAP_H
-#define __MACH_TEGRA_IOMAP_H
-
-#include <asm/sizes.h>
-
-#define TEGRA_IRAM_BASE 0x40000000
-#define TEGRA_IRAM_SIZE SZ_256K
-
-#define TEGRA_HOST1X_BASE 0x50000000
-#define TEGRA_HOST1X_SIZE 0x24000
-
-#define TEGRA_ARM_PERIF_BASE 0x50040000
-#define TEGRA_ARM_PERIF_SIZE SZ_8K
-
-#define TEGRA_ARM_PL310_BASE 0x50043000
-#define TEGRA_ARM_PL310_SIZE SZ_4K
-
-#define TEGRA_ARM_INT_DIST_BASE 0x50041000
-#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
-
-#define TEGRA_MPE_BASE 0x54040000
-#define TEGRA_MPE_SIZE SZ_256K
-
-#define TEGRA_VI_BASE 0x54080000
-#define TEGRA_VI_SIZE SZ_256K
-
-#define TEGRA_ISP_BASE 0x54100000
-#define TEGRA_ISP_SIZE SZ_256K
-
-#define TEGRA_DISPLAY_BASE 0x54200000
-#define TEGRA_DISPLAY_SIZE SZ_256K
-
-#define TEGRA_DISPLAY2_BASE 0x54240000
-#define TEGRA_DISPLAY2_SIZE SZ_256K
-
-#define TEGRA_HDMI_BASE 0x54280000
-#define TEGRA_HDMI_SIZE SZ_256K
-
-#define TEGRA_GART_BASE 0x58000000
-#define TEGRA_GART_SIZE SZ_32M
-
-#define TEGRA_RES_SEMA_BASE 0x60001000
-#define TEGRA_RES_SEMA_SIZE SZ_4K
-
-#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
-#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_TMR1_BASE 0x60005000
-#define TEGRA_TMR1_SIZE SZ_8
-
-#define TEGRA_TMR2_BASE 0x60005008
-#define TEGRA_TMR2_SIZE SZ_8
-
-#define TEGRA_TMRUS_BASE 0x60005010
-#define TEGRA_TMRUS_SIZE SZ_64
-
-#define TEGRA_TMR3_BASE 0x60005050
-#define TEGRA_TMR3_SIZE SZ_8
-
-#define TEGRA_TMR4_BASE 0x60005058
-#define TEGRA_TMR4_SIZE SZ_8
-
-#define TEGRA_CLK_RESET_BASE 0x60006000
-#define TEGRA_CLK_RESET_SIZE SZ_4K
-
-#define TEGRA_FLOW_CTRL_BASE 0x60007000
-#define TEGRA_FLOW_CTRL_SIZE 20
-
-#define TEGRA_AHB_DMA_BASE 0x60008000
-#define TEGRA_AHB_DMA_SIZE SZ_4K
-
-#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
-#define TEGRA_AHB_DMA_CH0_SIZE 32
-
-#define TEGRA_APB_DMA_BASE 0x6000A000
-#define TEGRA_APB_DMA_SIZE SZ_4K
-
-#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
-#define TEGRA_APB_DMA_CH0_SIZE 32
-
-#define TEGRA_AHB_GIZMO_BASE 0x6000C004
-#define TEGRA_AHB_GIZMO_SIZE 0x10C
-
-#define TEGRA_SB_BASE 0x6000C200
-#define TEGRA_SB_SIZE 256
-
-#define TEGRA_STATMON_BASE 0x6000C400
-#define TEGRA_STATMON_SIZE SZ_1K
-
-#define TEGRA_GPIO_BASE 0x6000D000
-#define TEGRA_GPIO_SIZE SZ_4K
-
-#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
-#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
-
-#define TEGRA_APB_MISC_BASE 0x70000000
-#define TEGRA_APB_MISC_SIZE SZ_4K
-
-#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
-#define TEGRA_APB_MISC_DAS_SIZE SZ_128
-
-#define TEGRA_AC97_BASE 0x70002000
-#define TEGRA_AC97_SIZE SZ_512
-
-#define TEGRA_SPDIF_BASE 0x70002400
-#define TEGRA_SPDIF_SIZE SZ_512
-
-#define TEGRA_I2S1_BASE 0x70002800
-#define TEGRA_I2S1_SIZE SZ_256
-
-#define TEGRA_I2S2_BASE 0x70002A00
-#define TEGRA_I2S2_SIZE SZ_256
-
-#define TEGRA_UARTA_BASE 0x70006000
-#define TEGRA_UARTA_SIZE SZ_64
-
-#define TEGRA_UARTB_BASE 0x70006040
-#define TEGRA_UARTB_SIZE SZ_64
-
-#define TEGRA_UARTC_BASE 0x70006200
-#define TEGRA_UARTC_SIZE SZ_256
-
-#define TEGRA_UARTD_BASE 0x70006300
-#define TEGRA_UARTD_SIZE SZ_256
-
-#define TEGRA_UARTE_BASE 0x70006400
-#define TEGRA_UARTE_SIZE SZ_256
-
-#define TEGRA_NAND_BASE 0x70008000
-#define TEGRA_NAND_SIZE SZ_256
-
-#define TEGRA_HSMMC_BASE 0x70008500
-#define TEGRA_HSMMC_SIZE SZ_256
-
-#define TEGRA_SNOR_BASE 0x70009000
-#define TEGRA_SNOR_SIZE SZ_4K
-
-#define TEGRA_PWFM_BASE 0x7000A000
-#define TEGRA_PWFM_SIZE SZ_256
-
-#define TEGRA_PWFM0_BASE 0x7000A000
-#define TEGRA_PWFM0_SIZE 4
-
-#define TEGRA_PWFM1_BASE 0x7000A010
-#define TEGRA_PWFM1_SIZE 4
-
-#define TEGRA_PWFM2_BASE 0x7000A020
-#define TEGRA_PWFM2_SIZE 4
-
-#define TEGRA_PWFM3_BASE 0x7000A030
-#define TEGRA_PWFM3_SIZE 4
-
-#define TEGRA_MIPI_BASE 0x7000B000
-#define TEGRA_MIPI_SIZE SZ_256
-
-#define TEGRA_I2C_BASE 0x7000C000
-#define TEGRA_I2C_SIZE SZ_256
-
-#define TEGRA_TWC_BASE 0x7000C100
-#define TEGRA_TWC_SIZE SZ_256
-
-#define TEGRA_SPI_BASE 0x7000C380
-#define TEGRA_SPI_SIZE 48
-
-#define TEGRA_I2C2_BASE 0x7000C400
-#define TEGRA_I2C2_SIZE SZ_256
-
-#define TEGRA_I2C3_BASE 0x7000C500
-#define TEGRA_I2C3_SIZE SZ_256
-
-#define TEGRA_OWR_BASE 0x7000C600
-#define TEGRA_OWR_SIZE 80
-
-#define TEGRA_DVC_BASE 0x7000D000
-#define TEGRA_DVC_SIZE SZ_512
-
-#define TEGRA_SPI1_BASE 0x7000D400
-#define TEGRA_SPI1_SIZE SZ_512
-
-#define TEGRA_SPI2_BASE 0x7000D600
-#define TEGRA_SPI2_SIZE SZ_512
-
-#define TEGRA_SPI3_BASE 0x7000D800
-#define TEGRA_SPI3_SIZE SZ_512
-
-#define TEGRA_SPI4_BASE 0x7000DA00
-#define TEGRA_SPI4_SIZE SZ_512
-
-#define TEGRA_RTC_BASE 0x7000E000
-#define TEGRA_RTC_SIZE SZ_256
-
-#define TEGRA_KBC_BASE 0x7000E200
-#define TEGRA_KBC_SIZE SZ_256
-
-#define TEGRA_PMC_BASE 0x7000E400
-#define TEGRA_PMC_SIZE SZ_256
-
-#define TEGRA_MC_BASE 0x7000F000
-#define TEGRA_MC_SIZE SZ_1K
-
-#define TEGRA_EMC_BASE 0x7000F400
-#define TEGRA_EMC_SIZE SZ_1K
-
-#define TEGRA_FUSE_BASE 0x7000F800
-#define TEGRA_FUSE_SIZE SZ_1K
-
-#define TEGRA_KFUSE_BASE 0x7000FC00
-#define TEGRA_KFUSE_SIZE SZ_1K
-
-#define TEGRA_CSITE_BASE 0x70040000
-#define TEGRA_CSITE_SIZE SZ_256K
-
-#define TEGRA_USB_BASE 0xC5000000
-#define TEGRA_USB_SIZE SZ_16K
-
-#define TEGRA_USB2_BASE 0xC5004000
-#define TEGRA_USB2_SIZE SZ_16K
-
-#define TEGRA_USB3_BASE 0xC5008000
-#define TEGRA_USB3_SIZE SZ_16K
-
-#define TEGRA_SDMMC1_BASE 0xC8000000
-#define TEGRA_SDMMC1_SIZE SZ_512
-
-#define TEGRA_SDMMC2_BASE 0xC8000200
-#define TEGRA_SDMMC2_SIZE SZ_512
-
-#define TEGRA_SDMMC3_BASE 0xC8000400
-#define TEGRA_SDMMC3_SIZE SZ_512
-
-#define TEGRA_SDMMC4_BASE 0xC8000600
-#define TEGRA_SDMMC4_SIZE SZ_512
-
-#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
-# define TEGRA_DEBUG_UART_BASE 0
-#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
-#endif
-
-/* On TEGRA, many peripherals are very closely packed in
- * two 256MB io windows (that actually only use about 64KB
- * at the start of each).
- *
- * We will just map the first 1MB of each window (to minimize
- * pt entries needed) and provide a macro to transform physical
- * io addresses to an appropriate void __iomem *.
- *
- */
-
-#define IO_IRAM_PHYS 0x40000000
-#define IO_IRAM_VIRT IOMEM(0xFE400000)
-#define IO_IRAM_SIZE SZ_256K
-
-#define IO_CPU_PHYS 0x50040000
-#define IO_CPU_VIRT IOMEM(0xFE000000)
-#define IO_CPU_SIZE SZ_16K
-
-#define IO_PPSB_PHYS 0x60000000
-#define IO_PPSB_VIRT IOMEM(0xFE200000)
-#define IO_PPSB_SIZE SZ_1M
-
-#define IO_APB_PHYS 0x70000000
-#define IO_APB_VIRT IOMEM(0xFE300000)
-#define IO_APB_SIZE SZ_1M
-
-#define TEGRA_PCIE_BASE 0x80000000
-#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M)
-
-#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
-#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
-
-#define IO_TO_VIRT(n) ( \
- IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \
- IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \
- IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \
- IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \
- IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \
- IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \
- IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \
- IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \
- NULL)
-
-#define IO_ADDRESS(n) (IO_TO_VIRT(n))
-
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 937c4c5..095216c 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -28,9 +28,10 @@
#include <linux/types.h>
#include <linux/serial_reg.h>
-#include <mach/iomap.h>
#include <mach/irammap.h>
+#include "../../iomap.h"
+
#define BIT(x) (1 << (x))
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index 58b4baf..7d09f30 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -26,9 +26,9 @@
#include <asm/page.h>
#include <asm/mach/map.h>
-#include <mach/iomap.h>
#include "board.h"
+#include "iomap.h"
static struct map_desc tegra_io_desc[] __initdata = {
{
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
new file mode 100644
index 0000000..5315103
--- /dev/null
+++ b/arch/arm/mach-tegra/iomap.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ * Colin Cross <ccross@google.com>
+ * Erik Gilling <konkers@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IOMAP_H
+#define __MACH_TEGRA_IOMAP_H
+
+#include <asm/sizes.h>
+
+#define TEGRA_IRAM_BASE 0x40000000
+#define TEGRA_IRAM_SIZE SZ_256K
+
+#define TEGRA_HOST1X_BASE 0x50000000
+#define TEGRA_HOST1X_SIZE 0x24000
+
+#define TEGRA_ARM_PERIF_BASE 0x50040000
+#define TEGRA_ARM_PERIF_SIZE SZ_8K
+
+#define TEGRA_ARM_PL310_BASE 0x50043000
+#define TEGRA_ARM_PL310_SIZE SZ_4K
+
+#define TEGRA_ARM_INT_DIST_BASE 0x50041000
+#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
+
+#define TEGRA_MPE_BASE 0x54040000
+#define TEGRA_MPE_SIZE SZ_256K
+
+#define TEGRA_VI_BASE 0x54080000
+#define TEGRA_VI_SIZE SZ_256K
+
+#define TEGRA_ISP_BASE 0x54100000
+#define TEGRA_ISP_SIZE SZ_256K
+
+#define TEGRA_DISPLAY_BASE 0x54200000
+#define TEGRA_DISPLAY_SIZE SZ_256K
+
+#define TEGRA_DISPLAY2_BASE 0x54240000
+#define TEGRA_DISPLAY2_SIZE SZ_256K
+
+#define TEGRA_HDMI_BASE 0x54280000
+#define TEGRA_HDMI_SIZE SZ_256K
+
+#define TEGRA_GART_BASE 0x58000000
+#define TEGRA_GART_SIZE SZ_32M
+
+#define TEGRA_RES_SEMA_BASE 0x60001000
+#define TEGRA_RES_SEMA_SIZE SZ_4K
+
+#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
+#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
+
+#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
+#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
+
+#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
+#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
+
+#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
+#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64
+
+#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
+#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
+
+#define TEGRA_TMR1_BASE 0x60005000
+#define TEGRA_TMR1_SIZE SZ_8
+
+#define TEGRA_TMR2_BASE 0x60005008
+#define TEGRA_TMR2_SIZE SZ_8
+
+#define TEGRA_TMRUS_BASE 0x60005010
+#define TEGRA_TMRUS_SIZE SZ_64
+
+#define TEGRA_TMR3_BASE 0x60005050
+#define TEGRA_TMR3_SIZE SZ_8
+
+#define TEGRA_TMR4_BASE 0x60005058
+#define TEGRA_TMR4_SIZE SZ_8
+
+#define TEGRA_CLK_RESET_BASE 0x60006000
+#define TEGRA_CLK_RESET_SIZE SZ_4K
+
+#define TEGRA_FLOW_CTRL_BASE 0x60007000
+#define TEGRA_FLOW_CTRL_SIZE 20
+
+#define TEGRA_AHB_DMA_BASE 0x60008000
+#define TEGRA_AHB_DMA_SIZE SZ_4K
+
+#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
+#define TEGRA_AHB_DMA_CH0_SIZE 32
+
+#define TEGRA_APB_DMA_BASE 0x6000A000
+#define TEGRA_APB_DMA_SIZE SZ_4K
+
+#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
+#define TEGRA_APB_DMA_CH0_SIZE 32
+
+#define TEGRA_AHB_GIZMO_BASE 0x6000C004
+#define TEGRA_AHB_GIZMO_SIZE 0x10C
+
+#define TEGRA_SB_BASE 0x6000C200
+#define TEGRA_SB_SIZE 256
+
+#define TEGRA_STATMON_BASE 0x6000C400
+#define TEGRA_STATMON_SIZE SZ_1K
+
+#define TEGRA_GPIO_BASE 0x6000D000
+#define TEGRA_GPIO_SIZE SZ_4K
+
+#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
+#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
+
+#define TEGRA_APB_MISC_BASE 0x70000000
+#define TEGRA_APB_MISC_SIZE SZ_4K
+
+#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
+#define TEGRA_APB_MISC_DAS_SIZE SZ_128
+
+#define TEGRA_AC97_BASE 0x70002000
+#define TEGRA_AC97_SIZE SZ_512
+
+#define TEGRA_SPDIF_BASE 0x70002400
+#define TEGRA_SPDIF_SIZE SZ_512
+
+#define TEGRA_I2S1_BASE 0x70002800
+#define TEGRA_I2S1_SIZE SZ_256
+
+#define TEGRA_I2S2_BASE 0x70002A00
+#define TEGRA_I2S2_SIZE SZ_256
+
+#define TEGRA_UARTA_BASE 0x70006000
+#define TEGRA_UARTA_SIZE SZ_64
+
+#define TEGRA_UARTB_BASE 0x70006040
+#define TEGRA_UARTB_SIZE SZ_64
+
+#define TEGRA_UARTC_BASE 0x70006200
+#define TEGRA_UARTC_SIZE SZ_256
+
+#define TEGRA_UARTD_BASE 0x70006300
+#define TEGRA_UARTD_SIZE SZ_256
+
+#define TEGRA_UARTE_BASE 0x70006400
+#define TEGRA_UARTE_SIZE SZ_256
+
+#define TEGRA_NAND_BASE 0x70008000
+#define TEGRA_NAND_SIZE SZ_256
+
+#define TEGRA_HSMMC_BASE 0x70008500
+#define TEGRA_HSMMC_SIZE SZ_256
+
+#define TEGRA_SNOR_BASE 0x70009000
+#define TEGRA_SNOR_SIZE SZ_4K
+
+#define TEGRA_PWFM_BASE 0x7000A000
+#define TEGRA_PWFM_SIZE SZ_256
+
+#define TEGRA_PWFM0_BASE 0x7000A000
+#define TEGRA_PWFM0_SIZE 4
+
+#define TEGRA_PWFM1_BASE 0x7000A010
+#define TEGRA_PWFM1_SIZE 4
+
+#define TEGRA_PWFM2_BASE 0x7000A020
+#define TEGRA_PWFM2_SIZE 4
+
+#define TEGRA_PWFM3_BASE 0x7000A030
+#define TEGRA_PWFM3_SIZE 4
+
+#define TEGRA_MIPI_BASE 0x7000B000
+#define TEGRA_MIPI_SIZE SZ_256
+
+#define TEGRA_I2C_BASE 0x7000C000
+#define TEGRA_I2C_SIZE SZ_256
+
+#define TEGRA_TWC_BASE 0x7000C100
+#define TEGRA_TWC_SIZE SZ_256
+
+#define TEGRA_SPI_BASE 0x7000C380
+#define TEGRA_SPI_SIZE 48
+
+#define TEGRA_I2C2_BASE 0x7000C400
+#define TEGRA_I2C2_SIZE SZ_256
+
+#define TEGRA_I2C3_BASE 0x7000C500
+#define TEGRA_I2C3_SIZE SZ_256
+
+#define TEGRA_OWR_BASE 0x7000C600
+#define TEGRA_OWR_SIZE 80
+
+#define TEGRA_DVC_BASE 0x7000D000
+#define TEGRA_DVC_SIZE SZ_512
+
+#define TEGRA_SPI1_BASE 0x7000D400
+#define TEGRA_SPI1_SIZE SZ_512
+
+#define TEGRA_SPI2_BASE 0x7000D600
+#define TEGRA_SPI2_SIZE SZ_512
+
+#define TEGRA_SPI3_BASE 0x7000D800
+#define TEGRA_SPI3_SIZE SZ_512
+
+#define TEGRA_SPI4_BASE 0x7000DA00
+#define TEGRA_SPI4_SIZE SZ_512
+
+#define TEGRA_RTC_BASE 0x7000E000
+#define TEGRA_RTC_SIZE SZ_256
+
+#define TEGRA_KBC_BASE 0x7000E200
+#define TEGRA_KBC_SIZE SZ_256
+
+#define TEGRA_PMC_BASE 0x7000E400
+#define TEGRA_PMC_SIZE SZ_256
+
+#define TEGRA_MC_BASE 0x7000F000
+#define TEGRA_MC_SIZE SZ_1K
+
+#define TEGRA_EMC_BASE 0x7000F400
+#define TEGRA_EMC_SIZE SZ_1K
+
+#define TEGRA_FUSE_BASE 0x7000F800
+#define TEGRA_FUSE_SIZE SZ_1K
+
+#define TEGRA_KFUSE_BASE 0x7000FC00
+#define TEGRA_KFUSE_SIZE SZ_1K
+
+#define TEGRA_CSITE_BASE 0x70040000
+#define TEGRA_CSITE_SIZE SZ_256K
+
+#define TEGRA_USB_BASE 0xC5000000
+#define TEGRA_USB_SIZE SZ_16K
+
+#define TEGRA_USB2_BASE 0xC5004000
+#define TEGRA_USB2_SIZE SZ_16K
+
+#define TEGRA_USB3_BASE 0xC5008000
+#define TEGRA_USB3_SIZE SZ_16K
+
+#define TEGRA_SDMMC1_BASE 0xC8000000
+#define TEGRA_SDMMC1_SIZE SZ_512
+
+#define TEGRA_SDMMC2_BASE 0xC8000200
+#define TEGRA_SDMMC2_SIZE SZ_512
+
+#define TEGRA_SDMMC3_BASE 0xC8000400
+#define TEGRA_SDMMC3_SIZE SZ_512
+
+#define TEGRA_SDMMC4_BASE 0xC8000600
+#define TEGRA_SDMMC4_SIZE SZ_512
+
+#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
+# define TEGRA_DEBUG_UART_BASE 0
+#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
+#endif
+
+/* On TEGRA, many peripherals are very closely packed in
+ * two 256MB io windows (that actually only use about 64KB
+ * at the start of each).
+ *
+ * We will just map the first 1MB of each window (to minimize
+ * pt entries needed) and provide a macro to transform physical
+ * io addresses to an appropriate void __iomem *.
+ *
+ */
+
+#define IO_IRAM_PHYS 0x40000000
+#define IO_IRAM_VIRT IOMEM(0xFE400000)
+#define IO_IRAM_SIZE SZ_256K
+
+#define IO_CPU_PHYS 0x50040000
+#define IO_CPU_VIRT IOMEM(0xFE000000)
+#define IO_CPU_SIZE SZ_16K
+
+#define IO_PPSB_PHYS 0x60000000
+#define IO_PPSB_VIRT IOMEM(0xFE200000)
+#define IO_PPSB_SIZE SZ_1M
+
+#define IO_APB_PHYS 0x70000000
+#define IO_APB_VIRT IOMEM(0xFE300000)
+#define IO_APB_SIZE SZ_1M
+
+#define TEGRA_PCIE_BASE 0x80000000
+#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M)
+
+#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
+#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
+
+#define IO_TO_VIRT(n) ( \
+ IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \
+ IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \
+ IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \
+ IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \
+ IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \
+ IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \
+ IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \
+ IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \
+ NULL)
+
+#define IO_ADDRESS(n) (IO_TO_VIRT(n))
+
+#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 2f5bd2d..b7886f1 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -25,9 +25,8 @@
#include <asm/hardware/gic.h>
-#include <mach/iomap.h>
-
#include "board.h"
+#include "iomap.h"
#define ICTLR_CPU_IEP_VFIQ 0x08
#define ICTLR_CPU_IEP_FIR 0x14
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index e82e8b8..53d0858 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -37,11 +37,11 @@
#include <asm/sizes.h>
#include <asm/mach/pci.h>
-#include <mach/iomap.h>
#include <mach/clk.h>
#include <mach/powergate.h>
#include "board.h"
+#include "iomap.h"
/* Hack - need to parse this from DT */
#define INT_PCIE_INTR 130
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index e50870c..1b926df 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -24,7 +24,6 @@
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
-#include <mach/iomap.h>
#include <mach/powergate.h>
#include "fuse.h"
@@ -33,6 +32,7 @@
#include "tegra_cpu_car.h"
#include "common.h"
+#include "iomap.h"
extern void tegra_secondary_startup(void);
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 7af6a54..d4fdb5f 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -19,7 +19,7 @@
#include <linux/io.h>
#include <linux/of.h>
-#include <mach/iomap.h>
+#include "iomap.h"
#define PMC_CTRL 0x0
#define PMC_CTRL_INTR_LOW (1 << 17)
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index de0662d..2cc1185 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -28,10 +28,10 @@
#include <linux/spinlock.h>
#include <mach/clk.h>
-#include <mach/iomap.h>
#include <mach/powergate.h>
#include "fuse.h"
+#include "iomap.h"
#define PWRGATE_TOGGLE 0x30
#define PWRGATE_TOGGLE_START (1 << 8)
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 5beb7eb..28e51b7 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -22,9 +22,9 @@
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
-#include <mach/iomap.h>
#include <mach/irammap.h>
+#include "iomap.h"
#include "reset.h"
#include "fuse.h"
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index ea81554..08e9481 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -26,7 +26,7 @@
#include <asm/assembler.h>
-#include <mach/iomap.h>
+#include "iomap.h"
#include "flowctrl.h"
#include "sleep.h"
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index e25a7cd..4889b28 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -17,7 +17,7 @@
#ifndef __MACH_TEGRA_SLEEP_H
#define __MACH_TEGRA_SLEEP_H
-#include <mach/iomap.h>
+#include "iomap.h"
#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
+ IO_CPU_VIRT)
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index deb873f..4eb6bc8 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -27,10 +27,9 @@
#include <linux/clkdev.h>
#include <linux/clk.h>
-#include <mach/iomap.h>
-
#include "clock.h"
#include "fuse.h"
+#include "iomap.h"
#include "tegra2_emc.h"
#include "tegra_cpu_car.h"
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 5cd502c..245f9a1 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -31,10 +31,9 @@
#include <asm/clkdev.h>
-#include <mach/iomap.h>
-
#include "clock.h"
#include "fuse.h"
+#include "iomap.h"
#include "tegra_cpu_car.h"
#define USE_PLL_LOCK_BITS 0
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index ef38c3c..842ab42 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -32,10 +32,9 @@
#include <asm/smp_twd.h>
#include <asm/sched_clock.h>
-#include <mach/iomap.h>
-
#include "board.h"
#include "clock.h"
+#include "iomap.h"
#define RTC_SECONDS 0x08
#define RTC_SHADOW_SECONDS 0x0c
--
1.7.0.4
^ permalink raw reply related
* [PATCH 5/5] ARM: tegra: select SPARSE_IRQ
From: Stephen Warren @ 2012-10-15 18:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1348090279-22631-5-git-send-email-swarren@wwwdotorg.org>
On 09/19/2012 03:31 PM, Stephen Warren wrote:
> SPARSE_IRQ is required for single zImage support.
>
> With this enabled, we can delete <mach/irqs.h>. This requires removing
> one unnecessary include of that file, and hard-coding the PCIe IRQ into
> the PCIe driver. This is a hack that will be dealt with as part of
> converting the PCIe driver into a true DT-supporting driver.
I have applied this series to Tegra's for-3.8/single-zimage branch.
I'm not sure yet if Tegra will actually be able to be part of single
zImage in 3.8, but this branch will certainly host a fair few changes to
get it very close at least.
^ permalink raw reply
* dma_alloc_coherent fails in framebuffer
From: Tony Prisk @ 2012-10-15 18:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121015094547.GC29125@suse.de>
On Mon, 2012-10-15 at 10:45 +0100, Mel Gorman wrote:
> On Mon, Oct 15, 2012 at 09:34:55AM +1300, Tony Prisk wrote:
> > On Sun, 2012-10-14 at 18:28 +1300, Tony Prisk wrote:
> > > Up until 07 Oct, drivers/video/wm8505-fb.c was working fine, but on the
> > > 11 Oct when I did another pull from linus all of a sudden
> > > dma_alloc_coherent is failing to allocate the framebuffer any longer.
> > >
> > > I did a quick look back and found this:
> > >
> > > ARM: add coherent dma ops
> > >
> > > arch_is_coherent is problematic as it is a global symbol. This
> > > doesn't work for multi-platform kernels or platforms which can support
> > > per device coherent DMA.
> > >
> > > This adds arm_coherent_dma_ops to be used for devices which connected
> > > coherently (i.e. to the ACP port on Cortex-A9 or A15). The arm_dma_ops
> > > are modified at boot when arch_is_coherent is true.
> > >
> > > Signed-off-by: Rob Herring <rob.herring@calxeda.com>
> > > Cc: Russell King <linux@arm.linux.org.uk>
> > > Cc: Marek Szyprowski <m.szyprowski@samsung.com>
> > > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > >
> > >
> > > This is the only patch lately that I could find (not that I would claim
> > > to be any good at finding things) that is related to the problem. Could
> > > it have caused the allocations to fail?
> > >
> > > Regards
> > > Tony P
> >
> > Have done a bit more digging and found the cause - not Rob's patch so
> > apologies.
> >
> > The cause of the regression is this patch:
> >
> > From f40d1e42bb988d2a26e8e111ea4c4c7bac819b7e Mon Sep 17 00:00:00 2001
> > From: Mel Gorman <mgorman@suse.de>
> > Date: Mon, 8 Oct 2012 16:32:36 -0700
> > Subject: [PATCH 2/3] mm: compaction: acquire the zone->lock as late as
> > possible
> >
> > Up until then, the framebuffer allocation with dma_alloc_coherent(...)
> > was fine. From this patch onwards, allocations fail.
> >
>
> Was this found through bisection or some other means?
>
> There was a bug in that series that broke CMA but it was commit bb13ffeb
> (mm: compaction: cache if a pageblock was scanned and no pages were
> isolated) and it was fixed by 62726059 (mm: compaction: fix bit ranges
> in {get,clear,set}_pageblock_skip()). So it should have been fixed by
> 3.7-rc1 and probably was included by the time you pulled in October 11th
> but bisection would be a pain. There were problems with that series during
> development but tests were completing for other people.
>
> Just in case, is this still broken in 3.7-rc1?
Still broken. Although the printk's might have cleared it up a bit.
>
> > I don't know how this patch would effect CMA allocations, but it seems
> > to be causing the issue (or at least, it's caused an error in
> > arch-vt8500 to become visible).
> >
> > Perhaps someone who understand -mm could explain the best way to
> > troubleshoot the cause of this problem?
> >
>
> If you are comfortable with ftrace, it can be used to narrow down where
> the exact failure is occurring but if you're not comfortable with that
> then the easiest is a bunch of printks starting in alloc_contig_range()
> to see at what point and why it returns failure.
>
> It's not obvious at the moment why that patch would cause an allocation
> problem. It's the type of patch that if it was wrong it would fail every
> time for everyone, not just for a single driver.
>
I added some printk's to see what was happening.
from arch/arm/mm/dma-mapping.c: arm_dma_alloc(..) it calls out to:
dma_alloc_from_coherent().
This returns 0, because:
mem = dev->dma_mem
if (!mem) return 0;
and then arm_dma_alloc() falls back on __dma_alloc(..)
I suspect the reason this fault is a bit 'weird' is because its
effectively not using alloc_from_coherent at all, but falling back on
__dma_alloc all the time, and sometimes it fails.
Why it caused a problem on that particular commit I don't know - but it
was reproducible by adding/removing it.
Regards
Tony P
^ permalink raw reply
* [PATCH RFC 2/6 v3] gpio: Add sysfs support to block GPIO API
From: Greg Kroah-Hartman @ 2012-10-15 18:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121015180702.GA12801@game.jcrosoft.org>
On Mon, Oct 15, 2012 at 08:07:02PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 21:11 Fri 12 Oct , Roland Stigge wrote:
> > This patch adds sysfs support to the block GPIO API.
> >
> > Signed-off-by: Roland Stigge <stigge@antcom.de>
> >
> > ---
> > Documentation/ABI/testing/sysfs-gpio | 6
> > drivers/gpio/gpiolib.c | 226 ++++++++++++++++++++++++++++++++++-
> > include/asm-generic/gpio.h | 11 +
> > include/linux/gpio.h | 13 ++
> > 4 files changed, 254 insertions(+), 2 deletions(-)
> I really don't like this sysfs we need to add a specific device with ioctl
Why?
> I put Greg in Cc
Again, why?
greg k-h
^ permalink raw reply
* [PATCH RFC 2/6 v3] gpio: Add sysfs support to block GPIO API
From: Roland Stigge @ 2012-10-15 18:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121015180702.GA12801@game.jcrosoft.org>
On 10/15/2012 08:07 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 21:11 Fri 12 Oct , Roland Stigge wrote:
>> This patch adds sysfs support to the block GPIO API.
>>
>> Signed-off-by: Roland Stigge <stigge@antcom.de>
>>
>> ---
>> Documentation/ABI/testing/sysfs-gpio | 6
>> drivers/gpio/gpiolib.c | 226 ++++++++++++++++++++++++++++++++++-
>> include/asm-generic/gpio.h | 11 +
>> include/linux/gpio.h | 13 ++
>> 4 files changed, 254 insertions(+), 2 deletions(-)
> I really don't like this sysfs we need to add a specific device with ioctl
The good thing about the current style is that you have a single value
for the whole block in a single file just as for single GPIOs. You can
consider it as a generalized GPIO.
And I like it. :-)
Thanks for considering,
Roland
^ permalink raw reply
* [PATCH RFC 2/6 v3] gpio: Add sysfs support to block GPIO API
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-10-15 18:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350069085-13283-3-git-send-email-stigge@antcom.de>
On 21:11 Fri 12 Oct , Roland Stigge wrote:
> This patch adds sysfs support to the block GPIO API.
>
> Signed-off-by: Roland Stigge <stigge@antcom.de>
>
> ---
> Documentation/ABI/testing/sysfs-gpio | 6
> drivers/gpio/gpiolib.c | 226 ++++++++++++++++++++++++++++++++++-
> include/asm-generic/gpio.h | 11 +
> include/linux/gpio.h | 13 ++
> 4 files changed, 254 insertions(+), 2 deletions(-)
I really don't like this sysfs we need to add a specific device with ioctl
I put Greg in Cc
Best Regards,
J.
>
> --- linux-2.6.orig/Documentation/ABI/testing/sysfs-gpio
> +++ linux-2.6/Documentation/ABI/testing/sysfs-gpio
> @@ -24,4 +24,8 @@ Description:
> /base ... (r/o) same as N
> /label ... (r/o) descriptive, not necessarily unique
> /ngpio ... (r/o) number of GPIOs; numbered N to N + (ngpio - 1)
> -
> + /blockN ... for each GPIO block #N
> + /ngpio ... (r/o) number of GPIOs in this group
> + /exported ... sysfs export state of this group (0, 1)
> + /value ... current value as 32 or 64 bit integer in decimal
> + (only available if /exported is 1)
> --- linux-2.6.orig/drivers/gpio/gpiolib.c
> +++ linux-2.6/drivers/gpio/gpiolib.c
> @@ -974,6 +974,218 @@ static void gpiochip_unexport(struct gpi
> chip->label, status);
> }
>
> +static ssize_t gpio_block_ngpio_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + const struct gpio_block *block = dev_get_drvdata(dev);
> +
> + return sprintf(buf, "%u\n", block->ngpio);
> +}
> +static struct device_attribute
> +dev_attr_block_ngpio = __ATTR(ngpio, 0444, gpio_block_ngpio_show, NULL);
> +
> +static ssize_t gpio_block_value_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + const struct gpio_block *block = dev_get_drvdata(dev);
> +
> + return sprintf(buf, "%u\n", gpio_block_get(block));
> +}
> +
> +static bool gpio_block_is_output(struct gpio_block *block)
> +{
> + int i;
> +
> + for (i = 0; i < block->ngpio; i++)
> + if (!test_bit(FLAG_IS_OUT, &gpio_desc[block->gpio[i]].flags))
> + return false;
> + return true;
> +}
> +
> +static ssize_t gpio_block_value_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t size)
> +{
> + ssize_t status;
> + struct gpio_block *block = dev_get_drvdata(dev);
> + unsigned long value;
> +
> + mutex_lock(&sysfs_lock);
> +
> + status = kstrtoul(buf, 0, &value);
> + if (status == 0) {
> + if (gpio_block_is_output(block)) {
> + gpio_block_set(block, value);
> + status = size;
> + } else {
> + status = -EPERM;
> + }
> + }
> +
> + mutex_unlock(&sysfs_lock);
> + return status;
> +}
> +
> +static struct device_attribute
> +dev_attr_block_value = __ATTR(value, 0644, gpio_block_value_show,
> + gpio_block_value_store);
> +
> +static int gpio_block_value_is_exported(struct gpio_block *block)
> +{
> + struct device *dev;
> + struct sysfs_dirent *sd = NULL;
> +
> + mutex_lock(&sysfs_lock);
> + dev = class_find_device(&gpio_class, NULL, block, match_export);
> + if (!dev)
> + goto out;
> +
> + sd = sysfs_get_dirent(dev->kobj.sd, NULL, "value");
> +
> +out:
> + mutex_unlock(&sysfs_lock);
> + return sd ? 1 : 0;
> +}
> +
> +static ssize_t gpio_block_exported_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct gpio_block *block = dev_get_drvdata(dev);
> +
> + return sprintf(buf, "%u\n", gpio_block_value_is_exported(block));
> +}
> +
> +static int gpio_block_value_export(struct gpio_block *block)
> +{
> + struct device *dev;
> + int status;
> + int i;
> +
> + mutex_lock(&sysfs_lock);
> +
> + for (i = 0; i < block->ngpio; i++) {
> + status = gpio_request(block->gpio[i], "sysfs");
> + if (status)
> + goto out;
> + }
> +
> + dev = class_find_device(&gpio_class, NULL, block, match_export);
> + if (!dev) {
> + status = -ENODEV;
> + goto out;
> + }
> +
> + status = device_create_file(dev, &dev_attr_block_value);
> + if (status)
> + goto out;
> +
> + mutex_unlock(&sysfs_lock);
> + return 0;
> +
> +out:
> + while (i > 0) {
> + i--;
> + gpio_free(block->gpio[i]);
> + }
> +
> + mutex_unlock(&sysfs_lock);
> + return status;
> +}
> +
> +static int gpio_block_value_unexport(struct gpio_block *block)
> +{
> + struct device *dev;
> + int i;
> +
> + dev = class_find_device(&gpio_class, NULL, block, match_export);
> + if (!dev)
> + return -ENODEV;
> +
> + for (i = 0; i < block->ngpio; i++)
> + gpio_free(block->gpio[i]);
> +
> + device_remove_file(dev, &dev_attr_block_value);
> +
> + return 0;
> +}
> +
> +static ssize_t gpio_block_exported_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t size)
> +{
> + long value;
> + int status;
> + struct gpio_block *block = dev_get_drvdata(dev);
> + int exported = gpio_block_value_is_exported(block);
> +
> + status = kstrtoul(buf, 0, &value);
> + if (status < 0)
> + goto err;
> +
> + if (value != exported) {
> + if (value)
> + status = gpio_block_value_export(block);
> + else
> + status = gpio_block_value_unexport(block);
> + if (!status)
> + status = size;
> + } else {
> + status = size;
> + }
> +err:
> + return status;
> +}
> +
> +static DEVICE_ATTR(exported, 0644, gpio_block_exported_show,
> + gpio_block_exported_store);
> +
> +static const struct attribute *gpio_block_attrs[] = {
> + &dev_attr_block_ngpio.attr,
> + &dev_attr_exported.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group gpio_block_attr_group = {
> + .attrs = (struct attribute **) gpio_block_attrs,
> +};
> +
> +int gpio_block_export(struct gpio_block *block)
> +{
> + int status;
> + struct device *dev;
> +
> + /* can't export until sysfs is available ... */
> + if (!gpio_class.p) {
> + pr_debug("%s: called too early!\n", __func__);
> + return -ENOENT;
> + }
> +
> + mutex_lock(&sysfs_lock);
> + dev = device_create(&gpio_class, NULL, MKDEV(0, 0), block,
> + block->name);
> + if (!IS_ERR(dev))
> + status = sysfs_create_group(&dev->kobj, &gpio_block_attr_group);
> + else
> + status = PTR_ERR(dev);
> + mutex_unlock(&sysfs_lock);
> +
> + return status;
> +}
> +EXPORT_SYMBOL_GPL(gpio_block_export);
> +
> +void gpio_block_unexport(struct gpio_block *block)
> +{
> + struct device *dev;
> +
> + mutex_lock(&sysfs_lock);
> + dev = class_find_device(&gpio_class, NULL, block, match_export);
> + if (dev)
> + device_unregister(dev);
> + mutex_unlock(&sysfs_lock);
> +}
> +EXPORT_SYMBOL_GPL(gpio_block_unexport);
> +
> static int __init gpiolib_sysfs_init(void)
> {
> int status;
> @@ -1882,7 +2094,14 @@ int gpio_block_register(struct gpio_bloc
> break;
> }
> }
> - return i == NR_GPIO_BLOCKS ? -EBUSY : 0;
> + if (i == NR_GPIO_BLOCKS)
> + goto err;
> +
> + gpio_block_export(block);
> +
> + return 0;
> +err:
> + return -EBUSY;
> }
> EXPORT_SYMBOL_GPL(gpio_block_register);
>
> @@ -1896,6 +2115,11 @@ void gpio_block_unregister(struct gpio_b
> break;
> }
> }
> +
> + if (i == NR_GPIO_BLOCKS)
> + return;
> +
> + gpio_block_unexport(block);
> }
> EXPORT_SYMBOL_GPL(gpio_block_unregister);
>
> --- linux-2.6.orig/include/asm-generic/gpio.h
> +++ linux-2.6/include/asm-generic/gpio.h
> @@ -210,6 +210,8 @@ extern int gpio_export_link(struct devic
> unsigned gpio);
> extern int gpio_sysfs_set_active_low(unsigned gpio, int value);
> extern void gpio_unexport(unsigned gpio);
> +extern int gpio_block_export(struct gpio_block *block);
> +extern void gpio_block_unexport(struct gpio_block *block);
>
> #endif /* CONFIG_GPIO_SYSFS */
>
> @@ -269,6 +271,15 @@ static inline int gpio_sysfs_set_active_
> static inline void gpio_unexport(unsigned gpio)
> {
> }
> +
> +static inline int gpio_block_export(struct gpio_block *block)
> +{
> + return -ENOSYS;
> +}
> +
> +static inline void gpio_block_unexport(struct gpio_block *block)
> +{
> +}
> #endif /* CONFIG_GPIO_SYSFS */
>
> #endif /* _ASM_GENERIC_GPIO_H */
> --- linux-2.6.orig/include/linux/gpio.h
> +++ linux-2.6/include/linux/gpio.h
> @@ -278,6 +278,19 @@ static inline void gpio_unexport(unsigne
> WARN_ON(1);
> }
>
> +static inline int gpio_block_export(struct gpio_block *block)
> +{
> + /* GPIO block can never have been requested or set as {in,out}put */
> + WARN_ON(1);
> + return -EINVAL;
> +}
> +
> +static inline void gpio_block_unexport(struct gpio_block *block)
> +{
> + /* GPIO block can never have been exported */
> + WARN_ON(1);
> +}
> +
> static inline int gpio_to_irq(unsigned gpio)
> {
> /* GPIO can never have been requested or set as input */
^ permalink raw reply
* [PATCH] ARM: tegra: remove <mach/dma.h>
From: Stephen Warren @ 2012-10-15 18:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349206245-22560-1-git-send-email-swarren@wwwdotorg.org>
On 10/02/2012 01:30 PM, Stephen Warren wrote:
> Remove includes of <mach/dma.h> from sound/soc; nothing from it is used.
>
> Remove include of <mach/dma.h> from mach-tegra/apbio.c; since the DMA
> transfers made by this file don't need flow-control with any peripheral,
> there's no need to set any slave ID.
>
> Once those changes are made, there are no remaining users of <mach/dma.h>
> so remove it. Drivers should get this information from device tree. This
> removal is necessary for single zImage.
Applied to Tegra's for-3.8/cleanup branch.
^ permalink raw reply
* [PATCH] ARM: tegra: move tegra-ahb.h out of arch/arm/mach-tegra/
From: Stephen Warren @ 2012-10-15 18:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1348091708-6622-1-git-send-email-swarren@wwwdotorg.org>
On 09/19/2012 03:55 PM, Stephen Warren wrote:
> We wish to empty arch/arm/mach-tegra/include/mach/ as much as possible
> to enable single zImage. Move tegra-ahb.h to a more central location
> (suggested by Arnd, OK'd by Greg KH), and actually make tegra-ahb.c
> include the header to ensure client and provider agree on the prototype.
Applied to Tegra's for-3.8/cleanup branch.
^ permalink raw reply
* [PATCH RFC 2/6 v3] gpio: Add sysfs support to block GPIO API
From: Roland Stigge @ 2012-10-15 18:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <507BA0B4.5030701@gmail.com>
On 10/15/2012 07:35 AM, Ryan Mallon wrote:
>> --- linux-2.6.orig/Documentation/ABI/testing/sysfs-gpio
>> +++ linux-2.6/Documentation/ABI/testing/sysfs-gpio
>> @@ -24,4 +24,8 @@ Description:
>> /base ... (r/o) same as N
>> /label ... (r/o) descriptive, not necessarily unique
>> /ngpio ... (r/o) number of GPIOs; numbered N to N + (ngpio - 1)
>> -
>> + /blockN ... for each GPIO block #N
>> + /ngpio ... (r/o) number of GPIOs in this group
>> + /exported ... sysfs export state of this group (0, 1)
>> + /value ... current value as 32 or 64 bit integer in decimal
>> + (only available if /exported is 1)
>> --- linux-2.6.orig/drivers/gpio/gpiolib.c
>> +++ linux-2.6/drivers/gpio/gpiolib.c
>> @@ -974,6 +974,218 @@ static void gpiochip_unexport(struct gpi
>> chip->label, status);
>> }
>>
>> +static ssize_t gpio_block_ngpio_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + const struct gpio_block *block = dev_get_drvdata(dev);
>> +
>> + return sprintf(buf, "%u\n", block->ngpio);
>> +}
>> +static struct device_attribute
>> +dev_attr_block_ngpio = __ATTR(ngpio, 0444, gpio_block_ngpio_show, NULL);
>
> static DEVICE_ATTR(ngpio, S_IRUGO, gpio_block_ngpio_show, NULL);
Of course I would have used this. :-) But DEVICE_ATTR isn't flexible
enough here. There is already another "ngpio" in this file (resulting in
its name "dev_attr_ngpio") for gpio chips, colliding with this attribute
here (only on C source level - for sysfs it's fine).
Using S_IRUGO - thanks.
>> +}
>> +
>> +static bool gpio_block_is_output(struct gpio_block *block)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < block->ngpio; i++)
>> + if (!test_bit(FLAG_IS_OUT, &gpio_desc[block->gpio[i]].flags))
>> + return false;
>
> Shouldn't a block force all of the pins to be the same direction? Or at
> least have gpio_block_set skip pins which aren't outputs.
It is again analogous to GPIOs themselves: The sysfs interface prevents
Oopses by checking for the direction with the above function. Otherwise,
the user is responsible for requesting and setting direction.
>> +static ssize_t gpio_block_value_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t size)
>> +{
>> + ssize_t status;
>> + struct gpio_block *block = dev_get_drvdata(dev);
>> + unsigned long value;
>> +
>> + mutex_lock(&sysfs_lock);
>> +
>> + status = kstrtoul(buf, 0, &value);
>> + if (status == 0) {
>
> You don't need to do the kstrtoul under the lock:
>
> err = kstrtoul(buf, 0, &value);
> if (err)
> return err;
>
> mutex_lock(&sysfs_lock);
> ...
>
> Global lock is a bit lame, it serialises all of your bitbanged busses
> against each other. Why is it not part of the gpio_block structure?
It's the same strategy as for GPIO value get/set.
More importantly maybe: Consider 32 GPIO lines on a single GPIO
controller. Several defined, say, 8 bit buses defined on this single
hardware word actually need to be locked against each other.
So sticking with it for now.
>> + if (gpio_block_is_output(block)) {
>> + gpio_block_set(block, value);
>> + status = size;
>> + } else {
>> + status = -EPERM;
>> + }
>> + }
>> +
>> + mutex_unlock(&sysfs_lock);
>> + return status;
>> +}
>> +
>> +static struct device_attribute
>> +dev_attr_block_value = __ATTR(value, 0644, gpio_block_value_show,
>> + gpio_block_value_store);
>
> Use DEVICE_ATTR and S_IWUSR | S_IRUGO permission macros.
Regarding DEVICE_ATTR as above. But adopting S_IWUSR | S_IRUGO - thanks.
Again, including all the other suggestions in the next update.
Thanks,
Roland
^ permalink raw reply
* [PATCH] ARM: tegra: remove unnecessary includes of <mach/*.h>
From: Stephen Warren @ 2012-10-15 18:00 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
This should make it easier to delete or move <mach/*.h>; something that
is useful for single-zImage.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
I thought I'd already posted this for review, but apparently not. Anyway,
I intend to apply this immediately to Tegra's for-3.8/cleanup branch.
arch/arm/mach-tegra/board-dt-tegra20.c | 1 -
arch/arm/mach-tegra/clock.c | 2 --
arch/arm/mach-tegra/cpu-tegra.c | 3 ---
arch/arm/mach-tegra/cpuidle.c | 2 --
arch/arm/mach-tegra/include/mach/powergate.h | 2 ++
arch/arm/mach-tegra/platsmp.c | 1 -
arch/arm/mach-tegra/sleep-t20.S | 2 --
arch/arm/mach-tegra/sleep-t30.S | 2 --
arch/arm/mach-tegra/tegra20_clocks_data.c | 2 --
arch/arm/mach-tegra/tegra2_emc.c | 2 --
10 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 57e235f..76497e0 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -41,7 +41,6 @@
#include <asm/setup.h>
#include <mach/iomap.h>
-#include <mach/irqs.h>
#include "board.h"
#include "clock.h"
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index fd82085..867bf8b 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -27,8 +27,6 @@
#include <linux/seq_file.h>
#include <linux/slab.h>
-#include <mach/clk.h>
-
#include "board.h"
#include "clock.h"
#include "tegra_cpu_car.h"
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index 627bf0f..a74d3c7 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -30,9 +30,6 @@
#include <linux/io.h>
#include <linux/suspend.h>
-
-#include <mach/clk.h>
-
/* Frequency table index must be sequential starting at 0 */
static struct cpufreq_frequency_table freq_table[] = {
{ 0, 216000 },
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 566e2f8..9a6f051 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -29,8 +29,6 @@
#include <asm/proc-fns.h>
-#include <mach/iomap.h>
-
static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index);
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index 4752b1a..06763fe 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -20,6 +20,8 @@
#ifndef _MACH_TEGRA_POWERGATE_H_
#define _MACH_TEGRA_POWERGATE_H_
+struct clk;
+
#define TEGRA_POWERGATE_CPU 0
#define TEGRA_POWERGATE_3D 1
#define TEGRA_POWERGATE_VENC 2
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 81cb265..e50870c 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -24,7 +24,6 @@
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
-#include <mach/clk.h>
#include <mach/iomap.h>
#include <mach/powergate.h>
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S
index a36ae41..72ce709 100644
--- a/arch/arm/mach-tegra/sleep-t20.S
+++ b/arch/arm/mach-tegra/sleep-t20.S
@@ -22,8 +22,6 @@
#include <asm/assembler.h>
-#include <mach/iomap.h>
-
#include "sleep.h"
#include "flowctrl.h"
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S
index 777d9ce..be7614b 100644
--- a/arch/arm/mach-tegra/sleep-t30.S
+++ b/arch/arm/mach-tegra/sleep-t30.S
@@ -18,8 +18,6 @@
#include <asm/assembler.h>
-#include <mach/iomap.h>
-
#include "sleep.h"
#include "flowctrl.h"
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index cc9b5fd..d8139b3 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -27,8 +27,6 @@
#include <linux/io.h>
#include <linux/clk.h>
-#include <mach/iomap.h>
-
#include "clock.h"
#include "fuse.h"
#include "tegra2_emc.h"
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index 5070d83..837c7b9 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -25,8 +25,6 @@
#include <linux/platform_device.h>
#include <linux/platform_data/tegra_emc.h>
-#include <mach/iomap.h>
-
#include "tegra2_emc.h"
#include "fuse.h"
--
1.7.0.4
^ permalink raw reply related
* [PATCH v3] ARM: vfp: fix save and restore when running on pre-VFPv3 and CONFIG_VFPv3 set
From: Tony Lindgren @ 2012-10-15 17:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1210150523190.15973@utopia.booyaka.com>
* Paul Walmsley <paul@pwsan.com> [121014 22:26]:
>
> After commit 846a136881b8f73c1f74250bf6acfaa309cab1f2 ("ARM: vfp: fix
> saving d16-d31 vfp registers on v6+ kernels"), the OMAP 2430SDP board
> started crashing during boot with omap2plus_defconfig:
>
> [ 3.875122] mmcblk0: mmc0:e624 SD04G 3.69 GiB
> [ 3.915954] mmcblk0: p1
> [ 4.086639] Internal error: Oops - undefined instruction: 0 [#1] SMP ARM
> [ 4.093719] Modules linked in:
> [ 4.096954] CPU: 0 Not tainted (3.6.0-02232-g759e00b #570)
> [ 4.103149] PC is at vfp_reload_hw+0x1c/0x44
> [ 4.107666] LR is at __und_usr_fault_32+0x0/0x8
>
> It turns out that the context save/restore fix unmasked a latent bug
> in commit 5aaf254409f8d58229107b59507a8235b715a960 ("ARM: 6203/1: Make
> VFPv3 usable on ARMv6"). When CONFIG_VFPv3 is set, but the kernel is
> booted on a pre-VFPv3 core, the code attempts to save and restore the
> d16-d31 VFP registers. These are only present on non-D16 VFPv3+, so
> this results in an undefined instruction exception. The code didn't
> crash before commit 846a136 because the save and restore code was
> only touching d0-d15, present on all VFP.
>
> Fix by implementing a request from Russell King to add a new HWCAP
> flag that affirmatively indicates the presence of the d16-d31
> registers:
>
> http://marc.info/?l=linux-arm-kernel&m=135013547905283&w=2
>
> and some feedback from M?ns to clarify the name of the HWCAP flag.
>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Russell King <rmk+kernel@arm.linux.org.uk>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Dave Martin <dave.martin@linaro.org>
> Cc: M?ns Rullg?rd <mans.rullgard@linaro.org>
This fixes the error above on my 2430sdp:
Tested-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply
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