* [PATCH 4/5] ARM: tegra: dts: cardhu: enable SLINK4
From: Laxman Dewangan @ 2012-10-18 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350557795-31487-1-git-send-email-ldewangan@nvidia.com>
Enable SLINK4 in Tegra30 based platform Cardhu.
Setting maximum spi frequency to 25MHz.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
arch/arm/boot/dts/tegra30-cardhu.dtsi | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index b245e6c..1bd73ea 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -275,6 +275,11 @@
};
};
+ slink at 7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ };
+
ahub {
i2s at 70080400 {
status = "okay";
--
1.7.1.1
^ permalink raw reply related
* [PATCH 3/5] ARM: tegra: fix clock entry of slink controller
From: Laxman Dewangan @ 2012-10-18 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350557795-31487-1-git-send-email-ldewangan@nvidia.com>
Fix the driver name, connection name and clock name
for slink controller clocks in clock table of
Tegra20 and Tegra30.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
arch/arm/mach-tegra/board-dt-tegra20.c | 8 ++++++
arch/arm/mach-tegra/board-dt-tegra30.c | 12 +++++++++
arch/arm/mach-tegra/tegra20_clocks_data.c | 16 ++++++------
arch/arm/mach-tegra/tegra30_clocks_data.c | 36 ++++++++++++++--------------
4 files changed, 46 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 2053f74..2d6915e 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -90,6 +90,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
&tegra_ehci3_pdata),
OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK1_BASE, "spi-tegra-slink.0", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK2_BASE, "spi-tegra-slink.1", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK3_BASE, "spi-tegra-slink.2", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK4_BASE, "spi-tegra-slink.3", NULL),
{}
};
@@ -109,6 +113,10 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
{ "sdmmc1", "pll_p", 48000000, false},
{ "sdmmc3", "pll_p", 48000000, false},
{ "sdmmc4", "pll_p", 48000000, false},
+ { "slink1", "pll_p", 100000000, false },
+ { "slink2", "pll_p", 100000000, false },
+ { "slink3", "pll_p", 100000000, false },
+ { "slink4", "pll_p", 100000000, false },
{ NULL, NULL, 0, 0},
};
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 9e6f79a..cf2defd 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -52,6 +52,12 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK1_BASE, "spi-tegra-slink.0", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK2_BASE, "spi-tegra-slink.1", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK3_BASE, "spi-tegra-slink.2", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK4_BASE, "spi-tegra-slink.3", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK5_BASE, "spi-tegra-slink.4", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK6_BASE, "spi-tegra-slink.5", NULL),
{}
};
@@ -71,6 +77,12 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
{ "sdmmc1", "pll_p", 48000000, false},
{ "sdmmc3", "pll_p", 48000000, false},
{ "sdmmc4", "pll_p", 48000000, false},
+ { "slink1", "pll_p", 100000000, false},
+ { "slink2", "pll_p", 100000000, false},
+ { "slink3", "pll_p", 100000000, false},
+ { "slink4", "pll_p", 100000000, false},
+ { "slink5", "pll_p", 100000000, false},
+ { "slink6", "pll_p", 100000000, false},
{ NULL, NULL, 0, 0},
};
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index 9615ee3..b23c99f 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -894,10 +894,10 @@ PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_c
PERIPH_CLK(spi, "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(xio, "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(twc, "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
-PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
-PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
-PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
-PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(slink1, "spi-tegra-slink.0", "slink", 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(slink2, "spi-tegra-slink.1", "slink", 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(slink3, "spi-tegra-slink.2", "slink", 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(slink4, "spi-tegra-slink.3", "slink", 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(ide, "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
@@ -960,10 +960,10 @@ static struct clk *tegra_list_clks[] = {
&tegra_spi,
&tegra_xio,
&tegra_twc,
- &tegra_sbc1,
- &tegra_sbc2,
- &tegra_sbc3,
- &tegra_sbc4,
+ &tegra_slink1,
+ &tegra_slink2,
+ &tegra_slink3,
+ &tegra_slink4,
&tegra_ide,
&tegra_ndflash,
&tegra_vfir,
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index 3d2e553..8fe2da8 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -1046,12 +1046,12 @@ PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pll
PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0);
-PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(slink1, "spi-tegra-slink.0", "slink", 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(slink2, "spi-tegra-slink.1", "slink", 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(slink3, "spi-tegra-slink.2", "slink", 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(slink4, "spi-tegra-slink.3", "slink", 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(slink5, "spi-tegra-slink.4", "slink", 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(slink6, "spi-tegra-slink.5", "slink", 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0);
@@ -1163,12 +1163,12 @@ struct clk *tegra_list_clks[] = {
&tegra_hda,
&tegra_hda2codec_2x,
&tegra_hda2hdmi,
- &tegra_sbc1,
- &tegra_sbc2,
- &tegra_sbc3,
- &tegra_sbc4,
- &tegra_sbc5,
- &tegra_sbc6,
+ &tegra_slink1,
+ &tegra_slink2,
+ &tegra_slink3,
+ &tegra_slink4,
+ &tegra_slink5,
+ &tegra_slink6,
&tegra_sata_oob,
&tegra_sata,
&tegra_sata_cold,
@@ -1271,12 +1271,12 @@ struct clk_duplicate tegra_clk_duplicates[] = {
CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
- CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
- CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
- CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
- CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
- CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
- CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
+ CLK_DUPLICATE("slink1", "spi_slave_tegra.0", NULL),
+ CLK_DUPLICATE("slink2", "spi_slave_tegra.1", NULL),
+ CLK_DUPLICATE("slink3", "spi_slave_tegra.2", NULL),
+ CLK_DUPLICATE("slink4", "spi_slave_tegra.3", NULL),
+ CLK_DUPLICATE("slink5", "spi_slave_tegra.4", NULL),
+ CLK_DUPLICATE("slink6", "spi_slave_tegra.5", NULL),
CLK_DUPLICATE("twd", "smp_twd", NULL),
CLK_DUPLICATE("vcp", "nvavp", "vcp"),
CLK_DUPLICATE("i2s0", NULL, "i2s0"),
--
1.7.1.1
^ permalink raw reply related
* [PATCH 2/5] ARM: tegra: dts: add slink controller dt entry
From: Laxman Dewangan @ 2012-10-18 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350557795-31487-1-git-send-email-ldewangan@nvidia.com>
Add slink controller details in the dts file of
Tegra20 and Tegra30.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
arch/arm/boot/dts/tegra20.dtsi | 40 ++++++++++++++++++++++++++
arch/arm/boot/dts/tegra30.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 100 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 6934bca..d12a310 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -186,6 +186,46 @@
status = "disabled";
};
+ slink at 7000d400 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d400 0x200>;
+ interrupts = <0 59 0x04>;
+ nvidia,dma-req-sel = <15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink at 7000d600 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d600 0x200>;
+ interrupts = <0 82 0x04>;
+ nvidia,dma-req-sel = <16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink at 7000d800 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d480 0x200>;
+ interrupts = <0 83 0x04>;
+ nvidia,dma-req-sel = <17>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink at 7000da00 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000da00 0x200>;
+ interrupts = <0 93 0x04>;
+ nvidia,dma-req-sel = <18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
pmc {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 81f5df4..f898911 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -191,6 +191,66 @@
status = "disabled";
};
+ slink at 7000d400 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000d400 0x200>;
+ interrupts = <0 59 0x04>;
+ nvidia,dma-req-sel = <15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink at 7000d600 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000d600 0x200>;
+ interrupts = <0 82 0x04>;
+ nvidia,dma-req-sel = <16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink at 7000d800 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000d480 0x200>;
+ interrupts = <0 83 0x04>;
+ nvidia,dma-req-sel = <17>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink at 7000da00 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000da00 0x200>;
+ interrupts = <0 93 0x04>;
+ nvidia,dma-req-sel = <18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink at 7000dc00 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000dc00 0x200>;
+ interrupts = <0 94 0x04>;
+ nvidia,dma-req-sel = <27>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink at 7000de00 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000de00 0x200>;
+ interrupts = <0 79 0x04>;
+ nvidia,dma-req-sel = <28>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
pmc {
compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
reg = <0x7000e400 0x400>;
--
1.7.1.1
^ permalink raw reply related
* [PATCH 1/5] ARM: tegra: Add slink controller base address
From: Laxman Dewangan @ 2012-10-18 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350557795-31487-1-git-send-email-ldewangan@nvidia.com>
Add base address of all slink controller of Tegra20
and tegra30.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
arch/arm/mach-tegra/include/mach/iomap.h | 22 ++++++++++++++--------
1 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index fee3a94..0f46765 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -206,17 +206,23 @@
#define TEGRA_DVC_BASE 0x7000D000
#define TEGRA_DVC_SIZE SZ_512
-#define TEGRA_SPI1_BASE 0x7000D400
-#define TEGRA_SPI1_SIZE SZ_512
+#define TEGRA_SLINK1_BASE 0x7000D400
+#define TEGRA_SLINK1_SIZE SZ_512
-#define TEGRA_SPI2_BASE 0x7000D600
-#define TEGRA_SPI2_SIZE SZ_512
+#define TEGRA_SLINK2_BASE 0x7000D600
+#define TEGRA_SLINK2_SIZE SZ_512
-#define TEGRA_SPI3_BASE 0x7000D800
-#define TEGRA_SPI3_SIZE SZ_512
+#define TEGRA_SLINK3_BASE 0x7000D800
+#define TEGRA_SLINK3_SIZE SZ_512
-#define TEGRA_SPI4_BASE 0x7000DA00
-#define TEGRA_SPI4_SIZE SZ_512
+#define TEGRA_SLINK4_BASE 0x7000DA00
+#define TEGRA_SLINK4_SIZE SZ_512
+
+#define TEGRA_SLINK5_BASE 0x7000DC00
+#define TEGRA_SLINK5_SIZE SZ_512
+
+#define TEGRA_SLINK6_BASE 0x7000DE00
+#define TEGRA_SLINK6_SIZE SZ_512
#define TEGRA_RTC_BASE 0x7000E000
#define TEGRA_RTC_SIZE SZ_256
--
1.7.1.1
^ permalink raw reply related
* [PATCH 0/5] ARM: tegra: Enable SLINK controller driver
From: Laxman Dewangan @ 2012-10-18 10:56 UTC (permalink / raw)
To: linux-arm-kernel
This series modify the dts file to add the slink addresses,
make entry of slink in clock tables, defines SLINK addressed,
enable slink controller in Tegra30 based platform cardhu.
Laxman Dewangan (5):
ARM: tegra: Add slink controller base address
ARM: tegra: dts: add slink controller dt entry
ARM: tegra: fix clock entry of slink controller
ARM: tegra: dts: cardhu: enable SLINK4
ARM: tegra: config: enable spi driver for Tegra SLINK controller
arch/arm/boot/dts/tegra20.dtsi | 40 +++++++++++++++++++
arch/arm/boot/dts/tegra30-cardhu.dtsi | 5 ++
arch/arm/boot/dts/tegra30.dtsi | 60 +++++++++++++++++++++++++++++
arch/arm/configs/tegra_defconfig | 2 +-
arch/arm/mach-tegra/board-dt-tegra20.c | 8 ++++
arch/arm/mach-tegra/board-dt-tegra30.c | 12 ++++++
arch/arm/mach-tegra/include/mach/iomap.h | 22 +++++++----
arch/arm/mach-tegra/tegra20_clocks_data.c | 16 ++++----
arch/arm/mach-tegra/tegra30_clocks_data.c | 36 +++++++++---------
9 files changed, 166 insertions(+), 35 deletions(-)
^ permalink raw reply
* [PATCH] dma: add new DMA control commands
From: Marek Vasut @ 2012-10-18 10:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <507FC827.40601@freescale.com>
Dear Huang Shijie,
> ? 2012?10?18? 16:49, Marek Vasut ??:
> > Dear Huang Shijie,
> >
> >> ? 2012?10?18? 16:16, Marek Vasut ??:
> >>> So we can't stream data from the chip? About time to adjust the MTD
> >>> framework to allow that. Maybe implement a command queue?
> >>
> >> IMHO, it's not possible. Because the READ-PAGE(00h-30h) command needs to
> >> check the busy status
> >> which means we have to stop in the middle, so we can not chain the all
> >> the read-pages DMA commands.
> >
> > Can the DMA not branch?
>
> it's too complicated to the MTD layer, as well as the gpmi driver.
Can you please elaborate ?
Best regards,
Marek Vasut
^ permalink raw reply
* [PATCHv9 8/8] ARM: OMAP4: USB: power down MUSB PHY if not used
From: Felipe Balbi @ 2012-10-18 10:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350552010-28760-9-git-send-email-t-kristo@ti.com>
Hi,
On Thu, Oct 18, 2012 at 12:20:10PM +0300, Tero Kristo wrote:
> Commit c9e4412ab8eb8ef82d645d8749c4ce96ad490007 removed all of the USB
> PHY functions for OMAP4, but this causes a problem with core retention
> as the MUSB module remains enabled if omap-usb2 phy driver is not used.
> This keeps the USB DPLL enabled and prevents l3_init pwrdm from idling.
>
> Fixed by adding a minimal function back that disables the USB PHY in
> case omap-usb2 driver is not used.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: Felipe Balbi <balbi@ti.com>
> Cc: Tony Lindgren <tony@atomide.com>
> ---
> arch/arm/mach-omap2/omap_phy_internal.c | 27 +++++++++++++++++++++++++++
> 1 files changed, 27 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
> index d992db8..6a4b9cf 100644
> --- a/arch/arm/mach-omap2/omap_phy_internal.c
> +++ b/arch/arm/mach-omap2/omap_phy_internal.c
> @@ -33,6 +33,33 @@
> #include "soc.h"
> #include "control.h"
>
> +#define CONTROL_DEV_CONF 0x300
> +#define PHY_PD 0x1
> +
> +#ifndef CONFIG_OMAP_USB2
this is a tristate, meaning that can be a module.
> +static int __init omap4430_phy_power_down(void)
> +{
> + void __iomem *ctrl_base;
> +
> + if (!cpu_is_omap44xx())
> + return 0;
> +
> + ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
> + if (!ctrl_base) {
> + pr_err("control module ioremap failed\n");
> + return -ENOMEM;
> + }
> +
> + /* Power down the phy */
> + __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
> +
> + iounmap(ctrl_base);
> +
> + return 0;
> +}
> +early_initcall(omap4430_phy_power_down);
> +#endif
I think you could do it even if the driver is enabled.
Just to make sure I understand the issue right: is the PHY enabled by
default or did bootloader left this enabled ?
--
balbi
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^ permalink raw reply
* [PATCHv1] arm:socfpga: Enable SMP for socfpga
From: Pavel Machek @ 2012-10-18 10:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <507F3F9C.7040704@gmail.com>
Hi!
> >>> + timeout = jiffies + (1 * HZ);
> >>> + while (time_before(jiffies, timeout)) {
> >>> + smp_rmb();
> >>> + if (pen_release == -1)
> >>> + break;
> >>> +
> >>> + udelay(10);
> >>> + }
> >>> +
> >>> + /*
> >>> + * now the secondary core is starting up let it run its
> >>> + * calibrations, then wait for it to finish
> >>> + */
> >>> + spin_unlock(&boot_lock);
> >>> + return pen_release != -1 ? -ENOSYS : 0;
> >>
> >> You don't need any of this if you can reset secondary cores on
> >> hotplug.
> >
> > What exactly is unneccessary? I'd like to wait for secondary to come
> > up so we can raise an error if it does not...?
> >
>
> Look at the highbank code.
>
> If hotplug will cause a reset of the core, then none of this pen code is
> needed. If hotplug just does a wfi and returns from the wfi when
> onlining the core like Versatile Express, then you need this pen code.
> There's been several prior discussions about this on the list.
>
> If you will never support hotplug (and therefore suspend), then you
> don't need this pen code either.
Ok, so I guess we should go with the simple code for now? Something
like...
BTW... I wonder if I should put socfpga_smp_init_cpus(void) into the
library somewhere? (Where?) Same code is used on highbank, imx,
socfpga, spear13xx, tegra and ct-ca9x4...
Signed-off-by: Pavel Machek <pavel@denx.de>
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index 081b4d1..ee19ce9 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -1,5 +1,5 @@
/*
- * linux/arch/arm/plat-socfpga5xs1/headsmp.S
+ * Trampoline to bring CPU from reset.
*
* Copyright (c) 2012 Pavel Machek <pavel@denx.de>
* Copyright (c) u-boot contributors
@@ -15,9 +15,9 @@
__INIT
-#define HPS_SYSMGR_ADDRESS 0xffd08000
-#define CONFIG_SYSTEM_MANAGER HPS_SYSMGR_ADDRESS
-#define CONFIG_CPU1_START_ADDR (CONFIG_SYSTEM_MANAGER + 0x10)
+#define HPS_SYSMGR_ADDRESS 0xffd08000
+#define CONFIG_SYSTEM_MANAGER HPS_SYSMGR_ADDRESS
+#define CONFIG_CPU1_START_ADDR (CONFIG_SYSTEM_MANAGER + 0x10)
ENTRY(secondary_trampoline)
movw r0, #:lower16:CONFIG_CPU1_START_ADDR
@@ -25,9 +25,4 @@ ENTRY(secondary_trampoline)
ldr r1, [r0]
bx r1
-
ENTRY(secondary_trampoline_end)
-
- .align
- .long pen_release
-
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 60c2b4a..fb3c58c 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -1,4 +1,7 @@
-/* Copyright 2010-2011 Calxeda, Inc.
+/*
+ * SMP support.
+ *
+ * Copyright 2010-2011 Calxeda, Inc.
* Copyright 2012 Pavel Machek <pavel@denx.de>
* Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
*
@@ -31,8 +34,6 @@
static void __iomem *sys_manager_base_addr;
static void __iomem *rst_manager_base_addr;
-static DEFINE_SPINLOCK(boot_lock);
-
static void __cpuinit socfpga_secondary_init(unsigned int cpu)
{
/*
@@ -41,41 +42,20 @@ static void __cpuinit socfpga_secondary_init(unsigned int cpu)
* for us: do so
*/
gic_secondary_init(0);
-
- /*
- * let the primary processor know we're out of the
- * pen, then head off into the C entry point
- */
- pen_release = -1;
- smp_wmb();
-
- /*
- * Synchronise with the boot thread.
- */
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
-
- early_printk("Secondary ready.\n");
+ early_printk("Started secondary.\n");
}
static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
- unsigned long timeout;
extern char secondary_trampoline, secondary_trampoline_end;
int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
early_printk("Boot secondary...\n");
- /*
- * Set synchronisation state between this boot processor
- * and the secondary one
- */
- spin_lock(&boot_lock);
memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
__raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
- pen_release = 0;
flush_cache_all();
smp_wmb();
outer_clean_range(0, trampoline_size);
@@ -83,21 +63,7 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct
in u-boot */
__raw_writel(0, rst_manager_base_addr + 0x10);
- timeout = jiffies + (1 * HZ);
- while (time_before(jiffies, timeout)) {
- smp_rmb();
- if (pen_release == -1)
- break;
-
- udelay(10);
- }
-
- /*
- * now the secondary core is starting up let it run its
- * calibrations, then wait for it to finish
- */
- spin_unlock(&boot_lock);
- return pen_release != -1 ? -ENOSYS : 0;
+ return 0;
}
/*
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply related
* [PATCH RFC 02/15 v5] gpio: Add sysfs support to block GPIO API
From: Roland Stigge @ 2012-10-18 10:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121017190520.GC25996@kroah.com>
On 10/17/2012 09:05 PM, Greg KH wrote:
>> +static int gpio_block_value_unexport(struct gpio_block *block)
>> +{
>> + struct device *dev;
>> + int i;
>> +
>> + dev = class_find_device(&gpio_block_class, NULL, block, match_export);
>> + if (!dev)
>> + return -ENODEV;
>> +
>> + for (i = 0; i < block->ngpio; i++)
>> + gpio_free(block->gpio[i]);
>> +
>> + device_remove_file(dev, &dev_attr_block_value);
>> +
>> + return 0;
>> +}
>
> Wait, what? You are removing a sysfs file in this function, from within
> a sysfs write:
Yes, exactly:
>> +static ssize_t gpio_block_exported_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t size)
>> +{
>> + long value;
>> + int status;
>> + struct gpio_block *block = dev_get_drvdata(dev);
>> + int exported = gpio_block_value_is_exported(block);
>> +
>> + status = kstrtoul(buf, 0, &value);
>> + if (status < 0)
>> + goto err;
>> +
>> + if (value != exported) {
>> + if (value)
>> + status = gpio_block_value_export(block);
>> + else
>> + status = gpio_block_value_unexport(block);
>
> That looks like a recipie for disaster. Why do you allow userspace to
> do this?
Exporting for gpio blocks is done as follows: writing "1" to the
"exported" _device_ attribute of the gpio block creates the "values"
attribute and at the same time requests the whole block (including all
of its gpios) as "sysfs".
This admittedly deviates from the exporting of gpios (with the "export"
and "unexport" _class_ attributes) because blocks are not numbered. In
contrast, they are registered in a list (as was requested). Now, I
already had the idea of also having an "export" and "unexport" _class_
attribute for blocks also, but from a userspace perspective you only see
the presence and name of the gpio block if it is already being in sysfs
(even if not exported yet). If it wouldn't be this way, a user couldn't
guess how the required gpio block is called (or numbered), wouldn't even
know about its presence.
Just for understanding your strong desire for the device attribute
("value") being always present (in contrast to being created and removed
dynamically) - can you please give me any hint how the dynamic approach
would lead to disaster?
One possibility would be to always have "value" as a default device
attribute, but then it wouldn't be so obvious that it's useless until
"exported" is "1".
What do you think?
For now, I would elaborate about my terse "only available if /exported
is 1" like this:
"
Block GPIO devices are visible in sysfs as soon as they are registered
(e.g. via devicetree definition). For actual I/O use, their "exported"
boolean attribute must be set to "1". Then, the attribute "values" is
created and at the same time, the GPIOs in the block are requested for
exclusive use by sysfs.
"
Thanks in advance,
Roland
^ permalink raw reply
* [PATCH] pinctrl: reserve pins when states are activated
From: Linus Walleij @ 2012-10-18 10:01 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This switches the way that pins are reserved for multiplexing:
We used to do this when the map was parsed, at the creation of
the settings inside the pinctrl handle, in pinmux_map_to_setting().
However this does not work for us, because we want to use the
same set of pins with different devices at different times: the
current code assumes that the pin groups in a pinmux state will
only be used with one single device, albeit different groups can
be active at different times. For example if a single I2C driver
block is used to drive two different busses located on two
pin groups A and B, then the pins for all possible states of a
function are reserved when fetching the pinctrl handle: the
I2C bus can choose either set A or set B by a mux state at
runtime, but all pins in both group A and B (the superset) are
effectively reserved for that I2C function and mapped to the
device. Another device can never get in and use the pins in
group A, even if the device/function is using group B at the
moment.
Instead: let use reserve the pins when the state is activated
and drop them when the state is disabled, i.e. when we move to
another state. This way different devices/functions can use the
same pins at different times.
We know that this is an odd way of doing things, but we really
need to switch e.g. an SD-card slot to become a tracing output
sink at runtime: we plug in a special "tracing card" then mux
the pins that used to be an SD slot around to the tracing
unit and push out tracing data there instead of SD-card
traffic.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Jean Nicolas Graux <jean-nicolas.graux@stericsson.com>
Cc: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Documentation/pinctrl.txt | 4 ++-
drivers/pinctrl/core.c | 2 ++
drivers/pinctrl/core.h | 2 ++
drivers/pinctrl/pinmux.c | 70 +++++++++++++++++------------------------------
4 files changed, 32 insertions(+), 46 deletions(-)
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index 3b4ee53..a1cd2f9 100644
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -1193,4 +1193,6 @@ foo_switch()
...
}
-The above has to be done from process context.
+The above has to be done from process context. The reservation of the pins
+will be done when the state is activated, so in effect one specific pin
+can be used by different functions at different times on a running system.
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 0f1ec9e..5c6dff2 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -563,6 +563,8 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map)
return -EPROBE_DEFER;
}
+ setting->dev_name = map->dev_name;
+
switch (map->type) {
case PIN_MAP_TYPE_MUX_GROUP:
ret = pinmux_map_to_setting(map, setting);
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 1f40ff6..12f5694 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -105,12 +105,14 @@ struct pinctrl_setting_configs {
* @type: the type of setting
* @pctldev: pin control device handling to be programmed. Not used for
* PIN_MAP_TYPE_DUMMY_STATE.
+ * @dev_name: the name of the device using this state
* @data: Data specific to the setting type
*/
struct pinctrl_setting {
struct list_head node;
enum pinctrl_map_type type;
struct pinctrl_dev *pctldev;
+ const char *dev_name;
union {
struct pinctrl_setting_mux mux;
struct pinctrl_setting_configs configs;
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 9301a7a..dadc891 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -314,14 +314,11 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
- const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
char const * const *groups;
unsigned num_groups;
int ret;
const char *group;
int i;
- const unsigned *pins;
- unsigned num_pins;
if (!pmxops) {
dev_err(pctldev->dev, "does not support mux function\n");
@@ -376,53 +373,15 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
}
setting->data.mux.group = ret;
- ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins,
- &num_pins);
- if (ret) {
- dev_err(pctldev->dev,
- "could not get pins for device %s group selector %d\n",
- pinctrl_dev_get_name(pctldev), setting->data.mux.group);
- return -ENODEV;
- }
-
- /* Try to allocate all pins in this group, one by one */
- for (i = 0; i < num_pins; i++) {
- ret = pin_request(pctldev, pins[i], map->dev_name, NULL);
- if (ret) {
- dev_err(pctldev->dev,
- "could not request pin %d on device %s\n",
- pins[i], pinctrl_dev_get_name(pctldev));
- /* On error release all taken pins */
- i--; /* this pin just failed */
- for (; i >= 0; i--)
- pin_free(pctldev, pins[i], NULL);
- return -ENODEV;
- }
- }
-
return 0;
}
void pinmux_free_setting(struct pinctrl_setting const *setting)
{
- struct pinctrl_dev *pctldev = setting->pctldev;
- const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
- const unsigned *pins;
- unsigned num_pins;
- int ret;
- int i;
-
- ret = pctlops->get_group_pins(pctldev, setting->data.mux.group,
- &pins, &num_pins);
- if (ret) {
- dev_err(pctldev->dev,
- "could not get pins for device %s group selector %d\n",
- pinctrl_dev_get_name(pctldev), setting->data.mux.group);
- return;
- }
-
- for (i = 0; i < num_pins; i++)
- pin_free(pctldev, pins[i], NULL);
+ /*
+ * If a setting is active, disable it so that all pins are released
+ */
+ pinmux_disable_setting(setting);
}
int pinmux_enable_setting(struct pinctrl_setting const *setting)
@@ -446,6 +405,22 @@ int pinmux_enable_setting(struct pinctrl_setting const *setting)
num_pins = 0;
}
+ /* Try to allocate all pins in this group, one by one */
+ for (i = 0; i < num_pins; i++) {
+ ret = pin_request(pctldev, pins[i], setting->dev_name, NULL);
+ if (ret) {
+ dev_err(pctldev->dev,
+ "could not request pin %d on device %s\n",
+ pins[i], pinctrl_dev_get_name(pctldev));
+ /* On error release all taken pins */
+ i--; /* this pin just failed */
+ for (; i >= 0; i--)
+ pin_free(pctldev, pins[i], NULL);
+ return -ENODEV;
+ }
+ }
+
+ /* Now that we have acquired the pins, encode the mux setting */
for (i = 0; i < num_pins; i++) {
desc = pin_desc_get(pctldev, pins[i]);
if (desc == NULL) {
@@ -482,6 +457,7 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
num_pins = 0;
}
+ /* Flag the descs that no setting is active */
for (i = 0; i < num_pins; i++) {
desc = pin_desc_get(pctldev, pins[i]);
if (desc == NULL) {
@@ -493,6 +469,10 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
desc->mux_setting = NULL;
}
+ /* And release the pins */
+ for (i = 0; i < num_pins; i++)
+ pin_free(pctldev, pins[i], NULL);
+
if (ops->disable)
ops->disable(pctldev, setting->data.mux.func, setting->data.mux.group);
}
--
1.7.11.3
^ permalink raw reply related
* [PATCH] ARM/dts: omap3: Fix mcbsp2/3 hwmods to be able to probe the drivers for audio
From: Benoit Cousson @ 2012-10-18 10:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350552307-10226-1-git-send-email-peter.ujfalusi@ti.com>
On 10/18/2012 11:25 AM, Peter Ujfalusi wrote:
> Fixes the following errors:
> [ 2.318084] omap-mcbsp 49022000.mcbsp: invalid rx DMA channel
> [ 2.324432] omap-mcbsp 49024000.mcbsp: invalid rx DMA channel
>
> Which is because we failed to link the sidetone hwmod for McBSP2/3. The
> missing sidetone hwmod link will prevent omap_device_alloc() to append the
> DMA resources since we - accidentally - end up having the same number of
> resources provided from DT (IO/IRQ) as we have in hwmod for the McBSP ports
> without the ST resources.
>
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Benoit Cousson <b-cousson@ti.com>
Regards,
Benoit
> ---
>
> Hi Tony, Benoit,
>
> Can you please take this patch for 3.7 since if we boot with DT audio will not
> work on BeagleBoard and on boards which uses McBSP2 or 3 for audio.
>
> Thank you,
> Peter
>
> arch/arm/boot/dts/omap3.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
> index f38ea87..696e929 100644
> --- a/arch/arm/boot/dts/omap3.dtsi
> +++ b/arch/arm/boot/dts/omap3.dtsi
> @@ -257,7 +257,7 @@
> interrupt-names = "common", "tx", "rx", "sidetone";
> interrupt-parent = <&intc>;
> ti,buffer-size = <1280>;
> - ti,hwmods = "mcbsp2";
> + ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
> };
>
> mcbsp3: mcbsp at 49024000 {
> @@ -272,7 +272,7 @@
> interrupt-names = "common", "tx", "rx", "sidetone";
> interrupt-parent = <&intc>;
> ti,buffer-size = <128>;
> - ti,hwmods = "mcbsp3";
> + ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
> };
>
> mcbsp4: mcbsp at 49026000 {
>
^ permalink raw reply
* [PATCH V2 3/3] ARM: tegra: move debug-macro.S to include/debug
From: Russell King - ARM Linux @ 2012-10-18 9:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <507F1F31.2060503@wwwdotorg.org>
On Wed, Oct 17, 2012 at 03:12:17PM -0600, Stephen Warren wrote:
> That implies we really do need to keep the two pieces of code completely
> in sync, so a shared header is the right way to go. It also implies that
> having duplicate mappings of the same physical address doesn't cause any
> immediate obvious catastrophic problems.
>
> Ways we might avoid files in arch/arm/include/debug having to use
> relative include paths to pick up that header are:
Why not take the opposite approach. Treat the platform as setting up the
addresses for the UART. Then arrange for the debug macros to match that.
Or we define a common virtual address for debug UARTs (which platforms
would not be able to use).
> b) Rework debug-macro.S so that it isn't an include file, but rather a
> regular top-level file.
No, that won't work. It's used in two places - the kernel and the
decompressor. Hence why it is an include file (it's not an include
file just for the fun of it.)
^ permalink raw reply
* [PATCH v3] ARM: mxs: Add support for the Armadeus Systems APF28 module
From: julien.boibessot at free.fr @ 2012-10-18 9:50 UTC (permalink / raw)
To: linux-arm-kernel
From: Julien Boibessot <julien.boibessot@armadeus.com>
The APF28 is a small SOM built around an i.MX28 processor with 128MBytes DDR2,
256MBytes NAND Flash and an Ethernet PHY.
Signed-off-by: Julien Boibessot <julien.boibessot@armadeus.com>
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
---
Changes since v2 (as advised by Shawn Guo):
* respect alphabetic order in arch/arm/boot/dts/Makefile
Changes since v1 (as advised by Shawn Guo):
* add imx28-apf28.dtb to arch/arm/boot/dts/Makefile
* fix partitions declaration for gpmi-nand in imx28-apf28.dts
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx28-apf28.dts | 85 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-mxs/mach-mxs.c | 7 +++
3 files changed, 93 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/imx28-apf28.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c1ce813..9bca96f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx23-olinuxino.dtb \
imx23-stmp378x_devb.dtb \
+ imx28-apf28.dtb \
imx28-apx4devkit.dtb \
imx28-cfa10036.dtb \
imx28-cfa10049.dtb \
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
new file mode 100644
index 0000000..7eb0758
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2012 Armadeus Systems - <support@armadeus.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+ model = "Armadeus Systems APF28 module";
+ compatible = "armadeus,imx28-apf28", "fsl,imx28";
+
+ memory {
+ reg = <0x40000000 0x08000000>;
+ };
+
+ apb at 80000000 {
+ apbh at 80000000 {
+ gpmi-nand at 8000c000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
+ status = "okay";
+
+ partition at 0 {
+ label = "u-boot";
+ reg = <0x0 0x300000>;
+ };
+
+ partition at 300000 {
+ label = "env";
+ reg = <0x300000 0x80000>;
+ };
+
+ partition at 380000 {
+ label = "env2";
+ reg = <0x380000 0x80000>;
+ };
+
+ partition at 400000 {
+ label = "dtb";
+ reg = <0x400000 0x80000>;
+ };
+
+ partition at 480000 {
+ label = "splash";
+ reg = <0x480000 0x80000>;
+ };
+
+ partition at 500000 {
+ label = "kernel";
+ reg = <0x500000 0x800000>;
+ };
+
+ partition at d00000 {
+ label = "rootfs";
+ reg = <0xd00000 0xf300000>;
+ };
+ };
+ };
+
+ apbx at 80040000 {
+ duart: serial at 80074000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+ };
+ };
+ };
+
+ ahb at 80080000 {
+ mac0: ethernet at 800f0000 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>;
+ phy-reset-gpios = <&gpio4 13 0>;
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index b8c452a..9cfb25c 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -367,6 +367,11 @@ static void __init cfa10049_init(void)
update_fec_mac_prop(OUI_CRYSTALFONTZ);
}
+static void __init apf28_init(void)
+{
+ enable_clk_enet_out();
+}
+
static void __init mxs_machine_init(void)
{
if (of_machine_is_compatible("fsl,imx28-evk"))
@@ -379,6 +384,8 @@ static void __init mxs_machine_init(void)
apx4devkit_init();
else if (of_machine_is_compatible("crystalfontz,cfa10049"))
cfa10049_init();
+ else if (of_machine_is_compatible("armadeus,imx28-apf28"))
+ apf28_init();
of_platform_populate(NULL, of_default_bus_match_table,
mxs_auxdata_lookup, NULL);
--
1.7.5.4
^ permalink raw reply related
* [PATCH 1/1] MTD: atmel_nand: use devm_xxx gpio kzalloc, gpio and ioremap
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-10-18 9:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350552998.5769.306.camel@sauron.fi.intel.com>
On 12:36 Thu 18 Oct , Artem Bityutskiy wrote:
> On Sat, 2012-10-13 at 14:06 +0200, Jean-Christophe PLAGNIOL-VILLARD
> wrote:
> > this will allow to simply the error and remove path
> >
> > Cc: linux-mtd at lists.infradead.org
> > Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>
> $:~/git/l2-mtd$ git apply --check ~/tmp/jc.mbox
> error: patch failed: drivers/mtd/nand/atmel_nand.c:1420
> error: drivers/mtd/nand/atmel_nand.c: patch does not apply
>
> Please, send an l2-mtd.git-based version.
>
> git://git.infradead.org/users/dedekind/l2-mtd-2.6.git
this will have to be merge after pinctrl
it's ok I'll push it via at91
Best Regards,
J.
^ permalink raw reply
* [PATCH 5/9] uprobes: allow arch-specific initialization
From: Srikar Dronamraju @ 2012-10-18 9:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350242593-17761-5-git-send-email-rabin@rab.in>
* Rabin Vincent <rabin@rab.in> [2012-10-14 21:23:09]:
> Add a weak function for any architecture-specific initialization. ARM
> will use this to register the handlers for the undefined instructions it
> uses to implement uprobes.
>
> Signed-off-by: Rabin Vincent <rabin@rab.in>
> ---
> include/linux/uprobes.h | 1 +
> kernel/events/uprobes.c | 10 ++++++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/include/linux/uprobes.h b/include/linux/uprobes.h
> index b4380ad..c3dc5de 100644
> --- a/include/linux/uprobes.h
> +++ b/include/linux/uprobes.h
> @@ -130,6 +130,7 @@ extern int arch_uprobe_exception_notify(struct notifier_block *self, unsigned l
> extern void arch_uprobe_abort_xol(struct arch_uprobe *aup, struct pt_regs *regs);
> extern bool __weak arch_uprobe_ignore(struct arch_uprobe *aup, struct pt_regs *regs);
> extern void __weak arch_uprobe_xol_copy(struct arch_uprobe *auprobe, void *vaddr);
> +extern int __weak arch_uprobes_init(void);
> #else /* !CONFIG_UPROBES */
> struct uprobes_state {
> };
> diff --git a/kernel/events/uprobes.c b/kernel/events/uprobes.c
> index f7ff3a4..ca000a9 100644
> --- a/kernel/events/uprobes.c
> +++ b/kernel/events/uprobes.c
> @@ -1634,8 +1634,14 @@ static struct notifier_block uprobe_exception_nb = {
> .priority = INT_MAX-1, /* notified after kprobes, kgdb */
> };
>
> +int __weak __init arch_uprobes_init(void)
> +{
> + return 0;
> +}
> +
> static int __init init_uprobes(void)
> {
> + int ret;
> int i;
>
> for (i = 0; i < UPROBES_HASH_SZ; i++) {
> @@ -1643,6 +1649,10 @@ static int __init init_uprobes(void)
> mutex_init(&uprobes_mmap_mutex[i]);
> }
>
> + ret = arch_uprobes_init();
> + if (ret)
> + return ret;
> +
> return register_die_notifier(&uprobe_exception_nb);
> }
> module_init(init_uprobes);
> --
We should be able to move the register_die_notifier and
uprobe_exception_nb structure into the default arch_uprobes_init.
Right?
--
thanks and regards
Srikar
^ permalink raw reply
* [PATCH 1/1] arm: KGDB support for PXA
From: Marko Katić @ 2012-10-18 9:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAN1soZwXSrpJCCCok=weJwRtWJHXz5zPQ6jB88UTr1HePU84gw@mail.gmail.com>
I'm still not seeing this patch in arch-pxa, tty or mainline trees.
Has it been forgotten again? Is there a problem with this patch that
needs to be fixed?
^ permalink raw reply
* [PATCH 2/5] ARM: OMAP2+: PRM: split PRM functions into OMAP2, OMAP3-specific files
From: Russ Dill @ 2012-10-18 9:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121015230541.18306.61050.stgit@dusk.lan>
On Mon, Oct 15, 2012 at 4:05 PM, Paul Walmsley <paul@pwsan.com> wrote:
> Move OMAP3xxx-specific PRM functions & macros into prm3xxx.[ch] and
> OMAP2xxx-specific macros into prm2xxx.h. (prm2xxx.c will be created
> by a subsequent patch when it's needed.) Move basic PRM register
> access functions into static inline functions in prm2xxx_3xxx.h, leaving
> only OMAP2/3 hardreset functions in prm2xxx_3xxx.c.
>
> Also clarify the initcall function naming to reinforce that this code
> is specifically for the PRM IP block.
>
> This is in preparation for the upcoming powerdomain series and the
> upcoming move of this code to drivers/.
Hi Paul, thank's for working to get this cleaned up. There are a
couple of places where comments like OMAP2/3 remain in files that are
now just 2xxx or 3xxx, but other than that small nit, things look
good.
Reviewed-by: Russ.Dill at ti.com
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
> arch/arm/mach-omap2/Makefile | 100 +++++++-----
> arch/arm/mach-omap2/control.c | 2
> arch/arm/mach-omap2/omap_hwmod.c | 2
> arch/arm/mach-omap2/pm24xx.c | 2
> arch/arm/mach-omap2/pm34xx.c | 2
> arch/arm/mach-omap2/prm-regbits-24xx.h | 2
> arch/arm/mach-omap2/prm-regbits-34xx.h | 2
> arch/arm/mach-omap2/prm2xxx.h | 122 +++++++++++++++
> arch/arm/mach-omap2/prm2xxx_3xxx.c | 265 --------------------------------
> arch/arm/mach-omap2/prm2xxx_3xxx.h | 256 ++++++-------------------------
> arch/arm/mach-omap2/prm3xxx.c | 164 ++------------------
> arch/arm/mach-omap2/prm3xxx.h | 158 +++++++++++++++++++
> arch/arm/mach-omap2/prm44xx.c | 15 +-
> arch/arm/mach-omap2/sdrc2xxx.c | 2
> arch/arm/mach-omap2/sleep34xx.S | 2
> arch/arm/mach-omap2/sram242x.S | 2
> arch/arm/mach-omap2/sram243x.S | 2
> 17 files changed, 421 insertions(+), 679 deletions(-)
> create mode 100644 arch/arm/mach-omap2/prm2xxx.h
> copy arch/arm/mach-omap2/{prm2xxx_3xxx.c => prm3xxx.c} (57%)
> create mode 100644 arch/arm/mach-omap2/prm3xxx.h
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index fe40d9e..20849604 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -4,30 +4,36 @@
>
> # Common support
> obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
> - common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o
> + common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
>
> -# INTCPS IP block support - XXX should be moved to drivers/
> -obj-$(CONFIG_ARCH_OMAP2) += irq.o
> -obj-$(CONFIG_ARCH_OMAP3) += irq.o
> -obj-$(CONFIG_SOC_AM33XX) += irq.o
> +omap-2-3-common = irq.o
> +hwmod-common = omap_hwmod.o \
> + omap_hwmod_common_data.o
> +clock-common = clock.o clock_common_data.o \
> + clkt_dpll.o clkt_clksel.o
> +secure-common = omap-smc.o omap-secure.o
>
> -# Secure monitor API support
> -obj-$(CONFIG_ARCH_OMAP3) += omap-smc.o omap-secure.o
> -obj-$(CONFIG_ARCH_OMAP4) += omap-smc.o omap-secure.o
> -obj-$(CONFIG_SOC_OMAP5) += omap-smc.o omap-secure.o
> +obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
> +obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
> +obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
> +obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
> +obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
>
> ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
> obj-y += mcbsp.o
> endif
>
> -obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
> +obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
> +obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
>
> # SMP support ONLY available for OMAP4
>
> obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
> obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
> -obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o
> -obj-$(CONFIG_SOC_OMAP5) += omap4-common.o omap-wakeupgen.o
> +omap-4-5-common = omap4-common.o omap-wakeupgen.o \
> + sleep44xx.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
> +obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common)
>
> plus_sec := $(call as-instr,.arch_extension sec,+sec)
> AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
> @@ -52,7 +58,6 @@ obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
> # SMS/SDRC
> obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
> # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
> -obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
>
> # OPP table initialization
> ifeq ($(CONFIG_PM_OPP),y)
> @@ -63,15 +68,15 @@ endif
>
> # Power Management
> ifeq ($(CONFIG_PM),y)
> -obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o sleep24xx.o
> +obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
> +obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
> obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
> obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
> -obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o
> -obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o sleep44xx.o
> +obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
> obj-$(CONFIG_PM_DEBUG) += pm-debug.o
>
> obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
> -obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
> +obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
>
> AFLAGS_sleep24xx.o :=-Wa,-march=armv6
> AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
> @@ -83,76 +88,88 @@ endif
> endif
>
> ifeq ($(CONFIG_CPU_IDLE),y)
> -obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
> -obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
> +obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
> +obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
> endif
>
> # PRCM
> obj-y += prcm.o prm_common.o
> obj-$(CONFIG_ARCH_OMAP2) += cm2xxx_3xxx.o prm2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += cm2xxx_3xxx.o prm2xxx_3xxx.o
> +obj-$(CONFIG_ARCH_OMAP3) += prm3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
> obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
> omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
> prcm_mpu44xx.o prminst44xx.o \
> - vc44xx_data.o vp44xx_data.o \
> - prm44xx.o
> + vc44xx_data.o vp44xx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
> obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
>
> # OMAP voltage domains
> -obj-y += voltage.o vc.o vp.o
> +voltagedomain-common := voltage.o vc.o vp.o
> +obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
> obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o
> +obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
> obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
> obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
> -obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
> +obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
> +obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
> +obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
>
> # OMAP powerdomain framework
> -obj-y += powerdomain.o powerdomain-common.o
> +powerdomain-common += powerdomain.o powerdomain-common.o
> +obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common)
> obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP2) += powerdomain2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP3) += powerdomain2xxx_3xxx.o
> +obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common)
> obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
> obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
> -obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o
> +obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
> obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
> -obj-$(CONFIG_SOC_OMAP5) += powerdomain44xx.o
> +obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
>
> # PRCM clockdomain control
> -obj-y += clockdomain.o
> +clockdomain-common += clockdomain.o
> +obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common)
> obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o
> obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
> obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
> +obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common)
> obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
> obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
> obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
> +obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
> obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o
> obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
> +obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
> obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o
>
> # Clock framework
> -obj-y += clock.o clock_common_data.o \
> - clkt_dpll.o clkt_clksel.o
> -obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o
> -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o clkt2xxx_sys.o
> +obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
> +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o
> +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
> obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
> obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o
> obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
> obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o
> obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o
> -obj-$(CONFIG_ARCH_OMAP3) += clock3xxx.o
> +obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
> -obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o clkt_iclk.o
> +obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
> obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP4) += clock44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
> -obj-$(CONFIG_SOC_AM33XX) += dpll3xxx.o clock33xx_data.o
> +obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
> +obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o
> +obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
> obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
>
> # OMAP2 clock rate set data (old "OPP" data)
> @@ -160,7 +177,6 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
> obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
>
> # hwmod data
> -obj-y += omap_hwmod_common_data.o
> obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
> obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
> obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
> @@ -206,10 +222,10 @@ obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
> obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
> obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
> obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
> -obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o
> +obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o
> obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
> -obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o
> -obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o
> +obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o
> +obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o
> obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o
> obj-$(CONFIG_MACH_OVERO) += board-overo.o
> obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index d1ff839..1220e0e 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -22,7 +22,7 @@
> #include "common.h"
> #include "cm-regbits-34xx.h"
> #include "prm-regbits-34xx.h"
> -#include "prm2xxx_3xxx.h"
> +#include "prm3xxx.h"
> #include "cm2xxx_3xxx.h"
> #include "sdrc.h"
> #include "pm.h"
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index b969ab1..525c58d 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -150,7 +150,7 @@
> #include "cm2xxx_3xxx.h"
> #include "cminst44xx.h"
> #include "cm33xx.h"
> -#include "prm2xxx_3xxx.h"
> +#include "prm3xxx.h"
> #include "prm44xx.h"
> #include "prm33xx.h"
> #include "prminst44xx.h"
> diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
> index 8af6cd6..78405a7 100644
> --- a/arch/arm/mach-omap2/pm24xx.c
> +++ b/arch/arm/mach-omap2/pm24xx.c
> @@ -41,7 +41,7 @@
> #include <plat/dma.h>
>
> #include "common.h"
> -#include "prm2xxx_3xxx.h"
> +#include "prm2xxx.h"
> #include "prm-regbits-24xx.h"
> #include "cm2xxx_3xxx.h"
> #include "cm-regbits-24xx.h"
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index ba670db..c02c9ca 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -48,7 +48,7 @@
> #include "cm-regbits-34xx.h"
> #include "prm-regbits-34xx.h"
>
> -#include "prm2xxx_3xxx.h"
> +#include "prm3xxx.h"
> #include "pm.h"
> #include "sdrc.h"
> #include "control.h"
> diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
> index 6ac9661..bd70a5a 100644
> --- a/arch/arm/mach-omap2/prm-regbits-24xx.h
> +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
> @@ -14,7 +14,7 @@
> * published by the Free Software Foundation.
> */
>
> -#include "prm2xxx_3xxx.h"
> +#include "prm2xxx.h"
>
> /* Bits shared between registers */
>
> diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
> index 64c087a..073d4db 100644
> --- a/arch/arm/mach-omap2/prm-regbits-34xx.h
> +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
> @@ -14,7 +14,7 @@
> #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
>
>
> -#include "prm2xxx_3xxx.h"
> +#include "prm3xxx.h"
>
> /* Shared register bits */
>
> diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
> new file mode 100644
> index 0000000..6490e1a
> --- /dev/null
> +++ b/arch/arm/mach-omap2/prm2xxx.h
> @@ -0,0 +1,122 @@
> +/*
> + * OMAP2xxx Power/Reset Management (PRM) register definitions
> + *
> + * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
> + * Copyright (C) 2008-2010 Nokia Corporation
> + * Paul Walmsley
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * The PRM hardware modules on the OMAP2/3 are quite similar to each
> + * other. The PRM on OMAP4 has a new register layout, and is handled
> + * in a separate file.
> + */
Still a few rouge omap3 references around.
> +#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
> +#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
> +
> +#include "prcm-common.h"
> +#include "prm.h"
> +#include "prm2xxx_3xxx.h"
> +
> +#define OMAP2420_PRM_REGADDR(module, reg) \
> + OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
> +#define OMAP2430_PRM_REGADDR(module, reg) \
> + OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
> +
> +/*
> + * OMAP2-specific global PRM registers
> + * Use __raw_{read,write}l() with these registers.
> + *
> + * With a few exceptions, these are the register names beginning with
> + * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
> + * bits.)
> + *
> + */
> +
> +#define OMAP2_PRCM_REVISION_OFFSET 0x0000
> +#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
> +#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
> +#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
> +
> +#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
> +#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
> +#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
> +#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
> +
> +#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
> +#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
> +#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
> +#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
> +#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
> +#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
> +#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
> +#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
> +#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
> +#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
> +#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
> +#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
> +#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
> +#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
> +#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
> +#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
> +#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
> +#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
> +#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
> +#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
> +
> +#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
> +#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
> +
> +#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
> +#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
> +
> +#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
> +#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
> +#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
> +#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
> +#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
> +#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
> +#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
> +#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
> +#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
> +#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
> +
> +/*
> + * Module specific PRM register offsets from PRM_BASE + domain offset
> + *
> + * Use prm_{read,write}_mod_reg() with these registers.
> + *
> + * With a few exceptions, these are the register names beginning with
> + * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the
> + * IRQSTATUS and IRQENABLE bits.)
> + */
> +
> +/* Register offsets appearing on both OMAP2 and OMAP3 */
> +
> +#define OMAP2_RM_RSTCTRL 0x0050
> +#define OMAP2_RM_RSTTIME 0x0054
> +#define OMAP2_RM_RSTST 0x0058
> +#define OMAP2_PM_PWSTCTRL 0x00e0
> +#define OMAP2_PM_PWSTST 0x00e4
> +
> +#define PM_WKEN 0x00a0
> +#define PM_WKEN1 PM_WKEN
> +#define PM_WKST 0x00b0
> +#define PM_WKST1 PM_WKST
> +#define PM_WKDEP 0x00c8
> +#define PM_EVGENCTRL 0x00d4
> +#define PM_EVGENONTIM 0x00d8
> +#define PM_EVGENOFFTIM 0x00dc
> +
> +/* OMAP2xxx specific register offsets */
> +#define OMAP24XX_PM_WKEN2 0x00a4
> +#define OMAP24XX_PM_WKST2 0x00b4
> +
> +#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
> +#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
> +#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
> +#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
> +
> +#endif
> diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> index 9529984..0d6cc54 100644
> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
> +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> @@ -15,82 +15,11 @@
> #include <linux/errno.h>
> #include <linux/err.h>
> #include <linux/io.h>
> -#include <linux/irq.h>
>
> -#include <plat/prcm.h>
> -
> -#include "soc.h"
> #include "common.h"
> -#include "vp.h"
>
> #include "prm2xxx_3xxx.h"
> -#include "cm2xxx_3xxx.h"
> #include "prm-regbits-24xx.h"
> -#include "prm-regbits-34xx.h"
> -
> -static const struct omap_prcm_irq omap3_prcm_irqs[] = {
> - OMAP_PRCM_IRQ("wkup", 0, 0),
> - OMAP_PRCM_IRQ("io", 9, 1),
> -};
> -
> -static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
> - .ack = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
> - .mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
> - .nr_regs = 1,
> - .irqs = omap3_prcm_irqs,
> - .nr_irqs = ARRAY_SIZE(omap3_prcm_irqs),
> - .irq = 11 + OMAP_INTC_START,
> - .read_pending_irqs = &omap3xxx_prm_read_pending_irqs,
> - .ocp_barrier = &omap3xxx_prm_ocp_barrier,
> - .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen,
> - .restore_irqen = &omap3xxx_prm_restore_irqen,
> -};
> -
> -u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
> -{
> - return __raw_readl(prm_base + module + idx);
> -}
> -
> -void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
> -{
> - __raw_writel(val, prm_base + module + idx);
> -}
> -
> -/* Read-modify-write a register in a PRM module. Caller must lock */
> -u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
> -{
> - u32 v;
> -
> - v = omap2_prm_read_mod_reg(module, idx);
> - v &= ~mask;
> - v |= bits;
> - omap2_prm_write_mod_reg(v, module, idx);
> -
> - return v;
> -}
> -
> -/* Read a PRM register, AND it, and shift the result down to bit 0 */
> -u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
> -{
> - u32 v;
> -
> - v = omap2_prm_read_mod_reg(domain, idx);
> - v &= mask;
> - v >>= __ffs(mask);
> -
> - return v;
> -}
> -
> -u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
> -{
> - return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
> -}
> -
> -u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
> -{
> - return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
> -}
> -
>
> /**
> * omap2_prm_is_hardreset_asserted - read the HW reset line state of
> @@ -104,9 +33,6 @@ u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
> */
> int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
> {
> - if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
> - return -EINVAL;
> -
> return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
> (1 << shift));
> }
> @@ -127,9 +53,6 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
> {
> u32 mask;
>
> - if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
> - return -EINVAL;
> -
> mask = 1 << shift;
> omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
>
> @@ -156,9 +79,6 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
> u32 rst, st;
> int c;
>
> - if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
> - return -EINVAL;
> -
> rst = 1 << rst_shift;
> st = 1 << st_shift;
>
> @@ -178,188 +98,3 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
> return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
> }
>
> -/* PRM VP */
> -
> -/*
> - * struct omap3_vp - OMAP3 VP register access description.
> - * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
> - */
> -struct omap3_vp {
> - u32 tranxdone_status;
> -};
> -
> -static struct omap3_vp omap3_vp[] = {
> - [OMAP3_VP_VDD_MPU_ID] = {
> - .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
> - },
> - [OMAP3_VP_VDD_CORE_ID] = {
> - .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
> - },
> -};
> -
> -#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
> -
> -u32 omap3_prm_vp_check_txdone(u8 vp_id)
> -{
> - struct omap3_vp *vp = &omap3_vp[vp_id];
> - u32 irqstatus;
> -
> - irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
> - OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
> - return irqstatus & vp->tranxdone_status;
> -}
> -
> -void omap3_prm_vp_clear_txdone(u8 vp_id)
> -{
> - struct omap3_vp *vp = &omap3_vp[vp_id];
> -
> - omap2_prm_write_mod_reg(vp->tranxdone_status,
> - OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
> -}
> -
> -u32 omap3_prm_vcvp_read(u8 offset)
> -{
> - return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
> -}
> -
> -void omap3_prm_vcvp_write(u32 val, u8 offset)
> -{
> - omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
> -}
> -
> -u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
> -{
> - return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
> -}
> -
> -/**
> - * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
> - * @events: ptr to a u32, preallocated by caller
> - *
> - * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
> - * MPU IRQs, and store the result into the u32 pointed to by @events.
> - * No return value.
> - */
> -void omap3xxx_prm_read_pending_irqs(unsigned long *events)
> -{
> - u32 mask, st;
> -
> - /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
> - mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
> - st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
> -
> - events[0] = mask & st;
> -}
> -
> -/**
> - * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
> - *
> - * Force any buffered writes to the PRM IP block to complete. Needed
> - * by the PRM IRQ handler, which reads and writes directly to the IP
> - * block, to avoid race conditions after acknowledging or clearing IRQ
> - * bits. No return value.
> - */
> -void omap3xxx_prm_ocp_barrier(void)
> -{
> - omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
> -}
> -
> -/**
> - * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
> - * @saved_mask: ptr to a u32 array to save IRQENABLE bits
> - *
> - * Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask
> - * must be allocated by the caller. Intended to be used in the PRM
> - * interrupt handler suspend callback. The OCP barrier is needed to
> - * ensure the write to disable PRM interrupts reaches the PRM before
> - * returning; otherwise, spurious interrupts might occur. No return
> - * value.
> - */
> -void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
> -{
> - saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
> - OMAP3_PRM_IRQENABLE_MPU_OFFSET);
> - omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
> -
> - /* OCP barrier */
> - omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
> -}
> -
> -/**
> - * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
> - * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
> - *
> - * Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended
> - * to be used in the PRM interrupt handler resume callback to restore
> - * values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP
> - * barrier should be needed here; any pending PRM interrupts will fire
> - * once the writes reach the PRM. No return value.
> - */
> -void omap3xxx_prm_restore_irqen(u32 *saved_mask)
> -{
> - omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
> - OMAP3_PRM_IRQENABLE_MPU_OFFSET);
> -}
> -
> -/**
> - * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
> - *
> - * Clear any previously-latched I/O wakeup events and ensure that the
> - * I/O wakeup gates are aligned with the current mux settings. Works
> - * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
> - * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No
> - * return value.
> - */
> -void omap3xxx_prm_reconfigure_io_chain(void)
> -{
> - int i = 0;
> -
> - omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> - PM_WKEN);
> -
> - omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
> - OMAP3430_ST_IO_CHAIN_MASK,
> - MAX_IOPAD_LATCH_TIME, i);
> - if (i == MAX_IOPAD_LATCH_TIME)
> - pr_warn("PRM: I/O chain clock line assertion timed out\n");
> -
> - omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> - PM_WKEN);
> -
> - omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
> - PM_WKST);
> -
> - omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
> -}
> -
> -/**
> - * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
> - *
> - * Activates the I/O wakeup event latches and allows events logged by
> - * those latches to signal a wakeup event to the PRCM. For I/O
> - * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
> - * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
> - * No return value.
> - */
> -static void __init omap3xxx_prm_enable_io_wakeup(void)
> -{
> - if (omap3_has_io_wakeup())
> - omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
> - PM_WKEN);
> -}
> -
> -static int __init omap3xxx_prcm_init(void)
> -{
> - int ret = 0;
> -
> - if (cpu_is_omap34xx()) {
> - omap3xxx_prm_enable_io_wakeup();
> - ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
> - if (!ret)
> - irq_set_status_flags(omap_prcm_event_to_irq("io"),
> - IRQ_NOAUTOEN);
> - }
> -
> - return ret;
> -}
> -subsys_initcall(omap3xxx_prcm_init);
> diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
> index c19d249..8d09a1a 100644
> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
> +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
> @@ -1,7 +1,7 @@
> /*
> - * OMAP2/3 Power/Reset Management (PRM) register definitions
> + * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
> *
> - * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
> + * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
> * Copyright (C) 2008-2010 Nokia Corporation
> * Paul Walmsley
> *
> @@ -19,160 +19,6 @@
> #include "prcm-common.h"
> #include "prm.h"
>
> -#define OMAP2420_PRM_REGADDR(module, reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
> -#define OMAP2430_PRM_REGADDR(module, reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
> -#define OMAP34XX_PRM_REGADDR(module, reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
> -
> -
> -/*
> - * OMAP2-specific global PRM registers
> - * Use __raw_{read,write}l() with these registers.
> - *
> - * With a few exceptions, these are the register names beginning with
> - * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
> - * bits.)
> - *
> - */
> -
> -#define OMAP2_PRCM_REVISION_OFFSET 0x0000
> -#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
> -#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
> -#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
> -
> -#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
> -#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
> -#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
> -#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
> -
> -#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
> -#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
> -#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
> -#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
> -#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
> -#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
> -#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
> -#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
> -#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
> -#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
> -#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
> -#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
> -#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
> -#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
> -#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
> -#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
> -#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
> -#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
> -#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
> -#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
> -
> -#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
> -#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
> -
> -#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
> -#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
> -
> -#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
> -#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
> -#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
> -#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
> -#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
> -#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
> -#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
> -#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
> -#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
> -#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
> -
> -/*
> - * OMAP3-specific global PRM registers
> - * Use __raw_{read,write}l() with these registers.
> - *
> - * With a few exceptions, these are the register names beginning with
> - * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE
> - * bits.)
> - */
> -
> -#define OMAP3_PRM_REVISION_OFFSET 0x0004
> -#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
> -#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
> -#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
> -
> -#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
> -#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
> -#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
> -#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
> -
> -
> -#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
> -#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
> -#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
> -#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
> -#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
> -#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
> -#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
> -#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
> -#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
> -#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
> -#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
> -#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
> -#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
> -#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
> -#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
> -#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
> -#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
> -#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
> -#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
> -#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
> -#define OMAP3_PRM_RSTST_OFFSET 0x0058
> -#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
> -#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
> -#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
> -#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
> -#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
> -#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
> -#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
> -#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
> -#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
> -#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
> -#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
> -#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
> -#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
> -#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
> -#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
> -#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
> -#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
> -#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
> -#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
> -#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
> -#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
> -#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
> -#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
> -#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
> -#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
> -#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
> -#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
> -#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
> -#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
> -#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
> -#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
> -#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
> -#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
> -#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
> -#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
> -#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
> -#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
> -#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
> -#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
> -#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
> -#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
> -
> -#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
> -#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
> -#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
> -#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
> -
> /*
> * Module specific PRM register offsets from PRM_BASE + domain offset
> *
> @@ -200,67 +46,63 @@
> #define PM_EVGENONTIM 0x00d8
> #define PM_EVGENOFFTIM 0x00dc
>
> -/* OMAP2xxx specific register offsets */
> -#define OMAP24XX_PM_WKEN2 0x00a4
> -#define OMAP24XX_PM_WKST2 0x00b4
> -
> -#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
> -#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
> -#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
> -#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
> -
> -/* OMAP3 specific register offsets */
> -#define OMAP3430ES2_PM_WKEN3 0x00f0
> -#define OMAP3430ES2_PM_WKST3 0x00b8
> -
> -#define OMAP3430_PM_MPUGRPSEL 0x00a4
> -#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
> -#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
>
> -#define OMAP3430_PM_IVAGRPSEL 0x00a8
> -#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
> -#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
> -
> -#define OMAP3430_PM_PREPWSTST 0x00e8
> -
> -#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
> -#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
> +#ifndef __ASSEMBLER__
>
> +#include <linux/io.h>
>
> -#ifndef __ASSEMBLER__
> /* Power/reset management domain register get/set */
> -extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
> -extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
> -extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
> -extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
> -extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
> -extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
> +static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
> +{
> + return __raw_readl(prm_base + module + idx);
> +}
> +
> +static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
> +{
> + __raw_writel(val, prm_base + module + idx);
> +}
> +
> +/* Read-modify-write a register in a PRM module. Caller must lock */
> +static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
> + s16 idx)
> +{
> + u32 v;
> +
> + v = omap2_prm_read_mod_reg(module, idx);
> + v &= ~mask;
> + v |= bits;
> + omap2_prm_write_mod_reg(v, module, idx);
> +
> + return v;
> +}
> +
> +/* Read a PRM register, AND it, and shift the result down to bit 0 */
> +static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
> +{
> + u32 v;
> +
> + v = omap2_prm_read_mod_reg(domain, idx);
> + v &= mask;
> + v >>= __ffs(mask);
> +
> + return v;
> +}
> +
> +static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
> +{
> + return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
> +}
> +
> +static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
> +{
> + return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
> +}
>
> /* These omap2_ PRM functions apply to both OMAP2 and 3 */
> extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
> extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
> extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
>
> -/* OMAP3-specific VP functions */
> -u32 omap3_prm_vp_check_txdone(u8 vp_id);
> -void omap3_prm_vp_clear_txdone(u8 vp_id);
> -
> -/*
> - * OMAP3 access functions for voltage controller (VC) and
> - * voltage proccessor (VP) in the PRM.
> - */
> -extern u32 omap3_prm_vcvp_read(u8 offset);
> -extern void omap3_prm_vcvp_write(u32 val, u8 offset);
> -extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
> -
> -extern void omap3xxx_prm_reconfigure_io_chain(void);
> -
> -/* PRM interrupt-related functions */
> -extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
> -extern void omap3xxx_prm_ocp_barrier(void);
> -extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
> -extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
> -
> #endif /* __ASSEMBLER */
>
> /*
> diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
> similarity index 57%
> copy from arch/arm/mach-omap2/prm2xxx_3xxx.c
> copy to arch/arm/mach-omap2/prm3xxx.c
> index 9529984..88f7d8d 100644
> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
> +++ b/arch/arm/mach-omap2/prm3xxx.c
> @@ -1,7 +1,7 @@
> /*
> - * OMAP2/3 PRM module functions
> + * OMAP3xxx PRM module functions
> *
> - * Copyright (C) 2010-2011 Texas Instruments, Inc.
> + * Copyright (C) 2010-2012 Texas Instruments, Inc.
> * Copyright (C) 2010 Nokia Corporation
> * Beno?t Cousson
> * Paul Walmsley
> @@ -17,15 +17,14 @@
> #include <linux/io.h>
> #include <linux/irq.h>
>
> +#include "common.h"
> +#include <plat/cpu.h>
> #include <plat/prcm.h>
>
> -#include "soc.h"
> -#include "common.h"
> #include "vp.h"
>
> -#include "prm2xxx_3xxx.h"
> +#include "prm3xxx.h"
> #include "cm2xxx_3xxx.h"
> -#include "prm-regbits-24xx.h"
> #include "prm-regbits-34xx.h"
>
> static const struct omap_prcm_irq omap3_prcm_irqs[] = {
> @@ -46,138 +45,6 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
> .restore_irqen = &omap3xxx_prm_restore_irqen,
> };
>
> -u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
> -{
> - return __raw_readl(prm_base + module + idx);
> -}
> -
> -void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
> -{
> - __raw_writel(val, prm_base + module + idx);
> -}
> -
> -/* Read-modify-write a register in a PRM module. Caller must lock */
> -u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
> -{
> - u32 v;
> -
> - v = omap2_prm_read_mod_reg(module, idx);
> - v &= ~mask;
> - v |= bits;
> - omap2_prm_write_mod_reg(v, module, idx);
> -
> - return v;
> -}
> -
> -/* Read a PRM register, AND it, and shift the result down to bit 0 */
> -u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
> -{
> - u32 v;
> -
> - v = omap2_prm_read_mod_reg(domain, idx);
> - v &= mask;
> - v >>= __ffs(mask);
> -
> - return v;
> -}
> -
> -u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
> -{
> - return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
> -}
> -
> -u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
> -{
> - return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
> -}
> -
> -
> -/**
> - * omap2_prm_is_hardreset_asserted - read the HW reset line state of
> - * submodules contained in the hwmod module
> - * @prm_mod: PRM submodule base (e.g. CORE_MOD)
> - * @shift: register bit shift corresponding to the reset line to check
> - *
> - * Returns 1 if the (sub)module hardreset line is currently asserted,
> - * 0 if the (sub)module hardreset line is not currently asserted, or
> - * -EINVAL if called while running on a non-OMAP2/3 chip.
> - */
> -int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
> -{
> - if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
> - return -EINVAL;
> -
> - return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
> - (1 << shift));
> -}
> -
> -/**
> - * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
> - * @prm_mod: PRM submodule base (e.g. CORE_MOD)
> - * @shift: register bit shift corresponding to the reset line to assert
> - *
> - * Some IPs like dsp or iva contain processors that require an HW
> - * reset line to be asserted / deasserted in order to fully enable the
> - * IP. These modules may have multiple hard-reset lines that reset
> - * different 'submodules' inside the IP block. This function will
> - * place the submodule into reset. Returns 0 upon success or -EINVAL
> - * upon an argument error.
> - */
> -int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
> -{
> - u32 mask;
> -
> - if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
> - return -EINVAL;
> -
> - mask = 1 << shift;
> - omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
> -
> - return 0;
> -}
> -
> -/**
> - * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
> - * @prm_mod: PRM submodule base (e.g. CORE_MOD)
> - * @rst_shift: register bit shift corresponding to the reset line to deassert
> - * @st_shift: register bit shift for the status of the deasserted submodule
> - *
> - * Some IPs like dsp or iva contain processors that require an HW
> - * reset line to be asserted / deasserted in order to fully enable the
> - * IP. These modules may have multiple hard-reset lines that reset
> - * different 'submodules' inside the IP block. This function will
> - * take the submodule out of reset and wait until the PRCM indicates
> - * that the reset has completed before returning. Returns 0 upon success or
> - * -EINVAL upon an argument error, -EEXIST if the submodule was already out
> - * of reset, or -EBUSY if the submodule did not exit reset promptly.
> - */
> -int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
> -{
> - u32 rst, st;
> - int c;
> -
> - if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
> - return -EINVAL;
> -
> - rst = 1 << rst_shift;
> - st = 1 << st_shift;
> -
> - /* Check the current status to avoid de-asserting the line twice */
> - if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
> - return -EEXIST;
> -
> - /* Clear the reset status by writing 1 to the status bit */
> - omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
> - /* de-assert the reset control line */
> - omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
> - /* wait the status to be set */
> - omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
> - st),
> - MAX_MODULE_HARDRESET_WAIT, c);
> -
> - return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
> -}
> -
> /* PRM VP */
>
> /*
> @@ -348,18 +215,19 @@ static void __init omap3xxx_prm_enable_io_wakeup(void)
> PM_WKEN);
> }
>
> -static int __init omap3xxx_prcm_init(void)
> +static int __init omap3xxx_prm_init(void)
> {
> - int ret = 0;
> + int ret;
> +
> + if (!cpu_is_omap34xx())
> + return 0;
>
> - if (cpu_is_omap34xx()) {
> - omap3xxx_prm_enable_io_wakeup();
> - ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
> - if (!ret)
> - irq_set_status_flags(omap_prcm_event_to_irq("io"),
> - IRQ_NOAUTOEN);
> - }
> + omap3xxx_prm_enable_io_wakeup();
> + ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
> + if (!ret)
> + irq_set_status_flags(omap_prcm_event_to_irq("io"),
> + IRQ_NOAUTOEN);
>
> return ret;
> }
> -subsys_initcall(omap3xxx_prcm_init);
> +subsys_initcall(omap3xxx_prm_init);
> diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
> new file mode 100644
> index 0000000..6821e83
> --- /dev/null
> +++ b/arch/arm/mach-omap2/prm3xxx.h
> @@ -0,0 +1,158 @@
> +/*
> + * OMAP3xxx Power/Reset Management (PRM) register definitions
> + *
> + * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
> + * Copyright (C) 2008-2010 Nokia Corporation
> + * Paul Walmsley
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * The PRM hardware modules on the OMAP2/3 are quite similar to each
> + * other. The PRM on OMAP4 has a new register layout, and is handled
> + * in a separate file.
> + */
> +#ifndef __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
> +#define __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
> +
> +#include "prcm-common.h"
> +#include "prm.h"
> +#include "prm2xxx_3xxx.h"
> +
> +#define OMAP34XX_PRM_REGADDR(module, reg) \
> + OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
> +
> +
> +/*
> + * OMAP3-specific global PRM registers
> + * Use __raw_{read,write}l() with these registers.
> + *
> + * With a few exceptions, these are the register names beginning with
> + * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE
> + * bits.)
> + */
> +
> +#define OMAP3_PRM_REVISION_OFFSET 0x0004
> +#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
> +#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
> +#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
> +
> +#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
> +#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
> +#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
> +#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
> +
> +
> +#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
> +#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
> +#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
> +#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
> +#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
> +#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
> +#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
> +#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
> +#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
> +#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
> +#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
> +#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
> +#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
> +#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
> +#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
> +#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
> +#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
> +#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
> +#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
> +#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
> +#define OMAP3_PRM_RSTST_OFFSET 0x0058
> +#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
> +#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
> +#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
> +#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
> +#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
> +#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
> +#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
> +#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
> +#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
> +#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
> +#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
> +#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
> +#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
> +#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
> +#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
> +#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
> +#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
> +#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
> +#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
> +#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
> +#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
> +#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
> +#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
> +#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
> +#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
> +#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
> +#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
> +#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
> +#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
> +#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
> +#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
> +#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
> +#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
> +#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
> +#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
> +#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
> +#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
> +#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
> +#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
> +#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
> +#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
> +
> +#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
> +#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
> +#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
> +#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
> +
> +/* OMAP3 specific register offsets */
> +#define OMAP3430ES2_PM_WKEN3 0x00f0
> +#define OMAP3430ES2_PM_WKST3 0x00b8
> +
> +#define OMAP3430_PM_MPUGRPSEL 0x00a4
> +#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
> +#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
> +
> +#define OMAP3430_PM_IVAGRPSEL 0x00a8
> +#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
> +#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
> +
> +#define OMAP3430_PM_PREPWSTST 0x00e8
> +
> +#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
> +#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
> +
> +
> +#ifndef __ASSEMBLER__
> +
> +/* OMAP3-specific VP functions */
> +u32 omap3_prm_vp_check_txdone(u8 vp_id);
> +void omap3_prm_vp_clear_txdone(u8 vp_id);
> +
> +/*
> + * OMAP3 access functions for voltage controller (VC) and
> + * voltage proccessor (VP) in the PRM.
> + */
> +extern u32 omap3_prm_vcvp_read(u8 offset);
> +extern void omap3_prm_vcvp_write(u32 val, u8 offset);
> +extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
> +
> +extern void omap3xxx_prm_reconfigure_io_chain(void);
> +
> +/* PRM interrupt-related functions */
> +extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
> +extern void omap3xxx_prm_ocp_barrier(void);
> +extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
> +extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
> +
> +#endif /* __ASSEMBLER */
> +
> +
> +#endif
> diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
> index f0c4d5f..06bb679 100644
> --- a/arch/arm/mach-omap2/prm44xx.c
> +++ b/arch/arm/mach-omap2/prm44xx.c
> @@ -291,12 +291,13 @@ static void __init omap44xx_prm_enable_io_wakeup(void)
> OMAP4_PRM_IO_PMCTRL_OFFSET);
> }
>
> -static int __init omap4xxx_prcm_init(void)
> +static int __init omap4xxx_prm_init(void)
> {
> - if (cpu_is_omap44xx()) {
> - omap44xx_prm_enable_io_wakeup();
> - return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
> - }
> - return 0;
> + if (!cpu_is_omap44xx())
> + return 0;
> +
> + omap44xx_prm_enable_io_wakeup();
> +
> + return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
> }
> -subsys_initcall(omap4xxx_prcm_init);
> +subsys_initcall(omap4xxx_prm_init);
> diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
> index 73e55e4..9abd6e2 100644
> --- a/arch/arm/mach-omap2/sdrc2xxx.c
> +++ b/arch/arm/mach-omap2/sdrc2xxx.c
> @@ -31,7 +31,7 @@
> #include "soc.h"
> #include "iomap.h"
> #include "common.h"
> -#include "prm2xxx_3xxx.h"
> +#include "prm2xxx.h"
> #include "clock.h"
> #include "sdrc.h"
>
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 5069879..d83b918 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -31,7 +31,7 @@
> #include "omap34xx.h"
> #include "iomap.h"
> #include "cm2xxx_3xxx.h"
> -#include "prm2xxx_3xxx.h"
> +#include "prm3xxx.h"
> #include "sdrc.h"
> #include "control.h"
>
> diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
> index 8f7326c..c720443 100644
> --- a/arch/arm/mach-omap2/sram242x.S
> +++ b/arch/arm/mach-omap2/sram242x.S
> @@ -34,7 +34,7 @@
>
> #include "soc.h"
> #include "iomap.h"
> -#include "prm2xxx_3xxx.h"
> +#include "prm2xxx.h"
> #include "cm2xxx_3xxx.h"
> #include "sdrc.h"
>
> diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
> index b140d65..cfdc0bc 100644
> --- a/arch/arm/mach-omap2/sram243x.S
> +++ b/arch/arm/mach-omap2/sram243x.S
> @@ -34,7 +34,7 @@
>
> #include "soc.h"
> #include "iomap.h"
> -#include "prm2xxx_3xxx.h"
> +#include "prm2xxx.h"
> #include "cm2xxx_3xxx.h"
> #include "sdrc.h"
>
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 1/1] MTD: atmel_nand: use devm_xxx gpio kzalloc, gpio and ioremap
From: Artem Bityutskiy @ 2012-10-18 9:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350129982-12106-1-git-send-email-plagnioj@jcrosoft.com>
On Sat, 2012-10-13 at 14:06 +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:
> this will allow to simply the error and remove path
>
> Cc: linux-mtd at lists.infradead.org
> Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
$:~/git/l2-mtd$ git apply --check ~/tmp/jc.mbox
error: patch failed: drivers/mtd/nand/atmel_nand.c:1420
error: drivers/mtd/nand/atmel_nand.c: patch does not apply
Please, send an l2-mtd.git-based version.
git://git.infradead.org/users/dedekind/l2-mtd-2.6.git
--
Best Regards,
Artem Bityutskiy
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^ permalink raw reply
* [PATCH] dma: add new DMA control commands
From: Jassi Brar @ 2012-10-18 9:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <507FA595.4020507@freescale.com>
On 18 October 2012 12:15, Huang Shijie <b32955@freescale.com> wrote:
> ? 2012?10?18? 14:18, Vinod Koul ??:
>
>> Why cant you do start (prepare clock etc) when you submit the descriptor
>> to dmaengine. Can be done in tx_submit callback.
>> Similarly remove the clock when dma transaction gets completed.
>
> I ever thought this method too.
>
> But it will become low efficient in the following case:
>
> Assuming the gpmi-nand driver has to read out 1024 pages in one _SINGLE_
> read operation.
> The gpmi-nand will submit the descriptor to dmaengine per page. So with your
> method,
> the system will repeat the enable/disable dma clock 1024 time. At every
> enable/disable dma clock,
> the system has to enable the clock chain and it's parents ...
>
> But with this patch, we only need to enable/disable dma clock one time, just
> at we select the nand chip.
>
If the clock is the dmac's property (not channels'), the toggling
seems too aggressive.
You could try using runtime_suspend/resume for clock
disabling/enabling. How about employing autosuspend with a few ms
delay?
^ permalink raw reply
* pxa:spitz_pm.c: commit b6eede11 breaks spitz resume under certain conditions.
From: Marko Katić @ 2012-10-18 9:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHod+Gd=aLbntWsX_S_26_XSUtG9DQYkki1Y+drq0+8GdnHfaw@mail.gmail.com>
> Almost there, but I guess we could do this better and less confusing by having
> another array, e.g. tosa_gpio18_config[], which is tosa specific, and only
> initialize that MFP setting in the tosa path.
>
>>
>> I also looked at the original sharp kernel sources.
>> Only tosa used the RDY signal for it's tc6393tx chip, other machines simply
>> configured gpio18 as output in their suspend routines.
Actually, tosa doesn't use sharpsl_pm. Tosa uses the pda-power framework.
I said that only tosa uses the RDY signal to point out that we
probably don't need
the mfp-config line in postsuspend. That being said, i still think
that the array ordering
fix is adequate. Maybe later we may remove the mfp-config line from
postsuspend when
we're absolutely sure it isn't necessary for devices that use spitz_pm.c.
^ permalink raw reply
* [PATCH] CLK: vt8500: Fix SDMMC clk special cases
From: Tony Prisk @ 2012-10-18 9:26 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds some additional handling for the SDMMC special case
in round_rate and set_rate which results in invalid divisor messages
at boot time.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
---
drivers/clk/clk-vt8500.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index a885600..fe25570 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -120,8 +120,17 @@ static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
+ struct clk_device *cdev = to_clk_device(hw);
u32 divisor = *prate / rate;
+ /*
+ * If this is a request for SDMMC we have to adjust the divisor
+ * when >31 to use the fixed predivisor
+ */
+ if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
+ divisor = 64 * ((divisor / 64) + 1);
+ }
+
return *prate / divisor;
}
@@ -135,6 +144,15 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
if (divisor == cdev->div_mask + 1)
divisor = 0;
+ /* SDMMC mask may need to be corrected before testing if its valid */
+ if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
+ /*
+ * Bit 5 is a fixed /64 predivisor. If the requested divisor
+ * is >31 then correct for the fixed divisor being required.
+ */
+ divisor = 0x20 + (divisor / 64);
+ }
+
if (divisor > cdev->div_mask) {
pr_err("%s: invalid divisor for clock\n", __func__);
return -EINVAL;
--
1.7.9.5
^ permalink raw reply related
* [PATCH] ARM/dts: omap3: Fix mcbsp2/3 hwmods to be able to probe the drivers for audio
From: Peter Ujfalusi @ 2012-10-18 9:25 UTC (permalink / raw)
To: linux-arm-kernel
Fixes the following errors:
[ 2.318084] omap-mcbsp 49022000.mcbsp: invalid rx DMA channel
[ 2.324432] omap-mcbsp 49024000.mcbsp: invalid rx DMA channel
Which is because we failed to link the sidetone hwmod for McBSP2/3. The
missing sidetone hwmod link will prevent omap_device_alloc() to append the
DMA resources since we - accidentally - end up having the same number of
resources provided from DT (IO/IRQ) as we have in hwmod for the McBSP ports
without the ST resources.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
Hi Tony, Benoit,
Can you please take this patch for 3.7 since if we boot with DT audio will not
work on BeagleBoard and on boards which uses McBSP2 or 3 for audio.
Thank you,
Peter
arch/arm/boot/dts/omap3.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index f38ea87..696e929 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -257,7 +257,7 @@
interrupt-names = "common", "tx", "rx", "sidetone";
interrupt-parent = <&intc>;
ti,buffer-size = <1280>;
- ti,hwmods = "mcbsp2";
+ ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
};
mcbsp3: mcbsp at 49024000 {
@@ -272,7 +272,7 @@
interrupt-names = "common", "tx", "rx", "sidetone";
interrupt-parent = <&intc>;
ti,buffer-size = <128>;
- ti,hwmods = "mcbsp3";
+ ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
};
mcbsp4: mcbsp at 49026000 {
--
1.7.12.3
^ permalink raw reply related
* [PATCH 7/7] ARM: tegra30: cpuidle: add LP2 driver for CPU0
From: Peter De Schrijver @ 2012-10-18 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <507D936F.70905@wwwdotorg.org>
On Tue, Oct 16, 2012 at 07:03:43PM +0200, Stephen Warren wrote:
> On 10/16/2012 02:06 AM, Peter De Schrijver wrote:
> >>> Even though we have plan to use coupled cpuidle, I still prefer to go
> >>> with the LP2 driver first. Then adding one more patch to support coupled
> >>> cpuidle based on LP2 driver. This is good for history. And if there is
> >>> any issue, it's more easy to roll back to the stable one.
> >>
> >> I don't think that implementing it one way and then changing to a
> >> different way will benefit history at all. It'll make the history more
> >> complicated. What exactly is the problem with just using coupled cpuidle
> >> from the start? If we did merge this implementation now, then switch to
> >> coupled cpuidle later, when do you think the switch would happen?
> >
> > Before we consider doing this, I think we should have some idea on how
> > frequently we run into the situation where CPU0 is idle but a secondary
> > core is not. Depending on that we can then decide how useful coupled cpuidle
> > would be for us.
>
> Would it not be 75% of the time where we have 1 of 4 CPUs active? At
> least, that's assuming that all work is evenly distributed amongst CPUs,
> and hence it's random which CPU is the last to go idle, but perhaps
> that's not the case if CPU0 is somehow special workload-wise?
>
Depends, at least it used to be possible to tune the scheduler to prefer
CPU0 if the workload can run on a single CPU.
Cheers,
Peter.
^ permalink raw reply
* [PATCHv9 8/8] ARM: OMAP4: USB: power down MUSB PHY if not used
From: Tero Kristo @ 2012-10-18 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350552010-28760-1-git-send-email-t-kristo@ti.com>
Commit c9e4412ab8eb8ef82d645d8749c4ce96ad490007 removed all of the USB
PHY functions for OMAP4, but this causes a problem with core retention
as the MUSB module remains enabled if omap-usb2 phy driver is not used.
This keeps the USB DPLL enabled and prevents l3_init pwrdm from idling.
Fixed by adding a minimal function back that disables the USB PHY in
case omap-usb2 driver is not used.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/omap_phy_internal.c | 27 +++++++++++++++++++++++++++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index d992db8..6a4b9cf 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -33,6 +33,33 @@
#include "soc.h"
#include "control.h"
+#define CONTROL_DEV_CONF 0x300
+#define PHY_PD 0x1
+
+#ifndef CONFIG_OMAP_USB2
+static int __init omap4430_phy_power_down(void)
+{
+ void __iomem *ctrl_base;
+
+ if (!cpu_is_omap44xx())
+ return 0;
+
+ ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
+ if (!ctrl_base) {
+ pr_err("control module ioremap failed\n");
+ return -ENOMEM;
+ }
+
+ /* Power down the phy */
+ __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
+
+ iounmap(ctrl_base);
+
+ return 0;
+}
+early_initcall(omap4430_phy_power_down);
+#endif
+
void am35x_musb_reset(void)
{
u32 regval;
--
1.7.4.1
^ permalink raw reply related
* [PATCHv9 7/8] ARM: OMAP: PM: update target fpwrst to what pwrdm can reach
From: Tero Kristo @ 2012-10-18 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350552010-28760-1-git-send-email-t-kristo@ti.com>
As the code within pwrdm_set_fpwrst is updating powerstate and logic
states according to powerdomain capabilities, it may alter the target
fpwrst also. Update the target fpwrst status according to these checks,
otherwise rest of the code in this function will malfunction.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/powerdomain.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index f5786b4..f92a867 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -711,6 +711,9 @@ int pwrdm_set_fpwrst(struct powerdomain *pwrdm, enum pwrdm_func_state fpwrst)
return -EINVAL;
}
+ /* Refresh target fprwst according to what we can reach */
+ fpwrst = _pwrdm_pwrst_to_fpwrst(pwrdm, pwrst, logic);
+
pr_debug("%s: set fpwrst %0x to pwrdm %s\n",
__func__, fpwrst, pwrdm->name);
--
1.7.4.1
^ permalink raw reply related
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