* [PATCH v4 0/5] rtc: omap dt support (for am33xx)
From: Afzal Mohammed @ 2012-10-19 9:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi Andrew,
This series enhances rtc-omap driver so as to be usable on
am33xx SoC by adding DT support (Beagle Bone uses am33xx).
This is a revised version of series that was posted on
27th July 2012 with the subject,
"omap-am33xx rtc dt support".
It seems rtc maintainer in inactive and hence sending it you.
Please help this reach mainline.
Brief:
Enhance rtc-omap driver to make it DT capable. This is
required to support boards that boot only with DT like
Beagle Bone. rtc-omap driver is used in DaVinci platforms
and they are also now going DT way, and these changes make
their DT migration easier. rtc-omap driver is made
intelligent enough to handle kicker mechanism. This also
helps in removing kicker mechanism support done for DaVinci
at platform level.
This series has been made over 3.7-rc1
This has been tested on Beaglebone (am33xx platform) and on
DaVinci da850 evm.
Regards
Afzal
v4:
Resolve build error during module build
Improve DT documentation
v3:
Remove unit address in DT node
Use readb/writeb instead of __raw_* variants
Remove unnecessary parens
v2:
Use device name da830-rtc instead of am1808-rtc, similar change in
compatible for DT
Newly added register name made similar to that existing in the driver
Better commit message description
Modify Kconfig help, resolve checkpatch warning
Afzal Mohammed (4):
rtc: omap: kicker mechanism support
ARM: davinci: remove rtc kicker release
rtc: omap: dt support
rtc: omap: depend on am33xx
Vaibhav Hiremath (1):
rtc: omap: Add runtime pm support
Documentation/devicetree/bindings/rtc/rtc-omap.txt | 17 +++++
arch/arm/mach-davinci/devices-da8xx.c | 13 +---
drivers/rtc/Kconfig | 10 +--
drivers/rtc/rtc-omap.c | 80 +++++++++++++++++++++-
4 files changed, 101 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-omap.txt
--
1.7.12
^ permalink raw reply
* [PATCH v4 1/5] rtc: omap: kicker mechanism support
From: Afzal Mohammed @ 2012-10-19 9:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1350633036.git.afzal@ti.com>
OMAP RTC IP can have kicker feature. This prevents spurious
writes to register. To write to registers kicker lock has to
be released. Procedure to do it as follows,
1. write to kick0 register, 0x83e70b13
2. write to kick1 register, 0x95a4f1e0
Writing value other than 0x83e70b13 to kick0 enables write
locking, more details about kicker mechanism can be found in
section 20.3.3.5.3 of AM335X TRM @www.ti.com/am335x
Here id table information is added and is used to distinguish
those that require kicker handling and the ones that doesn't
need it. There are more features in the newer IP's compared
to legacy ones other than kicker, which driver currently
doesn't handle, supporting additional features would be
easier with the addition of id table.
Older IP (of OMAP1) doesn't have revision register as per
TRM, so revision register can't be relied always to find
features, hence id table is being used.
While at it, replace __raw_writeb/__raw_readb with
writeb/readb; this driver is used on ARMv7 (AM335X SoC)
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
---
v4:
Resolve build error during module build
v3:
Use readb/writeb instead of __raw_* variants
Remove unnecessary parens
v2:
Use device name da830-rtc instead of am1808-rtc
Newly added register name made similar to that existing in the driver
Better commit message description
drivers/rtc/rtc-omap.c | 44 +++++++++++++++++++++++++++++++++++++++++---
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index 0b614e3..d948426 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -38,6 +38,8 @@
* the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
*/
+#define DRIVER_NAME "omap_rtc"
+
#define OMAP_RTC_BASE 0xfffb4800
/* RTC registers */
@@ -64,6 +66,9 @@
#define OMAP_RTC_COMP_MSB_REG 0x50
#define OMAP_RTC_OSC_REG 0x54
+#define OMAP_RTC_KICK0_REG 0x6c
+#define OMAP_RTC_KICK1_REG 0x70
+
/* OMAP_RTC_CTRL_REG bit fields: */
#define OMAP_RTC_CTRL_SPLIT (1<<7)
#define OMAP_RTC_CTRL_DISABLE (1<<6)
@@ -88,10 +93,18 @@
#define OMAP_RTC_INTERRUPTS_IT_ALARM (1<<3)
#define OMAP_RTC_INTERRUPTS_IT_TIMER (1<<2)
+/* OMAP_RTC_KICKER values */
+#define KICK0_VALUE 0x83e70b13
+#define KICK1_VALUE 0x95a4f1e0
+
+#define OMAP_RTC_HAS_KICKER 0x1
+
static void __iomem *rtc_base;
-#define rtc_read(addr) __raw_readb(rtc_base + (addr))
-#define rtc_write(val, addr) __raw_writeb(val, rtc_base + (addr))
+#define rtc_read(addr) readb(rtc_base + (addr))
+#define rtc_write(val, addr) writeb(val, rtc_base + (addr))
+
+#define rtc_writel(val, addr) writel(val, rtc_base + (addr))
/* we rely on the rtc framework to handle locking (rtc->ops_lock),
@@ -285,11 +298,23 @@ static struct rtc_class_ops omap_rtc_ops = {
static int omap_rtc_alarm;
static int omap_rtc_timer;
+static struct platform_device_id omap_rtc_devtype[] = {
+ {
+ .name = DRIVER_NAME,
+ }, {
+ .name = "da830-rtc",
+ .driver_data = OMAP_RTC_HAS_KICKER,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, omap_rtc_devtype);
+
static int __init omap_rtc_probe(struct platform_device *pdev)
{
struct resource *res, *mem;
struct rtc_device *rtc;
u8 reg, new_ctrl;
+ const struct platform_device_id *id_entry;
omap_rtc_timer = platform_get_irq(pdev, 0);
if (omap_rtc_timer <= 0) {
@@ -322,6 +347,12 @@ static int __init omap_rtc_probe(struct platform_device *pdev)
goto fail;
}
+ id_entry = platform_get_device_id(pdev);
+ if (id_entry && (id_entry->driver_data & OMAP_RTC_HAS_KICKER)) {
+ rtc_writel(KICK0_VALUE, OMAP_RTC_KICK0_REG);
+ rtc_writel(KICK1_VALUE, OMAP_RTC_KICK1_REG);
+ }
+
rtc = rtc_device_register(pdev->name, &pdev->dev,
&omap_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc)) {
@@ -398,6 +429,8 @@ fail2:
fail1:
rtc_device_unregister(rtc);
fail0:
+ if (id_entry && (id_entry->driver_data & OMAP_RTC_HAS_KICKER))
+ rtc_writel(0, OMAP_RTC_KICK0_REG);
iounmap(rtc_base);
fail:
release_mem_region(mem->start, resource_size(mem));
@@ -408,6 +441,8 @@ static int __exit omap_rtc_remove(struct platform_device *pdev)
{
struct rtc_device *rtc = platform_get_drvdata(pdev);
struct resource *mem = dev_get_drvdata(&rtc->dev);
+ const struct platform_device_id *id_entry =
+ platform_get_device_id(pdev);
device_init_wakeup(&pdev->dev, 0);
@@ -420,6 +455,8 @@ static int __exit omap_rtc_remove(struct platform_device *pdev)
free_irq(omap_rtc_alarm, rtc);
rtc_device_unregister(rtc);
+ if (id_entry && (id_entry->driver_data & OMAP_RTC_HAS_KICKER))
+ rtc_writel(0, OMAP_RTC_KICK0_REG);
iounmap(rtc_base);
release_mem_region(mem->start, resource_size(mem));
return 0;
@@ -471,9 +508,10 @@ static struct platform_driver omap_rtc_driver = {
.resume = omap_rtc_resume,
.shutdown = omap_rtc_shutdown,
.driver = {
- .name = "omap_rtc",
+ .name = DRIVER_NAME,
.owner = THIS_MODULE,
},
+ .id_table = omap_rtc_devtype,
};
static int __init rtc_init(void)
--
1.7.12
^ permalink raw reply related
* [PATCH v4 2/5] ARM: davinci: remove rtc kicker release
From: Afzal Mohammed @ 2012-10-19 9:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1350633036.git.afzal@ti.com>
rtc-omap driver is now capable of handling kicker mechanism,
hence remove kicker handling at platform level, instead
provide proper device name so that driver can handle kicker
mechanism by itself
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
---
v2:
Use device name da830-rtc instead of am1808-rtc
arch/arm/mach-davinci/devices-da8xx.c | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bd2f72b..2d25b24 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -674,7 +674,7 @@ static struct resource da8xx_rtc_resources[] = {
};
static struct platform_device da8xx_rtc_device = {
- .name = "omap_rtc",
+ .name = "da830-rtc",
.id = -1,
.num_resources = ARRAY_SIZE(da8xx_rtc_resources),
.resource = da8xx_rtc_resources,
@@ -683,17 +683,6 @@ static struct platform_device da8xx_rtc_device = {
int da8xx_register_rtc(void)
{
int ret;
- void __iomem *base;
-
- base = ioremap(DA8XX_RTC_BASE, SZ_4K);
- if (WARN_ON(!base))
- return -ENOMEM;
-
- /* Unlock the rtc's registers */
- __raw_writel(0x83e70b13, base + 0x6c);
- __raw_writel(0x95a4f1e0, base + 0x70);
-
- iounmap(base);
ret = platform_device_register(&da8xx_rtc_device);
if (!ret)
--
1.7.12
^ permalink raw reply related
* [PATCH v4 3/5] rtc: omap: dt support
From: Afzal Mohammed @ 2012-10-19 9:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1350633036.git.afzal@ti.com>
enhance rtc-omap driver with DT capability
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
---
v4:
Proper devicetree documentation
v2:
Use compatible as ti,da830-rtc instead of ti,am1808-rtc
Documentation/devicetree/bindings/rtc/rtc-omap.txt | 17 +++++++++++++++++
drivers/rtc/rtc-omap.c | 18 ++++++++++++++++++
2 files changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-omap.txt
diff --git a/Documentation/devicetree/bindings/rtc/rtc-omap.txt b/Documentation/devicetree/bindings/rtc/rtc-omap.txt
new file mode 100644
index 0000000..b47aa41
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/rtc-omap.txt
@@ -0,0 +1,17 @@
+TI Real Time Clock
+
+Required properties:
+- compatible: "ti,da830-rtc"
+- reg: Address range of rtc register set
+- interrupts: rtc timer, alarm interrupts in order
+- interrupt-parent: phandle for the interrupt controller
+
+Example:
+
+rtc at 1c23000 {
+ compatible = "ti,da830-rtc";
+ reg = <0x23000 0x1000>;
+ interrupts = <19
+ 19>;
+ interrupt-parent = <&intc>;
+};
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index d948426..dff9ff4 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -20,6 +20,8 @@
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
#include <asm/io.h>
@@ -298,6 +300,8 @@ static struct rtc_class_ops omap_rtc_ops = {
static int omap_rtc_alarm;
static int omap_rtc_timer;
+#define OMAP_RTC_DATA_DA830_IDX 1
+
static struct platform_device_id omap_rtc_devtype[] = {
{
.name = DRIVER_NAME,
@@ -309,12 +313,25 @@ static struct platform_device_id omap_rtc_devtype[] = {
};
MODULE_DEVICE_TABLE(platform, omap_rtc_devtype);
+static const struct of_device_id omap_rtc_of_match[] = {
+ { .compatible = "ti,da830-rtc",
+ .data = &omap_rtc_devtype[OMAP_RTC_DATA_DA830_IDX],
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
+
static int __init omap_rtc_probe(struct platform_device *pdev)
{
struct resource *res, *mem;
struct rtc_device *rtc;
u8 reg, new_ctrl;
const struct platform_device_id *id_entry;
+ const struct of_device_id *of_id;
+
+ of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
+ if (of_id)
+ pdev->id_entry = of_id->data;
omap_rtc_timer = platform_get_irq(pdev, 0);
if (omap_rtc_timer <= 0) {
@@ -510,6 +527,7 @@ static struct platform_driver omap_rtc_driver = {
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(omap_rtc_of_match),
},
.id_table = omap_rtc_devtype,
};
--
1.7.12
^ permalink raw reply related
* [PATCH v4 4/5] rtc: omap: depend on am33xx
From: Afzal Mohammed @ 2012-10-19 9:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1350633036.git.afzal@ti.com>
rtc-omap driver can be reused for AM33xx RTC.
Provide dependency in Kconfig.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
---
v2:
Modify Kconfig help, resolve checkpatch warning
drivers/rtc/Kconfig | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 19c03ab..4f7ecb6 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -777,11 +777,13 @@ config RTC_DRV_IMXDI
config RTC_DRV_OMAP
tristate "TI OMAP1"
- depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX
+ depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_DAVINCI_DA8XX || SOC_AM33XX
help
- Say "yes" here to support the real time clock on TI OMAP1 and
- DA8xx/OMAP-L13x chips. This driver can also be built as a
- module called rtc-omap.
+ Say "yes" here to support the on chip real time clock
+ present on TI OMAP1, AM33xx and DA8xx/OMAP-L13x.
+
+ This driver can also be built as a module, if so, module
+ will be called rtc-omap.
config HAVE_S3C_RTC
bool
--
1.7.12
^ permalink raw reply related
* [PATCH v4 5/5] rtc: omap: Add runtime pm support
From: Afzal Mohammed @ 2012-10-19 9:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1350633036.git.afzal@ti.com>
From: Vaibhav Hiremath <hvaibhav@ti.com>
OMAP1 RTC driver is used in multiple devices like,
OMAPL138 and AM33XX. Driver currently doesn't handle any clocks,
which may be right for OMAP1 architecture but in case of AM33XX,
the clock/module needs to be enabled in order to access the registers.
So covert this driver to runtime pm, which internally handles rest.
afzal at ti.com: handle error path
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
---
drivers/rtc/rtc-omap.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index dff9ff4..6009714 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -22,6 +22,7 @@
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
#include <asm/io.h>
@@ -364,6 +365,10 @@ static int __init omap_rtc_probe(struct platform_device *pdev)
goto fail;
}
+ /* Enable the clock/module so that we can access the registers */
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_get_sync(&pdev->dev);
+
id_entry = platform_get_device_id(pdev);
if (id_entry && (id_entry->driver_data & OMAP_RTC_HAS_KICKER)) {
rtc_writel(KICK0_VALUE, OMAP_RTC_KICK0_REG);
@@ -448,6 +453,8 @@ fail1:
fail0:
if (id_entry && (id_entry->driver_data & OMAP_RTC_HAS_KICKER))
rtc_writel(0, OMAP_RTC_KICK0_REG);
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
iounmap(rtc_base);
fail:
release_mem_region(mem->start, resource_size(mem));
@@ -474,6 +481,11 @@ static int __exit omap_rtc_remove(struct platform_device *pdev)
rtc_device_unregister(rtc);
if (id_entry && (id_entry->driver_data & OMAP_RTC_HAS_KICKER))
rtc_writel(0, OMAP_RTC_KICK0_REG);
+
+ /* Disable the clock/module */
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
iounmap(rtc_base);
release_mem_region(mem->start, resource_size(mem));
return 0;
@@ -496,11 +508,17 @@ static int omap_rtc_suspend(struct platform_device *pdev, pm_message_t state)
else
rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
+ /* Disable the clock/module */
+ pm_runtime_put_sync(&pdev->dev);
+
return 0;
}
static int omap_rtc_resume(struct platform_device *pdev)
{
+ /* Enable the clock/module so that we can access the registers */
+ pm_runtime_get_sync(&pdev->dev);
+
if (device_may_wakeup(&pdev->dev))
disable_irq_wake(omap_rtc_alarm);
else
--
1.7.12
^ permalink raw reply related
* [PATCH v2] arm/dts: AM33XX: Add SPI device tree data
From: Philip, Avinash @ 2012-10-19 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50810E2F.5@ti.com>
On Fri, Oct 19, 2012 at 13:54:15, Cousson, Benoit wrote:
> Hi Avinash,
>
> This look good to me except the: status = "disabled".
status = "disabled" in soc .dtsi file to make sure that IP driver
won't loaded unless if IP used.
So from board .dts file status = "okay" should be set if IP being used.
Follows the uart1 case in AM33xx dtsi.
uart1 also sets status = "disabled"; in am33xx.dtsi & set status = "okay";
in am335x-evm.dts.
Thanks
Avinash
>
> The "disabled" should be reserved for variant that does not contain the IP.
> Is it the case here?
>
> Regards,
> Benoit
>
> On 09/18/2012 07:30 AM, Philip, Avinash wrote:
> > Add McSPI data node to AM33XX device tree file. The McSPI module (and so
> > as the driver) is reused from OMAP4.
> >
> > Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
> > Tested-by: Matt Porter <mporter@ti.com>
> > ---
> > Changes since v1:
> > - Corrected reg offset in reg DT entry.
> >
> > :100644 100644 ff3badb... 065fd54... M arch/arm/boot/dts/am33xx.dtsi
> > arch/arm/boot/dts/am33xx.dtsi | 25 +++++++++++++++++++++++++
> > 1 files changed, 25 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> > index ff3badb..065fd54 100644
> > --- a/arch/arm/boot/dts/am33xx.dtsi
> > +++ b/arch/arm/boot/dts/am33xx.dtsi
> > @@ -219,5 +219,30 @@
> > interrupt-parent = <&intc>;
> > interrupts = <91>;
> > };
> > +
> > + spi0: spi at 48030000 {
> > + compatible = "ti,omap4-mcspi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x48030000 0x400>;
> > + interrupt-parent = <&intc>;
> > + interrupt = <65>;
> > + ti,spi-num-cs = <2>;
> > + ti,hwmods = "spi0";
> > + status = "disabled";
> > +
> > + };
> > +
> > + spi1: spi at 481a0000 {
> > + compatible = "ti,omap4-mcspi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x481a0000 0x400>;
> > + interrupt-parent = <&intc>;
> > + interrupt = <125>;
> > + ti,spi-num-cs = <2>;
> > + ti,hwmods = "spi1";
> > + status = "disabled";
> > + };
> > };
> > };
> >
>
>
^ permalink raw reply
* [PATCH v2 0/2] Add DMA and device tree support to the flash controller FLCTL
From: Bastian Hecht @ 2012-10-19 10:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350626232.5769.318.camel@sauron.fi.intel.com>
Hey Artem,
>> I can reproduce the error with the following output:
>> /tmp/ccYAbker.s: Assembler messages:
>> /tmp/ccYAbker.s: Error: bad immediate value for 8-bit offset (2048)
>> make[3]: *** [drivers/mtd/nand/docg4.o] Error 1
>>
>> The compiler version is: gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu5)
>> I usually use: gcc version 4.4.1 (Sourcery G++ Lite 2010q1-202) and
>> can compile things without problems.
>
> Yeah, a bug report would be great. I've switched to 4.4.1 and checked
> your patches with aiaiai:
Ok I'll file one.
I've added a cleanup patch 1/3 and tackled the problems below as follows:
> --------------------------------------------------------------------------------
>
> Successfully built configuration "arm-mackerel_defconfig,arm,arm-none-linux-gnueabi-", results:
>
> --- before_patching.log
> +++ after_patching.log
> @@ @@
> +drivers/mtd/nand/sh_flctl.c:1142 flctl_probe() warn: 'irq' was not released on error [smatch]
> +drivers/mtd/nand/sh_flctl.c:1142:2-8: ERROR: missing iounmap; ioremap on line 1117 and execution via conditional on line 1140 [coccinelle]
Oh yes, my bad. Fixed in patch 3 (formerly 2).
> +drivers/mtd/nand/sh_flctl.c:164:25: warning: cast removes address space of expression [sparse]
> +drivers/mtd/nand/sh_flctl.c:181:25: warning: cast removes address space of expression [sparse]
Here I have no idea how to fix it. dma_addr_t is a typedef to u32. How
could I possibly not loose the address space?
> -drivers/mtd/nand/sh_flctl.c:311 write_fiforeg() Error invalid range 4096 to -1 [smatch]
Here my smatch (git head version) doesn't complain. Still I switched
to unsigned int for indexing an array member and hope this solves the
problem. Done in new patch 1/3.
> -drivers/mtd/nand/sh_flctl.c:317:17: warning: incorrect type in argument 2 (different address spaces) [sparse]
> -drivers/mtd/nand/sh_flctl.c:317:17: expected void volatile [noderef] <asn:2>*addr [sparse]
> -drivers/mtd/nand/sh_flctl.c:317:17: got void *fifo_addr [sparse]
Fixed in new patch 1/3.
> +drivers/mtd/nand/sh_flctl.c:469 write_fiforeg() Error invalid range 4096 to -1 [smatch]
Same as above. Unclear how to solve.
> +drivers/mtd/nand/sh_flctl.c:485:17: warning: incorrect type in argument 2 (different address spaces) [sparse]
> +drivers/mtd/nand/sh_flctl.c:485:17: expected void volatile [noderef] <asn:2>*addr [sparse]
> +drivers/mtd/nand/sh_flctl.c:485:17: got void *fifo_addr [sparse]
Fixed in patch 1/3.
Thanks for checking, I'll send out the new patch series in a moment,
Bastian
^ permalink raw reply
* [PATCH v3 0/3] Add DMA and device tree support to the flash controller FLCTL
From: Bastian Hecht @ 2012-10-19 10:15 UTC (permalink / raw)
To: linux-arm-kernel
changelog v3: - due to shame on me by letting aiaiai complain, I've added
a third patch (1/3) that cleans up some parts of the driver
and added a correct error path to probe() in patch 3 (formerly 2/2).
I found no way to fix this though:
+drivers/mtd/nand/sh_flctl.c:181:25: warning: cast removes address space of expression [sparse]
changelog v2: - cosmetic fixes in patch 1
- added dmas and dma-names field in patch 2
This mini-series consists of 2 separately posted patch-sets that shrunk
to one patch each. It adds DMA support for the data part (not ECC) as
well as device tree support to the FLCTL flash controller.
As the 2nd patch is based on the 1st, I've decided to
collect them here to avoid any confusion.
The first set contained
[PATCH 1/2] mtd: sh_flctl: Setup and release DMA channels
[PATCH 2/2] mtd: sh_flctl: Use DMA for data fifo FLTDFIFO when available
and was merged after 2 reviews to
[PATCH] mtd: sh_flctl: Add DMA capabilty (same patch as in here)
The second set contained
[PATCH 1/3] mtd: sh_flctl: Probe SNAND_E flag from NAND chip
[PATCH 2/3] mtd: sh_flctl: Add device tree support
[PATCH 3/3] mtd: sh_flctl: Add sh7372 device tree config
and is merged here to
mtd: sh_flctl: Add device tree support
Patch 1 can be omitted as SNAND_E is handled in the FLCTL source anyway
correctly in set_cmd_regs() and the flag can be removed from existing board
codes without this patch.
Patch 2 without patch 3 may be confusing so I merged them too. Documentation
is added as well.
I've added linux-arm-kernel at lists.infradead.org as recipient for the
device tree part.
The patchset is based on
l2-mtd git://git.infradead.org/users/dedekind/l2-mtd.git
with reverted commit e26c113b4130aefa1d8446602bb5b05cfd646bfe.
Bastian Hecht (2):
mtd: sh_flctl: Add DMA capabilty
mtd: sh_flctl: Add device tree support
.../devicetree/bindings/mtd/flctl-nand.txt | 37 +++
drivers/mtd/nand/sh_flctl.c | 266 +++++++++++++++++++-
include/linux/mtd/sh_flctl.h | 12 +
3 files changed, 305 insertions(+), 10 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/flctl-nand.txt
--
1.7.5.4
^ permalink raw reply
* [PATCH v3 1/3] mtd: sh_flctl: Minor cleanups
From: Bastian Hecht @ 2012-10-19 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350641736-18192-1-git-send-email-hechtb@gmail.com>
Some small fixes to avoid sparse and smatch complain. Other cosmetic fixes
as well.
- Change of the type of the member index in struct sh_flctl from signed
to unsigned. We use index by addressing array members, so unsigned is more
concise here. Adapt functions relying on sh_flctl::index.
- Remove a blurring cast in write_fiforeg().
- Apply consistent naming scheme when refering to the data buffer.
- Shorten some unnecessarily verbose functions.
- Remove spaces at start of lines.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
---
v3: This is a newly added patch (v3 is misleading here) in reaction to the
aiaiai output of Artem. My smatch (git head) didn't complain about the
range problem mentioned in Artem's comment of v2 but I thought switching
to unsigned int can't hurt here and seems more clean.
drivers/mtd/nand/sh_flctl.c | 37 ++++++++++++++++---------------------
include/linux/mtd/sh_flctl.h | 2 +-
2 files changed, 17 insertions(+), 22 deletions(-)
diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 4fbfe96..78d18c0f 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -225,7 +225,7 @@ static enum flctl_ecc_res_t wait_recfifo_ready
for (i = 0; i < 3; i++) {
uint8_t org;
- int index;
+ unsigned int index;
data = readl(ecc_reg[i]);
@@ -305,28 +305,29 @@ static enum flctl_ecc_res_t read_ecfiforeg
return res;
}
-static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
+static void write_fiforeg(struct sh_flctl *flctl, int rlen,
+ unsigned int offset)
{
int i, len_4align;
- unsigned long *data = (unsigned long *)&flctl->done_buff[offset];
- void *fifo_addr = (void *)FLDTFIFO(flctl);
+ unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
len_4align = (rlen + 3) / 4;
for (i = 0; i < len_4align; i++) {
wait_wfifo_ready(flctl);
- writel(cpu_to_be32(data[i]), fifo_addr);
+ writel(cpu_to_be32(buf[i]), FLDTFIFO(flctl));
}
}
-static void write_ec_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
+static void write_ec_fiforeg(struct sh_flctl *flctl, int rlen,
+ unsigned int offset)
{
int i, len_4align;
- unsigned long *data = (unsigned long *)&flctl->done_buff[offset];
+ unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
len_4align = (rlen + 3) / 4;
for (i = 0; i < len_4align; i++) {
wait_wecfifo_ready(flctl);
- writel(cpu_to_be32(data[i]), FLECFIFO(flctl));
+ writel(cpu_to_be32(buf[i]), FLECFIFO(flctl));
}
}
@@ -748,41 +749,35 @@ static void flctl_select_chip(struct mtd_info *mtd, int chipnr)
static void flctl_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
struct sh_flctl *flctl = mtd_to_flctl(mtd);
- int index = flctl->index;
- memcpy(&flctl->done_buff[index], buf, len);
+ memcpy(&flctl->done_buff[flctl->index], buf, len);
flctl->index += len;
}
static uint8_t flctl_read_byte(struct mtd_info *mtd)
{
struct sh_flctl *flctl = mtd_to_flctl(mtd);
- int index = flctl->index;
uint8_t data;
- data = flctl->done_buff[index];
+ data = flctl->done_buff[flctl->index];
flctl->index++;
return data;
}
static uint16_t flctl_read_word(struct mtd_info *mtd)
{
- struct sh_flctl *flctl = mtd_to_flctl(mtd);
- int index = flctl->index;
- uint16_t data;
- uint16_t *buf = (uint16_t *)&flctl->done_buff[index];
+ struct sh_flctl *flctl = mtd_to_flctl(mtd);
+ uint16_t *buf = (uint16_t *)&flctl->done_buff[flctl->index];
- data = *buf;
- flctl->index += 2;
- return data;
+ flctl->index += 2;
+ return *buf;
}
static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
struct sh_flctl *flctl = mtd_to_flctl(mtd);
- int index = flctl->index;
- memcpy(buf, &flctl->done_buff[index], len);
+ memcpy(buf, &flctl->done_buff[flctl->index], len);
flctl->index += len;
}
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
index 01e4b15..4815576 100644
--- a/include/linux/mtd/sh_flctl.h
+++ b/include/linux/mtd/sh_flctl.h
@@ -147,7 +147,7 @@ struct sh_flctl {
uint8_t done_buff[2048 + 64]; /* max size 2048 + 64 */
int read_bytes;
- int index;
+ unsigned int index;
int seqin_column; /* column in SEQIN cmd */
int seqin_page_addr; /* page_addr in SEQIN cmd */
uint32_t seqin_read_cmd; /* read cmd in SEQIN cmd */
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3 2/3] mtd: sh_flctl: Add DMA capabilty
From: Bastian Hecht @ 2012-10-19 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350641736-18192-1-git-send-email-hechtb@gmail.com>
The code probes if DMA channels can get allocated and tears them down at
removal/failure if needed.
If available it uses them to transfer the data part (not ECC). On
failure we fall back to PIO mode.
Based on Guennadi Liakhovetski's code from the sh_mmcif driver.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Reviewed-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
v3: no changes. I don't know if the error
warning: cast removes address space of expression [sparse]
because of line
+ cfg.dst_addr = (dma_addr_t)FLDTFIFO(flctl);
can be fixed. dma_addr_t is loosly defined as u32 and I see no way how to make
a proper conversion.
drivers/mtd/nand/sh_flctl.c | 173 +++++++++++++++++++++++++++++++++++++++++-
include/linux/mtd/sh_flctl.h | 12 +++
2 files changed, 183 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 78d18c0f..6dc0369 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -23,11 +23,15 @@
#include <linux/module.h>
#include <linux/kernel.h>
+#include <linux/completion.h>
#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
+#include <linux/sh_dma.h>
#include <linux/slab.h>
#include <linux/string.h>
@@ -106,6 +110,84 @@ static void wait_completion(struct sh_flctl *flctl)
writeb(0x0, FLTRCR(flctl));
}
+static void flctl_dma_complete(void *param)
+{
+ struct sh_flctl *flctl = param;
+
+ complete(&flctl->dma_complete);
+}
+
+static void flctl_release_dma(struct sh_flctl *flctl)
+{
+ if (flctl->chan_fifo0_rx) {
+ dma_release_channel(flctl->chan_fifo0_rx);
+ flctl->chan_fifo0_rx = NULL;
+ }
+ if (flctl->chan_fifo0_tx) {
+ dma_release_channel(flctl->chan_fifo0_tx);
+ flctl->chan_fifo0_tx = NULL;
+ }
+}
+
+static void flctl_setup_dma(struct sh_flctl *flctl)
+{
+ dma_cap_mask_t mask;
+ struct dma_slave_config cfg;
+ struct platform_device *pdev = flctl->pdev;
+ struct sh_flctl_platform_data *pdata = pdev->dev.platform_data;
+ int ret;
+
+ if (!pdata)
+ return;
+
+ if (pdata->slave_id_fifo0_tx <= 0 || pdata->slave_id_fifo0_rx <= 0)
+ return;
+
+ /* We can only either use DMA for both Tx and Rx or not use it@all */
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter,
+ (void *)pdata->slave_id_fifo0_tx);
+ dev_dbg(&pdev->dev, "%s: TX: got channel %p\n", __func__,
+ flctl->chan_fifo0_tx);
+
+ if (!flctl->chan_fifo0_tx)
+ return;
+
+ memset(&cfg, 0, sizeof(cfg));
+ cfg.slave_id = pdata->slave_id_fifo0_tx;
+ cfg.direction = DMA_MEM_TO_DEV;
+ cfg.dst_addr = (dma_addr_t)FLDTFIFO(flctl);
+ cfg.src_addr = 0;
+ ret = dmaengine_slave_config(flctl->chan_fifo0_tx, &cfg);
+ if (ret < 0)
+ goto err;
+
+ flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter,
+ (void *)pdata->slave_id_fifo0_rx);
+ dev_dbg(&pdev->dev, "%s: RX: got channel %p\n", __func__,
+ flctl->chan_fifo0_rx);
+
+ if (!flctl->chan_fifo0_rx)
+ goto err;
+
+ cfg.slave_id = pdata->slave_id_fifo0_rx;
+ cfg.direction = DMA_DEV_TO_MEM;
+ cfg.dst_addr = 0;
+ cfg.src_addr = (dma_addr_t)FLDTFIFO(flctl);
+ ret = dmaengine_slave_config(flctl->chan_fifo0_rx, &cfg);
+ if (ret < 0)
+ goto err;
+
+ init_completion(&flctl->dma_complete);
+
+ return;
+
+err:
+ flctl_release_dma(flctl);
+}
+
static void set_addr(struct mtd_info *mtd, int column, int page_addr)
{
struct sh_flctl *flctl = mtd_to_flctl(mtd);
@@ -261,6 +343,70 @@ static void wait_wecfifo_ready(struct sh_flctl *flctl)
timeout_error(flctl, __func__);
}
+static int flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf,
+ int len, enum dma_data_direction dir)
+{
+ struct dma_async_tx_descriptor *desc = NULL;
+ struct dma_chan *chan;
+ enum dma_transfer_direction tr_dir;
+ dma_addr_t dma_addr;
+ dma_cookie_t cookie = -EINVAL;
+ uint32_t reg;
+ int ret;
+
+ if (dir == DMA_FROM_DEVICE) {
+ chan = flctl->chan_fifo0_rx;
+ tr_dir = DMA_DEV_TO_MEM;
+ } else {
+ chan = flctl->chan_fifo0_tx;
+ tr_dir = DMA_MEM_TO_DEV;
+ }
+
+ dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
+
+ if (dma_addr)
+ desc = dmaengine_prep_slave_single(chan, dma_addr, len,
+ tr_dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+
+ if (desc) {
+ reg = readl(FLINTDMACR(flctl));
+ reg |= DREQ0EN;
+ writel(reg, FLINTDMACR(flctl));
+
+ desc->callback = flctl_dma_complete;
+ desc->callback_param = flctl;
+ cookie = dmaengine_submit(desc);
+
+ dma_async_issue_pending(chan);
+ } else {
+ /* DMA failed, fall back to PIO */
+ flctl_release_dma(flctl);
+ dev_warn(&flctl->pdev->dev,
+ "DMA failed, falling back to PIO\n");
+ ret = -EIO;
+ goto out;
+ }
+
+ ret =
+ wait_for_completion_timeout(&flctl->dma_complete,
+ msecs_to_jiffies(3000));
+
+ if (ret <= 0) {
+ chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
+ dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n");
+ }
+
+out:
+ reg = readl(FLINTDMACR(flctl));
+ reg &= ~DREQ0EN;
+ writel(reg, FLINTDMACR(flctl));
+
+ dma_unmap_single(chan->device->dev, dma_addr, len, dir);
+
+ /* ret > 0 is success */
+ return ret;
+}
+
static void read_datareg(struct sh_flctl *flctl, int offset)
{
unsigned long data;
@@ -279,11 +425,20 @@ static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
len_4align = (rlen + 3) / 4;
+ /* initiate DMA transfer */
+ if (flctl->chan_fifo0_rx && rlen >= 32 &&
+ flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_DEV_TO_MEM) > 0)
+ goto convert; /* DMA success */
+
+ /* do polling transfer */
for (i = 0; i < len_4align; i++) {
wait_rfifo_ready(flctl);
buf[i] = readl(FLDTFIFO(flctl));
- buf[i] = be32_to_cpu(buf[i]);
}
+
+convert:
+ for (i = 0; i < len_4align; i++)
+ buf[i] = be32_to_cpu(buf[i]);
}
static enum flctl_ecc_res_t read_ecfiforeg
@@ -325,9 +480,19 @@ static void write_ec_fiforeg(struct sh_flctl *flctl, int rlen,
unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
len_4align = (rlen + 3) / 4;
+
+ for (i = 0; i < len_4align; i++)
+ buf[i] = cpu_to_be32(buf[i]);
+
+ /* initiate DMA transfer */
+ if (flctl->chan_fifo0_tx && rlen >= 32 &&
+ flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_MEM_TO_DEV) > 0)
+ return; /* DMA success */
+
+ /* do polling transfer */
for (i = 0; i < len_4align; i++) {
wait_wecfifo_ready(flctl);
- writel(cpu_to_be32(buf[i]), FLECFIFO(flctl));
+ writel(buf[i], FLECFIFO(flctl));
}
}
@@ -925,6 +1090,8 @@ static int __devinit flctl_probe(struct platform_device *pdev)
pm_runtime_enable(&pdev->dev);
pm_runtime_resume(&pdev->dev);
+ flctl_setup_dma(flctl);
+
ret = nand_scan_ident(flctl_mtd, 1, NULL);
if (ret)
goto err_chip;
@@ -942,6 +1109,7 @@ static int __devinit flctl_probe(struct platform_device *pdev)
return 0;
err_chip:
+ flctl_release_dma(flctl);
pm_runtime_disable(&pdev->dev);
free_irq(irq, flctl);
err_flste:
@@ -955,6 +1123,7 @@ static int __devexit flctl_remove(struct platform_device *pdev)
{
struct sh_flctl *flctl = platform_get_drvdata(pdev);
+ flctl_release_dma(flctl);
nand_release(&flctl->mtd);
pm_runtime_disable(&pdev->dev);
free_irq(platform_get_irq(pdev, 0), flctl);
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
index 4815576..1c28f88 100644
--- a/include/linux/mtd/sh_flctl.h
+++ b/include/linux/mtd/sh_flctl.h
@@ -20,6 +20,7 @@
#ifndef __SH_FLCTL_H__
#define __SH_FLCTL_H__
+#include <linux/completion.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
@@ -107,6 +108,7 @@
#define ESTERINTE (0x1 << 24) /* ECC error interrupt enable */
#define AC1CLR (0x1 << 19) /* ECC FIFO clear */
#define AC0CLR (0x1 << 18) /* Data FIFO clear */
+#define DREQ0EN (0x1 << 16) /* FLDTFIFODMA Request Enable */
#define ECERB (0x1 << 9) /* ECC error */
#define STERB (0x1 << 8) /* Status error */
#define STERINTE (0x1 << 4) /* Status error enable */
@@ -138,6 +140,8 @@ enum flctl_ecc_res_t {
FL_TIMEOUT
};
+struct dma_chan;
+
struct sh_flctl {
struct mtd_info mtd;
struct nand_chip chip;
@@ -161,6 +165,11 @@ struct sh_flctl {
unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */
unsigned holden:1; /* Hardware has FLHOLDCR and HOLDEN is set */
unsigned qos_request:1; /* QoS request to prevent deep power shutdown */
+
+ /* DMA related objects */
+ struct dma_chan *chan_fifo0_rx;
+ struct dma_chan *chan_fifo0_tx;
+ struct completion dma_complete;
};
struct sh_flctl_platform_data {
@@ -170,6 +179,9 @@ struct sh_flctl_platform_data {
unsigned has_hwecc:1;
unsigned use_holden:1;
+
+ unsigned int slave_id_fifo0_tx;
+ unsigned int slave_id_fifo0_rx;
};
static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3 3/3] mtd: sh_flctl: Add device tree support
From: Bastian Hecht @ 2012-10-19 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350641736-18192-1-git-send-email-hechtb@gmail.com>
The flctl can now be probed via device tree setup in addition to the
existing platform data way.
SoC specific setup data is set in the .data member of the OF match, so
kept within the driver itself, while board/user specific setup - like
partitioning - is taken from the device tree.
Actual configuration is added for the SoC sh7372.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
---
v3: Now a proper cleanup path is taken in case of a missing platform or
faulty DT config. Fixes coccinelle and smatch errors from Artem's aiaiaia
output.
.../devicetree/bindings/mtd/flctl-nand.txt | 49 ++++++++++
drivers/mtd/nand/sh_flctl.c | 94 ++++++++++++++++++--
2 files changed, 136 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/flctl-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/flctl-nand.txt b/Documentation/devicetree/bindings/mtd/flctl-nand.txt
new file mode 100644
index 0000000..427f46d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/flctl-nand.txt
@@ -0,0 +1,49 @@
+FLCTL NAND controller
+
+Required properties:
+- compatible : "renesas,shmobile-flctl-sh7372"
+- reg : Address range of the FLCTL
+- interrupts : flste IRQ number
+- nand-bus-width : bus width to NAND chip
+
+Optional properties:
+- dmas: DMA specifier(s)
+- dma-names: name for each DMA specifier. Valid names are
+ "data_tx", "data_rx", "ecc_tx", "ecc_rx"
+
+The DMA fields are not used yet in the driver but are listed here for
+completing the bindings.
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+ flctl at e6a30000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "renesas,shmobile-flctl-sh7372";
+ reg = <0xe6a30000 0x100>;
+ interrupts = <0x0d80>;
+
+ nand-bus-width = <16>;
+
+ dmas = <&dmac 1 /* data_tx */
+ &dmac 2;> /* data_rx */
+ dma-names = "data_tx", "data_rx";
+
+ system at 0 {
+ label = "system";
+ reg = <0x0 0x8000000>;
+ };
+
+ userdata at 8000000 {
+ label = "userdata";
+ reg = <0x8000000 0x10000000>;
+ };
+
+ cache at 18000000 {
+ label = "cache";
+ reg = <0x18000000 0x8000000>;
+ };
+ };
diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 6dc0369..d51e3c1 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -29,6 +29,9 @@
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_mtd.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/sh_dma.h>
@@ -1016,6 +1019,73 @@ static irqreturn_t flctl_handle_flste(int irq, void *dev_id)
return IRQ_HANDLED;
}
+#ifdef CONFIG_OF
+struct flctl_soc_config {
+ unsigned long flcmncr_val;
+ unsigned has_hwecc:1;
+ unsigned use_holden:1;
+};
+
+static struct flctl_soc_config flctl_sh7372_config = {
+ .flcmncr_val = CLK_16B_12L_4H | TYPESEL_SET | SHBUSSEL,
+ .has_hwecc = 1,
+ .use_holden = 1,
+};
+
+static const struct of_device_id of_flctl_match[] = {
+ { .compatible = "renesas,shmobile-flctl-sh7372",
+ .data = &flctl_sh7372_config },
+ {},
+};
+MODULE_DEVICE_TABLE(of, of_flctl_match);
+
+static struct sh_flctl_platform_data *flctl_parse_dt(struct device *dev)
+{
+ const struct of_device_id *match;
+ struct flctl_soc_config *config;
+ struct sh_flctl_platform_data *pdata;
+ struct device_node *dn = dev->of_node;
+ int ret;
+
+ match = of_match_device(of_flctl_match, dev);
+ if (match)
+ config = (struct flctl_soc_config *)match->data;
+ else {
+ dev_err(dev, "%s: no OF configuration attached\n", __func__);
+ return NULL;
+ }
+
+ pdata = devm_kzalloc(dev, sizeof(struct sh_flctl_platform_data),
+ GFP_KERNEL);
+ if (!pdata) {
+ dev_err(dev, "%s: failed to allocate config data\n", __func__);
+ return NULL;
+ }
+
+ /* set SoC specific options */
+ pdata->flcmncr_val = config->flcmncr_val;
+ pdata->has_hwecc = config->has_hwecc;
+ pdata->use_holden = config->use_holden;
+
+ /* parse user defined options */
+ ret = of_get_nand_bus_width(dn);
+ if (ret == 16)
+ pdata->flcmncr_val |= SEL_16BIT;
+ else if (ret != 8) {
+ dev_err(dev, "%s: invalid bus width\n", __func__);
+ return NULL;
+ }
+
+ return pdata;
+}
+#else /* CONFIG_OF */
+#define of_flctl_match NULL
+static struct sh_flctl_platform_data *flctl_parse_dt(struct device *dev)
+{
+ return NULL;
+}
+#endif /* CONFIG_OF */
+
static int __devinit flctl_probe(struct platform_device *pdev)
{
struct resource *res;
@@ -1025,12 +1095,7 @@ static int __devinit flctl_probe(struct platform_device *pdev)
struct sh_flctl_platform_data *pdata;
int ret = -ENXIO;
int irq;
-
- pdata = pdev->dev.platform_data;
- if (pdata == NULL) {
- dev_err(&pdev->dev, "no platform data defined\n");
- return -EINVAL;
- }
+ struct mtd_part_parser_data ppdata = {};
flctl = kzalloc(sizeof(struct sh_flctl), GFP_KERNEL);
if (!flctl) {
@@ -1062,6 +1127,17 @@ static int __devinit flctl_probe(struct platform_device *pdev)
goto err_flste;
}
+ if (pdev->dev.of_node)
+ pdata = flctl_parse_dt(&pdev->dev);
+ else
+ pdata = pdev->dev.platform_data;
+
+ if (!pdata) {
+ dev_err(&pdev->dev, "no setup data defined\n");
+ ret = -EINVAL;
+ goto err_pdata;
+ }
+
platform_set_drvdata(pdev, flctl);
flctl_mtd = &flctl->mtd;
nand = &flctl->chip;
@@ -1104,13 +1180,16 @@ static int __devinit flctl_probe(struct platform_device *pdev)
if (ret)
goto err_chip;
- mtd_device_register(flctl_mtd, pdata->parts, pdata->nr_parts);
+ ppdata.of_node = pdev->dev.of_node;
+ ret = mtd_device_parse_register(flctl_mtd, NULL, &ppdata, pdata->parts,
+ pdata->nr_parts);
return 0;
err_chip:
flctl_release_dma(flctl);
pm_runtime_disable(&pdev->dev);
+err_pdata:
free_irq(irq, flctl);
err_flste:
iounmap(flctl->reg);
@@ -1138,6 +1217,7 @@ static struct platform_driver flctl_driver = {
.driver = {
.name = "sh_flctl",
.owner = THIS_MODULE,
+ .of_match_table = of_flctl_match,
},
};
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 00/16] DMA Engine support for AM33XX
From: Bedia, Vaibhav @ 2012-10-19 10:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
Hi Matt,
On Thu, Oct 18, 2012 at 18:56:39, Porter, Matt wrote:
> Changes since v2:
> - Rebased on 3.7-rc1
> - Fixed bug in DT/pdata parsing first found by Gururaja
> that turned out to be masked by some toolchains
> - Dropped unused mach-omap2/devices.c hsmmc patch
> - Added AM33XX crossbar DMA event mux support
> - Added am335x-evm support
>
> Changes since v1:
> - Rebased on top of mainline from 12250d8
> - Dropped the feature removal schedule patch
> - Implemented dma_request_slave_channel_compat() and
> converted the mmc and spi drivers to use it
> - Dropped unneeded #address-cells and #size-cells from
> EDMA DT support
> - Moved private EDMA header to linux/platform_data/ and
> removed some unneeded definitions
> - Fixed parsing of optional properties
>
> TODO:
> - Add dmaengine support for per-channel caps so the
> hack to set the maximum segments can be replaced with
> a query to the dmaengine driver
>
> This series adds DMA Engine support for AM33xx, which uses
> an EDMA DMAC. The EDMA DMAC has been previously supported by only
> a private API implementation (much like the situation with OMAP
> DMA) found on the DaVinci family of SoCs.
>
> The series applies on top of 3.7-rc1 and the following patches:
>
> - GPMC fails to reserve memory fix:
> http://www.spinics.net/lists/linux-omap/msg79675.html
> - TPS65910 regulator fix:
> https://patchwork.kernel.org/patch/1593651/
> - dmaengine DT support from Vinod's dmaengine_dt branch in
> git://git.infradead.org/users/vkoul/slave-dma.git since
> 027478851791df751176398be02a3b1c5f6aa824
>
> The approach taken is similar to how OMAP DMA is being converted to
> DMA Engine support. With the functional EDMA private API already
> existing in mach-davinci/dma.c, we first move that to an ARM common
> area so it can be shared. Adding DT and runtime PM support to the
> private EDMA API implementation allows it to run on AM33xx. AM33xx
> *only* boots using DT so we leverage Jon's generic DT DMA helpers to
> register EDMA DMAC with the of_dma framework and then add support
> for calling the dma_request_slave_channel() API to both the mmc
> and spi drivers.
>
> With this series both BeagleBone and the AM335x EVM have working
> MMC and SPI support.
>
> This is tested on BeagleBone with a SPI framebuffer driver and MMC
> rootfs. A trivial gpio DMA event misc driver was used to test the
> crossbar DMA event support. It is also tested on the AM335x EVM
> with the onboard SPI flash and MMC rootfs. The branch at
> https://github.com/ohporter/linux/tree/edma-dmaengine-v3 has the
> complete series, dependencies, and some test drivers/defconfigs.
>
I didn't see all the patches that you posted on edma-dmaengine-v3
but I do seem them on edma-dmaengine-am33xx-v3 branch.
I added a couple of patches to enable earlyprintk and build the DTB
appended kernel image uImage-dtb.am335x-evm
Here's what i see
[...]
[ 0.128831] regulator-dummy: no parameters
[ 0.130793] NET: Registered protocol family 16
[ 0.131694] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.133030] omap-gpmc omap-gpmc: GPMC revision 6.0
[ 0.153136] platform 49000000.edma: alias fck already exists
[ 0.153176] platform 49000000.edma: alias fck already exists
[ 0.153199] platform 49000000.edma: alias fck already exists
[ 0.158184] OMAP GPIO hardware version 0.1
[ 0.172844] No ATAGs?
[ 0.172868] hw-breakpoint: debug architecture 0x4 unsupported.
[ 0.174282] genirq: Flags mismatch irq 28. 00000000 (edma) vs. 00000000 (edma)
[ 0.174536] ------------[ cut here ]------------
[ 0.174576] WARNING: at kernel/irq/manage.c:1211 __free_irq+0x9c/0x1c0()
[ 0.174586] Trying to free already-free IRQ 28
[ 0.174596] Modules linked in:
[ 0.174645] [<c001b0e0>] (unwind_backtrace+0x0/0xf0) from [<c0042900>] (warn_slowpath_common+0x4c/0x64)
[ 0.174668] [<c0042900>] (warn_slowpath_common+0x4c/0x64) from [<c00429ac>] (warn_slowpath_fmt+0x30/0x40)
[ 0.174688] [<c00429ac>] (warn_slowpath_fmt+0x30/0x40) from [<c00a8298>] (__free_irq+0x9c/0x1c0)
[ 0.174708] [<c00a8298>] (__free_irq+0x9c/0x1c0) from [<c00a8408>] (free_irq+0x4c/0xa8)
[ 0.174739] [<c00a8408>] (free_irq+0x4c/0xa8) from [<c07976ec>] (edma_probe+0x93c/0xa24)
[ 0.174770] [<c07976ec>] (edma_probe+0x93c/0xa24) from [<c03226d4>] (platform_drv_probe+0x18/0x1c)
[ 0.174793] [<c03226d4>] (platform_drv_probe+0x18/0x1c) from [<c0321494>] (driver_probe_device+0x84/0x224)
[ 0.174814] [<c0321494>] (driver_probe_device+0x84/0x224) from [<c03216c8>] (__driver_attach+0x94/0x98)
[ 0.174834] [<c03216c8>] (__driver_attach+0x94/0x98) from [<c031fd60>] (bus_for_each_dev+0x50/0x7c)
[ 0.174854] [<c031fd60>] (bus_for_each_dev+0x50/0x7c) from [<c0320bc4>] (bus_add_driver+0xa0/0x240)
[ 0.174874] [<c0320bc4>] (bus_add_driver+0xa0/0x240) from [<c0321bfc>] (driver_register+0x78/0x144)
[ 0.174896] [<c0321bfc>] (driver_register+0x78/0x144) from [<c03229a4>] (platform_driver_probe+0x18/0x9c)
[ 0.174918] [<c03229a4>] (platform_driver_probe+0x18/0x9c) from [<c0008874>] (do_one_initcall+0x34/0x180)
[ 0.174947] [<c0008874>] (do_one_initcall+0x34/0x180) from [<c055ad14>] (kernel_init+0x104/0x2b0)
[ 0.174978] [<c055ad14>] (kernel_init+0x104/0x2b0) from [<c0013590>] (ret_from_fork+0x14/0x24)
[ 0.175249] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.175354] edma: probe of 49000000.edma failed with error -16
[ 0.253165] bio: create slab <bio-0> at 0
[ 0.257894] edma-dma-engine edma-dma-engine.0: Can't allocate PaRAM dummy slot
[ 0.257954] edma-dma-engine: probe of edma-dma-engine.0 failed with error -5
[ 0.341189] omap-dma-engine omap-dma-engine: OMAP DMA engine driver
[ 0.343155] vbat: 5000 mV
[ 0.352193] SCSI subsystem initialized
[ 0.354571] usbcore: registered new interface driver usbfs
[ 0.355085] usbcore: registered new interface driver hub
[ 0.355944] usbcore: registered new device driver usb
[ 0.376170] omap_i2c 44e0b000.i2c: bus 0 rev2.4.0 at 400 kHz
[ 0.384465] vrtc: 1800 mV
[ 0.384897] vrtc: supplied by vbat
[ 0.388130] vio: at 1800 mV
[ 0.388284] vio: supplied by vbat
[ 0.391570] vdd_mpu: 912 <--> 1312 mV at 1262 mV
[ 0.391727] vdd_mpu: supplied by vbat
[ 0.394747] vdd_core: 912 <--> 1150 mV at 1137 mV
[ 0.394898] vdd_core: supplied by vbat
[ 0.398155] vdd3: 5000 mV
[ 0.400791] vdig1: at 1800 mV
[ 0.400943] vdig1: supplied by vbat
[ 0.403675] vdig2: at 1800 mV
[ 0.403817] vdig2: supplied by vbat
[ 0.407001] vpll: at 1800 mV
[ 0.407151] vpll: supplied by vbat
[ 0.410187] vdac: at 1800 mV
[ 0.410352] vdac: supplied by vbat
[ 0.413275] vaux1: at 1800 mV
[ 0.413414] vaux1: supplied by vbat
[ 0.416325] vaux2: at 3300 mV
[ 0.416467] vaux2: supplied by vbat
[ 0.419280] vaux33: at 3300 mV
[ 0.419419] vaux33: supplied by vbat
[ 0.422440] vmmc: 1800 <--> 3300 mV at 3300 mV
[ 0.422583] vmmc: supplied by vbat
[ 0.424630] tps65910 0-002d: No interrupt support, no core IRQ
[ 0.432157] Bluetooth: Core ver 2.16
[ 0.432767] NET: Registered protocol family 31
[ 0.432785] Bluetooth: HCI device and connection manager initialized
[ 0.432928] Bluetooth: HCI socket layer initialized
[ 0.432965] Bluetooth: L2CAP socket layer initialized
[ 0.433071] Bluetooth: SCO socket layer initialized
[ 0.435116] cfg80211: Calling CRDA to update world regulatory domain
[ 0.437286] Switching to clocksource gp_timer
[ 0.585766] NET: Registered protocol family 2
[ 0.587934] TCP established hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.588322] TCP bind hash table entries: 8192 (order: 6, 294912 bytes)
[ 0.592077] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.592331] TCP: reno registered
[ 0.592369] UDP hash table entries: 256 (order: 2, 20480 bytes)
[ 0.592634] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes)
[ 0.593454] NET: Registered protocol family 1
[ 0.595290] RPC: Registered named UNIX socket transport module.
[ 0.595315] RPC: Registered udp transport module.
[ 0.595328] RPC: Registered tcp transport module.
[ 0.595340] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.596399] NetWinder Floating Point Emulator V0.97 (double precision)
[ 0.596917] CPU PMU: probing PMU on CPU 0
[ 0.597083] hw perfevents: enabled with ARMv7 Cortex-A8 PMU driver, 5 counters available
[ 0.770294] VFS: Disk quotas dquot_6.5.2
[ 0.770539] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[ 0.773244] NFS: Registering the id_resolver key type
[ 0.773873] Key type id_resolver registered
[ 0.773897] Key type id_legacy registered
[ 0.774046] jffs2: version 2.2. (NAND) (SUMMARY) ?? 2001-2006 Red Hat, Inc.
[ 0.776552] msgmni has been set to 477
[ 0.780591] io scheduler noop registered
[ 0.780618] io scheduler deadline registered
[ 0.780721] io scheduler cfq registered (default)
[ 0.783750] pinctrl-single 44e10800.pinmux: 142 pins at pa f9e10800 size 568
[ 0.788066] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 0.795200] omap_uart 44e09000.serial: did not get pins for uart0 error: -19
[ 0.795696] 44e09000.serial: ttyO0 at MMIO 0x44e09000 (irq = 88) is a OMAP UART0
[ 1.728556] console [ttyO0] enabled
[ 1.769162] brd: module loaded
[ 1.793083] loop: module loaded
[ 1.802779] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 1.811045] OneNAND driver initializing
[ 1.816279] omap2_mcspi 48030000.spi: pins are not configured from the driver
[ 61.836153] INFO: rcu_sched detected stalls on CPUs/tasks: {} (detected by 0, t=7682 jiffies)
[ 61.845144] INFO: Stall ended before state dump start
[ 241.875170] INFO: rcu_sched detected stalls on CPUs/tasks: {} (detected by 0, t=30727 jiffies)
[ 241.884226] INFO: Stall ended before state dump start
[ 421.914230] INFO: rcu_sched detected stalls on CPUs/tasks: {} (detected by 0, t=53772 jiffies)
[...]
Let me know if I missed something.
Regards,
Vaibhav
^ permalink raw reply
* [PATCH RFC 2/6 v3] gpio: Add sysfs support to block GPIO API
From: Linus Walleij @ 2012-10-19 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121018043848.GA4022@minime.bse>
On Thu, Oct 18, 2012 at 6:38 AM, Daniel Gl?ckner <daniel-gl@gmx.net> wrote:
> On Mon, Oct 15, 2012 at 10:30:15PM +0200, Linus Walleij wrote:
>>
>> Another patch that is circulating concerns edge triggers and similar,
>> and it appear that some parts of the GPIO sysfs is for example
>> redefining and exporting IRQchip properties like trigger edge
>> in sysfs, while the settings of the irqchip actually used by the driver
>> is not reflected in the other direction. So you can *set* these things
>> by writing in the GPIO sysfs, but never trust what you *read* from
>> there. And you can set what edges an IRQ will trigger on a certain
>> GPIO, and the way to handle the IRQs from usespace is to poll
>> on a value. This is not really documented but well ...
>
> Part of this sounds like you are not familiar with the GPIOlib sysfs
> IRQ stuff.
Yeah you bet :-)
I'm just trying to maintain it, I think I need your help with this.
Do you think it'd be possible for you to augment the
Documentation/gpio.txt file with some userspace code examples?
I think this could be very useful.
> The trigger edge set in sysfs is only used when userspace
> polls the GPIO via sysfs. Drivers that want to register a gpio IRQ
> should IMHO always explicitly request the edge/level to trigger on and
> they should request the gpio beforehand. This prevents the gpio from
> being exported to userspace. Only IRQ triggers accepted by the irq chip
> are settable in sysfs, so you can trust the value read from that file.
OK.
>> Daniel: are you interested in helping us fixing the GPIOlib
>> sysfs ABI and kernel internals? I'm a bit afraid of it.
>
> Actually I don't know what you want to change to fix the existing sysfs
> ABI. Personally I'd like to see the following things changed:
> - /sys/gpio/.../direction does not correspond to hardware before first
> use of gpio_direction_* due to lack of gpio_get_direction.
> - Names given to gpios by the chip should just result in symlinks to
> the usual gpioX directories or (un)exporting of gpios should accept
> names.
Please send a patch! I'll merge.
Actually I'm mostly referring to another floating patch, I will try to
dig it up and CC you.
Yours,
Linus Walleij
^ permalink raw reply
* [RFC PATCH 2/2] ARM: OMAP4: clock: use omap4_clks_register API
From: Strashko, Grygorii @ 2012-10-19 10:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121018175312.21731.22864@nucleus>
Hi Mike,
> In addition to removing CK_443X/CK_446X you could also get rid of struct
> omap_clk completely (arch/arm/plat-omap/include/plat/clkdev_omap.h) and
> the CLK macro by changing the clk array to be of type struct clk_lookup
> and using the CLKDEV_INIT macro.
Yes. It may be done. As I understand, this approach is applicable for you, if so i can continue working on it. right?
> I wonder if splitting the tables would make initdata any easier. It
OMAP5,4,2 - there are no so much differences between SOcs, so it looks good and simple.
OMAP3 - it is a little bit more complex.
> would be nice to get more functional changes out of this series
> alongside the data reorganization.
Could you provide more details, pls?
> Also have you looked at splitting the tables for OMAP2/3?
Yes. I think, it can be done.
Best regards,
Grygorii Strashko | GlobalLogic
________________________________________
From: Mike Turquette [mturquette at linaro.org]
Sent: Thursday, October 18, 2012 8:53 PM
To: Strashko, Grygorii; Paul Walmsley
Cc: Hilman, Kevin; Tony Lindgren; linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Strashko, Grygorii
Subject: Re: [RFC PATCH 2/2] ARM: OMAP4: clock: use omap4_clks_register API
Quoting Grygorii Strashko (2012-10-18 09:38:17)
> Remove OMAP443x and OMAP446x specific clocks from omap44xx_clks
> array and add corresponding set of clocks per each SoC:
> - struct omap_clk omap44xx_clks[]; - common clocks set for all OMAP4
> - struct omap_clk omap443x_clks[]; - specific clocks set for OMAP443x
> - struct omap_clk omap446x_clks[]; - specific clocks set for OMAP446x
> and don't rely on platform specific flags any more.
>
> Use omap4_clks_register() API to register and init OMAP4 set of
> clocks.
>
> With this change, we can now safely remove CK_443X/CK_446X etc macro
> usage. It has not been done in this patch, but if the approach is OK,
> then, it is possible to do the same.
>
In addition to removing CK_443X/CK_446X you could also get rid of struct
omap_clk completely (arch/arm/plat-omap/include/plat/clkdev_omap.h) and
the CLK macro by changing the clk array to be of type struct clk_lookup
and using the CLKDEV_INIT macro.
> One additional benefit seen is that the match logic can entirely be
> skipped.
>
I wonder if splitting the tables would make initdata any easier. It
would be nice to get more functional changes out of this series
alongside the data reorganization.
Also have you looked at splitting the tables for OMAP2/3?
Regards,
Mike
> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
> ---
> arch/arm/mach-omap2/clock44xx_data.c | 40 ++++++++++++++++++----------------
> 1 file changed, 21 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
> index 6efc30c..4060c9c 100644
> --- a/arch/arm/mach-omap2/clock44xx_data.c
> +++ b/arch/arm/mach-omap2/clock44xx_data.c
> @@ -3145,10 +3145,7 @@ static struct omap_clk omap44xx_clks[] = {
> CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
> CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
> CLK(NULL, "aess_fck", &aess_fck, CK_443X),
> - CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
> - CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
> CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
> - CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
> CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
> CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
> CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
> @@ -3346,19 +3343,27 @@ static struct omap_clk omap44xx_clks[] = {
> CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
> CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
> CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
> + CLK(NULL, NULL, NULL, CK_443X),
> +};
> +
> +static struct omap_clk omap443x_clks[] = {
> + CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
> + CLK(NULL, NULL, NULL, CK_443X),
> +};
> +
> +
> +static struct omap_clk omap446x_clks[] = {
> + CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
> + CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
> + CLK(NULL, NULL, NULL, CK_446X),
> };
>
> int __init omap4xxx_clk_init(void)
> {
> - struct omap_clk *c;
> - u32 cpu_clkflg;
> -
> if (cpu_is_omap443x()) {
> cpu_mask = RATE_IN_4430;
> - cpu_clkflg = CK_443X;
> } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
> cpu_mask = RATE_IN_4460 | RATE_IN_4430;
> - cpu_clkflg = CK_446X | CK_443X;
>
> if (cpu_is_omap447x())
> pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
> @@ -3375,17 +3380,14 @@ int __init omap4xxx_clk_init(void)
> * omap2_clk_disable_clkdm_control();
> */
>
> - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
> - c++)
> - clk_preinit(c->lk.clk);
> -
> - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
> - c++)
> - if (c->cpu & cpu_clkflg) {
> - clkdev_add(&c->lk);
> - clk_register(c->lk.clk);
> - omap2_init_clk_clkdm(c->lk.clk);
> - }
> + omap2_clks_register(omap44xx_clks);
> +
> + if (cpu_is_omap443x())
> + omap2_clks_register(omap443x_clks);
> + else if (cpu_is_omap446x() || cpu_is_omap447x())
> + omap2_clks_register(omap446x_clks);
> + else
> + return 0;
>
> /* Disable autoidle on all clocks; let the PM code enable it later */
> omap_clk_disable_autoidle_all();
> --
> 1.7.9.5
^ permalink raw reply
* [PATCH RFC 02/15 v5] gpio: Add sysfs support to block GPIO API
From: Linus Walleij @ 2012-10-19 10:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <507FD4EB.1080204@antcom.de>
On Thu, Oct 18, 2012 at 12:07 PM, Roland Stigge <stigge@antcom.de> wrote:
> On 10/17/2012 09:05 PM, Greg KH wrote:
>>>
>>> + if (value != exported) {
>>> + if (value)
>>> + status = gpio_block_value_export(block);
>>> + else
>>> + status = gpio_block_value_unexport(block);
>>
>> That looks like a recipie for disaster. Why do you allow userspace to
>> do this?
>
> Exporting for gpio blocks is done as follows: writing "1" to the
> "exported" _device_ attribute of the gpio block creates the "values"
> attribute and at the same time requests the whole block (including all
> of its gpios) as "sysfs".
To me it reads like Greg's comment is basically pinpointing a flaw
in Brownell's initial design of gpio sysfs: that new sysfs files are
created and destroyed by writing into sysfs */export files from
userspace?
See commit: d8f388d8dc8d4f36539dd37c1fff62cc404ea0fc
The block GPIO stuff is just following that design pattern.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 1/3] ARM: dts: Update board files for pwm support
From: Tony Prisk @ 2012-10-19 10:38 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds pwm support to arch-vt8500 board files, and adds
the use-case of pwm-backlight.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
---
arch/arm/boot/dts/vt8500-bv07.dts | 8 ++++++++
arch/arm/boot/dts/vt8500.dtsi | 29 +++++++++++++++++++++++++++++
arch/arm/boot/dts/wm8505-ref.dts | 8 ++++++++
arch/arm/boot/dts/wm8505.dtsi | 29 +++++++++++++++++++++++++++++
arch/arm/boot/dts/wm8650-mid.dts | 8 ++++++++
arch/arm/boot/dts/wm8650.dtsi | 17 +++++++++++++----
6 files changed, 95 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
index 567cf4e..3cba367 100644
--- a/arch/arm/boot/dts/vt8500-bv07.dts
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -33,4 +33,12 @@
};
};
};
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000>;
+
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <5>;
+ };
};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index d8645e9..e196b2e 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -40,14 +40,43 @@
#address-cells = <1>;
#size-cells = <0>;
+ ref25: ref25M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
ref24: ref24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
+
+ pllb: pllb {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x204>;
+ };
+
+ clkpwm: pwm {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x348>;
+ enable-reg = <0x250>;
+ enable-bit = <14>;
+ };
};
};
+ pwm: pwm at d8220000 {
+ #pwm-cells = <2>;
+ compatible = "via,vt8500-pwm";
+ reg = <0xd8220000 0x100>;
+ clocks = <&clkpwm>;
+ };
+
timer at d8130100 {
compatible = "via,vt8500-timer";
reg = <0xd8130100 0x28>;
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
index fd4e248..f51c0ed 100644
--- a/arch/arm/boot/dts/wm8505-ref.dts
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -33,4 +33,12 @@
};
};
};
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000>;
+
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <5>;
+ };
};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index b459691..83c8ec5 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -54,14 +54,43 @@
#address-cells = <1>;
#size-cells = <0>;
+ ref25: ref25M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
ref24: ref24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
+
+ pllb: pllb {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x204>;
+ };
+
+ clkpwm: pwm {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x348>;
+ enable-reg = <0x250>;
+ enable-bit = <10>;
+ };
};
};
+ pwm: pwm at d8220000 {
+ #pwm-cells = <2>;
+ compatible = "via,vt8500-pwm";
+ reg = <0xd8220000 0x100>;
+ clocks = <&clkpwm>;
+ };
+
timer at d8130100 {
compatible = "via,vt8500-timer";
reg = <0xd8130100 0x28>;
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
index cefd938..7a05dd5 100644
--- a/arch/arm/boot/dts/wm8650-mid.dts
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -33,4 +33,12 @@
};
};
};
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000>;
+
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <5>;
+ };
};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index 83b9467..a25d240 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -75,14 +75,16 @@
reg = <0x204>;
};
- arm: arm {
+ clkpwm: pwm {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
- clocks = <&plla>;
- divisor-reg = <0x300>;
+ clocks = <&pllb>;
+ divisor-reg = <0x348>;
+ enable-reg = <0x250>;
+ enable-bit = <10>;
};
- sdhc: sdhc {
+ clksdhc: sdhc {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
@@ -94,6 +96,13 @@
};
};
+ pwm: pwm at d8220000 {
+ #pwm-cells = <2>;
+ compatible = "via,vt8500-pwm";
+ reg = <0xd8220000 0x100>;
+ clocks = <&clkpwm>;
+ };
+
timer at d8130100 {
compatible = "via,vt8500-timer";
reg = <0xd8130100 0x28>;
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/3] PWM: vt8500: Update vt8500 PWM driver support
From: Tony Prisk @ 2012-10-19 10:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350643135-13197-1-git-send-email-linux@prisktech.co.nz>
This patch updates pwm-vt8500.c to support devicetree probing and
make use of the common clock subsystem.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
---
drivers/pwm/pwm-vt8500.c | 79 ++++++++++++++++++++++++++++++----------------
1 file changed, 51 insertions(+), 28 deletions(-)
diff --git a/drivers/pwm/pwm-vt8500.c b/drivers/pwm/pwm-vt8500.c
index ad14389..c2a71ee 100644
--- a/drivers/pwm/pwm-vt8500.c
+++ b/drivers/pwm/pwm-vt8500.c
@@ -1,7 +1,8 @@
/*
* drivers/pwm/pwm-vt8500.c
*
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -21,14 +22,24 @@
#include <linux/io.h>
#include <linux/pwm.h>
#include <linux/delay.h>
+#include <linux/clk.h>
#include <asm/div64.h>
-#define VT8500_NR_PWMS 4
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+
+/*
+ * SoC architecture allocates register space for 4 PWMs but only
+ * 2 are currently implemented.
+ */
+#define VT8500_NR_PWMS 2
struct vt8500_chip {
struct pwm_chip chip;
void __iomem *base;
+ struct clk *clk;
};
#define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip)
@@ -52,7 +63,7 @@ static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
unsigned long long c;
unsigned long period_cycles, prescale, pv, dc;
- c = 25000000/2; /* wild guess --- need to implement clocks */
+ c = clk_get_rate(vt8500->clk);
c = c * period_ns;
do_div(c, 1000000000);
period_cycles = c;
@@ -107,12 +118,22 @@ static struct pwm_ops vt8500_pwm_ops = {
.owner = THIS_MODULE,
};
-static int __devinit pwm_probe(struct platform_device *pdev)
+static const struct of_device_id vt8500_pwm_dt_ids[] = {
+ { .compatible = "via,vt8500-pwm", },
+ { /* Sentinel */ }
+};
+
+static int __devinit vt8500_pwm_probe(struct platform_device *pdev)
{
struct vt8500_chip *chip;
- struct resource *r;
+ struct device_node *np = pdev->dev.of_node;
int ret;
+ if (!np) {
+ dev_err(&pdev->dev, "invalid devicetree node\n");
+ return -EINVAL;
+ }
+
chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
if (chip == NULL) {
dev_err(&pdev->dev, "failed to allocate memory\n");
@@ -123,26 +144,32 @@ static int __devinit pwm_probe(struct platform_device *pdev)
chip->chip.ops = &vt8500_pwm_ops;
chip->chip.base = -1;
chip->chip.npwm = VT8500_NR_PWMS;
+ chip->clk = of_clk_get(np, 0);
- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (r == NULL) {
- dev_err(&pdev->dev, "no memory resource defined\n");
- return -ENODEV;
+ if (!chip->clk) {
+ dev_err(&pdev->dev, "clock source not specified\n");
+ return -EINVAL;
}
- chip->base = devm_request_and_ioremap(&pdev->dev, r);
- if (chip->base == NULL)
+ chip->base = of_iomap(np, 0);
+ if (!chip->base) {
+ dev_err(&pdev->dev, "memory resource not available\n");
return -EADDRNOTAVAIL;
+ }
+
+ clk_prepare_enable(chip->clk);
ret = pwmchip_add(&chip->chip);
- if (ret < 0)
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to add pwmchip\n");
return ret;
+ }
platform_set_drvdata(pdev, chip);
return ret;
}
-static int __devexit pwm_remove(struct platform_device *pdev)
+static int __devexit vt8500_pwm_remove(struct platform_device *pdev)
{
struct vt8500_chip *chip;
@@ -150,28 +177,24 @@ static int __devexit pwm_remove(struct platform_device *pdev)
if (chip == NULL)
return -ENODEV;
+ clk_disable_unprepare(chip->clk);
+
return pwmchip_remove(&chip->chip);
}
-static struct platform_driver pwm_driver = {
+static struct platform_driver vt8500_pwm_driver = {
+ .probe = vt8500_pwm_probe,
+ .remove = __devexit_p(vt8500_pwm_remove),
.driver = {
.name = "vt8500-pwm",
.owner = THIS_MODULE,
+ .of_match_table = vt8500_pwm_dt_ids,
},
- .probe = pwm_probe,
- .remove = __devexit_p(pwm_remove),
};
-static int __init pwm_init(void)
-{
- return platform_driver_register(&pwm_driver);
-}
-arch_initcall(pwm_init);
-
-static void __exit pwm_exit(void)
-{
- platform_driver_unregister(&pwm_driver);
-}
-module_exit(pwm_exit);
+module_platform_driver(vt8500_pwm_driver);
-MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("VT8500 PWM Driver");
+MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids);
--
1.7.9.5
^ permalink raw reply related
* [PATCH 3/3] DOC: PWM: Adding binding document for via,vt8500-pwm
From: Tony Prisk @ 2012-10-19 10:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350643135-13197-1-git-send-email-linux@prisktech.co.nz>
Add a binding document describing the PWM controller found
on arch-vt8500 supported SoCs.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
---
.../devicetree/bindings/pwm/vt8500-pwm.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/vt8500-pwm.txt
diff --git a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt
new file mode 100644
index 0000000..e8ba133
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt
@@ -0,0 +1,17 @@
+VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller
+
+Required properties:
+- compatible: should be "via,vt8500-pwm"
+- reg: physical base address and length of the controller's registers
+- #pwm-cells: should be 2. The first cell specifies the per-chip index
+ of the PWM to use and the second cell is the period in nanoseconds.
+- clocks: pHandle to the PWM source clock
+
+Example:
+
+pwm1: pwm at d8220000 {
+ #pwm-cells = <2>;
+ compatible = "via,vt8500-pwm";
+ reg = <0xd8220000 0x1000>;
+ clocks = <&clkpwm>;
+};
--
1.7.9.5
^ permalink raw reply related
* [PATCH] arm/dts: am33xx rtc node
From: Afzal Mohammed @ 2012-10-19 10:50 UTC (permalink / raw)
To: linux-arm-kernel
add am33xx rtc node.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
Based on v3.7-rc1,
Dependent on series "rtc: omap dt support (for am33xx)",
(https://lkml.org/lkml/2012/10/19/163)
Tested on Beagle Bone.
arch/arm/boot/dts/am33xx.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff..356711e 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -210,5 +210,14 @@
interrupt-parent = <&intc>;
interrupts = <91>;
};
+
+ rtc {
+ compatible = "ti,da830-rtc";
+ ti,hwmods = "rtc";
+ reg = <0x44e3e000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <75
+ 76>;
+ };
};
};
--
1.7.12
^ permalink raw reply related
* [PATCH] arm/dts: am33xx rtc node
From: Mohammed, Afzal @ 2012-10-19 10:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350643825-9657-1-git-send-email-afzal@ti.com>
+ linux-omap and Daniel
On Fri, Oct 19, 2012 at 16:20:21, Mohammed, Afzal wrote:
> add am33xx rtc node.
>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> ---
>
> Based on v3.7-rc1,
> Dependent on series "rtc: omap dt support (for am33xx)",
> (https://lkml.org/lkml/2012/10/19/163)
> Tested on Beagle Bone.
>
> arch/arm/boot/dts/am33xx.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> index bb31bff..356711e 100644
> --- a/arch/arm/boot/dts/am33xx.dtsi
> +++ b/arch/arm/boot/dts/am33xx.dtsi
> @@ -210,5 +210,14 @@
> interrupt-parent = <&intc>;
> interrupts = <91>;
> };
> +
> + rtc {
> + compatible = "ti,da830-rtc";
> + ti,hwmods = "rtc";
> + reg = <0x44e3e000 0x1000>;
> + interrupt-parent = <&intc>;
> + interrupts = <75
> + 76>;
> + };
> };
> };
> --
> 1.7.12
>
>
^ permalink raw reply
* [PATCH 2/3] RTC: omap-rtc: enable pm_runtime
From: Mohammed, Afzal @ 2012-10-19 10:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EB43BD9@DBDE01.ent.ti.com>
Hi Daniel,
On Thu, Oct 18, 2012 at 22:03:13, Hiremath, Vaibhav wrote:
> On Thu, Oct 18, 2012 at 21:49:44, Daniel Mack wrote:
> > On 18.10.2012 18:12, Vaibhav Hiremath wrote:
> > > It would be really helpful if you could test these patches and ack them.
> > Ok, will do tomorrow. What's missing there is support for writing to the
> > OMAP_RTC_OSC_REG (path 3/3 in my series). Would like me to rebase the
> > functionality? I need thatkind of setup for my board ...
> This is bit tricky and required more discussion before merging it,
> let me reopen the old discussion which I had started some time back -
>
>
> RTC OSC clock is required to configure clocksource systemtimer for the
> kernel, and it is important when you get into PM related features.
>
> Please refer the below commit for more reference,
>
> http://marc.info/?l=u-boot&m=135057734713796&w=2
Newer version (v4) of omap rtc patches for am335x has been
posted, "rtc: omap dt support (for am33xx)".
In case you can test, please do it over the new series.
You would need also need DT patch that adds DT node to
test (it has been separated from the series as it is
felt that it should not be part of same series),
"arm/dts: am33xx rtc node"
If you are using mainline uboot, you would need the fix as
mentioned by Vaibhav H (as in the link he provided above),
expecting it to reach uboot mainline soon.
If the above is being attempted to achieve in Kernel it
would cause 2-3 seconds delay in boot time (else it had
to be made a module), please refer link provided by
Vaibhav H for more details.
else you can do in current mainline uboot,
mw.l 0x44e3e06c 0x83e70b13
mw.l 0x44e3e070 0x95a4f1e0
mw.b 0x44e3e054 0x48
and then boot kernel.
Regards
Afzal
^ permalink raw reply
* [RFC PATCH v3 00/16] DMA Engine support for AM33XX
From: Matt Porter @ 2012-10-19 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <B5906170F1614E41A8A28DE3B8D121433EBD29FC@DBDE01.ent.ti.com>
On Fri, Oct 19, 2012 at 10:26:20AM +0000, Bedia, Vaibhav wrote:
> Hi Matt,
>
> On Thu, Oct 18, 2012 at 18:56:39, Porter, Matt wrote:
> > Changes since v2:
> > - Rebased on 3.7-rc1
> > - Fixed bug in DT/pdata parsing first found by Gururaja
> > that turned out to be masked by some toolchains
> > - Dropped unused mach-omap2/devices.c hsmmc patch
> > - Added AM33XX crossbar DMA event mux support
> > - Added am335x-evm support
> >
> > Changes since v1:
> > - Rebased on top of mainline from 12250d8
> > - Dropped the feature removal schedule patch
> > - Implemented dma_request_slave_channel_compat() and
> > converted the mmc and spi drivers to use it
> > - Dropped unneeded #address-cells and #size-cells from
> > EDMA DT support
> > - Moved private EDMA header to linux/platform_data/ and
> > removed some unneeded definitions
> > - Fixed parsing of optional properties
> >
> > TODO:
> > - Add dmaengine support for per-channel caps so the
> > hack to set the maximum segments can be replaced with
> > a query to the dmaengine driver
> >
> > This series adds DMA Engine support for AM33xx, which uses
> > an EDMA DMAC. The EDMA DMAC has been previously supported by only
> > a private API implementation (much like the situation with OMAP
> > DMA) found on the DaVinci family of SoCs.
> >
> > The series applies on top of 3.7-rc1 and the following patches:
> >
> > - GPMC fails to reserve memory fix:
> > http://www.spinics.net/lists/linux-omap/msg79675.html
> > - TPS65910 regulator fix:
> > https://patchwork.kernel.org/patch/1593651/
> > - dmaengine DT support from Vinod's dmaengine_dt branch in
> > git://git.infradead.org/users/vkoul/slave-dma.git since
> > 027478851791df751176398be02a3b1c5f6aa824
> >
> > The approach taken is similar to how OMAP DMA is being converted to
> > DMA Engine support. With the functional EDMA private API already
> > existing in mach-davinci/dma.c, we first move that to an ARM common
> > area so it can be shared. Adding DT and runtime PM support to the
> > private EDMA API implementation allows it to run on AM33xx. AM33xx
> > *only* boots using DT so we leverage Jon's generic DT DMA helpers to
> > register EDMA DMAC with the of_dma framework and then add support
> > for calling the dma_request_slave_channel() API to both the mmc
> > and spi drivers.
> >
> > With this series both BeagleBone and the AM335x EVM have working
> > MMC and SPI support.
> >
> > This is tested on BeagleBone with a SPI framebuffer driver and MMC
> > rootfs. A trivial gpio DMA event misc driver was used to test the
> > crossbar DMA event support. It is also tested on the AM335x EVM
> > with the onboard SPI flash and MMC rootfs. The branch at
> > https://github.com/ohporter/linux/tree/edma-dmaengine-v3 has the
> > complete series, dependencies, and some test drivers/defconfigs.
> >
>
> I didn't see all the patches that you posted on edma-dmaengine-v3
> but I do seem them on edma-dmaengine-am33xx-v3 branch.
I see I referenced the wrong branch in the cover letter. Thanks for
testing and noticing this. Sorry to make you hunt for the correct
branch in that repo. ;)
https://github.com/ohporter/linux/tree/edma-dmaengine-am33xx-v3
is indeed the correct branch for those wanting to pull this in or
grab some of the not-to-be-merged drivers I used for testing.
> I added a couple of patches to enable earlyprintk and build the DTB
> appended kernel image uImage-dtb.am335x-evm
>
> Here's what i see
>
> [...]
<snip>
> [ 0.175354] edma: probe of 49000000.edma failed with error -16
I missed an uninitialized pdata case in the bug fixes mentioned in
the changelog and the folks previously failing the same way didn't
hit the case I suspect you are hitting. Can you try this and let me
know how it works?
Thanks,
Matt
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index b761b7a..b43b327 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1619,7 +1619,7 @@ static int __init edma_probe(struct platform_device *pdev)
if (node) {
pdata = devm_kzalloc(dev,
- sizeof(struct edma_soc_info),
+ EDMA_MAX_CC*sizeof(struct edma_soc_info),
GFP_KERNEL);
edma_of_parse_dt(dev, node, pdata);
info = &pdata;
^ permalink raw reply related
* [PATCH] GPIO: vt8500: Add extended gpio bank for WM8505/WM8650
From: Linus Walleij @ 2012-10-19 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350497893-25106-1-git-send-email-linux@prisktech.co.nz>
On Wed, Oct 17, 2012 at 8:18 PM, Tony Prisk <linux@prisktech.co.nz> wrote:
> These SoC's have an extended bank of GPIO's seperate to the main
> GPIO block. This patch adds the additional 5 GPIO's located in this
> block which control I2C and PWMOUT.
>
> Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Applied.
Thanks!
Linus Walleij
^ permalink raw reply
* [PATCH v2] arm/dts: AM33XX: Add SPI device tree data
From: Matt Porter @ 2012-10-19 11:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50810E2F.5@ti.com>
On Fri, Oct 19, 2012 at 10:24:15AM +0200, Benoit Cousson wrote:
> Hi Avinash,
>
> This look good to me except the: status = "disabled".
>
> The "disabled" should be reserved for variant that does not contain the IP.
> Is it the case here?
http://comments.gmane.org/gmane.linux.drivers.devicetree/18968 is what
I've been going by with the DTS support in the EDMA dmaengine series. It
does make the most sense to only enable what you need in the
<board>.dts.
-Matt
> On 09/18/2012 07:30 AM, Philip, Avinash wrote:
> > Add McSPI data node to AM33XX device tree file. The McSPI module (and so
> > as the driver) is reused from OMAP4.
> >
> > Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
> > Tested-by: Matt Porter <mporter@ti.com>
> > ---
> > Changes since v1:
> > - Corrected reg offset in reg DT entry.
> >
> > :100644 100644 ff3badb... 065fd54... M arch/arm/boot/dts/am33xx.dtsi
> > arch/arm/boot/dts/am33xx.dtsi | 25 +++++++++++++++++++++++++
> > 1 files changed, 25 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> > index ff3badb..065fd54 100644
> > --- a/arch/arm/boot/dts/am33xx.dtsi
> > +++ b/arch/arm/boot/dts/am33xx.dtsi
> > @@ -219,5 +219,30 @@
> > interrupt-parent = <&intc>;
> > interrupts = <91>;
> > };
> > +
> > + spi0: spi at 48030000 {
> > + compatible = "ti,omap4-mcspi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x48030000 0x400>;
> > + interrupt-parent = <&intc>;
> > + interrupt = <65>;
> > + ti,spi-num-cs = <2>;
> > + ti,hwmods = "spi0";
> > + status = "disabled";
> > +
> > + };
> > +
> > + spi1: spi at 481a0000 {
> > + compatible = "ti,omap4-mcspi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x481a0000 0x400>;
> > + interrupt-parent = <&intc>;
> > + interrupt = <125>;
> > + ti,spi-num-cs = <2>;
> > + ti,hwmods = "spi1";
> > + status = "disabled";
> > + };
> > };
> > };
> >
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox