* [PATCH 3/8] i2c: omap: fix error checking
From: Felipe Balbi @ 2012-10-25 10:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5089156E.7020701@amarulasolutions.com>
Hi,
On Thu, Oct 25, 2012 at 12:33:18PM +0200, Michael Trimarchi wrote:
> >>> @@ -587,9 +587,9 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
> >>> goto err_i2c_init;
> >>> }
> >>>
> >>> - /* We have an error */
> >>> - if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
> >>> - OMAP_I2C_STAT_XUDF)) {
> >>> + if ((dev->cmd_err & OMAP_I2C_STAT_AL)
> >>> + || (dev->cmd_err & OMAP_I2C_STAT_ROVR)
> >>> + || (dev->cmd_err & OMAP_I2C_STAT_XUDF)) {
> >>
> >> Sorry, what is the difference? I didn't understand the optimisation
> >> and why now is more clear. Can you just add a comment?
> >
> > semantically they're not the same, right ? We want to check if each of
> > those bits are set, not if all of them are set together.
> >
> > my 2 cents.
>
> You are doing the same thing, but of course is better with just one
I never claimed the contrary. I said *semantically* they're not the
same.
> *if* as before . A general rule is: when you have logic expression you
We still have a single *if* and I'm sure compiler will optimize that
expression as much as it likes.
> can use undefined states to simplify the logic.
don't-care is not the same as undefined states.
--
balbi
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* [PATCH 1/2] i2c: omap: re-factor omap_i2c_init function
From: Felipe Balbi @ 2012-10-25 10:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351160586-12306-2-git-send-email-shubhrajyoti@ti.com>
Hi,
(a small top-post here, don't forget to keep the patch version in the
subject, I think this is v3 already, so next patch should be v4)
On Thu, Oct 25, 2012 at 03:53:05PM +0530, Shubhrajyoti D wrote:
> re-factor omap_i2c_init() so that we can re-use it for resume.
> While at it also remove the bufstate variable as we write it
> in omap_i2c_resize_fifo for every transfer.
>
> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
> ---
> drivers/i2c/busses/i2c-omap.c | 71 ++++++++++++++++++----------------------
> 1 files changed, 32 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 5e5cefb..3d400b1 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -209,7 +209,6 @@ struct omap_i2c_dev {
> u16 pscstate;
> u16 scllstate;
> u16 sclhstate;
> - u16 bufstate;
> u16 syscstate;
> u16 westate;
> u16 errata;
> @@ -285,9 +284,31 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
> }
> }
>
> +static void __omap_i2c_init(struct omap_i2c_dev *dev)
> +{
> +
> + omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
> + /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
> + omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
> +
> + /* SCL low and high time values */
> + omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
> + omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
> + if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
> + omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
> + /* Take the I2C module out of reset: */
> + omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
> + /*
> + * Don't write to this register if the IE state is 0 as it can
> + * cause deadlock.
> + */
> + if (dev->iestate)
> + omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
you still miss the extra blank lines here. Try something like below:
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
/* SCL low and high time values */
omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
/* Take the I2C module out of reset: */
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
/*
* Don't write to this register if the IE state is 0 as it can
* cause deadlock.
*/
if (dev->iestate)
omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
--
balbi
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^ permalink raw reply
* [PATCH 2/2] i2c: omap: make reset a seperate function
From: Felipe Balbi @ 2012-10-25 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351160586-12306-3-git-send-email-shubhrajyoti@ti.com>
Hi,
On Thu, Oct 25, 2012 at 03:53:06PM +0530, Shubhrajyoti D wrote:
> Implement reset as a seperate function.
> This will enable us to make sure that we don't do the
> calculation again on every transfer.
> Also at probe the reset is not added as the hwmod is doing that
> for us.
since you're touching registers which supposedly only hwmod should
touch, you ought to Cc Benoit to make sure he knows what's you're doing
here. I'm adding him to Cc
> @@ -592,7 +597,8 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
> if (timeout == 0) {
> dev_err(dev->dev, "controller timed out\n");
> ret = -ETIMEDOUT;
> - omap_i2c_init(dev);
> + omap_i2c_reset(dev);
> + __omap_i2c_init(dev);
> goto out;
> }
>
> @@ -603,7 +609,8 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
> || (dev->cmd_err & OMAP_I2C_STAT_ROVR)
> || (dev->cmd_err & OMAP_I2C_STAT_XUDF)) {
> ret = -EIO;
> - omap_i2c_init(dev);
> + omap_i2c_reset(dev);
> + __omap_i2c_init(dev);
> goto out;
> }
>
> @@ -621,7 +628,8 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
> return 0;
>
> ret = -EREMOTEIO;
> - omap_i2c_init(dev);
> + omap_i2c_reset(dev);
> + __omap_i2c_init(dev);
eventually we need to try to forcefully trigger these errors above
(nack, overflow, underflow and arbitration lost) and try to make sure if
actually need to reset the controller all the time. I find it really odd
that we're always resetting the IP in every error condition without
actually trying to figure out what's wrong with the driver (if there is
something wrong with the driver, of course).
--
balbi
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* [PATCH 0/3] Use generic helper scu_power_mode()
From: Bastian Hecht @ 2012-10-25 10:58 UTC (permalink / raw)
To: linux-arm-kernel
Reposted to include the arch/arm mailing list.
The shmobile series implements its own code for setting the SCU power
register of the ARM MPCore. It uses 32-bit wide access and thus needs
locking as multiple CPUs might access it simultaneously for change. There is
already a small helper function that avoids the overhead by using 8-bit
wide access: As every CPU only accesses its own field we can drop the
lock and use it.
Bastian Hecht (3):
ARM: shmobile: emev2: Replace modify_scu_cpu_psr with scu_power_mode
ARM: shmobile: sh73a0: Replace modify_scu_cpu_psr with scu_power_mode
ARM: shmobile: r8a7779: Replace modify_scu_cpu_psr with
scu_power_mode
arch/arm/mach-shmobile/smp-emev2.c | 22 ++--------------------
arch/arm/mach-shmobile/smp-r8a7779.c | 25 +++----------------------
arch/arm/mach-shmobile/smp-sh73a0.c | 23 ++---------------------
3 files changed, 7 insertions(+), 63 deletions(-)
--
1.7.9.5
^ permalink raw reply
* [PATCH 1/3] ARM: shmobile: emev2: Replace modify_scu_cpu_psr with scu_power_mode
From: Bastian Hecht @ 2012-10-25 10:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351162702-8391-1-git-send-email-hechtb@gmail.com>
We can remove the extra code of modify_scu_cpu_psr() and use the cleaner
generic ARM helper scu_power_mode(). As every CPU only deals with its
own power register and scu_power_mode() operates with 8-bit accesses,
we save the locking overhead too.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
---
arch/arm/mach-shmobile/smp-emev2.c | 22 ++--------------------
1 file changed, 2 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index f674562..535426c 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -32,24 +32,8 @@
#define EMEV2_SCU_BASE 0x1e000000
-static DEFINE_SPINLOCK(scu_lock);
static void __iomem *scu_base;
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
- unsigned long tmp;
-
- /* we assume this code is running on a different cpu
- * than the one that is changing coherency setting */
- spin_lock(&scu_lock);
- tmp = readl(scu_base + 8);
- tmp &= ~clr;
- tmp |= set;
- writel(tmp, scu_base + 8);
- spin_unlock(&scu_lock);
-
-}
-
static unsigned int __init emev2_get_core_count(void)
{
if (!scu_base) {
@@ -95,7 +79,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
- modify_scu_cpu_psr(0, 3 << (cpu * 8));
+ scu_power_mode(scu_base, 0);
/* Tell ROM loader about our vector (in headsmp.S) */
emev2_set_boot_vector(__pa(shmobile_secondary_vector));
@@ -106,12 +90,10 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
{
- int cpu = cpu_logical_map(0);
-
scu_enable(scu_base);
/* enable cache coherency on CPU0 */
- modify_scu_cpu_psr(0, 3 << (cpu * 8));
+ scu_power_mode(scu_base, 0);
}
static void __init emev2_smp_init_cpus(void)
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/3] ARM: shmobile: sh73a0: Replace modify_scu_cpu_psr with scu_power_mode
From: Bastian Hecht @ 2012-10-25 10:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351162702-8391-1-git-send-email-hechtb@gmail.com>
We can remove the extra code of modify_scu_cpu_psr() and use the cleaner
generic ARM helper scu_power_mode(). As every CPU only deals with its
own power register and scu_power_mode() operates with 8-bit accesses,
we save the locking overhead too.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
---
arch/arm/mach-shmobile/smp-sh73a0.c | 23 ++---------------------
1 file changed, 2 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 624f00f..96ddb97 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -41,9 +41,6 @@ static void __iomem *scu_base_addr(void)
return (void __iomem *)0xf0000000;
}
-static DEFINE_SPINLOCK(scu_lock);
-static unsigned long tmp;
-
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
void __init sh73a0_register_twd(void)
@@ -52,20 +49,6 @@ void __init sh73a0_register_twd(void)
}
#endif
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
- void __iomem *scu_base = scu_base_addr();
-
- spin_lock(&scu_lock);
- tmp = __raw_readl(scu_base + 8);
- tmp &= ~clr;
- tmp |= set;
- spin_unlock(&scu_lock);
-
- /* disable cache coherency after releasing the lock */
- __raw_writel(tmp, scu_base + 8);
-}
-
static unsigned int __init sh73a0_get_core_count(void)
{
void __iomem *scu_base = scu_base_addr();
@@ -83,7 +66,7 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
- modify_scu_cpu_psr(0, 3 << (cpu * 8));
+ scu_power_mode(scu_base_addr(), 0);
if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
__raw_writel(1 << cpu, WUPCR); /* wake up */
@@ -95,8 +78,6 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
{
- int cpu = cpu_logical_map(0);
-
scu_enable(scu_base_addr());
/* Map the reset vector (in headsmp.S) */
@@ -104,7 +85,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
__raw_writel(__pa(shmobile_secondary_vector), SBAR);
/* enable cache coherency on CPU0 */
- modify_scu_cpu_psr(0, 3 << (cpu * 8));
+ scu_power_mode(scu_base_addr(), 0);
}
static void __init sh73a0_smp_init_cpus(void)
--
1.7.9.5
^ permalink raw reply related
* [PATCH 3/3] ARM: shmobile: r8a7779: Replace modify_scu_cpu_psr with scu_power_mode
From: Bastian Hecht @ 2012-10-25 10:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351162702-8391-1-git-send-email-hechtb@gmail.com>
We can remove the extra code of modify_scu_cpu_psr() and use the cleaner
generic ARM helper scu_power_mode(). As every CPU only deals with its
own power register and scu_power_mode() operates with 8-bit accesses,
we save the locking overhead too.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
---
arch/arm/mach-shmobile/smp-r8a7779.c | 25 +++----------------------
1 file changed, 3 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 2ce6af9..9def0f2 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -61,9 +61,6 @@ static void __iomem *scu_base_addr(void)
return (void __iomem *)0xf0000000;
}
-static DEFINE_SPINLOCK(scu_lock);
-static unsigned long tmp;
-
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
@@ -73,20 +70,6 @@ void __init r8a7779_register_twd(void)
}
#endif
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
- void __iomem *scu_base = scu_base_addr();
-
- spin_lock(&scu_lock);
- tmp = __raw_readl(scu_base + 8);
- tmp &= ~clr;
- tmp |= set;
- spin_unlock(&scu_lock);
-
- /* disable cache coherency after releasing the lock */
- __raw_writel(tmp, scu_base + 8);
-}
-
static unsigned int __init r8a7779_get_core_count(void)
{
void __iomem *scu_base = scu_base_addr();
@@ -102,7 +85,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
cpu = cpu_logical_map(cpu);
/* disable cache coherency */
- modify_scu_cpu_psr(3 << (cpu * 8), 0);
+ scu_power_mode(scu_base_addr(), 3);
if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
ch = r8a7779_ch_cpu[cpu];
@@ -145,7 +128,7 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
- modify_scu_cpu_psr(0, 3 << (cpu * 8));
+ scu_power_mode(scu_base_addr(), 0);
if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
ch = r8a7779_ch_cpu[cpu];
@@ -158,15 +141,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
{
- int cpu = cpu_logical_map(0);
-
scu_enable(scu_base_addr());
/* Map the reset vector (in headsmp.S) */
__raw_writel(__pa(shmobile_secondary_vector), AVECR);
/* enable cache coherency on CPU0 */
- modify_scu_cpu_psr(0, 3 << (cpu * 8));
+ scu_power_mode(scu_base_addr(), 0);
r8a7779_pm_init();
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 2/3] serial: mxs-auart: add the DMA support for mx28
From: Vinod Koul @ 2012-10-25 11:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5089033F.9040100@freescale.com>
On Thu, 2012-10-25 at 17:15 +0800, Huang Shijie wrote:
> yes. I have to setup the register. Could you told me which API is the
> right API?
dmaengine_slave_config() should be used to send the slave specfic
parameters
>
> It seems to the mxs-dma needs a patch again.
Yes definitely :)
--
Vinod Koul
Intel Corp.
^ permalink raw reply
* [PATCH 08/16] ARM: OMAP2: Move plat/menelaus.h to linux/mfd/menelaus.h
From: Samuel Ortiz @ 2012-10-25 11:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121004220451.26676.62349.stgit@muffinssi.local>
Hi Tony,
On Thu, Oct 04, 2012 at 03:04:52PM -0700, Tony Lindgren wrote:
> We can move menelaus.h to live with other mfd headers to
> get it out of plat for ARM common zImage support.
>
> Cc: Samuel Ortiz <sameo@linux.intel.com>
> Signed-off-by: Tony Lindgren <tony@atomide.com>
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* Possible regression in arm/io.h
From: Will Deacon @ 2012-10-25 11:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351148122.2507.63.camel@sauron.fi.intel.com>
On Thu, Oct 25, 2012 at 07:55:22AM +0100, Artem Bityutskiy wrote:
> On Wed, 2012-10-24 at 11:52 +0100, Will Deacon wrote:
> > (a) Understand what has changed in GCC to cause this error to start
> > cropping up.
>
> This is about already quite old gcc 4.6.3, which I use for about 4 last
> kernel releases already. So it is only the kernel that changed.
Looks like it's broken with gcc 4.7 too, so it might be that it's never
worked. The problem seems to be that offsettable addresses are assumed by
GCC to have a 12-bit immediate range, which isn't true for half- and double-
work accessors, so GAS barfs when presented with the final (invalid) code.
Since we don't have double-word I/O accessors, we can just fallback to "Q"
for the half-word case:
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 35c1ed8..42f042e 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -64,7 +64,7 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
static inline void __raw_writew(u16 val, volatile void __iomem *addr)
{
asm volatile("strh %1, %0"
- : "+Qo" (*(volatile u16 __force *)addr)
+ : "+Q" (*(volatile u16 __force *)addr)
: "r" (val));
}
@@ -72,7 +72,7 @@ static inline u16 __raw_readw(const volatile void __iomem *addr)
{
u16 val;
asm volatile("ldrh %1, %0"
- : "+Qo" (*(volatile u16 __force *)addr),
+ : "+Q" (*(volatile u16 __force *)addr),
"=r" (val));
return val;
}
but this has the downside of *always* generating the target address into a
register and then using the basic [rN] addressing mode. A simple example
being smsc911x_rx_readfifo, where we see:
c021bbe4: e1d230b2 ldrh r3, [r2, #2]
changed into:
c021bd50: e2820002 add r0, r2, #2
c021bd54: e1d030b0 ldrh r3, [r0]
which sucks, frankly. Unfortunately, GCC doesn't give us another constraint
that we can use for this, so I think we just have to grin and bear it.
Will
^ permalink raw reply related
* [PATCH v5 7/7] ARM: davinci: da850 evm: register uio_pruss device
From: Sekhar Nori @ 2012-10-25 11:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121008135442.GS11149@beef>
On 10/8/2012 7:24 PM, Matt Porter wrote:
> Registers the uio_pruss platform device on the DA850 EVM.
>
> Tested on AM180x-EVM using the PRU_memAccessPRUDataRam and
> PRU_memAccessL3andDDR examples from the PRU userspace tools
> available from http://www.ti.com/tool/sprc940
>
> Signed-off-by: Matt Porter <mporter@ti.com>
> ---
> arch/arm/mach-davinci/board-da850-evm.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
> index 7359375..9e7f954 100644
> --- a/arch/arm/mach-davinci/board-da850-evm.c
> +++ b/arch/arm/mach-davinci/board-da850-evm.c
> @@ -31,6 +31,7 @@
> #include <linux/platform_data/mtd-davinci.h>
> #include <linux/platform_data/mtd-davinci-aemif.h>
> #include <linux/platform_data/spi-davinci.h>
> +#include <linux/platform_data/uio_pruss.h>
> #include <linux/regulator/machine.h>
> #include <linux/regulator/tps6507x.h>
> #include <linux/spi/spi.h>
> @@ -1339,6 +1340,11 @@ static __init void da850_evm_init(void)
> pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
> ret);
>
> + ret = da8xx_register_uio_pruss();
> + if (ret)
> + pr_warning("da850_evm_init: pruss initialization failed: %d\n",
So this gave a checkpatch warning asking you to use pr_warn() instead. I
fixed this locally.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH 1/2] ARM: mach-imx: imx53.dtsi: pinctl update
From: Roland Stigge @ 2012-10-25 11:26 UTC (permalink / raw)
To: linux-arm-kernel
This patch supplements pinctl support on i.MX53.
Signed-off-by: Roland Stigge <stigge@antcom.de>
---
arch/arm/boot/dts/imx53.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
--- linux-2.6.orig/arch/arm/boot/dts/imx53.dtsi
+++ linux-2.6/arch/arm/boot/dts/imx53.dtsi
@@ -316,6 +316,24 @@
};
};
+ can1 {
+ pinctrl_can1_1: can1grp-1 {
+ fsl,pins = <
+ 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
+ 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
+ >;
+ };
+ };
+
+ can2 {
+ pinctrl_can2_1: can2grp-1 {
+ fsl,pins = <
+ 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
+ 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
+ >;
+ };
+ };
+
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
@@ -334,6 +352,15 @@
};
};
+ i2c3 {
+ pinctrl_i2c3_1: i2c3grp-1 {
+ fsl,pins = <
+ 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
+ 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
+ >;
+ };
+ };
+
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
@@ -369,6 +396,25 @@
>;
};
};
+
+ uart4 {
+ pinctrl_uart4_1: uart4grp-1 {
+ fsl,pins = <
+ 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
+ 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
+ >;
+ };
+ };
+
+ uart5 {
+ pinctrl_uart5_1: uart5grp-1 {
+ fsl,pins = <
+ 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
+ 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
+ >;
+ };
+ };
+
};
uart1: serial at 53fbc000 {
^ permalink raw reply
* [PATCH 2/2] ARM: mach-imx: CAN clock fix for i.MX53
From: Roland Stigge @ 2012-10-25 11:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351164400-27940-1-git-send-email-stigge@antcom.de>
This patch fixes CAN clocking on i.MX53.
Signed-off-by: Roland Stigge <stigge@antcom.de>
---
arch/arm/mach-imx/clk-imx51-imx53.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- linux-2.6.orig/arch/arm/mach-imx/clk-imx51-imx53.c
+++ linux-2.6/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -426,10 +426,10 @@ int __init mx53_clocks_init(unsigned lon
clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
- clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
- clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
- clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
- clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
+ clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR4, 6);
+ clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
+ clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 6);
+ clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
for (i = 0; i < ARRAY_SIZE(clk); i++)
^ permalink raw reply
* [PATCH 1/2] arm: mvebu: increase atomic coherent pool size for armada 370/XP
From: Arnd Bergmann @ 2012-10-25 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351086561-13569-2-git-send-email-gregory.clement@free-electrons.com>
On Wednesday 24 October 2012, Gregory CLEMENT wrote:
> For Armada 370/XP we have the same problem that for the commit
> cb01b63, so we applied the same solution: "The default 256 KiB
> coherent pool may be too small for some of the Kirkwood devices, so
> increase it to make sure that devices will be able to allocate their
> buffers with GFP_ATOMIC flag"
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Do you know why the ATA driver needs this? I find it surprising that
it's necessary, so I'd like to make sure we're not just working around
a device driver bug here.
Arnd
^ permalink raw reply
* [PATCH] watchdog: Support imx watchdog on SOC_IMX53
From: Roland Stigge @ 2012-10-25 11:28 UTC (permalink / raw)
To: linux-arm-kernel
This patch fixes watchdog support after devicetree switch for imx53
Signed-off-by: Roland Stigge <stigge@antcom.de>
---
arch/arm/mach-imx/Kconfig | 1 +
1 file changed, 1 insertion(+)
--- linux-2.6.orig/arch/arm/mach-imx/Kconfig
+++ linux-2.6/arch/arm/mach-imx/Kconfig
@@ -739,6 +739,7 @@ config SOC_IMX53
select ARCH_MX5
select ARCH_MX53
select HAVE_CAN_FLEXCAN if CAN
+ select IMX_HAVE_PLATFORM_IMX2_WDT
select PINCTRL
select PINCTRL_IMX53
select SOC_IMX5
^ permalink raw reply
* [PATCH v4 0/7] uio_pruss cleanup and platform support
From: Sekhar Nori @ 2012-10-25 11:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121024165436.GG1855@beef>
On Wed, Oct 24, 2012 at 10:24 PM, Matt Porter <mporter@ti.com> wrote:
> On Mon, Oct 08, 2012 at 04:27:20PM +0530, Sekhar Nori wrote:
>> On 10/5/2012 10:34 PM, Matt Porter wrote:
>>
>> > This series enables uio_pruss on DA850 and removes use of the
>> > private SRAM API by the driver. The driver previously was not
>> > enabled by any platform and the private SRAM API was accessing
>> > an invalid SRAM bank.
>> >
>> > It is regression tested on AM180x EVM with suspend/resume due
>> > to the new use of the shared SRAM for both PM and PRUSS. The
>> > uio_pruss driver is tested on the same platform using the
>> > PRU_memAccessPRUDataRam and PRU_memAccessL3andDDR examples from
>> > the PRU userspace tools available from http://www.ti.com/tool/sprc940
>>
>> I applied patches 2/7, 3/7 and 6/7 of this series for v3.8. I have some
>> comments on the board patch. Rest of the patches depend on acceptance of
>> 1/7 so I will take them only after that is accepted.
>
> Ok, Hans has accepted 1/7, will you take the entire series through the
> Davinci tree?
Yes.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH 2/8] i2c: omap: reorder exit path of omap_i2c_xfer_msg()
From: Shubhrajyoti Datta @ 2012-10-25 11:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350899218-13624-3-git-send-email-balbi@ti.com>
On Mon, Oct 22, 2012 at 3:16 PM, Felipe Balbi <balbi@ti.com> wrote:
> just a cleanup patch trying to make exit path
> more straightforward. No changes otherwise.
>
> Signed-off-by: Felipe Balbi <balbi@ti.com>
> ---
> drivers/i2c/busses/i2c-omap.c | 26 +++++++++++++++++---------
> 1 file changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index c07d9c4..bea0277 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -505,6 +505,7 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
> {
> struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
> unsigned long timeout;
> + int ret;
> u16 w;
>
> dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
> @@ -582,31 +583,38 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
> dev->buf_len = 0;
> if (timeout == 0) {
> dev_err(dev->dev, "controller timed out\n");
> - omap_i2c_init(dev);
> - return -ETIMEDOUT;
> + ret = -ETIMEDOUT;
> + goto err_i2c_init;
> }
>
> - if (likely(!dev->cmd_err))
> - return 0;
> -
> /* We have an error */
> if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
> OMAP_I2C_STAT_XUDF)) {
> - omap_i2c_init(dev);
> - return -EIO;
> + ret = -EIO;
> + goto err_i2c_init;
> }
>
> if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
> if (msg->flags & I2C_M_IGNORE_NAK)
> return 0;
> +
> if (stop) {
> w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
> w |= OMAP_I2C_CON_STP;
> omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
> }
> - return -EREMOTEIO;
> +
> + ret = -EREMOTEIO;
> + goto err;
This adds reset to nack may be that can be removed.
> }
> - return -EIO;
> +
> + return 0;
> +
> +err_i2c_init:
> + omap_i2c_init(dev);
> +
> +err:
> + return ret;
> }
>
>
> --
> 1.8.0.rc0
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-i2c" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 1/2] arm: mvebu: increase atomic coherent pool size for armada 370/XP
From: Thomas Petazzoni @ 2012-10-25 11:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201210251127.36960.arnd@arndb.de>
Arnd,
On Thu, 25 Oct 2012 11:27:36 +0000, Arnd Bergmann wrote:
> On Wednesday 24 October 2012, Gregory CLEMENT wrote:
> > For Armada 370/XP we have the same problem that for the commit
> > cb01b63, so we applied the same solution: "The default 256 KiB
> > coherent pool may be too small for some of the Kirkwood devices, so
> > increase it to make sure that devices will be able to allocate their
> > buffers with GFP_ATOMIC flag"
> >
> > Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>
> Do you know why the ATA driver needs this? I find it surprising that
> it's necessary, so I'd like to make sure we're not just working around
> a device driver bug here.
The sata_mv driver create dma_pool and allocate objects from them, and
all the memory allocated for dma_pools is allocated using
dma_alloc_coherent(), and I guess the driver is using too much of them.
Seems like the driver is too lazy and allocates everything coherent to
avoid the hassle of doing dma_map/dma_unmap operations when needed, but
I haven't looked in details at the driver yet to see if it would be
possible to switch those DMA coherent allocations into non-coherent
allocations + appropriate calls to the DMA operations.
That said, that's for sure a larger task than just enabling SATA on
Armada 370/XP, so I would advocate to handle this problem separately.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH] arm: bcm2835: remove useless variables from Makefile.boot
From: Thomas Petazzoni @ 2012-10-25 11:59 UTC (permalink / raw)
To: linux-arm-kernel
Neither params_phys-y nor initrd_phys-y are needed when booting with a
Device Tree. Those values are passed through the Device Tree blob. So
get rid of those variable definitions from Makefile.boot.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-bcm2835/Makefile.boot | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/mach-bcm2835/Makefile.boot b/arch/arm/mach-bcm2835/Makefile.boot
index 2d30e17..b327175 100644
--- a/arch/arm/mach-bcm2835/Makefile.boot
+++ b/arch/arm/mach-bcm2835/Makefile.boot
@@ -1,3 +1 @@
- zreladdr-y := 0x00008000
-params_phys-y := 0x00000100
-initrd_phys-y := 0x00800000
+zreladdr-y := 0x00008000
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/8] i2c: omap: reorder exit path of omap_i2c_xfer_msg()
From: Felipe Balbi @ 2012-10-25 12:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAM=Q2cvUeLbS20HScrGTOcraSUrCzhzCi8MQLxd9MOb_7ZFFYA@mail.gmail.com>
Hi,
On Thu, Oct 25, 2012 at 05:10:10PM +0530, Shubhrajyoti Datta wrote:
> On Mon, Oct 22, 2012 at 3:16 PM, Felipe Balbi <balbi@ti.com> wrote:
> > just a cleanup patch trying to make exit path
> > more straightforward. No changes otherwise.
> >
> > Signed-off-by: Felipe Balbi <balbi@ti.com>
> > ---
> > drivers/i2c/busses/i2c-omap.c | 26 +++++++++++++++++---------
> > 1 file changed, 17 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> > index c07d9c4..bea0277 100644
> > --- a/drivers/i2c/busses/i2c-omap.c
> > +++ b/drivers/i2c/busses/i2c-omap.c
> > @@ -505,6 +505,7 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
> > {
> > struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
> > unsigned long timeout;
> > + int ret;
> > u16 w;
> >
> > dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
> > @@ -582,31 +583,38 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
> > dev->buf_len = 0;
> > if (timeout == 0) {
> > dev_err(dev->dev, "controller timed out\n");
> > - omap_i2c_init(dev);
> > - return -ETIMEDOUT;
> > + ret = -ETIMEDOUT;
> > + goto err_i2c_init;
> > }
> >
> > - if (likely(!dev->cmd_err))
> > - return 0;
> > -
> > /* We have an error */
> > if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
> > OMAP_I2C_STAT_XUDF)) {
> > - omap_i2c_init(dev);
> > - return -EIO;
> > + ret = -EIO;
> > + goto err_i2c_init;
> > }
> >
> > if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
> > if (msg->flags & I2C_M_IGNORE_NAK)
> > return 0;
> > +
> > if (stop) {
> > w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
> > w |= OMAP_I2C_CON_STP;
> > omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
> > }
> > - return -EREMOTEIO;
> > +
> > + ret = -EREMOTEIO;
> > + goto err;
>
> This adds reset to nack may be that can be removed.
great catch. I will respin this series.
thanks
--
balbi
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^ permalink raw reply
* [PATCH V4 1/5] ARM: dts: OMAP: Add timer nodes
From: Hiremath, Vaibhav @ 2012-10-25 12:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50880C19.2090508@ti.com>
On Wed, Oct 24, 2012 at 21:11:13, Cousson, Benoit wrote:
> Hi Jon,
>
> On 10/19/2012 04:59 PM, Jon Hunter wrote:
> > Add the 12 GP timers nodes present in OMAP2.
> > Add the 12 GP timers nodes present in OMAP3.
> > Add the 11 GP timers nodes present in OMAP4.
> > Add the 7 GP timers nodes present in AM33xx.
> >
> > Add documentation for timer properties specific to OMAP.
> >
> > Thanks to Vaibhav Hiremath for creating the AM33xx timer nodes. I have modified
> > Vaibhav's original nodes adding information on which timers support a PWM
> > output.
> >
> > Cc: Benoit Cousson <b-cousson@ti.com>
> > Signed-off-by: Jon Hunter <jon-hunter@ti.com>
>
> I updated the patch to remove the interrupt-parent from the DTS nodes and the documentation, as discussed on the list in the context of OMAP5 DTS for GPIO.
>
> If you are OK with that version, I'll push it to Tony along with the others DTS patches.
>
> Regards,
> Benoit
>
> ---
> From 531cc8142ecd6da7929628772c4035dcf7996fef Mon Sep 17 00:00:00 2001
> From: Jon Hunter <jon-hunter@ti.com>
> Date: Fri, 19 Oct 2012 09:59:00 -0500
> Subject: [PATCH] ARM: dts: OMAP: Add timer nodes
>
> Add the 12 GP timers nodes present in OMAP2.
> Add the 12 GP timers nodes present in OMAP3.
> Add the 11 GP timers nodes present in OMAP4.
> Add the 7 GP timers nodes present in AM33xx.
>
> Add documentation for timer properties specific to OMAP.
>
> Thanks to Vaibhav Hiremath for creating the AM33xx timer nodes. I have modified
> Vaibhav's original nodes adding information on which timers support a PWM
> output.
>
> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
> [b-cousson at ti.com: Remove the interrupt-parent from nodes]
> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
> ---
> .../devicetree/bindings/arm/omap/timer.txt | 31 +++++++
> arch/arm/boot/dts/am33xx.dtsi | 54 +++++++++++
> arch/arm/boot/dts/omap2.dtsi | 85 +++++++++++++++++
> arch/arm/boot/dts/omap2420.dtsi | 8 ++
> arch/arm/boot/dts/omap2430.dtsi | 8 ++
> arch/arm/boot/dts/omap3.dtsi | 95 ++++++++++++++++++++
> arch/arm/boot/dts/omap4.dtsi | 86 ++++++++++++++++++
> 7 files changed, 367 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/omap/timer.txt
>
Benoit,
I have boot tested this on BeagleBone, so,
Tested-By: Vaibhav Hiremath <hvaibhav@ti.com>
Thanks,
Vaibhav
> diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt
> new file mode 100644
> index 0000000..b073d89
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/omap/timer.txt
> @@ -0,0 +1,31 @@
> +OMAP Timer bindings
> +
> +Required properties:
> +- compatible: Must be "ti,omap2-timer" for OMAP2+ controllers.
> +- reg: Contains timer register address range (base address and
> + length).
> +- interrupts: Contains the interrupt information for the timer. The
> + format is being dependent on which interrupt controller
> + the OMAP device uses.
> +- ti,hwmods: Name of the hwmod associated to the timer, "timer<X>",
> + where <X> is the instance number of the timer from the
> + HW spec.
> +
> +Optional properties:
> +- ti,timer-alwon: Indicates the timer is in an alway-on power domain.
> +- ti,timer-dsp: Indicates the timer can interrupt the on-chip DSP in
> + addition to the ARM CPU.
> +- ti,timer-pwm: Indicates the timer can generate a PWM output.
> +- ti,timer-secure: Indicates the timer is reserved on a secure OMAP device
> + and therefore cannot be used by the kernel.
> +
> +Example:
> +
> +timer12: timer at 48304000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48304000 0xfff>;
> + interrupts = <95>;
> + ti,hwmods = "timer12"
> + ti,timer-alwon;
> + ti,timer-secure;
> +};
> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> index 4709269..7522e16 100644
> --- a/arch/arm/boot/dts/am33xx.dtsi
> +++ b/arch/arm/boot/dts/am33xx.dtsi
> @@ -237,5 +237,59 @@
> interrupts = <55>;
> status = "disabled";
> };
> +
> + timer1: timer at 44e31000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x44e31000 0x1000>;
> + interrupts = <67>;
> + ti,hwmods = "timer1";
> + ti,timer-alwon;
> + };
> +
> + timer2: timer at 48040000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48040000 0x1000>;
> + interrupts = <68>;
> + ti,hwmods = "timer2";
> + };
> +
> + timer3: timer at 48042000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48042000 0x1000>;
> + interrupts = <69>;
> + ti,hwmods = "timer3";
> + };
> +
> + timer4: timer at 48044000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48044000 0x1000>;
> + interrupts = <92>;
> + ti,hwmods = "timer4";
> + ti,timer-pwm;
> + };
> +
> + timer5: timer at 48046000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48046000 0x1000>;
> + interrupts = <93>;
> + ti,hwmods = "timer5";
> + ti,timer-pwm;
> + };
> +
> + timer6: timer at 48048000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48048000 0x1000>;
> + interrupts = <94>;
> + ti,hwmods = "timer6";
> + ti,timer-pwm;
> + };
> +
> + timer7: timer at 4804a000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4804a000 0x1000>;
> + interrupts = <95>;
> + ti,hwmods = "timer7";
> + ti,timer-pwm;
> + };
> };
> };
> diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
> index f366482..731de55 100644
> --- a/arch/arm/boot/dts/omap2.dtsi
> +++ b/arch/arm/boot/dts/omap2.dtsi
> @@ -66,5 +66,90 @@
> ti,hwmods = "uart3";
> clock-frequency = <48000000>;
> };
> +
> + timer2: timer at 4802a000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4802a000 0xfff>;
> + interrupts = <38>;
> + ti,hwmods = "timer2";
> + };
> +
> + timer3: timer at 48078000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48078000 0xfff>;
> + interrupts = <39>;
> + ti,hwmods = "timer3";
> + };
> +
> + timer4: timer at 4807a000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4807a000 0xfff>;
> + interrupts = <40>;
> + ti,hwmods = "timer4";
> + };
> +
> + timer5: timer at 4807c000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4807c000 0xfff>;
> + interrupts = <41>;
> + ti,hwmods = "timer5";
> + ti,timer-dsp;
> + };
> +
> + timer6: timer at 4807e000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4807e000 0xfff>;
> + interrupts = <42>;
> + ti,hwmods = "timer6";
> + ti,timer-dsp;
> + };
> +
> + timer7: timer at 48080000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48080000 0xfff>;
> + interrupts = <43>;
> + ti,hwmods = "timer7";
> + ti,timer-dsp;
> + };
> +
> + timer8: timer at 48082000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48082000 0xfff>;
> + interrupts = <44>;
> + ti,hwmods = "timer8";
> + ti,timer-dsp;
> + };
> +
> + timer9: timer at 48084000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48084000 0xfff>;
> + interrupts = <45>;
> + ti,hwmods = "timer9";
> + ti,timer-pwm;
> + };
> +
> + timer10: timer at 48086000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48086000 0xfff>;
> + interrupts = <46>;
> + ti,hwmods = "timer10";
> + ti,timer-pwm;
> + };
> +
> + timer11: timer at 48088000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48088000 0xfff>;
> + interrupts = <47>;
> + ti,hwmods = "timer11";
> + ti,timer-pwm;
> + };
> +
> + timer12: timer at 4808a000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4808a000 0xfff>;
> + interrupts = <48>;
> + ti,hwmods = "timer12";
> + ti,timer-pwm;
> + };
> };
> };
> diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
> index 4d5ce91..eee3778 100644
> --- a/arch/arm/boot/dts/omap2420.dtsi
> +++ b/arch/arm/boot/dts/omap2420.dtsi
> @@ -42,5 +42,13 @@
> interrupt-names = "tx", "rx";
> ti,hwmods = "mcbsp2";
> };
> +
> + timer1: timer at 48028000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48028000 0xfff>;
> + interrupts = <37>;
> + ti,hwmods = "timer1";
> + ti,timer-alwon;
> + };
> };
> };
> diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
> index fa84532..eea5b8e 100644
> --- a/arch/arm/boot/dts/omap2430.dtsi
> +++ b/arch/arm/boot/dts/omap2430.dtsi
> @@ -83,5 +83,13 @@
> ti,buffer-size = <128>;
> ti,hwmods = "mcbsp5";
> };
> +
> + timer1: timer at 49018000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x49018000 0xfff>;
> + interrupts = <37>;
> + ti,hwmods = "timer1";
> + ti,timer-alwon;
> + };
> };
> };
> diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
> index 955cbdc..904c07e 100644
> --- a/arch/arm/boot/dts/omap3.dtsi
> +++ b/arch/arm/boot/dts/omap3.dtsi
> @@ -296,5 +296,100 @@
> ti,buffer-size = <128>;
> ti,hwmods = "mcbsp5";
> };
> +
> + timer1: timer at 48318000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48318000 0xfff>;
> + interrupts = <37>;
> + ti,hwmods = "timer1";
> + ti,timer-alwon;
> + };
> +
> + timer2: timer at 49032000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x49032000 0xfff>;
> + interrupts = <38>;
> + ti,hwmods = "timer2";
> + };
> +
> + timer3: timer at 49034000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x49034000 0xfff>;
> + interrupts = <39>;
> + ti,hwmods = "timer3";
> + };
> +
> + timer4: timer at 49036000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x49036000 0xfff>;
> + interrupts = <40>;
> + ti,hwmods = "timer4";
> + };
> +
> + timer5: timer at 49038000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x49038000 0xfff>;
> + interrupts = <41>;
> + ti,hwmods = "timer5";
> + ti,timer-dsp;
> + };
> +
> + timer6: timer at 4903a000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4903a000 0xfff>;
> + interrupts = <42>;
> + ti,hwmods = "timer6";
> + ti,timer-dsp;
> + };
> +
> + timer7: timer at 4903c000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4903c000 0xfff>;
> + interrupts = <43>;
> + ti,hwmods = "timer7";
> + ti,timer-dsp;
> + };
> +
> + timer8: timer at 4903e000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4903e000 0xfff>;
> + interrupts = <44>;
> + ti,hwmods = "timer8";
> + ti,timer-pwm;
> + ti,timer-dsp;
> + };
> +
> + timer9: timer at 49040000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x49040000 0xfff>;
> + interrupts = <45>;
> + ti,hwmods = "timer9";
> + ti,timer-pwm;
> + };
> +
> + timer10: timer at 48086000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48086000 0xfff>;
> + interrupts = <46>;
> + ti,hwmods = "timer10";
> + ti,timer-pwm;
> + };
> +
> + timer11: timer at 48088000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48088000 0xfff>;
> + interrupts = <47>;
> + ti,hwmods = "timer11";
> + ti,timer-pwm;
> + };
> +
> + timer12: timer at 48304000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48304000 0xfff>;
> + interrupts = <95>;
> + ti,hwmods = "timer12";
> + ti,timer-alwon;
> + ti,timer-secure;
> + };
> };
> };
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 2ab6e68..77f9cc9 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -433,5 +433,91 @@
> ranges;
> ti,hwmods = "ocp2scp_usb_phy";
> };
> +
> + timer1: timer at 4a318000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4a318000 0x7f>;
> + interrupts = <0 37 0x4>;
> + ti,hwmods = "timer1";
> + ti,timer-alwon;
> + };
> +
> + timer2: timer at 48032000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48032000 0x7f>;
> + interrupts = <0 38 0x4>;
> + ti,hwmods = "timer2";
> + };
> +
> + timer3: timer at 48034000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48034000 0x7f>;
> + interrupts = <0 39 0x4>;
> + ti,hwmods = "timer3";
> + };
> +
> + timer4: timer at 48036000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48036000 0x7f>;
> + interrupts = <0 40 0x4>;
> + ti,hwmods = "timer4";
> + };
> +
> + timer5: timer at 49038000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x49038000 0x7f>;
> + interrupts = <0 41 0x4>;
> + ti,hwmods = "timer5";
> + ti,timer-dsp;
> + };
> +
> + timer6: timer at 4903a000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4903a000 0x7f>;
> + interrupts = <0 42 0x4>;
> + ti,hwmods = "timer6";
> + ti,timer-dsp;
> + };
> +
> + timer7: timer at 4903c000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4903c000 0x7f>;
> + interrupts = <0 43 0x4>;
> + ti,hwmods = "timer7";
> + ti,timer-dsp;
> + };
> +
> + timer8: timer at 4903e000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4903e000 0x7f>;
> + interrupts = <0 44 0x4>;
> + ti,hwmods = "timer8";
> + ti,timer-pwm;
> + ti,timer-dsp;
> + };
> +
> + timer9: timer at 4803e000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x4803e000 0x7f>;
> + interrupts = <0 45 0x4>;
> + ti,hwmods = "timer9";
> + ti,timer-pwm;
> + };
> +
> + timer10: timer at 48086000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48086000 0x7f>;
> + interrupts = <0 46 0x4>;
> + ti,hwmods = "timer10";
> + ti,timer-pwm;
> + };
> +
> + timer11: timer at 48088000 {
> + compatible = "ti,omap2-timer";
> + reg = <0x48088000 0x7f>;
> + interrupts = <0 47 0x4>;
> + ti,hwmods = "timer11";
> + ti,timer-pwm;
> + };
> };
> };
> --
> 1.7.0.4
>
>
>
>
^ permalink raw reply
* [PATCH] ARM: decompressor: clear SCTLR.A bit for v7 cores
From: Russell King - ARM Linux @ 2012-10-25 12:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5086FEEC.5090203@free-electrons.com>
On Tue, Oct 23, 2012 at 10:32:44PM +0200, Gregory CLEMENT wrote:
> So is there a chance that this patch will be applied for 3.7?
>
> Currently I can't boot anymore Armada XP or Armada 370, if kernel is
> compressed in LZO. It's annoying.
>
> Russell, did Nicolas manage to convince you?
Frankly, no - less so now that we have a question mark over ARMv6 which
seems to conflict with Nicolas' justification. This issue is larger than
just ARMv7...
^ permalink raw reply
* [PATCH 2/6] pinctrl: Update clock handling for the pinctrl-nomadik GPIO driver
From: Linus Walleij @ 2012-10-25 12:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121025082341.GC3348@gmail.com>
On Thu, Oct 25, 2012 at 10:23 AM, Lee Jones <lee.jones@linaro.org> wrote:
> On Thu, 25 Oct 2012, Linus Walleij wrote:
>>
>> Yeah drop it for now.
>
> Actually, a quick question before I do:
>
> If it's better/faster to prepare the clock and keep it prepared
> while you do clk_enable/clk_disable,
It is generally faster that is why we call it fastpath.
E.g. if the clock hardware can do this in IRQ context by just
chaninging one bit in a quickly written register from 1->0 and
then the clock goes off from some silicon.
Whether it's "better" or not is a transcendental question,
as it requires a ruler to measure betterness.
> why don't we do that in all
> drivers? Why do we bother to prepare/unprepare each time if all
> it does is take up cycles?
Usually to save power.
Albeit saving power may be at odds with gaining the maximum
performance and/or latency.
So depending on the demands and use case the answer to
whether or not you want to do this will be different.
That's for the clock API.
In the ux500 case specifically, you can drill down to the
clock implementation and ask the question whether or not
we want to do this for this instance of the pin controller
in this case, I'll leave that for Ulf to answer... but remember
that this driver is also used for the Nomadik NHK8815.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH V4 1/5] ARM: dts: OMAP: Add timer nodes
From: Benoit Cousson @ 2012-10-25 12:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EB4A738@DBDE01.ent.ti.com>
Hi Vaibhav,
On 10/25/2012 02:05 PM, Hiremath, Vaibhav wrote:
> On Wed, Oct 24, 2012 at 21:11:13, Cousson, Benoit wrote:
>> Hi Jon,
>>
>> On 10/19/2012 04:59 PM, Jon Hunter wrote:
>>> Add the 12 GP timers nodes present in OMAP2.
>>> Add the 12 GP timers nodes present in OMAP3.
>>> Add the 11 GP timers nodes present in OMAP4.
>>> Add the 7 GP timers nodes present in AM33xx.
>>>
>>> Add documentation for timer properties specific to OMAP.
>>>
>>> Thanks to Vaibhav Hiremath for creating the AM33xx timer nodes. I have modified
>>> Vaibhav's original nodes adding information on which timers support a PWM
>>> output.
>>>
>>> Cc: Benoit Cousson <b-cousson@ti.com>
>>> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
>>
>> I updated the patch to remove the interrupt-parent from the DTS nodes and the documentation, as discussed on the list in the context of OMAP5 DTS for GPIO.
>>
>> If you are OK with that version, I'll push it to Tony along with the others DTS patches.
>>
>> Regards,
>> Benoit
>>
>> ---
>> From 531cc8142ecd6da7929628772c4035dcf7996fef Mon Sep 17 00:00:00 2001
>> From: Jon Hunter <jon-hunter@ti.com>
>> Date: Fri, 19 Oct 2012 09:59:00 -0500
>> Subject: [PATCH] ARM: dts: OMAP: Add timer nodes
>>
>> Add the 12 GP timers nodes present in OMAP2.
>> Add the 12 GP timers nodes present in OMAP3.
>> Add the 11 GP timers nodes present in OMAP4.
>> Add the 7 GP timers nodes present in AM33xx.
>>
>> Add documentation for timer properties specific to OMAP.
>>
>> Thanks to Vaibhav Hiremath for creating the AM33xx timer nodes. I have modified
>> Vaibhav's original nodes adding information on which timers support a PWM
>> output.
>>
>> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
>> [b-cousson at ti.com: Remove the interrupt-parent from nodes]
>> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
>> ---
>> .../devicetree/bindings/arm/omap/timer.txt | 31 +++++++
>> arch/arm/boot/dts/am33xx.dtsi | 54 +++++++++++
>> arch/arm/boot/dts/omap2.dtsi | 85 +++++++++++++++++
>> arch/arm/boot/dts/omap2420.dtsi | 8 ++
>> arch/arm/boot/dts/omap2430.dtsi | 8 ++
>> arch/arm/boot/dts/omap3.dtsi | 95 ++++++++++++++++++++
>> arch/arm/boot/dts/omap4.dtsi | 86 ++++++++++++++++++
>> 7 files changed, 367 insertions(+), 0 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/arm/omap/timer.txt
>>
>
> Benoit,
>
> I have boot tested this on BeagleBone, so,
>
> Tested-By: Vaibhav Hiremath <hvaibhav@ti.com>
Excellent, thanks.
Regards,
Benoit
^ permalink raw reply
* [PATCH V3 1/5] ARM: dts: OMAP: Add timer nodes
From: Hiremath, Vaibhav @ 2012-10-25 12:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50887315.2000509@ti.com>
On Thu, Oct 25, 2012 at 04:30:37, Hunter, Jon wrote:
>
> On 10/24/2012 01:17 PM, Hiremath, Vaibhav wrote:
> > On Wed, Oct 17, 2012 at 23:31:09, Hunter, Jon wrote:
> >> Add the 12 GP timers nodes present in OMAP2.
> >> Add the 12 GP timers nodes present in OMAP3.
> >> Add the 11 GP timers nodes present in OMAP4.
> >> Add the 7 GP timers nodes present in AM33xx.
> >>
> >> Add documentation for timer properties specific to OMAP.
> >>
> >> Please note that for OMAP2/3 devices, there is only one interrupt controller
> >> for the ARM CPU (which has the label "intc") and so globally define this as the
> >> interrupt parent to save duplicating the interrupt parent for all device nodes.
> >>
> >> Thanks to Vaibhav Hiremath for creating the AM33xx timer nodes. I have modified
> >> Vaibhav's original nodes adding information on which timers support a PWM
> >> output.
> >>
> >> Cc: Benoit Cousson <b-cousson@ti.com>
> >> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
> >> ---
> >> .../devicetree/bindings/arm/omap/timer.txt | 29 ++++++
> >> arch/arm/boot/dts/am33xx.dtsi | 61 +++++++++++++
> >> arch/arm/boot/dts/omap2.dtsi | 86 ++++++++++++++++++
> >> arch/arm/boot/dts/omap2420.dtsi | 8 ++
> >> arch/arm/boot/dts/omap2430.dtsi | 8 ++
> >> arch/arm/boot/dts/omap3.dtsi | 96 ++++++++++++++++++++
> >> arch/arm/boot/dts/omap4.dtsi | 86 ++++++++++++++++++
> >> 7 files changed, 374 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/arm/omap/timer.txt
> >>
> >
> > Although I have not tested this version of patch series at my end, but
> > whole patch-series Looks ok to me.
> >
> > Acked-By: Vaibhav Hiremath <hvaibhav@ti.com>
>
> Thanks. I made a couple cosmetic changes in V4 apart from the
> "interrupt-parent" addition which we are now dropping. Care to ACK
> patches 2-5 of V4?
>
Jon,
Good news, I could able to spend some time today on Timer issue on Am33xx
and figure out what is going wrong there. The register context is loosing,
which leads to failure of interrupt test cases.
Below log describes more on this,
[root at arago /]# echo 1 > /tmp/omap-test/timer/all
[ 9.156122] Testing 48042000.timer with 24000000 Hz clock ...
[root at arago /]#
[root at arago /]#
[root at arago /]#
[root at arago /]# [ 11.505497] Timer read test PASSED! No errors, 100 loops
[ 11.511493] omap_dm_timer_set_int_enable:664: irq_ena - 0
[ 11.517277] omap_dm_timer_set_int_enable:670: irq_ena - 2
[ 11.523095] omap_timer_interrupt_test:120: irq_ena - 0 [BOOOOOOOOM]
[ 12.521111] Timer interrupt test FAILED! No interrupt occurred in 1 sec
I changed the Test code as below, and not with your Timer patches, I have
tested all the timers without any issues.
So for all patch series,
Acked-Reviewed-&-Tested-By: Vaibhav Hiremath <hvaibhav@ti.com>
Test code diff:
===============
diff --git a/timer_test.c b/timer_test.c
index e502881..c87a830 100644
--- a/timer_test.c
+++ b/timer_test.c
@@ -13,6 +13,7 @@
#define OMAP1_NUM_TIMERS 8
#define OMAP2_NUM_TIMERS 11
+#define AM33XX_NUM_TIMERS 7
#define OMAP_MAX_NUM_TIMERS 12
#define OMAP_TIMER_SRC_CLKS 2
#define TIMER_TIMEOUT (msecs_to_jiffies(1000))
@@ -113,6 +114,9 @@ static int omap_timer_interrupt_test(struct omap_dm_timer *gptimer)
irq_data.gptimer = gptimer;
init_completion(&irq_data.complete);
+
+ omap_dm_timer_enable(gptimer);
+
omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
omap_dm_timer_set_load_start(gptimer, 0, 0xffffff00);
@@ -128,6 +132,8 @@ static int omap_timer_interrupt_test(struct omap_dm_timer *gptimer)
omap_dm_timer_stop(gptimer);
omap_dm_timer_set_int_enable(gptimer, 0);
+ omap_dm_timer_disable(gptimer);
+
free_irq(timer_irq, &irq_data);
return r;
@@ -141,6 +147,8 @@ static u32 omap_timer_num_timers(void)
max_num_timers = OMAP1_NUM_TIMERS;
else if (cpu_is_omap34xx() && (omap_type() == OMAP2_DEVICE_TYPE_GP))
max_num_timers = OMAP2_NUM_TIMERS + 1;
+ else if (soc_is_am33xx())
+ max_num_timers = AM33XX_NUM_TIMERS;
else
max_num_timers = OMAP2_NUM_TIMERS;
@@ -222,6 +230,7 @@ static int omap_timer_test_all(void)
}
for (i = 0; i < count; i++) {
+ pr_info("\n\n");
r = omap_timer_run_tests(gptimers[i]);
if (r)
errors += r;
Thanks,
Vaibhav
^ permalink raw reply related
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