* [GIT PULL] omap plat header removal for v3.8 merge window, part1
From: Tony Lindgren @ 2012-10-26 17:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201210261402.19759.arnd@arndb.de>
* Arnd Bergmann <arnd@arndb.de> [121026 07:04]:
> On Friday 19 October 2012, Tony Lindgren wrote:
> > Hi Arnd & Olof,
> >
> > Here's the first set of omap plat header removal for v3.8 merge
> > window. I have at least one more related set coming, but I wanted
> > to get these into linux next before driver patches add more
> > things for me to chase down and fix.
> >
> > Oh, forgot to mention in the tag that the increase in diffstat
> > is mostly because plat-omap/clock shared clock code is duplicated
> > as that's also needed for the common clock framework patches
> > coming up.
>
> Hi Tony,
>
> This is very cool, great work! I'm sorry for taking so long before
> we processed them, I wasn't coordinating well with Olof for the last
> week.
>
> I've applied all of it to a new next/headers branch. I thought about
> using the next/cleanup branch, but since it touches a lot of files
> outside of arch/arm, I decided to keep it separate. We might decide
> to merge it later after all.
OK thanks, yes it's OK to keep it separate as I have few more pull
requests coming to this as I get acks. It should all merge fine with
other branches, let me know if that's not the case.
> I tried running my old multiplatform scripts again and have a few
> comments, but none of them serious:
>
> $ git grep include.*mach-omap2
> arch/arm/plat-omap/debug-devices.c:#include "../mach-omap2/debug-devices.h"
> arch/arm/plat-omap/dma.c:#include "../mach-omap2/soc.h"
> arch/arm/plat-omap/dmtimer.c:#include "../mach-omap2/omap-pm.h"
> arch/arm/plat-omap/i2c.c:#include "../mach-omap2/soc.h"
> arch/arm/plat-omap/include/plat/cpu.h:#include "../../mach-omap2/soc.h"
> arch/arm/plat-omap/omap-pm-noop.c:#include "../mach-omap2/omap_device.h"
> arch/arm/plat-omap/omap-pm-noop.c:#include "../mach-omap2/omap-pm.h"
> arch/arm/plat-omap/sram.c:#include "../mach-omap2/soc.h"
> arch/arm/plat-omap/sram.c:#include "../mach-omap2/iomap.h"
> arch/arm/plat-omap/sram.c:#include "../mach-omap2/prm2xxx_3xxx.h"
> arch/arm/plat-omap/sram.c:#include "../mach-omap2/sdrc.h"
>
> I don't like the relative include paths too much. I would have preferred
> adding the mach-omap2/include/mach path in the plat-omap Makefile, but
> I suppose you want to leave it like it is now since you mention you
> have already built on top of it.
Well I wanted to keep them local to arch/arm/*omap*/ directories,
and not have them exposed at all for drivers.
Other than that I don't have an issue using non-relative paths, except
mach-omap2/include/mach traditionally has been exposed to drivers
as the legacy #include <mach/*.h>, so IMHO local headers in the
arch/arm/*omap*/ directories are better.
But now I wonder if we can somehow have drivers not be able to
include these local headers?
> drivers/staging/tidspbridge/core/_tiomap.h:#include <mach-omap2/powerdomain.h>
> drivers/staging/tidspbridge/core/_tiomap.h:#include <mach-omap2/clockdomain.h>
> drivers/staging/tidspbridge/core/_tiomap.h:#include <mach-omap2/cm2xxx_3xxx.h>
> drivers/staging/tidspbridge/core/_tiomap.h:#include <mach-omap2/prm-regbits-34xx.h>
> drivers/staging/tidspbridge/core/_tiomap.h:#include <mach-omap2/cm-regbits-34xx.h>
> drivers/staging/tidspbridge/core/tiomap3430_pwr.c:#include <mach-omap2/prm-regbits-34xx.h>
> drivers/staging/tidspbridge/core/tiomap3430_pwr.c:#include <mach-omap2/cm-regbits-34xx.h>
> drivers/staging/tidspbridge/rmgr/drv_interface.c:#include <mach-omap2/omap3-opp.h>
>
> This code is broken now. I wonder whether it's time to remove it from
> staging since we now have rpmsg/remoteproc, rather than getting it to
> compile again.
Oh crap, I totally missed these :( The drivers _should_not_ include
these files at all. Whatever they are doing with those includes is
totally wrong and a bad layering violation.
If it's not fixed, then yeah, I'd say let's just remove the breaking
pieces. Let's give Omar and Laurent a quick chance to fix it up before
dropping it though, I've added them to cc.
> sound/soc/omap/am3517evm.c:#include <mach-omap2/hardware.h>
> sound/soc/omap/am3517evm.c:#include <mach-omap2/gpio.h>
> sound/soc/omap/ams-delta.c:#include <mach-omap2/board-ams-delta.h>
> sound/soc/omap/n810.c:#include <mach-omap2/hardware.h>
> sound/soc/omap/sdp3430.c:#include <mach-omap2/hardware.h>
> sound/soc/omap/sdp3430.c:#include <mach-omap2/gpio.h>
> sound/soc/omap/zoom2.c:#include <mach-omap2/hardware.h>
> sound/soc/omap/zoom2.c:#include <mach-omap2/gpio.h>
> sound/soc/omap/zoom2.c:#include <mach-omap2/board-zoom.h>
>
> Not sure if you were just missing these or if you already have other
> patch lined up for them.
In which branch do you see the above?
I'm not seeing them in v3.7-rc2, looks like all sound/soc/omap/*.c
files have already been fixed up.
> $ git grep include.*mach-omap1
> drivers/video/omap/lcd_ams_delta.c:#include <mach-omap1/board-ams-delta.h>
> drivers/video/omap/lcd_inn1510.c:#include <mach-omap1/hardware.h>
> drivers/video/omap/lcd_osk.c:#include <mach-omap1/mux.h>
> drivers/video/omap/lcdc.c:#include <mach-omap1/lcdc.h>
> sound/soc/omap/osk5912.c:#include <mach-omap1/hardware.h>
>
> Same thing here.
I'm not seeing these either, you're probably looking at some
experimental branch modified with your automated scripts?
In any case, let's not have #include <mach-omap1/*.h> or
#include <mach-omap2/*.h> includes in the drivers, they are
wrong. Those headers are meant to be local, the legacy shared
headers should be in #include <mach/*.h>. Whatever needs to
be passed from arch/arm/*omap*/ to drivers, should be done
using include/linux/platform_data/*.h files.
For omap1, we might as well keep the existing ones from
#include <mach/*.h> as they are until somebody wants to fix
up things properly for omap1 for CONFIG_MULTIPLATFORM.
Regards,
Tony
^ permalink raw reply
* [PATCH v2 5/7] crypto: omap-sham: Convert to use pm_runtime API
From: Mark A. Greer @ 2012-10-26 17:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87lieunkat.fsf@deeprootsystems.com>
On Thu, Oct 25, 2012 at 05:34:02PM -0700, Kevin Hilman wrote:
> Hi Mark,
Hi Kevin.
> "Mark A. Greer" <mgreer@animalcreek.com> writes:
>
> > From: "Mark A. Greer" <mgreer@animalcreek.com>
> >
> > Convert the omap-sham crypto driver to use the
> > pm_runtime API instead of the clk API.
> >
> > CC: Kevin Hilman <khilman@deeprootsystems.com>
> > CC: Paul Walmsley <paul@pwsan.com>
> > CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
> > Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
>
> I can't pretend to fully understand this driver, It looks like the
> current code is doing a bit more fine-grained clock gating, and leaving
> the IP clocked only when needed.
>
> The proposed version does a 'get' in probe and a 'put' in remove, which
> means the IP will always be enabled (and thus preventing low-power
> states), even when it's not in use.
You're right, and what I did is wrong. I'll fix this in the next revision.
Thanks,
Mark
--
^ permalink raw reply
* [GIT PULL] vexpress: soc changes for v3.8
From: Pawel Moll @ 2012-10-26 17:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201210261700.52195.arnd@arndb.de>
On Fri, 2012-10-26 at 18:00 +0100, Arnd Bergmann wrote:
> Right, it works in -next. Can you rebase the soc changes on top of the
> stuff that went into Mike's tree and resubmit so it also builds in
> arm-soc?
Sure (if I understood you correctly ;-)
The following changes since commit ddffeb8c4d0331609ef2581d84de4d763607bd37:
Linux 3.7-rc1 (2012-10-14 14:41:04 -0700)
are available in the git repository at:
git://git.linaro.org/people/pawelmoll/linux.git vexpress-clk-soc
for you to fetch changes up to 60b3bee64022489ef66a4f56284ccf68b29bd7a9:
ARM: vexpress: Remove motherboard dependencies in the DTS files (2012-10-26 18:06:11 +0100)
----------------------------------------------------------------
Pawel Moll (7):
clk: Versatile Express clock generators ("osc") driver
clk: Common clocks implementation for Versatile Express
mfd: Versatile Express config infrastructure
mfd: Versatile Express system registers driver
ARM: vexpress: Add config bus components and clocks to DTs
ARM: vexpress: Start using new Versatile Express infrastructure
ARM: vexpress: Remove motherboard dependencies in the DTS files
.../devicetree/bindings/arm/vexpress-sysreg.txt | 50 ++
Documentation/devicetree/bindings/arm/vexpress.txt | 98 +++-
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 146 +++++-
arch/arm/boot/dts/vexpress-v2m.dtsi | 146 +++++-
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 121 ++++-
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 186 ++++++-
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 84 ++-
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 136 ++++-
arch/arm/include/asm/hardware/sp810.h | 6 +-
arch/arm/mach-vexpress/Kconfig | 4 +-
arch/arm/mach-vexpress/Makefile | 2 +-
arch/arm/mach-vexpress/ct-ca9x4.c | 41 +-
arch/arm/mach-vexpress/include/mach/motherboard.h | 81 ---
arch/arm/mach-vexpress/platsmp.c | 3 +-
arch/arm/mach-vexpress/v2m.c | 349 ++++---------
drivers/clk/Kconfig | 8 +-
drivers/clk/versatile/Makefile | 2 +
drivers/clk/versatile/clk-vexpress-osc.c | 150 ++++++
drivers/clk/versatile/clk-vexpress.c | 142 +++++
drivers/mfd/Kconfig | 6 +
drivers/mfd/Makefile | 1 +
drivers/mfd/vexpress-config.c | 277 ++++++++++
drivers/mfd/vexpress-sysreg.c | 552 ++++++++++++++++++++
include/linux/vexpress.h | 121 +++++
24 files changed, 2293 insertions(+), 419 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
create mode 100644 drivers/clk/versatile/clk-vexpress-osc.c
create mode 100644 drivers/clk/versatile/clk-vexpress.c
create mode 100644 drivers/mfd/vexpress-config.c
create mode 100644 drivers/mfd/vexpress-sysreg.c
create mode 100644 include/linux/vexpress.h
^ permalink raw reply
* [PATCH 10/16] ARM: OMAP: Make omap_device local to mach-omap2
From: Tony Lindgren @ 2012-10-26 17:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1210261701060.3301@utopia.booyaka.com>
* Paul Walmsley <paul@pwsan.com> [121026 10:03]:
> On Fri, 26 Oct 2012, Tony Lindgren wrote:
>
> > Can you do a branch on top of omap-for-v3.8/cleanup-headers
> > with all these fixes that I can pull in?
>
> Yes, will do that today.
OK thanks!
Tony
^ permalink raw reply
* [PATCH v2 1/3] drivers: bus: ocp2scp: add pdata support
From: Tony Lindgren @ 2012-10-26 17:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121026064736.GA22206@arwen.pp.htv.fi>
* Felipe Balbi <balbi@ti.com> [121025 23:55]:
> On Thu, Oct 25, 2012 at 10:44:47AM -0700, Tony Lindgren wrote:
> > * Felipe Balbi <balbi@ti.com> [121024 23:24]:
> > > Hi,
> > >
> > > On Wed, Oct 24, 2012 at 05:48:07PM -0700, Tony Lindgren wrote:
> > > > * Tony Lindgren <tony@atomide.com> [121016 09:53]:
> > > > > * Kishon Vijay Abraham I <kishon@ti.com> [121007 23:01]:
> > > > > > ocp2scp was not having pdata support which makes *musb* fail for non-dt
> > > > > > boot in OMAP platform. The pdata will have information about the devices
> > > > > > that is connected to ocp2scp. ocp2scp driver will now make use of this
> > > > > > information to create the devices that is attached to ocp2scp.
> > > > > >
> > > > > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> > > > >
> > > > > This fixes the regression on my panda es for musb port:
> > > > >
> > > > > Acked-by: Tony Lindgren <tony@atomide.com>
> > > >
> > > > Looks like nobody has picked this one up and we need it to
> > > > fix the musb regression on omap, so I'll queue these up.
> > >
> > > I don't seem to have the patches around in any mailbox :-(
> >
> > Bounced them to you. Do you have any better ideas for the
> > -rc cycle to fix the MUSB regression on omap4?
>
> Well, there are two regressions that I know of. One is caused by the
> mode1 DMA changes, which I'll just revert, and the other is the
> missing platform_data support on the new PHY driver which these patches
> are supposed to solve, right ?
Yes that's it AFAIK.
Regards,
Tony
^ permalink raw reply
* [GIT PULL] vexpress: soc changes for v3.8
From: Arnd Bergmann @ 2012-10-26 17:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351271439.9454.36.camel@hornet>
On Friday 26 October 2012, Pawel Moll wrote:
> On Fri, 2012-10-26 at 18:00 +0100, Arnd Bergmann wrote:
> > Right, it works in -next. Can you rebase the soc changes on top of the
> > stuff that went into Mike's tree and resubmit so it also builds in
> > arm-soc?
>
> Sure (if I understood you correctly ;-)
>
> The following changes since commit ddffeb8c4d0331609ef2581d84de4d763607bd37:
>
> Linux 3.7-rc1 (2012-10-14 14:41:04 -0700)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pawelmoll/linux.git vexpress-clk-soc
>
> for you to fetch changes up to 60b3bee64022489ef66a4f56284ccf68b29bd7a9:
>
> ARM: vexpress: Remove motherboard dependencies in the DTS files (2012-10-26 18:06:11 +0100)
This seems to work now, but the commit for the clock driver (46c5737245a2)
does not actually seem to be part of linux-next, unless I'm mistaken.
Are you sure it's the same commit that Mike has in his tree?
Is this not the tree that is part of linux-next?
Arnd
> ----------------------------------------------------------------
> Pawel Moll (7):
> clk: Versatile Express clock generators ("osc") driver
> clk: Common clocks implementation for Versatile Express
> mfd: Versatile Express config infrastructure
> mfd: Versatile Express system registers driver
> ARM: vexpress: Add config bus components and clocks to DTs
> ARM: vexpress: Start using new Versatile Express infrastructure
> ARM: vexpress: Remove motherboard dependencies in the DTS files
>
> .../devicetree/bindings/arm/vexpress-sysreg.txt | 50 ++
> Documentation/devicetree/bindings/arm/vexpress.txt | 98 +++-
> arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 146 +++++-
> arch/arm/boot/dts/vexpress-v2m.dtsi | 146 +++++-
> arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 121 ++++-
> arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 186 ++++++-
> arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 84 ++-
> arch/arm/boot/dts/vexpress-v2p-ca9.dts | 136 ++++-
> arch/arm/include/asm/hardware/sp810.h | 6 +-
> arch/arm/mach-vexpress/Kconfig | 4 +-
> arch/arm/mach-vexpress/Makefile | 2 +-
> arch/arm/mach-vexpress/ct-ca9x4.c | 41 +-
> arch/arm/mach-vexpress/include/mach/motherboard.h | 81 ---
> arch/arm/mach-vexpress/platsmp.c | 3 +-
> arch/arm/mach-vexpress/v2m.c | 349 ++++---------
> drivers/clk/Kconfig | 8 +-
> drivers/clk/versatile/Makefile | 2 +
> drivers/clk/versatile/clk-vexpress-osc.c | 150 ++++++
> drivers/clk/versatile/clk-vexpress.c | 142 +++++
> drivers/mfd/Kconfig | 6 +
> drivers/mfd/Makefile | 1 +
> drivers/mfd/vexpress-config.c | 277 ++++++++++
> drivers/mfd/vexpress-sysreg.c | 552 ++++++++++++++++++++
> include/linux/vexpress.h | 121 +++++
> 24 files changed, 2293 insertions(+), 419 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
> create mode 100644 drivers/clk/versatile/clk-vexpress-osc.c
> create mode 100644 drivers/clk/versatile/clk-vexpress.c
> create mode 100644 drivers/mfd/vexpress-config.c
> create mode 100644 drivers/mfd/vexpress-sysreg.c
> create mode 100644 include/linux/vexpress.h
>
>
>
>
^ permalink raw reply
* [PATCH v2 3/3] ARM: OMAP: ocp2scp: create omap device for ocp2scp
From: Tony Lindgren @ 2012-10-26 17:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201210260747.11848.arnd@arndb.de>
* Arnd Bergmann <arnd@arndb.de> [121026 00:48]:
> On Friday 26 October 2012, Felipe Balbi wrote:
> > > +static void omap_init_ocp2scp(void)
> > > +{
> > > + struct omap_hwmod *oh;
> > > + struct platform_device *pdev;
> > > + int bus_id = -1, dev_cnt = 0, i;
> > > + struct omap_ocp2scp_dev *ocp2scp_dev;
> > > + const char *oh_name, *name;
> > > + struct omap_ocp2scp_platform_data *pdata;
> > > +
> > > + oh_name = "ocp2scp_usb_phy";
> > > + name = "omap-ocp2scp";
> >
> > how about adding checks here to return early case we're not running on
> > OMAP4 or OMAP5 ??
> >
>
> I suppose even OMAP4-only, since OMAP5 always has DT enabled.
Hmm yes, currently omap_hwmod_lookup(oh_name) produces
bogus errors for other omaps as the hwmod data is only
there for omap4.
Regards,
Tony
^ permalink raw reply
* [PATCH] arm: kirkwood: add support for ZyXEL NSA310
From: Tero Jaasko @ 2012-10-26 17:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121025181326.GL18811@titan.lakedaemon.net>
Hello, Jason and thanks for your comments.
> hmmm, there probably won't be any conflicts when I go to apply this, but
> in the future, please base against a tag in Linus' tree. eg v3.6
I see and did that on the new submission attached to Andrew's mail.
> > + model = "ZyXEL NSA310";
> > + compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood";
>
> Is there only one variant of the nsa310? eg did they change flash types
> or ram size during a production run? Whether they did or not, we prefer
> to be as specific as possible here, eg "zyxel,nsa310-PRODNUM" If you can
> locate a PRODNUM that will most likely change if they change the BOM,
> etc. Please add this string in addition to what you currently have.i
I have no idea what product number or other id this device has.
On http://zyxel.nas-central.org/wiki/Category:NSA-310 it is
said that there is at least a sister model under "TDC Homedisk" label.
The TDC variant seems to have different amount of leds and at least
the NAND partition configuration is also different. And also some
variant exists on some sources somewhere which might not have been
sold at all.
The device I have looks like the one described on previous link
as a "genuine". It does not have even the NSA310 printed in it,
just "ZyXEL" and two printed stickers, one with ethernet MAC
address and one with a long number which might be a serial number.
Or not. It is formatted as S111M32xxxxxx, x being a number.
The string itself is unknown to google, hence it might be a unique id.
What should we do? Add better device id if/when somebody from
Denmark comes up with a TDC device that requires different DT?
> > +config MACH_NSA310_DT
> > + bool "ZyXEL NSA-310 (Flattened Device Tree)"
> > + select ARCH_KIRKWOOD_DT
> > + select ARM_APPENDED_DTB
> > + select ARM_ATAG_DTB_COMPAT
>
> I would prefer not to enable APPENDED_DTB by default.
Ok, I removed that. I just believe it is needed to be actually
boot the device with stock uBoot. Or is there other/better way to bundle the
DT blob into uImage?
The uBoot my device is dated as "U-Boot 1.1.4 (Feb 22 2011 - 10:31:35)
Marvell version: 3.4.1", and as far as I know, it does not have the DT
support. I have not tried with a more recent uBoot. After having bricked
one Buffalo Ls-xhl with a failed uBoot update, I will not do another
before populating the JTAG pins on PCB and verifying that the plan
B works;-)
> > diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c
> > new file mode 100644
> > index 0000000..4d20841
> > --- /dev/null
> > +++ b/arch/arm/mach-kirkwood/board-nsa310.c
> > @@ -0,0 +1,166 @@
> > +/*
> > + * arch/arm/mach-kirkwood/board-nsa310.c
> > + *
> > + * ZyXEL NSA-310 Setup
>
> Copyright?
..is not really mine at least. I have just deleted ~60% of
the code taken from openwrt.org's tree (commit at
https://dev.openwrt.org/browser/trunk/target/linux/kirkwood/
patches-3.3/202-zyxel-nsa-310.patch?rev=31673) and replaced
it with the dt definitions.
> > + *
> > + * This file is licensed under the terms of the GNU General Public
> > + * License version 2. This program is licensed "as is" without any
> > + * warranty of any kind, whether express or implied.
> > + */
> > +#define NSA310_GPIO_LED_ESATA_GREEN 12
> Please remove any of the above #define's that aren't used.
Done.
> > +static unsigned int nsa310_mpp_config[] __initdata = {
> > + MPP12_GPIO, /* led esata green */
> > + MPP13_GPIO, /* led esata red */
>
> There is a patch series to convert all kirkwood DT boards over to DT
> init of MPP is under review currently. If things go well, I'd like to
> see this use it as well.
That will be really a good improvement for all the boards and
conversion would be easy too. After this, ehci and pcie conversion,
the board-nsa310.c would be something like 70-80 lines instead of
~270 lines at original nsa-310-setup.c. Sweet.
> > +static struct mtd_partition nsa310_mtd_parts[] = {
> > + {
> > + .name = "uboot",
> Please move the above partition definitions into the dts file, you can
> then remove all of the nand init and relevant includes.
Done.
> > +
> > +static struct i2c_board_info __initdata nsa310_i2c_info[] = {
> > + { I2C_BOARD_INFO("adt7476", 0x2e) },
> > +};
>
> how far off from the adt7461 (lm90) is this? If similar, please
> consider extending lm90's compatibility list and describing this in the
> dts instead.
I did move at least the I2C to DT. Good catch, this is something
worth of a experimentation when a free time slot arrives. The chip seems
to have some sort of compatibility mode with adt7463 so it might just
work somehow with the other driver too.
> > +
> > +static void nsa310_power_off(void)
> > +{
> > + gpio_set_value(NSA310_GPIO_POWER_OFF, 1);
> > +}
> > +
> > +static int __init nsa310_gpio_request(unsigned int gpio, unsigned long flags,
> > + const char *label)
> > +{
> > + int err;
> > +
> > + err = gpio_request_one(gpio, flags, label);
> > + if (err)
> > + pr_err("NSA-310: can't setup GPIO%u (%s), err=%d\n",
> > + gpio, label, err);
> > +
> > + return err;
> > +}
> > +
> > +static void __init nsa310_gpio_init(void)
> > +{
> > + int err;
> > +
> > + err = nsa310_gpio_request(NSA310_GPIO_POWER_OFF, GPIOF_OUT_INIT_LOW,
> > + "Power Off");
> > + if (!err)
> > + pm_power_off = nsa310_power_off;
>
> This doesn't smell right.
What do you mean? The wrapper for gpio_request_one() that merely
serves as a source for debug messages? I can replace it with
a silent version if wanted. Is there a driver for shutting down device
by some gpio pin defined in DT?
> > + kirkwood_pcie_id(&dev, &rev);
>
> Does this board actually use pcie? If so, we've been looking for one to
> test on. Just an fyi, we'll probably be hitting you up later for pcie
> DT binding testing. ;-)
If you point to a tree or patches somewhere, I am willing to test it and/or
modify the nsa310 code to use it.
There is a NIC at end of pcie, or at least this is what the "lspci -vv" prints:
8<----8<------
00:00.0 Memory controller: Marvell Technology Group Ltd. 88F6281 [Kirkwood] ARM SoC (rev 03)
Subsystem: Marvell Technology Group Ltd. Device 11ab
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 9
Region 0: Memory@<ignored> (64-bit, prefetchable)
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [60] Express (v1) Root Port (Slot-), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <256ns, L1 <1us
ExtTag- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 unlimited
ClockPM+ Surprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
Capabilities: [100 v1] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
00:01.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 03)
Subsystem: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 9
Region 0: I/O ports at 1000 [size=256]
Region 2: Memory at e0014000 (64-bit, prefetchable) [size=4K]
Region 4: Memory at e0010000 (64-bit, prefetchable) [size=16K]
[virtual] Expansion ROM@e0000000 [disabled] [size=64K]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [70] Express (v2) Endpoint, MSI 01
DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 4096 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us
ClockPM+ Surprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Not Supported, TimeoutDis+
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -6dB
Capabilities: [ac] MSI-X: Enable- Count=4 Masked-
Vector table: BAR=4 offset=00000000
PBA: BAR=4 offset=00000800
Capabilities: [cc] Vital Product Data
Unknown small resource type 00, will not decode more.
Capabilities: [100 v1] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
Capabilities: [140 v1] Virtual Channel
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
Arb: Fixed- WRR32- WRR64- WRR128-
Ctrl: ArbSelect=Fixed
Status: InProgress-
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
Status: NegoPending- InProgress-
Capabilities: [160 v1] Device Serial Number 00-00-00-00-00-00-00-00
Kernel driver in use: r8169
8<----8<------
Best regards,
Tero
^ permalink raw reply
* [PATCH] ARM: OMAP1: CGRM: fix omap1_get_reset_sources() return type
From: Paul Walmsley @ 2012-10-26 17:27 UTC (permalink / raw)
To: linux-arm-kernel
An older version of the patch "ARM: OMAP1: create read_reset_sources()
function (for initial use by watchdog)" was sent upstream, which used
the wrong return type for the omap1_get_reset_sources() function.
Fix it to return a u32, which is what the WDTIMER platform_data
function pointer read_reset_sources() expects.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap1/common.h | 2 +-
arch/arm/mach-omap1/reset.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index d6ac18d..ecd0bb6 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -94,6 +94,6 @@ extern int ocpi_enable(void);
static inline int ocpi_enable(void) { return 0; }
#endif
-extern int omap1_get_reset_sources(void);
+extern u32 omap1_get_reset_sources(void);
#endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index a0a9f97..0df5536 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -43,7 +43,7 @@ void omap1_restart(char mode, const char *cmd)
* Returns bits that represent the last reset source for the SoC. The
* format is standardized across OMAPs for use by the OMAP watchdog.
*/
-int omap1_get_reset_sources(void)
+u32 omap1_get_reset_sources(void)
{
int ret = 0;
u16 rs;
--
1.7.10.4
^ permalink raw reply related
* [PATCH 1/5] ARM: omap: vc: replace data_shift with data_mask
From: Kevin Hilman @ 2012-10-26 17:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349313365-5262-2-git-send-email-mturquette@ti.com>
Mike Turquette <mturquette@ti.com> writes:
> From: Mike Turquette <mturquette@linaro.org>
>
> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Re: $SUBJECT... ok, I'll bite.... why?
(I'm sure I will find out when I read the rest of the series, but I'm
impatient and picky and would like to know here.) ;)
Kevin
^ permalink raw reply
* [PATCH 6/9] ARM: Kirkwood: Convert GoFlex Net to pinctrl.
From: Josh Coombs @ 2012-10-26 17:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351090434-30499-7-git-send-email-andrew@lunn.ch>
Initial test with my 3.7-rc2 DT kernel config failed when it tried to
build modules:
Building modules, stage 2.
MODPOST 733 modules
ERROR: "read_current_timer" [drivers/video/udlfb.ko] undefined!
ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!
make[1]: *** [__modpost] Error 1
make: *** [modules] Error 2
I didn't realize my play kernel test package still includes the
following patch, I thought it had been dealt with already. Should I
start a new thread on this issue?
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 60d3b73..6a37f8d 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -50,6 +50,7 @@ extern void fpundefinstr(void);
/* platform dependent support */
EXPORT_SYMBOL(arm_delay_ops);
+EXPORT_SYMBOL(read_current_timer);
/* networking */
EXPORT_SYMBOL(csum_partial);
In the mean time, I'll start a build with the default conf as
suggested and post test results once I have them.
Josh Coombs
On Wed, Oct 24, 2012 at 10:53 AM, Andrew Lunn <andrew@lunn.ch> wrote:
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> arch/arm/boot/dts/kirkwood-goflexnet.dts | 57 ++++++++++++++++++++++++++++++
> arch/arm/mach-kirkwood/board-goflexnet.c | 18 ----------
> 2 files changed, 57 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
> index 7c8238f..46d16a2 100644
> --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
> +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
> @@ -16,6 +16,63 @@
> };
>
> ocp at f1000000 {
> + pinctrl: pinctrl at 10000 {
> + compatible = "marvell,88f6281-pinctrl";
> + reg = <0x10000 0x20>;
> +
> + pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
> + &pmx_led_left_cap_0 &pmx_led_left_cap_1
> + &pmx_led_left_cap_2 &pmx_led_left_cap_3
> + &pmx_led_right_cap_0 &pmx_led_right_cap_1
> + &pmx_led_right_cap_2 &pmx_led_right_cap_3
> + >;
> + pinctrl-names = "default";
> +
> + pmx_usb_power_enable: pmx-usb-power-enable {
> + marvell,pins = "mpp29";
> + marvell,function = "gpio";
> + };
> + pmx_led_right_cap_0: pmx-led_right_cap_0 {
> + marvell,pins = "mpp38";
> + marvell,function = "gpio";
> + };
> + pmx_led_right_cap_1: pmx-led_right_cap_1 {
> + marvell,pins = "mpp39";
> + marvell,function = "gpio";
> + };
> + pmx_led_right_cap_2: pmx-led_right_cap_2 {
> + marvell,pins = "mpp40";
> + marvell,function = "gpio";
> + };
> + pmx_led_right_cap_3: pmx-led_right_cap_3 {
> + marvell,pins = "mpp41";
> + marvell,function = "gpio";
> + };
> + pmx_led_left_cap_0: pmx-led_left_cap_0 {
> + marvell,pins = "mpp42";
> + marvell,function = "gpio";
> + };
> + pmx_led_left_cap_1: pmx-led_left_cap_1 {
> + marvell,pins = "mpp43";
> + marvell,function = "gpio";
> + };
> + pmx_led_left_cap_2: pmx-led_left_cap_2 {
> + marvell,pins = "mpp44";
> + marvell,function = "gpio";
> + };
> + pmx_led_left_cap_3: pmx-led_left_cap_3 {
> + marvell,pins = "mpp45";
> + marvell,function = "gpio";
> + };
> + pmx_led_green: pmx-led_green {
> + marvell,pins = "mpp46";
> + marvell,function = "gpio";
> + };
> + pmx_led_orange: pmx-led_orange {
> + marvell,pins = "mpp47";
> + marvell,function = "gpio";
> + };
> + };
> serial at 12000 {
> clock-frequency = <200000000>;
> status = "ok";
> diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
> index 001ca8c..9643f4b 100644
> --- a/arch/arm/mach-kirkwood/board-goflexnet.c
> +++ b/arch/arm/mach-kirkwood/board-goflexnet.c
> @@ -34,34 +34,16 @@
> #include <mach/bridge-regs.h>
> #include <linux/platform_data/mmc-mvsdio.h>
> #include "common.h"
> -#include "mpp.h"
>
> static struct mv643xx_eth_platform_data goflexnet_ge00_data = {
> .phy_addr = MV643XX_ETH_PHY_ADDR(0),
> };
>
> -static unsigned int goflexnet_mpp_config[] __initdata = {
> - MPP29_GPIO, /* USB Power Enable */
> - MPP47_GPIO, /* LED Orange */
> - MPP46_GPIO, /* LED Green */
> - MPP45_GPIO, /* LED Left Capacity 3 */
> - MPP44_GPIO, /* LED Left Capacity 2 */
> - MPP43_GPIO, /* LED Left Capacity 1 */
> - MPP42_GPIO, /* LED Left Capacity 0 */
> - MPP41_GPIO, /* LED Right Capacity 3 */
> - MPP40_GPIO, /* LED Right Capacity 2 */
> - MPP39_GPIO, /* LED Right Capacity 1 */
> - MPP38_GPIO, /* LED Right Capacity 0 */
> - 0
> -};
> -
> void __init goflexnet_init(void)
> {
> /*
> * Basic setup. Needs to be called early.
> */
> - kirkwood_mpp_conf(goflexnet_mpp_config);
> -
> if (gpio_request(29, "USB Power Enable") != 0 ||
> gpio_direction_output(29, 1) != 0)
> pr_err("can't setup GPIO 29 (USB Power Enable)\n");
> --
> 1.7.10.4
>
^ permalink raw reply related
* [GIT PULL] omap plat header removal for v3.8 merge window, part1
From: Arnd Bergmann @ 2012-10-26 17:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121026170949.GF11908@atomide.com>
On Friday 26 October 2012, Tony Lindgren wrote:
> * Arnd Bergmann <arnd@arndb.de> [121026 07:04]:
>
> > I tried running my old multiplatform scripts again and have a few
> > comments, but none of them serious:
> >
> > $ git grep include.*mach-omap2
> > arch/arm/plat-omap/debug-devices.c:#include "../mach-omap2/debug-devices.h"
> > arch/arm/plat-omap/dma.c:#include "../mach-omap2/soc.h"
> > arch/arm/plat-omap/dmtimer.c:#include "../mach-omap2/omap-pm.h"
> > arch/arm/plat-omap/i2c.c:#include "../mach-omap2/soc.h"
> > arch/arm/plat-omap/include/plat/cpu.h:#include "../../mach-omap2/soc.h"
> > arch/arm/plat-omap/omap-pm-noop.c:#include "../mach-omap2/omap_device.h"
> > arch/arm/plat-omap/omap-pm-noop.c:#include "../mach-omap2/omap-pm.h"
> > arch/arm/plat-omap/sram.c:#include "../mach-omap2/soc.h"
> > arch/arm/plat-omap/sram.c:#include "../mach-omap2/iomap.h"
> > arch/arm/plat-omap/sram.c:#include "../mach-omap2/prm2xxx_3xxx.h"
> > arch/arm/plat-omap/sram.c:#include "../mach-omap2/sdrc.h"
> >
> > I don't like the relative include paths too much. I would have preferred
> > adding the mach-omap2/include/mach path in the plat-omap Makefile, but
> > I suppose you want to leave it like it is now since you mention you
> > have already built on top of it.
>
> Well I wanted to keep them local to arch/arm/*omap*/ directories,
> and not have them exposed at all for drivers.
>
> Other than that I don't have an issue using non-relative paths, except
> mach-omap2/include/mach traditionally has been exposed to drivers
> as the legacy #include <mach/*.h>, so IMHO local headers in the
> arch/arm/*omap*/ directories are better.
>
> But now I wonder if we can somehow have drivers not be able to
> include these local headers?
Well, once CONFIG_MULTIPLATFORM gets enabled, the mach/*.h files are
not visible to drivers any more, but they are still visible to files
in plat-omap if you add a line like
ccflags-$(CONFIG_ARCH_OMAP2) := -I$(srctree)/arch/arm/mach-omap2/include
ccflags-$(CONFIG_ARCH_OMAP1) := -I$(srctree)/arch/arm/mach-omap1/include
to arch/arm/plat-omap/Makefile. That is how the other multiplatform
Makefiles do it. If a driver writer really wants to cheat, they can of
course do the same thing in their directory, but they can also do
#include "../../../../arch/arm/mach-omap2/foo.h"
> > sound/soc/omap/am3517evm.c:#include <mach-omap2/hardware.h>
> > sound/soc/omap/am3517evm.c:#include <mach-omap2/gpio.h>
> > sound/soc/omap/ams-delta.c:#include <mach-omap2/board-ams-delta.h>
> > sound/soc/omap/n810.c:#include <mach-omap2/hardware.h>
> > sound/soc/omap/sdp3430.c:#include <mach-omap2/hardware.h>
> > sound/soc/omap/sdp3430.c:#include <mach-omap2/gpio.h>
> > sound/soc/omap/zoom2.c:#include <mach-omap2/hardware.h>
> > sound/soc/omap/zoom2.c:#include <mach-omap2/gpio.h>
> > sound/soc/omap/zoom2.c:#include <mach-omap2/board-zoom.h>
> >
> > Not sure if you were just missing these or if you already have other
> > patch lined up for them.
>
> In which branch do you see the above?
>
> I'm not seeing them in v3.7-rc2, looks like all sound/soc/omap/*.c
> files have already been fixed up.
I am looking at the arm-soc for-next branch, which is based on v3.7-rc2.
Note that before my script, this reads
#include <mach/hardware.h>
not
#include <mach-omap2/hardware.h>
but the effect is the same if the file is not available.
> In any case, let's not have #include <mach-omap1/*.h> or
> #include <mach-omap2/*.h> includes in the drivers, they are
> wrong. Those headers are meant to be local, the legacy shared
> headers should be in #include <mach/*.h>. Whatever needs to
> be passed from arch/arm/*omap*/ to drivers, should be done
> using include/linux/platform_data/*.h files.
I'm not suggesting to use mach-omap2/*.h, it's just what my
old script shows when hunting for platform header files that are
used in device drivers.
> For omap1, we might as well keep the existing ones from
> #include <mach/*.h> as they are until somebody wants to fix
> up things properly for omap1 for CONFIG_MULTIPLATFORM.
Fair enough.
Arnd
^ permalink raw reply
* [PATCH] ARM: OMAP2+: remove duplicated declaration of omap4430_init_late
From: Constantine Shulyupin @ 2012-10-26 17:29 UTC (permalink / raw)
To: linux-arm-kernel
From: Constantine Shulyupin <const@MakeLinux.com>
Problem:
Function omap4430_init_late is declared twice in arch/arm/mach-omap2/common.h.
Fix: remove out of order declaration, assuming all functions ordered accordingly processor number.
Signed-off-by: Constantine Shulyupin <const@MakeLinux.com>
---
arch/arm/mach-omap2/common.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 7045e4d..45478d1 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -152,7 +152,6 @@ void am33xx_init_early(void);
void omap4430_init_early(void);
void omap5_init_early(void);
void omap3_init_late(void); /* Do not use this one */
-void omap4430_init_late(void);
void omap2420_init_late(void);
void omap2430_init_late(void);
void omap3430_init_late(void);
--
1.7.9.5
^ permalink raw reply related
* [PATCH 08/10] pinctrl: single: support pinconf generic
From: Tony Lindgren @ 2012-10-26 17:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAN1soZyosQJYZAT61tUig6PGVrfXzwDeiC1R0hnKWoFLVP4Ayw@mail.gmail.com>
* Haojian Zhuang <haojian.zhuang@gmail.com> [121025 18:49]:
> On Fri, Oct 26, 2012 at 7:43 AM, Tony Lindgren <tony@atomide.com> wrote:
> > * Tony Lindgren <tony@atomide.com> [121022 10:11]:
> >> * Haojian Zhuang <haojian.zhuang@gmail.com> [121022 03:11]:
> >> > On Sat, Oct 20, 2012 at 3:13 AM, Tony Lindgren <tony@atomide.com> wrote:
> >> > > * Haojian Zhuang <haojian.zhuang@gmail.com> [121018 02:08]:
> >> > >> Add pinconf generic support with POWER SOURCE, BIAS PULL.
> >> > > ...
> >> > >
> >> > >> + case PIN_CONFIG_POWER_SOURCE:
> >> > >> + if (pcs->psmask == PCS_OFF_DISABLED
> >> > >> + || pcs->psshift == PCS_OFF_DISABLED)
> >> > >> + return -ENOTSUPP;
> >> > >> + data &= pcs->psmask;
> >> > >> + data = data >> pcs->psshift;
> >> > >> + *config = data;
> >> > >> + return 0;
> >> > >> + break;
> >> > >
> >> > > Hmm, only slightly related to this patch, mostly a generic
> >> > > question to others: Do others have any mux registers with
> >> > > status bits for things like PIN_CONFIG_POWER_SOURCE?
> >> > >
> >> > > I could use PIN_CONFIG_POWER_SOURCE for controlling the PBIAS
> >> > > for omap MMC. But there's also a status bit that needs to be
> >> > > checked for that. I think there was some other similar mux
> >> > > register for USB PHY that has a status register.
> >> > >
> >> > > So I'm wondering should the checking for status bit be handled
> >> > > in the pinctrl consume driver? Or should we have some bindings
> >> > > for that?
> >> > >
> >> >
> >> > Do you mean that the status register only exists in USB PHY controller or
> >> > MMC controller?
> >>
> >> The status register is in the MMC PBIAS register that is mux
> >> related otherwise. From OMAP4470_ES1.0_PUBLIC_TRM_vE.pdf,
> >> Table 19-599. CONTROL_PBIASLITE:
> >>
> >> Bits
> >> 26 MMC1_PWDNZ
> >> 25 MMC1_PBIASLITE_HIZ_MODE
> >> 24 MMC1_PBIASLITE_SUPPLY_HI_OUT
> >> 23 MMC1_PBIASLITE_VMODE_ERROR then this bit needs to clear..
> >> 22 MMC1_PBIASLITE_PWRDNZ
> >> 21 MMC1_PBIASLITE_VMODE ..after VMODE bit is set to 3V
> >>
> >> > If so, could we use regulator framework in USB PHY or MMC driver?
> >>
> >> Yes we could use regulator framework for that that. Or just read the
> >> status in the MMC driver for that bit if nobody else has mixed
> >> mux-regulator needs like this.
> >>
> >> The sequence is MMC specific, so from that point of view it would
> >> make sense to have the logic in the MMC driver.
> >
> > Well it turns out the VMODE_ERROR bit is not just for VMODE, it's a
> > comparator that can also triggers for the other invalid states for
> > CONTROL_PBIASLITE pinconf register. So hiding VMODE_ERROR into a
> > regulator would be wrong. For now, VMODE best handled using
> > PIN_CONFIG_POWER_SOURCE and let the MMC driver do the checking
> > using the pinconf API.
> >
> > Regards,
> >
> > Tony
>
> Could you share the link of downloading the spec?
Yes here's the omap4470 public TRM:
http://www.ti.com/litv/pdf/swpu270n
See CONTROL_PBIASLITE, and also "19.4.9.3 PBIAS Error Generation"
table on page 3520 for the combinations when the comparator can
generate errors.
Regards,
Tony
^ permalink raw reply
* [GIT PULL] vexpress: soc changes for v3.8
From: Pawel Moll @ 2012-10-26 17:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201210261718.08983.arnd@arndb.de>
On Fri, 2012-10-26 at 18:18 +0100, Arnd Bergmann wrote:
> Are you sure it's the same commit that Mike has in his tree?
> Is this not the tree that is part of linux-next?
Damn, I am seriously confused now... I'm looking at next-20121026 in
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git and
I'm _not_ seeing the vexpress clk drivers! Neither I can find the
patches in git://git.linaro.org/people/mturquette/linux.git clk-next.
Am I doing something wrong or just looking not where I should? You seem
to be able to see some -next vexpress clk patches - where about?
Mike, you said:
On Thu, 2012-10-11 at 23:40 +0100, Mike Turquette wrote:
> I've taken these into my new clk-next towards 3.8. That branch is not
> yet pushed out publicly but will be after -rc1 is released.
Has this happened yet?
Pawe?
^ permalink raw reply
* [PATCH 2/5] drivers: usb: otg: make twl6030_usb as a comparator driver to omap_usb2
From: Paul Walmsley @ 2012-10-26 17:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <508AAA85.6070905@ti.com>
On Fri, 26 Oct 2012, Benoit Cousson wrote:
> On 10/26/2012 05:16 PM, Roger Quadros wrote:
>
> > I still can't get musb to work on 3.7-rc2. Apparently it is still
> > missing the patches from Benoit's for_3.7/dts_part2.
> >
> > Maybe I just need to wait for it to be merged?
>
> They are now in a for_3.8/dts. Unfortunately, one patch that was adding
> ctrl_module address in the USB data was rejected and thus I'm not sure
> it will work without that.
For v3.7-rc timeframe, looks like it's waiting on an ack from you:
http://www.spinics.net/lists/arm-kernel/msg201028.html
- Paul
^ permalink raw reply
* [GIT PULL] omap plat header removal for v3.8 merge window, part1
From: Tony Lindgren @ 2012-10-26 17:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201210261728.22132.arnd@arndb.de>
* Arnd Bergmann <arnd@arndb.de> [121026 10:30]:
> On Friday 26 October 2012, Tony Lindgren wrote:
> > * Arnd Bergmann <arnd@arndb.de> [121026 07:04]:
> >
> > > I tried running my old multiplatform scripts again and have a few
> > > comments, but none of them serious:
> > >
> > > $ git grep include.*mach-omap2
> > > arch/arm/plat-omap/debug-devices.c:#include "../mach-omap2/debug-devices.h"
> > > arch/arm/plat-omap/dma.c:#include "../mach-omap2/soc.h"
> > > arch/arm/plat-omap/dmtimer.c:#include "../mach-omap2/omap-pm.h"
> > > arch/arm/plat-omap/i2c.c:#include "../mach-omap2/soc.h"
> > > arch/arm/plat-omap/include/plat/cpu.h:#include "../../mach-omap2/soc.h"
> > > arch/arm/plat-omap/omap-pm-noop.c:#include "../mach-omap2/omap_device.h"
> > > arch/arm/plat-omap/omap-pm-noop.c:#include "../mach-omap2/omap-pm.h"
> > > arch/arm/plat-omap/sram.c:#include "../mach-omap2/soc.h"
> > > arch/arm/plat-omap/sram.c:#include "../mach-omap2/iomap.h"
> > > arch/arm/plat-omap/sram.c:#include "../mach-omap2/prm2xxx_3xxx.h"
> > > arch/arm/plat-omap/sram.c:#include "../mach-omap2/sdrc.h"
> > >
> > > I don't like the relative include paths too much. I would have preferred
> > > adding the mach-omap2/include/mach path in the plat-omap Makefile, but
> > > I suppose you want to leave it like it is now since you mention you
> > > have already built on top of it.
> >
> > Well I wanted to keep them local to arch/arm/*omap*/ directories,
> > and not have them exposed at all for drivers.
> >
> > Other than that I don't have an issue using non-relative paths, except
> > mach-omap2/include/mach traditionally has been exposed to drivers
> > as the legacy #include <mach/*.h>, so IMHO local headers in the
> > arch/arm/*omap*/ directories are better.
> >
> > But now I wonder if we can somehow have drivers not be able to
> > include these local headers?
>
> Well, once CONFIG_MULTIPLATFORM gets enabled, the mach/*.h files are
> not visible to drivers any more, but they are still visible to files
> in plat-omap if you add a line like
>
> ccflags-$(CONFIG_ARCH_OMAP2) := -I$(srctree)/arch/arm/mach-omap2/include
> ccflags-$(CONFIG_ARCH_OMAP1) := -I$(srctree)/arch/arm/mach-omap1/include
>
> to arch/arm/plat-omap/Makefile. That is how the other multiplatform
> Makefiles do it. If a driver writer really wants to cheat, they can of
> course do the same thing in their directory, but they can also do
> #include "../../../../arch/arm/mach-omap2/foo.h"
OK thanks for clarifying that. Sounds like that can be used to
fix up the relative includes for plat-omap. I'll do some patches
for that after we have the #include <plat/*.h> and #include <mach/*.h>
issue sorted out.
> > > sound/soc/omap/am3517evm.c:#include <mach-omap2/hardware.h>
> > > sound/soc/omap/am3517evm.c:#include <mach-omap2/gpio.h>
> > > sound/soc/omap/ams-delta.c:#include <mach-omap2/board-ams-delta.h>
> > > sound/soc/omap/n810.c:#include <mach-omap2/hardware.h>
> > > sound/soc/omap/sdp3430.c:#include <mach-omap2/hardware.h>
> > > sound/soc/omap/sdp3430.c:#include <mach-omap2/gpio.h>
> > > sound/soc/omap/zoom2.c:#include <mach-omap2/hardware.h>
> > > sound/soc/omap/zoom2.c:#include <mach-omap2/gpio.h>
> > > sound/soc/omap/zoom2.c:#include <mach-omap2/board-zoom.h>
> > >
> > > Not sure if you were just missing these or if you already have other
> > > patch lined up for them.
> >
> > In which branch do you see the above?
> >
> > I'm not seeing them in v3.7-rc2, looks like all sound/soc/omap/*.c
> > files have already been fixed up.
>
> I am looking at the arm-soc for-next branch, which is based on v3.7-rc2.
>
> Note that before my script, this reads
>
> #include <mach/hardware.h>
>
> not
>
> #include <mach-omap2/hardware.h>
>
> but the effect is the same if the file is not available.
Well for omap2+, drivers should no longer include anything
with #include <mach/*.h> (or #include <mach-omap2/hardware.h>)
and the drivers should be fixed instead.
For omap2+, mach/hardware.h is empty now. It still needs to be
included for omap1, so that might require some conditional
includes for the shared code between omap1 and omap2+ like
sound/soc/omap/*mcbsp*.c. And that code should just be able
to use platform_data for omap1, and not need hardware.h either
eventually.
AFAIK, all the sound/soc/omap/*.c files are almost fixed up
for omap2+, so let's not change those includes in arm-soc tree
as that will just cause conflicts. All the remaining
#include <mach/*.h> and #include <plat/*.h> under sound/soc/omap
can eventually be just removed for omap2+.
For omap1, we can just leave them as they are for now. Those
are the sound/soc/omap/ams-delta.c and sound/soc/omap/osk5912.c
files for omap1.
> > In any case, let's not have #include <mach-omap1/*.h> or
> > #include <mach-omap2/*.h> includes in the drivers, they are
> > wrong. Those headers are meant to be local, the legacy shared
> > headers should be in #include <mach/*.h>. Whatever needs to
> > be passed from arch/arm/*omap*/ to drivers, should be done
> > using include/linux/platform_data/*.h files.
>
> I'm not suggesting to use mach-omap2/*.h, it's just what my
> old script shows when hunting for platform header files that are
> used in device drivers.
OK makes sense :) Well we should no have any of them after
v3.8 merge window except for the legacy ones for omap1.
Your script found a real issue though, and that's the tidspbridge
include of private headers from mach-omap2! That's something
that needs to be fixed or removed to cut the dependency between
core omap code and device drivers.
> > For omap1, we might as well keep the existing ones from
> > #include <mach/*.h> as they are until somebody wants to fix
> > up things properly for omap1 for CONFIG_MULTIPLATFORM.
>
> Fair enough.
Sounds good.
Tony
^ permalink raw reply
* [PATCH 0/7] ARM: EXYNOS: add support for new EXYNOS5440 SoC
From: Kukjin Kim @ 2012-10-26 17:55 UTC (permalink / raw)
To: linux-arm-kernel
This is for adding support EXYNOS5440 SoC which is including Cortex-A15 Quad cores and SSDK5440 board.
Note: this is based on Samsung common clk work and 3rd patch for uart is wip.
[PATCH 1/7] ARM: EXYNOS: add support for EXYNOS5440 SoC
[PATCH 2/7] clk: exynos5440: add common clock support for Samsung EXYNOS5440
[PATCH 3/7] ARM: EXYNOS: add support uart for EXYNOS SoCs - WIP
[PATCH 4/7] ARM: dts: add initial dts file for EXYNOS5440, SSDK5440
[PATCH 5/7] ARM: dts: add clock controller node for Samsung EXYNOS5440
[PATCH 6/7] pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC
[PATCH 7/7] ARM: dts: Add pin controller node for Samsung EXYNOS5440 SoC
Kukjin Kim (3):
ARM: EXYNOS: add support for EXYNOS5440 SoC
ARM: EXYNOS: add support uart for EXYNOS SoCs - WIP
ARM: dts: add initial dts file for EXYNOS5440, SSDK5440
Thomas Abraham (4):
clk: exynos5440: add common clock support for Samsung EXYNOS5440
ARM: dts: add clock controller node for Samsung EXYNOS5440
pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC
ARM: dts: Add pin controller node for Samsung EXYNOS5440 SoC
arch/arm/boot/dts/exynos5440-clock.dtsi | 143 ++++
arch/arm/boot/dts/exynos5440-ssdk5440.dts | 49 ++
arch/arm/boot/dts/exynos5440.dtsi | 159 +++++
arch/arm/mach-exynos/Kconfig | 20 +
arch/arm/mach-exynos/Makefile | 3 +-
arch/arm/mach-exynos/common.c | 85 +++-
arch/arm/mach-exynos/common.h | 2 +
arch/arm/mach-exynos/dev-uart.c | 14 +
arch/arm/mach-exynos/include/mach/irqs.h | 5 +
arch/arm/mach-exynos/include/mach/map.h | 8 +
arch/arm/mach-exynos/include/mach/regs-pmu.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 34 +-
arch/arm/mach-exynos/mct.c | 15 +
arch/arm/mach-exynos/setup-i2c0.c | 2 +-
arch/arm/plat-samsung/include/plat/cpu.h | 8 +
arch/arm/plat-samsung/include/plat/devs.h | 1 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5440.c | 66 ++
drivers/pinctrl/Kconfig | 5 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-exynos5440.c | 919 ++++++++++++++++++++++++++
drivers/tty/serial/samsung.c | 3 +-
22 files changed, 1527 insertions(+), 17 deletions(-)
^ permalink raw reply
* [PATCH 1/7] ARM: EXYNOS: add support for EXYNOS5440 SoC
From: Kukjin Kim @ 2012-10-26 17:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351274153-3120-1-git-send-email-kgene.kim@samsung.com>
This patch adds support for EXYNOS5440 SoC which is including
Cortex-A15 Quad cores.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos/Kconfig | 20 ++++++
arch/arm/mach-exynos/Makefile | 3 +-
arch/arm/mach-exynos/common.c | 85 ++++++++++++++++++++++++--
arch/arm/mach-exynos/common.h | 2 +
arch/arm/mach-exynos/dev-uart.c | 14 ++++
arch/arm/mach-exynos/include/mach/irqs.h | 5 ++
arch/arm/mach-exynos/include/mach/map.h | 8 +++
arch/arm/mach-exynos/include/mach/regs-pmu.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 34 ++++++++---
arch/arm/mach-exynos/mct.c | 15 +++++
arch/arm/mach-exynos/setup-i2c0.c | 2 +-
arch/arm/plat-samsung/include/plat/cpu.h | 8 +++
arch/arm/plat-samsung/include/plat/devs.h | 1 +
drivers/tty/serial/samsung.c | 3 +-
14 files changed, 184 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 1d0d083..c047aba 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -68,6 +68,16 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5440
+ bool "SAMSUNG EXYNOS5440"
+ default y
+ depends on ARCH_EXYNOS5
+ select ARM_ARCH_TIMER
+ select AUTO_ZRELADDR
+ select COMMON_CLK
+ help
+ Enable EXYNOS5440 SoC support
+
config EXYNOS4_MCT
bool
default y
@@ -426,6 +436,16 @@ config MACH_EXYNOS5_DT
Machine support for Samsung EXYNOS5 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS5 SoC based board.
+config MACH_EXYNOS5440_DT
+ bool "SAMSUNG EXYNOS5440 Machine using device tree"
+ depends on ARCH_EXYNOS5
+ select ARM_AMBA
+ select SOC_EXYNOS5440
+ select USE_OF
+ help
+ Machine support for Samsung EXYNOS5440 machine with device tree enabled.
+ Select this if a fdt blob is available for the EXYNOS5440 SoC based board.
+
if ARCH_EXYNOS4
comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index ad66c9f4..92df758 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -13,7 +13,7 @@ obj- :=
# Core
obj-$(CONFIG_ARCH_EXYNOS) += common.o
-obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o
+obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
@@ -41,6 +41,7 @@ obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
+obj-$(CONFIG_MACH_EXYNOS5440_DT) += mach-exynos5-dt.o
# device support
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index fea1542..786d8f4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -57,9 +57,11 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5440[] = "EXYNOS5440";
static void exynos4_map_io(void);
static void exynos5_map_io(void);
+static void exynos5440_map_io(void);
static void exynos5_init_clocks(int xtal);
static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
static int exynos_init(void);
@@ -94,6 +96,13 @@ static struct cpu_table cpu_ids[] __initdata = {
.init_uarts = exynos_init_uarts,
.init = exynos_init,
.name = name_exynos5250,
+ }, {
+ .idcode = EXYNOS5440_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5440_map_io,
+ .init_uarts = exynos_init_uarts,
+ .init = exynos_init,
+ .name = name_exynos5440,
},
};
@@ -108,6 +117,15 @@ static struct map_desc exynos_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5440_iodesc[] __initdata = {
+ {
+ .virtual = (unsigned long)S5P_VA_CHIPID,
+ .pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos4_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_SYS,
@@ -274,6 +292,25 @@ static struct map_desc exynos5_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5440_iodesc0[] __initdata = {
+ {
+ .virtual = (unsigned long)S3C_VA_UART,
+ .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
+ .length = SZ_512K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_GIC_CPU,
+ .pfn = __phys_to_pfn(EXYNOS5440_PA_GIC_CPU),
+ .length = SZ_64K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_GIC_DIST,
+ .pfn = __phys_to_pfn(EXYNOS5440_PA_GIC_DIST),
+ .length = SZ_64K,
+ .type = MT_DEVICE,
+ },
+};
+
void exynos4_restart(char mode, const char *cmd)
{
__raw_writel(0x1, S5P_SWRESET);
@@ -281,11 +318,29 @@ void exynos4_restart(char mode, const char *cmd)
void exynos5_restart(char mode, const char *cmd)
{
- __raw_writel(0x1, EXYNOS_SWRESET);
+ u32 val;
+ void __iomem *addr;
+
+ if (of_machine_is_compatible("samsung,exynos5250")) {
+ val = 0x1;
+ addr = EXYNOS_SWRESET;
+ } else if (of_machine_is_compatible("samsung,exynos5440")) {
+ val = (0x10 << 20) | (0x1 << 16);
+ addr = EXYNOS5440_SWRESET;
+ } else {
+ pr_err("%s: cannot support non-DT\n", __func__);
+ return;
+ }
+
+ __raw_writel(val, addr);
}
void __init exynos_init_late(void)
{
+ if (of_machine_is_compatible("samsung,exynos5440"))
+ /* to be supported later */
+ return;
+
exynos_pm_late_initcall();
}
@@ -298,7 +353,11 @@ void __init exynos_init_late(void)
void __init exynos_init_io(struct map_desc *mach_desc, int size)
{
/* initialize the io descriptors we need for initialization */
- iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
+ if (of_machine_is_compatible("samsung,exynos5440"))
+ iotable_init(exynos5440_iodesc, ARRAY_SIZE(exynos5440_iodesc));
+ else
+ iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
+
if (mach_desc)
iotable_init(mach_desc, size);
@@ -364,6 +423,11 @@ static void __init exynos5_map_io(void)
s3c_i2c2_setname("s3c2440-i2c");
}
+static void __init exynos5440_map_io(void)
+{
+ iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
+}
+
static void __init exynos5_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -587,6 +651,11 @@ static const struct of_device_id exynos4_dt_irq_match[] = {
.data = combiner_of_init, },
{},
};
+
+static const struct of_device_id exynos5440_dt_irq_match[] = {
+ { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
+ {},
+};
#endif
void __init exynos4_init_irq(void)
@@ -616,14 +685,18 @@ void __init exynos4_init_irq(void)
void __init exynos5_init_irq(void)
{
#ifdef CONFIG_OF
- of_irq_init(exynos4_dt_irq_match);
+ if (soc_is_exynos5440())
+ of_irq_init(exynos5440_dt_irq_match);
+ else
+ of_irq_init(exynos4_dt_irq_match);
#endif
/*
* The parameters of s5p_init_irq() are for VIC init.
* Theses parameters should be NULL and 0 because EXYNOS4
* uses GIC instead of VIC.
*/
- s5p_init_irq(NULL, 0);
+ if (!soc_is_exynos5440())
+ s5p_init_irq(NULL, 0);
}
struct bus_type exynos_subsys = {
@@ -646,7 +719,7 @@ static int __init exynos4_l2x0_cache_init(void)
{
int ret;
- if (soc_is_exynos5250())
+ if (soc_is_exynos5250() || soc_is_exynos5440())
return 0;
ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
@@ -714,6 +787,8 @@ static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
if (soc_is_exynos5250())
s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
+ else if (soc_is_exynos5440())
+ s3c24xx_init_uartdevs("exynos4210-uart", exynos5440_uart_resources, cfg, no);
else
s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
}
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 7a4e0ea..99b88f8 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -13,9 +13,11 @@
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
extern struct sys_timer exynos4_timer;
+extern struct sys_timer exynos5_timer;
struct map_desc;
void exynos_init_io(struct map_desc *mach_desc, int size);
+void exynos5440_init_io(struct map_desc *mach_desc, int size);
void exynos4_init_irq(void);
void exynos5_init_irq(void);
void exynos4_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
index 2e85c02..95b887f 100644
--- a/arch/arm/mach-exynos/dev-uart.c
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -76,3 +76,17 @@ struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
.nr_resources = ARRAY_SIZE(exynos5_uart3_resource),
},
};
+
+EXYNOS_UART_RESOURCE(5440, 0)
+EXYNOS_UART_RESOURCE(5440, 1)
+
+struct s3c24xx_uart_resources exynos5440_uart_resources[] __initdata = {
+ [0] = {
+ .resources = exynos5440_uart0_resource,
+ .nr_resources = ARRAY_SIZE(exynos5440_uart0_resource),
+ },
+ [1] = {
+ .resources = exynos5440_uart1_resource,
+ .nr_resources = ARRAY_SIZE(exynos5440_uart0_resource),
+ },
+};
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 35bced6..f43a96c 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -333,6 +333,11 @@
#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
+/* EXYNOS5440 */
+
+#define EXYNOS5440_IRQ_UART0 IRQ_SPI(2)
+#define EXYNOS5440_IRQ_UART1 IRQ_SPI(3)
+
#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 8480849..d0602d3 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -53,12 +53,14 @@
#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
#define EXYNOS_PA_CHIPID 0x10000000
+#define EXYNOS5440_PA_CHIPID 0x00160000
#define EXYNOS4_PA_SYSCON 0x10010000
#define EXYNOS5_PA_SYSCON 0x10050100
#define EXYNOS4_PA_PMU 0x10020000
#define EXYNOS5_PA_PMU 0x10040000
+#define EXYNOS5440_PA_PMU 0x00160000
#define EXYNOS4_PA_CMU 0x10030000
#define EXYNOS5_PA_CMU 0x10010000
@@ -83,6 +85,8 @@
#define EXYNOS4_PA_GIC_DIST 0x10490000
#define EXYNOS5_PA_GIC_CPU 0x10482000
#define EXYNOS5_PA_GIC_DIST 0x10481000
+#define EXYNOS5440_PA_GIC_CPU 0x002E2000
+#define EXYNOS5440_PA_GIC_DIST 0x002E1000
#define EXYNOS4_PA_COREPERI 0x10500000
#define EXYNOS4_PA_TWD 0x10500600
@@ -281,6 +285,10 @@
#define EXYNOS5_PA_UART3 0x12C30000
#define EXYNOS5_SZ_UART SZ_256
+#define EXYNOS5440_PA_UART0 0x000B0000
+#define EXYNOS5440_PA_UART1 0x000C0000
+#define EXYNOS5440_SZ_UART SZ_256
+
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index d4e392b..c0b74f3 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -31,6 +31,7 @@
#define S5P_SWRESET S5P_PMUREG(0x0400)
#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
+#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index db1cd8e..7052f80 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -75,20 +75,24 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
{},
};
-static void __init exynos5250_dt_map_io(void)
+static void __init exynos5_dt_map_io(void)
{
exynos_init_io(NULL, 0);
- s3c24xx_init_clocks(24000000);
+
+ if (of_machine_is_compatible("samsung,exynos5250"))
+ s3c24xx_init_clocks(24000000);
}
-static void __init exynos5250_dt_machine_init(void)
+static void __init exynos5_dt_machine_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- exynos5250_auxdata_lookup, NULL);
+ if (of_machine_is_compatible("samsung,exynos5250"))
+ of_platform_populate(NULL, of_default_bus_match_table,
+ exynos5250_auxdata_lookup, NULL);
}
-static char const *exynos5250_dt_compat[] __initdata = {
+static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5440",
NULL
};
@@ -96,11 +100,23 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.init_irq = exynos5_init_irq,
.smp = smp_ops(exynos_smp_ops),
- .map_io = exynos5250_dt_map_io,
+ .map_io = exynos5_dt_map_io,
.handle_irq = gic_handle_irq,
- .init_machine = exynos5250_dt_machine_init,
+ .init_machine = exynos5_dt_machine_init,
.init_late = exynos_init_late,
.timer = &exynos4_timer,
- .dt_compat = exynos5250_dt_compat,
+ .dt_compat = exynos5_dt_compat,
+ .restart = exynos5_restart,
+MACHINE_END
+
+DT_MACHINE_START(EXYNOS5440_DT, "SAMSUNG EXYNOS5440 (Flattened Device Tree)")
+ /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+ .init_irq = exynos5_init_irq,
+ .smp = smp_ops(exynos_smp_ops),
+ .map_io = exynos5_dt_map_io,
+ .handle_irq = gic_handle_irq,
+ .init_machine = exynos5_dt_machine_init,
+ .timer = &exynos5_timer,
+ .dt_compat = exynos5_dt_compat,
.restart = exynos5_restart,
MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index cc3805a..31f45ec 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -19,7 +19,9 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/percpu.h>
+#include <linux/of.h>
+#include <asm/arch_timer.h>
#include <asm/hardware/gic.h>
#include <asm/localtimer.h>
@@ -487,6 +489,9 @@ static void __init exynos4_timer_init(void)
exynos4x12_clk_init();
#endif
+ if (of_machine_is_compatible("samsung,exynos5440"))
+ arch_timer_of_register();
+
if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
mct_int_type = MCT_INT_SPI;
else
@@ -500,3 +505,13 @@ static void __init exynos4_timer_init(void)
struct sys_timer exynos4_timer = {
.init = exynos4_timer_init,
};
+
+static void __init exynos5_timer_init(void)
+{
+ if (of_machine_is_compatible("samsung,exynos5440"))
+ arch_timer_of_register();
+}
+
+struct sys_timer exynos5_timer = {
+ .init = exynos5_timer_init,
+};
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index 5700f23..e2d9dfb 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -20,7 +20,7 @@ struct platform_device; /* don't need the contents */
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
- if (soc_is_exynos5250())
+ if (soc_is_exynos5250() || soc_is_exynos5440())
/* will be implemented with gpio function */
return;
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index ace4451..e0072ce 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -43,6 +43,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define EXYNOS5250_SOC_ID 0x43520000
+#define EXYNOS5440_SOC_ID 0x54400000
#define EXYNOS5_SOC_MASK 0xFFFFF000
#define IS_SAMSUNG_CPU(name, id, mask) \
@@ -62,6 +63,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -130,6 +132,12 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
# define soc_is_exynos5250() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS5440)
+# define soc_is_exynos5440() is_samsung_exynos5440()
+#else
+# define soc_is_exynos5440() 0
+#endif
+
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
#ifndef KHZ
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 5da4b4f..cd90038 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -28,6 +28,7 @@ extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
extern struct s3c24xx_uart_resources s5p_uart_resources[];
extern struct s3c24xx_uart_resources exynos4_uart_resources[];
extern struct s3c24xx_uart_resources exynos5_uart_resources[];
+extern struct s3c24xx_uart_resources exynos5440_uart_resources[];
extern struct platform_device *s3c24xx_uart_devs[];
extern struct platform_device *s3c24xx_uart_src[];
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 7f04717..0e26a16 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1646,7 +1646,8 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
#endif
#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
- defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
+ defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
+ defined(CONFIG_SOC_EXYNOS5440)
static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
.info = &(struct s3c24xx_uart_info) {
.name = "Samsung Exynos4 UART",
--
1.7.4.4
^ permalink raw reply related
* [PATCH 2/7] clk: exynos5440: add common clock support for Samsung EXYNOS5440
From: Kukjin Kim @ 2012-10-26 17:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351274153-3120-1-git-send-email-kgene.kim@samsung.com>
From: Thomas Abraham <thomas.abraham@linaro.org>
This patch adds clock controller configuration support based on common
clock framework for Samsung EXYNOS5440.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5440.c | 66 ++++++++++++++++++++++++++++++++++
2 files changed, 67 insertions(+), 0 deletions(-)
create mode 100644 drivers/clk/samsung/clk-exynos5440.c
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 69487f7..27aab2c 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -4,3 +4,4 @@
obj-$(CONFIG_PLAT_SAMSUNG) += clk.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
+obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
new file mode 100644
index 0000000..da3b918
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk.h"
+
+static void __iomem *clk_base;
+
+/* register a fixed factor clock type instantiated from device tree */
+void __init samsung_of_clk_register_fixed_factor(struct device_node *np)
+{
+ struct clk *clk;
+ const char *clk_name = np->name;
+ const char *parent_name;
+ u32 mul = 1, div = 1;
+
+ of_property_read_string(np, "clock-output-names", &clk_name);
+ parent_name = of_clk_get_parent_name(np, 0);
+ of_property_read_u32(np, "clock-fixed-factor-mul", &mul);
+ of_property_read_u32(np, "clock-fixed-factor-div", &div);
+
+ clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
+ mul, div);
+ if (clk)
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static const __initconst struct of_device_id clk_match[] = {
+ { .compatible = "fixed-clock",
+ .data = of_fixed_clk_setup, },
+ { .compatible = "samsung,clock-gate",
+ .data = samsung_of_clk_register_gate, },
+ { .compatible = "samsung,fixed-factor-clock",
+ .data = samsung_of_clk_register_fixed_factor, },
+ {},
+};
+
+void __init exynos5440_of_clk_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-xmu");
+ if (!np) {
+ pr_err("%s: clock controller node not found\n", __func__);
+ return;
+ }
+
+ clk_base = of_iomap(np, 0);
+ WARN(!clk_base, "unable to map clocks registers\n");
+
+ samsung_clk_set_ctrl_base(clk_base);
+ of_clk_init(clk_match);
+}
+
+arch_initcall(exynos5440_of_clk_init);
--
1.7.4.4
^ permalink raw reply related
* [PATCH 4/7] ARM: dts: add initial dts file for EXYNOS5440, SSDK5440
From: Kukjin Kim @ 2012-10-26 17:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351274153-3120-1-git-send-email-kgene.kim@samsung.com>
This patch adds initial dts file for EXYNOS5440 SoC and adds the
dts file for SSDK5440 board which is a kind of reference board.
More properties will be added later.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/boot/dts/exynos5440-ssdk5440.dts | 49 ++++++++++
arch/arm/boot/dts/exynos5440.dtsi | 142 +++++++++++++++++++++++++++++
2 files changed, 191 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos5440-ssdk5440.dts
create mode 100644 arch/arm/boot/dts/exynos5440.dtsi
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
new file mode 100644
index 0000000..82960f0
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -0,0 +1,49 @@
+/*
+ * SAMSUNG SSDK5440 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5440.dtsi"
+
+/ {
+ model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
+ compatible = "samsung,ssdk5440", "samsung,exynos5440";
+
+ memory {
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC2,115200 init=/linuxrc";
+ };
+
+ spi {
+ status = "disabled";
+ };
+
+ i2c at F0000 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <20000>;
+ gpios = <&gpb3 0 2 3 0>,
+ <&gpb3 1 2 3 0>;
+ };
+
+ i2c at 100000 {
+ status = "disabled";
+ };
+
+ watchdog {
+ status = "disabled";
+ };
+
+ rtc {
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
new file mode 100644
index 0000000..380a89a
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -0,0 +1,142 @@
+/*
+ * SAMSUNG EXYNOS5440 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "samsung,exynos5440";
+
+ interrupt-parent = <&gic>;
+
+ gic:interrupt-controller at 2E0000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x2E0000 0x1000>, <0x2E1000 0x1000>;
+ };
+
+ cpus {
+ cpu at 0 {
+ compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <? ? ?>;
+ clock-frequency = <1000000>;
+ };
+ };
+ cpu at 1 {
+ compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 14 0x308>;
+ clock-frequency = <1000000>;
+ };
+ };
+ cpu at 2 {
+ compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 14 0x308>;
+ clock-frequency = <1000000>;
+ };
+ };
+ cpu at 3 {
+ compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 14 0x308>;
+ clock-frequency = <1000000>;
+ };
+ };
+ };
+
+ common {
+ compatible = "samsung,exynos5440";
+
+ };
+
+ serial at B0000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0xB0000 0x1000>;
+ interrupts = <0 2 0>;
+ };
+
+ serial at C0000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0xC0000 0x1000>;
+ interrupts = <0 3 0>;
+ };
+
+ spi {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0xD0000 0x1000>;
+ interrupts = <0 4 0>;
+ tx-dma-channel = <&pdma0 5>; /* preliminary */
+ rx-dma-channel = <&pdma0 4>; /* preliminary */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pinctrl {
+ compatible = "samsung,pinctrl-exynos5440";
+ reg = <0xE0000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ i2c at F0000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0xF0000 0x1000>;
+ interrupts = <0 5 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c at 100000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x100000 0x1000>;
+ interrupts = <0 6 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ watchdog {
+ compatible = "samsung,s3c2410-wdt";
+ reg = <0x110000 0x1000>;
+ interrupts = <0 1 0>;
+ };
+
+ amba {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "arm,amba-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ pdma0: pdma at 121A0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x120000 0x1000>;
+ interrupts = <0 34 0>;
+ };
+
+ pdma1: pdma at 121B0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x121000 0x1000>;
+ interrupts = <0 35 0>;
+ };
+ };
+
+ rtc {
+ compatible = "samsung,s3c6410-rtc";
+ reg = <0x130000 0x1000>;
+ interrupts = <0 16 0>, <0 17 0>;
+ };
+};
--
1.7.4.4
^ permalink raw reply related
* [PATCH 5/7] ARM: dts: add clock controller node for Samsung EXYNOS5440
From: Kukjin Kim @ 2012-10-26 17:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351274153-3120-1-git-send-email-kgene.kim@samsung.com>
From: Thomas Abraham <thomas.abraham@linaro.org>
This patch add device tree nodes for representing the clock controller
module in Samsung EXYNOS5440 SoC.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/boot/dts/exynos5440-clock.dtsi | 143 +++++++++++++++++++++++++++++++
1 files changed, 143 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos5440-clock.dtsi
diff --git a/arch/arm/boot/dts/exynos5440-clock.dtsi b/arch/arm/boot/dts/exynos5440-clock.dtsi
new file mode 100644
index 0000000..062f29f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440-clock.dtsi
@@ -0,0 +1,143 @@
+/*
+ * Samsung's EXYNOS5440 SoC clock nodes
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ xmu {
+ compatible = "samsung,exynos5440-xmu";
+ reg = <0x160000 0x1000>;
+
+ xtal: xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "xtal";
+ clock-frequency = <50000000>;
+ };
+
+ peri_pll: peri-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "xusbxti";
+ clock-frequency = <1000000000>;
+ };
+
+ peri_250mhz: peri-250mhz {
+ compatible = "samsung,fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-output-names = "peri-250mhz";
+ clocks = <&peri_pll>;
+ clock-fixed-factor-div = <4>;
+ };
+
+ peri_200mhz: peri-200mhz {
+ compatible = "samsung,fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-output-names = "peri-200mhz";
+ clocks = <&peri_pll>;
+ clock-fixed-factor-div = <5>;
+ };
+
+ peri_125mhz: peri-125mhz {
+ compatible = "samsung,fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-output-names = "peri-125mhz";
+ clocks = <&peri_250mhz>;
+ clock-fixed-factor-div = <2>;
+ };
+
+ b250_clk: b250-clk {
+ compatible = "samsung,clock-gate";
+ #clock-cells = <0>;
+ clock-output-names = "b250-clk";
+ clocks = <&peri_250mhz>;
+ reg-info = <0xf4 0>;
+ };
+
+ pb0250_clk: pb0250-clk {
+ compatible = "samsung,clock-gate";
+ #clock-cells = <0>;
+ clock-output-names = "pb0250-clk";
+ clocks = <&peri_250mhz>;
+ reg-info = <0xf4 1>;
+ };
+
+ pr0250_clk: pr0250-clk {
+ compatible = "samsung,clock-gate";
+ #clock-cells = <0>;
+ clock-output-names = "pr0250-clk";
+ clocks = <&peri_250mhz>;
+ reg-info = <0xf4 2>;
+ };
+
+ pr1250_clk: pr1250-clk {
+ compatible = "samsung,clock-gate";
+ #clock-cells = <0>;
+ clock-output-names = "pr1250-clk";
+ clocks = <&peri_250mhz>;
+ reg-info = <0xf4 3>;
+ };
+
+ cs250_clk: cs250-clk {
+ compatible = "samsung,clock-gate";
+ #clock-cells = <0>;
+ clock-output-names = "cs250-clk";
+ clocks = <&peri_250mhz>;
+ reg-info = <0xf4 4>;
+ };
+
+ drex_pclk: drex-pclk {
+ compatible = "samsung,clock-gate";
+ #clock-cells = <0>;
+ clock-output-names = "drex-pclk";
+ clocks = <&peri_125mhz>;
+ reg-info = <0xf4 5>;
+ };
+
+ b125_pclk: b125-pclk {
+ compatible = "samsung,clock-gate";
+ #clock-cells = <0>;
+ clock-output-names = "b125-pclk";
+ clocks = <&peri_125mhz>;
+ reg-info = <0xf4 6>;
+ };
+
+ b200_clk: b200-clk {
+ compatible = "samsung,clock-gate";
+ #clock-cells = <0>;
+ clock-output-names = "b200-clk";
+ clocks = <&peri_200mhz>;
+ reg-info = <0xf4 7>;
+ };
+
+ sata_clk: sata-clk {
+ compatible = "samsung,clock-gate";
+ #clock-cells = <0>;
+ clock-output-names = "sata-clk";
+ clocks = <&peri_200mhz>;
+ reg-info = <0xf4 8>;
+ };
+
+ usb_clk: usb-clk {
+ compatible = "samsung,clock-gate";
+ #clock-cells = <0>;
+ clock-output-names = "usb-clk";
+ clocks = <&peri_200mhz>;
+ reg-info = <0xf4 9>;
+ };
+
+ gmac0_clk: gmac0-clk {
+ compatible = "samsung,clock-gate";
+ #clock-cells = <0>;
+ clock-output-names = "gmac0-clk";
+ clocks = <&peri_200mhz>;
+ reg-info = <0xf4 10>;
+ };
+ };
+};
--
1.7.4.4
^ permalink raw reply related
* [PATCH 6/7] pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC
From: Kukjin Kim @ 2012-10-26 17:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351274153-3120-1-git-send-email-kgene.kim@samsung.com>
From: Thomas Abraham <thomas.abraham@linaro.org>
Add a new pinctrl driver for Samsung EXYNOS5440 SoC. The pin controller
module in EXYNOS5440 is different from the pin controller found on other
Samsung SoC. Hence, the pin controller driver for EXYNOS5440 SoC is
independent of the Samsung pinctrl framework.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
drivers/pinctrl/Kconfig | 5 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-exynos5440.c | 919 ++++++++++++++++++++++++++++++++++
3 files changed, 925 insertions(+), 0 deletions(-)
create mode 100644 drivers/pinctrl/pinctrl-exynos5440.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 7bf914d..ddb201d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -186,6 +186,11 @@ config PINCTRL_EXYNOS4
bool "Pinctrl driver data for Exynos4 SoC"
select PINCTRL_SAMSUNG
+config PINCTRL_EXYNOS5440
+ bool "Samsung EXYNOS5440 SoC pinctrl driver"
+ select PINMUX
+ select PINCONF
+
config PINCTRL_MVEBU
bool
depends on ARCH_MVEBU
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f395ba5..476928b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
obj-$(CONFIG_PINCTRL_EXYNOS4) += pinctrl-exynos.o
+obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o
obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c
new file mode 100644
index 0000000..b8635f6
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-exynos5440.c
@@ -0,0 +1,919 @@
+/*
+ * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include "core.h"
+
+/* EXYNOS5440 GPIO and Pinctrl register offsets */
+#define GPIO_MUX 0x00
+#define GPIO_IE 0x04
+#define GPIO_INT 0x08
+#define GPIO_TYPE 0x0C
+#define GPIO_VAL 0x10
+#define GPIO_OE 0x14
+#define GPIO_IN 0x18
+#define GPIO_PE 0x1C
+#define GPIO_PS 0x20
+#define GPIO_SR 0x24
+#define GPIO_DS0 0x28
+#define GPIO_DS1 0x2C
+
+#define EXYNOS5440_MAX_PINS 23
+#define PIN_NAME_LENGTH 10
+
+#define GROUP_SUFFIX "-grp"
+#define GSUFFIX_LEN sizeof(GROUP_SUFFIX)
+#define FUNCTION_SUFFIX "-mux"
+#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX)
+
+/*
+ * pin configuration type and its value are packed together into a 16-bits.
+ * The upper 8-bits represent the configuration type and the lower 8-bits
+ * hold the value of the configuration type.
+ */
+#define PINCFG_TYPE_MASK 0xFF
+#define PINCFG_VALUE_SHIFT 8
+#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
+#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
+#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
+#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
+ PINCFG_VALUE_SHIFT)
+
+/**
+ * enum pincfg_type - possible pin configuration types supported.
+ * @PINCFG_TYPE_PUD: Pull up/down configuration.
+ * @PINCFG_TYPE_DRV: Drive strength configuration.
+ * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
+ * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
+ */
+enum pincfg_type {
+ PINCFG_TYPE_PUD,
+ PINCFG_TYPE_DRV,
+ PINCFG_TYPE_SKEW_RATE,
+ PINCFG_TYPE_INPUT_TYPE
+};
+
+/**
+ * struct exynos5440_pin_group: represent group of pins for pincfg setting.
+ * @name: name of the pin group, used to lookup the group.
+ * @pins: the pins included in this group.
+ * @num_pins: number of pins included in this group.
+ */
+struct exynos5440_pin_group {
+ const char *name;
+ const unsigned int *pins;
+ u8 num_pins;
+};
+
+/**
+ * struct exynos5440_pmx_func: represent a pin function.
+ * @name: name of the pin function, used to lookup the function.
+ * @groups: one or more names of pin groups that provide this function.
+ * @num_groups: number of groups included in @groups.
+ * @function: the function number to be programmed when selected.
+ */
+struct exynos5440_pmx_func {
+ const char *name;
+ const char **groups;
+ u8 num_groups;
+ unsigned long function;
+};
+
+/**
+ * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
+ * @reg_base: ioremapped based address of the register space.
+ * @gc: gpio chip registered with gpiolib.
+ * @pin_groups: list of pin groups parsed from device tree.
+ * @nr_groups: number of pin groups available.
+ * @pmx_functions: list of pin functions parsed from device tree.
+ * @nr_functions: number of pin functions available.
+ */
+struct exynos5440_pinctrl_priv_data {
+ void __iomem *reg_base;
+ struct gpio_chip *gc;
+
+ const struct exynos5440_pin_group *pin_groups;
+ unsigned int nr_groups;
+ const struct exynos5440_pmx_func *pmx_functions;
+ unsigned int nr_functions;
+};
+
+/* list of all possible config options supported */
+struct pin_config {
+ char *prop_cfg;
+ unsigned int cfg_type;
+} pcfgs[] = {
+ { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
+ { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
+ { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
+ { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
+};
+
+/* check if the selector is a valid pin group selector */
+static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
+{
+ struct exynos5440_pinctrl_priv_data *priv;
+
+ priv = pinctrl_dev_get_drvdata(pctldev);
+ return priv->nr_groups;
+}
+
+/* return the name of the group selected by the group selector */
+static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct exynos5440_pinctrl_priv_data *priv;
+
+ priv = pinctrl_dev_get_drvdata(pctldev);
+ return priv->pin_groups[selector].name;
+}
+
+/* return the pin numbers associated with the specified group */
+static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned selector, const unsigned **pins, unsigned *num_pins)
+{
+ struct exynos5440_pinctrl_priv_data *priv;
+
+ priv = pinctrl_dev_get_drvdata(pctldev);
+ *pins = priv->pin_groups[selector].pins;
+ *num_pins = priv->pin_groups[selector].num_pins;
+ return 0;
+}
+
+/* create pinctrl_map entries by parsing device tree nodes */
+static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np, struct pinctrl_map **maps,
+ unsigned *nmaps)
+{
+ struct device *dev = pctldev->dev;
+ struct pinctrl_map *map;
+ unsigned long *cfg = NULL;
+ char *gname, *fname;
+ int cfg_cnt = 0, map_cnt = 0, idx = 0;
+
+ /* count the number of config options specfied in the node */
+ for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
+ if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
+ cfg_cnt++;
+
+ /*
+ * Find out the number of map entries to create. All the config options
+ * can be accomadated into a single config map entry.
+ */
+ if (cfg_cnt)
+ map_cnt = 1;
+ if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
+ map_cnt++;
+ if (!map_cnt) {
+ dev_err(dev, "node %s does not have either config or function "
+ "configurations\n", np->name);
+ return -EINVAL;
+ }
+
+ /* Allocate memory for pin-map entries */
+ map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
+ if (!map) {
+ dev_err(dev, "could not alloc memory for pin-maps\n");
+ return -ENOMEM;
+ }
+ *nmaps = 0;
+
+ /*
+ * Allocate memory for pin group name. The pin group name is derived
+ * from the node name from which these map entries are be created.
+ */
+ gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL);
+ if (!gname) {
+ dev_err(dev, "failed to alloc memory for group name\n");
+ goto free_map;
+ }
+ sprintf(gname, "%s%s", np->name, GROUP_SUFFIX);
+
+ /*
+ * don't have config options? then skip over to creating function
+ * map entries.
+ */
+ if (!cfg_cnt)
+ goto skip_cfgs;
+
+ /* Allocate memory for config entries */
+ cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
+ if (!cfg) {
+ dev_err(dev, "failed to alloc memory for configs\n");
+ goto free_gname;
+ }
+
+ /* Prepare a list of config settings */
+ for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
+ u32 value;
+ if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
+ cfg[cfg_cnt++] =
+ PINCFG_PACK(pcfgs[idx].cfg_type, value);
+ }
+
+ /* create the config map entry */
+ map[*nmaps].data.configs.group_or_pin = gname;
+ map[*nmaps].data.configs.configs = cfg;
+ map[*nmaps].data.configs.num_configs = cfg_cnt;
+ map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+ *nmaps += 1;
+
+skip_cfgs:
+ /* create the function map entry */
+ if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
+ fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL);
+ if (!fname) {
+ dev_err(dev, "failed to alloc memory for func name\n");
+ goto free_cfg;
+ }
+ sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX);
+
+ map[*nmaps].data.mux.group = gname;
+ map[*nmaps].data.mux.function = fname;
+ map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
+ *nmaps += 1;
+ }
+
+ *maps = map;
+ return 0;
+
+free_cfg:
+ kfree(cfg);
+free_gname:
+ kfree(gname);
+free_map:
+ kfree(map);
+ return -ENOMEM;
+}
+
+/* free the memory allocated to hold the pin-map table */
+static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned num_maps)
+{
+ int idx;
+
+ for (idx = 0; idx < num_maps; idx++) {
+ if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
+ kfree(map[idx].data.mux.function);
+ if (!idx)
+ kfree(map[idx].data.mux.group);
+ } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
+ kfree(map[idx].data.configs.configs);
+ if (!idx)
+ kfree(map[idx].data.configs.group_or_pin);
+ }
+ };
+
+ kfree(map);
+}
+
+/* list of pinctrl callbacks for the pinctrl core */
+static struct pinctrl_ops exynos5440_pctrl_ops = {
+ .get_groups_count = exynos5440_get_group_count,
+ .get_group_name = exynos5440_get_group_name,
+ .get_group_pins = exynos5440_get_group_pins,
+ .dt_node_to_map = exynos5440_dt_node_to_map,
+ .dt_free_map = exynos5440_dt_free_map,
+};
+
+/* check if the selector is a valid pin function selector */
+static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
+{
+ struct exynos5440_pinctrl_priv_data *priv;
+
+ priv = pinctrl_dev_get_drvdata(pctldev);
+ return priv->nr_functions;
+}
+
+/* return the name of the pin function specified */
+static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct exynos5440_pinctrl_priv_data *priv;
+
+ priv = pinctrl_dev_get_drvdata(pctldev);
+ return priv->pmx_functions[selector].name;
+}
+
+/* return the groups associated for the specified function selector */
+static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
+ unsigned selector, const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct exynos5440_pinctrl_priv_data *priv;
+
+ priv = pinctrl_dev_get_drvdata(pctldev);
+ *groups = priv->pmx_functions[selector].groups;
+ *num_groups = priv->pmx_functions[selector].num_groups;
+ return 0;
+}
+
+/* enable or disable a pinmux function */
+static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group, bool enable)
+{
+ struct exynos5440_pinctrl_priv_data *priv;
+ void __iomem *base;
+ u32 function;
+ u32 data;
+
+ priv = pinctrl_dev_get_drvdata(pctldev);
+ base = priv->reg_base;
+ function = priv->pmx_functions[selector].function;
+
+ data = readl(base + GPIO_MUX);
+ if (enable)
+ data |= (1 << function);
+ else
+ data &= ~(1 << function);
+ writel(data, base + GPIO_MUX);
+}
+
+/* enable a specified pinmux by writing to registers */
+static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
+{
+ exynos5440_pinmux_setup(pctldev, selector, group, true);
+ return 0;
+}
+
+/* disable a specified pinmux by writing to registers */
+static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev,
+ unsigned selector, unsigned group)
+{
+ exynos5440_pinmux_setup(pctldev, selector, group, false);
+}
+
+/*
+ * The calls to gpio_direction_output() and gpio_direction_input()
+ * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
+ * function called from the gpiolib interface).
+ */
+static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned offset, bool input)
+{
+ return 0;
+}
+
+/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
+static struct pinmux_ops exynos5440_pinmux_ops = {
+ .get_functions_count = exynos5440_get_functions_count,
+ .get_function_name = exynos5440_pinmux_get_fname,
+ .get_function_groups = exynos5440_pinmux_get_groups,
+ .enable = exynos5440_pinmux_enable,
+ .disable = exynos5440_pinmux_disable,
+ .gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
+};
+
+/* set the pin config settings for a specified pin */
+static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long config)
+{
+ struct exynos5440_pinctrl_priv_data *priv;
+ void __iomem *base;
+ enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(config);
+ u32 cfg_value = PINCFG_UNPACK_VALUE(config);
+ u32 data;
+
+ priv = pinctrl_dev_get_drvdata(pctldev);
+ base = priv->reg_base;
+
+ switch (cfg_type) {
+ case PINCFG_TYPE_PUD:
+ /* first set pull enable/disable bit */
+ data = readl(base + GPIO_PE);
+ data &= ~(1 << pin);
+ if (cfg_value)
+ data |= (1 << pin);
+ writel(data, base + GPIO_PE);
+
+ /* then set pull up/down bit */
+ data = readl(base + GPIO_PS);
+ data &= ~(1 << pin);
+ if (cfg_value == 2)
+ data |= (1 << pin);
+ writel(data, base + GPIO_PS);
+ break;
+
+ case PINCFG_TYPE_DRV:
+ /* set the first bit of the drive strength */
+ data = readl(base + GPIO_DS0);
+ data &= ~(1 << pin);
+ data |= ((cfg_value & 1) << pin);
+ writel(data, base + GPIO_DS0);
+ cfg_value >>= 1;
+
+ /* set the second bit of the driver strength */
+ data = readl(base + GPIO_DS1);
+ data &= ~(1 << pin);
+ data |= ((cfg_value & 1) << pin);
+ writel(data, base + GPIO_DS1);
+ break;
+ case PINCFG_TYPE_SKEW_RATE:
+ data = readl(base + GPIO_SR);
+ data &= ~(1 << pin);
+ data |= ((cfg_value & 1) << pin);
+ writel(data, base + GPIO_SR);
+ break;
+ case PINCFG_TYPE_INPUT_TYPE:
+ data = readl(base + GPIO_TYPE);
+ data &= ~(1 << pin);
+ data |= ((cfg_value & 1) << pin);
+ writel(data, base + GPIO_TYPE);
+ break;
+ default:
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/* get the pin config settings for a specified pin */
+static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *config)
+{
+ struct exynos5440_pinctrl_priv_data *priv;
+ void __iomem *base;
+ enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
+ u32 data;
+
+ priv = pinctrl_dev_get_drvdata(pctldev);
+ base = priv->reg_base;
+
+ switch (cfg_type) {
+ case PINCFG_TYPE_PUD:
+ data = readl(base + GPIO_PE);
+ data = (data >> pin) & 1;
+ if (!data)
+ *config = 0;
+ else
+ *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
+ break;
+ case PINCFG_TYPE_DRV:
+ data = readl(base + GPIO_DS0);
+ data = (data >> pin) & 1;
+ *config = data;
+ data = readl(base + GPIO_DS1);
+ data = (data >> pin) & 1;
+ *config |= (data << 1);
+ break;
+ case PINCFG_TYPE_SKEW_RATE:
+ data = readl(base + GPIO_SR);
+ *config = (data >> pin) & 1;
+ break;
+ case PINCFG_TYPE_INPUT_TYPE:
+ data = readl(base + GPIO_TYPE);
+ *config = (data >> pin) & 1;
+ break;
+ default:
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/* set the pin config settings for a specified pin group */
+static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned group, unsigned long config)
+{
+ struct exynos5440_pinctrl_priv_data *priv;
+ const unsigned int *pins;
+ unsigned int cnt;
+
+ priv = pinctrl_dev_get_drvdata(pctldev);
+ pins = priv->pin_groups[group].pins;
+
+ for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
+ exynos5440_pinconf_set(pctldev, pins[cnt], config);
+
+ return 0;
+}
+
+/* get the pin config settings for a specified pin group */
+static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned int group, unsigned long *config)
+{
+ struct exynos5440_pinctrl_priv_data *priv;
+ const unsigned int *pins;
+
+ priv = pinctrl_dev_get_drvdata(pctldev);
+ pins = priv->pin_groups[group].pins;
+ exynos5440_pinconf_get(pctldev, pins[0], config);
+ return 0;
+}
+
+/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
+static struct pinconf_ops exynos5440_pinconf_ops = {
+ .pin_config_get = exynos5440_pinconf_get,
+ .pin_config_set = exynos5440_pinconf_set,
+ .pin_config_group_get = exynos5440_pinconf_group_get,
+ .pin_config_group_set = exynos5440_pinconf_group_set,
+};
+
+/* gpiolib gpio_set callback function */
+static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
+{
+ struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
+ void __iomem *base = priv->reg_base;
+ u32 data;
+
+ data = readl(base + GPIO_VAL);
+ data &= ~(1 << offset);
+ if (value)
+ data |= 1 << offset;
+ writel(data, base + GPIO_VAL);
+}
+
+/* gpiolib gpio_get callback function */
+static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
+{
+ struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
+ void __iomem *base = priv->reg_base;
+ u32 data;
+
+ data = readl(base + GPIO_IN);
+ data >>= offset;
+ data &= 1;
+ return data;
+}
+
+/* gpiolib gpio_direction_input callback function */
+static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
+{
+ struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
+ void __iomem *base = priv->reg_base;
+ u32 data;
+
+ /* first disable the data output enable on this pin */
+ data = readl(base + GPIO_OE);
+ data &= ~(1 << offset);
+ writel(data, base + GPIO_OE);
+
+ /* now enable input on this pin */
+ data = readl(base + GPIO_IE);
+ data |= 1 << offset;
+ writel(data, base + GPIO_IE);
+ return 0;
+}
+
+/* gpiolib gpio_direction_output callback function */
+static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
+ int value)
+{
+ struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
+ void __iomem *base = priv->reg_base;
+ u32 data;
+
+ exynos5440_gpio_set(gc, offset, value);
+
+ /* first disable the data input enable on this pin */
+ data = readl(base + GPIO_IE);
+ data &= ~(1 << offset);
+ writel(data, base + GPIO_IE);
+
+ /* now enable output on this pin */
+ data = readl(base + GPIO_OE);
+ data |= 1 << offset;
+ writel(data, base + GPIO_OE);
+ return 0;
+}
+
+/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
+static int __init exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
+ struct device_node *cfg_np, unsigned int **pin_list,
+ unsigned int *npins)
+{
+ struct device *dev = &pdev->dev;
+ struct property *prop;
+
+ prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
+ if (!prop)
+ return -ENOENT;
+
+ *npins = prop->length / sizeof(unsigned long);
+ if (!*npins) {
+ dev_err(dev, "invalid pin list in %s node", cfg_np->name);
+ return -EINVAL;
+ }
+
+ *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
+ if (!*pin_list) {
+ dev_err(dev, "failed to allocate memory for pin list\n");
+ return -ENOMEM;
+ }
+
+ return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
+ *pin_list, *npins);
+}
+
+/*
+ * Parse the information about all the available pin groups and pin functions
+ * from device node of the pin-controller.
+ */
+static int __init exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
+ struct exynos5440_pinctrl_priv_data *priv)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *dev_np = dev->of_node;
+ struct device_node *cfg_np;
+ struct exynos5440_pin_group *groups, *grp;
+ struct exynos5440_pmx_func *functions, *func;
+ unsigned *pin_list;
+ unsigned int npins, grp_cnt, func_idx = 0;
+ char *gname, *fname;
+ int ret;
+
+ grp_cnt = of_get_child_count(dev_np);
+ if (!grp_cnt)
+ return -EINVAL;
+
+ groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
+ if (!groups) {
+ dev_err(dev, "failed allocate memory for ping group list\n");
+ return -EINVAL;
+ }
+ grp = groups;
+
+ functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
+ if (!functions) {
+ dev_err(dev, "failed to allocate memory for function list\n");
+ return -EINVAL;
+ }
+ func = functions;
+
+ /*
+ * Iterate over all the child nodes of the pin controller node
+ * and create pin groups and pin function lists.
+ */
+ for_each_child_of_node(dev_np, cfg_np) {
+ u32 function;
+
+ ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
+ &pin_list, &npins);
+ if (ret)
+ return ret;
+
+ /* derive pin group name from the node name */
+ gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN,
+ GFP_KERNEL);
+ if (!gname) {
+ dev_err(dev, "failed to alloc memory for group name\n");
+ return -ENOMEM;
+ }
+ sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX);
+
+ grp->name = gname;
+ grp->pins = pin_list;
+ grp->num_pins = npins;
+ grp++;
+
+ ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
+ &function);
+ if (ret)
+ continue;
+
+ /* derive function name from the node name */
+ fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN,
+ GFP_KERNEL);
+ if (!fname) {
+ dev_err(dev, "failed to alloc memory for func name\n");
+ return -ENOMEM;
+ }
+ sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX);
+
+ func->name = fname;
+ func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
+ if (!func->groups) {
+ dev_err(dev, "failed to alloc memory for group list "
+ "in pin function");
+ return -ENOMEM;
+ }
+ func->groups[0] = gname;
+ func->num_groups = 1;
+ func->function = function;
+ func++;
+ func_idx++;
+ }
+
+ priv->pin_groups = groups;
+ priv->nr_groups = grp_cnt;
+ priv->pmx_functions = functions;
+ priv->nr_functions = func_idx;
+ return 0;
+}
+
+/* register the pinctrl interface with the pinctrl subsystem */
+static int __init exynos5440_pinctrl_register(struct platform_device *pdev,
+ struct exynos5440_pinctrl_priv_data *priv)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl_desc *ctrldesc;
+ struct pinctrl_dev *pctl_dev;
+ struct pinctrl_pin_desc *pindesc, *pdesc;
+ struct pinctrl_gpio_range grange;
+ char *pin_names;
+ int pin, ret;
+
+ ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
+ if (!ctrldesc) {
+ dev_err(dev, "could not allocate memory for pinctrl desc\n");
+ return -ENOMEM;
+ }
+
+ ctrldesc->name = "exynos5440-pinctrl";
+ ctrldesc->owner = THIS_MODULE;
+ ctrldesc->pctlops = &exynos5440_pctrl_ops;
+ ctrldesc->pmxops = &exynos5440_pinmux_ops;
+ ctrldesc->confops = &exynos5440_pinconf_ops;
+
+ pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
+ EXYNOS5440_MAX_PINS, GFP_KERNEL);
+ if (!pindesc) {
+ dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
+ return -ENOMEM;
+ }
+ ctrldesc->pins = pindesc;
+ ctrldesc->npins = EXYNOS5440_MAX_PINS;
+
+ /* dynamically populate the pin number and pin name for pindesc */
+ for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
+ pdesc->number = pin;
+
+ /*
+ * allocate space for storing the dynamically generated names for all
+ * the pins which belong to this pin-controller.
+ */
+ pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
+ ctrldesc->npins, GFP_KERNEL);
+ if (!pin_names) {
+ dev_err(&pdev->dev, "mem alloc for pin names failed\n");
+ return -ENOMEM;
+ }
+
+ /* for each pin, set the name of the pin */
+ for (pin = 0; pin < ctrldesc->npins; pin++) {
+ sprintf(pin_names, "gpio%02d", pin);
+ pdesc = pindesc + pin;
+ pdesc->name = pin_names;
+ pin_names += PIN_NAME_LENGTH;
+ }
+
+ ret = exynos5440_pinctrl_parse_dt(pdev, priv);
+ if (ret)
+ return ret;
+
+ pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv);
+ if (!pctl_dev) {
+ dev_err(&pdev->dev, "could not register pinctrl driver\n");
+ return -EINVAL;
+ }
+
+ grange.name = "exynos5440-pctrl-gpio-range";
+ grange.id = 0;
+ grange.base = 0;
+ grange.npins = EXYNOS5440_MAX_PINS;
+ grange.gc = priv->gc;
+ pinctrl_add_gpio_range(pctl_dev, &grange);
+ return 0;
+}
+
+/* register the gpiolib interface with the gpiolib subsystem */
+static int __init exynos5440_gpiolib_register(struct platform_device *pdev,
+ struct exynos5440_pinctrl_priv_data *priv)
+{
+ struct gpio_chip *gc;
+ int ret;
+
+ gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
+ if (!gc) {
+ dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
+ return -ENOMEM;
+ }
+
+ priv->gc = gc;
+ gc->base = 0;
+ gc->ngpio = EXYNOS5440_MAX_PINS;
+ gc->dev = &pdev->dev;
+ gc->set = exynos5440_gpio_set;
+ gc->get = exynos5440_gpio_get;
+ gc->direction_input = exynos5440_gpio_direction_input;
+ gc->direction_output = exynos5440_gpio_direction_output;
+ gc->label = "gpiolib-exynos5440";
+ gc->owner = THIS_MODULE;
+ ret = gpiochip_add(gc);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
+ "code: %d\n", gc->label, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/* unregister the gpiolib interface with the gpiolib subsystem */
+static int __init exynos5440_gpiolib_unregister(struct platform_device *pdev,
+ struct exynos5440_pinctrl_priv_data *priv)
+{
+ int ret = gpiochip_remove(priv->gc);
+ if (ret) {
+ dev_err(&pdev->dev, "gpio chip remove failed\n");
+ return ret;
+ }
+ return 0;
+}
+
+static int __devinit exynos5440_pinctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct exynos5440_pinctrl_priv_data *priv;
+ struct resource *res;
+ int ret;
+
+ if (!dev->of_node) {
+ dev_err(dev, "device tree node not found\n");
+ return -ENODEV;
+ }
+
+ priv = devm_kzalloc(dev, sizeof(priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(dev, "could not allocate memory for private data\n");
+ return -ENOMEM;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "cannot find IO resource\n");
+ return -ENOENT;
+ }
+
+ priv->reg_base = devm_request_and_ioremap(&pdev->dev, res);
+ if (!priv->reg_base) {
+ dev_err(dev, "ioremap failed\n");
+ return -ENODEV;
+ }
+
+ ret = exynos5440_gpiolib_register(pdev, priv);
+ if (ret)
+ return ret;
+
+ ret = exynos5440_pinctrl_register(pdev, priv);
+ if (ret) {
+ exynos5440_gpiolib_unregister(pdev, priv);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, priv);
+ dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
+ return 0;
+}
+
+static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
+ { .compatible = "samsung,exynos5440-pinctrl" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match);
+
+static struct platform_driver exynos5440_pinctrl_driver = {
+ .probe = exynos5440_pinctrl_probe,
+ .driver = {
+ .name = "exynos5440-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(exynos5440_pinctrl_dt_match),
+ },
+};
+
+static int __init exynos5440_pinctrl_drv_register(void)
+{
+ return platform_driver_register(&exynos5440_pinctrl_driver);
+}
+postcore_initcall(exynos5440_pinctrl_drv_register);
+
+static void __exit exynos5440_pinctrl_drv_unregister(void)
+{
+ platform_driver_unregister(&exynos5440_pinctrl_driver);
+}
+module_exit(exynos5440_pinctrl_drv_unregister);
+
+MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
+MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.7.4.4
^ permalink raw reply related
* [PATCH 7/7] ARM: dts: Add pin controller node for Samsung EXYNOS5440 SoC
From: Kukjin Kim @ 2012-10-26 17:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351274153-3120-1-git-send-email-kgene.kim@samsung.com>
From: Thomas Abraham <thomas.abraham@linaro.org>
Add a pin controller node for Samsung Exynos5440 (EXYNOS5440) SoC.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/boot/dts/exynos5440.dtsi | 17 +++++++++++++++++
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 380a89a..a7cda84 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -90,6 +90,23 @@
reg = <0xE0000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
+ #gpio-cells = <2>;
+
+ fan: fan {
+ samsung,exynos5440-pin-function = <1>;
+ };
+
+ hdd_led0: hdd_led0 {
+ samsung,exynos5440-pin-function = <2>;
+ };
+
+ hdd_led1: hdd_led1 {
+ samsung,exynos5440-pin-function = <3>;
+ };
+
+ uart1: uart1 {
+ samsung,exynos5440-pin-function = <4>;
+ };
};
i2c at F0000 {
--
1.7.4.4
^ permalink raw reply related
* [PATCH 2/5] drivers: usb: otg: make twl6030_usb as a comparator driver to omap_usb2
From: Benoit Cousson @ 2012-10-26 17:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1210261750430.7573@utopia.booyaka.com>
Hi Paul,
On 10/26/2012 07:54 PM, Paul Walmsley wrote:
> On Fri, 26 Oct 2012, Benoit Cousson wrote:
>
>> On 10/26/2012 05:16 PM, Roger Quadros wrote:
>>
>>> I still can't get musb to work on 3.7-rc2. Apparently it is still
>>> missing the patches from Benoit's for_3.7/dts_part2.
>>>
>>> Maybe I just need to wait for it to be merged?
>>
>> They are now in a for_3.8/dts. Unfortunately, one patch that was adding
>> ctrl_module address in the USB data was rejected and thus I'm not sure
>> it will work without that.
>
> For v3.7-rc timeframe, looks like it's waiting on an ack from you:
>
> http://www.spinics.net/lists/arm-kernel/msg201028.html
Oups, I missed that one. But I thought Roger was mentioning the DT patch
and not that one.
Anyway, I will answer to Tony. Thanks for the reminder Paul.
Regards,
Benoit
^ permalink raw reply
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