* [PATCH 11/11] ARM: shmobile: r8a7740: Enable PMU
From: Simon Horman @ 2012-11-01 0:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351730513-2952-1-git-send-email-horms@verge.net.au>
From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
This patch enables PMU for r8a7740.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
[horms at verge.net.au: corrected indentation]
Signed-off-by: Simon Horman <horms@verge.net.au>
---
arch/arm/configs/armadillo800eva_defconfig | 1 +
arch/arm/mach-shmobile/setup-r8a7740.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index f78d259..3d76407 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -7,6 +7,7 @@ CONFIG_LOG_BUF_SHIFT=16
# CONFIG_IPC_NS is not set
# CONFIG_PID_NS is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 9777e2d..6ac242c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -590,6 +590,21 @@ static struct platform_device i2c1_device = {
.num_resources = ARRAY_SIZE(i2c1_resources),
};
+static struct resource pmu_resources[] = {
+ [0] = {
+ .start = evt2irq(0x19a0),
+ .end = evt2irq(0x19a0),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device pmu_device = {
+ .name = "arm-pmu",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(pmu_resources),
+ .resource = pmu_resources,
+};
+
static struct platform_device *r8a7740_late_devices[] __initdata = {
&i2c0_device,
&i2c1_device,
@@ -597,6 +612,7 @@ static struct platform_device *r8a7740_late_devices[] __initdata = {
&dma1_device,
&dma2_device,
&usb_dma_device,
+ &pmu_device,
};
/*
--
1.7.10.4
^ permalink raw reply related
* [PATCH v3 3/9] pinctrl: single: support pinconf generic
From: Tony Lindgren @ 2012-11-01 0:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351724661-29050-4-git-send-email-haojian.zhuang@gmail.com>
> --- a/drivers/pinctrl/pinctrl-single.c
> +++ b/drivers/pinctrl/pinctrl-single.c
> @@ -20,6 +20,7 @@
> #include <linux/of_device.h>
> #include <linux/of_address.h>
>
> +#include <linux/pinctrl/pinconf-generic.h>
> #include <linux/pinctrl/pinctrl.h>
> #include <linux/pinctrl/pinmux.h>
>
> @@ -28,6 +29,9 @@
> #define DRIVER_NAME "pinctrl-single"
> #define PCS_MUX_PINS_NAME "pinctrl-single,pins"
> #define PCS_MUX_BITS_NAME "pinctrl-single,bits"
> +#define PCS_BIAS_NAME "pinctrl-single,bias"
> +#define PCS_POWER_SOURCE_NAME "pinctrl-single,power-source"
> +#define PCS_SCHMITT_NAME "pinctrl-single,input-schmitt"
> #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1)
> #define PCS_OFF_DISABLED ~0U
> #define PCS_MAX_GPIO_VALUES 3
Here too you can remove the new defines.
> static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
> struct device_node *np,
> struct pinctrl_map **map,
> + unsigned num_configs,
> const char **pgnames)
> {
...
Then I suggest you add a generic pinconf-generic property to
indicate the controller supports pinconf. At least for omaps,
only some register ranges support pinconf. And by adding
pinconf-generic, you can parse it once during the probe of
pinctrl-single.c, and set pcs->pinconf flag.
Then you can use here and avoid calling of_property_read_u32
for about 600 times unnecessarily for omap4:
if (pcs->pinconf) {
> + if (!num_configs)
> + return 0;
> + config = devm_kzalloc(pcs->dev, sizeof(*config) * num_configs,
> + GFP_KERNEL);
> + if (!config) {
> + res = -ENOMEM;
> + goto free_pingroup;
> + }
> + index = 0;
> +
> + if (!of_property_read_u32(np, PCS_SCHMITT_NAME, &value))
> + config[index++] =
> + pinconf_to_config_packed(PIN_CONFIG_INPUT_SCHMITT,
> + value & 0xffff);
> + if (!of_property_read_u32(np, PCS_BIAS_NAME, &value))
> + config[index++] =
> + pinconf_to_config_packed(PIN_CONFIG_BIAS_DISABLE,
> + value & 0xffff);
> + if (!of_property_read_u32(np, PCS_POWER_SOURCE_NAME, &value))
> + config[index++] =
> + pinconf_to_config_packed(PIN_CONFIG_POWER_SOURCE,
> + value & 0xffff);
}
> +static int pcs_dt_check_maps(struct device_node *np, unsigned *num_maps,
> + unsigned *num_configs)
> +{
> + unsigned size;
> +
> + *num_maps = 0;
> + *num_configs = 0;
> + if (of_get_property(np, PCS_MUX_PINS_NAME, &size)
> + || of_get_property(np, PCS_MUX_BITS_NAME, &size))
> + (*num_maps)++;
> + if (of_get_property(np, PCS_SCHMITT_NAME, &size))
> + (*num_configs)++;
> + if (of_get_property(np, PCS_BIAS_NAME, &size))
> + (*num_configs)++;
> + if (of_get_property(np, PCS_POWER_SOURCE_NAME, &size))
> + (*num_configs)++;
> + if (*num_configs)
> + (*num_maps)++;
> + if (!(*num_maps))
> + return -EINVAL;
> + return 0;
> +}
> +
> /**
> * pcs_dt_node_to_map() - allocates and parses pinctrl maps
> * @pctldev: pinctrl instance
> @@ -802,29 +1019,32 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
> {
> struct pcs_device *pcs;
> const char **pgnames;
> + unsigned num_configs;
> int ret;
>
> pcs = pinctrl_dev_get_drvdata(pctldev);
Here too:
if (pcs->pinconf) {
> - *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL);
> + ret = pcs_dt_check_maps(np_config, num_maps, &num_configs);
> + if (ret)
> + return ret;
> +
> + *map = devm_kzalloc(pcs->dev, sizeof(**map) * (*num_maps), GFP_KERNEL);
> if (!map)
> return -ENOMEM;
} else {
> - *num_maps = 0;
> -
}
Regards,
Tony
^ permalink raw reply
* [GIT PULL] Renesas ARM-based SoC defconfig for v3.8
From: Simon Horman @ 2012-11-01 0:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201210302141.27919.arnd@arndb.de>
On Tue, Oct 30, 2012 at 09:41:27PM +0000, Arnd Bergmann wrote:
> On Tuesday 30 October 2012, Simon Horman wrote:
> > While I am more than happy to help address the issues raised in this
> > thread, and others that arise. There do seem to be a number of issues
> > between where we are now and a more generic shmobile_defconfig. I would
> > like consideration given to allowing the exixting, working, well-maintained,
> > per-board defconfigs to be updated until these issues have been resolved.
>
> Yes, no problem. This seemed like a low-hanging fruit initially but has
> turned into something much bigger now.
>
> Instead of attacking all these at ones, we can leave them as something
> worthwhile doing later. I noticed that out of the 11 shmobile defconfigs,
> only three (marzen, kzm9d and kzm9g) actually have a nonzero MEMORY_START.
>
> Maybe it's possible to consolidate all or some of the others first, since
> they should still work with the same uImage at the expense of just making
> the early debugging a little harder, as we discussed earlier.
>
> For all I know, these three boards are also the ones seeing the most
> ongoing development, so you could start by using a shared defconfig
> for the oldest (ARM11 based) boards at first that are also less likely
> to impact new development starting from the defconfig.
Thanks, good observations. I will look into that.
My expectation is that marzen and kzm9g will continue to see
heavy development in the near future.
^ permalink raw reply
* [PATCH v3 9/9] pinctrl: single: dump pinmux register value
From: Tony Lindgren @ 2012-11-01 0:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351724661-29050-10-git-send-email-haojian.zhuang@gmail.com>
* Haojian Zhuang <haojian.zhuang@gmail.com> [121031 16:07]:
> Dump pinmux register value, not only function part in the pinmux
> register.
>
> Also fix the issue on caluclating pin offset. The last parameter
> should be pin number, not register offset.
You have a minor typo ^^^^^^^^^^^ should be calculating
instead.
Is there a bug that should be fixed for the -rc cycle
here? That's the impression I get from the description.
Or is it just a cosmetic fix to rename offset to pin?
Regards,
Tony
> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
> ---
> drivers/pinctrl/pinctrl-single.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
> index 3b97b65..72017e7 100644
> --- a/drivers/pinctrl/pinctrl-single.c
> +++ b/drivers/pinctrl/pinctrl-single.c
> @@ -283,15 +283,15 @@ static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
>
> static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
> struct seq_file *s,
> - unsigned offset)
> + unsigned pin)
> {
> struct pcs_device *pcs;
> - unsigned val;
> + unsigned val, mux_bytes;
>
> pcs = pinctrl_dev_get_drvdata(pctldev);
>
> - val = pcs->read(pcs->base + offset);
> - val &= pcs->fmask;
> + mux_bytes = pcs->width / BITS_PER_BYTE;
> + val = pcs->read(pcs->base + pin * mux_bytes);
>
> seq_printf(s, "%08x %s " , val, DRIVER_NAME);
> }
> --
> 1.7.10.4
>
^ permalink raw reply
* [RFC 1/7] capebus: Core capebus support
From: Russ Dill @ 2012-11-01 0:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <EBB972CD-D9D9-4704-AABF-2DFCED584297@antoniou-consulting.com>
On Wed, Oct 31, 2012 at 3:07 PM, Pantelis Antoniou
<panto@antoniou-consulting.com> wrote:
>
> On Oct 31, 2012, at 11:55 PM, Russ Dill wrote:
>
>> On Wed, Oct 31, 2012 at 9:52 AM, Pantelis Antoniou
>> <panto@antoniou-consulting.com> wrote:
>>> Introducing capebus; a bus that allows small boards (capes) to connect
>>> to a complex SoC using simple expansion connectors.
>>>
>
> [snip]
>>> + if (drv) {
>>> + /* call the removed bus method (if added prev.) */
>>> + if (cape_dev->added) {
>>> + BUG_ON(cape_dev->bus == NULL);
>>> + BUG_ON(cape_dev->bus->ops == NULL);
>>> + if (cape_dev->bus->ops->dev_removed)
>>> + cape_dev->bus->ops->dev_removed(cape_dev);
>>> + cape_dev->added = 0;
>>> + }
>>
>> Is there any case where added will not track drv?
>
>
> Yes, there is a corner case here.
>
> There is the case where while the device is created there is no matching
> driver yet. Either that's the case of a not supported cape, or the
> cape driver hasn't been loaded yet.
>
> We do need the device to be created, so that the user can browse in the
> sysfs it's eeprom attributes.
>
> There's some further complications with runtime cape overrides, but
> that's the gist of it.
I'm trying to figure out how that would come about, here is where
added is set to 1:
+ /* all is fine... */
+ cape_dev->driver = drv;
+ cape_dev->added = 1;
This is after calling drv->probe, so drv is not null.
There is a brief time here where added is 0, but driver is not.
+ if (drv) {
+ /* call the removed bus method (if added prev.) */
+ if (cape_dev->added) {
+ BUG_ON(cape_dev->bus == NULL);
+ BUG_ON(cape_dev->bus->ops == NULL);
+ if (cape_dev->bus->ops->dev_removed)
+ cape_dev->bus->ops->dev_removed(cape_dev);
+ cape_dev->added = 0;
+ }
+ if (drv->remove) {
+ pm_runtime_get_sync(dev);
+ drv->remove(cape_dev);
+ pm_runtime_put_noidle(dev);
+ }
+ cape_dev->driver = NULL;
Is one of the remove or resume functions check added in this case?
^ permalink raw reply
* [GIT PULL v2] Renesas ARM-based SoC defconfig for v3.8
From: Simon Horman @ 2012-11-01 1:02 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Arnd,
please consider the following defconfig enhancements for 3.8.
I will work on the suggestions by Arnd to reduce the number
of defconfigs for shmobile - in essence moving towards one or
two generic configs rather than per-board configs. However,
this seems to be somewhat non-trivial and in the mean time
I would like to keep updating the existing defcoings.
----------------------------------------------------------------
The following changes since commit ddffeb8c4d0331609ef2581d84de4d763607bd37:
Linux 3.7-rc1 (2012-10-14 14:41:04 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git defconfig
for you to fetch changes up to 67e13cbb807c6b95706e4ec0ca2c068f14f25588:
ARM: shmobile: leave CONFIG_INOTIFY_USER enabled by default (2012-11-01 08:51:34 +0800)
----------------------------------------------------------------
Guennadi Liakhovetski (1):
ARM: shmobile: leave CONFIG_INOTIFY_USER enabled by default
Kuninori Morimoto (2):
ARM: shmobile: mackerel: defconfig update
ARM: shmobile: armadillo800eva: enable L2X0 cache on defconfig
arch/arm/configs/ap4evb_defconfig | 1 -
arch/arm/configs/armadillo800eva_defconfig | 2 +-
arch/arm/configs/kota2_defconfig | 1 -
arch/arm/configs/kzm9g_defconfig | 1 -
arch/arm/configs/mackerel_defconfig | 19 ++++++++++++++++---
5 files changed, 17 insertions(+), 7 deletions(-)
^ permalink raw reply
* [PATCH 1/3] ARM: shmobile: mackerel: defconfig update
From: Simon Horman @ 2012-11-01 1:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351731731-8435-1-git-send-email-horms@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch enables following devices by default
- I2C
- HDMI
- USB (host/gadget)
- ALSA (FSI)
- DMAEngine
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
arch/arm/configs/mackerel_defconfig | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index 306a2e2..7b79a0b 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -70,17 +70,31 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=8
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_SH_MOBILE=y
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
CONFIG_FB=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_FB_SH_MOBILE_HDMI=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SOC_SH4_FSI=y
+CONFIG_USB=y
+CONFIG_USB_RENESAS_USBHS_HCD=y
+CONFIG_USB_RENESAS_USBHS=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_RENESAS_USBHS_UDC=y
+CONFIG_DMADEVICES=y
+CONFIG_SH_DMAE=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
--
1.7.10.4
^ permalink raw reply related
* [PATCH 2/3] ARM: shmobile: armadillo800eva: enable L2X0 cache on defconfig
From: Simon Horman @ 2012-11-01 1:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351731731-8435-1-git-send-email-horms@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
arch/arm/configs/armadillo800eva_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index f78d259..a18593d 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -20,7 +20,7 @@ CONFIG_MACH_ARMADILLO800EVA=y
# CONFIG_SH_TIMER_TMU is not set
CONFIG_ARM_THUMB=y
CONFIG_CPU_BPREDICT_DISABLE=y
-# CONFIG_CACHE_L2X0 is not set
+CONFIG_CACHE_L2X0=y
CONFIG_ARM_ERRATA_430973=y
CONFIG_ARM_ERRATA_458693=y
CONFIG_ARM_ERRATA_460075=y
--
1.7.10.4
^ permalink raw reply related
* [PATCH 3/3] ARM: shmobile: leave CONFIG_INOTIFY_USER enabled by default
From: Simon Horman @ 2012-11-01 1:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351731731-8435-1-git-send-email-horms@verge.net.au>
From: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
CONFIG_INOTIFY_USER is enabled by default in its Kconfig. Disabling it
breaks udevd. Fix shmobile defconfig files to not specify this option
explicitly.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
arch/arm/configs/ap4evb_defconfig | 1 -
arch/arm/configs/kota2_defconfig | 1 -
arch/arm/configs/kzm9g_defconfig | 1 -
arch/arm/configs/mackerel_defconfig | 1 -
4 files changed, 4 deletions(-)
diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig
index 2eef85e..66894f7 100644
--- a/arch/arm/configs/ap4evb_defconfig
+++ b/arch/arm/configs/ap4evb_defconfig
@@ -46,7 +46,6 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/kota2_defconfig b/arch/arm/configs/kota2_defconfig
index b7735d6..fa83db1 100644
--- a/arch/arm/configs/kota2_defconfig
+++ b/arch/arm/configs/kota2_defconfig
@@ -112,7 +112,6 @@ CONFIG_LEDS_GPIO=y
CONFIG_LEDS_RENESAS_TPU=y
CONFIG_LEDS_TRIGGERS=y
# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index c88b578..b377a6f 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -120,7 +120,6 @@ CONFIG_SH_DMAE=y
CONFIG_ASYNC_TX_DMA=y
CONFIG_STAGING=y
# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY_USER=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index 7b79a0b..2098ce1 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -105,7 +105,6 @@ CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
--
1.7.10.4
^ permalink raw reply related
* [PATCH] ARM: plat-versatile: move FPGA irq driver to drivers/irqchip
From: Rob Herring @ 2012-11-01 1:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351719113-30880-1-git-send-email-linus.walleij@linaro.org>
On 10/31/2012 04:31 PM, Linus Walleij wrote:
> This moves the Versatile FPGA interrupt controller driver, used in
> the Integrator/AP, Integrator/CP and some Versatile boards, out
> of arch/arm/plat-versatile and down to drivers/irqchip where we
> have consensus that such drivers belong. The header file is
> consequently moved to <linux/platform_data/irq-versatile-fpga.h>.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm/Kconfig | 4 +-
> arch/arm/mach-integrator/integrator_ap.c | 3 +-
> arch/arm/mach-integrator/integrator_cp.c | 2 +-
> arch/arm/mach-versatile/core.c | 2 +-
> arch/arm/plat-versatile/Kconfig | 9 -
> arch/arm/plat-versatile/Makefile | 1 -
> drivers/irqchip/Kconfig | 9 +-
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-arm-fpga.c | 204 +++++++++++++++++++++
> .../irqchip/irq-versatile-fpga.c | 4 +-
> .../linux/platform_data/irq-versatile-fpga.h | 0
> 11 files changed, 220 insertions(+), 19 deletions(-)
> create mode 100644 drivers/irqchip/irq-arm-fpga.c
> rename arch/arm/plat-versatile/fpga-irq.c => drivers/irqchip/irq-versatile-fpga.c (97%)
> rename arch/arm/plat-versatile/include/plat/fpga-irq.h => include/linux/platform_data/irq-versatile-fpga.h (100%)
I think include/linux/irqchip/ is the right place. Ideally we would not
need the header at all. You can remove some of the function declarations
if you base this on Thomas Petazzoni's series to have a common init
function for DT and also move the fpga_handle_irq init into the
fpga_irq_init function.
Rob
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 73067ef..2205e3e 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -284,8 +284,8 @@ config ARCH_INTEGRATOR
> select MULTI_IRQ_HANDLER
> select NEED_MACH_MEMORY_H
> select PLAT_VERSATILE
> - select PLAT_VERSATILE_FPGA_IRQ
> select SPARSE_IRQ
> + select VERSATILE_FPGA_IRQ
> help
> Support for ARM's Integrator platform.
>
> @@ -318,7 +318,7 @@ config ARCH_VERSATILE
> select PLAT_VERSATILE
> select PLAT_VERSATILE_CLCD
> select PLAT_VERSATILE_CLOCK
> - select PLAT_VERSATILE_FPGA_IRQ
> + select VERSATILE_FPGA_IRQ
> help
> This enables support for ARM Ltd Versatile board.
>
> diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
> index 4f13bc5..caa279f 100644
> --- a/arch/arm/mach-integrator/integrator_ap.c
> +++ b/arch/arm/mach-integrator/integrator_ap.c
> @@ -34,6 +34,7 @@
> #include <linux/mtd/physmap.h>
> #include <linux/clk.h>
> #include <linux/platform_data/clk-integrator.h>
> +#include <linux/platform_data/irq-versatile-fpga.h>
> #include <linux/of_irq.h>
> #include <linux/of_address.h>
> #include <linux/of_platform.h>
> @@ -56,8 +57,6 @@
> #include <asm/mach/pci.h>
> #include <asm/mach/time.h>
>
> -#include <plat/fpga-irq.h>
> -
> #include "common.h"
>
> /*
> diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
> index 4423bc8..b50fdc7 100644
> --- a/arch/arm/mach-integrator/integrator_cp.c
> +++ b/arch/arm/mach-integrator/integrator_cp.c
> @@ -23,6 +23,7 @@
> #include <linux/gfp.h>
> #include <linux/mtd/physmap.h>
> #include <linux/platform_data/clk-integrator.h>
> +#include <linux/platform_data/irq-versatile-fpga.h>
> #include <linux/of_irq.h>
> #include <linux/of_address.h>
> #include <linux/of_platform.h>
> @@ -46,7 +47,6 @@
> #include <asm/hardware/timer-sp.h>
>
> #include <plat/clcd.h>
> -#include <plat/fpga-irq.h>
> #include <plat/sched_clock.h>
>
> #include "common.h"
> diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
> index 5b5c1ee..46bfb8c 100644
> --- a/arch/arm/mach-versatile/core.c
> +++ b/arch/arm/mach-versatile/core.c
> @@ -35,6 +35,7 @@
> #include <linux/gfp.h>
> #include <linux/clkdev.h>
> #include <linux/mtd/physmap.h>
> +#include <linux/platform_data/irq-versatile-fpga.h>
>
> #include <asm/irq.h>
> #include <asm/hardware/arm_timer.h>
> @@ -51,7 +52,6 @@
> #include <asm/hardware/timer-sp.h>
>
> #include <plat/clcd.h>
> -#include <plat/fpga-irq.h>
> #include <plat/sched_clock.h>
>
> #include "core.h"
> diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
> index 2a4ae8a..619f0fa 100644
> --- a/arch/arm/plat-versatile/Kconfig
> +++ b/arch/arm/plat-versatile/Kconfig
> @@ -6,15 +6,6 @@ config PLAT_VERSATILE_CLOCK
> config PLAT_VERSATILE_CLCD
> bool
>
> -config PLAT_VERSATILE_FPGA_IRQ
> - bool
> - select IRQ_DOMAIN
> -
> -config PLAT_VERSATILE_FPGA_IRQ_NR
> - int
> - default 4
> - depends on PLAT_VERSATILE_FPGA_IRQ
> -
> config PLAT_VERSATILE_LEDS
> def_bool y if NEW_LEDS
> depends on ARCH_REALVIEW || ARCH_VERSATILE
> diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
> index 74cfd94..f88d448 100644
> --- a/arch/arm/plat-versatile/Makefile
> +++ b/arch/arm/plat-versatile/Makefile
> @@ -2,7 +2,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
>
> obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
> obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
> -obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
> obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o
> obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o
> obj-$(CONFIG_SMP) += headsmp.o platsmp.o
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 1bb8bf6..62ca575 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -1 +1,8 @@
> -# empty
> +config VERSATILE_FPGA_IRQ
> + bool
> + select IRQ_DOMAIN
> +
> +config VERSATILE_FPGA_IRQ_NR
> + int
> + default 4
> + depends on VERSATILE_FPGA_IRQ
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 054321d..e2e6eb5 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -1 +1,2 @@
> obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
> +obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
> diff --git a/drivers/irqchip/irq-arm-fpga.c b/drivers/irqchip/irq-arm-fpga.c
> new file mode 100644
> index 0000000..92fb9d6
> --- /dev/null
> +++ b/drivers/irqchip/irq-arm-fpga.c
> @@ -0,0 +1,204 @@
> +/*
> + * Support for Versatile FPGA-based IRQ controllers
> + */
> +#include <linux/bitops.h>
> +#include <linux/irq.h>
> +#include <linux/io.h>
> +#include <linux/irqdomain.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_data/irq-versatile-fpga.h>
> +
> +#include <asm/exception.h>
> +#include <asm/mach/irq.h>
> +
> +#define IRQ_STATUS 0x00
> +#define IRQ_RAW_STATUS 0x04
> +#define IRQ_ENABLE_SET 0x08
> +#define IRQ_ENABLE_CLEAR 0x0c
> +#define INT_SOFT_SET 0x10
> +#define INT_SOFT_CLEAR 0x14
> +#define FIQ_STATUS 0x20
> +#define FIQ_RAW_STATUS 0x24
> +#define FIQ_ENABLE 0x28
> +#define FIQ_ENABLE_SET 0x28
> +#define FIQ_ENABLE_CLEAR 0x2C
> +
> +/**
> + * struct fpga_irq_data - irq data container for the FPGA IRQ controller
> + * @base: memory offset in virtual memory
> + * @chip: chip container for this instance
> + * @domain: IRQ domain for this instance
> + * @valid: mask for valid IRQs on this controller
> + * @used_irqs: number of active IRQs on this controller
> + */
> +struct fpga_irq_data {
> + void __iomem *base;
> + struct irq_chip chip;
> + u32 valid;
> + struct irq_domain *domain;
> + u8 used_irqs;
> +};
> +
> +/* we cannot allocate memory when the controllers are initially registered */
> +static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
> +static int fpga_irq_id;
> +
> +static void fpga_irq_mask(struct irq_data *d)
> +{
> + struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
> + u32 mask = 1 << d->hwirq;
> +
> + writel(mask, f->base + IRQ_ENABLE_CLEAR);
> +}
> +
> +static void fpga_irq_unmask(struct irq_data *d)
> +{
> + struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
> + u32 mask = 1 << d->hwirq;
> +
> + writel(mask, f->base + IRQ_ENABLE_SET);
> +}
> +
> +static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
> +{
> + struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
> + u32 status = readl(f->base + IRQ_STATUS);
> +
> + if (status == 0) {
> + do_bad_IRQ(irq, desc);
> + return;
> + }
> +
> + do {
> + irq = ffs(status) - 1;
> + status &= ~(1 << irq);
> + generic_handle_irq(irq_find_mapping(f->domain, irq));
> + } while (status);
> +}
> +
> +/*
> + * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero
> + * if we've handled at least one interrupt. This does a single read of the
> + * status register and handles all interrupts in order from LSB first.
> + */
> +static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
> +{
> + int handled = 0;
> + int irq;
> + u32 status;
> +
> + while ((status = readl(f->base + IRQ_STATUS))) {
> + irq = ffs(status) - 1;
> + handle_IRQ(irq_find_mapping(f->domain, irq), regs);
> + handled = 1;
> + }
> +
> + return handled;
> +}
> +
> +/*
> + * Keep iterating over all registered FPGA IRQ controllers until there are
> + * no pending interrupts.
> + */
> +asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
> +{
> + int i, handled;
> +
> + do {
> + for (i = 0, handled = 0; i < fpga_irq_id; ++i)
> + handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
> + } while (handled);
> +}
> +
> +static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
> + irq_hw_number_t hwirq)
> +{
> + struct fpga_irq_data *f = d->host_data;
> +
> + /* Skip invalid IRQs, only register handlers for the real ones */
> + if (!(f->valid & BIT(hwirq)))
> + return -ENOTSUPP;
> + irq_set_chip_data(irq, f);
> + irq_set_chip_and_handler(irq, &f->chip,
> + handle_level_irq);
> + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
> + return 0;
> +}
> +
> +static struct irq_domain_ops fpga_irqdomain_ops = {
> + .map = fpga_irqdomain_map,
> + .xlate = irq_domain_xlate_onetwocell,
> +};
> +
> +void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
> + int parent_irq, u32 valid, struct device_node *node)
> +{
> + struct fpga_irq_data *f;
> + int i;
> +
> + if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
> + pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__);
> + return;
> + }
> + f = &fpga_irq_devices[fpga_irq_id];
> + f->base = base;
> + f->chip.name = name;
> + f->chip.irq_ack = fpga_irq_mask;
> + f->chip.irq_mask = fpga_irq_mask;
> + f->chip.irq_unmask = fpga_irq_unmask;
> + f->valid = valid;
> +
> + if (parent_irq != -1) {
> + irq_set_handler_data(parent_irq, f);
> + irq_set_chained_handler(parent_irq, fpga_irq_handle);
> + }
> +
> + /* This will also allocate irq descriptors */
> + f->domain = irq_domain_add_simple(node, fls(valid), irq_start,
> + &fpga_irqdomain_ops, f);
> +
> + /* This will allocate all valid descriptors in the linear case */
> + for (i = 0; i < fls(valid); i++)
> + if (valid & BIT(i)) {
> + if (!irq_start)
> + irq_create_mapping(f->domain, i);
> + f->used_irqs++;
> + }
> +
> + pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
> + fpga_irq_id, name, base, f->used_irqs);
> +
> + fpga_irq_id++;
> +}
> +
> +#ifdef CONFIG_OF
> +int __init fpga_irq_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + struct fpga_irq_data *f;
> + void __iomem *base;
> + u32 clear_mask;
> + u32 valid_mask;
> +
> + if (WARN_ON(!node))
> + return -ENODEV;
> +
> + base = of_iomap(node, 0);
> + WARN(!base, "unable to map fpga irq registers\n");
> +
> + if (of_property_read_u32(node, "clear-mask", &clear_mask))
> + clear_mask = 0;
> +
> + if (of_property_read_u32(node, "valid-mask", &valid_mask))
> + valid_mask = 0;
> +
> + fpga_irq_init(base, node->name, 0, -1, valid_mask, node);
> +
> + writel(clear_mask, base + IRQ_ENABLE_CLEAR);
> + writel(clear_mask, base + FIQ_ENABLE_CLEAR);
> +
> + return 0;
> +}
> +#endif
> diff --git a/arch/arm/plat-versatile/fpga-irq.c b/drivers/irqchip/irq-versatile-fpga.c
> similarity index 97%
> rename from arch/arm/plat-versatile/fpga-irq.c
> rename to drivers/irqchip/irq-versatile-fpga.c
> index dfe317c..b7aab6e 100644
> --- a/arch/arm/plat-versatile/fpga-irq.c
> +++ b/drivers/irqchip/irq-versatile-fpga.c
> @@ -8,10 +8,10 @@
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> +#include <linux/platform_data/irq-versatile-fpga.h>
>
> #include <asm/exception.h>
> #include <asm/mach/irq.h>
> -#include <plat/fpga-irq.h>
>
> #define IRQ_STATUS 0x00
> #define IRQ_RAW_STATUS 0x04
> @@ -42,7 +42,7 @@ struct fpga_irq_data {
> };
>
> /* we cannot allocate memory when the controllers are initially registered */
> -static struct fpga_irq_data fpga_irq_devices[CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR];
> +static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
> static int fpga_irq_id;
>
> static void fpga_irq_mask(struct irq_data *d)
> diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/include/linux/platform_data/irq-versatile-fpga.h
> similarity index 100%
> rename from arch/arm/plat-versatile/include/plat/fpga-irq.h
> rename to include/linux/platform_data/irq-versatile-fpga.h
>
^ permalink raw reply
* [PATCH] ARM: shmobile: leave CONFIG_INOTIFY_USER enabled by default
From: Simon Horman @ 2012-11-01 1:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <Pine.LNX.4.64.1210302358590.29432@axis700.grange>
On Wed, Oct 31, 2012 at 12:03:45AM +0100, Guennadi Liakhovetski wrote:
> CONFIG_INOTIFY_USER is enabled by default in its Kconfig. Disabling it
> breaks udevd. Fix shmobile defconfig files to not specify this option
> explicitly.
Thanks, applied to the defcofigs branch.
I have sent a pull request for the defcofigs branch to the arm-soc people.
I have also rebased the next branch to incorporate this change.
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git
^ permalink raw reply
* [PATCH] ARM: Fix the "WFI" instruction opcode definition.
From: Yangfei (Felix) @ 2012-11-01 1:24 UTC (permalink / raw)
To: linux-arm-kernel
The current "WFI" opcode definiton causes CPU hot-plug feature fails to work
if the kernel is built with CONFIG_THUMB2_KERNEL/CONFIG_CPU_ENDIAN_BE8 being
defined. An invalid instruction exception will be generated.
Signed-off-by: yangfei.kernel at gmail.com
---
arch/arm/mach-exynos/hotplug.c | 8 +++++++-
arch/arm/mach-realview/hotplug.c | 8 +++++++-
arch/arm/mach-shmobile/hotplug.c | 8 +++++++-
3 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index f4d7dd2..823a0e4 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -18,11 +18,17 @@
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/smp_plat.h>
+#include <asm/opcodes.h>
#include <mach/regs-pmu.h>
#include "common.h"
+/*
+ * Define opcode of the WFI instruction.
+ */
+#define __WFI __inst_arm_thumb16(0xe320f003, 0xbf30)
+
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
@@ -72,7 +78,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
/*
* here's the WFI
*/
- asm(".word 0xe320f003\n"
+ asm(__WFI
:
:
: "memory", "cc");
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index 53818e5..5271a1a 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -15,6 +15,12 @@
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/smp_plat.h>
+#include <asm/opcodes.h>
+
+/*
+ * Define opcode of the WFI instruction.
+ */
+#define __WFI __inst_arm_thumb16(0xe320f003, 0xbf30)
static inline void cpu_enter_lowpower(void)
{
@@ -64,7 +70,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
/*
* here's the WFI
*/
- asm(".word 0xe320f003\n"
+ asm(__WFI
:
:
: "memory", "cc");
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
index b09a0bd..0d7b7d1 100644
--- a/arch/arm/mach-shmobile/hotplug.c
+++ b/arch/arm/mach-shmobile/hotplug.c
@@ -20,6 +20,12 @@
#include <mach/emev2.h>
#include <asm/cacheflush.h>
#include <asm/mach-types.h>
+#include <asm/opcodes.h>
+
+/*
+ * Define opcode of the WFI instruction.
+ */
++#define __WFI __inst_arm_thumb16(0xe320f003, 0xbf30)
static cpumask_t dead_cpus;
@@ -39,7 +45,7 @@ void shmobile_cpu_die(unsigned int cpu)
/*
* here's the WFI
*/
- asm(".word 0xe320f003\n"
+ asm(__WFI
:
:
: "memory", "cc");
--
^ permalink raw reply related
* [PATCH] ARM: mxs: Add support for the Armadeus Systems APF28Dev docking board
From: Shawn Guo @ 2012-11-01 1:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351705166-62669-1-git-send-email-gwenhael.goavec-merou@armadeus.com>
On Wed, Oct 31, 2012 at 06:39:26PM +0100, Gwenhael Goavec-Merou wrote:
> The APF28Dev is a docking board for an APF28 SOM
>
> Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
> Signed-off-by: Julien Boibessot <julien.boibessot@armadeus.com>
Applied, thanks.
^ permalink raw reply
* [PATCH] ARM: Fix the "WFI" instruction opcode definition.
From: Rob Herring @ 2012-11-01 1:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DA41BE1DDCA941489001C7FBD7A8820E3CB5512E@szxeml549-mbx.china.huawei.com>
On 10/31/2012 08:24 PM, Yangfei (Felix) wrote:
> The current "WFI" opcode definiton causes CPU hot-plug feature fails to work
> if the kernel is built with CONFIG_THUMB2_KERNEL/CONFIG_CPU_ENDIAN_BE8 being
> defined. An invalid instruction exception will be generated.
>
> Signed-off-by: yangfei.kernel at gmail.com
> ---
> arch/arm/mach-exynos/hotplug.c | 8 +++++++-
> arch/arm/mach-realview/hotplug.c | 8 +++++++-
> arch/arm/mach-shmobile/hotplug.c | 8 +++++++-
> 3 files changed, 21 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
> index f4d7dd2..823a0e4 100644
> --- a/arch/arm/mach-exynos/hotplug.c
> +++ b/arch/arm/mach-exynos/hotplug.c
> @@ -18,11 +18,17 @@
> #include <asm/cacheflush.h>
> #include <asm/cp15.h>
> #include <asm/smp_plat.h>
> +#include <asm/opcodes.h>
>
> #include <mach/regs-pmu.h>
>
> #include "common.h"
>
> +/*
> + * Define opcode of the WFI instruction.
> + */
> +#define __WFI __inst_arm_thumb16(0xe320f003, 0xbf30)
> +
> static inline void cpu_enter_lowpower(void)
> {
> unsigned int v;
> @@ -72,7 +78,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
> /*
> * here's the WFI
> */
> - asm(".word 0xe320f003\n"
> + asm(__WFI
Wouldn't using the actual wfi instruction fix this. There is a wfi() macro.
Or just call cpu_do_idle() which will do any other things needed before
wfi like a dsb instruction.
Rob
> :
> :
> : "memory", "cc");
> diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
> index 53818e5..5271a1a 100644
> --- a/arch/arm/mach-realview/hotplug.c
> +++ b/arch/arm/mach-realview/hotplug.c
> @@ -15,6 +15,12 @@
> #include <asm/cacheflush.h>
> #include <asm/cp15.h>
> #include <asm/smp_plat.h>
> +#include <asm/opcodes.h>
> +
> +/*
> + * Define opcode of the WFI instruction.
> + */
> +#define __WFI __inst_arm_thumb16(0xe320f003, 0xbf30)
>
> static inline void cpu_enter_lowpower(void)
> {
> @@ -64,7 +70,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
> /*
> * here's the WFI
> */
> - asm(".word 0xe320f003\n"
> + asm(__WFI
> :
> :
> : "memory", "cc");
> diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
> index b09a0bd..0d7b7d1 100644
> --- a/arch/arm/mach-shmobile/hotplug.c
> +++ b/arch/arm/mach-shmobile/hotplug.c
> @@ -20,6 +20,12 @@
> #include <mach/emev2.h>
> #include <asm/cacheflush.h>
> #include <asm/mach-types.h>
> +#include <asm/opcodes.h>
> +
> +/*
> + * Define opcode of the WFI instruction.
> + */
> ++#define __WFI __inst_arm_thumb16(0xe320f003, 0xbf30)
>
> static cpumask_t dead_cpus;
>
> @@ -39,7 +45,7 @@ void shmobile_cpu_die(unsigned int cpu)
> /*
> * here's the WFI
> */
> - asm(".word 0xe320f003\n"
> + asm(__WFI
> :
> :
> : "memory", "cc");
> --
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply
* [PATCH V4 3/7] ARM: tegra30: cpuidle: add powered-down state for secondary CPUs
From: Joseph Lo @ 2012-11-01 1:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMbhsRRT60oyecsZqjf196Y=Cog209TwfMCPJ9nyLG+fwu7mqg@mail.gmail.com>
On Thu, 2012-11-01 at 05:19 +0800, Colin Cross wrote:
> On Wed, Oct 31, 2012 at 2:41 AM, Joseph Lo <josephl@nvidia.com> wrote:
> > This supports power-gated idle on secondary CPUs for Tegra30. The
> > secondary CPUs can go into powered-down state independently. When
> > CPU goes into this state, it saves it's contexts and puts itself
> > to flow controlled WFI state. After that, it will been power gated.
> >
> > Be aware of that, you may see the legacy power state "LP2" in the
> > code which is exactly the same meaning of "CPU power down".
>
> On Tegra20, LP2 included powering off the GIC. Is that still the case
> for Tegra30 individual secondary cpu power gating? If so, how do IPIs
> to an idle cpu wake it up?
Hi Colin,
Thanks for your review.
For Tegra30, the LP2 of secondary CPU didn't power gate GIC. Only when 4
cores in LP2, the power of cpu cluster will be shut off that include
GIC. For the LP2 of individual secondary CPU, it can be woke up by IPI.
Thanks,
Joseph
^ permalink raw reply
* [PATCH] arm-dt: Enable DT proc updates.
From: Rob Herring @ 2012-11-01 2:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351699069-4661-1-git-send-email-panto@antoniou-consulting.com>
On 10/31/2012 10:57 AM, Pantelis Antoniou wrote:
> This simple patch enables dynamic changes of the DT tree on runtime
> to be visible to the device-tree proc interface.
>
> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
> ---
> arch/arm/include/asm/prom.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h
> index aeae9c6..6d65ba2 100644
> --- a/arch/arm/include/asm/prom.h
> +++ b/arch/arm/include/asm/prom.h
> @@ -11,6 +11,8 @@
> #ifndef __ASMARM_PROM_H
> #define __ASMARM_PROM_H
>
> +#define HAVE_ARCH_DEVTREE_FIXUPS
> +
> #ifdef CONFIG_OF
>
> extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys);
>
^ permalink raw reply
* OMAP baseline test results for v3.7-rc1
From: Paul Walmsley @ 2012-11-01 2:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAORVsuUWD3gHh1NcMLeGwZ=hF=UiOG2VyJkADZNcGVr1g1TFgQ@mail.gmail.com>
Hi
On Wed, 31 Oct 2012, Jean Pihet wrote:
> Paul,
> Could you please check with the 2 calls to PM QoS from the I2C code
> commented out? This will rule out the PM QoS impact.
Will be happy to do a test run for you, after the boot log from your local
test run is posted:
http://marc.info/?l=linux-arm-kernel&m=135167153510814&w=2
- Paul
^ permalink raw reply
* [PATCH 2/4] ARM: OMAP: hwmod: wait for sysreset complete after enabling hwmod
From: Paul Walmsley @ 2012-11-01 2:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121031104312.6557.22628.stgit@dusk.lan>
Here's the updated patch for this one.
- Paul
From: Tero Kristo <t-kristo@ti.com>
Date: Mon, 29 Oct 2012 22:02:13 -0600
Subject: [PATCH 1/3] ARM: OMAP: hwmod: wait for sysreset complete after
enabling hwmod
When waking up from off-mode, some IP blocks are reset automatically by
hardware. For this reason, software must wait until the reset has
completed before attempting to access the IP block.
This patch fixes for example the bug introduced by commit
6c31b2150ff96755d24e0ab6d6fea08a7bf5c44c ("mmc: omap_hsmmc: remove access
to SYSCONFIG register"), in which the MMC IP block is reset during
off-mode entry, but the code expects the module to be already available
during the execution of context restore.
This version includes a fix from Kevin Hilman <khilman@ti.com> for
GPIO problems on the 37xx EVM - thanks Kevin.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Venkatraman S <svenkatr@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
[paul at pwsan.com: moved softreset wait code into separate function; call
from top of _enable_sysc() rather than the bottom; include fix from Kevin
Hilman for GPIO sluggishness]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 60 +++++++++++++++++++++++++++++---------
1 file changed, 46 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index b969ab1..70267d2 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -422,6 +422,38 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v)
}
/**
+ * _wait_softreset_complete - wait for an OCP softreset to complete
+ * @oh: struct omap_hwmod * to wait on
+ *
+ * Wait until the IP block represented by @oh reports that its OCP
+ * softreset is complete. This can be triggered by software (see
+ * _ocp_softreset()) or by hardware upon returning from off-mode (one
+ * example is HSMMC). Waits for up to MAX_MODULE_SOFTRESET_WAIT
+ * microseconds. Returns the number of microseconds waited.
+ */
+static int _wait_softreset_complete(struct omap_hwmod *oh)
+{
+ struct omap_hwmod_class_sysconfig *sysc;
+ u32 softrst_mask;
+ int c = 0;
+
+ sysc = oh->class->sysc;
+
+ if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
+ omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs)
+ & SYSS_RESETDONE_MASK),
+ MAX_MODULE_SOFTRESET_WAIT, c);
+ else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) {
+ softrst_mask = (0x1 << sysc->sysc_fields->srst_shift);
+ omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs)
+ & softrst_mask),
+ MAX_MODULE_SOFTRESET_WAIT, c);
+ }
+
+ return c;
+}
+
+/**
* _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v
* @oh: struct omap_hwmod *
*
@@ -1282,6 +1314,18 @@ static void _enable_sysc(struct omap_hwmod *oh)
if (!oh->class->sysc)
return;
+ /*
+ * Wait until reset has completed, this is needed as the IP
+ * block is reset automatically by hardware in some cases
+ * (off-mode for example), and the drivers require the
+ * IP to be ready when they access it
+ */
+ if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
+ _enable_optional_clocks(oh);
+ _wait_softreset_complete(oh);
+ if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
+ _disable_optional_clocks(oh);
+
v = oh->_sysc_cache;
sf = oh->class->sysc->sysc_flags;
@@ -1804,7 +1848,7 @@ static int _am33xx_disable_module(struct omap_hwmod *oh)
*/
static int _ocp_softreset(struct omap_hwmod *oh)
{
- u32 v, softrst_mask;
+ u32 v;
int c = 0;
int ret = 0;
@@ -1834,19 +1878,7 @@ static int _ocp_softreset(struct omap_hwmod *oh)
if (oh->class->sysc->srst_udelay)
udelay(oh->class->sysc->srst_udelay);
- if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
- omap_test_timeout((omap_hwmod_read(oh,
- oh->class->sysc->syss_offs)
- & SYSS_RESETDONE_MASK),
- MAX_MODULE_SOFTRESET_WAIT, c);
- else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) {
- softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
- omap_test_timeout(!(omap_hwmod_read(oh,
- oh->class->sysc->sysc_offs)
- & softrst_mask),
- MAX_MODULE_SOFTRESET_WAIT, c);
- }
-
+ c = _wait_softreset_complete(oh);
if (c == MAX_MODULE_SOFTRESET_WAIT)
pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
oh->name, MAX_MODULE_SOFTRESET_WAIT);
--
1.7.10.4
^ permalink raw reply related
* [GIT PULL v2] ARM: OMAP: more hwmod/PRCM fixes for 3.7-rc
From: Paul Walmsley @ 2012-11-01 2:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1210311050040.4160@utopia.booyaka.com>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hi Tony
The following changes since commit 8f0d8163b50e01f398b14bcd4dc039ac5ab18d64:
Linux 3.7-rc3 (2012-10-28 12:24:48 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git tags/omap-fixes-b2-for-3.7-rc
for you to fetch changes up to bc05244e65f26b7b6f87e0964bfe277803914ed9:
ARM: OMAP4: hwmod data: do not enable or reset the McPDM during kernel init (2012-10-31 05:02:31 -0600)
- ----------------------------------------------------------------
A few more OMAP fixes for the 3.7-rc timeframe. Mostly hwmod fixes.
This second revision includes a missing fix from Kevin for a GPIO problem.
Basic test logs are available here:
http://www.pwsan.com/omap/testlogs/fixes_b_v3.7-rc/20121031050331/
However the v3.7-rc3 kernel is still missing fixes for several regressions,
which cause several tests to fail. With several reverts, fixes, and workarounds
applied, the following test logs were obtained:
http://www.pwsan.com/omap/testlogs/TEST_fixes_b_v3.7-rc/20121031050433/
which indicate that the series tests cleanly.
- ----------------------------------------------------------------
vmlinux object size
(delta in bytes from test_v3.7-rc3 (8f0d8163b50e01f398b14bcd4dc039ac5ab18d64)):
text data bss total kernel
-8 0 0 -8 am33xx_only
+156 +8 0 +164 n800_multi_omap2xxx
+136 +16 0 +152 n800_only_a
-8 -8 0 -16 omap1_defconfig
+12 -24 0 -12 omap1_defconfig_1510innovator_only
+12 +8 +32 +52 omap1_defconfig_5912osk_only
+132 0 0 +132 omap2plus_defconfig
+156 -16 0 +140 omap2plus_defconfig_2430sdp_only
+68 0 0 +68 omap2plus_defconfig_cpupm
+132 0 +64 +196 omap2plus_defconfig_no_pm
+104 +24 +64 +192 omap2plus_defconfig_omap2_4_only
+40 +16 0 +56 omap2plus_defconfig_omap3_4_only
+304 0 0 +304 rmk_omap3430_ldp_oldconfig
+260 0 0 +260 rmk_omap4430_sdp_oldconfig
Miguel Vadillo (1):
ARM: OMAP2+: clockdomain: Fix OMAP4 ISS clk domain to support only SWSUP
Paul Walmsley (2):
ARM: OMAP2+: hwmod: add flag to prevent hwmod code from touching IP block during init
ARM: OMAP4: hwmod data: do not enable or reset the McPDM during kernel init
Tero Kristo (1):
ARM: OMAP: hwmod: wait for sysreset complete after enabling hwmod
arch/arm/mach-omap2/clockdomains44xx_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod.c | 63 ++++++++++++++++++++------
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 8 ++++
arch/arm/plat-omap/include/plat/omap_hwmod.h | 6 +++
4 files changed, 64 insertions(+), 15 deletions(-)
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^ permalink raw reply
* [PATCH V4 0/4] ARM: tegra: Enable SLINK controller driver
From: Laxman Dewangan @ 2012-11-01 3:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5091791F.4080400@wwwdotorg.org>
On Thursday 01 November 2012 12:46 AM, Stephen Warren wrote:
> On 10/31/2012 11:31 AM, Laxman Dewangan wrote:
>> On Wednesday 31 October 2012 09:59 PM, Stephen Warren wrote:
>>> On 10/31/2012 03:02 AM, Laxman Dewangan wrote:
>>>> This series modify the dts file to add the slink addresses,
>>>> make AUXDATA in board dt files, enable slink4 for tegra30-cardhu and
>>>> enable slink controller defconfig.
>>> I don't appear to have received patch 1/4 this time around. I'll assume
>>> it's identical to V3, since I don't think anything needed to change
>>> there...
>> Yes, it is identical to V3, no change on the 1/4.
> OK, I have applied the series now. Thanks.
>
> BTW, I noticed that the Cardu board files sets the SPI controller's max
> frequency to 25MHZ (which is consistent with the commit description) but
> the SPI flash node's frequency to 20MHz. Was that intended, or should I
> fix it up to be 25MHz?
If device provide the max frequency then the spi communciation will on
this requested frequency.
If device does not provide the max spi frequency then it will
communciate with the controller max frequency.
In this case we provide the 20MHz for device and 25MHz for controller.
So spi communciation with this device will be always 20MHz.
^ permalink raw reply
* [PATCH -next] CLK: clk-twl6040: fix return value check in twl6040_clk_probe()
From: Wei Yongjun @ 2012-11-01 5:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
In case of error, the function clk_register() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().
dpatch engine is used to auto generate this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
---
drivers/clk/clk-twl6040.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-twl6040.c b/drivers/clk/clk-twl6040.c
index f4a3389..bc1e713 100644
--- a/drivers/clk/clk-twl6040.c
+++ b/drivers/clk/clk-twl6040.c
@@ -92,8 +92,8 @@ static int __devinit twl6040_clk_probe(struct platform_device *pdev)
clkdata->mcpdm_fclk.init = &wm831x_clkout_init;
clkdata->clk = clk_register(&pdev->dev, &clkdata->mcpdm_fclk);
- if (!clkdata->clk)
- return -EINVAL;
+ if (IS_ERR(clkdata->clk))
+ return PTR_ERR(clkdata->clk);
dev_set_drvdata(&pdev->dev, clkdata);
^ permalink raw reply related
* [PATCH v3 9/9] pinctrl: single: dump pinmux register value
From: Haojian Zhuang @ 2012-11-01 5:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121101004734.GK15766@atomide.com>
On Thu, Nov 1, 2012 at 1:47 AM, Tony Lindgren <tony@atomide.com> wrote:
> * Haojian Zhuang <haojian.zhuang@gmail.com> [121031 16:07]:
>> Dump pinmux register value, not only function part in the pinmux
>> register.
>>
>> Also fix the issue on caluclating pin offset. The last parameter
>> should be pin number, not register offset.
>
> You have a minor typo ^^^^^^^^^^^ should be calculating
> instead.
>
> Is there a bug that should be fixed for the -rc cycle
> here? That's the impression I get from the description.
> Or is it just a cosmetic fix to rename offset to pin?
>
> Regards,
>
> Tony
>
>> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
>> ---
>> drivers/pinctrl/pinctrl-single.c | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
>> index 3b97b65..72017e7 100644
>> --- a/drivers/pinctrl/pinctrl-single.c
>> +++ b/drivers/pinctrl/pinctrl-single.c
>> @@ -283,15 +283,15 @@ static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
>>
>> static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
>> struct seq_file *s,
>> - unsigned offset)
>> + unsigned pin)
>> {
>> struct pcs_device *pcs;
>> - unsigned val;
>> + unsigned val, mux_bytes;
>>
>> pcs = pinctrl_dev_get_drvdata(pctldev);
>>
>> - val = pcs->read(pcs->base + offset);
>> - val &= pcs->fmask;
>> + mux_bytes = pcs->width / BITS_PER_BYTE;
>> + val = pcs->read(pcs->base + pin * mux_bytes);
>>
>> seq_printf(s, "%08x %s " , val, DRIVER_NAME);
>> }
>> --
>> 1.7.10.4
>>
There's also include a bug fix. I'm OK that this patch could be
included in -rc cycle.
^ permalink raw reply
* [PATCH 4/4] arm/dts: am33xx: Add CPSW and MDIO module nodes for AM33XX
From: Richard Cochran @ 2012-11-01 7:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50914107.2090909@ti.com>
On Wed, Oct 31, 2012 at 04:17:27PM +0100, Benoit Cousson wrote:
> > + compatible = "ti,cpsw";
> > + ti,hwmods = "cpgmac0";
> > + cpdma_channels = <8>;
> > + host_port_no = <0>;
> > + cpdma_reg_ofs = <0x800>;
> > + cpdma_sram_ofs = <0xa00>;
> > + ale_reg_ofs = <0xd00>;
> > + ale_entries = <1024>;
> > + host_port_reg_ofs = <0x108>;
> > + hw_stats_reg_ofs = <0x900>;
> > + bd_ram_ofs = <0x2000>;
> > + bd_ram_size = <0x2000>;
> > + no_bd_ram = <0>;
> > + rx_descs = <64>;
> > + mac_control = <0x20>;
>
> Do you have to store all these data in the DTS? Cannot it be in the driver?
>
> Do you expect to have several instance of the same IP with different
> parameters here?
As I understand it, there are only two different layouts for the CPSW,
the one in the dm814x and the one in the am335x. So I think it would
work to put only the version register offet in the DT, and the let the
driver figure out the rest from there.
But if TI is planning on reordering the registers with each new
silicon revision, again and again, then it might make sense to keep
the offsets in the DT.
[ I really wonder why the hardware people think that reshuffling the
register layout constitutes an improvement. ]
Thanks,
Richard
^ permalink raw reply
* OMAP baseline test results for v3.7-rc1
From: Jean Pihet @ 2012-11-01 7:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1211010242001.6693@utopia.booyaka.com>
Hi Paul,
On Wed, Oct 31, 2012 at 10:44 PM, Paul Walmsley <paul@pwsan.com> wrote:
> Hi
>
> On Wed, 31 Oct 2012, Jean Pihet wrote:
>
>> Paul,
>> Could you please check with the 2 calls to PM QoS from the I2C code
>> commented out? This will rule out the PM QoS impact.
>
> Will be happy to do a test run for you, after the boot log from your local
> test run is posted:
>
> http://marc.info/?l=linux-arm-kernel&m=135167153510814&w=2
As said earlier [1] the test has been done already. I did check the
boot messages and tried to read/write the RTC. All test were
successfull and the only difference in the logs was the absence of the
I2C timeout messages.
I can redo the tests and provide a log but that will not happen before Saturday.
[1] http://marc.info/?l=linux-omap&m=135161909714517&w=2
Regards,
Jean
>
>
> - Paul
^ permalink raw reply
* [PATCHv2] Input: omap4-keypad: Add pinctrl support
From: Linus Walleij @ 2012-11-01 8:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87obji8kta.fsf@deeprootsystems.com>
On Wed, Oct 31, 2012 at 9:10 PM, Kevin Hilman
<khilman@deeprootsystems.com>wrote:
> Linus Walleij <linus.walleij@linaro.org> writes:
>
> > piece of hardware, this would be the right thing to do,
> > and I think the in-kernel examples are all "simple",
> > e.g. arch/arm/mach-omap2/powerdomain* is all about
> > power domains and nothing else,
>
> FYI... that code isn't the same as PM domain.
This sort of points to a core problem here. Our terminologies are
ambiguous that we cannot understand each others code. As long
as <linux/pm_domain.h> begins:
/*
* pm_domain.h - Definitions and headers related to device power domains.
*
But arguably that should just be patched (I think there are a few
remnants in the code still implying that these things are only about
power).
> That code is for the
> *hardware* powerdomains, not the software concept of "PM domain." In
> OMAP, PM domain is implmented at the omap_device level. And omap_device
> is the abstraction of an IP block that knows about all the PM related
> register settings, clocks, HW powerdomain, voltage domain, PM related
> pin-muxing etc. etc. All of these things are abstracted in an
> omap_device, so that the PM domain implementation for OMAP looks rather
> simple (c.f. omap_device_pm_domain in arch/arm/plat-omap/omap_device.c.)
>
OK following now...
> > I think the lesser of two evils is the distributed approach,
>
The pinctrl examples I've seen mentioned so far are all PM related
> (sleep, idle, wakeup, etc.) so to me I think they still belong in
> PM domains (and that's how we handle the PM related pins in OMAP.)
>
Well, the pinctrl grabbers in these drivers are using these states also
for platforms that do not even select CONFIG_PM. For example
mach-nomadik is quite happy that the PL011 driver is thusly
muxing in its pins. And would require refactoring to use PM
domains.
So basically this requirement comes down to:
- When dealing with a SoC IP block driver
- That need to multiplex pins
- Then your SoC must select CONFIG_PM and
CONFIG_PM_RUNTIME and
CONFIG_PM_GENERIC_DOMAINS and implement
proper domain handling hooks.
Is this correct? And for Mark, Dmitry, does this correspond to
your view?
It's actually something that needs to be acknowledged by the
ARM SoC maintainers, because they will be the ones telling
all subarch maintainers to go implement full PM handling
with these three frameworks whenever an SoC driver want
to handle pins.
Bascially all subsystem maintainers dealing with embedded
SoCs need to be aligned on this as well...
And IIUC not only pins but also silicon block clocks?
I can surely fix these for "my" systems, but it really needs
to be enforced widely or it will be a mess.
> > I worry that the per-SoC power domain implementation
> > which will live in arch/arm/mach-* as of today will become
> > the new board file problem, overburdening the arch/* tree.
> > Maybe I'm mistaken as to the size of these things,
> > but just doing ls arch/arm/mach-omap2/powerdomain*
> > makes me start worrying.
>
> Yes, I agree that this means more code/data in arch/arm/mach-*, but
> IMO, that's really where it belongs. It really is SoC integration
> details, and driver should really not know about it.
OK we need feedback from ARM SoC on this.
Yours,
Linus Walleij
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