* [PATCH 06/15] ARM: OMAP2+: hwmod: Enable OCMCRAM registration in AM33XX
From: Vaibhav Bedia @ 2012-11-02 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-1-git-send-email-vaibhav.bedia@ti.com>
The hwmod data for OCMCRAM in AM33XX was commented out.
This data is needed by the power management code, hence
uncomment the same and register the OCP interface for it.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 11 ++++++++++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 2e470ce..ec3fbb2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -415,7 +415,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
* - cEFUSE (doesn't fall under any ocp_if)
* - clkdiv32k
* - debugss
- * - ocmc ram
* - ocp watch point
* - aes0
* - sha0
@@ -481,6 +480,7 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
},
},
};
+#endif
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
@@ -501,6 +501,7 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
},
};
+#if 0
/* ocpwp */
static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
.name = "ocpwp",
@@ -3331,6 +3332,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
.flags = OCPIF_SWSUP_IDLE,
};
+/* l3 main -> ocmc */
+static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_ocmcram_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_fw__emif_fw,
&am33xx_l3_main__emif,
@@ -3401,6 +3409,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__tptc0,
&am33xx_l3_main__tptc1,
&am33xx_l3_main__tptc2,
+ &am33xx_l3_main__ocmc,
&am33xx_l3_s__usbss,
&am33xx_l4_hs__cpgmac0,
&am33xx_cpgmac0__mdio,
--
1.7.0.4
^ permalink raw reply related
* [PATCH 07/15] ARM: OMAP2+: hwmod: Update the hwmod data for TPTCs in AM33XX
From: Vaibhav Bedia @ 2012-11-02 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-1-git-send-email-vaibhav.bedia@ti.com>
Update the TPTC hwmod entry to reflect the fact that
the idle and standby transitions are s/w controlled.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index ec3fbb2..7772c29 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -1827,6 +1827,7 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
.class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_tptc0_irqs,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
--
1.7.0.4
^ permalink raw reply related
* [PATCH 08/15] ARM: OMAP2+: hwmod: Fix the omap_hwmod_addr_space for CPGMAC0
From: Vaibhav Bedia @ 2012-11-02 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-1-git-send-email-vaibhav.bedia@ti.com>
The first entry for CPGMAC0 should be ADDR_MAP_ON_INIT
instead of ADDR_TYPE_RT to ensure the omap hwmod code
maps the memory space at init and writes to the SYSCONFIG
registers.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 7772c29..881b570 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -2500,7 +2500,7 @@ static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
{
.pa_start = 0x4a100000,
.pa_end = 0x4a100000 + SZ_2K - 1,
- .flags = ADDR_TYPE_RT,
+ .flags = ADDR_MAP_ON_INIT,
},
/* cpsw wr */
{
--
1.7.0.4
^ permalink raw reply related
* [PATCH 09/15] ARM: OMAP: AM33XX: Remove unnecessary include and use __ASSEMBLER__ macros
From: Vaibhav Bedia @ 2012-11-02 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-1-git-send-email-vaibhav.bedia@ti.com>
Get rid of some unnecessary header file inclusions
and also use __ASSEMBLER__ macros to allow the
various register offsets from PM assembly code
which be added in a subsequent patch.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
---
arch/arm/mach-omap2/clock33xx_data.c | 1 +
arch/arm/mach-omap2/cm33xx.h | 10 ++++------
arch/arm/mach-omap2/prm33xx.h | 2 ++
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 17e3de5..78dc85b 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -17,6 +17,7 @@
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
+#include <linux/io.h>
#include "soc.h"
#include "iomap.h"
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 5fa0b62..91515f1 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -17,16 +17,11 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
#include "common.h"
#include "cm.h"
#include "cm-regbits-33xx.h"
-#include "cm33xx.h"
+#include "iomap.h"
/* CM base address */
#define AM33XX_CM_BASE 0x44e00000
@@ -381,6 +376,7 @@
#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
+#ifndef __ASSEMBLER__
extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
@@ -417,4 +413,6 @@ static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
}
#endif
+#endif /* ASSEMBLER */
+
#endif
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 181fdab..3683376 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -117,6 +117,7 @@
#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004
#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
+#ifndef __ASSEMBLER__
extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
@@ -126,4 +127,5 @@ extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
extern int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
u16 rstctrl_offs, u16 rstst_offs);
+#endif /* __ASSEMBLER__ */
#endif
--
1.7.0.4
^ permalink raw reply related
* [PATCH 10/15] ARM: OMAP2+: control: Add some AM33XX Control module registers
From: Vaibhav Bedia @ 2012-11-02 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-1-git-send-email-vaibhav.bedia@ti.com>
These registers will be required in a subsequent
patch which adds basic suspend-resume support for
AM33XX.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
---
arch/arm/mach-omap2/control.h | 29 +++++++++++++++++++++++++++++
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a89e825..bb99302 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -357,6 +357,35 @@
#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
+#define AM33XX_DDR_IO_CTRL 0x0E04
+#define AM33XX_VTP0_CTRL_REG 0x0E0C
+
+/* AM33XX VTP0_CTRL_REG bits */
+#define AM33XX_VTP_CTRL_START_EN BIT(0)
+#define AM33XX_VTP_CTRL_LOCK_EN BIT(4)
+#define AM33XX_VTP_CTRL_READY BIT(5)
+#define AM33XX_VTP_CTRL_ENABLE BIT(6)
+
+
+/* AM33XX M3_TXEV_EOI registers */
+#define AM33XX_CONTROL_M3_TXEV_EOI 0x1324
+
+/* AM33XX IPC message registers */
+#define AM33XX_CONTROL_IPC_MSG_REG0 0x1328
+#define AM33XX_CONTROL_IPC_MSG_REG1 0x132C
+#define AM33XX_CONTROL_IPC_MSG_REG2 0x1330
+#define AM33XX_CONTROL_IPC_MSG_REG3 0x1334
+#define AM33XX_CONTROL_IPC_MSG_REG4 0x1338
+#define AM33XX_CONTROL_IPC_MSG_REG5 0x133C
+#define AM33XX_CONTROL_IPC_MSG_REG6 0x1340
+#define AM33XX_CONTROL_IPC_MSG_REG7 0x1344
+
+#define AM33XX_DDR_CMD0_IOCTRL 0x1404
+#define AM33XX_DDR_CMD1_IOCTRL 0x1408
+#define AM33XX_DDR_CMD2_IOCTRL 0x140C
+#define AM33XX_DDR_DATA0_IOCTRL 0x1440
+#define AM33XX_DDR_DATA1_IOCTRL 0x1444
+
/* CONTROL OMAP STATUS register to identify OMAP3 features */
#define OMAP3_CONTROL_OMAP_STATUS 0x044c
--
1.7.0.4
^ permalink raw reply related
* [PATCH 11/15] ARM: OMAP: timer: Interchange clksrc and clkevt for AM33XX
From: Vaibhav Bedia @ 2012-11-02 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-1-git-send-email-vaibhav.bedia@ti.com>
AM33XX has only one usable timer in the WKUP domain.
Currently the timer instance in WKUP domain is used
as the clockevent and the timer in non-WKUP domain
as the clocksource. The timer in WKUP domain can keep
running in suspend from a 32K clock and hence serve
as the persistent clock. To enable this, interchange
the timers used as clocksource and clockevent for
AM33XX. A subsequent patch will add suspend-resume
support for the clockevent to ensure that there are
no issues with timekeeping.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
---
arch/arm/mach-omap2/timer.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 565e575..6584ee0 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -460,7 +460,7 @@ OMAP_SYS_TIMER(3_secure)
#endif
#ifdef CONFIG_SOC_AM33XX
-OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER_INIT(3_am33xx, 2, OMAP4_MPU_SOURCE, 1, OMAP4_MPU_SOURCE)
OMAP_SYS_TIMER(3_am33xx)
#endif
--
1.7.0.4
^ permalink raw reply related
* [PATCH 12/15] ARM: OMAP: timer: Add suspend-resume callbacks for clockevent device
From: Vaibhav Bedia @ 2012-11-02 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-1-git-send-email-vaibhav.bedia@ti.com>
From: Vaibhav Hiremath <hvaibhav@ti.com>
The current OMAP timer code registers two timers -
one as clocksource and one as clockevent.
AM33XX has only one usable timer in the WKUP domain
so one of the timers needs suspend-resume support
to restore the configuration to pre-suspend state.
commit adc78e6 (timekeeping: Add suspend and resume
of clock event devices) introduced .suspend and .resume
callbacks for clock event devices. Leverages these
callbacks to have AM33XX clockevent timer which is
in not in WKUP domain to behave properly across system
suspend.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
---
arch/arm/mach-omap2/timer.c | 31 +++++++++++++++++++++++++++++++
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 6584ee0..e8781fd 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -135,6 +135,35 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
}
}
+static void omap_clkevt_suspend(struct clock_event_device *unused)
+{
+ char name[10];
+ struct omap_hwmod *oh;
+
+ sprintf(name, "timer%d", 2);
+ oh = omap_hwmod_lookup(name);
+ if (!oh)
+ return;
+
+ omap_hwmod_idle(oh);
+}
+
+static void omap_clkevt_resume(struct clock_event_device *unused)
+{
+ char name[10];
+ struct omap_hwmod *oh;
+
+ sprintf(name, "timer%d", 2);
+ oh = omap_hwmod_lookup(name);
+ if (!oh)
+ return;
+
+ omap_hwmod_enable(oh);
+ __omap_dm_timer_load_start(&clkev,
+ OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
+ __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
+}
+
static struct clock_event_device clockevent_gpt = {
.name = "gp_timer",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
@@ -142,6 +171,8 @@ static struct clock_event_device clockevent_gpt = {
.rating = 300,
.set_next_event = omap2_gp_timer_set_next_event,
.set_mode = omap2_gp_timer_set_mode,
+ .suspend = omap_clkevt_suspend,
+ .resume = omap_clkevt_resume,
};
static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
--
1.7.0.4
^ permalink raw reply related
* [PATCH 13/15] ARM: DTS: AM33XX: Add nodes for OCMCRAM and Mailbox
From: Vaibhav Bedia @ 2012-11-02 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-1-git-send-email-vaibhav.bedia@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
---
arch/arm/boot/dts/am33xx.dtsi | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff..e2cbf24 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -210,5 +210,16 @@
interrupt-parent = <&intc>;
interrupts = <91>;
};
+
+ ocmcram: ocmcram at 40300000 {
+ compatible = "ti,ocmcram";
+ ti,hwmods = "ocmcram";
+ ti,no_idle_on_suspend;
+ };
+
+ wkup_m3: wkup_m3 at 44d00000 {
+ compatible = "ti,wkup_m3";
+ ti,hwmods = "wkup_m3";
+ };
};
};
--
1.7.0.4
^ permalink raw reply related
* [PATCH 14/15] ARM: OMAP2+: omap2plus_defconfig: Enable Mailbox
From: Vaibhav Bedia @ 2012-11-02 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-1-git-send-email-vaibhav.bedia@ti.com>
AM33XX PM code depends on Mailbox module for IPC
between MPU and WKUP_M3.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
---
arch/arm/configs/omap2plus_defconfig | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 6230304..3fbb13d 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -23,6 +23,8 @@ CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_ARCH_OMAP=y
CONFIG_OMAP_RESET_CLOCKS=y
CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_OMAP_MBOX_FWK=y
+CONFIG_OMAP_MBOX_KFIFO_SIZE=256
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_ERRATA_411920=y
CONFIG_NO_HZ=y
--
1.7.0.4
^ permalink raw reply related
* [PATCH 15/15] ARM: OMAP2+: AM33XX: Basic suspend resume support
From: Vaibhav Bedia @ 2012-11-02 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-1-git-send-email-vaibhav.bedia@ti.com>
AM335x supports various low power modes as documented
in section 8.1.4.3 of the AM335x TRM which is available
@ http://www.ti.com/litv/pdf/spruh73f
DeepSleep0 mode offers the lowest power mode with limited
wakeup sources without a system reboot and is mapped as
the suspend state in the kernel. In this state, MPU and
PER domains are turned off with the internal RAM held in
retention to facilitate resume process. As part of the boot
process, the assembly code is copied over to OCMCRAM using
the OMAP SRAM code.
AM335x has a Cortex-M3 (WKUP_M3) which assists the MPU
in DeepSleep0 entry and exit. WKUP_M3 takes care of the
clockdomain and powerdomain transitions based on the
intended low power state. MPU needs to load the appropriate
WKUP_M3 binary onto the WKUP_M3 memory space before it can
leverage any of the PM features like DeepSleep.
The IPC mechanism between MPU and WKUP_M3 uses a mailbox
sub-module and 8 IPC registers in the Control module. MPU
uses the assigned Mailbox for issuing an interrupt to
WKUP_M3 which then goes and checks the IPC registers for
the payload. WKUP_M3 has the ability to trigger on interrupt
to MPU by executing the "sev" instruction.
In the current implementation when the suspend process
is initiated MPU interrupts the WKUP_M3 to let about the
intent of entering DeepSleep0 and waits for an ACK. When
the ACK is received, MPU continues with its suspend process
to suspend all the drivers and then jumps to assembly in
OCMC RAM to put the PLLs in bypass, put the external RAM in
self-refresh mode and then finally execute the WFI instruction.
The WFI instruction triggers another interrupt to the WKUP_M3
which then continues wiht the power down sequence wherein the
clockdomain and powerdomain transition takes place. As part of
the sleep sequence, WKUP_M3 unmasks the interrupt lines for
the wakeup sources. When WKUP_M3 executes WFI, the hardware
disables the main oscillator.
When a wakeup event occurs, WKUP_M3 starts the power-up
sequence by switching on the power domains and finally
enabling the clock to MPU. Since the MPU gets powered down
as part of the sleep sequence, in the resume path ROM code
starts executing. The ROM code detects a wakeup from sleep
and then jumps to the resume location in OCMC which was
populated in one of the IPC registers as part of the suspend
sequence.
The low level code in OCMC relocks the PLLs, enables access
to external RAM and then jumps to the cpu_resume code of
the kernel to finish the resume process.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
---
arch/arm/mach-omap2/Makefile | 2 +
arch/arm/mach-omap2/board-generic.c | 1 +
arch/arm/mach-omap2/common.h | 10 +
arch/arm/mach-omap2/io.c | 7 +
arch/arm/mach-omap2/pm.h | 7 +
arch/arm/mach-omap2/pm33xx.c | 429 ++++++++++++++++++++++++++
arch/arm/mach-omap2/pm33xx.h | 100 ++++++
arch/arm/mach-omap2/sleep33xx.S | 571 +++++++++++++++++++++++++++++++++++
arch/arm/plat-omap/sram.c | 10 +-
arch/arm/plat-omap/sram.h | 2 +
10 files changed, 1138 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/pm33xx.c
create mode 100644 arch/arm/mach-omap2/pm33xx.h
create mode 100644 arch/arm/mach-omap2/sleep33xx.S
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ae87a3e..80736aa 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -71,6 +71,7 @@ endif
ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
+obj-$(CONFIG_SOC_AM33XX) += pm33xx.o sleep33xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
@@ -80,6 +81,7 @@ obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
+AFLAGS_sleep33xx.o :=-Wa,-march=armv7-a$(plus_sec)
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
ifeq ($(CONFIG_PM_VERBOSE),y)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 601ecdf..23894df 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -109,6 +109,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = am33xx_map_io,
.init_early = am33xx_init_early,
+ .init_late = am33xx_init_late,
.init_irq = omap_intc_of_init,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_generic_init,
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index c925c80..d4319ad 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -109,6 +109,15 @@ static inline int omap3_pm_init(void)
}
#endif
+#if defined(CONFIG_PM) && defined(CONFIG_SOC_AM33XX)
+int am33xx_pm_init(void);
+#else
+static inline int am33xx_pm_init(void)
+{
+ return 0;
+}
+#endif
+
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
int omap4_pm_init(void);
#else
@@ -157,6 +166,7 @@ void am33xx_init_early(void);
void omap4430_init_early(void);
void omap5_init_early(void);
void omap3_init_late(void); /* Do not use this one */
+void am33xx_init_late(void);
void omap4430_init_late(void);
void omap2420_init_late(void);
void omap2430_init_late(void);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4fadc78..d06f84a 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -528,6 +528,13 @@ void __init am33xx_init_early(void)
omap_hwmod_init_postsetup();
am33xx_clk_init();
}
+
+void __init am33xx_init_late(void)
+{
+ omap_mux_late_init();
+ omap2_common_pm_late_init();
+ am33xx_pm_init();
+}
#endif
#ifdef CONFIG_ARCH_OMAP4
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 67d6613..d37f20e 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -83,6 +83,13 @@ extern unsigned int omap3_do_wfi_sz;
/* ... and its pointer from SRAM after copy */
extern void (*omap3_do_wfi_sram)(void);
+/* am33xx_do_wfi function pointer and size, for copy to SRAM */
+extern void am33xx_do_wfi(void);
+extern unsigned int am33xx_do_wfi_sz;
+extern unsigned int am33xx_resume_offset;
+/* ... and its pointer from SRAM after copy */
+extern void (*am33xx_do_wfi_sram)(void);
+
/* save_secure_ram_context function pointer and size, for copy to SRAM */
extern int save_secure_ram_context(u32 *addr);
extern unsigned int save_secure_ram_context_sz;
diff --git a/arch/arm/mach-omap2/pm33xx.c b/arch/arm/mach-omap2/pm33xx.c
new file mode 100644
index 0000000..836af52
--- /dev/null
+++ b/arch/arm/mach-omap2/pm33xx.c
@@ -0,0 +1,429 @@
+/*
+ * AM33XX Power Management Routines
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Bedia <vaibhav.bedia@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/firmware.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/suspend.h>
+#include <linux/completion.h>
+#include <linux/module.h>
+
+#include <plat/prcm.h>
+#include <plat/mailbox.h>
+#include "../plat-omap/sram.h"
+
+#include <asm/suspend.h>
+#include <asm/proc-fns.h>
+#include <asm/sizes.h>
+#include <asm/system_misc.h>
+
+#include "pm.h"
+#include "cm33xx.h"
+#include "pm33xx.h"
+#include "control.h"
+#include "clockdomain.h"
+#include "powerdomain.h"
+#include "omap_hwmod.h"
+#include "omap_device.h"
+#include "soc.h"
+
+void (*am33xx_do_wfi_sram)(void);
+
+static void __iomem *am33xx_emif_base;
+static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm;
+static struct clockdomain *gfx_l3_clkdm, *gfx_l4ls_clkdm;
+static struct wkup_m3_context *wkup_m3;
+
+static DECLARE_COMPLETION(wkup_m3_sync);
+
+#ifdef CONFIG_SUSPEND
+static int am33xx_do_sram_idle(long unsigned int unused)
+{
+ am33xx_do_wfi_sram();
+ return 0;
+}
+
+static int am33xx_pm_suspend(void)
+{
+ int status, ret = 0;
+
+ struct omap_hwmod *gpmc_oh, *usb_oh;
+ struct omap_hwmod *tptc0_oh, *tptc1_oh, *tptc2_oh;
+
+ /*
+ * By default the following IPs do not have MSTANDBY asserted
+ * which is necessary for PER domain transition. If the drivers
+ * are not compiled into the kernel HWMOD code will not change the
+ * state of the IPs if the IP was not never enabled
+ */
+ usb_oh = omap_hwmod_lookup("usb_otg_hs");
+ gpmc_oh = omap_hwmod_lookup("gpmc");
+ tptc0_oh = omap_hwmod_lookup("tptc0");
+ tptc1_oh = omap_hwmod_lookup("tptc1");
+ tptc2_oh = omap_hwmod_lookup("tptc2");
+
+ omap_hwmod_enable(usb_oh);
+ omap_hwmod_enable(gpmc_oh);
+ omap_hwmod_enable(tptc0_oh);
+ omap_hwmod_enable(tptc1_oh);
+ omap_hwmod_enable(tptc2_oh);
+
+ omap_hwmod_idle(usb_oh);
+ omap_hwmod_idle(gpmc_oh);
+ omap_hwmod_idle(tptc0_oh);
+ omap_hwmod_idle(tptc1_oh);
+ omap_hwmod_idle(tptc2_oh);
+
+ /* Put the GFX clockdomains to sleep */
+ clkdm_sleep(gfx_l3_clkdm);
+ clkdm_sleep(gfx_l4ls_clkdm);
+
+ /* Try to put GFX to sleep */
+ pwrdm_set_next_pwrst(gfx_pwrdm, PWRDM_POWER_OFF);
+
+ ret = cpu_suspend(0, am33xx_do_sram_idle);
+
+ status = pwrdm_read_pwrst(gfx_pwrdm);
+ if (status != PWRDM_POWER_OFF)
+ pr_err("GFX domain did not transition\n");
+ else
+ pr_info("GFX domain entered low power state\n");
+
+ /* Needed to ensure L4LS clockdomain transitions properly */
+ clkdm_wakeup(gfx_l3_clkdm);
+ clkdm_wakeup(gfx_l4ls_clkdm);
+
+ if (ret) {
+ pr_err("Kernel suspend failure\n");
+ } else {
+ status = omap_ctrl_readl(AM33XX_CONTROL_IPC_MSG_REG1);
+ status &= IPC_RESP_MASK;
+ status >>= __ffs(IPC_RESP_MASK);
+
+ switch (status) {
+ case 0:
+ pr_info("Successfully transitioned to low power state\n");
+ if (wkup_m3->sleep_mode == IPC_CMD_DS0)
+ /* XXX: Use SOC specific ops for this? */
+ per_pwrdm->ret_logic_off_counter++;
+ break;
+ case 1:
+ pr_err("Could not enter low power state\n");
+ ret = -1;
+ break;
+ default:
+ pr_err("Something is terribly wrong :(\nStatus = %d\n",
+ status);
+ ret = -1;
+ }
+ }
+
+ return ret;
+}
+
+static int am33xx_pm_enter(suspend_state_t suspend_state)
+{
+ int ret = 0;
+
+ switch (suspend_state) {
+ case PM_SUSPEND_STANDBY:
+ case PM_SUSPEND_MEM:
+ ret = am33xx_pm_suspend();
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static int am33xx_pm_begin(suspend_state_t state)
+{
+ int ret = 0;
+
+ disable_hlt();
+
+ /*
+ * Physical resume address to be used by ROM code
+ */
+ wkup_m3->resume_addr = (AM33XX_OCMC_END - am33xx_do_wfi_sz +
+ am33xx_resume_offset + 0x4);
+
+ wkup_m3->sleep_mode = IPC_CMD_DS0;
+ wkup_m3->ipc_data1 = DS_IPC_DEFAULT;
+ wkup_m3->ipc_data2 = DS_IPC_DEFAULT;
+
+ am33xx_ipc_cmd();
+
+ wkup_m3->state = M3_STATE_MSG_FOR_LP;
+
+ omap_mbox_enable_irq(wkup_m3->mbox, IRQ_RX);
+
+ ret = omap_mbox_msg_send(wkup_m3->mbox, 0xABCDABCD);
+ if (ret) {
+ pr_err("A8<->CM3 MSG for LP failed\n");
+ am33xx_m3_state_machine_reset();
+ ret = -1;
+ }
+
+ if (!wait_for_completion_timeout(&wkup_m3_sync,
+ msecs_to_jiffies(500))) {
+ pr_err("A8<->CM3 sync failure\n");
+ am33xx_m3_state_machine_reset();
+ ret = -1;
+ } else {
+ pr_debug("Message sent for entering DeepSleep mode\n");
+ omap_mbox_disable_irq(wkup_m3->mbox, IRQ_RX);
+ }
+
+ return ret;
+}
+
+static void am33xx_pm_end(void)
+{
+ omap_mbox_enable_irq(wkup_m3->mbox, IRQ_RX);
+
+ am33xx_m3_state_machine_reset();
+
+ enable_hlt();
+
+ return;
+}
+
+static const struct platform_suspend_ops am33xx_pm_ops = {
+ .begin = am33xx_pm_begin,
+ .end = am33xx_pm_end,
+ .enter = am33xx_pm_enter,
+ .valid = suspend_valid_only_mem,
+};
+
+static void am33xx_ipc_cmd(void)
+{
+ omap_ctrl_writel(wkup_m3->resume_addr, AM33XX_CONTROL_IPC_MSG_REG0);
+ omap_ctrl_writel(wkup_m3->sleep_mode, AM33XX_CONTROL_IPC_MSG_REG1);
+ omap_ctrl_writel(wkup_m3->ipc_data1, AM33XX_CONTROL_IPC_MSG_REG2);
+ omap_ctrl_writel(wkup_m3->ipc_data2, AM33XX_CONTROL_IPC_MSG_REG3);
+}
+
+static void am33xx_m3_state_machine_reset(void)
+{
+ int ret = 0;
+
+ wkup_m3->resume_addr = 0x0;
+ wkup_m3->sleep_mode = IPC_CMD_RESET;
+ wkup_m3->ipc_data1 = DS_IPC_DEFAULT;
+ wkup_m3->ipc_data2 = DS_IPC_DEFAULT;
+
+ am33xx_ipc_cmd();
+
+ wkup_m3->state = M3_STATE_MSG_FOR_RESET;
+
+ ret = omap_mbox_msg_send(wkup_m3->mbox, 0xABCDABCD);
+ if (!ret) {
+ pr_debug("Message sent for resetting M3 state machine\n");
+ if (!wait_for_completion_timeout(&wkup_m3_sync,
+ msecs_to_jiffies(500)))
+ pr_err("A8<->CM3 sync failure\n");
+ } else {
+ pr_err("Could not reset M3 state machine!!!\n");
+ wkup_m3->state = M3_STATE_UNKNOWN;
+ }
+}
+#endif /* CONFIG_SUSPEND */
+
+/*
+ * Dummy notifier for the mailbox
+ */
+int wkup_mbox_msg(struct notifier_block *self, unsigned long len, void *msg)
+{
+ return 0;
+}
+
+static struct notifier_block wkup_mbox_notifier = {
+ .notifier_call = wkup_mbox_msg,
+};
+
+static irqreturn_t wkup_m3_txev_handler(int irq, void *unused)
+{
+ omap_ctrl_writel(0x1, AM33XX_CONTROL_M3_TXEV_EOI);
+
+ switch (wkup_m3->state) {
+ case M3_STATE_RESET:
+ wkup_m3->state = M3_STATE_INITED;
+ break;
+ case M3_STATE_MSG_FOR_RESET:
+ wkup_m3->state = M3_STATE_INITED;
+ omap_mbox_msg_rx_flush(wkup_m3->mbox);
+ complete(&wkup_m3_sync);
+ break;
+ case M3_STATE_MSG_FOR_LP:
+ omap_mbox_msg_rx_flush(wkup_m3->mbox);
+ complete(&wkup_m3_sync);
+ break;
+ case M3_STATE_UNKNOWN:
+ pr_err("IRQ %d with WKUP_M3 in unknown state\n", irq);
+ omap_mbox_msg_rx_flush(wkup_m3->mbox);
+ return IRQ_NONE;
+ }
+
+ omap_ctrl_writel(0x0, AM33XX_CONTROL_M3_TXEV_EOI);
+ return IRQ_HANDLED;
+}
+
+static void am33xx_pm_firmware_cb(const struct firmware *fw, void *context)
+{
+ struct wkup_m3_context *wkup_m3_context = context;
+ struct platform_device *pdev = to_platform_device(wkup_m3_context->dev);
+ int ret = 0;
+
+ /* no firmware found */
+ if (!fw) {
+ dev_err(wkup_m3_context->dev, "request_firmware failed\n");
+ goto err;
+ }
+
+ memcpy((void *)wkup_m3_context->code, fw->data, fw->size);
+ pr_info("Copied the M3 firmware to UMEM\n");
+
+ wkup_m3->state = M3_STATE_RESET;
+
+ ret = omap_device_deassert_hardreset(pdev, "wkup_m3");
+ if (ret) {
+ pr_err("Could not deassert the reset for WKUP_M3\n");
+ goto err;
+ } else {
+#ifdef CONFIG_SUSPEND
+ suspend_set_ops(&am33xx_pm_ops);
+#endif
+ return;
+ }
+
+err:
+ omap_mbox_put(wkup_m3_context->mbox, &wkup_mbox_notifier);
+}
+
+static int wkup_m3_init(void)
+{
+ int irq, ret = 0;
+ struct resource *mem;
+ struct platform_device *pdev = to_platform_device(wkup_m3->dev);
+
+ omap_device_enable_hwmods(to_omap_device(pdev));
+
+ /* Reserve the MBOX for sending messages to M3 */
+ wkup_m3->mbox = omap_mbox_get("wkup_m3", &wkup_mbox_notifier);
+ if (IS_ERR(wkup_m3->mbox)) {
+ pr_err("Could not reserve mailbox for A8->M3 IPC\n");
+ ret = -ENODEV;
+ goto exit;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mem)
+ dev_err(wkup_m3->dev, "no memory resource\n");
+
+ wkup_m3->code = devm_request_and_ioremap(wkup_m3->dev, mem);
+ ret = devm_request_irq(wkup_m3->dev, irq, wkup_m3_txev_handler,
+ IRQF_DISABLED, "wkup_m3_txev", NULL);
+ if (ret) {
+ dev_err(wkup_m3->dev, "request_irq failed\n");
+ goto err;
+ }
+
+ pr_info("Trying to load am335x-pm-firmware.bin");
+
+ /* We don't want to delay boot */
+ request_firmware_nowait(THIS_MODULE, 0, "am335x-pm-firmware.bin",
+ wkup_m3->dev, GFP_KERNEL, wkup_m3,
+ am33xx_pm_firmware_cb);
+ return 0;
+
+err:
+ omap_mbox_put(wkup_m3->mbox, &wkup_mbox_notifier);
+exit:
+ return ret;
+}
+
+/*
+ * Push the minimal suspend-resume code to SRAM
+ */
+void am33xx_push_sram_idle(void)
+{
+ am33xx_do_wfi_sram = (void *)omap_sram_push
+ (am33xx_do_wfi, am33xx_do_wfi_sz);
+}
+
+static int __init am33xx_map_emif(void)
+{
+ am33xx_emif_base = ioremap(AM33XX_EMIF_BASE, SZ_32K);
+
+ if (!am33xx_emif_base)
+ return -ENOMEM;
+
+ return 0;
+}
+
+void __iomem *am33xx_get_emif_base(void)
+{
+ return am33xx_emif_base;
+}
+
+int __init am33xx_pm_init(void)
+{
+ int ret;
+
+ if (!soc_is_am33xx())
+ return -ENODEV;
+
+ pr_info("Power Management for AM33XX family\n");
+
+ wkup_m3 = kzalloc(sizeof(struct wkup_m3_context), GFP_KERNEL);
+ if (!wkup_m3) {
+ pr_err("Memory allocation failed\n");
+ return -ENOMEM;
+ }
+
+ ret = am33xx_map_emif();
+
+ (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
+
+ /* CEFUSE domain should be turned off post bootup */
+ cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
+ if (cefuse_pwrdm)
+ pwrdm_set_next_pwrst(cefuse_pwrdm, PWRDM_POWER_OFF);
+ else
+ pr_err("Failed to get cefuse_pwrdm\n");
+
+ gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
+ per_pwrdm = pwrdm_lookup("per_pwrdm");
+
+ gfx_l3_clkdm = clkdm_lookup("gfx_l3_clkdm");
+ gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
+
+ wkup_m3->dev = omap_device_get_by_hwmod_name("wkup_m3");
+
+ ret = wkup_m3_init();
+ if (ret)
+ pr_err("Could not initialise firmware loading\n");
+
+ return ret;
+}
diff --git a/arch/arm/mach-omap2/pm33xx.h b/arch/arm/mach-omap2/pm33xx.h
new file mode 100644
index 0000000..38f8ae7
--- /dev/null
+++ b/arch/arm/mach-omap2/pm33xx.h
@@ -0,0 +1,100 @@
+/*
+ * AM33XX Power Management Routines
+ *
+ * Copyright (C) 2012 Texas Instruments Inc.
+ * Vaibhav Bedia <vaibhav.bedia@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H
+#define __ARCH_ARM_MACH_OMAP2_PM33XX_H
+
+#ifndef __ASSEMBLER__
+struct wkup_m3_context {
+ struct device *dev;
+ struct firmware *firmware;
+ struct omap_mbox *mbox;
+ void __iomem *code;
+ int resume_addr;
+ int ipc_data1;
+ int ipc_data2;
+ int sleep_mode;
+ u8 state;
+};
+
+#ifdef CONFIG_SUSPEND
+static void am33xx_ipc_cmd(void);
+static void am33xx_m3_state_machine_reset(void);
+#else
+static inline void am33xx_ipc_cmd(void) {}
+static inline void am33xx_m3_state_machine_reset(void) {}
+#endif /* CONFIG_SUSPEND */
+
+extern void __iomem *am33xx_get_emif_base(void);
+int wkup_mbox_msg(struct notifier_block *self, unsigned long len, void *msg);
+#endif
+
+#define IPC_CMD_DS0 0x3
+#define IPC_CMD_RESET 0xe
+#define DS_IPC_DEFAULT 0xffffffff
+
+#define IPC_RESP_SHIFT 16
+#define IPC_RESP_MASK (0xffff << 16)
+
+#define M3_STATE_UNKNOWN 0
+#define M3_STATE_RESET 1
+#define M3_STATE_INITED 2
+#define M3_STATE_MSG_FOR_LP 3
+#define M3_STATE_MSG_FOR_RESET 4
+
+#define AM33XX_OCMC_END 0x40310000
+#define AM33XX_EMIF_BASE 0x4C000000
+
+/*
+ * This a subset of registers defined in drivers/memory/emif.h
+ * Move that to include/linux/?
+ */
+#define EMIF_MODULE_ID_AND_REVISION 0x0000
+#define EMIF_STATUS 0x0004
+#define EMIF_SDRAM_CONFIG 0x0008
+#define EMIF_SDRAM_CONFIG_2 0x000c
+#define EMIF_SDRAM_REFRESH_CONTROL 0x0010
+#define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014
+#define EMIF_SDRAM_TIMING_1 0x0018
+#define EMIF_SDRAM_TIMING_1_SHDW 0x001c
+#define EMIF_SDRAM_TIMING_2 0x0020
+#define EMIF_SDRAM_TIMING_2_SHDW 0x0024
+#define EMIF_SDRAM_TIMING_3 0x0028
+#define EMIF_SDRAM_TIMING_3_SHDW 0x002c
+#define EMIF_LPDDR2_NVM_TIMING 0x0030
+#define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034
+#define EMIF_POWER_MANAGEMENT_CONTROL 0x0038
+#define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c
+#define EMIF_PERFORMANCE_COUNTER_1 0x0080
+#define EMIF_PERFORMANCE_COUNTER_2 0x0084
+#define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088
+#define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c
+#define EMIF_PERFORMANCE_COUNTER_TIME 0x0090
+#define EMIF_MISC_REG 0x0094
+#define EMIF_DLL_CALIB_CTRL 0x0098
+#define EMIF_DLL_CALIB_CTRL_SHDW 0x009c
+#define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4
+#define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac
+#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4
+#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc
+#define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8
+#define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4
+#define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8
+#define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc
+#define EMIF_DDR_PHY_CTRL_1 0x00e4
+#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8
+
+#endif
diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
new file mode 100644
index 0000000..f7b34e5
--- /dev/null
+++ b/arch/arm/mach-omap2/sleep33xx.S
@@ -0,0 +1,571 @@
+/*
+ * Low level suspend code for AM33XX SoCs
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Bedia <vaibhav.bedia@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/linkage.h>
+#include <asm/memory.h>
+#include <asm/assembler.h>
+
+#include "cm33xx.h"
+#include "pm33xx.h"
+#include "prm33xx.h"
+#include "control.h"
+
+/* replicated define because linux/bitops.h cannot be included in assembly */
+#define BIT(nr) (1 << (nr))
+
+ .text
+ .align 3
+
+ .macro pll_bypass, name, clk_mode_addr, idlest_addr, pll_mode
+pll_bypass_\name:
+ ldr r0, \clk_mode_addr
+ ldr r1, [r0]
+ str r1, clk_mode_\pll_mode
+ bic r1, r1, #(7 << 0)
+ orr r1, r1, #0x5
+ str r1, [r0]
+ ldr r0, \idlest_addr
+wait_pll_bypass_\name:
+ ldr r1, [r0]
+ tst r1, #0x0
+ bne wait_pll_bypass_\name
+ .endm
+
+ .macro pll_lock, name, clk_mode_addr, idlest_addr, pll_mode
+pll_lock_\name:
+ ldr r0, \clk_mode_addr
+ ldr r1, clk_mode_\pll_mode
+ str r1, [r0]
+ and r1, r1, #0x7
+ cmp r1, #0x7
+ bne pll_mode_restored_\name
+ ldr r0, \idlest_addr
+wait_pll_lock_\name:
+ ldr r1, [r0]
+ ands r1, #0x1
+ beq wait_pll_lock_\name
+pll_mode_restored_\name:
+ nop
+ .endm
+
+ .macro ddr_self_refresh, num
+ddr_self_refresh_\num:
+ add r1, r0, #EMIF_POWER_MANAGEMENT_CONTROL
+ ldr r2, [r1]
+ orr r2, r2, #0xa0 @ a reasonable delay for entering SR
+ str r2, [r1, #0]
+ str r2, [r1, #4] @ write to shadow register also
+
+ ldr r2, ddr_start @ do a dummy access to DDR
+ ldr r3, [r2, #0]
+ ldr r3, [r1, #0]
+ orr r3, r3, #0x200 @ now set the LP MODE to Self-Refresh
+ str r3, [r1, #0]
+
+ mov r1, #0x1000 @ Give some time for system to enter SR
+wait_sr_\num:
+ subs r1, r1, #1
+ bne wait_sr_\num
+ .endm
+
+ .macro wait_sdram_config, num
+wait_sdram_config_\num:
+ mov r0, #0x100
+wait_sc_\num:
+ subs r0, r0 ,#1
+ bne wait_sc_\num
+ .endm
+
+ENTRY(am33xx_do_wfi)
+ stmfd sp!, {r4 - r11, lr} @ save registers on stack
+ /* Get the EMIF virtual address */
+ ldr r0, emif_addr_func
+ blx r0
+ /* Save it for later use */
+ str r0, emif_addr_virt
+
+ /* This ensures isb */
+ ldr r0, dcache_flush
+ blx r0
+
+ /* Same as v7_flush_icache_all - saving a branch */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
+
+ ldr r0, emif_addr_virt
+ /* Save EMIF configuration */
+ ldr r1, [r0, #EMIF_SDRAM_CONFIG]
+ str r1, emif_sdcfg_val
+ ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
+ str r1, emif_ref_ctrl_val
+ ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
+ str r1, emif_timing1_val
+ ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
+ str r1, emif_timing2_val
+ ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
+ str r1, emif_timing3_val
+ ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
+ str r1, emif_pmcr_val
+ ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
+ str r1, emif_pmcr_shdw_val
+ ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
+ str r1, emif_zqcfg_val
+ ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
+ str r1, emif_rd_lat_val
+
+ /* Ensure that all the writes to DDR leave the A8 */
+ dsb
+ dmb
+ isb
+
+ ddr_self_refresh 1
+
+ /* Disable EMIF at this point */
+ ldr r1, virt_emif_clkctrl
+ ldr r2, [r1]
+ bic r2, r2, #(3 << 0)
+ str r2, [r1]
+
+ ldr r1, virt_emif_clkctrl
+wait_emif_disable:
+ ldr r2, [r1]
+ ldr r3, module_disabled_val
+ cmp r2, r3
+ bne wait_emif_disable
+
+ /*
+ * For the MPU WFI to be registered as an interrupt
+ * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set
+ * to DISABLED
+ */
+ ldr r1, virt_mpu_clkctrl
+ ldr r2, [r1]
+ bic r2, r2, #(3 << 0)
+ str r2, [r1]
+
+ /* DDR3 reset override and mDDR mode selection */
+ ldr r0, virt_ddr_io_ctrl
+ mov r1, #(0x9 << 28)
+ str r1, [r0]
+
+ /* Weak pull down for DQ, DM */
+ ldr r1, virt_ddr_data0_ioctrl
+ ldr r2, susp_io_pull_data
+ str r2, [r1]
+
+ ldr r1, virt_ddr_data1_ioctrl
+ ldr r2, susp_io_pull_data
+ str r2, [r1]
+
+ /* Disable VTP */
+ ldr r1, virt_ddr_vtp_ctrl
+ ldr r2, susp_vtp_ctrl_val
+ str r2, [r1]
+
+ /* Enable SRAM LDO ret mode */
+ ldr r0, virt_sram_ldo_addr
+ ldr r1, [r0]
+ orr r1, #1
+ str r1, [r0]
+
+put_pll_bypass:
+ /* Put the PLLs in bypass mode */
+ pll_bypass core, virt_core_clk_mode, virt_core_idlest, core_val
+ pll_bypass ddr, virt_ddr_clk_mode, virt_ddr_idlest, ddr_val
+ pll_bypass disp, virt_disp_clk_mode, virt_disp_idlest, disp_val
+ pll_bypass per, virt_per_clk_mode, virt_per_idlest, per_val
+ pll_bypass mpu, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
+
+ dsb
+ dmb
+ isb
+
+ wfi
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /* We come here in case of an abort due to a late interrupt */
+
+ /* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */
+ ldr r1, virt_mpu_clkctrl
+ mov r2, #0x2
+ str r2, [r1]
+
+ /* Relock the PLLs */
+ pll_lock mpu_abt, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
+ pll_lock per_abt, virt_per_clk_mode, virt_per_idlest, per_val
+ pll_lock disp_abt, virt_disp_clk_mode, virt_disp_idlest, disp_val
+ pll_lock ddr_abt, virt_ddr_clk_mode, virt_ddr_idlest, ddr_val
+ pll_lock core_abt, virt_core_clk_mode, virt_core_idlest, core_val
+
+ /* Disable SRAM LDO ret mode */
+ ldr r0, virt_sram_ldo_addr
+ ldr r1, [r0]
+ bic r1, #1
+ str r1, [r0]
+
+ /* Restore the pull for DQ, DM */
+ ldr r1, virt_ddr_data0_ioctrl
+ ldr r2, resume_io_pull_data
+ str r2, [r1]
+
+ ldr r1, virt_ddr_data1_ioctrl
+ ldr r2, resume_io_pull_data
+ str r2, [r1]
+
+ /* Enable EMIF */
+ ldr r1, virt_emif_clkctrl
+ mov r2, #0x2
+ str r2, [r1]
+wait_emif_enable:
+ ldr r3, [r1]
+ cmp r2, r3
+ bne wait_emif_enable
+
+ /* Enable VTP */
+config_vtp_abt:
+ ldr r0, virt_ddr_vtp_ctrl
+ ldr r1, [r0]
+ mov r2, #0x0 @ clear the register
+ str r2, [r0]
+ mov r2, #0x6 @ write the filter value
+ str r2, [r0]
+
+ ldr r1, [r0]
+ ldr r2, vtp_enable @ set the enable bit
+ orr r2, r2, r1
+ str r2, [r0]
+
+ ldr r1, [r0] @ toggle the CLRZ bit
+ bic r1, #1
+ str r1, [r0]
+
+ ldr r1, [r0]
+ orr r1, #1
+ str r1, [r0]
+
+poll_vtp_ready_abt:
+ ldr r1, [r0] @ poll for VTP ready
+ tst r1, #(1 << 5)
+ beq poll_vtp_ready_abt
+
+ /* DDR3 reset override and mDDR mode clear */
+ ldr r0, virt_ddr_io_ctrl
+ mov r1, #0
+ str r1, [r0]
+
+emif_self_refresh_dis:
+ /* Disable EMIF self-refresh */
+ ldr r0, emif_addr_virt
+ add r0, r0, #EMIF_POWER_MANAGEMENT_CONTROL
+ ldr r1, [r0]
+ bic r1, r1, #(0x7 << 8)
+ str r1, [r0]
+ str r1, [r0, #4]
+
+ /*
+ * A write to SDRAM CONFIG register triggers
+ * an init sequence and hence it must be done
+ * at the end
+ */
+ ldr r0, emif_addr_virt
+ add r0, r0, #EMIF_SDRAM_CONFIG
+ ldr r4, emif_sdcfg_val
+ str r4, [r0]
+
+ mov r0, #0x1000
+wait_abt:
+ subs r0, r0, #1
+ bne wait_abt
+
+ /* Let the suspend code know about the abort */
+ mov r0, #1
+ ldmfd sp!, {r4 - r11, pc} @ restore regs and return
+ENDPROC(am33xx_do_wfi)
+
+ .align
+ENTRY(am33xx_resume_offset)
+ .word . - am33xx_do_wfi
+
+ENTRY(am33xx_resume_from_deep_sleep)
+ /* Take the PLLs out of LP_BYPASS */
+ pll_lock mpu, phys_mpu_clk_mode, phys_mpu_idlest, mpu_val
+ pll_lock per, phys_per_clk_mode, phys_per_idlest, per_val
+ pll_lock disp, phys_disp_clk_mode, phys_disp_idlest, disp_val
+ pll_lock ddr, phys_ddr_clk_mode, phys_ddr_idlest, ddr_val
+ pll_lock core, phys_core_clk_mode, phys_core_idlest, core_val
+
+ /* Disable SRAM LDO ret mode */
+ ldr r0, phys_sram_ldo_addr
+ ldr r1, [r0]
+ bic r1, #1
+ str r1, [r0]
+
+ /* Restore the pull for DQ, DM */
+ ldr r1, phys_ddr_data0_ioctrl
+ ldr r2, resume_io_pull_data
+ str r2, [r1]
+
+ ldr r1, phys_ddr_data1_ioctrl
+ ldr r2, resume_io_pull_data
+ str r2, [r1]
+
+config_vtp:
+ ldr r0, phys_ddr_vtp_ctrl
+ ldr r1, [r0]
+ mov r2, #0x0 @ clear the register
+ str r2, [r0]
+ mov r2, #0x6 @ write the filter value
+ str r2, [r0]
+
+ ldr r1, [r0]
+ ldr r2, vtp_enable @ set the enable bit
+ orr r2, r2, r1
+ str r2, [r0]
+
+ ldr r1, [r0] @ toggle the CLRZ bit
+ bic r1, #1
+ str r1, [r0]
+
+ ldr r1, [r0]
+ orr r1, #1
+ str r1, [r0]
+
+poll_vtp_ready:
+ ldr r1, [r0] @ poll for VTP ready
+ tst r1, #(1 << 5)
+ beq poll_vtp_ready
+
+ /* DDR3 reset override and mDDR mode clear */
+ ldr r0, phys_ddr_io_ctrl
+ mov r1, #0
+ str r1, [r0]
+
+config_emif_timings:
+ ldr r3, emif_phys_addr
+ ldr r4, emif_rd_lat_val
+ str r4, [r3, #EMIF_DDR_PHY_CTRL_1]
+ str r4, [r3, #EMIF_DDR_PHY_CTRL_1_SHDW]
+ ldr r4, emif_timing1_val
+ str r4, [r3, #EMIF_SDRAM_TIMING_1]
+ str r4, [r3, #EMIF_SDRAM_TIMING_1_SHDW]
+ ldr r4, emif_timing2_val
+ str r4, [r3, #EMIF_SDRAM_TIMING_2]
+ str r4, [r3, #EMIF_SDRAM_TIMING_2_SHDW]
+ ldr r4, emif_timing3_val
+ str r4, [r3, #EMIF_SDRAM_TIMING_3]
+ str r4, [r3, #EMIF_SDRAM_TIMING_3_SHDW]
+ ldr r4, emif_ref_ctrl_val
+ str r4, [r3, #EMIF_SDRAM_REFRESH_CONTROL]
+ str r4, [r3, #EMIF_SDRAM_REFRESH_CTRL_SHDW]
+ ldr r4, emif_pmcr_val
+ str r4, [r3, #EMIF_POWER_MANAGEMENT_CONTROL]
+ ldr r4, emif_pmcr_shdw_val
+ str r4, [r3, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
+
+ /*
+ * A write to SDRAM CONFIG register triggers
+ * an init sequence and hence it must be done
+ *@the end
+ */
+ ldr r4, emif_sdcfg_val
+ str r4, [r3, #EMIF_SDRAM_CONFIG]
+
+ /* Back from la-la-land. Kill some time for sanity to settle in */
+ mov r0, #0x1000
+wait_resume:
+ subs r0, r0, #1
+ bne wait_resume
+
+ /* We are back. Branch to the common CPU resume routine */
+ mov r0, #0
+ ldr pc, resume_addr
+ENDPROC(am33xx_resume_from_deep_sleep)
+
+
+/*
+ * Local variables
+ */
+ .align
+resume_addr:
+ .word cpu_resume - PAGE_OFFSET + 0x80000000
+dcache_flush:
+ .word v7_flush_dcache_all
+emif_addr_func:
+ .word am33xx_get_emif_base
+ddr_start:
+ .word PAGE_OFFSET
+emif_phys_addr:
+ .word AM33XX_EMIF_BASE
+virt_mpu_idlest:
+ .word AM33XX_CM_IDLEST_DPLL_MPU
+virt_mpu_clk_mode:
+ .word AM33XX_CM_CLKMODE_DPLL_MPU
+phys_mpu_clk_mode:
+ .word (AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + \
+ AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET)
+phys_mpu_idlest:
+ .word (AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + \
+ AM33XX_CM_IDLEST_DPLL_MPU_OFFSET)
+virt_core_idlest:
+ .word AM33XX_CM_IDLEST_DPLL_CORE
+virt_core_clk_mode:
+ .word AM33XX_CM_CLKMODE_DPLL_CORE
+phys_core_clk_mode:
+ .word (AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + \
+ AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET)
+phys_core_idlest:
+ .word (AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + \
+ AM33XX_CM_IDLEST_DPLL_CORE_OFFSET)
+virt_per_idlest:
+ .word AM33XX_CM_IDLEST_DPLL_PER
+virt_per_clk_mode:
+ .word AM33XX_CM_CLKMODE_DPLL_PER
+phys_per_clk_mode:
+ .word (AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + \
+ AM33XX_CM_CLKMODE_DPLL_PER_OFFSET)
+phys_per_idlest:
+ .word (AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + \
+ AM33XX_CM_IDLEST_DPLL_PER_OFFSET)
+virt_disp_idlest:
+ .word AM33XX_CM_IDLEST_DPLL_DISP
+virt_disp_clk_mode:
+ .word AM33XX_CM_CLKMODE_DPLL_DISP
+phys_disp_clk_mode:
+ .word (AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + \
+ AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET)
+phys_disp_idlest:
+ .word (AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + \
+ AM33XX_CM_IDLEST_DPLL_DISP_OFFSET)
+virt_ddr_idlest:
+ .word AM33XX_CM_IDLEST_DPLL_DDR
+virt_ddr_clk_mode:
+ .word AM33XX_CM_CLKMODE_DPLL_DDR
+phys_ddr_clk_mode:
+ .word (AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + \
+ AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET)
+phys_ddr_idlest:
+ .word (AM33XX_CM_BASE + AM33XX_CM_WKUP_MOD + \
+ AM33XX_CM_IDLEST_DPLL_DDR_OFFSET)
+virt_sram_ldo_addr:
+ .word AM33XX_PRM_LDO_SRAM_MPU_CTRL
+phys_sram_ldo_addr:
+ .word (AM33XX_PRM_BASE + AM33XX_PRM_DEVICE_MOD + \
+ AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET)
+virt_mpu_clkctrl:
+ .word AM33XX_CM_MPU_MPU_CLKCTRL
+virt_emif_clkctrl:
+ .word AM33XX_CM_PER_EMIF_CLKCTRL
+phys_emif_clkctrl:
+ .word (AM33XX_CM_BASE + AM33XX_CM_PER_MOD + \
+ AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET)
+module_disabled_val:
+ .word 0x30000
+
+/* DDR related defines */
+virt_ddr_io_ctrl:
+ .word AM33XX_CTRL_REGADDR(AM33XX_DDR_IO_CTRL)
+phys_ddr_io_ctrl:
+ .word AM33XX_CTRL_BASE + AM33XX_DDR_IO_CTRL
+virt_ddr_vtp_ctrl:
+ .word AM33XX_CTRL_REGADDR(AM33XX_VTP0_CTRL_REG)
+phys_ddr_vtp_ctrl:
+ .word AM33XX_CTRL_BASE + AM33XX_VTP0_CTRL_REG
+virt_ddr_cmd0_ioctrl:
+ .word AM33XX_CTRL_REGADDR(AM33XX_DDR_CMD0_IOCTRL)
+phys_ddr_cmd0_ioctrl:
+ .word AM33XX_CTRL_BASE + AM33XX_DDR_CMD0_IOCTRL
+virt_ddr_cmd1_ioctrl:
+ .word AM33XX_CTRL_REGADDR(AM33XX_DDR_CMD1_IOCTRL)
+phys_ddr_cmd1_ioctrl:
+ .word AM33XX_CTRL_BASE + AM33XX_DDR_CMD1_IOCTRL
+virt_ddr_cmd2_ioctrl:
+ .word AM33XX_CTRL_REGADDR(AM33XX_DDR_CMD2_IOCTRL)
+phys_ddr_cmd2_ioctrl:
+ .word AM33XX_CTRL_BASE + AM33XX_DDR_CMD2_IOCTRL
+virt_ddr_data0_ioctrl:
+ .word AM33XX_CTRL_REGADDR(AM33XX_DDR_DATA0_IOCTRL)
+phys_ddr_data0_ioctrl:
+ .word AM33XX_CTRL_BASE + AM33XX_DDR_DATA0_IOCTRL
+virt_ddr_data1_ioctrl:
+ .word AM33XX_CTRL_REGADDR(AM33XX_DDR_DATA1_IOCTRL)
+phys_ddr_data1_ioctrl:
+ .word AM33XX_CTRL_BASE + AM33XX_DDR_DATA1_IOCTRL
+vtp_enable:
+ .word AM33XX_VTP_CTRL_ENABLE
+
+/* Values recommended by the HW team */
+susp_io_pull_data:
+ .word 0x3FF00003
+susp_io_pull_cmd1:
+ .word 0xFFE0018B
+susp_io_pull_cmd2:
+ .word 0xFFA0098B
+resume_io_pull_data:
+ .word 0x18B
+resume_io_pull_cmd:
+ .word 0x18B
+susp_vtp_ctrl_val:
+ .word 0x10117
+
+/* Placeholder for storing EMIF configuration */
+emif_addr_virt:
+ .word 0xDEADBEEF
+emif_rd_lat_val:
+ .word 0xDEADBEEF
+emif_timing1_val:
+ .word 0xDEADBEEF
+emif_timing2_val:
+ .word 0xDEADBEEF
+emif_timing3_val:
+ .word 0xDEADBEEF
+emif_sdcfg_val:
+ .word 0xDEADBEEF
+emif_ref_ctrl_val:
+ .word 0xDEADBEEF
+emif_zqcfg_val:
+ .word 0xDEADBEEF
+emif_pmcr_val:
+ .word 0xDEADBEEF
+emif_pmcr_shdw_val:
+ .word 0xDEADBEEF
+
+/* Placeholder for storing PLL mode */
+clk_mode_mpu_val:
+ .word 0xDEADBEEF
+clk_mode_per_val:
+ .word 0xDEADBEEF
+clk_mode_disp_val:
+ .word 0xDEADBEEF
+clk_mode_ddr_val:
+ .word 0xDEADBEEF
+clk_mode_core_val:
+ .word 0xDEADBEEF
+
+ .align 3
+ENTRY(am33xx_do_wfi_sz)
+ .word . - am33xx_do_wfi
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 70dcc22..c96a9d1 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -182,7 +182,7 @@ static void __init omap_map_sram(void)
omap_sram_size -= SZ_16K;
}
#endif
- if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx() || soc_is_am33xx()) {
/*
* SRAM must be marked as non-cached on OMAP3 since the
* CORE DPLL M2 divider change code (in SRAM) runs with the
@@ -381,10 +381,18 @@ static inline int omap34xx_sram_init(void)
}
#endif /* CONFIG_ARCH_OMAP3 */
+#ifdef CONFIG_SOC_AM33XX
static inline int am33xx_sram_init(void)
{
+ am33xx_push_sram_idle();
return 0;
}
+#else
+static inline int am33xx_sram_init(void)
+{
+ return 0;
+}
+#endif
int __init omap_sram_init(void)
{
diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h
index cefda2e..4790340 100644
--- a/arch/arm/plat-omap/sram.h
+++ b/arch/arm/plat-omap/sram.h
@@ -85,8 +85,10 @@ extern unsigned long omap3_sram_configure_core_dpll_sz;
#ifdef CONFIG_PM
extern void omap_push_sram_idle(void);
+extern void am33xx_push_sram_idle(void);
#else
static inline void omap_push_sram_idle(void) {}
+static inline void am33xx_push_sram_idle(void) {}
#endif /* CONFIG_PM */
#endif /* __ASSEMBLY__ */
--
1.7.0.4
^ permalink raw reply related
* [PATCH v2 2/5] ARM: gic: remove direct use of gic_raise_softirq
From: Srinidhi Kasagar @ 2012-11-02 12:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351695517-5636-3-git-send-email-robherring2@gmail.com>
Rob,
On Wed, Oct 31, 2012 at 15:58:34 +0100, Rob Herring wrote:
> From: Rob Herring <rob.herring@calxeda.com>
>
> In preparation of moving gic code to drivers/irqchip, remove the direct
> platform dependencies on gic_raise_softirq. Move the setup of
> smp_cross_call into the gic code. Now that all platforms are using IPI#0
> for core wakeup, create a common wakeup ipi function.
>
> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: David Brown <davidb@codeaurora.org>
> Cc: Daniel Walker <dwalker@fifo99.com>
> Cc: Bryan Huntsman <bryanh@codeaurora.org>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Paul Mundt <lethal@linux-sh.org>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Shiraz Hashim <shiraz.hashim@st.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
[...]
> static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
> diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
> index 3db7782..774e527 100644
> --- a/arch/arm/mach-ux500/platsmp.c
> +++ b/arch/arm/mach-ux500/platsmp.c
> @@ -155,8 +155,6 @@ static void __init ux500_smp_init_cpus(void)
>
> for (i = 0; i < ncores; i++)
> set_cpu_possible(i, true);
> -
> - set_smp_cross_call(gic_raise_softirq);
The ux500 changes looks ok too..
However would you mind re-spinning your series on top of the below patch?
>From 6a574702ad6c45819c182a2c2bbd70d3ba7a859f Mon Sep 17 00:00:00 2001
From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Date: Fri, 2 Nov 2012 12:45:40 +0530
Subject: [PATCH] ARM : mach-ux500: use SGI0 to wake up the other core
The commit 7d28e3eaa1a8e951251b942e7220f97114bd73b9
("ARM: ux500: wake secondary cpu via resched") makes use
of schedule IPI to wake up the secondary core which seems
incorrect. Rather use SGI0.
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
---
arch/arm/mach-ux500/platsmp.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index da1d5ad..3f996f2 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -97,7 +97,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
write_pen_release(cpu_logical_map(cpu));
- smp_send_reschedule(cpu);
+ gic_raise_softirq(cpumask_of(cpu), 0);
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
--
1.7.2.dirty
^ permalink raw reply related
* [PATCH 01/15] ARM: clps711x: Load serial driver from boards
From: Alexander Shiyan @ 2012-11-02 12:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121101122731.GS21164@n2100.arm.linux.org.uk>
On Thu, 1 Nov 2012 12:27:31 +0000
Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:
> BOn Thu, Nov 01, 2012 at 01:26:31PM +0400, Alexander Shiyan wrote:
> > MACHINE_START(AUTCPU12, "autronix autcpu12")
> > /* Maintainer: Thomas Gleixner */
> > .atag_offset = 0x20000,
> > - .init_machine = autcpu12_init,
> > .map_io = autcpu12_map_io,
> > + .init_machine = autcpu12_init,
> > .init_irq = clps711x_init_irq,
> > - .timer = &clps711x_timer,
> > .restart = clps711x_restart,
> > + .timer = &clps711x_timer,
> > MACHINE_END
>
> NAK. If you're going to sort them, arrange them in the same order as
> in the structure declaration in mach/arch.h. That's the order in which
> the functions will be called.
>
> IOW, changing the order of .timer to be after .restart is wrong, .restart
> should be the last. .timer should be immediately before .init_machine.
> .init_irq should be immediately before .timer.
It's just sort by functionality and does not affect on operation.
Original sort I will return in the next patch after applying it.
Please comment on the rest of the patches in this series.
Thanks.
--
Alexander Shiyan <shc_work@mail.ru>
^ permalink raw reply
* [PATCH] ARM: S3C64XX: Fix up IRQ mapping for balblair on Cragganmore
From: Dimitris Papastamos @ 2012-11-02 13:01 UTC (permalink / raw)
To: linux-arm-kernel
We are using S3C_EINT(4) instead of S3C_EINT(5).
Change-Id: I84e77fd75d59c6b8fecbcb11e81dc78dbf07f156
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
---
arch/arm/mach-s3c64xx/mach-crag6410-module.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 4744c42..c6d8dba 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -60,7 +60,7 @@ static struct spi_board_info balblair_devs[] = {
.bus_num = 0,
.chip_select = 0,
.mode = SPI_MODE_0,
- .irq = S3C_EINT(5),
+ .irq = S3C_EINT(4),
.controller_data = &wm0010_spi_csinfo,
.platform_data = &wm0010_pdata,
},
--
1.8.0
^ permalink raw reply related
* [PATCH] ARM: S3C64XX: Fix up IRQ mapping for balblair on Cragganmore
From: Dimitris Papastamos @ 2012-11-02 13:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5093B962.1060903@mvista.com>
On Fri, Nov 02, 2012 at 04:15:30PM +0400, Sergei Shtylyov wrote:
> Hello.
>
> On 02-11-2012 14:38, Dimitris Papastamos wrote:
>
>> We are using S3C_EINT(4) instead of S3C_EINT(5).
>
>> Change-Id: Ia197069ddc736813f2711c763469eaf655ea58ac
>
> Remove this line please -- it has no place in the upstream patch.
>
>> Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
>
> WBR, Sergei
>
Oops, thanks for catching that.
^ permalink raw reply
* [PATCH 01/15] ARM: clps711x: Load serial driver from boards
From: Russell King - ARM Linux @ 2012-11-02 13:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121102165040.09be40cce1feb5845d7e51b5@mail.ru>
On Fri, Nov 02, 2012 at 04:50:40PM +0400, Alexander Shiyan wrote:
> On Thu, 1 Nov 2012 12:27:31 +0000
> Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:
>
> > BOn Thu, Nov 01, 2012 at 01:26:31PM +0400, Alexander Shiyan wrote:
> > > MACHINE_START(AUTCPU12, "autronix autcpu12")
> > > /* Maintainer: Thomas Gleixner */
> > > .atag_offset = 0x20000,
> > > - .init_machine = autcpu12_init,
> > > .map_io = autcpu12_map_io,
> > > + .init_machine = autcpu12_init,
> > > .init_irq = clps711x_init_irq,
> > > - .timer = &clps711x_timer,
> > > .restart = clps711x_restart,
> > > + .timer = &clps711x_timer,
> > > MACHINE_END
> >
> > NAK. If you're going to sort them, arrange them in the same order as
> > in the structure declaration in mach/arch.h. That's the order in which
> > the functions will be called.
> >
> > IOW, changing the order of .timer to be after .restart is wrong, .restart
> > should be the last. .timer should be immediately before .init_machine.
> > .init_irq should be immediately before .timer.
>
> It's just sort by functionality and does not affect on operation.
Please don't dream up different sorting criteral for structures; it's a
_real_ pain if I have to go through all the platforms and change something
(which I normally do in a scripted fashion) to have each sub-architecture
choosing to do things differently.
> Original sort I will return in the next patch after applying it.
The original wasn't actually correct. As you're touching all of these,
it would be a good time for _you_ to fix it. Please look at
asm/mach/arch.h and ensure that all initializer fields are in the same
order as those found in the structure declaration in mach-clps711x.
Thanks.
^ permalink raw reply
* [PATCH v2] ARM: S3C64XX: Fix up IRQ mapping for balblair on Cragganmore
From: Dimitris Papastamos @ 2012-11-02 13:04 UTC (permalink / raw)
To: linux-arm-kernel
We are using S3C_EINT(4) instead of S3C_EINT(5).
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
---
arch/arm/mach-s3c64xx/mach-crag6410-module.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 4744c42..c6d8dba 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -60,7 +60,7 @@ static struct spi_board_info balblair_devs[] = {
.bus_num = 0,
.chip_select = 0,
.mode = SPI_MODE_0,
- .irq = S3C_EINT(5),
+ .irq = S3C_EINT(4),
.controller_data = &wm0010_spi_csinfo,
.platform_data = &wm0010_pdata,
},
--
1.8.0
^ permalink raw reply related
* [PATCH 15/15] ARM: OMAP2+: AM33XX: Basic suspend resume support
From: Bedia, Vaibhav @ 2012-11-02 13:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-16-git-send-email-vaibhav.bedia@ti.com>
On Fri, Nov 02, 2012 at 18:02:46, Bedia, Vaibhav wrote:
[...]
> +int wkup_mbox_msg(struct notifier_block *self, unsigned long len, void *msg)
> +{
> + return 0;
> +}
This should have been static. Will change in the next version.
^ permalink raw reply
* [PATCHv2 1/6] arch: Change defconfigs to point to g_mass_storage.
From: Michal Nazarewicz @ 2012-11-02 13:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1351715302.v2.git.mina86@mina86.com>
From: Michal Nazarewicz <mina86@mina86.com>
The File-backed Storage Gadget (g_file_storage) is being removed, since
it has been replaced by Mass Storage Gadget (g_mass_storage). This commit
changes defconfigs point to the new gadget.
Signed-off-by: Michal Nazarewicz <mina86@mina86.com>
---
arch/arm/configs/afeb9260_defconfig | 2 +-
arch/arm/configs/at91sam9260_defconfig | 2 +-
arch/arm/configs/at91sam9261_defconfig | 2 +-
arch/arm/configs/at91sam9263_defconfig | 2 +-
arch/arm/configs/at91sam9g20_defconfig | 2 +-
arch/arm/configs/corgi_defconfig | 2 +-
arch/arm/configs/davinci_all_defconfig | 2 +-
arch/arm/configs/h7202_defconfig | 3 +--
arch/arm/configs/magician_defconfig | 2 +-
arch/arm/configs/mini2440_defconfig | 2 +-
arch/arm/configs/omap1_defconfig | 3 +--
arch/arm/configs/prima2_defconfig | 1 -
arch/arm/configs/spitz_defconfig | 2 +-
arch/arm/configs/stamp9g20_defconfig | 2 +-
arch/arm/configs/viper_defconfig | 2 +-
arch/arm/configs/zeus_defconfig | 2 +-
arch/avr32/configs/atngw100_defconfig | 2 +-
arch/avr32/configs/atngw100_evklcd100_defconfig | 2 +-
arch/avr32/configs/atngw100_evklcd101_defconfig | 2 +-
arch/avr32/configs/atngw100_mrmt_defconfig | 2 +-
arch/avr32/configs/atngw100mkii_defconfig | 2 +-
.../avr32/configs/atngw100mkii_evklcd100_defconfig | 2 +-
.../avr32/configs/atngw100mkii_evklcd101_defconfig | 2 +-
arch/avr32/configs/atstk1002_defconfig | 2 +-
arch/avr32/configs/atstk1003_defconfig | 2 +-
arch/avr32/configs/atstk1004_defconfig | 2 +-
arch/avr32/configs/atstk1006_defconfig | 2 +-
arch/avr32/configs/favr-32_defconfig | 2 +-
arch/avr32/configs/hammerhead_defconfig | 2 +-
arch/blackfin/configs/CM-BF527_defconfig | 2 +-
arch/blackfin/configs/CM-BF548_defconfig | 2 +-
arch/blackfin/configs/CM-BF561_defconfig | 2 +-
arch/mips/configs/bcm47xx_defconfig | 2 +-
arch/mips/configs/mtx1_defconfig | 2 +-
arch/sh/configs/ecovec24_defconfig | 2 +-
arch/sh/configs/se7724_defconfig | 2 +-
37 files changed, 35 insertions(+), 39 deletions(-)
diff --git a/arch/arm/configs/afeb9260_defconfig b/arch/arm/configs/afeb9260_defconfig
index c285a9d..a8dbc1e 100644
--- a/arch/arm/configs/afeb9260_defconfig
+++ b/arch/arm/configs/afeb9260_defconfig
@@ -79,7 +79,7 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_ZERO=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_RTC_CLASS=y
CONFIG_RTC_DEBUG=y
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig
index 505b376..0ea5d2c 100644
--- a/arch/arm/configs/at91sam9260_defconfig
+++ b/arch/arm/configs/at91sam9260_defconfig
@@ -75,7 +75,7 @@ CONFIG_USB_STORAGE_DEBUG=y
CONFIG_USB_GADGET=y
CONFIG_USB_ZERO=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AT91SAM9=y
diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_defconfig
index 1e8712e..c87beb9 100644
--- a/arch/arm/configs/at91sam9261_defconfig
+++ b/arch/arm/configs/at91sam9261_defconfig
@@ -125,7 +125,7 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_MMC=y
CONFIG_MMC_ATMELMCI=m
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index d2050ca..c5212f4 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -133,7 +133,7 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_MMC=y
CONFIG_SDIO_UART=m
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig
index e1b0e80..3b18810 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9g20_defconfig
@@ -96,7 +96,7 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_ZERO=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_MMC=y
CONFIG_MMC_ATMELMCI=m
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index 4b8a25d..1fd1d1d 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -218,7 +218,7 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_MMC=y
CONFIG_MMC_PXA=y
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 67b5abb6..4ea7c95 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -144,7 +144,7 @@ CONFIG_USB_GADGET_DEBUG_FS=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
diff --git a/arch/arm/configs/h7202_defconfig b/arch/arm/configs/h7202_defconfig
index 69405a7..e16d3f3 100644
--- a/arch/arm/configs/h7202_defconfig
+++ b/arch/arm/configs/h7202_defconfig
@@ -34,8 +34,7 @@ CONFIG_FB_MODE_HELPERS=y
CONFIG_USB_GADGET=m
CONFIG_USB_ZERO=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_FILE_STORAGE_TEST=y
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_EXT2_FS=y
CONFIG_TMPFS=y
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
index a691ef4..557dd29 100644
--- a/arch/arm/configs/magician_defconfig
+++ b/arch/arm/configs/magician_defconfig
@@ -136,7 +136,7 @@ CONFIG_USB_PXA27X=y
CONFIG_USB_ETH=m
# CONFIG_USB_ETH_RNDIS is not set
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_GPIO_VBUS=y
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 00630e6..a07948a 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -240,7 +240,7 @@ CONFIG_USB_GADGET_S3C2410=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index dde2a1a..42eab9a 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -214,8 +214,7 @@ CONFIG_USB_TEST=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETH=m
# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_FILE_STORAGE_TEST=y
+CONFIG_USB_MASS_STORAGE=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
index 807d4e2..6a936c7 100644
--- a/arch/arm/configs/prima2_defconfig
+++ b/arch/arm/configs/prima2_defconfig
@@ -37,7 +37,6 @@ CONFIG_SPI_SIRF=y
CONFIG_SPI_SPIDEV=y
# CONFIG_HWMON is not set
CONFIG_USB_GADGET=y
-CONFIG_USB_FILE_STORAGE=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index df77931..2e0419d 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -214,7 +214,7 @@ CONFIG_USB_GADGET_DUMMY_HCD=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_MMC=y
CONFIG_MMC_PXA=y
diff --git a/arch/arm/configs/stamp9g20_defconfig b/arch/arm/configs/stamp9g20_defconfig
index 52f1488..b845f55 100644
--- a/arch/arm/configs/stamp9g20_defconfig
+++ b/arch/arm/configs/stamp9g20_defconfig
@@ -97,7 +97,7 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=m
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_MMC=y
CONFIG_MMC_ATMELMCI=y
diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig
index 1d01ddd..d36e0d3 100644
--- a/arch/arm/configs/viper_defconfig
+++ b/arch/arm/configs/viper_defconfig
@@ -139,7 +139,7 @@ CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_GADGET=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_PRINTER=m
CONFIG_RTC_CLASS=y
diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig
index 547a3c1..731d4f9 100644
--- a/arch/arm/configs/zeus_defconfig
+++ b/arch/arm/configs/zeus_defconfig
@@ -143,7 +143,7 @@ CONFIG_USB_GADGET=m
CONFIG_USB_PXA27X=y
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_PRINTER=m
CONFIG_MMC=y
diff --git a/arch/avr32/configs/atngw100_defconfig b/arch/avr32/configs/atngw100_defconfig
index a06bfcc..f4025db 100644
--- a/arch/avr32/configs/atngw100_defconfig
+++ b/arch/avr32/configs/atngw100_defconfig
@@ -109,7 +109,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=350
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
diff --git a/arch/avr32/configs/atngw100_evklcd100_defconfig b/arch/avr32/configs/atngw100_evklcd100_defconfig
index d8f1fe8..c76a49b 100644
--- a/arch/avr32/configs/atngw100_evklcd100_defconfig
+++ b/arch/avr32/configs/atngw100_evklcd100_defconfig
@@ -125,7 +125,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=350
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
diff --git a/arch/avr32/configs/atngw100_evklcd101_defconfig b/arch/avr32/configs/atngw100_evklcd101_defconfig
index d4c5b19..2d8ab08 100644
--- a/arch/avr32/configs/atngw100_evklcd101_defconfig
+++ b/arch/avr32/configs/atngw100_evklcd101_defconfig
@@ -124,7 +124,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=350
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
diff --git a/arch/avr32/configs/atngw100_mrmt_defconfig b/arch/avr32/configs/atngw100_mrmt_defconfig
index 77ca4f9..b189e0c 100644
--- a/arch/avr32/configs/atngw100_mrmt_defconfig
+++ b/arch/avr32/configs/atngw100_mrmt_defconfig
@@ -99,7 +99,7 @@ CONFIG_SND_ATMEL_AC97C=m
# CONFIG_SND_SPI is not set
CONFIG_USB_GADGET=m
CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_MMC=y
CONFIG_MMC_ATMELMCI=y
diff --git a/arch/avr32/configs/atngw100mkii_defconfig b/arch/avr32/configs/atngw100mkii_defconfig
index 6e0dca4..2e4de42 100644
--- a/arch/avr32/configs/atngw100mkii_defconfig
+++ b/arch/avr32/configs/atngw100mkii_defconfig
@@ -111,7 +111,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=350
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
diff --git a/arch/avr32/configs/atngw100mkii_evklcd100_defconfig b/arch/avr32/configs/atngw100mkii_evklcd100_defconfig
index 7f2a344..fad3cd2 100644
--- a/arch/avr32/configs/atngw100mkii_evklcd100_defconfig
+++ b/arch/avr32/configs/atngw100mkii_evklcd100_defconfig
@@ -128,7 +128,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=350
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
diff --git a/arch/avr32/configs/atngw100mkii_evklcd101_defconfig b/arch/avr32/configs/atngw100mkii_evklcd101_defconfig
index 085eeba..2998623 100644
--- a/arch/avr32/configs/atngw100mkii_evklcd101_defconfig
+++ b/arch/avr32/configs/atngw100mkii_evklcd101_defconfig
@@ -127,7 +127,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=350
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
diff --git a/arch/avr32/configs/atstk1002_defconfig b/arch/avr32/configs/atstk1002_defconfig
index d1a887e..a582465 100644
--- a/arch/avr32/configs/atstk1002_defconfig
+++ b/arch/avr32/configs/atstk1002_defconfig
@@ -126,7 +126,7 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
diff --git a/arch/avr32/configs/atstk1003_defconfig b/arch/avr32/configs/atstk1003_defconfig
index 956f281..57a79df 100644
--- a/arch/avr32/configs/atstk1003_defconfig
+++ b/arch/avr32/configs/atstk1003_defconfig
@@ -105,7 +105,7 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
diff --git a/arch/avr32/configs/atstk1004_defconfig b/arch/avr32/configs/atstk1004_defconfig
index 40c69f3..1a49bd8 100644
--- a/arch/avr32/configs/atstk1004_defconfig
+++ b/arch/avr32/configs/atstk1004_defconfig
@@ -104,7 +104,7 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
diff --git a/arch/avr32/configs/atstk1006_defconfig b/arch/avr32/configs/atstk1006_defconfig
index 511eb8a..206a1b6 100644
--- a/arch/avr32/configs/atstk1006_defconfig
+++ b/arch/avr32/configs/atstk1006_defconfig
@@ -129,7 +129,7 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
diff --git a/arch/avr32/configs/favr-32_defconfig b/arch/avr32/configs/favr-32_defconfig
index 19973b0..0421498 100644
--- a/arch/avr32/configs/favr-32_defconfig
+++ b/arch/avr32/configs/favr-32_defconfig
@@ -117,7 +117,7 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
diff --git a/arch/avr32/configs/hammerhead_defconfig b/arch/avr32/configs/hammerhead_defconfig
index 6f45681..82f24eb 100644
--- a/arch/avr32/configs/hammerhead_defconfig
+++ b/arch/avr32/configs/hammerhead_defconfig
@@ -127,7 +127,7 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_MMC=m
CONFIG_MMC_ATMELMCI=m
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
index c280a50..f59c80e 100644
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ b/arch/blackfin/configs/CM-BF527_defconfig
@@ -106,7 +106,7 @@ CONFIG_MUSB_PIO_ONLY=y
CONFIG_USB_STORAGE=m
CONFIG_USB_GADGET=m
CONFIG_USB_ETH=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_PRINTER=m
CONFIG_RTC_CLASS=y
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
index 349922b..e961483 100644
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ b/arch/blackfin/configs/CM-BF548_defconfig
@@ -107,7 +107,7 @@ CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
# CONFIG_USB_ETH_RNDIS is not set
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_PRINTER=m
CONFIG_MMC=m
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig
index 0456dea..24936b9 100644
--- a/arch/blackfin/configs/CM-BF561_defconfig
+++ b/arch/blackfin/configs/CM-BF561_defconfig
@@ -83,7 +83,7 @@ CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_USB_GADGET=m
CONFIG_USB_ETH=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_PRINTER=m
CONFIG_MMC=y
diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig
index b6fde2b..4ca8e5c 100644
--- a/arch/mips/configs/bcm47xx_defconfig
+++ b/arch/mips/configs/bcm47xx_defconfig
@@ -473,7 +473,7 @@ CONFIG_USB_GADGET_NET2280=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_LEDS_CLASS=y
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 46c61edc..a0277d4 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -661,7 +661,7 @@ CONFIG_USB_GADGET_NET2280=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_MMC=m
diff --git a/arch/sh/configs/ecovec24_defconfig b/arch/sh/configs/ecovec24_defconfig
index 911e30c9..c6c2bec 100644
--- a/arch/sh/configs/ecovec24_defconfig
+++ b/arch/sh/configs/ecovec24_defconfig
@@ -112,7 +112,7 @@ CONFIG_USB_MON=y
CONFIG_USB_R8A66597_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_MMC=y
CONFIG_MMC_SPI=y
CONFIG_MMC_SDHI=y
diff --git a/arch/sh/configs/se7724_defconfig b/arch/sh/configs/se7724_defconfig
index ed35093..1faa788 100644
--- a/arch/sh/configs/se7724_defconfig
+++ b/arch/sh/configs/se7724_defconfig
@@ -109,7 +109,7 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_MMC=y
CONFIG_MMC_SPI=y
--
1.7.7.3
^ permalink raw reply related
* [PATCHv2 1/6] arch: Change defconfigs to point to g_mass_storage.
From: Nicolas Ferre @ 2012-11-02 13:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <46dde680f525562e9fd19567deb5247f0bf26842.1351715302.v2.git.mina86@mina86.com>
On 11/02/2012 02:31 PM, Michal Nazarewicz :
> From: Michal Nazarewicz <mina86@mina86.com>
>
> The File-backed Storage Gadget (g_file_storage) is being removed, since
> it has been replaced by Mass Storage Gadget (g_mass_storage). This commit
> changes defconfigs point to the new gadget.
>
> Signed-off-by: Michal Nazarewicz <mina86@mina86.com>
> ---
> arch/arm/configs/afeb9260_defconfig | 2 +-
> arch/arm/configs/at91sam9260_defconfig | 2 +-
> arch/arm/configs/at91sam9261_defconfig | 2 +-
> arch/arm/configs/at91sam9263_defconfig | 2 +-
> arch/arm/configs/at91sam9g20_defconfig | 2 +-
For AT91 related defconfigs:
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> arch/arm/configs/corgi_defconfig | 2 +-
> arch/arm/configs/davinci_all_defconfig | 2 +-
> arch/arm/configs/h7202_defconfig | 3 +--
> arch/arm/configs/magician_defconfig | 2 +-
> arch/arm/configs/mini2440_defconfig | 2 +-
> arch/arm/configs/omap1_defconfig | 3 +--
> arch/arm/configs/prima2_defconfig | 1 -
> arch/arm/configs/spitz_defconfig | 2 +-
> arch/arm/configs/stamp9g20_defconfig | 2 +-
> arch/arm/configs/viper_defconfig | 2 +-
> arch/arm/configs/zeus_defconfig | 2 +-
> arch/avr32/configs/atngw100_defconfig | 2 +-
> arch/avr32/configs/atngw100_evklcd100_defconfig | 2 +-
> arch/avr32/configs/atngw100_evklcd101_defconfig | 2 +-
> arch/avr32/configs/atngw100_mrmt_defconfig | 2 +-
> arch/avr32/configs/atngw100mkii_defconfig | 2 +-
> .../avr32/configs/atngw100mkii_evklcd100_defconfig | 2 +-
> .../avr32/configs/atngw100mkii_evklcd101_defconfig | 2 +-
> arch/avr32/configs/atstk1002_defconfig | 2 +-
> arch/avr32/configs/atstk1003_defconfig | 2 +-
> arch/avr32/configs/atstk1004_defconfig | 2 +-
> arch/avr32/configs/atstk1006_defconfig | 2 +-
> arch/avr32/configs/favr-32_defconfig | 2 +-
> arch/avr32/configs/hammerhead_defconfig | 2 +-
> arch/blackfin/configs/CM-BF527_defconfig | 2 +-
> arch/blackfin/configs/CM-BF548_defconfig | 2 +-
> arch/blackfin/configs/CM-BF561_defconfig | 2 +-
> arch/mips/configs/bcm47xx_defconfig | 2 +-
> arch/mips/configs/mtx1_defconfig | 2 +-
> arch/sh/configs/ecovec24_defconfig | 2 +-
> arch/sh/configs/se7724_defconfig | 2 +-
> 37 files changed, 35 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm/configs/afeb9260_defconfig b/arch/arm/configs/afeb9260_defconfig
> index c285a9d..a8dbc1e 100644
> --- a/arch/arm/configs/afeb9260_defconfig
> +++ b/arch/arm/configs/afeb9260_defconfig
> @@ -79,7 +79,7 @@ CONFIG_USB_STORAGE=y
> CONFIG_USB_GADGET=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_RTC_CLASS=y
> CONFIG_RTC_DEBUG=y
> diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig
> index 505b376..0ea5d2c 100644
> --- a/arch/arm/configs/at91sam9260_defconfig
> +++ b/arch/arm/configs/at91sam9260_defconfig
> @@ -75,7 +75,7 @@ CONFIG_USB_STORAGE_DEBUG=y
> CONFIG_USB_GADGET=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_RTC_CLASS=y
> CONFIG_RTC_DRV_AT91SAM9=y
> diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_defconfig
> index 1e8712e..c87beb9 100644
> --- a/arch/arm/configs/at91sam9261_defconfig
> +++ b/arch/arm/configs/at91sam9261_defconfig
> @@ -125,7 +125,7 @@ CONFIG_USB_GADGET=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_MMC=y
> CONFIG_MMC_ATMELMCI=m
> diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
> index d2050ca..c5212f4 100644
> --- a/arch/arm/configs/at91sam9263_defconfig
> +++ b/arch/arm/configs/at91sam9263_defconfig
> @@ -133,7 +133,7 @@ CONFIG_USB_GADGET=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_MMC=y
> CONFIG_SDIO_UART=m
> diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig
> index e1b0e80..3b18810 100644
> --- a/arch/arm/configs/at91sam9g20_defconfig
> +++ b/arch/arm/configs/at91sam9g20_defconfig
> @@ -96,7 +96,7 @@ CONFIG_USB_STORAGE=y
> CONFIG_USB_GADGET=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_MMC=y
> CONFIG_MMC_ATMELMCI=m
> diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
> index 4b8a25d..1fd1d1d 100644
> --- a/arch/arm/configs/corgi_defconfig
> +++ b/arch/arm/configs/corgi_defconfig
> @@ -218,7 +218,7 @@ CONFIG_USB_GADGET=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_MMC=y
> CONFIG_MMC_PXA=y
> diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
> index 67b5abb6..4ea7c95 100644
> --- a/arch/arm/configs/davinci_all_defconfig
> +++ b/arch/arm/configs/davinci_all_defconfig
> @@ -144,7 +144,7 @@ CONFIG_USB_GADGET_DEBUG_FS=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_G_PRINTER=m
> CONFIG_USB_CDC_COMPOSITE=m
> diff --git a/arch/arm/configs/h7202_defconfig b/arch/arm/configs/h7202_defconfig
> index 69405a7..e16d3f3 100644
> --- a/arch/arm/configs/h7202_defconfig
> +++ b/arch/arm/configs/h7202_defconfig
> @@ -34,8 +34,7 @@ CONFIG_FB_MODE_HELPERS=y
> CONFIG_USB_GADGET=m
> CONFIG_USB_ZERO=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> -CONFIG_USB_FILE_STORAGE_TEST=y
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_EXT2_FS=y
> CONFIG_TMPFS=y
> diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
> index a691ef4..557dd29 100644
> --- a/arch/arm/configs/magician_defconfig
> +++ b/arch/arm/configs/magician_defconfig
> @@ -136,7 +136,7 @@ CONFIG_USB_PXA27X=y
> CONFIG_USB_ETH=m
> # CONFIG_USB_ETH_RNDIS is not set
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_USB_GPIO_VBUS=y
> diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
> index 00630e6..a07948a 100644
> --- a/arch/arm/configs/mini2440_defconfig
> +++ b/arch/arm/configs/mini2440_defconfig
> @@ -240,7 +240,7 @@ CONFIG_USB_GADGET_S3C2410=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_MMC=y
> diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
> index dde2a1a..42eab9a 100644
> --- a/arch/arm/configs/omap1_defconfig
> +++ b/arch/arm/configs/omap1_defconfig
> @@ -214,8 +214,7 @@ CONFIG_USB_TEST=y
> CONFIG_USB_GADGET=y
> CONFIG_USB_ETH=m
> # CONFIG_USB_ETH_RNDIS is not set
> -CONFIG_USB_FILE_STORAGE=m
> -CONFIG_USB_FILE_STORAGE_TEST=y
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_MMC=y
> CONFIG_MMC_SDHCI=y
> CONFIG_MMC_SDHCI_PLTFM=y
> diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
> index 807d4e2..6a936c7 100644
> --- a/arch/arm/configs/prima2_defconfig
> +++ b/arch/arm/configs/prima2_defconfig
> @@ -37,7 +37,6 @@ CONFIG_SPI_SIRF=y
> CONFIG_SPI_SPIDEV=y
> # CONFIG_HWMON is not set
> CONFIG_USB_GADGET=y
> -CONFIG_USB_FILE_STORAGE=m
> CONFIG_USB_MASS_STORAGE=m
> CONFIG_MMC=y
> CONFIG_MMC_SDHCI=y
> diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
> index df77931..2e0419d 100644
> --- a/arch/arm/configs/spitz_defconfig
> +++ b/arch/arm/configs/spitz_defconfig
> @@ -214,7 +214,7 @@ CONFIG_USB_GADGET_DUMMY_HCD=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_MMC=y
> CONFIG_MMC_PXA=y
> diff --git a/arch/arm/configs/stamp9g20_defconfig b/arch/arm/configs/stamp9g20_defconfig
> index 52f1488..b845f55 100644
> --- a/arch/arm/configs/stamp9g20_defconfig
> +++ b/arch/arm/configs/stamp9g20_defconfig
> @@ -97,7 +97,7 @@ CONFIG_USB_STORAGE=y
> CONFIG_USB_GADGET=m
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_MMC=y
> CONFIG_MMC_ATMELMCI=y
> diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig
> index 1d01ddd..d36e0d3 100644
> --- a/arch/arm/configs/viper_defconfig
> +++ b/arch/arm/configs/viper_defconfig
> @@ -139,7 +139,7 @@ CONFIG_USB_SERIAL_MCT_U232=m
> CONFIG_USB_GADGET=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_G_PRINTER=m
> CONFIG_RTC_CLASS=y
> diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig
> index 547a3c1..731d4f9 100644
> --- a/arch/arm/configs/zeus_defconfig
> +++ b/arch/arm/configs/zeus_defconfig
> @@ -143,7 +143,7 @@ CONFIG_USB_GADGET=m
> CONFIG_USB_PXA27X=y
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_G_PRINTER=m
> CONFIG_MMC=y
> diff --git a/arch/avr32/configs/atngw100_defconfig b/arch/avr32/configs/atngw100_defconfig
> index a06bfcc..f4025db 100644
> --- a/arch/avr32/configs/atngw100_defconfig
> +++ b/arch/avr32/configs/atngw100_defconfig
> @@ -109,7 +109,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=350
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_MMC=y
> diff --git a/arch/avr32/configs/atngw100_evklcd100_defconfig b/arch/avr32/configs/atngw100_evklcd100_defconfig
> index d8f1fe8..c76a49b 100644
> --- a/arch/avr32/configs/atngw100_evklcd100_defconfig
> +++ b/arch/avr32/configs/atngw100_evklcd100_defconfig
> @@ -125,7 +125,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=350
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_MMC=y
> diff --git a/arch/avr32/configs/atngw100_evklcd101_defconfig b/arch/avr32/configs/atngw100_evklcd101_defconfig
> index d4c5b19..2d8ab08 100644
> --- a/arch/avr32/configs/atngw100_evklcd101_defconfig
> +++ b/arch/avr32/configs/atngw100_evklcd101_defconfig
> @@ -124,7 +124,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=350
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_MMC=y
> diff --git a/arch/avr32/configs/atngw100_mrmt_defconfig b/arch/avr32/configs/atngw100_mrmt_defconfig
> index 77ca4f9..b189e0c 100644
> --- a/arch/avr32/configs/atngw100_mrmt_defconfig
> +++ b/arch/avr32/configs/atngw100_mrmt_defconfig
> @@ -99,7 +99,7 @@ CONFIG_SND_ATMEL_AC97C=m
> # CONFIG_SND_SPI is not set
> CONFIG_USB_GADGET=m
> CONFIG_USB_GADGET_DEBUG_FILES=y
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_MMC=y
> CONFIG_MMC_ATMELMCI=y
> diff --git a/arch/avr32/configs/atngw100mkii_defconfig b/arch/avr32/configs/atngw100mkii_defconfig
> index 6e0dca4..2e4de42 100644
> --- a/arch/avr32/configs/atngw100mkii_defconfig
> +++ b/arch/avr32/configs/atngw100mkii_defconfig
> @@ -111,7 +111,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=350
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_MMC=y
> diff --git a/arch/avr32/configs/atngw100mkii_evklcd100_defconfig b/arch/avr32/configs/atngw100mkii_evklcd100_defconfig
> index 7f2a344..fad3cd2 100644
> --- a/arch/avr32/configs/atngw100mkii_evklcd100_defconfig
> +++ b/arch/avr32/configs/atngw100mkii_evklcd100_defconfig
> @@ -128,7 +128,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=350
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_MMC=y
> diff --git a/arch/avr32/configs/atngw100mkii_evklcd101_defconfig b/arch/avr32/configs/atngw100mkii_evklcd101_defconfig
> index 085eeba..2998623 100644
> --- a/arch/avr32/configs/atngw100mkii_evklcd101_defconfig
> +++ b/arch/avr32/configs/atngw100mkii_evklcd101_defconfig
> @@ -127,7 +127,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=350
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_MMC=y
> diff --git a/arch/avr32/configs/atstk1002_defconfig b/arch/avr32/configs/atstk1002_defconfig
> index d1a887e..a582465 100644
> --- a/arch/avr32/configs/atstk1002_defconfig
> +++ b/arch/avr32/configs/atstk1002_defconfig
> @@ -126,7 +126,7 @@ CONFIG_USB_GADGET=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_MMC=y
> diff --git a/arch/avr32/configs/atstk1003_defconfig b/arch/avr32/configs/atstk1003_defconfig
> index 956f281..57a79df 100644
> --- a/arch/avr32/configs/atstk1003_defconfig
> +++ b/arch/avr32/configs/atstk1003_defconfig
> @@ -105,7 +105,7 @@ CONFIG_USB_GADGET=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_MMC=y
> diff --git a/arch/avr32/configs/atstk1004_defconfig b/arch/avr32/configs/atstk1004_defconfig
> index 40c69f3..1a49bd8 100644
> --- a/arch/avr32/configs/atstk1004_defconfig
> +++ b/arch/avr32/configs/atstk1004_defconfig
> @@ -104,7 +104,7 @@ CONFIG_USB_GADGET=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_MMC=y
> diff --git a/arch/avr32/configs/atstk1006_defconfig b/arch/avr32/configs/atstk1006_defconfig
> index 511eb8a..206a1b6 100644
> --- a/arch/avr32/configs/atstk1006_defconfig
> +++ b/arch/avr32/configs/atstk1006_defconfig
> @@ -129,7 +129,7 @@ CONFIG_USB_GADGET=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_MMC=y
> diff --git a/arch/avr32/configs/favr-32_defconfig b/arch/avr32/configs/favr-32_defconfig
> index 19973b0..0421498 100644
> --- a/arch/avr32/configs/favr-32_defconfig
> +++ b/arch/avr32/configs/favr-32_defconfig
> @@ -117,7 +117,7 @@ CONFIG_USB_GADGET=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_CDC_COMPOSITE=m
> CONFIG_MMC=y
> diff --git a/arch/avr32/configs/hammerhead_defconfig b/arch/avr32/configs/hammerhead_defconfig
> index 6f45681..82f24eb 100644
> --- a/arch/avr32/configs/hammerhead_defconfig
> +++ b/arch/avr32/configs/hammerhead_defconfig
> @@ -127,7 +127,7 @@ CONFIG_USB_GADGET=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_MMC=m
> CONFIG_MMC_ATMELMCI=m
> diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
> index c280a50..f59c80e 100644
> --- a/arch/blackfin/configs/CM-BF527_defconfig
> +++ b/arch/blackfin/configs/CM-BF527_defconfig
> @@ -106,7 +106,7 @@ CONFIG_MUSB_PIO_ONLY=y
> CONFIG_USB_STORAGE=m
> CONFIG_USB_GADGET=m
> CONFIG_USB_ETH=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_G_PRINTER=m
> CONFIG_RTC_CLASS=y
> diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
> index 349922b..e961483 100644
> --- a/arch/blackfin/configs/CM-BF548_defconfig
> +++ b/arch/blackfin/configs/CM-BF548_defconfig
> @@ -107,7 +107,7 @@ CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> # CONFIG_USB_ETH_RNDIS is not set
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_G_PRINTER=m
> CONFIG_MMC=m
> diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig
> index 0456dea..24936b9 100644
> --- a/arch/blackfin/configs/CM-BF561_defconfig
> +++ b/arch/blackfin/configs/CM-BF561_defconfig
> @@ -83,7 +83,7 @@ CONFIG_GPIOLIB=y
> CONFIG_GPIO_SYSFS=y
> CONFIG_USB_GADGET=m
> CONFIG_USB_ETH=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_G_PRINTER=m
> CONFIG_MMC=y
> diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig
> index b6fde2b..4ca8e5c 100644
> --- a/arch/mips/configs/bcm47xx_defconfig
> +++ b/arch/mips/configs/bcm47xx_defconfig
> @@ -473,7 +473,7 @@ CONFIG_USB_GADGET_NET2280=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_MIDI_GADGET=m
> CONFIG_LEDS_CLASS=y
> diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
> index 46c61edc..a0277d4 100644
> --- a/arch/mips/configs/mtx1_defconfig
> +++ b/arch/mips/configs/mtx1_defconfig
> @@ -661,7 +661,7 @@ CONFIG_USB_GADGET_NET2280=y
> CONFIG_USB_ZERO=m
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_USB_MIDI_GADGET=m
> CONFIG_MMC=m
> diff --git a/arch/sh/configs/ecovec24_defconfig b/arch/sh/configs/ecovec24_defconfig
> index 911e30c9..c6c2bec 100644
> --- a/arch/sh/configs/ecovec24_defconfig
> +++ b/arch/sh/configs/ecovec24_defconfig
> @@ -112,7 +112,7 @@ CONFIG_USB_MON=y
> CONFIG_USB_R8A66597_HCD=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_GADGET=y
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_MMC=y
> CONFIG_MMC_SPI=y
> CONFIG_MMC_SDHI=y
> diff --git a/arch/sh/configs/se7724_defconfig b/arch/sh/configs/se7724_defconfig
> index ed35093..1faa788 100644
> --- a/arch/sh/configs/se7724_defconfig
> +++ b/arch/sh/configs/se7724_defconfig
> @@ -109,7 +109,7 @@ CONFIG_USB_STORAGE=y
> CONFIG_USB_GADGET=y
> CONFIG_USB_ETH=m
> CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> +CONFIG_USB_MASS_STORAGE=m
> CONFIG_USB_G_SERIAL=m
> CONFIG_MMC=y
> CONFIG_MMC_SPI=y
>
--
Nicolas Ferre
^ permalink raw reply
* [PATCH 5/8] ARM: zynq: add COMMON_CLK support
From: Josh Cartwright @ 2012-11-02 13:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50939378.2050500@metafoo.de>
Thanks for the review.
On Fri, Nov 02, 2012 at 10:33:44AM +0100, Lars-Peter Clausen wrote:
> On 10/31/2012 07:58 PM, Josh Cartwright wrote:
> > [...]
> > +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x)&3)>>4])
> > +#define PERIPH_CLK_CTRL_DIV(x) (((x)&0x3F00)>>8)
>
> A few more spaces wouldn't hurt ;)
Okay, sure.
> > [...]
> > +static void __init zynq_periph_clk_setup(struct device_node *np)
> > +{
> > + struct zynq_periph_clk *periph;
> > + const char *parent_names[3];
> > + struct clk_init_data init;
> > + struct clk *clk;
> > + int err;
> > + u32 reg;
> > + int i;
> > +
> > + err = of_property_read_u32(np, "reg", ®);
> > + WARN_ON(err);
>
> Shouldn't the function abort if a error happens somewhere? Continuing here
> will lead to undefined behavior. Same is probably true for the other WARN_ONs.
The way I see it is: the kernel is will be left in a bad state in the
case of any failure, regardless of if we bail out or continue. AFAICT,
there is no clean way to recover from a failure this early.
Given that, it seems simpler (albeit marginally so) just to continue; so
that's what I chose to do. I'm not opposed to bailing out, just not
convinced it does anything for us.
> > +
> > + periph = kzalloc(sizeof(*periph), GFP_KERNEL);
> > + WARN_ON(!periph);
> > +
> > + periph->clk_ctrl = slcr_base + reg;
> > + spin_lock_init(&periph->clkact_lock);
> > +
> > + init.name = np->name;
> > + init.ops = &zynq_periph_clk_ops;
> > + for (i = 0; i < ARRAY_SIZE(parent_names); i++)
> > + parent_names[i] = of_clk_get_parent_name(np, i);
> > + init.parent_names = parent_names;
> > + init.num_parents = ARRAY_SIZE(parent_names);
> > +
> > + periph->hw.init = &init;
> > +
> > + clk = clk_register(NULL, &periph->hw);
> > + WARN_ON(IS_ERR(clk));
> > +
> > + err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
> > + WARN_ON(err);
> > +
> > + for (i = 0; i < 2; i++) {
>
> Not all of the peripheral clock generators have two output clocks. I think
> it makes sense to use the number entries in clock-output-names here.
Yes, I agree. I'll also update the bindings documentation.
Thanks again,
Josh
^ permalink raw reply
* [PATCH 7/8] serial: xilinx_uartps: get clock rate info from dts
From: Josh Cartwright @ 2012-11-02 13:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50939061.9060201@metafoo.de>
On Fri, Nov 02, 2012 at 10:20:33AM +0100, Lars-Peter Clausen wrote:
> On 10/31/2012 08:28 PM, Josh Cartwright wrote:
> > Add support for specifying clock information for the uart clk via the
> > device tree. This eliminates the need to hardcode rates in the device
> > tree.
> >
> > Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
> > ---
> > arch/arm/boot/dts/zynq-7000.dtsi | 4 ++--
> > drivers/tty/serial/xilinx_uartps.c | 30 +++++++++++++++++-------------
> > 2 files changed, 19 insertions(+), 15 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
> > index bb3085c..5fb763f 100644
> > --- a/arch/arm/boot/dts/zynq-7000.dtsi
> > +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> > @@ -44,14 +44,14 @@
> > compatible = "xlnx,xuartps";
> > reg = <0xE0000000 0x1000>;
> > interrupts = <0 27 4>;
> > - clock = <50000000>;
> > + clocks = <&uart_clk 0>;
> > };
> >
> > uart1: uart at e0001000 {
> > compatible = "xlnx,xuartps";
> > reg = <0xE0001000 0x1000>;
> > interrupts = <0 50 4>;
> > - clock = <50000000>;
> > + clocks = <&uart_clk 0>;
>
> Shouldn't this be <&uart_clk 1>?
Yes, indeed.
Thanks,
Josh
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121102/a37426c2/attachment.sig>
^ permalink raw reply
* [PATCH 09/10] ARM: SMP: add function arch_send_wakeup_ipi_mask()
From: Shawn Guo @ 2012-11-02 13:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121031034331.GB8100@S2100-06.ap.freescale.net>
On Wed, Oct 31, 2012 at 11:43:34AM +0800, Shawn Guo wrote:
> On Tue, Oct 23, 2012 at 11:22:58PM +0800, Shawn Guo wrote:
> > Add function arch_send_wakeup_ipi_mask(), so that platform code can
> > use it as an easy way to wake up cores that are in WFI.
> >
> > Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> > Cc: Russell King <linux@arm.linux.org.uk>
>
> Hi Russell,
>
> Can I ask for your ack to have the patch go via arm-soc being part
> of the series?
>
Ping
Shawn
^ permalink raw reply
* [PATCH v3 04/11] clk: davinci - add pll divider clock driver
From: Murali Karicheri @ 2012-11-02 13:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5093AF8A.8000707@ti.com>
On 11/02/2012 07:33 AM, Sekhar Nori wrote:
> On 10/25/2012 9:41 PM, Murali Karicheri wrote:
>
>> pll dividers are present in the pll controller of DaVinci and Other
>> SoCs that re-uses the same hardware IP. This has a enable bit for
>> bypass the divider or enable the driver. This is a sub class of the
>> clk-divider clock checks the enable bit to calculare the rate and
>> invoke the recalculate() function of the clk-divider if enabled.
>>
>> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
>> ---
>> drivers/clk/davinci/clk-div.c | 124 +++++++++++++++++++++++++++++++++++++++++
>> drivers/clk/davinci/clk-div.h | 42 ++++++++++++++
>> 2 files changed, 166 insertions(+)
>> create mode 100644 drivers/clk/davinci/clk-div.c
>> create mode 100644 drivers/clk/davinci/clk-div.h
>>
>> diff --git a/drivers/clk/davinci/clk-div.c b/drivers/clk/davinci/clk-div.c
>> new file mode 100644
>> index 0000000..8147d99
>> --- /dev/null
>> +++ b/drivers/clk/davinci/clk-div.c
>> @@ -0,0 +1,124 @@
>> +/*
>> + * Copyright 2012 Freescale Semiconductor, Inc.
>> + * Copyright 2012 Texas instuments
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
> incomplete sentence.
Will fix
>
>> +/**
>> + * clk_register_davinci_plldiv - register function for DaVinci PLL divider clk
>> + *
>> + * @dev: device ptr
>> + * @name: name of the clock
>> + * @parent_name: name of parent clock
>> + * @plldiv_data: ptr to pll divider data
>> + * @lock: ptr to spinlock passed to divider clock
>> + */
>> +struct clk *clk_register_davinci_plldiv(struct device *dev,
> Why do you need a dev pointer here and which device does it point to? In
> the only usage of this API in the series, you pass a NULL here. I should
> have probably asked this question on one of the earlier patches itself.
>
I did a grep in the drivers/clk directory. All of the platform drivers
are having the device ptr and all of them are called with NULL. I am not
sure what is the intent of this arg in the API. As per documentation of
the clk_register() API, the device ptr points to the device that is
registering this clk. So if a specific device driver ever has to
register a PLL div clk, this will be non NULL. In the normal use case,
clk is registered in a platform specific code and is always passed NULL.
The platform/SoC specific clock initialization code will be using
davinci_plldiv_clk() that doesn't have a device ptr arg.
So this can be changed in future in sync with other drivers (assuming
this will get removed if unused), and changes
doesn't impact the platform code that initialize the clock. So IMO, we
should keep this arg so that it is in sync with other driver APIs.
+ const char *name, const char *parent_name,
+ struct clk_plldiv_data *plldiv_data,
+ spinlock_t *lock)
+{
+ struct clk_div *div;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &clk_div_ops;
+ init.flags = plldiv_data->flags;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ div->reg = plldiv_data->reg;
+ div->en_id = plldiv_data->en_id;
+
+ div->divider.reg = plldiv_data->reg;
+ div->divider.shift = plldiv_data->shift;
+ div->divider.width = plldiv_data->width;
+ div->divider.flags = plldiv_data->divider_flags;
+ div->divider.lock = lock;
+ div->divider.hw.init = &init;
+ div->ops = &clk_divider_ops;
+
+ clk = clk_register(NULL, &div->divider.hw);
> Shouldn't you be calling clk_register_divider() here which in turn will
> do clk_register()?
As stated in the top of the file, this is a subclass driver of clk-div
similar in line with mxs/clk-div.c. The
driver registers the clock instead of calling clk_register_divider() so
that it's ops function has a chance to do whatever it wants to do and
call the divider ops function after that.
Murali
> Thanks,
> Sekhar
>
>
^ permalink raw reply
* [PATCH v2] ARM: S3C64XX: Fix up IRQ mapping for balblair on Cragganmore
From: Mark Brown @ 2012-11-02 14:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351861454-20032-1-git-send-email-dp@opensource.wolfsonmicro.com>
On Fri, Nov 02, 2012 at 01:04:14PM +0000, Dimitris Papastamos wrote:
> We are using S3C_EINT(4) instead of S3C_EINT(5).
Reviwed-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121102/5ecfdda4/attachment.sig>
^ permalink raw reply
* [Patch v2 3/4] ASoC: atmel-ssc-dai: register platform from DAIs
From: Mark Brown @ 2012-11-02 14:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5093312D.4070408@atmel.com>
On Fri, Nov 02, 2012 at 10:34:21AM +0800, Bo Shen wrote:
> On 11/1/2012 22:43, Mark Brown wrote:
> >On Wed, Oct 31, 2012 at 03:26:59PM +0800, Bo Shen wrote:
> >>+dai: dai {
> >>+ compatible = "atmel,atmel-ssc-dai";
> >>+ atmel,dai-master = <&ssc0>;
> >>+};
> >This seems to be a purely virtual device which remaps the SSC onto the
> >Linux audio subsystem? If that is the case then it shouldn't appear in
> >the device tree,
> Yes. This is a purely virtual device. I add this as to the following reason.
> In our case, the ssc can connect to audio codec, DAC and other
> devices. In order to avoid duplicate the code, so keep ssc as a
> library, register it directly in Linux and use remap method to let
> it work onto other different subsystem.
Your quote appears to have deleted the bit of my mail where I told you
how to fix this. Is there something unclear in my suggestion that the
machine driver directly reference the SSC node?
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121102/d8cbe679/attachment.sig>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox