* [Patch v2 3/4] ASoC: atmel-ssc-dai: register platform from DAIs
From: Bo Shen @ 2012-11-05 5:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121102142444.GY4413@opensource.wolfsonmicro.com>
Hi Mark Brown,
On 11/2/2012 22:24, Mark Brown wrote:
> On Fri, Nov 02, 2012 at 10:34:21AM +0800, Bo Shen wrote:
>> On 11/1/2012 22:43, Mark Brown wrote:
>>> On Wed, Oct 31, 2012 at 03:26:59PM +0800, Bo Shen wrote:
>
>>>> +dai: dai {
>>>> + compatible = "atmel,atmel-ssc-dai";
>>>> + atmel,dai-master = <&ssc0>;
>>>> +};
>
>>> This seems to be a purely virtual device which remaps the SSC onto the
>>> Linux audio subsystem? If that is the case then it shouldn't appear in
>>> the device tree,
>
>> Yes. This is a purely virtual device. I add this as to the following reason.
>
>> In our case, the ssc can connect to audio codec, DAC and other
>> devices. In order to avoid duplicate the code, so keep ssc as a
>> library, register it directly in Linux and use remap method to let
>> it work onto other different subsystem.
>
> Your quote appears to have deleted the bit of my mail where I told you
> how to fix this. Is there something unclear in my suggestion that the
> machine driver directly reference the SSC node?
>
Sorry for misunderstand. I split your e-mail into two parts. May be you
miss some parts of my e-mail. You can check the last mail from me. Or
check the following fully quote.
--------------------------------------------------------------------------
On 11/1/2012 22:43, Mark Brown wrote:
> On Wed, Oct 31, 2012 at 03:26:59PM +0800, Bo Shen wrote:
>
>> +Required properties:
>> + - compatible: "atmel,atmel-ssc-dai"
>> + - atmel,dai-master: this dai base on which ssc controller
>
>> +Example:
>> +dai: dai {
>> + compatible = "atmel,atmel-ssc-dai";
>> + atmel,dai-master = <&ssc0>;
>> +};
>
> This seems to be a purely virtual device which remaps the SSC onto the
> Linux audio subsystem? If that is the case then it shouldn't appear in
> the device tree,
Yes. This is a purely virtual device. I add this as to the following reason.
In our case, the ssc can connect to audio codec, DAC and other devices.
In order to avoid duplicate the code, so keep ssc as a library, register
it directly in Linux and use remap method to let it work onto other
different subsystem.
So, for ssc connect to audio codec, use dai to remap the SSC onto the
Linux audio subsystem. In this way, just let the dai know which ssc
channel it based on. The remap is just a simple way. Please take
following code as a reference.
---<8---
if (pdev->dev.of_node) {
struct device_node *np = pdev->dev.of_node;
struct device_node *dai_master_np;
dai_master_np = of_parse_phandle(np,
"atmel,dai-master", 0);
if (!dai_master_np) {
dev_err(&pdev->dev, "No SSC for atmel dai");
return -EINVAL;
}
id = of_alias_get_id(dai_master_np, "ssc");
} else {
id = to_platform_device(pdev->dev.parent)->id;
}
ssc = ssc_request(id);
if (IS_ERR(ssc)) {
dev_err(&pdev->dev, "Failed to request SSC %d\n", id);
return PTR_ERR(ssc);
}
ssc_info.ssc = ssc;
pdev->dev.parent = &(ssc->pdev->dev);
--->8---
If ssc connect to other devices, also need to remap to other subsystem.
> the machine driver should just directly reference the
> SSC and instantiate any devices required in Linux directly.
I am not fully understand this. So, which do you mean as the following
two method or any other else?
Our old method:
using audio machine driver (e.g: sam9g20_wm8731.c) call
atmel_ssc_set_audio function to allocate the platform device for
atmel-ssc-dai and atmel-pcm-audio and then add device.
Code as following:
---<8---
/* Allocate a dummy device for DMA if we don't have one already */
if (!dma_pdev) {
dma_pdev = platform_device_alloc("atmel-pcm-audio", -1);
if (!dma_pdev)
return -ENOMEM;
ret = platform_device_add(dma_pdev);
if (ret < 0) {
platform_device_put(dma_pdev);
dma_pdev = NULL;
return ret;
}
}
ssc_pdev = platform_device_alloc("atmel-ssc-dai", ssc_id);
if (!ssc_pdev)
return -ENOMEM;
/* If we can grab the SSC briefly to parent the DAI device off
it */
ssc = ssc_request(ssc_id);
if (IS_ERR(ssc))
pr_warn("Unable to parent ASoC SSC DAI on SSC: %ld\n",
PTR_ERR(ssc));
else {
ssc_pdev->dev.parent = &(ssc->pdev->dev);
ssc_free(ssc);
}
ret = platform_device_add(ssc_pdev);
--->8---
Other SoC do like this:
register i2s device, and then register dai, finally register
platform. So, only one device.
--------------------------------------------------------------------------
Best regards,
Bo Shen
^ permalink raw reply
* [PATCH V2 0/3] ARM: dts: omap5: EMIF and LPDDR2 device tree data
From: Lokesh Vutla @ 2012-11-05 5:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349959669-16366-1-git-send-email-lokeshvutla@ti.com>
Hi,
On Thursday 11 October 2012 06:17 PM, Lokesh Vutla wrote:
> This patch series adds Device tree data for the EMIF
> sdram controllers in OMAP5 and LPDDR2 memory devices
> in OMAP5-evm board.
>
> Testing:
> - Boot tested on OMAP5430 evm.
> - Built EMIF as a module.
>
> Changes from v1:
> * Created a seperate dtsi file for Samsung LPDDR2 memory device
> used in OMAP5-evm.
> * Passing reg and interrupt fields from dt for EMIF1 and EMIF2.
Gentle ping on this series.
Thanks
Lokesh
>
> Lokesh Vutla (3):
> ARM: dts: omap5-evm: Fix size of memory defined for EVM
> ARM: dts: omap5: EMIF device tree data for OMAP5 boards
> ARM: dts: omap5-evm: LPDDR2 memory device details for EVM
>
> arch/arm/boot/dts/omap5-evm.dts | 13 +++++-
> arch/arm/boot/dts/omap5.dtsi | 24 +++++++++++
> arch/arm/boot/dts/samsung_k3pe0e000b.dtsi | 67 +++++++++++++++++++++++++++++
> 3 files changed, 103 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
>
^ permalink raw reply
* [PATCH] ARM: dts: AM33XX: Add usbss node
From: Afzal Mohammed @ 2012-11-05 5:59 UTC (permalink / raw)
To: linux-arm-kernel
From: Ajay Kumar Gupta <ajay.gupta@ti.com>
Device tree node for usbss on AM33XX. There are two musb
controllers on am33xx platform so have port0-mode and
port1-mode data.
[afzal at ti.com: reg & interrupt property addition]
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Santhapuri, Damodar <damodar.santhapuri@ti.com>
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
Hi Benoit,
This is based on your "for_3.8/dts" branch.
This is made on top of "usb: musb: am335x support"
(http://marc.info/?l=linux-omap&m=135187391904863&w=2)
and has been tested on Beagle Bone.
Regards
Afzal
arch/arm/boot/dts/am33xx.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 5dfd682..78340a5 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -321,5 +321,22 @@
ti,hwmods = "spi1";
status = "disabled";
};
+
+ usb_otg_hs at 47400000 {
+ compatible = "ti,musb-am33xx";
+ reg = <0x47400000 0x1000 /* usbss */
+ 0x47401000 0x800 /* musb instance 0 */
+ 0x47401800 0x800>; /* musb instance 1 */
+ interrupts = <17 /* usbss */
+ 18 /* musb instance 0 */
+ 19>; /* musb instance 1 */
+ multipoint = <1>;
+ num-eps = <16>;
+ ram-bits = <12>;
+ port0-mode = <3>;
+ port1-mode = <3>;
+ power = <250>;
+ ti,hwmods = "usb_otg_hs";
+ };
};
};
--
1.7.12
^ permalink raw reply related
* [PATCH] i2c: at91: add a sanity check on i2c message length
From: Voss, Nikolaus @ 2012-11-05 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5093EE2B.8080005@atmel.com>
ludovic.desroches wrote on Friday, November 02, 2012 5:01 PM:
> Le 11/02/2012 12:14 PM, Wolfram Sang a ?crit :
> > On Fri, Nov 02, 2012 at 12:04:45PM +0100, ludovic.desroches wrote:
> >> Hi Wolfram,
> >>
> >> Le 11/01/2012 11:29 PM, Wolfram Sang a ?crit :
> >>> On Wed, Oct 10, 2012 at 04:25:58PM +0200,
> ludovic.desroches at atmel.com wrote:
> >>>> From: Ludovic Desroches <ludovic.desroches@atmel.com>
> >>>>
> >>>> If the i2c message length is zero, i2c-at91 will directly return an error
> >>>> instead of trying to send a zero-length message.
> >>>>
> >>>> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
> >>>
> >>> What happens if you send a 0 byte message? Some hardware is able to
> do
> >>> this and it will be used in SMBUS QUICK which the driver states to
> >>> support according to at91_twi_func().
> >>
> >> Without this I had some data corruption when writing to / reading
> >> from a serial eeprom (depending on the IP version).
> >>
> >> Yes SMBUS quick command is supported but is not managed in the
> >> driver, we have to tell explicitly the IP that we want to send this
> >> command.
> >
> > Ok, so unless you want to implement the support, please update this
> > patch with a comment that SMBUS_QUICK is a TODO and remove the
> > SMBUS_QUICK capability.
> >
>
> Implementation should not be a huge task, only one bit to set in a
> register but I have no device to test it.
> So I will choose to remove the SMBUS_QUICK capability.
>
> Hi Nikolaus,
>
> Did you test the driver with SMBus compatible devices? Can I keep other
> SMBus capabilities from SMBUS_EMUL?
Hi Ludovic,
yes, I use this driver with the sbs driver to query a smbus-attached
battery with a TI bq chip (I actually wrote this driver only for this
purpose). I implemented and tested SMBUS_BLOCK but not
SMBUS_QUICK...
Niko
^ permalink raw reply
* [PATCH v2] leds: leds-gpio: adopt pinctrl support
From: AnilKumar, Chimata @ 2012-11-05 6:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdY_db3ju4LVnoR=0Wq8TFUxa48jNFGhvGM-3uSrmGZVew@mail.gmail.com>
On Sun, Nov 04, 2012 at 23:07:44, Linus Walleij wrote:
> On Tue, Oct 30, 2012 at 3:12 PM, AnilKumar, Chimata <anilkumar@ti.com> wrote:
>
> > I completely understood this named modes, I have added named
> > modes like this in am335x-xxx.dts files
>
> I do not understand how the pinctrl-single dts files work actually,
> so please get Tony to review this part.
>
> > I think "pinctrl-1" state will be used in driver
> > suspend/resume calls.
>
> Hopefully, I think you should test the code and monitor the
> system to make sure the right thing happens.
I will test while adding "pinctrl-1" data to .dts files.
>
> > I have the pinmux/conf settings for default state but fully
> > optimized pinmux/conf values in idle & suspend states are not
> > available yet.
>
> You have defined a "sleep" state which is what should be used
> for suspend? Or do you mean that you do have a state but
> you're just not defining it to the most optimal setting yet?
Yes, sleep state is used for suspend. Regarding to this suspend
state fully optimized pinmux/conf values are not available.
Thanks
AnilKumar
^ permalink raw reply
* [PATCH 04/15] ARM: OMAP2+: hwmod: Update the reset API for AM33XX
From: Vaibhav Hiremath @ 2012-11-05 6:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-5-git-send-email-vaibhav.bedia@ti.com>
On 11/2/2012 6:02 PM, Vaibhav Bedia wrote:
> WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
> Update the hardreset API to take care of the same to ensure
> that the reset line properly deasserted.
>
Thanks for the patch, comments below -
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod.c | 5 +----
> arch/arm/mach-omap2/prm33xx.c | 15 +++++++--------
> arch/arm/mach-omap2/prm33xx.h | 2 +-
> 3 files changed, 9 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 37eeb45..a1d5835 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -2944,11 +2944,8 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
> static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
> struct omap_hwmod_rst_info *ohri)
> {
> - if (ohri->st_shift)
> - pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
> - oh->name, ohri->name);
> -
> return am33xx_prm_deassert_hardreset(ohri->rst_shift,
> + ohri->st_shift,
> oh->clkdm->pwrdm.ptr->prcm_offs,
> oh->prcm.omap4.rstctrl_offs,
> oh->prcm.omap4.rstst_offs);
> diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
> index 53ec9cb..0f29cb9 100644
> --- a/arch/arm/mach-omap2/prm33xx.c
> +++ b/arch/arm/mach-omap2/prm33xx.c
> @@ -112,23 +112,22 @@ int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
> * -EINVAL upon an argument error, -EEXIST if the submodule was already out
> * of reset, or -EBUSY if the submodule did not exit reset promptly.
> */
> -int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
> +int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
> u16 rstctrl_offs, u16 rstst_offs)
> {
> int c;
> - u32 mask = 1 << shift;
> -
> - /* Check the current status to avoid de-asserting the line twice */
> - if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
> - return -EEXIST;
Any specific reason why you have removed this check?
Thanks,
Vaibhav
> + u32 mask = 1 << st_shift;
>
> /* Clear the reset status by writing 1 to the status bit */
> am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
> +
> /* de-assert the reset control line */
> + mask = 1 << shift;
> +
> am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
> - /* wait the status to be set */
>
> - omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
> + /* wait the status to be set */
> + omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, inst,
> rstst_offs),
> MAX_MODULE_HARDRESET_WAIT, c);
>
> diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
> index 3f25c56..181fdab 100644
> --- a/arch/arm/mach-omap2/prm33xx.h
> +++ b/arch/arm/mach-omap2/prm33xx.h
> @@ -124,6 +124,6 @@ extern void am33xx_prm_global_warm_sw_reset(void);
> extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
> u16 rstctrl_offs);
> extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
> -extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
> +extern int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
> u16 rstctrl_offs, u16 rstst_offs);
> #endif
>
^ permalink raw reply
* [PATCH 05/15] ARM: OMAP2+: AM33XX: Update WKUP_M3 hwmod entry for reset status
From: Vaibhav Hiremath @ 2012-11-05 6:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-6-git-send-email-vaibhav.bedia@ti.com>
On 11/2/2012 6:02 PM, Vaibhav Bedia wrote:
> Add the reset status offset for WKUP_M3 in the hwmod data
>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
Thanks for the patch, Probably you can resubmit this patch separately
which can be merged independently from this patch-series.
Acked-by: Vaibhav Hiremath <hvaibhav@ti.com>
Thanks,
Vaibhav
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> index 3c235d8..2e470ce 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -269,6 +269,7 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
> .omap4 = {
> .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
> .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
> + .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
> .modulemode = MODULEMODE_SWCTRL,
> },
> },
>
^ permalink raw reply
* [RFC PATCH v3 00/16] DMA Engine support for AM33XX
From: Hebbar, Gururaja @ 2012-11-05 7:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
On Thu, Oct 18, 2012 at 18:56:39, Porter, Matt wrote:
...snip...
...snip...
...snip...
>
> This series adds DMA Engine support for AM33xx, which uses
> an EDMA DMAC. The EDMA DMAC has been previously supported by only
> a private API implementation (much like the situation with OMAP
> DMA) found on the DaVinci family of SoCs.
>
> The series applies on top of 3.7-rc1 and the following patches:
>
> - GPMC fails to reserve memory fix:
> http://www.spinics.net/lists/linux-omap/msg79675.html
> - TPS65910 regulator fix:
> https://patchwork.kernel.org/patch/1593651/
> - dmaengine DT support from Vinod's dmaengine_dt branch in
> git://git.infradead.org/users/vkoul/slave-dma.git since
> 027478851791df751176398be02a3b1c5f6aa824
>
> The approach taken is similar to how OMAP DMA is being converted to
> DMA Engine support. With the functional EDMA private API already
> existing in mach-davinci/dma.c, we first move that to an ARM common
> area so it can be shared. Adding DT and runtime PM support to the
> private EDMA API implementation allows it to run on AM33xx. AM33xx
> *only* boots using DT so we leverage Jon's generic DT DMA helpers to
> register EDMA DMAC with the of_dma framework and then add support
> for calling the dma_request_slave_channel() API to both the mmc
> and spi drivers.
>
> With this series both BeagleBone and the AM335x EVM have working
> MMC and SPI support.
>
> This is tested on BeagleBone with a SPI framebuffer driver and MMC
> rootfs. A trivial gpio DMA event misc driver was used to test the
> crossbar DMA event support. It is also tested on the AM335x EVM
> with the onboard SPI flash and MMC rootfs. The branch at
> https://github.com/ohporter/linux/tree/edma-dmaengine-v3 has the
> complete series, dependencies, and some test drivers/defconfigs.
>
> Regression testing was done on AM180x-EVM (which also makes use
> of the EDMA dmaengine driver and the EDMA private API) using SD,
> SPI flash, and the onboard audio supported by the ASoC Davinci
> driver.
Since you have tested MMC, and probably will be adding Audio support
for AM335x as well, I believe you will also be adding Pin-mux support
for both the modules.
Can you share your plan to release the next version?
I have few patches pending for AM335x Audio (DT related).
Thanks in advance
Regards
Gururaja
>
> After this series, the plan is to convert the last in-tree user
> of the private EDMA API (davinci-pcm/mcasp) and then eliminate
> the private EDMA API by folding its functionality into
> drivers/dma/edma.c.
>
> Matt Porter (16):
> dmaengine: edma: fix slave config dependency on direction
> ARM: davinci: move private EDMA API to arm/common
> ARM: edma: remove unused transfer controller handlers
> ARM: edma: add DT and runtime PM support for AM33XX
> ARM: edma: add AM33XX crossbar event support
> dmaengine: edma: enable build for AM33XX
> dmaengine: edma: Add TI EDMA device tree binding
> ARM: dts: add AM33XX EDMA support
> dmaengine: add dma_request_slave_channel_compat()
> mmc: omap_hsmmc: convert to dma_request_slave_channel_compat()
> mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
> mmc: omap_hsmmc: add generic DMA request support to the DT binding
> ARM: dts: add AM33XX MMC support
> spi: omap2-mcspi: convert to dma_request_slave_channel_compat()
> spi: omap2-mcspi: add generic DMA request support to the DT binding
> ARM: dts: add AM33XX SPI support
>
^ permalink raw reply
* [PATCH 07/15] ARM: OMAP2+: hwmod: Update the hwmod data for TPTCs in AM33XX
From: Vaibhav Hiremath @ 2012-11-05 7:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-8-git-send-email-vaibhav.bedia@ti.com>
On 11/2/2012 6:02 PM, Vaibhav Bedia wrote:
> Update the TPTC hwmod entry to reflect the fact that
> the idle and standby transitions are s/w controlled.
>
Acked-by: Vaibhav Hiremath <hvaibhav@ti.com>
Thanks,
Vaibhav
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> index ec3fbb2..7772c29 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -1827,6 +1827,7 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
> .class = &am33xx_tptc_hwmod_class,
> .clkdm_name = "l3_clkdm",
> .mpu_irqs = am33xx_tptc0_irqs,
> + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
> .main_clk = "l3_gclk",
> .prcm = {
> .omap4 = {
>
^ permalink raw reply
* [PATCH v2 1/5] clk: samsung: add common clock framework support for Samsung platforms
From: Thomas Abraham @ 2012-11-05 7:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121030163012.18780.19304@nucleus>
Hi Mike,
Thanks for your review.
On 30 October 2012 22:00, Mike Turquette <mturquette@ti.com> wrote:
> Hi Thomas,
>
> Quoting Thomas Abraham (2012-10-07 10:10:51)
>> +/* determine the output clock speed of the pll */
>> +static unsigned long samsung_pll_clock_recalc_rate(struct clk_hw *hw,
>> + unsigned long parent_rate)
>> +{
>> + struct samsung_pll_clock *clk_pll = to_clk_pll(hw);
>> +
>> + if (clk_pll->get_rate)
>> + return to_clk_pll(hw)->get_rate(parent_rate);
>
> Why the extra indirection? Does your samsung_pll_clock abstract several
> different PLL implementations (with separate clock ops)? If so, why not
> make a unique struct for each PLL type?
Yes, it abstracts several PLL types. There are multiple PLL types used
by Samsung SoC's and this clock type was supposed to abstract all the
types of PLL's. But yes, you are right. It is better to have a unique
implementation for each type of PLL. That way, multiple user's of a
PLL type need not be worried about setting up runtime callbacks for
clock operations.
>
>> +
>> + return 0;
>> +}
>> +
>> +/* round operation not supported */
>> +static long samsung_pll_clock_round_rate(struct clk_hw *hw, unsigned long drate,
>> + unsigned long *prate)
>> +{
>> + return samsung_pll_clock_recalc_rate(hw, *prate);
>
> Why is round_rate not supported? How is returning the recalculated rate
> the right thing here?
The PLL does not include a divider for the rounding operation. So the
output of the PLL clock type is not something that can be divided
down. The parent clock of the PLL clock type is usually a low
frequency oscillator. Hence, the round rate operation has not been
implemented for the PLL clock type.
>
>> +/*
>> + * Allow platform specific implementations to attach set_rate and get_rate
>> + * callbacks for the pll type clock. Typical calling sequence..
>> + *
>> + * struct clk *clk = clk_get(NULL, "pll-clk-name");
>> + * samsung_pll_clk_set_cb(clk, pll_set_rate, pll_get_rate);
>> + */
>> +void __init samsung_pll_clk_set_cb(struct clk *clk,
>> + int (*set_rate)(unsigned long rate),
>> + unsigned long (*get_rate)(unsigned long rate))
>> +{
>> + struct samsung_pll_clock *clk_pll;
>> + struct clk_hw *hw = __clk_get_hw(clk);
>> +
>> + clk_pll = to_clk_pll(hw);
>> + clk_pll->set_rate = set_rate;
>> + clk_pll->get_rate = get_rate;
>> +}
>
> This answers my questions above having different PLL types. Why not
> just make seprate clk_hw structs for each PLL type instead of the extra
> layer of abstraction + runtime assignment of clk ops?
Ok. I will redo this in the next version of this patch.
Thanks,
Thomas.
>
> Regards,
> Mike
^ permalink raw reply
* [PATCH 06/15] ARM: OMAP2+: hwmod: Enable OCMCRAM registration in AM33XX
From: Vaibhav Hiremath @ 2012-11-05 7:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-7-git-send-email-vaibhav.bedia@ti.com>
On 11/2/2012 6:02 PM, Vaibhav Bedia wrote:
> The hwmod data for OCMCRAM in AM33XX was commented out.
> This data is needed by the power management code, hence
> uncomment the same and register the OCP interface for it.
>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 11 ++++++++++-
> 1 files changed, 10 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> index 2e470ce..ec3fbb2 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -415,7 +415,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
> * - cEFUSE (doesn't fall under any ocp_if)
> * - clkdiv32k
> * - debugss
> - * - ocmc ram
> * - ocp watch point
> * - aes0
> * - sha0
> @@ -481,6 +480,7 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
> },
> },
> };
> +#endif
>
> /* ocmcram */
> static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
> @@ -501,6 +501,7 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
> },
> };
>
> +#if 0
Can you cut-n-paste the ocmcram hwmod entry outside of #if and resubmit
it again?
Thanks,
Vaibhav
> /* ocpwp */
> static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
> .name = "ocpwp",
> @@ -3331,6 +3332,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
> .flags = OCPIF_SWSUP_IDLE,
> };
>
> +/* l3 main -> ocmc */
> +static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
> + .master = &am33xx_l3_main_hwmod,
> + .slave = &am33xx_ocmcram_hwmod,
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
> &am33xx_l4_fw__emif_fw,
> &am33xx_l3_main__emif,
> @@ -3401,6 +3409,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
> &am33xx_l3_main__tptc0,
> &am33xx_l3_main__tptc1,
> &am33xx_l3_main__tptc2,
> + &am33xx_l3_main__ocmc,
> &am33xx_l3_s__usbss,
> &am33xx_l4_hs__cpgmac0,
> &am33xx_cpgmac0__mdio,
>
^ permalink raw reply
* [PATCH v3 0/6] DT support for AT91RM9200
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-11-05 7:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGhQ9VzWxhM7QitutizN3WB6w-bDTDia9Bo6xNQ_F0runJMiqQ@mail.gmail.com>
On 18:55 Sun 04 Nov , Joachim Eastwood wrote:
> On 4 November 2012 16:52, Jean-Christophe PLAGNIOL-VILLARD
> <plagnioj@jcrosoft.com> wrote:
> > On 19:31 Sun 28 Oct , Joachim Eastwood wrote:
> >> Patch 1 is a fix for a build failure which can happen if board-dt is enabled when no AT91SAM machines are enabled.
> >>
> >> Patch 2 adds DT support to the AT91RM9200 system timer. Based on AT91 PIT patch by Jean-Christophe PLAGNIOL-VILLARD.
> >>
> >> Patch 3 adds clock lookups for DT.
> >>
> >> Patch 4 adds a new board for RM9200 DT support.
> >>
> >> Patch 5-6 adds the base devicetree for AT91RM9200 and support for AT91RM9200-EK board.
> >>
> >>
> >> I don't have a AT91RM9200-EK to test on but I was able to boot at91rm9200ek.dts on my custom board using a >>initrd. As far as I can tell pinctrl, usart and ohci all work.
> >
> > After updating barebox to have the DT support I've tested it on rm9200ek with net support
> >
> > work fine
>
> Excellent.
>
> > It does not apply on my tree as I've a more patch but I'll manage the merge
> > conflict
>
> Thanks for fixing it up Jean-Christophe.
I'll also fix the usb device and add missing nor flash support and emac +
pinctrl + defconfig
Best Regards,
J.
^ permalink raw reply
* [PATCH 0/2 v2] net: at91_ether add dt and pinctrl support
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-11-05 7:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
v2: fix typo in doc + miising empty line
This patch serie add dt and pinctrl support to the at91 ether
this is need to use the network on at91rm9200 as we now have dt
support on it
Jean-Christophe PLAGNIOL-VILLARD (2):
net: at91_ether: add dt support
net: at91_ether: add pinctrl support
Documentation/devicetree/bindings/net/cdns-emac.txt | 23 +++++++++++++++++++++++
drivers/net/ethernet/cadence/at91_ether.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
2 files changed, 100 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/cdns-emac.txt
Best Regards,
J.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 1/2 v2] net: at91_ether: add dt support
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-11-05 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121105073015.GM19021@game.jcrosoft.org>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: netdev at vger.kernel.org
---
.../devicetree/bindings/net/cdns-emac.txt | 23 ++++++
drivers/net/ethernet/cadence/at91_ether.c | 73 ++++++++++++++++++--
2 files changed, 89 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/cdns-emac.txt
diff --git a/Documentation/devicetree/bindings/net/cdns-emac.txt b/Documentation/devicetree/bindings/net/cdns-emac.txt
new file mode 100644
index 0000000..09055c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cdns-emac.txt
@@ -0,0 +1,23 @@
+* Cadence EMAC Ethernet controller
+
+Required properties:
+- compatible: Should be "cdns,[<chip>-]{emac}"
+ Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
+ or the generic form: "cdns,emac".
+- reg: Address and length of the register set for the device
+- interrupts: Should contain macb interrupt
+- phy-mode: String, operation mode of the PHY interface.
+ Supported values are: "mii", "rmii".
+
+Optional properties:
+- local-mac-address: 6 bytes, mac address
+
+Examples:
+
+ macb0: ethernet at fffc4000 {
+ compatible = "cdns,at91rm9200-emac";
+ reg = <0xfffc4000 0x4000>;
+ interrupts = <21>;
+ phy-mode = "rmii";
+ local-mac-address = [3a 0e 03 04 05 06];
+ };
diff --git a/drivers/net/ethernet/cadence/at91_ether.c b/drivers/net/ethernet/cadence/at91_ether.c
index 0d6392d..039e7ef 100644
--- a/drivers/net/ethernet/cadence/at91_ether.c
+++ b/drivers/net/ethernet/cadence/at91_ether.c
@@ -31,6 +31,9 @@
#include <linux/gfp.h>
#include <linux/phy.h>
#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_net.h>
#include "macb.h"
@@ -443,6 +446,50 @@ static const struct net_device_ops at91ether_netdev_ops = {
#endif
};
+#if defined(CONFIG_OF)
+static const struct of_device_id at91ether_dt_ids[] = {
+ { .compatible = "cdns,at91rm9200-emac" },
+ { .compatible = "cdns,emac" },
+ { /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, at91ether_dt_ids);
+
+static int at91ether_get_phy_mode_dt(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+
+ if (np)
+ return of_get_phy_mode(np);
+
+ return -ENODEV;
+}
+
+static int at91ether_get_hwaddr_dt(struct macb *bp)
+{
+ struct device_node *np = bp->pdev->dev.of_node;
+
+ if (np) {
+ const char *mac = of_get_mac_address(np);
+ if (mac) {
+ memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+#else
+static int at91ether_get_phy_mode_dt(struct platform_device *pdev)
+{
+ return -ENODEV;
+}
+static int at91ether_get_hwaddr_dt(struct macb *bp)
+{
+ return -ENODEV;
+}
+#endif
+
/*
* Detect MAC & PHY and perform ethernet interface initialization
*/
@@ -466,7 +513,8 @@ static int __init at91ether_probe(struct platform_device *pdev)
lp = netdev_priv(dev);
lp->pdev = pdev;
lp->dev = dev;
- lp->board_data = *board_data;
+ if (board_data)
+ lp->board_data = *board_data;
spin_lock_init(&lp->lock);
dev->base_addr = regs->start; /* physical base address */
@@ -496,18 +544,28 @@ static int __init at91ether_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, dev);
SET_NETDEV_DEV(dev, &pdev->dev);
- get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
+ res = at91ether_get_hwaddr_dt(lp);
+ if (res < 0)
+ get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
+
update_mac_address(dev); /* Program ethernet address into MAC */
+ res = at91ether_get_phy_mode_dt(pdev);
+ if (res < 0) {
+ if (board_data && board_data->is_rmii)
+ lp->phy_interface = PHY_INTERFACE_MODE_RMII;
+ else
+ lp->phy_interface = PHY_INTERFACE_MODE_MII;
+ } else {
+ lp->phy_interface = res;
+ }
+
macb_writel(lp, NCR, 0);
- if (board_data->is_rmii) {
+ if (lp->phy_interface == PHY_INTERFACE_MODE_RMII)
macb_writel(lp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG) | MACB_BIT(RM9200_RMII));
- lp->phy_interface = PHY_INTERFACE_MODE_RMII;
- } else {
+ else
macb_writel(lp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
- lp->phy_interface = PHY_INTERFACE_MODE_MII;
- }
/* Register the network interface */
res = register_netdev(dev);
@@ -602,6 +660,7 @@ static struct platform_driver at91ether_driver = {
.driver = {
.name = DRV_NAME,
.owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(at91ether_dt_ids),
},
};
--
1.7.10.4
^ permalink raw reply related
* [PATCH 2/2 v2] net: at91_ether: add pinctrl support
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-11-05 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352100892-19936-1-git-send-email-plagnioj@jcrosoft.com>
If no pinctrl available just report a warning as some architecture may not
need to do anything.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: netdev at vger.kernel.org
---
drivers/net/ethernet/cadence/at91_ether.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/net/ethernet/cadence/at91_ether.c b/drivers/net/ethernet/cadence/at91_ether.c
index 039e7ef..6eb928e 100644
--- a/drivers/net/ethernet/cadence/at91_ether.c
+++ b/drivers/net/ethernet/cadence/at91_ether.c
@@ -34,6 +34,7 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_net.h>
+#include <linux/pinctrl/consumer.h>
#include "macb.h"
@@ -501,11 +502,21 @@ static int __init at91ether_probe(struct platform_device *pdev)
struct phy_device *phydev;
struct macb *lp;
int res;
+ struct pinctrl *pinctrl;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs)
return -ENOENT;
+ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+ if (IS_ERR(pinctrl)) {
+ res = PTR_ERR(pinctrl);
+ if (res == -EPROBE_DEFER)
+ return res;
+
+ dev_warn(&pdev->dev, "No pinctrl provided\n");
+ }
+
dev = alloc_etherdev(sizeof(struct macb));
if (!dev)
return -ENOMEM;
--
1.7.10.4
^ permalink raw reply related
* [PATCH v2 1/5] clk: samsung: add common clock framework support for Samsung platforms
From: Thomas Abraham @ 2012-11-05 7:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50905E60.6090005@gmail.com>
Hi Sylwester,
On 31 October 2012 04:40, Sylwester Nawrocki
<sylvester.nawrocki@gmail.com> wrote:
> Hi Thomas,
>
> On 10/29/2012 11:09 AM, Thomas Abraham wrote:
>> Hi Sylwester,
>>
>> Thanks for your comments. As usual, your comments are very helpful.
>
> Thanks.
>> On 22 October 2012 21:25, Sylwester Nawrocki<s.nawrocki@samsung.com> wrote:
>>> Hi Thomas,
>>>
>>> On 10/07/2012 07:10 PM, Thomas Abraham wrote:
>>>> All Samsung platforms include several types of clocks including fixed-rate,
>>>> mux, divider and gate clock types. There are typically hundreds of such clocks
>>>> on each of the Samsung platforms. To enable Samsung platforms to register these
>>>> clocks using the common clock framework, a bunch of utility functions are
>>>> introduced here which simplify the clock registration process.
>>>>
>>>> In addition to the basic types of clock supported by common clock framework,
>>>> a Samsung specific representation of the PLL clocks is also introduced.
>>>>
>>>> Both legacy and device tree based Samsung platforms are supported. On legacy
>>>> platforms, the clocks are statically instantiated and registered with common
>>>> clock framework. On device tree enabled platforms, the device tree is
>>>> searched and all clock nodes found are registered. It is also possible to
>>>> register statically instantiated clocks on device tree enabled platforms.
>>>>
>>>> Cc: Mike Turquette<mturquette@ti.com>
>>>> Cc: Kukjin Kim<kgene.kim@samsung.com>
>>>> Signed-off-by: Thomas Abraham<thomas.abraham@linaro.org>
>>>
>>> Thanks for the patch. I'm trying to use this series on an Exynos4412
>>> SoC based board. I think it wasn't tested with Exynos4x12 (with FDT
>>> support), was it ?
>>
>> No, it has not been tested on any Exynos4x12 based board. I have
>> tested it only for Exynos4210 based origen board.
>
> OK, thanks. I've had some issues with the root clocks on Exynos4412
> and I put this on a back burner for a while. I plan to get back to
> this, possibly after ELCE/LinuxCon.
Ok.
>
>>>> ---
>>>> drivers/clk/Makefile | 1 +
>>>> drivers/clk/samsung/Makefile | 5 +
>>>> drivers/clk/samsung/clk.c | 414 ++++++++++++++++++++++++++++++++++++++++++
>>>> drivers/clk/samsung/clk.h | 212 +++++++++++++++++++++
>>>> 4 files changed, 632 insertions(+), 0 deletions(-)
>>>> create mode 100644 drivers/clk/samsung/Makefile
>>>> create mode 100644 drivers/clk/samsung/clk.c
>>>> create mode 100644 drivers/clk/samsung/clk.h
> ...
>>>> +/* register a samsung pll type clock */
>>>> +void __init samsung_clk_register_pll(const char *name, const char **pnames,
>>>> + struct device_node *np,
>>>> + int (*set_rate)(unsigned long rate),
>>>> + unsigned long (*get_rate)(unsigned long rate))
>>>> +{
>>>> + struct samsung_pll_clock *clk_pll;
>>>> + struct clk *clk;
>>>> + struct clk_init_data init;
>>>> + int ret;
>>>> +
>>>> + clk_pll = kzalloc(sizeof(*clk_pll), GFP_KERNEL);
>>>> + if (!clk_pll) {
>>>> + pr_err("%s: could not allocate pll clk %s\n", __func__, name);
>>>> + return;
>>>> + }
>>>> +
>>>> + init.name = name;
>>>> + init.ops =&samsung_pll_clock_ops;
>>>> + init.flags = CLK_GET_RATE_NOCACHE;
>>>> + init.parent_names = pnames;
>>>> + init.num_parents = 1;
>>>> +
>>>> + clk_pll->set_rate = set_rate;
>>>> + clk_pll->get_rate = get_rate;
>>>> + clk_pll->hw.init =&init;
>>>> +
>>>> + /* register the clock */
>>>> + clk = clk_register(NULL,&clk_pll->hw);
>>>> + if (IS_ERR(clk)) {
>>>> + pr_err("%s: failed to register pll clock %s\n", __func__,
>>>> + name);
>>>> + kfree(clk_pll);
>>>> + return;
>>>> + }
>>>> +
>>>> +#ifdef CONFIG_OF
>>>> + if (np)
>>>> + of_clk_add_provider(np, of_clk_src_simple_get, clk);
>>>> +#endif
>>>
>>> Is it really required to do clk_register() and of_clk_add_provider() for
>>> each single clock ? This seems more heavy than it could be. Looking at
>>
>> of_clk_add_provider call for every clock instance is not really
>> required but it does allow platform code to lookup the clock and
>> retrieve/display the clock speed. That was the intention to add a
>> lookup for all the clocks.
>
> Hmm, do you mean calling clk_get() with NULL 'dev' argument ?
> It's probably not a big deal to look up the clocks root node and
> then use of_clk_get() function to find required clock ?
Yes, I was referring to calling clk_get() with NULL 'dev' argument.
Usually, at boot, the clock frequency of some of the system clocks
(such as aclk_200) are displayed. So all the clocks were registered
using clk_register allowing clock frequency of any the clock to be
retrieved using clk_get.
Your suggestion to use of_clk_get assumes the clock implementation
follows the imx style, which was not way used in this patch series.
And then there is this problem of supporting non-dt platforms as well.
>
>>> drivers/clk/mxs/clk-imx28.c, it registers only single clock provider for
>>> whole group of clocks. Also, couldn't we statically define most of the
>>> clocks and still register them so they can be used with platforms using
>>> FDT ? Something along the lines of imx28 implementation (arch/arm/boot/dts
>>> /imx28.dtsi), where a clock is specified at consumer device node by
>>> a phandle to the clock controller node and a clock index ?
>>
>> We could do it that way. I was tempted to list out all the clocks in
>> device tree and then register them so that there is no static
>> definition of the clocks needed. You seem to prefer not to do that. I
>> am fine with either way, static or device tree based registration.
>
> Ok, it's also worth noting that clk_get() would have been more expensive
> when there would be a need to iterate over large number of clock providers.
> Indexed look up might be a better alternative.
Yes, true.
>
> Exynos SoCs have fairly complex clock tree structure, I personally do find
> it harder to understand from a bit bulky description in form of a device
> tree node list. Comparing to the original Samsung clock API there is now
> more clock objects, since, e.g. single struct clk_clksrc is now represented
> by mux, div and gate clock group, which makes things slightly more
> complicated, i.e. there is even more clocks to be listed.
>
Ok.
>>> Besides that, what bothers me with in the current approach is the
>>> clock consumers being defined through one big data structure together
>>> with the actual clocks. Not all clock objects are going to have
>>> consumers, some resources are waisted by using flat tables of those
>>> big data structure objects. Perhaps we could use two tables, one for the
>>> platform clocks and one for the consumers ? These common clock driver
>>> is intended to cover all Samsung SoC, I would expect all samsung
>>> sub-archs getting converted to use it eventually, with as many of them
>>> as possible then reworked to support device tree. It's a lot of work
>>> and is going to take some time, but it would be good to have it planned
>>> in advance. That said I'm not sure the common samsung clock driver in
>>> non-dt variant would be really a temporary thing.
>>
>> Non-dt support in Samsung common clock driver will be maintained. But
>> for existing Exynos4 non-dt platforms, it should be possible to
>> convert them to completely device tree based platforms.
>
> OK, let's then focus on device tree support for exynos4+ SoCs. I hope we
> could have the clocks statically defined and still freely accessible in
> the device tree.
Ok. I will implement it as you mentioned.
>
>>>> + /*
>>>> + * Register a clock lookup for the pll-type clock even if this
>>>> + * has been instantiated from device tree. This helps to do
>>>> + * clk_get() lookup on this clock for pruposes of displaying its
>>>> + * clock speed at boot time.
>>>> + */
>>>> + ret = clk_register_clkdev(clk, name, NULL);
>>>> + if (ret)
>>>> + pr_err("%s: failed to register clock lookup for %s", __func__,
>>>> + name);
>>>> +}
> ...
>>>> +
>>>> +#ifdef CONFIG_OF
>>>> +/* register a samsung gate type clock instantiated from device tree */
>>>> +void __init samsung_of_clk_register_gate(struct device_node *np)
>>>> +{
>>>> + struct samsung_gate_clock clk_gate;
>>>> + const char *clk_name = np->name;
>>>> + const char *parent_name;
>>>> + u32 reg_info[2];
>>>> +
>>>> + of_property_read_string(np, "clock-output-names",&clk_name);
>>>> + parent_name = of_clk_get_parent_name(np, 0);
>>>> + if (of_property_read_u32_array(np, "reg-info", reg_info, 2))
>>>> + pr_err("%s: invalid register info in node\n", __func__);
>>>> +
>>>> + clk_gate.name = clk_name;
>>>> + clk_gate.parent_name = parent_name;
>>>> + clk_gate.reg = (void __iomem *)(reg_base + reg_info[0]);
>>>> + clk_gate.bit_idx = reg_info[1];
>>>> + clk_gate.dev_name = NULL;
>>>> + clk_gate.flags = 0;
>>>> + clk_gate.gate_flags = 0;
>>>
>>> Some clocks need CLK_SET_RATE_PARENT for the drivers to work
>>> as before. So far it is not set for any mux, div nor gate clock.
>>
>> Ok. I will fix this.
>>
>> So about the static vs device tree based clock registration, what
>> would you suggest?
>
> Defining the clocks statically has my preference, it would be nice to
> hear more opinions on that though. I think on a heavily utilised SoC
> the list of clock nodes could have grown significantly. And with
> preprocessor support at the dt compiler (not sure if it is already
> there) indexed clock definitions could be made more explicit.
>
> These are roughly our conclusions from discussing this patch series
> with Tomasz F.
Ok. Thanks for your comments. I will redo this patch series and post them.
Thanks,
Thomas.
>
> --
> Thanks,
> Sylwester
^ permalink raw reply
* [PATCH 1/1] usb: at91_udc: fix typo on vubs pullup valid check
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-11-05 7:39 UTC (permalink / raw)
To: linux-arm-kernel
if the gpio is not valid complain
since 3285e0ec088febc5a88f57ddd78385a7da71476c
ARM: at91/udc: use gpio_is_valid to check the gpio
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: linux-usb at vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
Hi Greg,
this is broken since 3.2 can we have on the stable too
Best Regards,
J.
drivers/usb/gadget/at91_udc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 89d90b5..888cb2a 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -1739,7 +1739,7 @@ static int __devinit at91udc_probe(struct platform_device *pdev)
/* rm9200 needs manual D+ pullup; off by default */
if (cpu_is_at91rm9200()) {
- if (gpio_is_valid(udc->board.pullup_pin)) {
+ if (!gpio_is_valid(udc->board.pullup_pin)) {
DBG("no D+ pullup?\n");
retval = -ENODEV;
goto fail0;
--
1.7.10.4
^ permalink raw reply related
* [PATCH v2 1/5] clk: samsung: add common clock framework support for Samsung platforms
From: Thomas Abraham @ 2012-11-05 7:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9262175.YChVmHd9ev@flatron>
Hi Tomasz,
On 31 October 2012 05:02, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Thomas, Sylwester,
>
> On Wednesday 31 of October 2012 00:10:24 Sylwester Nawrocki wrote:
>> >>> +/* register a samsung pll type clock */
>> >>> +void __init samsung_clk_register_pll(const char *name, const char
>> >>> **pnames, + struct device_node *np,
>> >>> + int (*set_rate)(unsigned long rate),
>> >>> + unsigned long (*get_rate)(unsigned long
>> >>> rate)) +{
>> >>> + struct samsung_pll_clock *clk_pll;
>> >>> + struct clk *clk;
>> >>> + struct clk_init_data init;
>> >>> + int ret;
>> >>> +
>> >>> + clk_pll = kzalloc(sizeof(*clk_pll), GFP_KERNEL);
>> >>> + if (!clk_pll) {
>> >>> + pr_err("%s: could not allocate pll clk %s\n", __func__,
>> >>> name); + return;
>> >>> + }
>> >>> +
>> >>> + init.name = name;
>> >>> + init.ops =&samsung_pll_clock_ops;
>> >>> + init.flags = CLK_GET_RATE_NOCACHE;
>> >>> + init.parent_names = pnames;
>> >>> + init.num_parents = 1;
>> >>> +
>> >>> + clk_pll->set_rate = set_rate;
>> >>> + clk_pll->get_rate = get_rate;
>> >>> + clk_pll->hw.init =&init;
>> >>> +
>> >>> + /* register the clock */
>> >>> + clk = clk_register(NULL,&clk_pll->hw);
>> >>> + if (IS_ERR(clk)) {
>> >>> + pr_err("%s: failed to register pll clock %s\n",
>> >>> __func__,
>> >>> + name);
>> >>> + kfree(clk_pll);
>> >>> + return;
>> >>> + }
>> >>> +
>> >>> +#ifdef CONFIG_OF
>> >>> + if (np)
>> >>> + of_clk_add_provider(np, of_clk_src_simple_get, clk);
>> >>> +#endif
>> >>
>> >> Is it really required to do clk_register() and of_clk_add_provider()
>> >> for
>> >> each single clock ? This seems more heavy than it could be. Looking at
>> >
>> > of_clk_add_provider call for every clock instance is not really
>> > required but it does allow platform code to lookup the clock and
>> > retrieve/display the clock speed. That was the intention to add a
>> > lookup for all the clocks.
>
> I'm not really sure if displaying clock speed is really a good
> justification for increasing the list of system clocks almost by a factor
> of three. This will make clock lookup a bit heavy.
>
> You might display speed of several most important clocks directly from the
> samsung clk driver using internal data, without the need of involving
> generic clock lookup for this purpose.
Ok. But that would mean that we implment the clk_get_rate() function
for such clocks again. For example, to get the rate of the aclk_200
clock, its parent clock would have to be divided and then displayed.
But it was easier to just use the clk_get api. But yes I agree, this
is not a compelling reason to register all the clocks.
>
>>
>> Hmm, do you mean calling clk_get() with NULL 'dev' argument ?
>> It's probably not a big deal to look up the clocks root node and
>> then use of_clk_get() function to find required clock ?
>
> I believe that the intention was for it to work on non-DT platforms as
> well. However I might have misunderstood your suggestion, could you
> elaborate?
>
>> >> drivers/clk/mxs/clk-imx28.c, it registers only single clock provider
>> >> for
>> >> whole group of clocks. Also, couldn't we statically define most of the
>> >> clocks and still register them so they can be used with platforms
>> >> using
>> >> FDT ? Something along the lines of imx28 implementation
>> >> (arch/arm/boot/dts /imx28.dtsi), where a clock is specified at
>> >> consumer device node by a phandle to the clock controller node and a
>> >> clock index ?
>> >
>> > We could do it that way. I was tempted to list out all the clocks in
>> > device tree and then register them so that there is no static
>> > definition of the clocks needed. You seem to prefer not to do that. I
>> > am fine with either way, static or device tree based registration.
>>
>> Ok, it's also worth noting that clk_get() would have been more expensive
>> when there would be a need to iterate over large number of clock
>> providers. Indexed look up might be a better alternative.
>
> I'm definitely for indexed lookup. With the ability to define constants in
> device tree sources the main drawback of this solution being less readable
> now disappeared and everything left are advantages.
Ok.
>
>> Exynos SoCs have fairly complex clock tree structure, I personally do
>> find it harder to understand from a bit bulky description in form of a
>> device tree node list. Comparing to the original Samsung clock API there
>> is now more clock objects, since, e.g. single struct clk_clksrc is now
>> represented by mux, div and gate clock group, which makes things
>> slightly more complicated, i.e. there is even more clocks to be listed.
>
> If it's about readability I tend to disagree. I find device tree much more
> readable as a way of describing hardware than hardcoded data structures,
> often using complex macros to keep the definitions short.
>
>> >> Besides that, what bothers me with in the current approach is the
>> >> clock consumers being defined through one big data structure together
>> >> with the actual clocks. Not all clock objects are going to have
>> >> consumers, some resources are waisted by using flat tables of those
>> >> big data structure objects. Perhaps we could use two tables, one for
>> >> the
>> >> platform clocks and one for the consumers ? These common clock driver
>> >> is intended to cover all Samsung SoC, I would expect all samsung
>> >> sub-archs getting converted to use it eventually, with as many of them
>> >> as possible then reworked to support device tree. It's a lot of work
>> >> and is going to take some time, but it would be good to have it
>> >> planned
>> >> in advance. That said I'm not sure the common samsung clock driver in
>> >> non-dt variant would be really a temporary thing.
>> >
>> > Non-dt support in Samsung common clock driver will be maintained. But
>> > for existing Exynos4 non-dt platforms, it should be possible to
>> > convert them to completely device tree based platforms.
>>
>> OK, let's then focus on device tree support for exynos4+ SoCs. I hope we
>> could have the clocks statically defined and still freely accessible in
>> the device tree.
>
> Using the approach with indexed clocks inside a single provider would allow
> to reuse the same internal SoC-specific data for both DT and non-DT
> variants, without any data duplication. This is definitely an advantage.
Ok.
>
>> >>> +
>> >>> +#ifdef CONFIG_OF
>> >>> +/* register a samsung gate type clock instantiated from device tree
>> >>> */
>> >>> +void __init samsung_of_clk_register_gate(struct device_node *np)
>> >>> +{
>> >>> + struct samsung_gate_clock clk_gate;
>> >>> + const char *clk_name = np->name;
>> >>> + const char *parent_name;
>> >>> + u32 reg_info[2];
>> >>> +
>> >>> + of_property_read_string(np, "clock-output-names",&clk_name);
>> >>> + parent_name = of_clk_get_parent_name(np, 0);
>> >>> + if (of_property_read_u32_array(np, "reg-info", reg_info, 2))
>> >>> + pr_err("%s: invalid register info in node\n",
>> >>> __func__);
>> >>> +
>> >>> + clk_gate.name = clk_name;
>> >>> + clk_gate.parent_name = parent_name;
>> >>> + clk_gate.reg = (void __iomem *)(reg_base + reg_info[0]);
>> >>> + clk_gate.bit_idx = reg_info[1];
>> >>> + clk_gate.dev_name = NULL;
>> >>> + clk_gate.flags = 0;
>> >>> + clk_gate.gate_flags = 0;
>> >>
>> >> Some clocks need CLK_SET_RATE_PARENT for the drivers to work
>> >> as before. So far it is not set for any mux, div nor gate clock.
>> >
>> > Ok. I will fix this.
>> >
>> > So about the static vs device tree based clock registration, what
>> > would you suggest?
>>
>> Defining the clocks statically has my preference, it would be nice to
>> hear more opinions on that though. I think on a heavily utilised SoC
>> the list of clock nodes could have grown significantly. And with
>> preprocessor support at the dt compiler (not sure if it is already
>> there) indexed clock definitions could be made more explicit.
>>
>> These are roughly our conclusions from discussing this patch series
>> with Tomasz F.
>
> Yes, as I said, I'm definitely for the single clock provider approach (aka
> imx-like approach).
Ok. Thanks for your comments. I will redo this patch series.
Thanks,
Thomas.
>
> Best regards,
> Tomasz Figa
>
^ permalink raw reply
* [PATCHv2 0/7] i2c: omap: updates
From: Felipe Balbi @ 2012-11-05 7:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352025873-27492-1-git-send-email-shubhrajyoti@ti.com>
HI,
On Sun, Nov 04, 2012 at 04:14:26PM +0530, Shubhrajyoti D wrote:
> Does the followiing
> - Make the revision a 32- bit consisting of rev_lo amd rev_hi each
> of 16 bits.
>
> - Also use the revision register for the erratum i207.
> - Refactor the i2c_omap_init code.
>
>
> Also more cleanup is possible will check on that subsequently.
>
>
> Tested on OMAP4430sdp ,4460 ,omap3630 ,3430 and omap2430.
>
> For omap2 testing the below patch was used
> [PATCH] ARM: vfp: fix save and restore when running on pre-VFPv3 and CONFIG_VFPv3 set
>
> Also for using the pm testing below patches are used.
>
> arm: sched: stop sched_clock() during suspend
> ARM: OMAP: hwmod: wait for sysreset complete after enabling hwmod
>
> Also available through
> git://gitorious.org/linus-tree/linus-tree.git i2c_omap/for_3.8
>
>
> Shubhrajyoti D (7):
> i2c: omap: Fix the revision register read
> i2c: omap: use revision check for OMAP_I2C_FLAG_APPLY_ERRATA_I207
> i2c: omap: remove the dtrev
> ARM: i2c: omap: Remove the i207 errata flag
> i2c: omap: re-factor omap_i2c_init function
> i2c: omap: make reset a seperate function
> i2c: omap: Restore i2c context always
>
> arch/arm/mach-omap2/omap_hwmod_2430_data.c | 3 +-
> arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 9 +-
> drivers/i2c/busses/i2c-omap.c | 166 +++++++++++++++++-----------
> include/linux/i2c-omap.h | 1 -
> 4 files changed, 104 insertions(+), 75 deletions(-)
since I have reviewed your previous version, it would be nice to Cc me
so I don't loose your series ;-)
--
balbi
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^ permalink raw reply
* [PATCH 3/5] ARM: Exynos: add device tree support for MCT controller driver
From: Thomas Abraham @ 2012-11-05 7:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50954B60.2090500@gmail.com>
Hi Sylwester,
Thanks for your comments.
On 3 November 2012 22:20, Sylwester Nawrocki
<sylvester.nawrocki@gmail.com> wrote:
> Hi Thomas,
>
>
> On 11/03/2012 03:45 PM, Thomas Abraham wrote:
>>
>> Allow the MCT controller base address and interrupts to be obtained from
>> device tree and remove unused static definitions of these. The non-dt
>> support
>> for Exynos5250 is removed but retained for Exynos4210 based platforms.
>>
>> Cc: Changhwan Youn<chaos.youn@samsung.com>
>> Signed-off-by: Thomas Abraham<thomas.abraham@linaro.org>
>> ---
>> .../bindings/timer/samsung,exynos4210-mct.txt | 70
>> ++++++++++++++++++++
>> arch/arm/mach-exynos/include/mach/irqs.h | 6 --
>> arch/arm/mach-exynos/mct.c | 42 ++++++++----
>> 3 files changed, 99 insertions(+), 19 deletions(-)
>> create mode 100644
>> Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
>>
>> diff --git
>> a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
>> b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
>> new file mode 100644
>> index 0000000..c53fd93
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
>> @@ -0,0 +1,70 @@
>> +Samsung's Multi Core Timer (MCT)
>> +
>> +The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
>> +global timer and CPU local timers. The global timer is a 64-bit free
>> running
>> +up-counter and can generate 4 interrupts when the counter reaches one of
>> the
>> +four preset counter values. The CPU local timers are 32-bit free running
>> +down-counters and generates an interrupt when the counter expires. There
>> is
>
>
> s/generates/generate ?
Ok.
>
>
>> +one CPU local timer instantiated in MCT for every CPU in the system.
>> +
>> +Required properties:
>> +
>> +- compatible: should be "samsung,exynos4210-mct".
>> +- reg: base address of the mct controller and length of the address space
>> + it occupies.
>> +- interrupts: the list of interrupts generated by the controller. The
>> following
>> + should be the order of the interrupts specified. The local timer
>> interrupts
>> + should be specified after the four global timer interrupts have been
>> + specified.
>> +
>> + 0: Global Timer Interrupt 0
>> + 1: Global Timer Interrupt 1
>> + 2: Global Timer Interrupt 2
>> + 3: Global Timer Interrupt 3
>> + 4: Local Timer Interrupt 0
>> + 5: Local Timer Interrupt 1
>> + 6: ..
>> + 7: ..
>> + i: Local Timer Interrupt n
>> +
>> +- samsung,mct-nr-local-irqs: The number of local timer interrupts
>> supported
>> + by the MCT controller.
>> +
>> +Example 1: In this example, the system uses only the first global timer
>> + interrupt generated by MCT and the remaining three global timer
>> + interrupts are unused. Two local timer interrupts have been
>> + specified.
>> +
>> + mct at 10050000 {
>> + compatible = "samsung,exynos4210-mct";
>> + reg =<0x10050000 0x800>;
>> + interrupts =<0 57 0>,<0 0 0>,<0 0 0>,<0 0 0>,
>> + <0 42 0>,<0 48 0>;
>> + samsung,mct-nr-local-irqs =<4>;
>
>
> Then this means the MCT supports 4 local interrupts but only 2 are
> specified here ? Doesn't the code below expect
>
> samsung,mct-nr-local-irqs = <2>;
>
> in this case ? Or should interrupts really be
>
>
> interrupts =<0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
> <0 42 0>, <0 48 0>, <0 0 0>, <0 0 0>;
>
> ?
No, that was a typo. It should be samsung,mct-nr-local-irqs = <2>.
Thanks for spotting this.
>>
>> + };
>> +
>> +Example 2: In this example, the MCT global and local timer interrupts are
>> + connected to two seperate interrupt controllers. Hence, an
>> + interrupt-map is created to map the interrupts to the
>> respective
>> + interrupt controllers.
>> +
>> + mct at 101C0000 {
>> + compatible = "samsung,exynos4210-mct";
>> + reg =<0x101C0000 0x800>;
>> + interrupt-controller;
>> + #interrups-cells =<2>;
>> + interrupt-parent =<&mct_map>;
>> + interrupts =<0 0>,<1 0>,<2 0>,<3 0>,
>> + <4 0>,<5 0>;
>> + samsung,mct-nr-local-irqs =<2>;
>
>
> Here the samsung,mct-nr-local-irqs' value matches what's specified in the
> interrupts property.
>
>
>> +
>> + mct_map: mct-map {
>> + compatible = "samsung,mct-map";
>
>
> Do we need a compatible property in sub-nodes like this one ?
> Wouldn't it be sufficient to reference this node, for example by name ?
Yes, it is not really required. I will remove it.
>
>> + #interrupt-cells =<2>;
>> + #address-cells =<0>;
>> + #size-cells =<0>;
>> + interrupt-map =<0x0 0&combiner 23 3>,
>> + <0x4 0&gic 0 120 0>,
>> + <0x5 0&gic 0 121 0>;
>>
>> + };
>> + };
>> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
>> b/arch/arm/mach-exynos/include/mach/irqs.h
>> index 6da3115..03c9f04 100644
>> --- a/arch/arm/mach-exynos/include/mach/irqs.h
>> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
>> @@ -30,8 +30,6 @@
>>
>> /* For EXYNOS4 and EXYNOS5 */
>>
>> -#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
>> -
>> #define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
>>
>> /* For EXYNOS4 SoCs */
>> @@ -320,8 +318,6 @@
>> #define EXYNOS5_IRQ_CEC IRQ_SPI(114)
>> #define EXYNOS5_IRQ_SATA IRQ_SPI(115)
>>
>> -#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
>> -#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
>> #define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
>> #define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
>> #define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
>> @@ -411,8 +407,6 @@
>> #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
>>
>> #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
>> -#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
>> -#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
>>
>> #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
>> #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
>> diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
>> index d65d0c7..f7792b8 100644
>> --- a/arch/arm/mach-exynos/mct.c
>> +++ b/arch/arm/mach-exynos/mct.c
>> @@ -19,6 +19,9 @@
>> #include<linux/platform_device.h>
>> #include<linux/delay.h>
>> #include<linux/percpu.h>
>> +#include<linux/of.h>
>> +#include<linux/of_irq.h>
>> +#include<linux/of_address.h>
>>
>> #include<asm/hardware/gic.h>
>> #include<asm/localtimer.h>
>> @@ -483,14 +486,16 @@ static struct local_timer_ops exynos4_mct_tick_ops
>> __cpuinitdata = {
>> };
>> #endif /* CONFIG_LOCAL_TIMERS */
>>
>> -static void __init exynos4_timer_resources(void)
>> +static void __init exynos4_timer_resources(struct device_node *np)
>> {
>> struct clk *mct_clk;
>> mct_clk = clk_get(NULL, "xtal");
>>
>> clk_rate = clk_get_rate(mct_clk);
>>
>> - reg_base = S5P_VA_SYSTIMER;
>> + reg_base = (np) ? of_iomap(np, 0) : S5P_VA_SYSTIMER;
>
>
> nit: Parentheses around np look redundant.
Ok.
>
>
>> + if (!reg_base)
>> + panic("%s: unable to ioremap mct address space\n",
>> __func__);
>
>
> How about adding a line like:
>
> #define pr_fmt(fmt) "%s: " fmt, __func__
>
> on top of this file and dropping "%s: " and __func__ in those panic() calls
> ? It would make the logs more consistent across whole file.
Ok.
>
>
>> #ifdef CONFIG_LOCAL_TIMERS
>> if (mct_int_type == MCT_INT_PPI) {
>> @@ -509,23 +514,34 @@ static void __init exynos4_timer_resources(void)
>>
>> static void __init exynos4_timer_init(void)
>> {
>> - if (soc_is_exynos4210()) {
>> + struct device_node *np;
>> + u32 nr_irqs, i;
>> +
>> + np = of_find_compatible_node(NULL, NULL,
>> "samsung,exynos4210-mct");
>> + if (np) {
>> + if (of_machine_is_compatible("samsung,exynos4210") ||
>> + of_machine_is_compatible("samsung,exynos5250"))
>> + mct_int_type = MCT_INT_SPI;
>> + else
>> + mct_int_type = MCT_INT_PPI;
>
>
> Does it make sense to specify this mct_int_type as a property of
> the mct node ?
The MCT bindings are independent of the system integration details.
There could be a system that uses MCT controller but not GIC
controller.
Thanks,
Thomas.
^ permalink raw reply
* [PATCH 1/1] usb: at91_udc: fix typo on vubs pullup valid check
From: Greg Kroah-Hartman @ 2012-11-05 7:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352101183-20606-1-git-send-email-plagnioj@jcrosoft.com>
On Mon, Nov 05, 2012 at 08:39:43AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> if the gpio is not valid complain
>
> since 3285e0ec088febc5a88f57ddd78385a7da71476c
> ARM: at91/udc: use gpio_is_valid to check the gpio
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> Cc: linux-usb at vger.kernel.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> Hi Greg,
>
> this is broken since 3.2 can we have on the stable too
Sure, but you should be sending gadget patches to Felipe, not me, as
he's in charge of that tree. So I suggest you resend this, cc: Felipe
and add the proper stable tree marking to the Cc: area of the
signed-off-by: part of the patch, like the file
Documentation/stable_kernel_rules.txt describes to do. That way it will
be picked up automatically for the stable releases when it gets in to
Linus's tree.
thanks,
greg k-h
^ permalink raw reply
* [PATCHv2 1/7] i2c: omap: Fix the revision register read
From: Felipe Balbi @ 2012-11-05 7:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352025873-27492-2-git-send-email-shubhrajyoti@ti.com>
Hi,
On Sun, Nov 04, 2012 at 04:14:27PM +0530, Shubhrajyoti D wrote:
> The revision register on OMAP4 is a 16-bit lo and a 16-bit
> hi. Currently the driver reads only the lower 8-bits.
> Fix the same by preventing the truncating of the rev register
> for OMAP4.
>
> Also use the scheme bit ie bit-14 of the hi register to know if it
> is OMAP_I2C_IP_VERSION_2.
>
> On platforms previous to OMAP4 the offset 0x04 is IE register whose
> bit-14 reset value is 0, the code uses the same to its advantage.
>
> Also since the omap_i2c_read_reg uses reg_map_ip_* a raw_readw is done
> to fetch the revision register.
>
> The dev->regs is populated after reading the rev_hi. A NULL check
> has been added in the resume handler to prevent the access before
> the setting of the regs.
>
> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
> ---
> drivers/i2c/busses/i2c-omap.c | 61 ++++++++++++++++++++++++++++++++---------
> 1 files changed, 48 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index db31eae..72fce6d 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -49,9 +49,10 @@
> #define OMAP_I2C_OMAP1_REV_2 0x20
>
> /* I2C controller revisions present on specific hardware */
> -#define OMAP_I2C_REV_ON_2430 0x36
> -#define OMAP_I2C_REV_ON_3430_3530 0x3C
> -#define OMAP_I2C_REV_ON_3630_4430 0x40
> +#define OMAP_I2C_REV_ON_2430 0x00000036
> +#define OMAP_I2C_REV_ON_3430_3530 0x0000003C
> +#define OMAP_I2C_REV_ON_3630 0x00000040
> +#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
>
> /* timeout waiting for the controller to respond */
> #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
> @@ -202,7 +203,7 @@ struct omap_i2c_dev {
> * fifo_size==0 implies no fifo
> * if set, should be trsh+1
> */
> - u8 rev;
> + u32 rev;
> unsigned b_hw:1; /* bad h/w fixes */
> unsigned receiver:1; /* true when we're in receiver mode */
> u16 iestate; /* Saved interrupt register */
> @@ -490,7 +491,7 @@ static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
>
> omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
>
> - if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
> + if (dev->rev < OMAP_I2C_REV_ON_3630)
> dev->b_hw = 1; /* Enable hardware fixes */
>
> /* calculate wakeup latency constraint for MPU */
> @@ -1052,6 +1053,16 @@ static const struct of_device_id omap_i2c_of_match[] = {
> MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
> #endif
>
> +#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
> +
> +#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
> +#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
> +
> +#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
> +#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
> +#define OMAP_I2C_SCHEME_0 0
> +#define OMAP_I2C_SCHEME_1 1
> +
> static int __devinit
> omap_i2c_probe(struct platform_device *pdev)
> {
> @@ -1064,6 +1075,8 @@ omap_i2c_probe(struct platform_device *pdev)
> const struct of_device_id *match;
> int irq;
> int r;
> + u32 rev;
> + u16 minor, major;
>
> /* NOTE: driver uses the static register mapping */
> mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> @@ -1117,11 +1130,6 @@ omap_i2c_probe(struct platform_device *pdev)
>
> dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
>
> - if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
> - dev->regs = (u8 *)reg_map_ip_v2;
> - else
> - dev->regs = (u8 *)reg_map_ip_v1;
> -
> pm_runtime_enable(dev->dev);
> pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
> pm_runtime_use_autosuspend(dev->dev);
> @@ -1130,7 +1138,31 @@ omap_i2c_probe(struct platform_device *pdev)
> if (IS_ERR_VALUE(r))
> goto err_free_mem;
>
> - dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
> + /*
> + * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
> + * On omap3 Offset 4 is IE Reg the bit [15:14] is XDR_IE which is 0
comment is wrong. You talk about 2 bits and document only one of them.
Also, this is valid for all OMAPs until OMAP3, comment should probably
read: On OMAP1/2/3 offset 0x04 is.....
> + * at reset. Also since the omap_i2c_read_reg uses reg_map_ip_* a
> + * raw_readw is done.
> + */
> + rev = __raw_readw(dev->base + 0x04);
> +
> + switch (OMAP_I2C_SCHEME(rev)) {
> + case OMAP_I2C_SCHEME_0:
> + dev->regs = (u8 *)reg_map_ip_v1;
> + dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
drop the 0xff. Top byte is supposed to be zero and if it's not, we want
to know what they hold.
> + minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
> + major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
> + break;
> + case OMAP_I2C_SCHEME_1:
> + /* FALLTHROUGH */
> + default:
> + dev->regs = (u8 *)reg_map_ip_v2;
> + rev = (rev << 16) |
> + omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
> + minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
> + major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
> + dev->rev = rev;
> + }
>
> dev->errata = 0;
>
> @@ -1155,7 +1187,7 @@ omap_i2c_probe(struct platform_device *pdev)
>
> dev->fifo_size = (dev->fifo_size / 2);
>
> - if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
> + if (dev->rev < OMAP_I2C_REV_ON_3630)
> dev->b_hw = 1; /* Enable hardware fixes */
looks like this was applicable to 4430 too, what happened ?
--
balbi
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* [PATCHv2 2/7] i2c: omap: use revision check for OMAP_I2C_FLAG_APPLY_ERRATA_I207
From: Felipe Balbi @ 2012-11-05 7:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352025873-27492-3-git-send-email-shubhrajyoti@ti.com>
On Sun, Nov 04, 2012 at 04:14:28PM +0530, Shubhrajyoti D wrote:
> The errata i207 is enabled for 2430 and 3xxx. Use the revision check
> to enable the erratum instead.
>
> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
> ---
> drivers/i2c/busses/i2c-omap.c | 3 ++-
> 1 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 72fce6d..e009985 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -1166,7 +1166,8 @@ omap_i2c_probe(struct platform_device *pdev)
>
> dev->errata = 0;
>
> - if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
> + if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
> + dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
> dev->errata |= I2C_OMAP_ERRATA_I207;
>
> if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
> --
> 1.7.5.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
balbi
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* [PATCHv2 3/7] i2c: omap: remove the dtrev
From: Felipe Balbi @ 2012-11-05 7:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352025873-27492-4-git-send-email-shubhrajyoti@ti.com>
Hi,
On Sun, Nov 04, 2012 at 04:14:29PM +0530, Shubhrajyoti D wrote:
> The dtrev is used only for the comments. Remove the same and use
> the scheme instead to know if it is version2.
>
> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
I would drop dtrev completely and not use scheme to "emulate" it. dtrev
is wrong and unnecessary; it was only created due to the wrong
assumption that HW revision register was wrong. Looks like that
assumption was made based on the driver which is clearly wrong wrt
revision detection.
Also, when dropping dtrev, also drop it from platform_data and
omap_hwmod database (could be done on a separate patch).
--
balbi
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* [PATCHv2 4/7] ARM: i2c: omap: Remove the i207 errata flag
From: Felipe Balbi @ 2012-11-05 7:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352025873-27492-5-git-send-email-shubhrajyoti@ti.com>
On Sun, Nov 04, 2012 at 04:14:30PM +0530, Shubhrajyoti D wrote:
> The commit [i2c: omap: use revision check for OMAP_I2C_FLAG_APPLY_ERRATA_I207]
> uses the revision id instead of the flag. So the flag can be safely removed.
>
> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod_2430_data.c | 3 +--
> arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 9 +++------
> drivers/i2c/busses/i2c-omap.c | 3 +--
> include/linux/i2c-omap.h | 1 -
> 4 files changed, 5 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
> index c455e41..b79ccf6 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
> @@ -76,8 +76,7 @@ static struct omap_hwmod_class i2c_class = {
>
> static struct omap_i2c_dev_attr i2c_dev_attr = {
> .fifo_depth = 8, /* bytes */
> - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
> - OMAP_I2C_FLAG_BUS_SHIFT_2 |
> + .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
> OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
> };
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
> index f67b7ee..943222c4 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
> @@ -791,8 +791,7 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
> /* I2C1 */
> static struct omap_i2c_dev_attr i2c1_dev_attr = {
> .fifo_depth = 8, /* bytes */
> - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
> - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
> + .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
> OMAP_I2C_FLAG_BUS_SHIFT_2,
> };
>
> @@ -818,8 +817,7 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
> /* I2C2 */
> static struct omap_i2c_dev_attr i2c2_dev_attr = {
> .fifo_depth = 8, /* bytes */
> - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
> - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
> + .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
> OMAP_I2C_FLAG_BUS_SHIFT_2,
> };
>
> @@ -845,8 +843,7 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
> /* I2C3 */
> static struct omap_i2c_dev_attr i2c3_dev_attr = {
> .fifo_depth = 64, /* bytes */
> - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
> - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
> + .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
> OMAP_I2C_FLAG_BUS_SHIFT_2,
> };
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index b62cd9d..8a54efc 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -1029,8 +1029,7 @@ static const struct i2c_algorithm omap_i2c_algo = {
> #ifdef CONFIG_OF
> static struct omap_i2c_bus_platform_data omap3_pdata = {
> .rev = OMAP_I2C_IP_VERSION_1,
> - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
> - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
> + .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
> OMAP_I2C_FLAG_BUS_SHIFT_2,
> };
>
> diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h
> index df804ba..5c88187 100644
> --- a/include/linux/i2c-omap.h
> +++ b/include/linux/i2c-omap.h
> @@ -21,7 +21,6 @@
> #define OMAP_I2C_FLAG_SIMPLE_CLOCK BIT(1)
> #define OMAP_I2C_FLAG_16BIT_DATA_REG BIT(2)
> #define OMAP_I2C_FLAG_RESET_REGS_POSTIDLE BIT(3)
> -#define OMAP_I2C_FLAG_APPLY_ERRATA_I207 BIT(4)
> #define OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK BIT(5)
> #define OMAP_I2C_FLAG_FORCE_19200_INT_CLK BIT(6)
> /* how the CPU address bus must be translated for I2C unit access */
> --
> 1.7.5.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
balbi
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