* [PATCH 2/2] Input: nomadik-ske-keypad - start using the apb_pclk
From: Ulf Hansson @ 2012-11-05 12:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdbZB4nhFQtLH-GxBSK99RFk7yhSYMhO5keVjyugrqr7JA@mail.gmail.com>
On 4 November 2012 19:12, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Thu, Nov 1, 2012 at 3:20 PM, Ulf Hansson <ulf.hansson@stericsson.com> wrote:
>
>> From: Ulf Hansson <ulf.hansson@linaro.org>
>>
>> Previously this clock was handled internally by the clockdriver,
>> but now this is separate clk. So we need take care of it.
>>
>> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
>
> So this is a silicon block clock and falls into the category of things
> we've been discussing...
>
> If I understand correctly, the only "real" solution is to
> implement the PM domains and have these enable the clocks.
Agree.
Although, since the pm_domain not yet exist, this as a way forward for
now - to fix what is broken.
When the pm_domain is in place and when we decide to fold in the clock
handling in there, we can move it.
>
> An alternative may be to move this driver over to the AMBA bus,
> because I think this device actually has primecell registers.
> Then the bus will take care of the pclk for starters.
You are definitely right, this driver can be converted into using the AMBA bus.
Although, do you think that should be done _instead_ of going ahead
with this patch or do you want that to be handled as a next and a
separate step?
Kind regards
Ulf Hansson
^ permalink raw reply
* [PATCHv3 8/8] i2c: omap: cleanup the sysc write
From: Shubhrajyoti D @ 2012-11-05 12:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352118223-3796-1-git-send-email-shubhrajyoti@ti.com>
Currently after the reset the sysc is written with hardcoded values.
The patch reads the sysc register and writes back the same value
after reset.
- Some unnecessary rev checks can be optimised.
- Also due to whatever reason the hwmod flags are changed
we will not reset the values.
- In some of the cases the minor values of the 2430 register
is different(0x37) in that case the autoidle setting may be missed.
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
---
drivers/i2c/busses/i2c-omap.c | 20 +++++---------------
1 files changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 25f1564..a09acdc 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -302,7 +302,11 @@ static void __omap_i2c_init(struct omap_i2c_dev *dev)
static int omap_i2c_reset(struct omap_i2c_dev *dev)
{
unsigned long timeout;
+ u16 sysc;
+
if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
+ sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);
+
/* Disable I2C controller before soft reset */
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
@@ -324,22 +328,8 @@ static int omap_i2c_reset(struct omap_i2c_dev *dev)
}
/* SYSC register is cleared by the reset; rewrite it */
- if (dev->rev == OMAP_I2C_REV_ON_2430) {
-
- omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
- SYSC_AUTOIDLE_MASK);
+ omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
- } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
- dev->syscstate = SYSC_AUTOIDLE_MASK;
- dev->syscstate |= SYSC_ENAWAKEUP_MASK;
- dev->syscstate |= (SYSC_IDLEMODE_SMART <<
- __ffs(SYSC_SIDLEMODE_MASK));
- dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
- __ffs(SYSC_CLOCKACTIVITY_MASK));
-
- omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
- dev->syscstate);
- }
}
return 0;
}
--
1.7.5.4
^ permalink raw reply related
* [PATCHv3 7/8] i2c: omap: Restore i2c context always
From: Shubhrajyoti D @ 2012-11-05 12:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352118223-3796-1-git-send-email-shubhrajyoti@ti.com>
Currently the restore is done based on the flag
OMAP_I2C_FLAG_RESET_REGS_POSTIDLE.
This helps the following
- The driver is always capable of restoring regardless
of the off mode support being there or not.
- While testing omap2430 it is found that in case of certain
error paths (timeout) a reset is done. However the restore
never happens as it is dependent on the POSTIDLE flag.
The other option would be to call a restore in the reset
case. As there are only a few registers to be restored
the penalty in the idle case should not be much.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
---
Todo: the flag could be deleted if the patch is accepted.
drivers/i2c/busses/i2c-omap.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 7393017..25f1564 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1316,8 +1316,7 @@ static int omap_i2c_runtime_resume(struct device *dev)
if (!_dev->regs)
return 0;
- if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE)
- __omap_i2c_init(_dev);
+ __omap_i2c_init(_dev);
return 0;
}
--
1.7.5.4
^ permalink raw reply related
* [PATCHv3 6/8] i2c: omap: make reset a seperate function
From: Shubhrajyoti D @ 2012-11-05 12:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352118223-3796-1-git-send-email-shubhrajyoti@ti.com>
Implement reset as a separate function.
This will enable us to make sure that we don't do the
calculation again on every transfer.
Also at probe the reset is not added as the hwmod is doing that
for us.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
---
todo: reprodue the errors and optimise the reset if possible
drivers/i2c/busses/i2c-omap.c | 39 ++++++++++++++++++++++++---------------
1 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 393bb22..7393017 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -299,15 +299,9 @@ static void __omap_i2c_init(struct omap_i2c_dev *dev)
omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
}
-static int omap_i2c_init(struct omap_i2c_dev *dev)
+static int omap_i2c_reset(struct omap_i2c_dev *dev)
{
- u16 psc = 0, scll = 0, sclh = 0;
- u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
- unsigned long fclk_rate = 12000000;
unsigned long timeout;
- unsigned long internal_clk = 0;
- struct clk *fclk;
-
if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
/* Disable I2C controller before soft reset */
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
@@ -345,14 +339,27 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
dev->syscstate);
- /*
- * Enabling all wakup sources to stop I2C freezing on
- * WFI instruction.
- * REVISIT: Some wkup sources might not be needed.
- */
- dev->westate = OMAP_I2C_WE_ALL;
}
}
+ return 0;
+}
+
+static int omap_i2c_init(struct omap_i2c_dev *dev)
+{
+ u16 psc = 0, scll = 0, sclh = 0;
+ u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
+ unsigned long fclk_rate = 12000000;
+ unsigned long internal_clk = 0;
+ struct clk *fclk;
+
+ if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
+ /*
+ * Enabling all wakup sources to stop I2C freezing on
+ * WFI instruction.
+ * REVISIT: Some wkup sources might not be needed.
+ */
+ dev->westate = OMAP_I2C_WE_ALL;
+ }
if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
/*
@@ -592,7 +599,8 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
dev->buf_len = 0;
if (timeout == 0) {
dev_err(dev->dev, "controller timed out\n");
- omap_i2c_init(dev);
+ omap_i2c_reset(dev);
+ __omap_i2c_init(dev);
return -ETIMEDOUT;
}
@@ -602,7 +610,8 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
/* We have an error */
if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
OMAP_I2C_STAT_XUDF)) {
- omap_i2c_init(dev);
+ omap_i2c_reset(dev);
+ __omap_i2c_init(dev);
return -EIO;
}
--
1.7.5.4
^ permalink raw reply related
* [PATCHv3 5/8] i2c: omap: re-factor omap_i2c_init function
From: Shubhrajyoti D @ 2012-11-05 12:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352118223-3796-1-git-send-email-shubhrajyoti@ti.com>
re-factor omap_i2c_init() so that we can re-use it for resume.
While at it also remove the bufstate variable as we write it
in omap_i2c_resize_fifo for every transfer.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
---
drivers/i2c/busses/i2c-omap.c | 75 +++++++++++++++++++----------------------
1 files changed, 35 insertions(+), 40 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 88358d8..393bb22 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -209,7 +209,6 @@ struct omap_i2c_dev {
u16 pscstate;
u16 scllstate;
u16 sclhstate;
- u16 bufstate;
u16 syscstate;
u16 westate;
u16 errata;
@@ -275,9 +274,34 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
(i2c_dev->regs[reg] << i2c_dev->reg_shift));
}
+static void __omap_i2c_init(struct omap_i2c_dev *dev)
+{
+
+ omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
+
+ /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
+ omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
+
+ /* SCL low and high time values */
+ omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
+ omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
+ if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
+ omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
+
+ /* Take the I2C module out of reset: */
+ omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
+
+ /*
+ * Don't write to this register if the IE state is 0 as it can
+ * cause deadlock.
+ */
+ if (dev->iestate)
+ omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
+}
+
static int omap_i2c_init(struct omap_i2c_dev *dev)
{
- u16 psc = 0, scll = 0, sclh = 0, buf = 0;
+ u16 psc = 0, scll = 0, sclh = 0;
u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
unsigned long fclk_rate = 12000000;
unsigned long timeout;
@@ -327,11 +351,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
* REVISIT: Some wkup sources might not be needed.
*/
dev->westate = OMAP_I2C_WE_ALL;
- omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
- dev->westate);
}
}
- omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
/*
@@ -416,28 +437,17 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
}
- /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
- omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
-
- /* SCL low and high time values */
- omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
- omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
-
- /* Take the I2C module out of reset: */
- omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
-
- /* Enable interrupts */
dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
(OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
- omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
- if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
- dev->pscstate = psc;
- dev->scllstate = scll;
- dev->sclhstate = sclh;
- dev->bufstate = buf;
- }
+
+ dev->pscstate = psc;
+ dev->scllstate = scll;
+ dev->sclhstate = sclh;
+
+ __omap_i2c_init(dev);
+
return 0;
}
@@ -1297,23 +1307,8 @@ static int omap_i2c_runtime_resume(struct device *dev)
if (!_dev->regs)
return 0;
- if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
- omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
- omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
- omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
- omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
- omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
- omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
- omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
- omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
- }
-
- /*
- * Don't write to this register if the IE state is 0 as it can
- * cause deadlock.
- */
- if (_dev->iestate)
- omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate);
+ if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE)
+ __omap_i2c_init(_dev);
return 0;
}
--
1.7.5.4
^ permalink raw reply related
* [PATCHv3 4/8] ARM: i2c: omap: Remove the i207 errata flag
From: Shubhrajyoti D @ 2012-11-05 12:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352118223-3796-1-git-send-email-shubhrajyoti@ti.com>
The commit [i2c: omap: use revision check for OMAP_I2C_FLAG_APPLY_ERRATA_I207]
uses the revision id instead of the flag. So the flag can be safely removed.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 3 +--
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 9 +++------
drivers/i2c/busses/i2c-omap.c | 3 +--
include/linux/i2c-omap.h | 1 -
4 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index c455e41..b79ccf6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -76,8 +76,7 @@ static struct omap_hwmod_class i2c_class = {
static struct omap_i2c_dev_attr i2c_dev_attr = {
.fifo_depth = 8, /* bytes */
- .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
- OMAP_I2C_FLAG_BUS_SHIFT_2 |
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index f67b7ee..943222c4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -791,8 +791,7 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
/* I2C1 */
static struct omap_i2c_dev_attr i2c1_dev_attr = {
.fifo_depth = 8, /* bytes */
- .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
- OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+ .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
OMAP_I2C_FLAG_BUS_SHIFT_2,
};
@@ -818,8 +817,7 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
/* I2C2 */
static struct omap_i2c_dev_attr i2c2_dev_attr = {
.fifo_depth = 8, /* bytes */
- .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
- OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+ .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
OMAP_I2C_FLAG_BUS_SHIFT_2,
};
@@ -845,8 +843,7 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
/* I2C3 */
static struct omap_i2c_dev_attr i2c3_dev_attr = {
.fifo_depth = 64, /* bytes */
- .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
- OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+ .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
OMAP_I2C_FLAG_BUS_SHIFT_2,
};
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 5f0c06c..88358d8 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1029,8 +1029,7 @@ static const struct i2c_algorithm omap_i2c_algo = {
#ifdef CONFIG_OF
static struct omap_i2c_bus_platform_data omap3_pdata = {
.rev = OMAP_I2C_IP_VERSION_1,
- .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
- OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+ .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
OMAP_I2C_FLAG_BUS_SHIFT_2,
};
diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h
index df804ba..5c88187 100644
--- a/include/linux/i2c-omap.h
+++ b/include/linux/i2c-omap.h
@@ -21,7 +21,6 @@
#define OMAP_I2C_FLAG_SIMPLE_CLOCK BIT(1)
#define OMAP_I2C_FLAG_16BIT_DATA_REG BIT(2)
#define OMAP_I2C_FLAG_RESET_REGS_POSTIDLE BIT(3)
-#define OMAP_I2C_FLAG_APPLY_ERRATA_I207 BIT(4)
#define OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK BIT(5)
#define OMAP_I2C_FLAG_FORCE_19200_INT_CLK BIT(6)
/* how the CPU address bus must be translated for I2C unit access */
--
1.7.5.4
^ permalink raw reply related
* [PATCHv3 3/8] i2c: omap: remove the dtrev
From: Shubhrajyoti D @ 2012-11-05 12:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352118223-3796-1-git-send-email-shubhrajyoti@ti.com>
The dtrev is used only for the comments. Remove the same and use
the scheme instead to know if it is version2.
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
---
v3: remove the scheme from the commments.
todo: remove the dtrev from hwmod etc.
drivers/i2c/busses/i2c-omap.c | 12 +++++-------
1 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 737d843..5f0c06c 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -191,7 +191,6 @@ struct omap_i2c_dev {
u32 latency; /* maximum MPU wkup latency */
struct pm_qos_request pm_qos_request;
u32 speed; /* Speed of bus in kHz */
- u32 dtrev; /* extra revision from DT */
u32 flags;
u16 cmd_err;
u8 *buf;
@@ -1076,7 +1075,7 @@ omap_i2c_probe(struct platform_device *pdev)
int irq;
int r;
u32 rev;
- u16 minor, major;
+ u16 minor, major, scheme;
/* NOTE: driver uses the static register mapping */
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1108,7 +1107,6 @@ omap_i2c_probe(struct platform_device *pdev)
u32 freq = 100000; /* default to 100000 Hz */
pdata = match->data;
- dev->dtrev = pdata->rev;
dev->flags = pdata->flags;
of_property_read_u32(node, "clock-frequency", &freq);
@@ -1117,7 +1115,6 @@ omap_i2c_probe(struct platform_device *pdev)
} else if (pdata != NULL) {
dev->speed = pdata->clkrate;
dev->flags = pdata->flags;
- dev->dtrev = pdata->rev;
}
dev->dev = &pdev->dev;
@@ -1146,7 +1143,8 @@ omap_i2c_probe(struct platform_device *pdev)
*/
rev = __raw_readw(dev->base + 0x04);
- switch (OMAP_I2C_SCHEME(rev)) {
+ scheme = OMAP_I2C_SCHEME(rev);
+ switch (scheme) {
case OMAP_I2C_SCHEME_0:
dev->regs = (u8 *)reg_map_ip_v1;
dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
@@ -1230,8 +1228,8 @@ omap_i2c_probe(struct platform_device *pdev)
goto err_unuse_clocks;
}
- dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", adap->nr,
- dev->dtrev, major, minor, dev->speed);
+ dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
+ major, minor, dev->speed);
of_i2c_register_devices(adap);
--
1.7.5.4
^ permalink raw reply related
* [PATCHv3 2/8] i2c: omap: use revision check for OMAP_I2C_FLAG_APPLY_ERRATA_I207
From: Shubhrajyoti D @ 2012-11-05 12:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352118223-3796-1-git-send-email-shubhrajyoti@ti.com>
The errata i207 is enabled for 2430 and 3xxx. Use the revision check
to enable the erratum instead.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
---
drivers/i2c/busses/i2c-omap.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 5c6f538..737d843 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1166,7 +1166,8 @@ omap_i2c_probe(struct platform_device *pdev)
dev->errata = 0;
- if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
+ if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
+ dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
dev->errata |= I2C_OMAP_ERRATA_I207;
if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
--
1.7.5.4
^ permalink raw reply related
* [PATCHv3 1/8] i2c: omap: Fix the revision register read
From: Shubhrajyoti D @ 2012-11-05 12:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352118223-3796-1-git-send-email-shubhrajyoti@ti.com>
The revision register on OMAP4 is a 16-bit lo and a 16-bit
hi. Currently the driver reads only the lower 8-bits.
Fix the same by preventing the truncating of the rev register
for OMAP4.
Also use the scheme bit ie bit-14 of the hi register to know if it
is OMAP_I2C_IP_VERSION_2.
On platforms previous to OMAP4 the offset 0x04 is IE register whose
bit-14 reset value is 0, the code uses the same to its advantage.
Also since the omap_i2c_read_reg uses reg_map_ip_* a raw_readw is done
to fetch the revision register.
The dev->regs is populated after reading the rev_hi. A NULL check
has been added in the resume handler to prevent the access before
the setting of the regs.
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
---
v3: Fix the comments.
drivers/i2c/busses/i2c-omap.c | 61 ++++++++++++++++++++++++++++++++---------
1 files changed, 48 insertions(+), 13 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index db31eae..5c6f538 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -49,9 +49,10 @@
#define OMAP_I2C_OMAP1_REV_2 0x20
/* I2C controller revisions present on specific hardware */
-#define OMAP_I2C_REV_ON_2430 0x36
-#define OMAP_I2C_REV_ON_3430_3530 0x3C
-#define OMAP_I2C_REV_ON_3630_4430 0x40
+#define OMAP_I2C_REV_ON_2430 0x00000036
+#define OMAP_I2C_REV_ON_3430_3530 0x0000003C
+#define OMAP_I2C_REV_ON_3630 0x00000040
+#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
/* timeout waiting for the controller to respond */
#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
@@ -202,7 +203,7 @@ struct omap_i2c_dev {
* fifo_size==0 implies no fifo
* if set, should be trsh+1
*/
- u8 rev;
+ u32 rev;
unsigned b_hw:1; /* bad h/w fixes */
unsigned receiver:1; /* true when we're in receiver mode */
u16 iestate; /* Saved interrupt register */
@@ -490,7 +491,7 @@ static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
- if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
+ if (dev->rev < OMAP_I2C_REV_ON_3630)
dev->b_hw = 1; /* Enable hardware fixes */
/* calculate wakeup latency constraint for MPU */
@@ -1052,6 +1053,16 @@ static const struct of_device_id omap_i2c_of_match[] = {
MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
#endif
+#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
+
+#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
+#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
+
+#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
+#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
+#define OMAP_I2C_SCHEME_0 0
+#define OMAP_I2C_SCHEME_1 1
+
static int __devinit
omap_i2c_probe(struct platform_device *pdev)
{
@@ -1064,6 +1075,8 @@ omap_i2c_probe(struct platform_device *pdev)
const struct of_device_id *match;
int irq;
int r;
+ u32 rev;
+ u16 minor, major;
/* NOTE: driver uses the static register mapping */
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1117,11 +1130,6 @@ omap_i2c_probe(struct platform_device *pdev)
dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
- if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
- dev->regs = (u8 *)reg_map_ip_v2;
- else
- dev->regs = (u8 *)reg_map_ip_v1;
-
pm_runtime_enable(dev->dev);
pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
pm_runtime_use_autosuspend(dev->dev);
@@ -1130,7 +1138,31 @@ omap_i2c_probe(struct platform_device *pdev)
if (IS_ERR_VALUE(r))
goto err_free_mem;
- dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
+ /*
+ * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
+ * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
+ * Also since the omap_i2c_read_reg uses reg_map_ip_* a
+ * raw_readw is done.
+ */
+ rev = __raw_readw(dev->base + 0x04);
+
+ switch (OMAP_I2C_SCHEME(rev)) {
+ case OMAP_I2C_SCHEME_0:
+ dev->regs = (u8 *)reg_map_ip_v1;
+ dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
+ minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
+ major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
+ break;
+ case OMAP_I2C_SCHEME_1:
+ /* FALLTHROUGH */
+ default:
+ dev->regs = (u8 *)reg_map_ip_v2;
+ rev = (rev << 16) |
+ omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
+ minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
+ major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
+ dev->rev = rev;
+ }
dev->errata = 0;
@@ -1155,7 +1187,7 @@ omap_i2c_probe(struct platform_device *pdev)
dev->fifo_size = (dev->fifo_size / 2);
- if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
+ if (dev->rev < OMAP_I2C_REV_ON_3630)
dev->b_hw = 1; /* Enable hardware fixes */
/* calculate wakeup latency constraint for MPU */
@@ -1198,7 +1230,7 @@ omap_i2c_probe(struct platform_device *pdev)
}
dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", adap->nr,
- dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
+ dev->dtrev, major, minor, dev->speed);
of_i2c_register_devices(adap);
@@ -1264,6 +1296,9 @@ static int omap_i2c_runtime_resume(struct device *dev)
struct platform_device *pdev = to_platform_device(dev);
struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
+ if (!_dev->regs)
+ return 0;
+
if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
--
1.7.5.4
^ permalink raw reply related
* [PATCHv3 0/7] i2c: omap: updates
From: Shubhrajyoti D @ 2012-11-05 12:23 UTC (permalink / raw)
To: linux-arm-kernel
Does the followiing
- Make the revision a 32- bit consisting of rev_lo amd rev_hi each
of 16 bits.
- Also use the revision register for the erratum i207.
- Refactor the i2c_omap_init code.
Adds a patch to remove the hardcoding sysc register. Instead
read register ,reset and then writeback the read value.
Also more cleanup is possible will check on that subsequently.
Previous discussions can be found
http://www.spinics.net/lists/linux-omap/msg81265.html
Tested on OMAP4430sdp ,4460 ,omap3630 ,3430 and omap2430.
For omap2 testing the below patch was used
[PATCH] ARM: vfp: fix save and restore when running on pre-VFPv3 and CONFIG_VFPv3 set
Also for using the pm testing below patches are used.
arm: sched: stop sched_clock() during suspend
ARM: OMAP: hwmod: wait for sysreset complete after enabling hwmod
The following changes since commit 3d70f8c617a436c7146ecb81df2265b4626dfe89:
Linux 3.7-rc4 (2012-11-04 11:07:39 -0800)
are available in the git repository at:
git://gitorious.org/linus-tree/linus-tree.git i2c_omap/for_3.8
Shubhrajyoti D (8):
i2c: omap: Fix the revision register read
i2c: omap: use revision check for OMAP_I2C_FLAG_APPLY_ERRATA_I207
i2c: omap: remove the dtrev
ARM: i2c: omap: Remove the i207 errata flag
i2c: omap: re-factor omap_i2c_init function
i2c: omap: make reset a seperate function
i2c: omap: Restore i2c context always
i2c: omap: cleanup the sysc write
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 3 +-
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 9 +-
drivers/i2c/busses/i2c-omap.c | 202 ++++++++++++++++------------
include/linux/i2c-omap.h | 1 -
4 files changed, 118 insertions(+), 97 deletions(-)
--
1.7.5.4
^ permalink raw reply
* [PATCH 6/8] serial: xilinx_uartps: kill CONFIG_OF conditional
From: Michal Simek @ 2012-11-05 12:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <61e872b2cd4abc25c2dab82668e5094b590571a0.1351721190.git.josh.cartwright@ni.com>
2012/10/30 Josh Cartwright <josh.cartwright@ni.com>:
> The Zynq platform requires the use of CONFIG_OF. Remove the #ifdef
> conditionals in the uartps driver.
>
> Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
> ---
> drivers/tty/serial/xilinx_uartps.c | 9 ---------
> 1 file changed, 9 deletions(-)
Please send this separately out of this patchset.
Also if you do this change which is understandable, you should also
add
depends on OF
Thanks,
Michal
^ permalink raw reply
* gic_set_affinity
From: Will Deacon @ 2012-11-05 12:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOmFF10ZvpoJ4gaW5WWhzvV4ecxrYJx-kobvNVmaNxBria6Jzg@mail.gmail.com>
On Fri, Nov 02, 2012 at 11:32:50AM +0000, Robert Beckett wrote:
> (CC maintainers)
>
> On 1 November 2012 17:54, Robert Beckett <bob.beckett@gmail.com> wrote:
> > Hello,
> >
> > I was looking through the arm gic code while debugging a problem I am
> > having, and noticed something in gic_set_affinity.
> >
> > When something comes along and setts an irq affinity mask (e.g.
> > through /proc/irq/<irq>/smp_affinity_mask), the calls goes like so :
> >
> > ...
> > 1. irq_set_affinity : grabs the desc->lock
> > 2. __irq_set_affinity_locked : calls chip->irq_set_affinity
> > 3. gic_set_affinity : writes a new mask to the gic distributor
> >
> > my question is, what happens if an interrupt is raised between 1 and 3?
> > To me, it looks like the interrupt could end up being handled on 2
> > cpus. When it is raised, the handler will be called and sit spinning
> > for desc->lock (e.g. in handle_fasteoi_irq). The mask will be set to
> > set the affinity to the new cpu, the new cpu will receive the
> > interrupt as it has not been ackd or disabled yet
The interrupt will have been acked in gic_handle_irq before the flow handler
is invoked, so it will transition to the active state and will not get
signalled to another CPU. Since we never set more than one target CPU at the
distributor level, the interrupt will only be forwarded to one CPU interface
at any given time.
Will
^ permalink raw reply
* [PATCH] pinctrl: nomadik: Add terminating entry for platform_device_id table
From: Linus Walleij @ 2012-11-05 11:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352043042.11324.0.camel@phoenix>
On Sun, Nov 4, 2012 at 4:30 PM, Axel Lin <axel.lin@ingics.com> wrote:
> The platform_device_id table is supposed to be zero-terminated.
>
> Signed-off-by: Axel Lin <axel.lin@ingics.com>
Thanks Axel, patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 6/6] pinctrl: sirf: enable the driver support new SiRFmarco SoC
From: Linus Walleij @ 2012-11-05 11:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGsJ_4wPVsRNZF-c=8hU-DFKuKOk5VciXJTShuT3j53pRmSb9A@mail.gmail.com>
On Thu, Nov 1, 2012 at 4:04 PM, Barry Song <21cnbao@gmail.com> wrote:
> Hi Linus,
> this one can be applied now. would you apply? as i have tried, now it
> can be applied directly againest 3.7-rc3:
Yes works like a charm, patch applied!
Thanks Barry,
Linus Walleij
^ permalink raw reply
* [PATCH 0/2] clk: ux500: Add some more clk lookups for u8500
From: Linus Walleij @ 2012-11-05 11:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351690853-13021-1-git-send-email-ulf.hansson@stericsson.com>
On Wed, Oct 31, 2012 at 2:40 PM, Ulf Hansson <ulf.hansson@stericsson.com> wrote:
> From: Ulf Hansson <ulf.hansson@linaro.org>
>
> Some more clock lookups added for rng clocks and for the nomadik ske
> keypad clocks.
>
> Ulf Hansson (2):
> clk: ux500: Register rng clock lookups for u8500
> clk: ux500: Register nomadik keypad clock lookups for u8500
Acked-by: Linus Walleij <linus.walleij@linaro.org>
for these.
They have the right name and all, apb_pclk is
"AMBA peripheral bus, peripheral block clock"
so a clock for the silicon, right.
... then how it's supposed to be used, that's another
issue...
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 6/7] pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC
From: Linus Walleij @ 2012-11-05 11:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351274153-3120-6-git-send-email-kgene.kim@samsung.com>
On Fri, Oct 26, 2012 at 7:55 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> From: Thomas Abraham <thomas.abraham@linaro.org>
>
> Add a new pinctrl driver for Samsung EXYNOS5440 SoC. The pin controller
> module in EXYNOS5440 is different from the pin controller found on other
> Samsung SoC. Hence, the pin controller driver for EXYNOS5440 SoC is
> independent of the Samsung pinctrl framework.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
If I haven't ACK:ed this before here's an
Acked-by: Linus Walleij <linus.walleij@linaro.org>
I expect this to go through the Samsung tree?
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 0/9] Pinctrl: SPEAr: Fixes for 3.7-rc3
From: Linus Walleij @ 2012-11-05 11:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOh2x=nZRowRXNcOYT3P83mUS3wu==F=-L7mhYa5OYg2p30UCg@mail.gmail.com>
On Mon, Nov 5, 2012 at 11:46 AM, viresh kumar <viresh.kumar@linaro.org> wrote:
> [Me]
>> I suspect they are fixing regressions in a non-mainline kernel
>> which is none of our business, but convince me and I'll move
>> them to the fixes branch ... I have still merged them, but aimed
>> for v3.8.
>
> Frankly speaking i haven't thought from this perspective while sending them.
> Just grouped the fixes/mistakes together :)
OK no big deal.
> You can add 4,6 and 9 in your linux-next branch. :)
There were merge dependencies so I just applied all of them
to fixes. We'll manage.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 3/8] ARM: zynq: dts: add description of the second uart
From: Michal Simek @ 2012-11-05 11:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8c2fac7167cd7c5201d5e1d8e1ceeb183ee2f63f.1351721190.git.josh.cartwright@ni.com>
2012/10/31 Josh Cartwright <josh.cartwright@ni.com>:
> The zynq-7000 has an additional UART at 0xE0001000. Describe it in the
> device tree.
>
> Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
> ---
> arch/arm/boot/dts/zynq-ep107.dts | 7 +++++++
> 1 file changed, 7 insertions(+)
Applied to my testing branch.
Thanks,
Michal
^ permalink raw reply
* [PATCH v3] ARM: dts: AM33xx: Add SPI node
From: Philip, Avinash @ 2012-11-05 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50927DF5.4080008@ti.com>
On Thu, Nov 01, 2012 at 19:19:41, Cousson, Benoit wrote:
> Hi Avinash,
>
> On 10/31/2012 11:51 AM, Philip, Avinash wrote:
> > Add McSPI data node to AM33XX device tree file. The McSPI module (and so
> > as the driver) is reused from OMAP4.
> >
> > Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
> > Tested-by: Matt Porter <mporter@ti.com>
>
> I've just realized the interrupt-parent was still there, so I removed both.
>
> Please find below the updated version.
I tested it and thanks for the fix.
Thanks
Avinash
^ permalink raw reply
* [PATCH 4/8] ARM: zynq: dts: split up device tree
From: Michal Simek @ 2012-11-05 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1dc81a3260da0a911dbcabd737547b7bff16a99c.1351721190.git.josh.cartwright@ni.com>
2012/10/31 Josh Cartwright <josh.cartwright@ni.com>:
> The purpose of the created zynq-7000.dtsi file is to describe the
> hardware common to all Zynq 7000-based boards. Also, get rid of the
> zynq-ep107 device tree, since it is not hardware anyone can purchase.
>
> Add a zc702 dts file based on the zynq-7000.dtsi. Add it to the
> dts/Makefile so it is built with the 'dtbs' target.
>
> Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> .../boot/dts/{zynq-ep107.dts => zynq-7000.dtsi} | 19 +++-----------
> arch/arm/boot/dts/zynq-zc702.dts | 30 ++++++++++++++++++++++
> arch/arm/mach-zynq/common.c | 3 ++-
> 4 files changed, 36 insertions(+), 17 deletions(-)
> rename arch/arm/boot/dts/{zynq-ep107.dts => zynq-7000.dtsi} (79%)
> create mode 100644 arch/arm/boot/dts/zynq-zc702.dts
Not going to apply this. We need to finish our discussion in
"[PATCH v4 1/5] zynq: use GIC device tree bindings" before.
Definitely I like idea to use "xlnx,zynq-7000" generic model name.
Thanks,
Michal
^ permalink raw reply
* [PATCH 1/1] ARM: oprofile: add A5/A7/A15 entries in op_perf_name
From: Will Deacon @ 2012-11-05 11:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351853016-4476-1-git-send-email-jgq516@gmail.com>
On Fri, Nov 02, 2012 at 10:43:36AM +0000, jgq516 at gmail.com wrote:
> From: Xiao Jiang <jgq516@gmail.com>
>
> Add related name for A5/A7/A15 which are consistent with the OProfile
> user ABI.
>
> Signed-off-by: Xiao Jiang <jgq516@gmail.com>
> ---
> arch/arm/oprofile/common.c | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c
> index 99c63d4b..ec10db1 100644
> --- a/arch/arm/oprofile/common.c
> +++ b/arch/arm/oprofile/common.c
> @@ -37,8 +37,11 @@ static struct op_perf_name {
> { "xscale1", "arm/xscale2" },
> { "v6", "arm/armv6" },
> { "v6mpcore", "arm/mpcore" },
> + { "ARMv7 Cortex-A5", "arm/armv7-ca5" },
> + { "ARMv7 Cortex-A7", "arm/armv7-ca7" },
> { "ARMv7 Cortex-A8", "arm/armv7" },
> { "ARMv7 Cortex-A9", "arm/armv7-ca9" },
> + { "ARMv7 Cortex-A15", "arm/armv7-ca15" },
> };
>
> char *op_name_from_perf_id(void)
I'd rather not go down this route now that we have the operf tool as part of
oprofile, which can use the perf syscall directly and doesn't need this
string translation.
Will
^ permalink raw reply
* [PATCH v2 2/2] ARM: OMAP: omap_device: Correct resource handling for DT boot
From: Benoit Cousson @ 2012-11-05 11:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5094D648.80608@deeprootsystems.com>
Hi Kevin,
On 11/03/2012 09:31 AM, Kevin Hilman wrote:
> On 10/30/2012 12:24 PM, Peter Ujfalusi wrote:
>> When booting with DT the OF core can fill up the resources provided
>> within
>> the DT blob.
>> The current way of handling the DT boot prevents us from removing
>> hwmod data
>> for platforms only suppose to boot with DT (OMAP5 for example) since
>> we need
>> to keep the whole hwmod database intact in order to have more
>> resources in
>> hwmod than in DT (to be able to append the DMA resource from hwmod).
>>
>> To fix this issue we just examine the OF provided resources:
>> If we do not have resources we use hwmod to fill them.
>> If we have resources we check if we already able to recive DMA
>> resource, if
>> no we only append the DMA resurce from hwmod to the OF provided ones.
>>
>> In this way we can start removing hwmod data for devices which have their
>> resources correctly configured in DT without regressions.
>>
>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>ke
>
> Acked-by: Kevin Hilman <khilman@ti.com>
>
> Benoit, feel free to take this one as well.
Thanks, I'll do.
Regards,
Benoit
^ permalink raw reply
* [PATCH 0/4] Support the MX6 FEC as a PTP hardware clock
From: Frank Li @ 2012-11-05 11:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351898728.2703.30.camel@bwh-desktop.uk.solarflarecom.com>
? 2012?11?3?????Ben Hutchings ???
> On Fri, 2012-11-02 at 09:43 +0100, Richard Cochran wrote:
> > On Fri, Nov 02, 2012 at 10:36:09AM +0800, Frank Li wrote:
> > > >
> > > > All applied to net-next.
> > > >
> > > > Please make sure your changes are in sync with Ben's PTP/PPS
> > > > Kconfig changes of today, and send me any changes if necessary.
> > > >
> > >
> > > Thank you very much.
> > > I checked Ben's patch, which not affect FEC.
> >
> > Maybe just remove the Kconfig line "select PPS".
>
> More than that: FEC should select PTP_1588_CLOCK,
okay, I will do that.
> FEC_PTP should be
> removed and all the conditional code made unconditional. Alternately,
> if that would cost too much (in terms of performance or memory) on some
> systems where the driver is used, FEC_PTP should default to 'y'.
Bd description will be difference between no PTP and PTP hardware,
So driver will not incompatible at two kind of hardware.
I can set it default is Y at MX6 platform.
> Ben.
>
> --
> Ben Hutchings, Staff Engineer, Solarflare
> Not speaking for my employer; that's the marketing department's job.
> They asked us to note that Solarflare product names are trademarked.
>
>
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^ permalink raw reply
* [PATCH 2/8] ARM: zynq: move ttc timer code to drivers/clocksource
From: Michal Simek @ 2012-11-05 11:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c0347788fbad559a249a25128a23f40c85d9cbda.1351721190.git.josh.cartwright@ni.com>
2012/10/29 Josh Cartwright <josh.cartwright@ni.com>:
> Suggested cleanup by Arnd Bergmann. Move the ttc timer.c code to
> drivers/clocksource, and out of the mach-zynq directory.
>
> The common.h (which only held the timer declaration) was renamed to
> xilinx_ttc.h and moved into include/linux.
>
> Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/arm/mach-zynq/Makefile | 2 +-
> arch/arm/mach-zynq/common.c | 2 +-
> drivers/clocksource/Makefile | 1 +
> arch/arm/mach-zynq/timer.c => drivers/clocksource/xilinx_ttc.c | 1 -
> arch/arm/mach-zynq/common.h => include/linux/xilinx_ttc.h | 4 ++--
> 5 files changed, 5 insertions(+), 5 deletions(-)
> rename arch/arm/mach-zynq/timer.c => drivers/clocksource/xilinx_ttc.c (99%)
> rename arch/arm/mach-zynq/common.h => include/linux/xilinx_ttc.h (91%)
Not going to apply this patch till there is clean way how to move all
drivers there.
Especially I don't like to add xilinx_ttc.h to include/linux folder.
Thanks,
Michal
^ permalink raw reply
* [PATCH 1/8] ARM: zynq: move arm-specific sys_timer out of ttc
From: Michal Simek @ 2012-11-05 11:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3ec3531d21c247ac3dcc76d91ff6be13ebfc733b.1351721190.git.josh.cartwright@ni.com>
2012/10/31 Josh Cartwright <josh.cartwright@ni.com>:
> Move the sys_timer definition out of ttc driver and make it part of the
> common zynq code. This is preparation for renaming and COMMON_CLK
> support.
>
> Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
> ---
> arch/arm/mach-zynq/common.c | 13 +++++++++++++
> arch/arm/mach-zynq/common.h | 4 +---
> arch/arm/mach-zynq/timer.c | 10 +---------
> 3 files changed, 15 insertions(+), 12 deletions(-)
>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Looks good to me. I have added it to my testing branch
and will provide path to mainline through xilinx arm-next branch
Thanks,
Michal
^ permalink raw reply
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