* Building for MMU-less vexpress targets
From: Russell King - ARM Linux @ 2012-11-07 13:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201211071259.15107.arnd@arndb.de>
On Wed, Nov 07, 2012 at 12:59:14PM +0000, Arnd Bergmann wrote:
> On Tuesday 06 November 2012, Russell King - ARM Linux wrote:
> > Now, we don't _have_ to have the single and multi variants if they aren't
> > appropriate for the platform, but we can cover all the cases: a platform
> > where it's part of the multi-platform kernel when built for MMU, but is
> > incapable of being a multi-platform kernel when built without MMU.
> >
> > And we can do it without _too_ much Kconfig pain, and certainly without
> > having to delve into anything beyond arch/arm/Kconfig.
>
> Sure, that works. My point was just that I think it would be simpler
> to keep vexpress multiplatform-only if there are no reasons that prevent
> us from doing that.
>
> I also hope that we can at some point in the future get all ARMv6 and ARMv7
> platforms to be multiplatform-only, while leaving each ARMv4/ARMv5 to be
> any of single, multi, or mixed.
Except... we have one report where this approach already doesn't work,
where we have what is essentially an ARMv7 platform needing to be built
outside the multiplatform stuff...
^ permalink raw reply
* [Resend PATCH v3 2/4] ARM: at91: atmel-ssc: add device tree support
From: Mark Brown @ 2012-11-07 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107104121.GG20063@game.jcrosoft.org>
On Wed, Nov 07, 2012 at 11:41:21AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 10:21 Wed 07 Nov , Mark Brown wrote:
> > Like I say it's not an issue right now and it seems like it should be
> > trivial to fix. Is anything needed here other than adding the
> > pinctrl_get_set_default() call, in which case would it not be less
> > effort all round to just send the patch? If there is more involved then
> > what is needed?
> for the driver point of view I agreee with you for the dtsi I disagree I miss
> 100 lignes of pinctrl description
> so today if no pinctrl the pin are input gpio and the drivers will not work
> if this code was tested this work MUST have been done otherwise we will apply
> non tested work
> so dor the dtsi part I do NACK it and the pinctrl code is arropund for 2 or 3
> months so no excuse even Joachim who add the rm9200 support to DT handled the
> pinctrl so no exeption on at91 when switching to DT the pinctrl is mandatory
> If you want to apply the part of the patch that touch only the drivers I'm
> fine but for the dtsi no
So what the above is saying is that we should have a followup patch to
add the pinctrl setup to the DT (probably one that goes along with the
pinctrl changes and adds complete pinctrl setup for the affected boards
rather than just doing the audio piecemeal) and do the mindless call in
the driver. That doesn't seem impossible.
So long as we get those things in place prior to the merge window we
should be fine. Even if we don't manage that it still seems like having
the patch is better than not having it, from the sounds of it the boards
are going to be totally broken if they boot with DT but without the
pinctrl setup and the ASoC bindings are pretty much an orthogonal issue
to that. Having the bindings for the SSC (which depend on this AFAICT)
will allow other machines which are doing a better job with pinctrl to
work.
Does that seem reasonable?
^ permalink raw reply
* drivers/staging/ced1401/ced_ioc.c:918 GetTransfer() error: potential null dereference 'tx'. (kzalloc returns null)
From: Arnd Bergmann @ 2012-11-07 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107100525.GA31190@localhost>
On Wednesday 07 November 2012, Fengguang Wu wrote:
> FYI, there are new smatch warnings show up in
>
> tree: git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git testing/defconfig-warnings
Thanks for the report. All three should be fixed now.
Arnd
^ permalink raw reply
* [PATCH] ARM: setup_mm_for_reboot(): use flush_cache_louis()
From: Santosh Shilimkar @ 2012-11-07 14:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107094726.GB17831@e102568-lin.cambridge.arm.com>
On Wednesday 07 November 2012 03:47 AM, Lorenzo Pieralisi wrote:
> On Tue, Nov 06, 2012 at 09:57:17PM +0000, Santosh Shilimkar wrote:
>> On Tuesday 06 November 2012 03:12 PM, Nicolas Pitre wrote:
>>>
>>> ... instead of flush_cache_all(). The later unconditionally flushes
>>> the L2 cache on ARMv7 architectures such as Cortex A15 and A7 which
>>> is costly and unnecessary in some scenarios where setup_mm_for_reboot()
>>> is used. If L2 has to be flushed as well, it should already be done
>>> separately on other architectures anyway.
>>>
>>> Signed-off-by: Nicolas Pitre <nico@linaro.org>
>>>
>>> diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
>>> index ab88ed4f8e..2c61085a10 100644
>>> --- a/arch/arm/mm/idmap.c
>>> +++ b/arch/arm/mm/idmap.c
>>> @@ -104,7 +104,7 @@ early_initcall(init_static_idmap);
>>> void setup_mm_for_reboot(void)
>>> {
>>> /* Clean and invalidate L1. */
>>> - flush_cache_all();
>>> + flush_cache_louis();
>>>
>>> /* Switch to the identity mapping. */
>>> cpu_switch_mm(idmap_pgd, &init_mm);
>>>
>> Nice. Just one difference is that the I-cache invalidation won't
>> happen with this change. Not that it is needed here but capturing
>> that in change-log would be good.
>
> Yes, it does happen. The LoUIS API mirrors the flush_cache_all() API in
> this respect, and it has to. The only change is the data cache level at
> which it operates.
>
Indeed. I remember our discussion on this part now. Thanks Lorenzo
for clarification.
Regards
Santosh
^ permalink raw reply
* [PATCH v4 1/5] zynq: use GIC device tree bindings
From: Josh Cartwright @ 2012-11-07 14:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHTX3dLgWxCzLT=TH+7ydep-m4+euVCP2cBo=Yx1qhe4xVL7NA@mail.gmail.com>
On Wed, Nov 07, 2012 at 01:05:57PM +0100, Michal Simek wrote:
> 2012/11/5 Josh Cartwright <josh.cartwright@ni.com>:
[..]
> > Our usecase may admittedly be a bit weird, because what logic is in the
> > PL is ultimately determined (and even implemented) by the end user and
> > is loaded at runtime. There is a lot of machinery to make that happen,
> > but the point is that I don't have sufficient knowledge upfront to
> > generate appropriate bindings for what's in the PL.
>
> ok. It means that you need to use just the part of DTS without PL logic at all.
> Does it mean that PL will be connected with any DTS fragment?
Yes. For the time being, this is true. We have our own mechanisms for
enumerating IP at runtime.
> > > > Having a dtsi allows for easy extension of the zynq-7000
> > > > platform for our boards, without having to carry duplicate data.
> > >
> > > ok. I think that make sense if you send the next your series as
> > > RFC to see how exactly you would like to use it.
> >
> > It seems like you caught a glimpse of this in my COMMON_CLK
> > patchset. :)
>
> Yes. Just need to get some time to analyze it.
>
[..]
> > I wouldn't be as opposed to device tree generation if the device tree
> > generator was in tree.
>
> Which tree do you exactly mean? Linux kernel or just any git tree?
No, I mean in the upstream Linux kernel tree. I don't think this is
likely to happen. My point here is that the generator necessarily has a
dependency on how the bindings are written. If those bindings change
(or new bindings are added), the generator must be updated to generate
device trees according to the new bindings.
I fail to see how these changes are handled with your generator.
> Let me give you more information about the generator. It uses TCL in SDK
> where it provides all structure from the system. It means device-tree generator
> will read all information from design tool and based on that will generate
> DTS file. It also means if user will setup specific irq lines in design, special
> paramters setting in registers then all these values will be added to DTS.
>
> > Device tree bindings change, how would/could an out-of-tree
> > generator possibly handle changes in bindings?
>
> What do you mean by that? Any example?
Yes, I have a real life example. In 3.2 (?), GIC bindings were added to
the kernel. It was necessary for us to update our board descriptions to
reflect the new #interrupt-cells = <3>; and figure out the appropriate
interrupt numbers (which differed from how they were specified before).
How would your generator have known whether or not I was targetting a
kernel with the GIC bindings, and appropriately generate the GIC node,
and generate interruptspecs for all children with #interrupt-cells = <3>?
Or, maybe another example: say clk bindings are added to the upstream
kernel, and I would like to use a kernel that contains them on my board.
Say this has all happened before Xilinx has even released a new version
of their SDK. How could I use your dts generator to output proper clk
nodes in my dts?
It seems the only way that Xilinx can possibly handle this is to tightly
couple the version of the kernel and their generator.
With increasing support for Zynq in the mainline kernel tree, it may
become more palatable for some existing users to switch to using the
upstream kernel instead of the Xilinx tree for their boards, and
coupling between the generator and target kernel version will be broken.
[..]
> > It is odd to me that the use of a generator would be required to create
> > what is completely static data. What I'm referring to here is the
> > collection of peripherals on the zynq-7000 that are not in the PL. For
> > me, this requirement adds an unnecessary dependency on the Xilinx EDK
> > that I would like to avoid.
>
> I am not saying that you need to use it. If you want to write your DTS
> by hand, you still can but I expect that the most of zynq users will
> use generator and generate it because it is just easier than to
> describe it by hand and they can be sure that all parameters are
> correctly generated.
Again, you can only make this assurance _for a specific version of the
kernel_. If a user is not using the version of the kernel that came
with the SDK (and, maybe instead using a vanilla upstream kernel), all
bets are off.
> If you are using any non-standard solution where you will load pl
> logic at runtime then you can use just generated DTS for hardblock or
> write it by hand.
I choose 'write it by hand'. I want what I write by hand to also be
useful to others by including the zynq-7000.dtsi in the upstream kernel.
[..]
> If you want to use solution with several dtsi files and compose it as
> you describe then it is completely fine but forcing others to use this
> structure and write dts by hand will be big pain for a lot of users.
Using a composed model in the upstream kernel doesn't force anything
upon the existing users of your generator. They can still use whatever
gets spit out of your generator (assuming it generates nodes with
appropriate bindings). Unless I'm missing something here.
> Also in design tools you can setup if you use qspi,nor,nand flash
> memory interface.
> memory interface, baudrates, dma, ports to PL logic, connections, etc.
> and from my point of view is very complicated to describe it by
>
> There are a lot of combination which you can have on one reference
> board. You can't enable all hard IPs at one time and use all of them
> that's why you shouldn't list all of them in the kernel.
I disagree with this. In my opinion, all of the "hard IPs" should be
described in the zynq-7000.dtsi, and those nodes which aren't available
explicitly disabled in the board-specific file.
> From my point of view make sense to have one DTS file in the kernel
> and one defconfig for the most popular zynq board where will be
> exactly written that this DTS is connected to this reference hw
> design. If you want to get more reference design go to this page and
> download it. Adding all DTSes for zynq boards to the kernel is
> overkill. If you want to use your hw design you can use this
> generator and generate it or write it by hand.
All I'm asking for is for there to be a common zynq-7000.dtsi that
describes all of the static PS logic ("hard IPs") in the upstream kernel
source that I can include in my own (hand maintained) board
descriptions. It would be nice if there was an example of its use, like
with a zc702 board file also upstream, but it is not really important to
me.
I do not want a dependency on the EDK.
My request does not sound unreasonable to me and is what other platforms
are doing.
Josh
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121107/84878c5b/attachment.sig>
^ permalink raw reply
* [PATCH] ARM: mxs: apf28dev: Add I2C, SPI and spidev support
From: gwenhael.goavec @ 2012-11-07 14:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509A24D4.9000308@free-electrons.com>
On Wed, 07 Nov 2012 10:07:32 +0100
Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> Le 06/11/2012 19:16, Gwenhael Goavec-Merou a ?crit :
> >
> > Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
> > ---
> > arch/arm/boot/dts/imx28-apf28dev.dts | 19 +++++++++++++++++++
> > 1 files changed, 19 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
> > index 1643d25..da7013d 100644
> > --- a/arch/arm/boot/dts/imx28-apf28dev.dts
> > +++ b/arch/arm/boot/dts/imx28-apf28dev.dts
> > @@ -27,6 +27,19 @@
> > status = "okay";
> > };
> >
> > + ssp2: ssp at 80014000 {
> > + compatible = "fsl,imx28-spi";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&spi2_pins_a>;
> > + status = "okay";
> > +
> > + spidev: spidev at 0 {
> > + compatible = "spidev";
> > + spi-max-frequency = <40000000>;
> > + reg = <0>;
> > + };
> > + };
>
> This won't work, since the compatible string is not matching in the
> spidev driver.
>
This patch has been successfully tested on the Shawn Guo's git. Spidev dt
support seems to be not yet available with this git.
>
> You need to add the compatible string of the spi device that you will
> drive with spidev in the spidev driver, and then use this string in your
> dts.
>
> See
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-October/129134.html
> and
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-October/129133.html
>
The APF28dev docking board contains no spi peripheral by default. The spidev
driver is used to evaluation and fast prototyping of peripherals before creating
a driver. Consequently it's a bit difficult to add a compatible string...
What is the solution in this situation?
Gwenhael Goavec-Merou
Armadeus Systems
^ permalink raw reply
* [PATCH] ARM: mxs: apf28dev: Add I2C, SPI and spidev support
From: Mark Brown @ 2012-11-07 14:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107152005.549fa8de@dell>
On Wed, Nov 07, 2012 at 03:20:05PM +0100, gwenhael.goavec wrote:
> The APF28dev docking board contains no spi peripheral by default. The spidev
> driver is used to evaluation and fast prototyping of peripherals before creating
> a driver. Consequently it's a bit difficult to add a compatible string...
> What is the solution in this situation?
If you're doing that sort of prototyping and development surely it's
easy to locally edit the DT and/or kernel code to register the device as
part of the development? The DT is supposed to describe the hardware so
if you're changing the hardware it seems reasonable to change the DT.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121107/24a99ccf/attachment-0001.sig>
^ permalink raw reply
* [Resend PATCH v3 2/4] ARM: at91: atmel-ssc: add device tree support
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-11-07 14:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107140535.GA28954@opensource.wolfsonmicro.com>
On 14:05 Wed 07 Nov , Mark Brown wrote:
> On Wed, Nov 07, 2012 at 11:41:21AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 10:21 Wed 07 Nov , Mark Brown wrote:
>
> > > Like I say it's not an issue right now and it seems like it should be
> > > trivial to fix. Is anything needed here other than adding the
> > > pinctrl_get_set_default() call, in which case would it not be less
> > > effort all round to just send the patch? If there is more involved then
> > > what is needed?
>
> > for the driver point of view I agreee with you for the dtsi I disagree I miss
> > 100 lignes of pinctrl description
>
> > so today if no pinctrl the pin are input gpio and the drivers will not work
>
> > if this code was tested this work MUST have been done otherwise we will apply
> > non tested work
>
> > so dor the dtsi part I do NACK it and the pinctrl code is arropund for 2 or 3
> > months so no excuse even Joachim who add the rm9200 support to DT handled the
> > pinctrl so no exeption on at91 when switching to DT the pinctrl is mandatory
>
> > If you want to apply the part of the patch that touch only the drivers I'm
> > fine but for the dtsi no
>
> So what the above is saying is that we should have a followup patch to
> add the pinctrl setup to the DT (probably one that goes along with the
> pinctrl changes and adds complete pinctrl setup for the affected boards
> rather than just doing the audio piecemeal) and do the mindless call in
> the driver. That doesn't seem impossible.
>
> So long as we get those things in place prior to the merge window we
> should be fine. Even if we don't manage that it still seems like having
> the patch is better than not having it, from the sounds of it the boards
> are going to be totally broken if they boot with DT but without the
> pinctrl setup and the ASoC bindings are pretty much an orthogonal issue
> to that. Having the bindings for the SSC (which depend on this AFAICT)
> will allow other machines which are doing a better job with pinctrl to
> work.
so for me Bo re do his patch series by splitting in 2 patch seires
the one via ASoC for the driver with the pinctrl for now but MUST add it later
the arch/arm related via AT91 tree where the pinctrl is mandatory in the dtsi
I'm no going to spend hours to do the pinctrl to test Bo patch that he is
supposed to have deon to test this code
As basically today on DT none of the board will work if BO does no provide the
pinctrl so for me he MUST put in the dtsi
is it ok with you?
Best Regards,
J.
^ permalink raw reply
* [PATCH] ARM: EXYNOS: origen: Add missing USB regulators
From: Tomasz Figa @ 2012-11-07 14:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1706359.z5UOYbqyny@amdc1227>
On Wednesday 07 of November 2012 14:01:19 Tomasz Figa wrote:
> This patch adds missing USB OTG regulators needed for s3c-hsotg driver
> to work on Origen board.
>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
> arch/arm/mach-exynos/mach-origen.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-exynos/mach-origen.c
> b/arch/arm/mach-exynos/mach-origen.c index d8dc6d7..ddf6358 100644
> --- a/arch/arm/mach-exynos/mach-origen.c
> +++ b/arch/arm/mach-exynos/mach-origen.c
> @@ -100,6 +100,8 @@ static struct regulator_consumer_supply __initdata
> ldo3_consumer[] = { REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /*
> MIPI */
> REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
> REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
> + REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* OTG */
> + REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* OTG */
> };
> static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
> REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
It's worth noting that this patch is based on board file of Origen in
Linaro tree
http://git.linaro.org/gitweb?p=landingteams/working/samsung/kernel;a=summary
branch samsung-linux-3.6-2012.10
and not confirmed with respective board schematics (although verified
working on an Origen board).
Personally I find these two consumers, which are supposed to provided with
completely different voltages, connected to a single regulator a bit
suspicious, so someone who know details of this board should ack or
correct this patch.
Best regards,
--
Tomasz Figa
Samsung Poland R&D Center
SW Solution Development, Linux Platform
^ permalink raw reply
* [PATCH] pinctrl: SPEAr: Add SoC specific gpio configuration routines
From: Viresh Kumar @ 2012-11-07 14:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Shiraz Hashim <shiraz.hashim@st.com>
Different SPEAr SoCs have different approach to configure pins as gpios. Some
configure a group of gpios with single register bit and others have one bit per
gpio pin. Only earlier one is implemented till now, this patch adds support for
later one.
Here we add callbacks to SoC specific code to configure gpios in
gpio_request_enable(). That will do additional SoC specific configuration to
enable gpio pins.
We also implement this callback for SPEAr1340 in this patch.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/pinctrl/spear/pinctrl-spear.c | 26 ++++++++++++--------------
drivers/pinctrl/spear/pinctrl-spear.h | 14 ++++++++++++++
drivers/pinctrl/spear/pinctrl-spear1340.c | 27 +++++++++++++++++++++++++++
3 files changed, 53 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
index cbca6dc..f9483ae 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.c
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -14,7 +14,6 @@
*/
#include <linux/err.h>
-#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
@@ -29,16 +28,6 @@
#define DRIVER_NAME "spear-pinmux"
-static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
-{
- return readl_relaxed(pmx->vbase + reg);
-}
-
-static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
-{
- writel_relaxed(val, pmx->vbase + reg);
-}
-
static void muxregs_endisable(struct spear_pmx *pmx,
struct spear_muxreg *muxregs, u8 count, bool enable)
{
@@ -316,16 +305,25 @@ static int gpio_request_endisable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset, bool enable)
{
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+ struct spear_pinctrl_machdata *machdata = pmx->machdata;
struct spear_gpio_pingroup *gpio_pingroup;
+ /*
+ * Some SoC have configuration options applicable to group of pins,
+ * rather than a single pin.
+ */
gpio_pingroup = get_gpio_pingroup(pmx, offset);
- if (IS_ERR(gpio_pingroup))
- return PTR_ERR(gpio_pingroup);
-
if (gpio_pingroup)
muxregs_endisable(pmx, gpio_pingroup->muxregs,
gpio_pingroup->nmuxregs, enable);
+ /*
+ * SoC may need some extra configurations, or configurations for single
+ * pin
+ */
+ if (machdata->gpio_request_endisable)
+ machdata->gpio_request_endisable(pmx, offset, enable);
+
return 0;
}
diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h
index 94f142c..b063327 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.h
+++ b/drivers/pinctrl/spear/pinctrl-spear.h
@@ -13,11 +13,13 @@
#define __PINMUX_SPEAR_H__
#include <linux/gpio.h>
+#include <linux/io.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/types.h>
struct platform_device;
struct device;
+struct spear_pmx;
/**
* struct spear_pmx_mode - SPEAr pmx mode
@@ -155,6 +157,8 @@ struct spear_pinctrl_machdata {
struct spear_pingroup **groups;
unsigned ngroups;
struct spear_gpio_pingroup *gpio_pingroups;
+ void (*gpio_request_endisable)(struct spear_pmx *pmx, int offset,
+ bool enable);
unsigned ngpio_pingroups;
bool modes_supported;
@@ -178,6 +182,16 @@ struct spear_pmx {
};
/* exported routines */
+static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
+{
+ return readl_relaxed(pmx->vbase + reg);
+}
+
+static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
+{
+ writel_relaxed(val, pmx->vbase + reg);
+}
+
void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
void __devinit
pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c
index 0606b8c..0b4af0e 100644
--- a/drivers/pinctrl/spear/pinctrl-spear1340.c
+++ b/drivers/pinctrl/spear/pinctrl-spear1340.c
@@ -1971,6 +1971,32 @@ static struct spear_function *spear1340_functions[] = {
&sata_function,
};
+static void gpio_request_endisable(struct spear_pmx *pmx, int pin,
+ bool enable)
+{
+ unsigned int regoffset, regindex, bitoffset;
+ unsigned int val;
+
+ /* pin++ as gpio configuration starts from 2nd bit of base register */
+ pin++;
+
+ regindex = pin / 32;
+ bitoffset = pin % 32;
+
+ if (regindex <= 3)
+ regoffset = PAD_FUNCTION_EN_1 + regindex * sizeof(int *);
+ else
+ regoffset = PAD_FUNCTION_EN_5 + (regindex - 4) * sizeof(int *);
+
+ val = pmx_readl(pmx, regoffset);
+ if (enable)
+ val &= ~(0x1 << bitoffset);
+ else
+ val |= 0x1 << bitoffset;
+
+ pmx_writel(pmx, val, regoffset);
+}
+
static struct spear_pinctrl_machdata spear1340_machdata = {
.pins = spear1340_pins,
.npins = ARRAY_SIZE(spear1340_pins),
@@ -1978,6 +2004,7 @@ static struct spear_pinctrl_machdata spear1340_machdata = {
.ngroups = ARRAY_SIZE(spear1340_pingroups),
.functions = spear1340_functions,
.nfunctions = ARRAY_SIZE(spear1340_functions),
+ .gpio_request_endisable = gpio_request_endisable,
.modes_supported = false,
};
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH] ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER
From: Igor Grinberg @ 2012-11-07 14:42 UTC (permalink / raw)
To: linux-arm-kernel
CONFIG_OMAP_32K_TIMER is kind of standing on the single zImage way.
Make OMAP2+ timer code independant from the CONFIG_OMAP_32K_TIMER
setting.
To remove the dependancy, several conversions/additions had to be done:
1) Timer structures and initialization functions are named by the platform
name and the clock source in use. The decision which timer is
used is done statically from the machine_desc structure. In the
future it should come from DT.
2) Settings under the CONFIG_OMAP_32K_TIMER option are expanded into
separate timer structures along with the timer init functions.
This removes the CONFIG_OMAP_32K_TIMER on OMAP2+ timer code.
3) Since we have all the timers defined inside machine_desc structure
and we no longer need the fallback to gp_timer clock source in case
32k_timer clock source is unavailable (namely on AM33xx), we no
longer need the #ifdef around __omap2_sync32k_clocksource_init()
function. Remove the #ifdef CONFIG_OMAP_32K_TIMER around the
__omap2_sync32k_clocksource_init() function.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
---
Finally I'm sending this out...
I've lost following Tony's branches and deciding which one to base on,
so I used linux-omap/master as a base for the patch.
Tony, tell me if you want it based on some other branch.
This has been compile tested on omap1|2plus_defconfig only.
arch/arm/mach-omap2/board-2430sdp.c | 2 +-
arch/arm/mach-omap2/board-3430sdp.c | 2 +-
arch/arm/mach-omap2/board-3630sdp.c | 2 +-
arch/arm/mach-omap2/board-4430sdp.c | 2 +-
arch/arm/mach-omap2/board-am3517crane.c | 2 +-
arch/arm/mach-omap2/board-am3517evm.c | 2 +-
arch/arm/mach-omap2/board-apollon.c | 2 +-
arch/arm/mach-omap2/board-cm-t35.c | 18 ++--
arch/arm/mach-omap2/board-cm-t3517.c | 2 +-
arch/arm/mach-omap2/board-devkit8000.c | 2 +-
arch/arm/mach-omap2/board-generic.c | 14 ++--
arch/arm/mach-omap2/board-h4.c | 2 +-
arch/arm/mach-omap2/board-igep0020.c | 4 +-
arch/arm/mach-omap2/board-ldp.c | 2 +-
arch/arm/mach-omap2/board-n8x0.c | 6 +-
arch/arm/mach-omap2/board-omap3beagle.c | 2 +-
arch/arm/mach-omap2/board-omap3encore.c | 2 +-
arch/arm/mach-omap2/board-omap3evm.c | 2 +-
arch/arm/mach-omap2/board-omap3logic.c | 4 +-
arch/arm/mach-omap2/board-omap3pandora.c | 2 +-
arch/arm/mach-omap2/board-omap3stalker.c | 2 +-
arch/arm/mach-omap2/board-omap3touchbook.c | 2 +-
arch/arm/mach-omap2/board-omap4panda.c | 2 +-
arch/arm/mach-omap2/board-omap4pcm049.c | 2 +-
arch/arm/mach-omap2/board-overo.c | 2 +-
arch/arm/mach-omap2/board-rm680.c | 4 +-
arch/arm/mach-omap2/board-rx51.c | 2 +-
arch/arm/mach-omap2/board-ti8168evm.c | 4 +-
arch/arm/mach-omap2/board-zoom.c | 4 +-
arch/arm/mach-omap2/common.h | 17 ++-
arch/arm/mach-omap2/timer.c | 162 ++++++++++++++--------------
arch/arm/plat-omap/Kconfig | 5 +
32 files changed, 147 insertions(+), 137 deletions(-)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index d1c0162..90c1584 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -284,6 +284,6 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_2430sdp_init,
.init_late = omap2430_init_late,
- .timer = &omap2_timer,
+ .timer = &omap2_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 79fd904..e14b355 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -596,6 +596,6 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_3430sdp_init,
.init_late = omap3430_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 81871b1..030d292 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -211,6 +211,6 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_sdp_init,
.init_late = omap3630_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index fd80d97..c29e446 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -880,6 +880,6 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
.handle_irq = gic_handle_irq,
.init_machine = omap_4430sdp_init,
.init_late = omap4430_init_late,
- .timer = &omap4_timer,
+ .timer = &omap4_local_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 603503c..db2c007 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -92,6 +92,6 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
.handle_irq = omap3_intc_handle_irq,
.init_machine = am3517_crane_init,
.init_late = am35xx_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 96d6c5a..8802928 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -392,6 +392,6 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
.handle_irq = omap3_intc_handle_irq,
.init_machine = am3517_evm_init,
.init_late = am35xx_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 64cf1bd..d7fa83c 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -337,6 +337,6 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_apollon_init,
.init_late = omap2420_init_late,
- .timer = &omap2_timer,
+ .timer = &omap2_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index a8cad22..6cfed1a 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -750,19 +750,19 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
.handle_irq = omap3_intc_handle_irq,
.init_machine = cm_t35_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
MACHINE_START(CM_T3730, "Compulab CM-T3730")
- .atag_offset = 0x100,
- .reserve = omap_reserve,
- .map_io = omap3_map_io,
- .init_early = omap3630_init_early,
- .init_irq = omap3_init_irq,
+ .atag_offset = 0x100,
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = omap3630_init_early,
+ .init_irq = omap3_init_irq,
.handle_irq = omap3_intc_handle_irq,
- .init_machine = cm_t3730_init,
- .init_late = omap3630_init_late,
- .timer = &omap3_timer,
+ .init_machine = cm_t3730_init,
+ .init_late = omap3630_init_late,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 2786647..4af5b75 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -297,6 +297,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
.handle_irq = omap3_intc_handle_irq,
.init_machine = cm_t3517_init,
.init_late = am35xx_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 933479e..3b2f5e58 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -642,6 +642,6 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
.handle_irq = omap3_intc_handle_irq,
.init_machine = devkit8000_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_secure_timer,
+ .timer = &omap3_secure_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index d690180..b57f4ac 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -55,7 +55,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
.init_irq = omap_intc_of_init,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
- .timer = &omap2_timer,
+ .timer = &omap2_sync32k_timer,
.dt_compat = omap242x_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
@@ -74,7 +74,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
.init_irq = omap_intc_of_init,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
- .timer = &omap2_timer,
+ .timer = &omap2_sync32k_timer,
.dt_compat = omap243x_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
@@ -93,7 +93,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
.init_irq = omap_intc_of_init,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_generic_init,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.dt_compat = omap3_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
@@ -110,7 +110,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
.init_irq = omap_intc_of_init,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_generic_init,
- .timer = &omap3_secure_timer,
+ .timer = &omap3_secure_sync32k_timer,
.dt_compat = omap3_gp_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
@@ -129,7 +129,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
.init_irq = omap_intc_of_init,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_generic_init,
- .timer = &omap3_am33xx_timer,
+ .timer = &omap3_am33xx_gp_timer,
.dt_compat = am33xx_boards_compat,
MACHINE_END
#endif
@@ -149,7 +149,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
.handle_irq = gic_handle_irq,
.init_machine = omap_generic_init,
.init_late = omap4430_init_late,
- .timer = &omap4_timer,
+ .timer = &omap4_local_sync32k_timer,
.dt_compat = omap4_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
@@ -169,7 +169,7 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
.init_irq = omap_gic_of_init,
.handle_irq = gic_handle_irq,
.init_machine = omap_generic_init,
- .timer = &omap5_timer,
+ .timer = &omap5_realtime_sync32k_timer,
.dt_compat = omap5_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 8668c72..cf404f3 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -385,6 +385,6 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_h4_init,
.init_late = omap2420_init_late,
- .timer = &omap2_timer,
+ .timer = &omap2_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index dbc705a..279af3f 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -650,7 +650,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = igep_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
@@ -663,6 +663,6 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
.handle_irq = omap3_intc_handle_irq,
.init_machine = igep_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 1164b10..7508f4c 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -435,6 +435,6 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_ldp_init,
.init_late = omap3430_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 123fda3..49dc3eb 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -731,7 +731,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
.handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.init_late = omap2420_init_late,
- .timer = &omap2_timer,
+ .timer = &omap2_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
@@ -744,7 +744,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
.handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.init_late = omap2420_init_late,
- .timer = &omap2_timer,
+ .timer = &omap2_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
@@ -757,6 +757,6 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
.handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.init_late = omap2420_init_late,
- .timer = &omap2_timer,
+ .timer = &omap2_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 5a3800d..cd6e636 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -544,6 +544,6 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_beagle_init,
.init_late = omap3_init_late,
- .timer = &omap3_secure_timer,
+ .timer = &omap3_secure_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3encore.c b/arch/arm/mach-omap2/board-omap3encore.c
index 675c47a..6e92d6a 100644
--- a/arch/arm/mach-omap2/board-omap3encore.c
+++ b/arch/arm/mach-omap2/board-omap3encore.c
@@ -326,5 +326,5 @@ MACHINE_START(ENCORE, "encore")
.init_irq = omap3_init_irq,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_encore_init,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 3c0b9a9..d72bc7e 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -756,6 +756,6 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_evm_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index e84e2a8..28b5d65 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -231,7 +231,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3logic_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
@@ -244,6 +244,6 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3logic_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index ce31bd3..074d84d 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -618,6 +618,6 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3pandora_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index ba11245..9e6c92a 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -426,6 +426,6 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_stalker_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_secure_timer,
+ .timer = &omap3_secure_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index a225d81..7ae22d4 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -386,6 +386,6 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_touchbook_init,
.init_late = omap3430_init_late,
- .timer = &omap3_secure_timer,
+ .timer = &omap3_secure_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 8c00b99..02eb646 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -523,6 +523,6 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
.handle_irq = gic_handle_irq,
.init_machine = omap4_panda_init,
.init_late = omap4430_init_late,
- .timer = &omap4_timer,
+ .timer = &omap4_local_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4pcm049.c b/arch/arm/mach-omap2/board-omap4pcm049.c
index 47a710e..7f3ffdd 100644
--- a/arch/arm/mach-omap2/board-omap4pcm049.c
+++ b/arch/arm/mach-omap2/board-omap4pcm049.c
@@ -538,5 +538,5 @@ MACHINE_START(PCM049, "phyCORE OMAP4")
.init_irq = gic_init_irq,
.handle_irq = gic_handle_irq,
.init_machine = pcm049_init,
- .timer = &omap4_timer,
+ .timer = &omap4_local_sync32k_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 1cfb037..864be4c 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -552,6 +552,6 @@ MACHINE_START(OVERO, "Gumstix Overo")
.handle_irq = omap3_intc_handle_irq,
.init_machine = overo_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 1997e0e..5514d2e 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -147,7 +147,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = rm680_init,
.init_late = omap3630_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
@@ -160,6 +160,6 @@ MACHINE_START(NOKIA_RM696, "Nokia RM-696 board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = rm680_init,
.init_late = omap3630_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index c388aec..03ae3f3 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -126,6 +126,6 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = rx51_init,
.init_late = omap3430_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index 5e672c2..9f03177 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -43,7 +43,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
.map_io = ti81xx_map_io,
.init_early = ti81xx_init_early,
.init_irq = ti81xx_init_irq,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.init_machine = ti81xx_evm_init,
.init_late = ti81xx_init_late,
.restart = omap_prcm_restart,
@@ -55,7 +55,7 @@ MACHINE_START(TI8148EVM, "ti8148evm")
.map_io = ti81xx_map_io,
.init_early = ti81xx_init_early,
.init_irq = ti81xx_init_irq,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.init_machine = ti81xx_evm_init,
.init_late = ti81xx_init_late,
.restart = omap_prcm_restart,
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 8feb4d9..b906430 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -137,7 +137,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_zoom_init,
.init_late = omap3430_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
@@ -150,6 +150,6 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_zoom_init,
.init_late = omap3630_init_late,
- .timer = &omap3_timer,
+ .timer = &omap3_sync32k_timer,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index fd97f31..153aa39 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -135,12 +135,17 @@ static inline void omap5_map_common_io(void)
extern void omap2_init_common_infrastructure(void);
-extern struct sys_timer omap2_timer;
-extern struct sys_timer omap3_timer;
-extern struct sys_timer omap3_secure_timer;
-extern struct sys_timer omap3_am33xx_timer;
-extern struct sys_timer omap4_timer;
-extern struct sys_timer omap5_timer;
+extern struct sys_timer omap2_sync32k_timer;
+extern struct sys_timer omap2_gp_timer;
+extern struct sys_timer omap3_sync32k_timer;
+extern struct sys_timer omap3_gp_timer;
+extern struct sys_timer omap3_secure_sync32k_timer;
+extern struct sys_timer omap3_secure_gp_timer;
+extern struct sys_timer omap3_am33xx_gp_timer;
+extern struct sys_timer omap4_local_sync32k_timer;
+extern struct sys_timer omap4_local_gp_timer;
+extern struct sys_timer omap5_realtime_sync32k_timer;
+extern struct sys_timer omap5_realtime_gp_timer;
void omap2420_init_early(void);
void omap2430_init_early(void);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 684d2fc..a4ad7a0 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -63,20 +63,8 @@
#define OMAP2_32K_SOURCE "func_32k_ck"
#define OMAP3_32K_SOURCE "omap_32k_fck"
#define OMAP4_32K_SOURCE "sys_32k_ck"
-
-#ifdef CONFIG_OMAP_32K_TIMER
-#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
-#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
-#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
-#define OMAP3_SECURE_TIMER 12
#define TIMER_PROP_SECURE "ti,timer-secure"
-#else
-#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
-#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
-#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
-#define OMAP3_SECURE_TIMER 1
-#define TIMER_PROP_SECURE "ti,timer-alwon"
-#endif
+#define TIMER_PROP_ALWON "ti,timer-alwon"
#define REALTIME_COUNTER_BASE 0x48243200
#define INCREMENTER_NUMERATOR_OFFSET 0x10
@@ -216,7 +204,7 @@ void __init omap_dmtimer_init(void)
/* If we are a secure device, remove any secure timer nodes */
if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
- np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
+ np = omap_get_timer_dt(omap_timer_match, TIMER_PROP_SECURE);
if (np)
of_node_put(np);
}
@@ -378,9 +366,8 @@ static u32 notrace dmtimer_read_sched_clock(void)
return 0;
}
-#ifdef CONFIG_OMAP_32K_TIMER
/* Setup free-running counter for clocksource */
-static int __init omap2_sync32k_clocksource_init(void)
+static int __init __omap2_sync32k_clocksource_init(void)
{
int ret;
struct device_node *np = NULL;
@@ -439,15 +426,9 @@ static int __init omap2_sync32k_clocksource_init(void)
return ret;
}
-#else
-static inline int omap2_sync32k_clocksource_init(void)
-{
- return -ENODEV;
-}
-#endif
-static void __init omap2_gptimer_clocksource_init(int gptimer_id,
- const char *fck_source)
+static void __init omap2_gp_clocksource_init(int gptimer_id,
+ const char *fck_source)
{
int res;
@@ -466,23 +447,10 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
gptimer_id, clksrc.rate);
}
-static void __init omap2_clocksource_init(int gptimer_id,
- const char *fck_source)
+static void __init omap2_sync32k_clocksource_init(int gptimer_id,
+ const char *fck_source)
{
- /*
- * First give preference to kernel parameter configuration
- * by user (clocksource="gp_timer").
- *
- * In case of missing kernel parameter for clocksource,
- * first check for availability for 32k-sync timer, in case
- * of failure in finding 32k_counter module or registering
- * it as clocksource, execution will fallback to gp-timer.
- */
- if (use_gptimer_clksrc == true)
- omap2_gptimer_clocksource_init(gptimer_id, fck_source);
- else if (omap2_sync32k_clocksource_init())
- /* Fall back to gp-timer code */
- omap2_gptimer_clocksource_init(gptimer_id, fck_source);
+ __omap2_sync32k_clocksource_init();
}
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
@@ -563,52 +531,64 @@ static inline void __init realtime_counter_init(void)
{}
#endif
-#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
- clksrc_nr, clksrc_src) \
-static void __init omap##name##_timer_init(void) \
+#define OMAP_SYS_TIMER_INIT(n, clksrc_name, clkev_nr, clkev_src, \
+ clkev_prop, clksrc_nr, clksrc_src) \
+static void __init omap##n##_##clksrc_name##_timer_init(void) \
{ \
omap_dmtimer_init(); \
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
- omap2_clocksource_init((clksrc_nr), clksrc_src); \
+ \
+ if (use_gptimer_clksrc) \
+ omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
+ else \
+ omap2_##clksrc_name##_clocksource_init((clksrc_nr), \
+ clksrc_src); \
}
-#define OMAP_SYS_TIMER(name) \
-struct sys_timer omap##name##_timer = { \
- .init = omap##name##_timer_init, \
-};
+#define OMAP_SYS_TIMER(n, clksrc) \
+struct sys_timer omap##n##_##clksrc##_timer = { \
+ .init = omap##n##_##clksrc##_timer_init, \
+}
#ifdef CONFIG_ARCH_OMAP2
-OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, "ti,timer-alwon",
- 2, OMAP2_MPU_SOURCE)
-OMAP_SYS_TIMER(2)
+OMAP_SYS_TIMER_INIT(2, sync32k, 1, OMAP2_32K_SOURCE, TIMER_PROP_ALWON,
+ 2, OMAP2_MPU_SOURCE);
+OMAP_SYS_TIMER(2, sync32k);
+OMAP_SYS_TIMER_INIT(2, gp, 1, OMAP2_MPU_SOURCE, TIMER_PROP_ALWON,
+ 2, OMAP2_MPU_SOURCE);
+OMAP_SYS_TIMER(2, gp);
#endif
#ifdef CONFIG_ARCH_OMAP3
-OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, "ti,timer-alwon",
- 2, OMAP3_MPU_SOURCE)
-OMAP_SYS_TIMER(3)
-OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
- TIMER_PROP_SECURE, 2, OMAP3_MPU_SOURCE)
-OMAP_SYS_TIMER(3_secure)
+OMAP_SYS_TIMER_INIT(3, sync32k, 1, OMAP3_32K_SOURCE, TIMER_PROP_ALWON,
+ 2, OMAP3_MPU_SOURCE);
+OMAP_SYS_TIMER(3, sync32k);
+OMAP_SYS_TIMER_INIT(3, gp, 1, OMAP3_MPU_SOURCE, TIMER_PROP_ALWON,
+ 2, OMAP3_MPU_SOURCE);
+OMAP_SYS_TIMER(3, gp);
+OMAP_SYS_TIMER_INIT(3_secure, sync32k, 12, OMAP3_32K_SOURCE, TIMER_PROP_SECURE,
+ 2, OMAP3_MPU_SOURCE);
+OMAP_SYS_TIMER(3_secure, sync32k);
+OMAP_SYS_TIMER_INIT(3_secure, gp, 1, OMAP3_MPU_SOURCE, TIMER_PROP_ALWON,
+ 2, OMAP3_MPU_SOURCE);
+OMAP_SYS_TIMER(3_secure, gp);
#endif
#ifdef CONFIG_SOC_AM33XX
-OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
- 2, OMAP4_MPU_SOURCE)
-OMAP_SYS_TIMER(3_am33xx)
+OMAP_SYS_TIMER_INIT(3_am33xx, gp, 1, OMAP4_MPU_SOURCE, TIMER_PROP_ALWON,
+ 2, OMAP4_MPU_SOURCE);
+OMAP_SYS_TIMER(3_am33xx, gp);
#endif
#ifdef CONFIG_ARCH_OMAP4
+OMAP_SYS_TIMER_INIT(4, sync32k, 1, OMAP4_32K_SOURCE, TIMER_PROP_ALWON,
+ 2, OMAP4_MPU_SOURCE);
+OMAP_SYS_TIMER_INIT(4, gp, 1, OMAP4_MPU_SOURCE, TIMER_PROP_ALWON,
+ 2, OMAP4_MPU_SOURCE);
#ifdef CONFIG_LOCAL_TIMERS
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
- OMAP44XX_LOCAL_TWD_BASE, 29);
-#endif
-
-static void __init omap4_timer_init(void)
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
+static void __init omap4_local_timer_init(void)
{
- omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon");
- omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
-#ifdef CONFIG_LOCAL_TIMERS
/* Local timers are not supprted on OMAP4430 ES1.0 */
if (omap_rev() != OMAP4430_REV_ES1_0) {
int err;
@@ -622,25 +602,45 @@ static void __init omap4_timer_init(void)
if (err)
pr_err("twd_local_timer_register failed %d\n", err);
}
+}
+#else
+static inline void omap4_local_timer_init(void) {}
#endif
+
+#define OMAP4_LOCAL_TIMER_INIT(clksrc_name) \
+static void __init omap4_local_##clksrc_name##_timer_init(void) \
+{ \
+ omap4_##clksrc_name##_timer_init(); \
+ omap4_local_timer_init(); \
}
-OMAP_SYS_TIMER(4)
+OMAP4_LOCAL_TIMER_INIT(sync32k);
+OMAP_SYS_TIMER(4_local, sync32k);
+OMAP4_LOCAL_TIMER_INIT(gp);
+OMAP_SYS_TIMER(4_local, gp);
#endif
#ifdef CONFIG_SOC_OMAP5
-static void __init omap5_timer_init(void)
-{
- int err;
-
- omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon");
- omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
- realtime_counter_init();
-
- err = arch_timer_of_register();
- if (err)
- pr_err("%s: arch_timer_register failed %d\n", __func__, err);
+OMAP_SYS_TIMER_INIT(5, sync32k, 1, OMAP4_32K_SOURCE, TIMER_PROP_ALWON,
+ 2, OMAP4_MPU_SOURCE);
+OMAP_SYS_TIMER_INIT(5, gp, 1, OMAP4_MPU_SOURCE, TIMER_PROP_ALWON,
+ 2, OMAP4_MPU_SOURCE);
+#define OMAP5_REALTIME_TIMER_INIT(clksrc_name) \
+static void __init omap5_realtime_##clksrc_name##_timer_init(void) \
+{ \
+ int err; \
+ \
+ omap5_##clksrc_name##_timer_init(); \
+ realtime_counter_init(); \
+ \
+ err = arch_timer_of_register(); \
+ if (err) \
+ pr_err("%s: arch_timer_register failed %d\n", \
+ __func__, err); \
}
-OMAP_SYS_TIMER(5)
+OMAP5_REALTIME_TIMER_INIT(sync32k);
+OMAP_SYS_TIMER(5_realtime, sync32k);
+OMAP5_REALTIME_TIMER_INIT(gp);
+OMAP_SYS_TIMER(5_realtime, gp);
#endif
/**
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 82fcb20..9b36a2ad 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -154,6 +154,11 @@ config OMAP_32K_TIMER
intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
+ On OMAP2PLUS this value is only used for CONFIG_HZ and
+ CLOCK_TICK_RATE compile time calculation.
+ The actual timer selection is done in the in the board file
+ through (DT_)MACHINE_START structure.
+
config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
depends on ARCH_OMAP3 && PM
--
1.7.3.4
^ permalink raw reply related
* [Resend PATCH v3 2/4] ARM: at91: atmel-ssc: add device tree support
From: Mark Brown @ 2012-11-07 14:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107143046.GA4576@game.jcrosoft.org>
On Wed, Nov 07, 2012 at 03:30:46PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> the one via ASoC for the driver with the pinctrl for now but MUST add it later
> the arch/arm related via AT91 tree where the pinctrl is mandatory in the dtsi
> I'm no going to spend hours to do the pinctrl to test Bo patch that he is
> supposed to have deon to test this code
> As basically today on DT none of the board will work if BO does no provide the
> pinctrl so for me he MUST put in the dtsi
> is it ok with you?
Or add the pinmux bindings for other IPs over in the pinmux branch and
the pinmux binding for SSC here (which will help with bisection as the
DT bindings for the audio will then always exist in conjunction with the
.dtsi changes for them). Either way is fine with me; I'll leave things
as they are until I see some new patches.
Though I have to say now that I look in -next it's a bit surprising that
there are so many IPs in the file that have no pinmix configuration,
based on what you're saying it seems like the entire board will be
falling over with the pinmux code anyway - in the case of the sam9g20ek
we'd at least need I2C pinmux settings. I may be misunderstanding.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121107/a6759dba/attachment.sig>
^ permalink raw reply
* [PATCH v3 5/9] document: devicetree: bind pinconf with pin-single
From: Haojian Zhuang @ 2012-11-07 15:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5092B9A0.9000204@wwwdotorg.org>
On Fri, Nov 2, 2012 at 2:04 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 10/31/2012 05:04 PM, Haojian Zhuang wrote:
>> Add comments with pinconf & gpio range in the document of
>> pinctrl-single.
>
> I'd tend to suggest separating the series to add GPIO range support and
> pinconf support, especially since didn't Tony suggest a separate driver
> for pinconf? Perhaps that was just for non-generic properties.
>
>> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
>
>> +- pinctrl-single,gpio-ranges : gpio range list of phandles.
>> + Must be present if gpio range phandle is specified.
>> + This property should be existing in .dtsi files for those silicons.
>> +
>> +- pinctrl-single,gpio : array with gpio range start, size & register
>> + offset. Must be present if gpio range phandle is specified.
>> + This property should be existing in .dts files for those boards.
>> +
>> +- pinctrl-single,gpio-func : gpio function value in the pinmux register.
>> + Must be present if gpio range phandle is specified.
>> + This property should be existing in .dts files for those boards.
>
> I don't see any reason why pinctrl-single,gpio or
> pinctrl-single,gpio-func are board-specific rather than SoC-specific.
Oh, I wrote it with error. It should be SoC-specific.
> Surely it's the Soc HW construction that defines how the pinctrl and
> GPIO modules relate to each-other? I would simply remove the last
> sentence from each of the three descriptions above.
>
> Also, isn't this list a list of properties for the main pinctrl-single
> node itself? I think you should split the list up as follows:
>
> 1) A description of the main node
> 2) A list of required and optional properties for the main node
> 3) A description of what a GPIO range node is
> 4) A list of required and optional properties for a GPIO range node.
>
> I think that would explain the whole structure a lot more clearly.
>
> Oh, and why not just get rid of the pinctrl-single,gpio-ranges property
> entirely, and simply make the GPIO range definitions be child nodes of
> the pinctrl-single node? That would require them to either be named
> according to some scheme or have some compatible property to
> differentiate them from any other nodes, but I think that's workable.
>
Em. Removing pinctrl-single,gpio-ranges should be better. Now I define
range as sub node. There're two properties in this sub-node: reg &
pinctrl-single,gpio.
>> @@ -42,6 +77,15 @@ Where 0xdc is the offset from the pinctrl register base address for the
>> device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
>> be used when applying this change to the register.
>>
>> +In case pinctrl device supports gpio function, it needs to define gpio range.
>> +All the phandles of gpio range list should be set in below:
>> +
>> + pinctrl-single,gpio-ranges = <[phandle of gpio range]>;
>> +
>> + [phandle of gpio range]: {
>
> That's a label, not a phandle. The reference to the label gets compiled
> to a phandle in the DTB. The node name is missing. you should probably
> just use an example label and re-write the last 3 lines as:
>
> pinctrl-single,gpio-ranges = <&range0>;
>
> range0: range0 {
>
Updated.
^ permalink raw reply
* [RFC PATCH 4/4] ARM: gic: use a private mapping for CPU target interfaces
From: Nicolas Pitre @ 2012-11-07 15:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107102357.GD23305@mudshark.cambridge.arm.com>
On Wed, 7 Nov 2012, Will Deacon wrote:
> On Tue, Nov 06, 2012 at 10:59:35PM +0000, Nicolas Pitre wrote:
> > On Tue, 6 Nov 2012, Will Deacon wrote:
> > > > /*
> > > > + * Get what the GIC says our CPU mask is.
> > > > + */
> > > > + BUG_ON(cpu >= 8);
> > > > + cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0);
> > >
> > > Making the mask a u8 and using readb_relaxed here makes this bit of code
> > > clearer to me (and the GIC apparently allows such an access to this
> > > register).
> >
> > Not always. At least RTSM throws an exception if you do so.
> > Been there.
>
> That would be a bug in the RTSM then. Have you reported it to support? (if
> not, I can chase this one up). I'd rather we just fix the model than work
> around it in Linux.
I have no problem with you chasing it down with the support people.
I don't want to wait for fixed RTSM versions to be released and the
whole world to migrate to them though.
While the readl is maybe marginally unintuitive compared to a readb
here, the code is always using readl everywhere else already, even using
bit masking and shifting when a readb/writeb could have made the code
much simpler (see gic_set_affinity() for example). I therefore much
prefer to stick to a proven 32-bit access than risking regression on
some possible implementation where the 8-bit access wasn't properly
implemented as the doc says it should and never exercised before.
In other words, I prefer erring on the safe side here.
Nicolas
^ permalink raw reply
* [Resend PATCH v3 2/4] ARM: at91: atmel-ssc: add device tree support
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-11-07 15:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107144450.GF20844@opensource.wolfsonmicro.com>
On 15:44 Wed 07 Nov , Mark Brown wrote:
> On Wed, Nov 07, 2012 at 03:30:46PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
>
> > the one via ASoC for the driver with the pinctrl for now but MUST add it later
>
> > the arch/arm related via AT91 tree where the pinctrl is mandatory in the dtsi
>
> > I'm no going to spend hours to do the pinctrl to test Bo patch that he is
> > supposed to have deon to test this code
>
> > As basically today on DT none of the board will work if BO does no provide the
> > pinctrl so for me he MUST put in the dtsi
>
> > is it ok with you?
>
> Or add the pinmux bindings for other IPs over in the pinmux branch and
> the pinmux binding for SSC here (which will help with bisection as the
> DT bindings for the audio will then always exist in conjunction with the
> .dtsi changes for them). Either way is fine with me; I'll leave things
> as they are until I see some new patches.
>
> Though I have to say now that I look in -next it's a bit surprising that
> there are so many IPs in the file that have no pinmix configuration,
> based on what you're saying it seems like the entire board will be
> falling over with the pinmux code anyway - in the case of the sam9g20ek
> we'd at least need I2C pinmux settings. I may be misunderstanding.
yes I've a new patch series that finish to add them as they was in the Dt
before the add of the pinctrl (macb/usb device /host) i2c after as on 9g20ek
we use gpio i2c so no need to do any pinctrl for now
but now new switch to DT must handle the pinctrl
Best Regards,
J.
^ permalink raw reply
* [Resend PATCH v3 2/4] ARM: at91: atmel-ssc: add device tree support
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-11-07 15:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107144450.GF20844@opensource.wolfsonmicro.com>
On 15:44 Wed 07 Nov , Mark Brown wrote:
> On Wed, Nov 07, 2012 at 03:30:46PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
>
> > the one via ASoC for the driver with the pinctrl for now but MUST add it later
>
> > the arch/arm related via AT91 tree where the pinctrl is mandatory in the dtsi
>
> > I'm no going to spend hours to do the pinctrl to test Bo patch that he is
> > supposed to have deon to test this code
>
> > As basically today on DT none of the board will work if BO does no provide the
> > pinctrl so for me he MUST put in the dtsi
>
> > is it ok with you?
>
> Or add the pinmux bindings for other IPs over in the pinmux branch and
> the pinmux binding for SSC here (which will help with bisection as the
> DT bindings for the audio will then always exist in conjunction with the
> .dtsi changes for them). Either way is fine with me; I'll leave things
> as they are until I see some new patches.
for where it's merge honestly I do not care much but the pinctrl must be
handled correctly
Best Regards,
J.
^ permalink raw reply
* [PATCH v4 0/9] use pinctrl-single in arch mmp
From: Haojian Zhuang @ 2012-11-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
Changelog:
v4:
1. Define gpio range as sub-node, not label. And remove
pinctrl-single,gpio-ranges property.
2. Use new two properties in sub-node, reg &
pinctrl-single,gpio. GPIO number & GPIO function are listed in
the pinctrl-single,gpio property.
3. Reference the names like pinctrl-single,bias.
4. Add compatible name "pinconf-single". If the compatible name is
"pinctrl-single", there's no pinconf. If the compatible name is
"pinconf-single", there's the generic pinconf in pinctrl-single.
5. Update documents.
v3:
1. Add more comments in document.
2. Replace pcs_readl() & pcs_writel() by pcs->read() & pcs->write().
3. Clean code.
v2:
1. Remove "pinctrl-single,gpio-mask". Since GPIO function is one of the
mux function in the pinmux register of both OMAP and PXA/MMP silicons.
Use "pinctrl-single,function-mask" instead.
2. Remove "pinctrl-single,gpio-enable" & "pinctrl-single,gpio-disable".
Use "pinctrl-single,gpio-func" instead. Because GPIO mode is only one
of the mux functions in the pinmux register. Defining "gpio-enable" &
"gpio-disable" are redundant.
3. Define register with __iomem, not u32 type.
4. Remove "pinctrl-single,input-schmit-shift",
"pinctrl-single,power-source-shift", "pinctrl-single,bias-shift". All
these properties could be calculated by mask fields.
5. Return -EPROBE_DEFER if pinmux could be got in device driver. And
the device driver would be probed again deferred.
^ permalink raw reply
* [PATCH v4 1/9] ARM: mmp: select pinctrl driver
From: Haojian Zhuang @ 2012-11-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-1-git-send-email-haojian.zhuang@gmail.com>
Pinctrl driver is necessary for MMP DT & MMP2 DT platforms.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-mmp/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 178d4da..ebdda83 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -89,6 +89,8 @@ config MACH_MMP_DT
select CPU_PXA168
select CPU_PXA910
select USE_OF
+ select PINCTRL
+ select PINCTRL_SINGLE
help
Include support for Marvell MMP2 based platforms using
the device tree. Needn't select any other machine while
@@ -99,6 +101,8 @@ config MACH_MMP2_DT
depends on !CPU_MOHAWK
select CPU_MMP2
select USE_OF
+ select PINCTRL
+ select PINCTRL_SINGLE
help
Include support for Marvell MMP2 based platforms using
the device tree.
--
1.7.10.4
^ permalink raw reply related
* [PATCH v4 2/9] pinctrl: single: support gpio request and free
From: Haojian Zhuang @ 2012-11-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-1-git-send-email-haojian.zhuang@gmail.com>
Marvell's PXA/MMP silicon also match the behavior of pinctrl-single.
Each pin binds to one register. A lot of pins could be configured
as gpio.
Now add these properties in below.
<gpio range phandle>:
include "pinctrl-single,gpio" & "pinctrl,gpio-func" properties.
pinctrl-single,gpio: <gpio base, npins in range, register offset>
pinctrl-single,gpio-func: <gpio function value in mux>
pinctrl-single,gpio-ranges: phandle list of gpio range array
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
drivers/pinctrl/pinctrl-single.c | 100 +++++++++++++++++++++++++++++++++++++-
1 file changed, 98 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 726a729..a7c5fdd 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -30,6 +30,7 @@
#define PCS_MUX_BITS_NAME "pinctrl-single,bits"
#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1)
#define PCS_OFF_DISABLED ~0U
+#define PCS_MAX_GPIO_VALUES 3
/**
* struct pcs_pingroup - pingroups for a function
@@ -77,6 +78,18 @@ struct pcs_function {
};
/**
+ * struct pcs_gpio_range - pinctrl gpio range
+ * @range: subrange of the GPIO number space
+ * @gpio_func: gpio function value in the pinmux register
+ * @func_en: need to handle gpio function in the pinmux register
+ */
+struct pcs_gpio_range {
+ struct pinctrl_gpio_range range;
+ int gpio_func;
+ unsigned func_en:1;
+};
+
+/**
* struct pcs_data - wrapper for data needed by pinctrl framework
* @pa: pindesc array
* @cur: index to current element
@@ -123,8 +136,10 @@ struct pcs_name {
* @ftree: function index radix tree
* @pingroups: list of pingroups
* @functions: list of functions
+ * @ranges: list of gpio ranges
* @ngroups: number of pingroups
* @nfuncs: number of functions
+ * @nranges: number of gpio ranges
* @desc: pin controller descriptor
* @read: register read function to use
* @write: register write function to use
@@ -148,8 +163,10 @@ struct pcs_device {
struct radix_tree_root ftree;
struct list_head pingroups;
struct list_head functions;
+ struct list_head ranges;
unsigned ngroups;
unsigned nfuncs;
+ unsigned nranges;
struct pinctrl_desc desc;
unsigned (*read)(void __iomem *reg);
void (*write)(unsigned val, void __iomem *reg);
@@ -403,9 +420,27 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
}
static int pcs_request_gpio(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range, unsigned offset)
+ struct pinctrl_gpio_range *range, unsigned pin)
{
- return -ENOTSUPP;
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ struct pcs_gpio_range *gpio = NULL;
+ int end, mux_bytes;
+ unsigned data;
+
+ gpio = container_of(range, struct pcs_gpio_range, range);
+ if (!gpio->func_en)
+ return -ENOTSUPP;
+ end = range->pin_base + range->npins - 1;
+ if (pin < range->pin_base || pin > end) {
+ dev_err(pctldev->dev, "pin %d isn't in the range of "
+ "%d to %d\n", pin, range->pin_base, end);
+ return -EINVAL;
+ }
+ mux_bytes = pcs->width / BITS_PER_BYTE;
+ data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
+ data |= gpio->gpio_func;
+ pcs->write(data, pcs->base + pin * mux_bytes);
+ return 0;
}
static struct pinmux_ops pcs_pinmux_ops = {
@@ -879,6 +914,62 @@ static void pcs_free_resources(struct pcs_device *pcs)
static struct of_device_id pcs_of_match[];
+static int __devinit pcs_add_gpio_range(struct device_node *node,
+ struct pcs_device *pcs)
+{
+ struct pcs_gpio_range *gpio;
+ struct device_node *np;
+ const __be32 *list;
+ const char list_name[] = "pinctrl-single,gpio-ranges";
+ const char name[] = "pinctrl-single";
+ u32 gpiores[PCS_MAX_GPIO_VALUES];
+ int ret, size, i, mux_bytes = 0;
+
+ list = of_get_property(node, list_name, &size);
+ if (!list)
+ return 0;
+ size = size / sizeof(*list);
+ for (i = 0; i < size; i++) {
+ np = of_parse_phandle(node, list_name, i);
+ memset(gpiores, 0, sizeof(u32) * PCS_MAX_GPIO_VALUES);
+ ret = of_property_read_u32_array(np, "pinctrl-single,gpio",
+ gpiores, PCS_MAX_GPIO_VALUES);
+ if (ret < 0)
+ return -ENOENT;
+ gpio = devm_kzalloc(pcs->dev, sizeof(*gpio), GFP_KERNEL);
+ if (!gpio) {
+ dev_err(pcs->dev, "failed to allocate pcs gpio\n");
+ return -ENOMEM;
+ }
+ gpio->range.id = i;
+ gpio->range.base = gpiores[0];
+ gpio->range.npins = gpiores[1];
+ gpio->range.name = devm_kzalloc(pcs->dev, sizeof(name),
+ GFP_KERNEL);
+ if (!gpio->range.name) {
+ dev_err(pcs->dev, "failed to allocate range name\n");
+ return -ENOMEM;
+ }
+ memcpy(&gpio->range.name, name, sizeof(name));
+ mux_bytes = pcs->width / BITS_PER_BYTE;
+ gpio->range.pin_base = gpiores[2] / mux_bytes;
+ memset(gpiores, 0, sizeof(u32) * PCS_MAX_GPIO_VALUES);
+ ret = of_property_read_u32(np, "pinctrl-single,gpio-func",
+ &gpio->gpio_func);
+ if (ret < 0)
+ return -ENOENT;
+ gpio->func_en = 1;
+
+ mutex_lock(&pcs->mutex);
+ list_add_tail(&gpio->range.node, &pcs->ranges);
+ pcs->nranges++;
+ mutex_unlock(&pcs->mutex);
+
+ pinctrl_add_gpio_range(pcs->pctl, &gpio->range);
+ }
+ return 0;
+}
+
static int __devinit pcs_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -900,6 +991,7 @@ static int __devinit pcs_probe(struct platform_device *pdev)
mutex_init(&pcs->mutex);
INIT_LIST_HEAD(&pcs->pingroups);
INIT_LIST_HEAD(&pcs->functions);
+ INIT_LIST_HEAD(&pcs->ranges);
PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
"register width not specified\n");
@@ -975,6 +1067,10 @@ static int __devinit pcs_probe(struct platform_device *pdev)
goto free;
}
+ ret = pcs_add_gpio_range(np, pcs);
+ if (ret < 0)
+ goto free;
+
dev_info(pcs->dev, "%i pins at pa %p size %u\n",
pcs->desc.npins, pcs->base, pcs->size);
--
1.7.10.4
^ permalink raw reply related
* [PATCH v4 3/9] pinctrl: single: support pinconf generic
From: Haojian Zhuang @ 2012-11-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-1-git-send-email-haojian.zhuang@gmail.com>
Add pinconf generic support with POWER SOURCE, BIAS PULL.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/pinctrl-single.c | 354 +++++++++++++++++++++++++++++++-------
2 files changed, 293 insertions(+), 62 deletions(-)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 7bf914d..e9f2d2d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -139,6 +139,7 @@ config PINCTRL_SINGLE
depends on OF
select PINMUX
select PINCONF
+ select GENERIC_PINCONF
help
This selects the device tree based generic pinctrl driver.
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index a7c5fdd..77aec05 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -20,6 +20,7 @@
#include <linux/of_device.h>
#include <linux/of_address.h>
+#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
@@ -30,7 +31,7 @@
#define PCS_MUX_BITS_NAME "pinctrl-single,bits"
#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1)
#define PCS_OFF_DISABLED ~0U
-#define PCS_MAX_GPIO_VALUES 3
+#define PCS_MAX_GPIO_VALUES 2
/**
* struct pcs_pingroup - pingroups for a function
@@ -81,12 +82,20 @@ struct pcs_function {
* struct pcs_gpio_range - pinctrl gpio range
* @range: subrange of the GPIO number space
* @gpio_func: gpio function value in the pinmux register
- * @func_en: need to handle gpio function in the pinmux register
*/
struct pcs_gpio_range {
struct pinctrl_gpio_range range;
int gpio_func;
- unsigned func_en:1;
+};
+
+/**
+ * struct pcs_conf - configuration of pinctrl device
+ * @nconf: number of configuration that is defined for pinconf
+ * @is_generic: for pin controller that want to use the generic interface
+ */
+struct pcs_conf {
+ unsigned nconfs;
+ bool is_generic;
};
/**
@@ -130,16 +139,24 @@ struct pcs_name {
* @fshift: function register shift
* @foff: value to turn mux off
* @fmax: max number of functions in fmask
+ * @bmask: bias mask in pinconf
+ * @bshift: bias register shift
+ * @bdis: bias disable value in pinconf
+ * @bpullup: bias pull up value in pinconf
+ * @bpulldown: bias pull down value in pinconf
+ * @ismask: input schmitt mask in pinconf
+ * @isshift: input schmitt register shift
+ * @psmask: power source mask in pinconf
+ * @psshift: power source register shift
* @names: array of register names for pins
* @pins: physical pins on the SoC
+ * @conf: value of pinconf
* @pgtree: pingroup index radix tree
* @ftree: function index radix tree
* @pingroups: list of pingroups
* @functions: list of functions
- * @ranges: list of gpio ranges
* @ngroups: number of pingroups
* @nfuncs: number of functions
- * @nranges: number of gpio ranges
* @desc: pin controller descriptor
* @read: register read function to use
* @write: register write function to use
@@ -156,17 +173,25 @@ struct pcs_device {
unsigned fshift;
unsigned foff;
unsigned fmax;
+ unsigned bmask;
+ unsigned bshift;
+ unsigned bdis;
+ unsigned bpullup;
+ unsigned bpulldown;
+ unsigned ismask;
+ unsigned isshift;
+ unsigned psmask;
+ unsigned psshift;
bool bits_per_mux;
struct pcs_name *names;
struct pcs_data pins;
+ struct pcs_conf conf;
struct radix_tree_root pgtree;
struct radix_tree_root ftree;
struct list_head pingroups;
struct list_head functions;
- struct list_head ranges;
unsigned ngroups;
unsigned nfuncs;
- unsigned nranges;
struct pinctrl_desc desc;
unsigned (*read)(void __iomem *reg);
void (*write)(unsigned val, void __iomem *reg);
@@ -428,8 +453,6 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev,
unsigned data;
gpio = container_of(range, struct pcs_gpio_range, range);
- if (!gpio->func_en)
- return -ENOTSUPP;
end = range->pin_base + range->npins - 1;
if (pin < range->pin_base || pin > end) {
dev_err(pctldev->dev, "pin %d isn't in the range of "
@@ -452,28 +475,163 @@ static struct pinmux_ops pcs_pinmux_ops = {
.gpio_request_enable = pcs_request_gpio,
};
+static void pcs_free_pingroups(struct pcs_device *pcs);
+
static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *config)
{
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ unsigned data;
+ u32 offset;
+
+ offset = pin * (pcs->width / BITS_PER_BYTE);
+ data = pcs->read(pcs->base + offset);
+
+ switch (param) {
+ case PIN_CONFIG_POWER_SOURCE:
+ if (pcs->psmask == PCS_OFF_DISABLED
+ || pcs->psshift == PCS_OFF_DISABLED)
+ return -ENOTSUPP;
+ data &= pcs->psmask;
+ data = data >> pcs->psshift;
+ *config = data;
+ return 0;
+ break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (pcs->bmask == PCS_OFF_DISABLED
+ || pcs->bshift == PCS_OFF_DISABLED
+ || pcs->bdis == PCS_OFF_DISABLED)
+ return -ENOTSUPP;
+ data &= pcs->bmask;
+ *config = 0;
+ if (data == pcs->bdis)
+ return 0;
+ else
+ return -EINVAL;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (pcs->bmask == PCS_OFF_DISABLED
+ || pcs->bshift == PCS_OFF_DISABLED
+ || pcs->bpullup == PCS_OFF_DISABLED)
+ return -ENOTSUPP;
+ data &= pcs->bmask;
+ *config = 0;
+ if (data == pcs->bpullup)
+ return 0;
+ else
+ return -EINVAL;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (pcs->bmask == PCS_OFF_DISABLED
+ || pcs->bshift == PCS_OFF_DISABLED
+ || pcs->bpulldown == PCS_OFF_DISABLED)
+ return -ENOTSUPP;
+ data &= pcs->bmask;
+ *config = 0;
+ if (data == pcs->bpulldown)
+ return 0;
+ else
+ return -EINVAL;
+ break;
+ default:
+ break;
+ }
return -ENOTSUPP;
}
static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long config)
{
- return -ENOTSUPP;
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param config_param = pinconf_to_config_param(config);
+ unsigned ret, mask = ~0UL;
+ u32 offset, data;
+
+ switch (config_param) {
+ case PIN_CONFIG_POWER_SOURCE:
+ if (pcs->psmask == PCS_OFF_DISABLED
+ || pcs->psshift == PCS_OFF_DISABLED)
+ return 0;
+ mask = pcs->psmask;
+ data = (pinconf_to_config_argument(config) << pcs->psshift)
+ & pcs->psmask;
+ break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (pcs->bmask == PCS_OFF_DISABLED
+ || pcs->bshift == PCS_OFF_DISABLED)
+ return 0;
+ mask = pcs->bmask;
+ data = (pinconf_to_config_argument(config) << pcs->bshift)
+ & pcs->bmask;
+ break;
+ default:
+ return 0;
+ }
+ offset = pin * (pcs->width / BITS_PER_BYTE);
+ ret = pcs->read(pcs->base + offset) & ~mask;
+ pcs->write(ret | data, pcs->base + offset);
+ return 0;
}
static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned group, unsigned long *config)
{
- return -ENOTSUPP;
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ struct pcs_pingroup *pins;
+
+ pins = radix_tree_lookup(&pcs->pgtree, group);
+ if (!pins) {
+ dev_err(pcs->dev, "%s could not find pingroup%i\n",
+ __func__, group);
+ return -EINVAL;
+ }
+ return pcs_pinconf_get(pctldev, pins->gpins[0], config);
}
static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long config)
{
- return -ENOTSUPP;
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param config_param = pinconf_to_config_param(config);
+ struct pcs_pingroup *pins;
+ u32 offset, data;
+ unsigned ret, mask = ~0UL;
+ int i;
+
+ switch (config_param) {
+ case PIN_CONFIG_POWER_SOURCE:
+ if (pcs->psmask == PCS_OFF_DISABLED
+ || pcs->psshift == PCS_OFF_DISABLED)
+ return 0;
+ mask = pcs->psmask;
+ data = (pinconf_to_config_argument(config) << pcs->psshift)
+ & pcs->psmask;
+ break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (pcs->bmask == PCS_OFF_DISABLED
+ || pcs->bshift == PCS_OFF_DISABLED)
+ return 0;
+ mask = pcs->bmask;
+ data = (pinconf_to_config_argument(config) << pcs->bshift)
+ & pcs->bmask;
+ break;
+ default:
+ return 0;
+ }
+
+ pins = radix_tree_lookup(&pcs->pgtree, group);
+ if (!pins) {
+ dev_err(pcs->dev, "%s could not find pingroup%i\n",
+ __func__, group);
+ return -EINVAL;
+ }
+ for (i = 0; i < pins->ngpins; i++) {
+ offset = pins->gpins[i] * (pcs->width / BITS_PER_BYTE);
+ ret = pcs->read(pcs->base + offset) & ~mask;
+ pcs->write(ret | data, pcs->base + offset);
+ }
+ return 0;
}
static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
@@ -688,6 +846,7 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
* @pcs: pinctrl driver instance
* @np: device node of the mux entry
* @map: map entry
+ * @num_configs: number of pin configurations
* @pgnames: pingroup names
*
* Note that this binding currently supports only sets of one register + value.
@@ -707,9 +866,12 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
const char **pgnames)
{
struct pcs_func_vals *vals;
+ struct pinctrl_map *p = *map;
const __be32 *mux;
int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM;
struct pcs_function *function;
+ unsigned long *config;
+ u32 value, nconfs;
if (pcs->bits_per_mux) {
params = 3;
@@ -763,6 +925,7 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
pins[found++] = pin;
}
+ nconfs = pcs->conf.nconfs;
pgnames[0] = np->name;
function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
if (!function)
@@ -772,12 +935,42 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
if (res < 0)
goto free_function;
- (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
- (*map)->data.mux.group = np->name;
- (*map)->data.mux.function = np->name;
+ p->type = PIN_MAP_TYPE_MUX_GROUP;
+ p->data.mux.group = np->name;
+ p->data.mux.function = np->name;
+
+ if (!nconfs)
+ return 0;
+
+ config = devm_kzalloc(pcs->dev, sizeof(*config) * nconfs, GFP_KERNEL);
+ if (!config) {
+ res = -ENOMEM;
+ goto free_pingroup;
+ }
+ index = 0;
+ if (!of_property_read_u32(np, "pinctrl-single,input-schmitt", &value))
+ config[index++] =
+ pinconf_to_config_packed(PIN_CONFIG_INPUT_SCHMITT,
+ value & 0xffff);
+ if (!of_property_read_u32(np, "pinctrl-single,bias", &value))
+ config[index++] =
+ pinconf_to_config_packed(PIN_CONFIG_BIAS_DISABLE,
+ value & 0xffff);
+ if (!of_property_read_u32(np, "pinctrl-single,power-source", &value))
+ config[index++] =
+ pinconf_to_config_packed(PIN_CONFIG_POWER_SOURCE,
+ value & 0xffff);
+ p++;
+ p->type = PIN_MAP_TYPE_CONFIGS_GROUP;
+ p->data.configs.group_or_pin = np->name;
+ p->data.configs.configs = config;
+ p->data.configs.num_configs = nconfs;
return 0;
+free_pingroup:
+ pcs_free_pingroups(pcs);
+
free_function:
pcs_remove_function(pcs, function);
@@ -789,6 +982,7 @@ free_vals:
return res;
}
+
/**
* pcs_dt_node_to_map() - allocates and parses pinctrl maps
* @pctldev: pinctrl instance
@@ -806,34 +1000,27 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
pcs = pinctrl_dev_get_drvdata(pctldev);
- *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL);
- if (!map)
- return -ENOMEM;
+ if (!pcs->conf.nconfs)
+ *num_maps = 1;
+ else
+ *num_maps = 2;
- *num_maps = 0;
+ *map = devm_kzalloc(pcs->dev, sizeof(**map) * (*num_maps), GFP_KERNEL);
+ if (!*map)
+ return -ENOMEM;
pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
- if (!pgnames) {
- ret = -ENOMEM;
- goto free_map;
- }
+ if (!pgnames)
+ return -ENOMEM;
ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames);
if (ret < 0) {
dev_err(pcs->dev, "no pins entries for %s\n",
np_config->name);
- goto free_pgnames;
+ return ret;
}
- *num_maps = 1;
return 0;
-
-free_pgnames:
- devm_kfree(pcs->dev, pgnames);
-free_map:
- devm_kfree(pcs->dev, *map);
-
- return ret;
}
/**
@@ -918,52 +1105,40 @@ static int __devinit pcs_add_gpio_range(struct device_node *node,
struct pcs_device *pcs)
{
struct pcs_gpio_range *gpio;
- struct device_node *np;
- const __be32 *list;
- const char list_name[] = "pinctrl-single,gpio-ranges";
+ struct device_node *child;
+ struct resource r;
const char name[] = "pinctrl-single";
u32 gpiores[PCS_MAX_GPIO_VALUES];
- int ret, size, i, mux_bytes = 0;
+ int ret, i = 0, mux_bytes = 0;
- list = of_get_property(node, list_name, &size);
- if (!list)
- return 0;
- size = size / sizeof(*list);
- for (i = 0; i < size; i++) {
- np = of_parse_phandle(node, list_name, i);
+ for_each_child_of_node(node, child) {
+ ret = of_address_to_resource(child, 0, &r);
+ if (ret < 0)
+ continue;
memset(gpiores, 0, sizeof(u32) * PCS_MAX_GPIO_VALUES);
- ret = of_property_read_u32_array(np, "pinctrl-single,gpio",
+ ret = of_property_read_u32_array(child, "pinctrl-single,gpio",
gpiores, PCS_MAX_GPIO_VALUES);
if (ret < 0)
- return -ENOENT;
+ continue;
gpio = devm_kzalloc(pcs->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio) {
dev_err(pcs->dev, "failed to allocate pcs gpio\n");
return -ENOMEM;
}
- gpio->range.id = i;
- gpio->range.base = gpiores[0];
- gpio->range.npins = gpiores[1];
gpio->range.name = devm_kzalloc(pcs->dev, sizeof(name),
GFP_KERNEL);
if (!gpio->range.name) {
dev_err(pcs->dev, "failed to allocate range name\n");
return -ENOMEM;
}
- memcpy(&gpio->range.name, name, sizeof(name));
- mux_bytes = pcs->width / BITS_PER_BYTE;
- gpio->range.pin_base = gpiores[2] / mux_bytes;
- memset(gpiores, 0, sizeof(u32) * PCS_MAX_GPIO_VALUES);
- ret = of_property_read_u32(np, "pinctrl-single,gpio-func",
- &gpio->gpio_func);
- if (ret < 0)
- return -ENOENT;
- gpio->func_en = 1;
+ memcpy((char *)gpio->range.name, name, sizeof(name));
- mutex_lock(&pcs->mutex);
- list_add_tail(&gpio->range.node, &pcs->ranges);
- pcs->nranges++;
- mutex_unlock(&pcs->mutex);
+ gpio->range.id = i++;
+ gpio->range.base = gpiores[0];
+ gpio->gpio_func = gpiores[1];
+ mux_bytes = pcs->width / BITS_PER_BYTE;
+ gpio->range.pin_base = (r.start - pcs->res->start) / mux_bytes;
+ gpio->range.npins = (r.end - r.start) / mux_bytes + 1;
pinctrl_add_gpio_range(pcs->pctl, &gpio->range);
}
@@ -976,11 +1151,13 @@ static int __devinit pcs_probe(struct platform_device *pdev)
const struct of_device_id *match;
struct resource *res;
struct pcs_device *pcs;
+ const struct pcs_conf *conf;
int ret;
match = of_match_device(pcs_of_match, &pdev->dev);
if (!match)
return -EINVAL;
+ conf = match->data;
pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
if (!pcs) {
@@ -988,10 +1165,10 @@ static int __devinit pcs_probe(struct platform_device *pdev)
return -ENOMEM;
}
pcs->dev = &pdev->dev;
+ memcpy(&pcs->conf, conf, sizeof(*conf));
mutex_init(&pcs->mutex);
INIT_LIST_HEAD(&pcs->pingroups);
INIT_LIST_HEAD(&pcs->functions);
- INIT_LIST_HEAD(&pcs->ranges);
PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
"register width not specified\n");
@@ -1009,6 +1186,46 @@ static int __devinit pcs_probe(struct platform_device *pdev)
pcs->bits_per_mux = of_property_read_bool(np,
"pinctrl-single,bit-per-mux");
+ if (conf->nconfs) {
+ pcs_pinconf_ops.is_generic = true;
+ ret = of_property_read_u32(np,
+ "pinctrl-single,power-source-mask",
+ &pcs->psmask);
+ if (ret) {
+ pcs->psmask = PCS_OFF_DISABLED;
+ pcs->psshift = PCS_OFF_DISABLED;
+ } else
+ pcs->psshift = ffs(pcs->psmask) - 1;
+ ret = of_property_read_u32(np,
+ "pinctrl-single,bias-mask", &pcs->bmask);
+ if (ret) {
+ pcs->bmask = PCS_OFF_DISABLED;
+ pcs->bshift = PCS_OFF_DISABLED;
+ } else
+ pcs->bshift = ffs(pcs->bmask) - 1;
+ ret = of_property_read_u32(np,
+ "pinctrl-single,bias-disable", &pcs->bdis);
+ if (ret)
+ pcs->bdis = PCS_OFF_DISABLED;
+ ret = of_property_read_u32(np,
+ "pinctrl-single,bias-pull-up", &pcs->bpullup);
+ if (ret)
+ pcs->bpullup = PCS_OFF_DISABLED;
+ ret = of_property_read_u32(np,
+ "pinctrl-single,bias-pull-down",
+ &pcs->bpulldown);
+ if (ret)
+ pcs->bpulldown = PCS_OFF_DISABLED;
+ ret = of_property_read_u32(np,
+ "pinctrl-single,input-schmitt-mask",
+ &pcs->ismask);
+ if (ret) {
+ pcs->ismask = PCS_OFF_DISABLED;
+ pcs->isshift = PCS_OFF_DISABLED;
+ } else
+ pcs->isshift = ffs(pcs->ismask) - 1;
+ }
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(pcs->dev, "could not get resource\n");
@@ -1094,8 +1311,21 @@ static int __devexit pcs_remove(struct platform_device *pdev)
return 0;
}
+/* PINCONF isn't supported */
+static struct pcs_conf pinctrl_conf __devinitdata = {
+ .nconfs = 0,
+ .is_generic = false,
+};
+
+/* Generic PINCONF is supported. */
+static struct pcs_conf pinconf_conf __devinitdata = {
+ .nconfs = 7,
+ .is_generic = true,
+};
+
static struct of_device_id pcs_of_match[] __devinitdata = {
- { .compatible = DRIVER_NAME, },
+ { .compatible = "pinctrl-single", .data = &pinctrl_conf },
+ { .compatible = "pinconf-single", .data = &pinconf_conf },
{ },
};
MODULE_DEVICE_TABLE(of, pcs_of_match);
--
1.7.10.4
^ permalink raw reply related
* [PATCH v4 4/9] ARM: dts: support pinctrl single in pxa910
From: Haojian Zhuang @ 2012-11-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-1-git-send-email-haojian.zhuang@gmail.com>
Add pinctrl-single support with device tree in pxa910 dkb platform.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
arch/arm/boot/dts/pxa910-dkb.dts | 186 +++++++++++++++++++++++++++++++++++++-
arch/arm/boot/dts/pxa910.dtsi | 74 +++++++++++++++
2 files changed, 259 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
index 595492a..5a8b533 100644
--- a/arch/arm/boot/dts/pxa910-dkb.dts
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -24,10 +24,194 @@
soc {
apb at d4000000 {
- uart1: uart at d4017000 {
+ pmx: pinmux at d401e000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&board_pins>;
+
+ board_pins: pinmux_board_pins {
+ /* pins not owned by device driver */
+ /* w1 */
+ pinctrl-single,pins = <
+ 0x0cc 0x2 /* CLK_REQ_W1 */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0>;
+ };
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ 0x198 0x6 /* GPIO47_UART1_RXD */
+ 0x19c 0x6 /* GPIO48_UART1_TXD */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0x6>;
+ };
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ 0x150 0x4 /* GPIO29_UART2_CTS */
+ 0x154 0x4 /* GPIO30_UART2_RTS */
+ 0x158 0x4 /* GPIO31_UART2_TXD */
+ 0x15c 0x4 /* GPIO32_UART2_RXD */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0>;
+ };
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ 0x188 0x7 /* GPIO43_UART3_RXD */
+ 0x18c 0x7 /* GPIO44_UART3_TXD */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0>;
+ };
+ twsi1_pins: pinmux_twsi1_pins {
+ pinctrl-single,pins = <
+ 0x1b0 0x2 /* GPIO53_TWSI_SCL */
+ 0x1b4 0x2 /* GPIO54_TWSI_SDA */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0>;
+ };
+ nand_pins: pinmux_nand_pins {
+ pinctrl-single,pins = <
+ 0x040 0x0 /* ND_IO0 */
+ 0x03c 0x0 /* ND_IO1 */
+ 0x038 0x0 /* ND_IO2 */
+ 0x034 0x0 /* ND_IO3 */
+ 0x030 0x0 /* ND_IO4 */
+ 0x02c 0x0 /* ND_IO5 */
+ 0x028 0x0 /* ND_IO6 */
+ 0x024 0x0 /* ND_IO7 */
+ 0x020 0x0 /* ND_IO8 */
+ 0x01c 0x0 /* ND_IO9 */
+ 0x018 0x0 /* ND_IO10 */
+ 0x014 0x0 /* ND_IO11 */
+ 0x010 0x0 /* ND_IO12 */
+ 0x00c 0x0 /* ND_IO13 */
+ 0x008 0x0 /* ND_IO14 */
+ 0x004 0x0 /* ND_IO15 */
+ 0x044 0x0 /* ND_nCS0 */
+ 0x060 0x1 /* ND_ALE */
+ 0x05c 0x0 /* ND_CLE */
+ 0x054 0x1 /* ND_nWE */
+ 0x058 0x1 /* ND_nRE */
+ 0x068 0x0 /* ND_RDY0 */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0>;
+ };
+ mmc1_ldata_pins: pinmux_mmc1_ldata_pins {
+ pinctrl-single,pins = <
+ 0x0a0 0x0 /* MMC1_DATA0 */
+ 0x09c 0x0 /* MMC1_DATA1 */
+ 0x098 0x0 /* MMC1_DATA2 */
+ 0x094 0x0 /* MMC1_DATA3 */
+ >;
+ pinctrl-single,power-source = <0x3>;
+ pinctrl-single,bias = <0>;
+ };
+ mmc1_hdata_pins: pinmux_mmc1_hdata_pins {
+ pinctrl-single,pins = <
+ 0x090 0x0 /* MMC1_DATA4 */
+ 0x08c 0x0 /* MMC1_DATA5 */
+ 0x088 0x0 /* MMC1_DATA6 */
+ 0x084 0x0 /* MMC1_DATA7 */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0>;
+ };
+ mmc1_clk_pins: pinmux_mmc1_clk_pins {
+ pinctrl-single,pins = <
+ 0x0a4 0x0 /* MMC1_CMD */
+ 0x0a8 0x0 /* MMC1_CLK */
+ >;
+ pinctrl-single,power-source = <0x3>;
+ pinctrl-single,bias = <0>;
+ };
+ mmc1_cd_pins: pinmux_mmc1_cd_pins {
+ pinctrl-single,pins = <
+ 0x0ac 0x0 /* MMC1_CD */
+ 0x0b0 0x0 /* MMC1_WP */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0>;
+ };
+ mmc2_pins: pinmux_mmc2_pins {
+ pinctrl-single,pins = <
+ 0x180 0x1 /* MMC2_CMD */
+ 0x184 0x1 /* MMC2_CLK */
+ 0x17c 0x1 /* MMC2_DATA0 */
+ 0x178 0x1 /* MMC2_DATA1 */
+ 0x174 0x1 /* MMC2_DATA2 */
+ 0x170 0x1 /* MMC2_DATA3 */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0>;
+ };
+ ssp1_pins: pinmux_ssp1_pins {
+ pinctrl-single,pins = <
+ 0x130 0x1 /* GPIO21_SSP1_SCLK */
+ 0x134 0x1 /* GPIO22_SSP1_FRM */
+ 0x138 0x1 /* GPIO23_SSP1_TXD */
+ 0x13c 0x1 /* GPIO24_SSP1_RXD */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0>;
+ };
+ keypad_pins: pinmux_keypad_pins {
+ pinctrl-single,pins = <
+ 0x0dc 0x1 /* GPIO0_MKIN0 */
+ 0x0e0 0x1 /* GPIO1_MKOUT0 */
+ 0x0e4 0x1 /* GPIO2_MKIN1 */
+ 0x0e8 0x1 /* GPIO3_MKOUT1 */
+ 0x0ec 0x1 /* GPIO4_MKIN2 */
+ 0x0f0 0x1 /* GPIO5_MKOUT2 */
+ 0x0f4 0x1 /* GPIO6_MKIN3 */
+ 0x0f8 0x1 /* GPIO7_MKOUT3 */
+ 0x0fc 0x1 /* GPIO8_MKIN4 */
+ 0x100 0x1 /* GPIO9_MKOUT4 */
+ 0x10c 0x1 /* GPIO12_MKIN6 */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0>;
+ };
+ nfc_pins: pinmux_nfc_pins {
+ pinctrl-single,pins = <
+ 0x120 0x0 /* GPIO17 */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0>;
+ };
+ wlan_pins: pinmux_wlan_pins {
+ pinctrl-single,pins = <
+ 0x114 0x0 /* GPIO14 */
+ 0x12c 0x0 /* GPIO20 */
+ 0x160 0x0 /* GPIO33 */
+ 0x164 0x0 /* GPIO34 */
+ 0x168 0x0 /* GPIO35 */
+ 0x16c 0x0 /* GPIO36 */
+ >;
+ pinctrl-single,power-source = <0x2>;
+ pinctrl-single,bias = <0>;
+ };
+ };
+ uart1: uart at d4017000 { /* FFUART */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+ };
+ uart2: uart at d4018000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+ };
+ uart3: uart at d4036000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
status = "okay";
};
twsi1: i2c at d4011000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&twsi1_pins>;
status = "okay";
pmic: 88pm860x at 34 {
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index 825aaca..aac5a2e 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -54,6 +54,80 @@
reg = <0xd4000000 0x00200000>;
ranges;
+ pmx: pinmux at d401e000 {
+ compatible = "pinconf-single";
+ reg = <0xd401e000 0x0330>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+ pinctrl-single,power-source-mask = <0x1800>;
+ pinctrl-single,bias-mask = <0xe000>;
+ pinctrl-single,bias-disable = <0>;
+ pinctrl-single,bias-pull-down = <0xa000>;
+ pinctrl-single,bias-pull-up = <0xc000>;
+ pinctrl-single,input-schmitt-mask = <0x70>;
+
+ range0: range at d401e0dc {
+ /* GPIO0 ~ GPIO54 */
+ reg = <0xd401e0dc 0xdc>;
+ /* gpio base & gpio func */
+ pinctrl-single,gpio = <0 0>;
+ };
+ range1: range at d401e2f0 {
+ /* GPIO55 ~ GPIO59 */
+ reg = <0xd401e2f0 0x14>;
+ pinctrl-single,gpio = <55 1>;
+ };
+ range2: range at d401e304 {
+ /* GPIO60 ~ GPIO66 */
+ reg = <0xd401e304 0x1c>;
+ pinctrl-single,gpio = <60 0>;
+ };
+ range3: range at d401e1b8 {
+ /* GPIO67 ~ GPIO109 */
+ reg = <0xd401e1b8 0xac>;
+ pinctrl-single,gpio = <67 0>;
+ };
+ range4: range at d401e298 {
+ /* GPIO110 ~ GPIO116 */
+ reg = <0xd401e298 0x1c>;
+ pinctrl-single,gpio = <110 0>;
+ };
+ range5: range at d401e0b4 {
+ /* GPIO117 ~ GPIO120 */
+ reg = <0xd401e0b4 0x10>;
+ pinctrl-single,gpio = <117 1>;
+ };
+ range6: range at d401e32c {
+ /* GPIO121 */
+ reg = <0xd401e32c 0x04>;
+ pinctrl-single,gpio = <121 0>;
+ };
+ range7: range at d401e0c8 {
+ /* GPIO122 ~ GPIO123 */
+ reg = <0xd401e0c8 0x08>;
+ pinctrl-single,gpio = <122 1>;
+ };
+ range8: range at d401e0d0 {
+ /* GPIO124 */
+ reg = <0xd401e0d0 0x04>;
+ pinctrl-single,gpio = <124 0>;
+ };
+ range9: range at d401e0d4 {
+ /* GPIO125 */
+ reg = <0xd401e0d4 0x04>;
+ pinctrl-single,gpio = <125 1>;
+ };
+ range10: range at d401e06c {
+ /* GPIO126 ~ GPIO127 */
+ reg = <0xd401e06c 0x08>;
+ pinctrl-single,gpio = <126 0>;
+ };
+ };
+
timer0: timer at d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
--
1.7.10.4
^ permalink raw reply related
* [PATCH v4 5/9] document: devicetree: bind pinconf with pin-single
From: Haojian Zhuang @ 2012-11-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-1-git-send-email-haojian.zhuang@gmail.com>
Add comments with pinconf & gpio range in the document of
pinctrl-single.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
.../devicetree/bindings/pinctrl/pinctrl-single.txt | 67 +++++++++++++++++++-
1 file changed, 66 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index 2c81e45..0b8705f 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -1,7 +1,9 @@
One-register-per-pin type device tree based pinctrl driver
Required properties:
-- compatible : "pinctrl-single"
+- compatible : "pinctrl-single" or "pinconf-single".
+ "pinctrl-single" means that pinconf isn't supported.
+ "pinconf-single" means that generic pinconf is supported.
- reg : offset and length of the register set for the mux registers
@@ -14,9 +16,33 @@ Optional properties:
- pinctrl-single,function-off : function off mode for disabled state if
available and same for all registers; if not specified, disabling of
pin functions is ignored
+
- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
more than one pin
+- pinctrl-single,power-source-mask : mask of setting power source in
+ the pinmux register
+
+- pinctrl-single,power-source : value of setting power source field
+ in the pinmux register
+
+- pinctrl-single,bias-mask : mask of setting bias value in the pinmux
+ register
+
+- pinctrl-single,bias-disable : value of disabling bias in the pinmux
+ register
+
+- pinctrl-single,bias-pull-down : value of setting bias pull down in
+ the pinmux register
+
+- pinctrl-single,bias-pull-up : value of setting bias pull up in the
+ pinmux register
+
+- pinctrl-single,bias : value of setting bias in the pinmux register
+
+- pinctrl-single,input-schmitt-mask : mask of setting input schmitt
+ in the pinmux register
+
This driver assumes that there is only one register for each pin (unless the
pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
specified in the pinctrl-bindings.txt document in this directory.
@@ -42,6 +68,25 @@ Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
be used when applying this change to the register.
+
+Optional sub-node: In case some pins could be configured as GPIO in the pinmux
+register. If both GPIO nubmer and pin base of those pins are in ascending order,
+those pins could be defined as a GPIO range. The sub-node should be defined in
+.dtsi files of those silicons.
+
+Required properties in sub-node:
+- reg : offset and length of the GPIO range sub-node.
+
+- pinctrl-single,gpio : array of GPIO base number in the range and the GPIO
+ function in the pinmux register.
+
+ range0: {
+ /* GPIO0 ~ GPIO54 */
+ reg = <0xd401e0dc 55>;
+ pinctrl-single,gpio = <0 0>;
+ };
+
+
Example:
/* SoC common file */
@@ -76,6 +121,26 @@ control_devconf0: pinmux at 48002274 {
pinctrl-single,function-mask = <0x5F>;
};
+/* third controller instance for pins in gpio domain */
+pmx_gpio: pinmux at d401e000 {
+ compatible = "pinctrl-single";
+ reg = <0xd401e000 0x0330>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+
+ range0: range at d401e0dc {
+ /* GPIO0 ~ GPIO54 */
+ reg = <0xd401e0dc 0xdc>;
+ /* gpio base & gpio func */
+ pinctrl-single,gpio = <0 0>;
+ };
+};
+
+
/* board specific .dts file */
&pmx_core {
--
1.7.10.4
^ permalink raw reply related
* [PATCH v4 6/9] tty: pxa: configure pin
From: Haojian Zhuang @ 2012-11-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-1-git-send-email-haojian.zhuang@gmail.com>
Configure pins by pinctrl driver.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/tty/serial/pxa.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
index 9033fc6..02dc771 100644
--- a/drivers/tty/serial/pxa.c
+++ b/drivers/tty/serial/pxa.c
@@ -37,6 +37,7 @@
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/of.h>
+#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
@@ -809,6 +810,7 @@ static int serial_pxa_probe_dt(struct platform_device *pdev,
struct uart_pxa_port *sport)
{
struct device_node *np = pdev->dev.of_node;
+ struct pinctrl *pinctrl;
int ret;
if (!np)
@@ -819,6 +821,10 @@ static int serial_pxa_probe_dt(struct platform_device *pdev,
dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
return ret;
}
+ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+ if (IS_ERR(pinctrl))
+ return -EPROBE_DEFER;
+
sport->port.line = ret;
return 0;
}
@@ -857,7 +863,7 @@ static int serial_pxa_probe(struct platform_device *dev)
ret = serial_pxa_probe_dt(dev, sport);
if (ret > 0)
sport->port.line = dev->id;
- else if (ret < 0)
+ if (ret < 0)
goto err_clk;
snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
--
1.7.10.4
^ permalink raw reply related
* [PATCH v4 7/9] i2c: pxa: use devm_kzalloc
From: Haojian Zhuang @ 2012-11-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-1-git-send-email-haojian.zhuang@gmail.com>
Use devm_kzalloc & add checking in probe() function.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
---
drivers/i2c/busses/i2c-pxa.c | 26 ++++++++++----------------
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 1034d93..7c8b5d0 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -1078,6 +1078,8 @@ static int i2c_pxa_probe_pdata(struct platform_device *pdev,
struct i2c_pxa_platform_data *plat = pdev->dev.platform_data;
const struct platform_device_id *id = platform_get_device_id(pdev);
+ if (!id)
+ return -EINVAL;
*i2c_types = id->driver_data;
if (plat) {
i2c->use_pio = plat->use_pio;
@@ -1094,29 +1096,23 @@ static int i2c_pxa_probe(struct platform_device *dev)
struct resource *res = NULL;
int ret, irq;
- i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
- if (!i2c) {
- ret = -ENOMEM;
- goto emalloc;
- }
+ i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
+ if (!i2c)
+ return -ENOMEM;
ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
if (ret > 0)
ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
if (ret < 0)
- goto eclk;
+ return ret;
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
irq = platform_get_irq(dev, 0);
- if (res == NULL || irq < 0) {
- ret = -ENODEV;
- goto eclk;
- }
+ if (res == NULL || irq < 0)
+ return -ENODEV;
- if (!request_mem_region(res->start, resource_size(res), res->name)) {
- ret = -ENOMEM;
- goto eclk;
- }
+ if (!request_mem_region(res->start, resource_size(res), res->name))
+ return -ENOMEM;
i2c->adap.owner = THIS_MODULE;
i2c->adap.retries = 5;
@@ -1209,8 +1205,6 @@ ereqirq:
eremap:
clk_put(i2c->clk);
eclk:
- kfree(i2c);
-emalloc:
release_mem_region(res->start, resource_size(res));
return ret;
}
--
1.7.10.4
^ permalink raw reply related
* [PATCH v4 8/9] i2c: pxa: configure pinmux
From: Haojian Zhuang @ 2012-11-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-1-git-send-email-haojian.zhuang@gmail.com>
Configure pins by pinctrl driver.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/i2c/busses/i2c-pxa.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 7c8b5d0..11e4a30 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -32,6 +32,7 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_i2c.h>
+#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
@@ -1051,6 +1052,7 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
enum pxa_i2c_types *i2c_types)
{
struct device_node *np = pdev->dev.of_node;
+ struct pinctrl *pinctrl;
const struct of_device_id *of_id =
of_match_device(i2c_pxa_dt_ids, &pdev->dev);
int ret;
@@ -1063,6 +1065,9 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
return ret;
}
pdev->id = ret;
+ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+ if (IS_ERR(pinctrl))
+ return -EPROBE_DEFER;
if (of_get_property(np, "mrvl,i2c-polling", NULL))
i2c->use_pio = 1;
if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
--
1.7.10.4
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox