* [GIT PULL] Ux500 pin changes
From: Linus Walleij @ 2012-11-08 8:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi ARM SoC guys,
here is a set of pinctrl table patches all just hitting one and the same ux500
file. Description in the signed tag, intended for v3.8.
Please pull them in!
Yours,
Linus Walleij
The following changes since commit ddffeb8c4d0331609ef2581d84de4d763607bd37:
Linux 3.7-rc1 (2012-10-14 14:41:04 -0700)
are available in the git repository at:
http://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
tags/ux500-pins-for-arm-soc
for you to fetch changes up to d792aebfa2daeb58ac6a669ce328ad05e9e4112c:
ARM: ux500: fixup magnetometer pins (2012-11-06 11:10:55 +0100)
----------------------------------------------------------------
Ux500 pinctrl table update for v3.8, basically accumulated
updates to pin muxing and biasing from internal deployment
and regression testing for power performance.
----------------------------------------------------------------
Jean-Nicolas Graux (1):
ARM: ux500: add STM pin configuration
Jorgen Jonsson (1):
ARM: ux500: fixup magnetometer pins
Linus Walleij (1):
ARM: ux500: delete duplicate macro
Patrice Chotard (6):
ARM: ux500: 8500: register LCD VSI pinctrl table
ARM: ux500: 8500: add IDLE pin configuration for SPI
ARM: ux500: 8500: update SKE keypad pinctrl table
ARM: ux500: 8500: define SDI sleep states
ARM: ux500: cosmetic fixups for uart0
ARM: ux500: 8500: add pinctrl support for uart1 and uart2
arch/arm/mach-ux500/board-mop500-pins.c | 427 +++++++++++++++++++++++++++-----
1 file changed, 362 insertions(+), 65 deletions(-)
^ permalink raw reply
* [PATCH v2] ARM: EXYNOS5250: Add support for USB 3.0 dwc3 controller
From: Vivek Gautam @ 2012-11-08 8:32 UTC (permalink / raw)
To: linux-arm-kernel
Changes from v1:
- Changed the device node name from 'dwc3' to 'usb at 12000000'.
- Added the documentation for device tree bindings for dwc3 controller.
Based on changes for USB 2.0:
'https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-November/022046.html'
Tested with required driver DT patches for dwc3-exynos:
http://www.spinics.net/lists/linux-usb/msg73857.html
and USB 3.0 phy support patches:
https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-November/021926.html
Vivek Gautam (1):
ARM: Exynos5250: Enabling dwc3-exynos driver
.../devicetree/bindings/usb/exynos-usb.txt | 14 +++++++++++
arch/arm/boot/dts/exynos5250.dtsi | 6 +++++
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/clock-exynos5.c | 24 ++++++++++++++++++++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 2 +
6 files changed, 48 insertions(+), 0 deletions(-)
--
1.7.6.5
^ permalink raw reply
* [PATCH v2] ARM: Exynos5250: Enabling dwc3-exynos driver
From: Vivek Gautam @ 2012-11-08 8:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352363533-14970-1-git-send-email-gautam.vivek@samsung.com>
Adding DWC3 device tree node for Exynos5250 along with the
device address and clock support needed for the controller.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
.../devicetree/bindings/usb/exynos-usb.txt | 14 +++++++++++
arch/arm/boot/dts/exynos5250.dtsi | 6 +++++
arch/arm/mach-exynos/Kconfig | 1 +
arch/arm/mach-exynos/clock-exynos5.c | 24 ++++++++++++++++++++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 2 +
6 files changed, 48 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index 5ff3def1..a7e3eaa 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -38,3 +38,17 @@ Example:
reg = <0x12120000 0x100>;
interrupts = <0 71 0>;
};
+
+DWC3
+Required properties:
+ - compatible: should be "samsung,exynos-dwc3" for USB 3.0 DWC3 controller.
+ - reg: physical base address of the controller and length of memory mapped
+ region.
+ - interrupts: interrupt number to the cpu.
+
+Example:
+ usb at 12000000 {
+ compatible = "samsung,exynos-dwc3";
+ reg = <0x12000000 0x10000>;
+ interrupts = <0 72 0>;
+ };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index f18abe0..d349636 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -68,6 +68,12 @@
interrupts = <0 96 0>;
};
+ usb at 12000000 {
+ compatible = "samsung,exynos-dwc3";
+ reg = <0x12000000 0x10000>;
+ interrupts = <0 72 0>;
+ };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index bb3b09a..588814a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -422,6 +422,7 @@ config MACH_EXYNOS5_DT
select ARM_AMBA
select SOC_EXYNOS5250
select USE_OF
+ select USB_ARCH_HAS_XHCI
help
Machine support for Samsung EXYNOS5 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS5 SoC based board.
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index a88e0d9..ee094ee 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -740,6 +740,11 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_fsys_ctrl ,
.ctrlbit = (1 << 18),
}, {
+ .name = "usbdrd30",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 19),
+ }, {
.name = "usbotg",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
@@ -1004,6 +1009,16 @@ struct clksrc_sources exynos5_clkset_group = {
.nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
};
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+ [0] = &exynos5_clk_mout_mpll.clk,
+ [1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+ .sources = exynos5_clkset_usbdrd30_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
/* Possible clock sources for aclk_266_gscl_sub Mux */
static struct clk *clk_src_gscl_266_list[] = {
[0] = &clk_ext_xtal_mux,
@@ -1288,6 +1303,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
.parent = &exynos5_clk_mout_cpll.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+ }, {
+ .clk = {
+ .name = "sclk_usbdrd30",
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 28),
+ },
+ .sources = &exynos5_clkset_usbdrd30,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 },
},
};
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 471ffaf..064ca1c 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -197,6 +197,7 @@
#define EXYNOS4_PA_EHCI 0x12580000
#define EXYNOS4_PA_OHCI 0x12590000
#define EXYNOS4_PA_HSPHY 0x125B0000
+#define EXYNOS5_PA_DRD 0x12000000
#define EXYNOS5_PA_EHCI 0x12110000
#define EXYNOS5_PA_OHCI 0x12120000
#define EXYNOS4_PA_MFC 0x13400000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index c03f3dd..3032222 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -90,6 +90,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
"s5p-ehci", NULL),
OF_DEV_AUXDATA("samsung,exynos-ohci", EXYNOS5_PA_OHCI,
"exynos-ohci", NULL),
+ OF_DEV_AUXDATA("samsung,exynos-dwc3", EXYNOS5_PA_DRD,
+ "exynos-dwc3", NULL),
{},
};
--
1.7.6.5
^ permalink raw reply related
* [PATCH 2/4] ARM: EXYNOS: PL330 MDMA1 fix for revision 0 of Exynos4210 SOC
From: Bartlomiej Zolnierkiewicz @ 2012-11-08 9:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0cea01cdbd6c$7ace7200$706b5600$%kim@samsung.com>
On Thursday 08 November 2012 05:49:47 Kukjin Kim wrote:
> Bartlomiej Zolnierkiewicz wrote:
> >
> > > Hmm...above change and adding definition of EXYNOS_PA_S_MDMA1 address
> > > can fix the problem you commented on EXYNOS4210 Rev0 without others?...
> >
> > The problem is affecting only EXYNOS4210 Rev0 and the fix is applied only
> > for case when soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0,
> > or did you mean something else?
> >
> Yeah, I know. I mean just adding secure mdma1 address is enough for
> exynos4210 rev0.
>
> 8<-----
> @@ -275,6 +275,9 @@ static int __init exynos_dma_init(void)
> exynos_pdma1_pdata.nr_valid_peri =
> ARRAY_SIZE(exynos4210_pdma1_peri);
> exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
> +
> + if (samsung_rev() == EXYNOS4210_REV_0)
> + exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1;
> } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
> exynos_pdma0_pdata.nr_valid_peri =
> ARRAY_SIZE(exynos4212_pdma0_peri);
> diff --git a/arch/arm/mach-exynos/include/mach/map.h
> b/arch/arm/mach-exynos/include/mach/map.h
> index 8480849..0abfe78 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -90,6 +90,7 @@
>
> #define EXYNOS4_PA_MDMA0 0x10810000
> #define EXYNOS4_PA_MDMA1 0x12850000
> +#define EXYNOS4_PA_S_MDMA1 0x12840000
> #define EXYNOS4_PA_PDMA0 0x12680000
> #define EXYNOS4_PA_PDMA1 0x12690000
> #define EXYNOS5_PA_MDMA0 0x10800000
> 8<----
Ah, okay. Here is full simplified patch.
From: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Subject: [PATCH v2] ARM: EXYNOS: PL330 MDMA1 fix for revision 0 of Exynos4210 SOC
Commit 8214513 ("ARM: EXYNOS: fix address for EXYNOS4 MDMA1")
changed EXYNOS specific setup of PL330 DMA engine to use 'non-secure'
mdma1 address instead of 'secure' one (from 0x12840000 to 0x12850000)
to fix issue with some Exynos4212 SOCs. Unfortunately it brakes
PL330 setup for revision 0 of Exynos4210 SOC (mdma1 device cannot
be found at 'non-secure' address):
[ 0.566245] dma-pl330 dma-pl330.2: PERIPH_ID 0x0, PCELL_ID 0x0 !
[ 0.566278] dma-pl330: probe of dma-pl330.2 failed with error -22
Fix it by using 'secure' mdma1 address on Exynos4210 revision 0 SOC.
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
arch/arm/mach-exynos/dma.c | 3 +++
arch/arm/mach-exynos/include/mach/map.h | 1 +
2 files changed, 4 insertions(+)
Index: b/arch/arm/mach-exynos/dma.c
===================================================================
--- a/arch/arm/mach-exynos/dma.c 2012-11-07 18:20:36.561743865 +0100
+++ b/arch/arm/mach-exynos/dma.c 2012-11-08 10:48:23.445067606 +0100
@@ -275,6 +275,9 @@ static int __init exynos_dma_init(void)
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4210_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
+
+ if (samsung_rev() == EXYNOS4210_REV_0)
+ exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1;
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4212_pdma0_peri);
Index: b/arch/arm/mach-exynos/include/mach/map.h
===================================================================
--- a/arch/arm/mach-exynos/include/mach/map.h 2012-11-07 18:20:44.801743862 +0100
+++ b/arch/arm/mach-exynos/include/mach/map.h 2012-11-08 10:48:40.597067605 +0100
@@ -92,6 +92,7 @@
#define EXYNOS4_PA_MDMA0 0x10810000
#define EXYNOS4_PA_MDMA1 0x12850000
+#define EXYNOS4_PA_S_MDMA1 0x12840000
#define EXYNOS4_PA_PDMA0 0x12680000
#define EXYNOS4_PA_PDMA1 0x12690000
#define EXYNOS5_PA_MDMA0 0x10800000
^ permalink raw reply
* [PATCH] lpc32xx: Add the motor PWM clock
From: Roland Stigge @ 2012-11-08 10:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAAAP30FjE0QQSJaRN26M-1JdDCXCByK3UNkenBhoN3=dX1-Bbg@mail.gmail.com>
On 07/11/12 16:55, Alexandre Pereira da Silva wrote:
> On Wed, Nov 7, 2012 at 1:47 PM, Alban Bedel
> <alban.bedel@avionic-design.de> wrote:
>> Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
>
> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Acked-by: Roland Stigge <stigge@antcom.de>
I'm adding this to the lpc32xx tree.
Thanks,
Roland
>
>> ---
>> arch/arm/mach-lpc32xx/clock.c | 8 ++++++++
>> arch/arm/mach-lpc32xx/include/mach/platform.h | 1 +
>> 2 files changed, 9 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
>> index f48c2e9..dd5d6f5 100644
>> --- a/arch/arm/mach-lpc32xx/clock.c
>> +++ b/arch/arm/mach-lpc32xx/clock.c
>> @@ -585,6 +585,13 @@ static struct clk clk_timer3 = {
>> .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
>> .get_rate = local_return_parent_rate,
>> };
>> +static struct clk clk_mpwm = {
>> + .parent = &clk_pclk,
>> + .enable = local_onoff_enable,
>> + .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
>> + .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN,
>> + .get_rate = local_return_parent_rate,
>> +};
>> static struct clk clk_wdt = {
>> .parent = &clk_pclk,
>> .enable = local_onoff_enable,
>> @@ -1202,6 +1209,7 @@ static struct clk_lookup lookups[] = {
>> CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
>> CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
>> CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
>> + CLKDEV_INIT("400e8000.mpwm", NULL, &clk_mpwm),
>> CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
>> CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
>> CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
>> diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
>> index acc4aab..b5612a1 100644
>> --- a/arch/arm/mach-lpc32xx/include/mach/platform.h
>> +++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
>> @@ -515,6 +515,7 @@
>> /*
>> * clkpwr_timers_pwms_clk_ctrl_1 register definitions
>> */
>> +#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 0x40
>> #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20
>> #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10
>> #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08
>> --
>> 1.7.0.4
>>
^ permalink raw reply
* [PATCH] ARM: plat-versatile: move secondary CPU startup code out of .init for hotplug
From: Claudio Fontana @ 2012-11-08 10:39 UTC (permalink / raw)
To: linux-arm-kernel
Using __CPUINIT instead of __INIT puts the secondary CPU startup code
into the "right" section: it will not be freed in hotplug configurations,
allowing hot-add of cpus, while still getting freed in non-hotplug configs.
Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
---
arch/arm/plat-versatile/headsmp.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
index dd703ef..19fe180 100644
--- a/arch/arm/plat-versatile/headsmp.S
+++ b/arch/arm/plat-versatile/headsmp.S
@@ -11,7 +11,7 @@
#include <linux/linkage.h>
#include <linux/init.h>
- __INIT
+ __CPUINIT
/*
* Realview/Versatile Express specific entry point for secondary CPUs.
--
1.7.12.1
^ permalink raw reply related
* [PATCH v2] ARM: EXYNOS: origen: Add missing USB regulators
From: Tomasz Figa @ 2012-11-08 10:50 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds missing USB OTG regulators needed for s3c-hsotg driver
to work on Origen board.
Confirmed with schematics of and tested on Origen board.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/mach-exynos/mach-origen.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index d8dc6d7..bf34704 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -100,6 +100,7 @@ static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
+ REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* OTG */
};
static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
@@ -110,6 +111,7 @@ static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */
+ REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* OTG */
};
static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
--
1.8.0
^ permalink raw reply related
* [PATCH 1/2] ARM: ux500: add PRCM register base for pinctrl
From: Linus Walleij @ 2012-11-08 11:55 UTC (permalink / raw)
To: linux-arm-kernel
From: Jonas Aaberg <jonas.aberg@stericsson.com>
This adds the PRCM register range base as a resource to
the pinctrl driver do we can break the dependency to the
PRCMU driver and handle these registers in the driver
alone.
Cc: arm at kernel.org
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ARM SoC guys: this patch is better contained in the
pinctrl tree, can I have your ACK to push it through
pinctrl? Thanks.
---
arch/arm/mach-ux500/cpu-db8500.c | 2 +-
arch/arm/mach-ux500/devices-common.h | 8 +++++++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 87a8f9f..113d9c4 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -158,7 +158,7 @@ static void __init db8500_add_gpios(struct device *parent)
dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
IRQ_DB8500_GPIO0, &pdata);
- dbx500_add_pinctrl(parent, "pinctrl-db8500");
+ dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
}
static int usb_db8500_rx_dma_cfg[] = {
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index 7fbf0ba..96fa4ac 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -129,12 +129,18 @@ void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
int irq, struct nmk_gpio_platform_data *pdata);
static inline void
-dbx500_add_pinctrl(struct device *parent, const char *name)
+dbx500_add_pinctrl(struct device *parent, const char *name,
+ resource_size_t base)
{
+ struct resource res[] = {
+ DEFINE_RES_MEM(base, SZ_8K),
+ };
struct platform_device_info pdevinfo = {
.parent = parent,
.name = name,
.id = -1,
+ .res = res,
+ .num_res = ARRAY_SIZE(res),
};
platform_device_register_full(&pdevinfo);
--
1.7.11.3
^ permalink raw reply related
* [PATCH 2/2] pinctrl/nomadik: make independent of prcmu driver
From: Linus Walleij @ 2012-11-08 11:55 UTC (permalink / raw)
To: linux-arm-kernel
From: Jonas Aaberg <jonas.aberg@stericsson.com>
Currently there are some unnecessary criss-cross
dependencies between the PRCMU driver in MFD and a lot of
other drivers, mainly because other drivers need to poke
around in the PRCM register range.
In cases like this there are actually just a few select
registers that the pinctrl driver need to read/modify/write,
and it turns out that no other driver is actually using
these registers, so there are no concurrency issues
whatsoever.
So: don't let the location of the register range complicate
things, just poke into these registers directly and skip
a layer of indirection.
Cc: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/pinctrl-nomadik-db8500.c | 4 +--
drivers/pinctrl/pinctrl-nomadik-db8540.c | 4 +--
drivers/pinctrl/pinctrl-nomadik-stn8815.c | 4 +--
drivers/pinctrl/pinctrl-nomadik.c | 52 ++++++++++++++++++-------------
drivers/pinctrl/pinctrl-nomadik.h | 14 +++++----
5 files changed, 45 insertions(+), 33 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c
index 6de52e7..e73d75e 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8500.c
+++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c
@@ -1230,7 +1230,7 @@ static const u16 db8500_prcm_gpiocr_regs[] = {
[PRCM_IDX_GPIOCR2] = 0x574,
};
-static const struct nmk_pinctrl_soc_data nmk_db8500_soc = {
+static struct nmk_pinctrl_soc_data nmk_db8500_soc = {
.gpio_ranges = nmk_db8500_ranges,
.gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges),
.pins = nmk_db8500_pins,
@@ -1245,7 +1245,7 @@ static const struct nmk_pinctrl_soc_data nmk_db8500_soc = {
};
void __devinit
-nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
+nmk_pinctrl_db8500_init(struct nmk_pinctrl_soc_data **soc)
{
*soc = &nmk_db8500_soc;
}
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8540.c b/drivers/pinctrl/pinctrl-nomadik-db8540.c
index 52fc301..1276ba3 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8540.c
+++ b/drivers/pinctrl/pinctrl-nomadik-db8540.c
@@ -1240,7 +1240,7 @@ static const u16 db8540_prcm_gpiocr_regs[] = {
[PRCM_IDX_GPIOCR3] = 0x2bc,
};
-static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
+static struct nmk_pinctrl_soc_data nmk_db8540_soc = {
.gpio_ranges = nmk_db8540_ranges,
.gpio_num_ranges = ARRAY_SIZE(nmk_db8540_ranges),
.pins = nmk_db8540_pins,
@@ -1255,7 +1255,7 @@ static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
};
void __devinit
-nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
+nmk_pinctrl_db8540_init(struct nmk_pinctrl_soc_data **soc)
{
*soc = &nmk_db8540_soc;
}
diff --git a/drivers/pinctrl/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/pinctrl-nomadik-stn8815.c
index 7d432c3..ed5b144 100644
--- a/drivers/pinctrl/pinctrl-nomadik-stn8815.c
+++ b/drivers/pinctrl/pinctrl-nomadik-stn8815.c
@@ -339,7 +339,7 @@ static const struct nmk_function nmk_stn8815_functions[] = {
FUNCTION(i2cusb),
};
-static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {
+static struct nmk_pinctrl_soc_data nmk_stn8815_soc = {
.gpio_ranges = nmk_stn8815_ranges,
.gpio_num_ranges = ARRAY_SIZE(nmk_stn8815_ranges),
.pins = nmk_stn8815_pins,
@@ -351,7 +351,7 @@ static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {
};
void __devinit
-nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
+nmk_pinctrl_stn8815_init(struct nmk_pinctrl_soc_data **soc)
{
*soc = &nmk_stn8815_soc;
}
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 22f6937..33c614e 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -30,20 +30,6 @@
#include <linux/pinctrl/pinconf.h>
/* Since we request GPIOs from ourself */
#include <linux/pinctrl/consumer.h>
-/*
- * For the U8500 archs, use the PRCMU register interface, for the older
- * Nomadik, provide some stubs. The functions using these will only be
- * called on the U8500 series.
- */
-#ifdef CONFIG_ARCH_U8500
-#include <linux/mfd/dbx500-prcmu.h>
-#else
-static inline u32 prcmu_read(unsigned int reg) {
- return 0;
-}
-static inline void prcmu_write(unsigned int reg, u32 value) {}
-static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
-#endif
#include <linux/platform_data/pinctrl-nomadik.h>
#include <asm/mach/irq.h>
@@ -85,7 +71,7 @@ struct nmk_gpio_chip {
struct nmk_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
- const struct nmk_pinctrl_soc_data *soc;
+ struct nmk_pinctrl_soc_data *soc;
};
static struct nmk_gpio_chip *
@@ -247,6 +233,15 @@ nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
}
+static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
+{
+ u32 val;
+
+ val = readl(reg);
+ val = ((val & ~mask) | (value & mask));
+ writel(val, reg);
+}
+
static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
unsigned offset, unsigned alt_num)
{
@@ -285,8 +280,8 @@ static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
if (pin_desc->altcx[i].used == true) {
reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
bit = pin_desc->altcx[i].control_bit;
- if (prcmu_read(reg) & BIT(bit)) {
- prcmu_write_masked(reg, BIT(bit), 0);
+ if (readl(npct->soc->prcmu_base + reg) & BIT(bit)) {
+ nmk_write_masked(npct->soc->prcmu_base + reg, BIT(bit), 0);
dev_dbg(npct->dev,
"PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
offset, i+1);
@@ -314,8 +309,8 @@ static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
if (pin_desc->altcx[i].used == true) {
reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
bit = pin_desc->altcx[i].control_bit;
- if (prcmu_read(reg) & BIT(bit)) {
- prcmu_write_masked(reg, BIT(bit), 0);
+ if (readl(npct->soc->prcmu_base + reg) & BIT(bit)) {
+ nmk_write_masked(npct->soc->prcmu_base + reg, BIT(bit), 0);
dev_dbg(npct->dev,
"PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
offset, i+1);
@@ -327,7 +322,7 @@ static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
bit = pin_desc->altcx[alt_index].control_bit;
dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
offset, alt_index+1);
- prcmu_write_masked(reg, BIT(bit), BIT(bit));
+ nmk_write_masked(npct->soc->prcmu_base + reg, BIT(bit), BIT(bit));
}
static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
@@ -693,7 +688,7 @@ static int nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
if (pin_desc->altcx[i].used == true) {
reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
bit = pin_desc->altcx[i].control_bit;
- if (prcmu_read(reg) & BIT(bit))
+ if (readl(npct->soc->prcmu_base + reg) & BIT(bit))
return NMK_GPIO_ALT_C+i+1;
}
}
@@ -1851,6 +1846,7 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
const struct platform_device_id *platid = platform_get_device_id(pdev);
struct device_node *np = pdev->dev.of_node;
struct nmk_pinctrl *npct;
+ struct resource *res;
unsigned int version = 0;
int i;
@@ -1872,6 +1868,20 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
if (version == PINCTRL_NMK_DB8540)
nmk_pinctrl_db8540_init(&npct->soc);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res) {
+ npct->soc->prcmu_base = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
+ if (!npct->soc->prcmu_base) {
+ dev_err(&pdev->dev,
+ "failed to ioremap prcmu registers\n");
+ return -ENOMEM;
+ }
+ } else {
+ dev_info(&pdev->dev,
+ "No PRCMU base, assume no ALT-Cx control is available\n");
+ }
+
/*
* We need all the GPIO drivers to probe FIRST, or we will not be able
* to obtain references to the struct gpio_chip * for them, and we
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
index bcd4191..9dd727a 100644
--- a/drivers/pinctrl/pinctrl-nomadik.h
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -125,6 +125,7 @@ struct nmk_pingroup {
* @altcx_pins: The pins that support Other alternate-C function on this SoC
* @npins_altcx: The number of Other alternate-C pins
* @prcm_gpiocr_registers: The array of PRCM GPIOCR registers on this SoC
+ * @prcmu_base: PRCMU virtual base
*/
struct nmk_pinctrl_soc_data {
struct pinctrl_gpio_range *gpio_ranges;
@@ -138,16 +139,17 @@ struct nmk_pinctrl_soc_data {
const struct prcm_gpiocr_altcx_pin_desc *altcx_pins;
unsigned npins_altcx;
const u16 *prcm_gpiocr_registers;
+ void __iomem *prcmu_base;
};
#ifdef CONFIG_PINCTRL_STN8815
-void nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc);
+void nmk_pinctrl_stn8815_init(struct nmk_pinctrl_soc_data **soc);
#else
static inline void
-nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
+nmk_pinctrl_stn8815_init(struct nmk_pinctrl_soc_data **soc)
{
}
@@ -155,12 +157,12 @@ nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
#ifdef CONFIG_PINCTRL_DB8500
-void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
+void nmk_pinctrl_db8500_init(struct nmk_pinctrl_soc_data **soc);
#else
static inline void
-nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
+nmk_pinctrl_db8500_init(struct nmk_pinctrl_soc_data **soc)
{
}
@@ -168,12 +170,12 @@ nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
#ifdef CONFIG_PINCTRL_DB8540
-void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc);
+void nmk_pinctrl_db8540_init(struct nmk_pinctrl_soc_data **soc);
#else
static inline void
-nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
+nmk_pinctrl_db8540_init(struct nmk_pinctrl_soc_data **soc)
{
}
--
1.7.11.3
^ permalink raw reply related
* [PATCH 1/2] ARM: ux500: add PRCM register base for pinctrl
From: Arnd Bergmann @ 2012-11-08 12:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352375731-29570-1-git-send-email-linus.walleij@stericsson.com>
On Thursday 08 November 2012, Linus Walleij wrote:
> From: Jonas Aaberg <jonas.aberg@stericsson.com>
>
> This adds the PRCM register range base as a resource to
> the pinctrl driver do we can break the dependency to the
> PRCMU driver and handle these registers in the driver
> alone.
>
> Cc: arm at kernel.org
> Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
^ permalink raw reply
* [PATCH 1/5] gpiolib: fix up function prototypes etc
From: Linus Walleij @ 2012-11-08 12:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKohpon2OBMgNjc5RRGibEUqN_yPGPdXX5RBFP-bQLmyeF4zuw@mail.gmail.com>
On Wed, Nov 7, 2012 at 6:09 AM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> On 6 November 2012 20:46, Linus Walleij <linus.walleij@stericsson.com>
>> -void gpiochip_add_pin_range(struct gpio_chip *chip, const char
>> *pinctl_name,
>> - unsigned int pin_base, unsigned int npins);
>> -void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
>> -#endif
>> +#ifdef CONFIG_PINCTRL
>
> Shouldn't this be ifndef??
Probably, fixed up in later patches...
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 3/5] gpiolib: remove duplicate pin range code
From: Linus Walleij @ 2012-11-08 12:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOh2x=nT8_95uu9tfEnOHy9Gkm6gEEAVAKKwPAqbLJz3bwFDNw@mail.gmail.com>
On Wed, Nov 7, 2012 at 6:14 AM, viresh kumar <viresh.kumar@linaro.org> wrote:
> On Tue, Nov 6, 2012 at 8:46 PM, Linus Walleij
> <linus.walleij@stericsson.com> wrote:
>> From: Linus Walleij <linus.walleij@linaro.org>
>>
>> Commit 69e1601bca88809dc118abd1becb02c15a02ec71
>> "gpiolib: provide provision to register pin ranges"
>>
>> Introduced both of_gpiochip_remove_pin_range() and
>> gpiochip_remove_pin_ranges(). But the contents are exactly
>> the same so remove the OF one and rely on the range deletion
>> in the core.
>>
>> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
>
> I can't believe that i did this :(
Don't worry, it's impossible to get these things right. I am
trying to fix it properly here and just introduce new bugs
for every fix I try to make.
Maybe I'll soon have something that actually doesn't
break x86...
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] gpiolib: iron out include ladder mistakes
From: Linus Walleij @ 2012-11-08 12:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509983D0.1060107@wwwdotorg.org>
On Tue, Nov 6, 2012 at 10:40 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/06/2012 09:21 AM, Linus Walleij wrote:
>> And we need to keep the static inlines in <linux/gpio.h>
>> but here for the !CONFIG_GENERIC_GPIO case, and then we
>> may as well throw in a few warnings like the other
>> prototypes there, if someone would have the bad taste
>> of compiling without GENERIC_GPIO even.
>
> Hmm. Is there way to avoid the duplication of the dummy implementations?
> Having a prototype and a truly dummy implementation in one place, but a
> WARNing/failing dummy implementation elsewhere, seems like it'll cause
> issues.
Yeah :-/
This is not exactly elegant and is some side effect of the split
between CONFIG_GENERIC_GPIO and CONFIG_GPIOLIB,
the real fix is to get rid of all GENERIC_GPIO implementations
in the kernel and switch everyone over to GPIOLIB.
Not that easy though :-( can't think of any nice fix.
> Does this patch mean the previous series causes "git bisect" failures?
Yeah once I have something that doesn't break x86 I might
just squash collapse all of this into the gpioranges patch.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 4/4] arm/dts: am33xx: Add CPSW and MDIO module nodes for AM33XX
From: Mugunthan V N @ 2012-11-08 12:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50914107.2090909@ti.com>
On 10/31/2012 8:47 PM, Benoit Cousson wrote:
> diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
> index c634f87..e233cfa 100644
> --- a/arch/arm/boot/dts/am335x-bone.dts
> +++ b/arch/arm/boot/dts/am335x-bone.dts
> @@ -78,3 +78,11 @@
> };
> };
> };
> +
> +&cpsw_emac0 {
> + phy_id = "4a101000.mdio:00";
> Why are you using that kind of interface? You seem to want a reference
> to a device.
>
> Cannot you have something less hard coded like:
> phy_id = <&davinci_mdio>, <0>;
Benoit
I am having a issue in converting the above phy_id conversion from
"<&davinci_mdio>, <0>" to
"4a101000.mdio:00". Since davinci_mdio is a child node to cpsw, the
platform device for mdio is
not created to get the mdio device name "4a101000.mdio".
Can you point me a reference to get the right implementation.
Regards
Mugunthan V N
^ permalink raw reply
* [PATCH 15/15] ARM: OMAP2+: AM33XX: Basic suspend resume support
From: Bedia, Vaibhav @ 2012-11-08 13:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87pq3p72s7.fsf@deeprootsystems.com>
On Wed, Nov 07, 2012 at 22:45:20, Kevin Hilman wrote:
[...]
> >>
> >
> > We could perhaps add a couple of APIs to check the SYSC values when coming
> > out of suspend and take appropriate action if the sysc cache does not match?
>
> Yes, for IPs with only SW support and no drivers, we may need something
> like this. But again, it needs to be suspend and idle aware, not just
> suspend.
>
Ok, if the pwrmdm pre and post transition callbacks do this that should take
care of both suspend and idle.
Regards,
Vaibhav
^ permalink raw reply
* [PATCH 11/15] ARM: OMAP: timer: Interchange clksrc and clkevt for AM33XX
From: Bedia, Vaibhav @ 2012-11-08 13:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509836BA.5030507@ti.com>
Hi Santosh,
On Tue, Nov 06, 2012 at 20:05:40, Bedia, Vaibhav wrote:
> Hi Santosh,
>
> On Tue, Nov 06, 2012 at 03:29:22, Shilimkar, Santosh wrote:
>
> [...]
>
> > >
> > > IMO, assuming that idle will not be useful from the begining is leading
> > > down the path to poor design choices that will be much more difficult to
> > > fixup down the road in order to add idle support later. We need to
> > > design both idle and suspend at the same time.
> > >
> > I agree with Kevin. Not supporting CPUIDLE deep states can hit the
> > active power numbers dearly. I just don't know why the SOCs don't share
> > the standard and must have design choices. But thats another discussion.
> >
>
> Yes, active power numbers are not comparable to OMAP :(
>
> > How about leaving the timer choices as is. PER timer for clock source
> > and wakeuptimer for clock event. Anyway in suspend the clock-source
> > can be suspended and that is evident from recent discussion. The only
> > downside is you won't count time in suspend which is any way the case.
> >
> > Vaibhav,
> > Do you guys see any implementation bottleneck for above ?
> >
>
> Looking at the timekeeping code I see one more potential reason for making
> this change. OMAP registers the 32k sync timer as the persistent clock and
> since there's no 32k sync timer in AM33xx it doesn't register a persistent
> clock right now. Based on what I understood, we need to have to register
> one and DMTimer1 is the only clock that can serve as the persistent clock
> in suspend state. When we do so we might as well use it as the clocksource.
>
> A related question that I had was, is there a mechanism to handle the 32k
> counter (DMTimer or sync timer) wraparound condition in suspend?
>
Does interchanging the clksrc and clkevt look fine to you?
Regards,
Vaibhav
^ permalink raw reply
* [PATCH] ARM: VIC: remove unused irq_base variable
From: Arnd Bergmann @ 2012-11-08 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350392786-29191-1-git-send-email-linus.walleij@stericsson.com>
"ARM: VIC: use irq_domain_add_simple()" causes a new warning:
arch/arm/common/vic.c: In function 'vic_of_init':
arch/arm/common/vic.c:410:6: warning: unused variable 'irq_base' [-Wunused-variable]
Since the irq_base variable is not used any more, it should be
removed now
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
On Tuesday 16 October 2012, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij@linaro.org>
>
> Instead of allocating descriptors on-the-fly for the device tree
> initialization case, use irq_domain_add_simple() which will take
> care of this if you pass negative as the first_irq.
>
> Alter the signature of __vic_init() to pass the first_irq as
> signed so this works as expected.
>
> Switching the VIC to use irq_domain_add_simple() also has the
> upside of displaying the same WARNING when you boot with
> pre-allocated descriptors on systems using SPARSE_IRQ but
> yet not using device tree.
>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 4fd5d98..e4df17c 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -407,7 +407,6 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
int __init vic_of_init(struct device_node *node, struct device_node *parent)
{
void __iomem *regs;
- int irq_base;
if (WARN(parent, "non-root VICs are not supported"))
return -EINVAL;
^ permalink raw reply related
* [PATCH] ARM: VIC: remove unused irq_base variable
From: Russell King - ARM Linux @ 2012-11-08 13:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201211081340.54440.arnd@arndb.de>
On Thu, Nov 08, 2012 at 01:40:54PM +0000, Arnd Bergmann wrote:
> "ARM: VIC: use irq_domain_add_simple()" causes a new warning:
>
> arch/arm/common/vic.c: In function 'vic_of_init':
> arch/arm/common/vic.c:410:6: warning: unused variable 'irq_base' [-Wunused-variable]
>
> Since the irq_base variable is not used any more, it should be
> removed now
I've just committed exactly the same patch to my tree...
^ permalink raw reply
* [PATCH v2] gpiolib: iron out include ladder mistakes
From: Linus Walleij @ 2012-11-08 13:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
The <*/gpio.h> includes are updated again: now we need to account
for the problem introduced by commit:
595679a8038584df7b9398bf34f61db3c038bfea
"gpiolib: fix up function prototypes etc"
Actually we need static inlines in include/asm-generic/gpio.h
as well since we may have GPIOLIB but not PINCTRL.
Make sure to move all the CONFIG_PINCTRL business
to the end of the file so we are sure we have
declared struct gpio_chip.
And we need to keep the static inlines in <linux/gpio.h>
but here for the !CONFIG_GENERIC_GPIO case, and then we
may as well throw in a few warnings like the other
prototypes there, if someone would have the bad taste
of compiling without GENERIC_GPIO even.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- Move function prototypes below all other #ifdefs at the
bottom of the file so we know we have struct irq_chip
defines
- Provide a proper return value from the
gpiochip_add_pin_range() stub
- Thanks to Stephen Rothwell for pointing this out.
---
include/asm-generic/gpio.h | 56 +++++++++++++++++++++++++++++-----------------
include/linux/gpio.h | 7 +++---
2 files changed, 38 insertions(+), 25 deletions(-)
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 50d995e..2b84fc3 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -48,27 +48,6 @@ struct seq_file;
struct module;
struct device_node;
-#ifdef CONFIG_PINCTRL
-
-/**
- * struct gpio_pin_range - pin range controlled by a gpio chip
- * @head: list for maintaining set of pin ranges, used internally
- * @pctldev: pinctrl device which handles corresponding pins
- * @range: actual range of pins controlled by a gpio controller
- */
-
-struct gpio_pin_range {
- struct list_head node;
- struct pinctrl_dev *pctldev;
- struct pinctrl_gpio_range range;
-};
-
-int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
- unsigned int pin_base, unsigned int npins);
-void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
-
-#endif
-
/**
* struct gpio_chip - abstract a GPIO controller
* @label: for diagnostics
@@ -288,4 +267,39 @@ static inline void gpio_unexport(unsigned gpio)
}
#endif /* CONFIG_GPIO_SYSFS */
+#ifdef CONFIG_PINCTRL
+
+/**
+ * struct gpio_pin_range - pin range controlled by a gpio chip
+ * @head: list for maintaining set of pin ranges, used internally
+ * @pctldev: pinctrl device which handles corresponding pins
+ * @range: actual range of pins controlled by a gpio controller
+ */
+
+struct gpio_pin_range {
+ struct list_head node;
+ struct pinctrl_dev *pctldev;
+ struct pinctrl_gpio_range range;
+};
+
+int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
+ unsigned int pin_base, unsigned int npins);
+void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
+
+#else
+
+static inline int
+gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
+ unsigned int pin_base, unsigned int npins)
+{
+ return 0;
+}
+
+static inline void
+gpiochip_remove_pin_ranges(struct gpio_chip *chip)
+{
+}
+
+#endif /* CONFIG_PINCTRL */
+
#endif /* _ASM_GENERIC_GPIO_H */
diff --git a/include/linux/gpio.h b/include/linux/gpio.h
index 81bbfe5..7ba2762 100644
--- a/include/linux/gpio.h
+++ b/include/linux/gpio.h
@@ -231,21 +231,20 @@ static inline int irq_to_gpio(unsigned irq)
return -EINVAL;
}
-#ifdef CONFIG_PINCTRL
-
static inline int
gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
unsigned int pin_base, unsigned int npins)
{
+ WARN_ON(1);
+ return -EINVAL;
}
static inline void
gpiochip_remove_pin_ranges(struct gpio_chip *chip)
{
+ WARN_ON(1);
}
-#endif /* CONFIG_PINCTRL */
-
#endif /* ! CONFIG_GENERIC_GPIO */
#endif /* __LINUX_GPIO_H */
--
1.7.11.3
^ permalink raw reply related
* [PATCH] ARM: VIC: remove unused irq_base variable
From: Linus Walleij @ 2012-11-08 14:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121108135537.GZ28327@n2100.arm.linux.org.uk>
On Thu, Nov 8, 2012 at 2:55 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Thu, Nov 08, 2012 at 01:40:54PM +0000, Arnd Bergmann wrote:
>> "ARM: VIC: use irq_domain_add_simple()" causes a new warning:
>>
>> arch/arm/common/vic.c: In function 'vic_of_init':
>> arch/arm/common/vic.c:410:6: warning: unused variable 'irq_base' [-Wunused-variable]
>>
>> Since the irq_base variable is not used any more, it should be
>> removed now
>
> I've just committed exactly the same patch to my tree...
Thanks guys...
Acked-by, FWIW
Yours,
Linus Walleij
^ permalink raw reply
* [GIT PULL] vexpress: fixes for v3.8
From: Arnd Bergmann @ 2012-11-08 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350580125.4984.23.camel@hornet>
On Thursday 18 October 2012, Pawel Moll wrote:
> ----------------------------------------------------------------
> Pawel Moll (1):
> ARM: vexpress: Make the debug UART detection more specific
>
Building allyesconfig in linux-next now gives me:
arch/arm/kernel/debug.S: Assembler messages:
arch/arm/kernel/debug.S:81: Error: selected processor does not support ARM mode `movw r2,#0xc 091'
arch/arm/kernel/debug.S:81: Error: selected processor does not support ARM mode `movt r2,#0x4 10f'
arch/arm/kernel/debug.S:97: Error: selected processor does not support ARM mode `movw r2,#0xc 091'
arch/arm/kernel/debug.S:97: Error: selected processor does not support ARM mode `movt r2,#0x4 10f'
arch/arm/kernel/debug.S:104: Error: selected processor does not support ARM mode `movw r3,#0x c091'
arch/arm/kernel/debug.S:104: Error: selected processor does not support ARM mode `movt r3,#0x 410f'
The patch below fixes this. Do you think it's appropriate?
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
diff --git a/arch/arm/include/debug/vexpress.S b/arch/arm/include/debug/vexpress.S
index 0c6abbf..dc8e882 100644
--- a/arch/arm/include/debug/vexpress.S
+++ b/arch/arm/include/debug/vexpress.S
@@ -21,6 +21,7 @@
#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
.macro addruart,rp,rv,tmp
+ .arch armv7-a
@ Make an educated guess regarding the memory map:
@ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
^ permalink raw reply related
* [PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
From: Arnd Bergmann @ 2012-11-08 14:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <508666A6.9040701@free-electrons.com>
The newly introduced l2_wt_override should be in the same #ifdef
as the code using it, otherwise we get:
arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
On Tuesday 23 October 2012, Gregory CLEMENT wrote:
> @@ -33,6 +34,11 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock);
> static u32 l2x0_way_mask; /* Bitmask of active ways */
> static u32 l2x0_size;
> static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
> +static int l2_wt_override;
> +
> +/* Aurora don't have the cache ID register available, so we have to
> + * pass it though the device tree */
> +static u32 cache_id_part_number_from_dt;
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 92ee4a0..6911b8b 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -34,7 +34,6 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock);
static u32 l2x0_way_mask; /* Bitmask of active ways */
static u32 l2x0_size;
static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
-static int l2_wt_override;
/* Aurora don't have the cache ID register available, so we have to
* pass it though the device tree */
@@ -424,6 +423,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
}
#ifdef CONFIG_OF
+static int l2_wt_override;
+
/*
* Note that the end addresses passed to Linux primitives are
* noninclusive, while the hardware cache range operations use
^ permalink raw reply related
* [PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
From: Russell King - ARM Linux @ 2012-11-08 14:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201211081408.41983.arnd@arndb.de>
On Thu, Nov 08, 2012 at 02:08:41PM +0000, Arnd Bergmann wrote:
> The newly introduced l2_wt_override should be in the same #ifdef
> as the code using it, otherwise we get:
>
> arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used
This should already be fixed. I think your patch pre-dates 7547/4.
^ permalink raw reply
* arm: Add ARM ERRATA 775420 workaround
From: jungseung lee @ 2012-11-08 14:29 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
I have question the work-around code.
The below code will be enter after handling exception handling path.
(that is fix-up code)
As far as i know, the dsb instruction should be inserted before the any
isb instruction on exception handling code for breaking erratum condition .
this errata could meet the requirement?
> source "arch/arm/common/Kconfig"
> diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> index 39e3fb3..3b17227 100644
> --- a/arch/arm/mm/cache-v7.S
> +++ b/arch/arm/mm/cache-v7.S
> @@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range)
> * isn't mapped, fail with -EFAULT.
> */
> 9001:
> +#ifdef CONFIG_ARM_ERRATA_775420
> + dsb
> +#endif
> mov r0, #-EFAULT
> mov pc, lr
> UNWIND(.fnend )
> On Thu, Sep 20, 2012 at 10:58:53AM +0100, Catalin Marinas wrote:
> > On 12 September 2012 08:14, Simon Horman wrote:
> > > +config ARM_ERRATA_775420
> > > + bool "ARM errata: A data cache maintenance operation which
> > > aborts, might lead to deadlock"
> > > + depends on CPU_V7
> > > + help
> > > + This option enables the workaround for the 775420 Cortex-A9
> > > (r2p2,
> > > + r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache
> > > maintenance
> > > + operation aborts with MMU exception, it might cause the
> > > processor
> > > + deadlock. This workaround puts DSB before executing ISB at
> > > the
> > > + beginning of the abort exception handler.
> > > +
> > > endmenu
> >
> > The only case where we can get an abort on cache maintenance is
> > v7_coherent_user_range(). I don't think we have any ISB on the
> > exception handling path for this function, so we could just add the
> > DSB there:
>
> I think that an advantage of Abe-san's implementation is that
> it might to be a bit more robust. But your proposal is certainly
> much cleaner and for that reason I agree it is a good option.
>
> I've updated the patch, but since the code is now all yours
> I'm unsure if the author should be changed or not.
>
> ----------------------------------------------------------------
> From: Kouei Abe
>
> arm: Add ARM ERRATA 775420 workaround
>
> Workaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0) erratum.
> In case a date cache maintenance operation aborts with MMU exception, it
> might cause the processor to deadlock. This workaround puts DSB before
> executing ISB if an abort may occur on cache maintenance.
>
> Based on work by Kouei Abe and feedback from Catalin Marinas.
>
> Cc: Catalin Marinas
> Signed-off-by: Kouei Abe
> Signed-off-by: Simon Horman
>
> ---
>
> v2
> * Add some details to changelog entry
> * Alternate implementation suggested by Catalin Marinas
> - Add the dsb directly to v7_coherent_user_range() rather
> than the exception handler
> ---
> arch/arm/Kconfig | 10 ++++++++++
> arch/arm/mm/cache-v7.S | 3 +++
> 2 files changed, 13 insertions(+)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 2f88d8d..48c19d4 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1413,6 +1413,16 @@ config PL310_ERRATA_769419
> on systems with an outer cache, the store buffer is drained
> explicitly.
>
> +config ARM_ERRATA_775420
> + bool "ARM errata: A data cache maintenance operation which aborts,
> might lead to deadlock"
> + depends on CPU_V7
> + help
> + This option enables the workaround for the 775420 Cortex-A9 (r2p2,
> + r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
> + operation aborts with MMU exception, it might cause the processor
> + to deadlock. This workaround puts DSB before executing ISB if
> + an abort may occur on cache maintenance.
> +
> endmenu
>
> source "arch/arm/common/Kconfig"
> diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> index 39e3fb3..3b17227 100644
> --- a/arch/arm/mm/cache-v7.S
> +++ b/arch/arm/mm/cache-v7.S
> @@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range)
> * isn't mapped, fail with -EFAULT.
> */
> 9001:
> +#ifdef CONFIG_ARM_ERRATA_775420
> + dsb
> +#endif
> mov r0, #-EFAULT
> mov pc, lr
> UNWIND(.fnend )
> --
> 1.7.10.4
>
>
^ permalink raw reply
* test
From: jungseung lee @ 2012-11-08 14:35 UTC (permalink / raw)
To: linux-arm-kernel
test
^ permalink raw reply
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