* [PATCH v2 1/5] ARM: kernel: smp_setup_processor_id() updates
From: Lorenzo Pieralisi @ 2012-11-09 15:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109144446.GC17405@mudshark.cambridge.arm.com>
On Fri, Nov 09, 2012 at 02:44:46PM +0000, Will Deacon wrote:
> On Fri, Nov 09, 2012 at 02:34:10PM +0000, Lorenzo Pieralisi wrote:
> > This patch applies some basic changes to the smp_setup_processor_id()
> > ARM implementation to make the code that builds cpu_logical_map more
> > uniform across the kernel.
> >
> > The function now prints the full extent of the boot CPU MPIDR[23:0] and
> > initializes the cpu_logical_map for CPUs up to nr_cpu_ids.
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > ---
> > arch/arm/kernel/setup.c | 7 ++++---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> > index da1d1aa..ede7c84 100644
> > --- a/arch/arm/kernel/setup.c
> > +++ b/arch/arm/kernel/setup.c
> > @@ -426,13 +426,14 @@ int __cpu_logical_map[NR_CPUS];
> > void __init smp_setup_processor_id(void)
> > {
> > int i;
> > - u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
> > + u32 mpidr = read_cpuid_mpidr() & 0xffffff;
>
> We need that is_smp() check, otherwise we'll go and do a funky CP15
> operation on CPU's that might not be too happy about it.
You are right, sorry my apologies.
I will have to check it even when parsing the DT then.
Lorenzo
^ permalink raw reply
* [PATCH 4/6] ASoC: wm8974: add SPI as a possible bus master
From: Mark Brown @ 2012-11-09 14:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109145504.GC8598@pengutronix.de>
On Fri, Nov 09, 2012 at 03:55:04PM +0100, Steffen Trumtrar wrote:
> On Fri, Nov 09, 2012 at 02:38:42PM +0000, Mark Brown wrote:
> > We should be converting things to regmap if we're going to do this -
> > we're trying to phase out the ASoC-specific I/O and this makes the code
> > simpler anyway as the core will just be able to get the regmap from the
> > struct device without bouncing information around through the private
> > data and so on.
> I wasn't aware of that driver. That sounds way better than the private data stuff.
If you look in mainline there's a bunch of conversions been done
recently, it's fairly mechanical so hopefully they'll show you what
needs doing.
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* [PATCH 5/6] ARM i.MX: rename ssi1 clock for imx27
From: Mark Brown @ 2012-11-09 14:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352469625-32024-6-git-send-email-s.trumtrar@pengutronix.de>
On Fri, Nov 09, 2012 at 03:00:24PM +0100, Steffen Trumtrar wrote:
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
You don't say anything about why you're renaming here...
> - clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
> + clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "10010000.ssi");
> clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
I'm guessing this is for DT... why are we only renaming one of the
clocks here and will this not break non-DT users?
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* [PATCH v2 2/5] ARM: kernel: add device tree init map function
From: Lorenzo Pieralisi @ 2012-11-09 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109144259.GB17405@mudshark.cambridge.arm.com>
On Fri, Nov 09, 2012 at 02:42:59PM +0000, Will Deacon wrote:
> On Fri, Nov 09, 2012 at 02:34:11PM +0000, Lorenzo Pieralisi wrote:
> > When booting through a device tree, the kernel cpu logical id map can be
> > initialized using device tree data passed by FW or through an embedded blob.
> >
> > This patch adds a function that parses device tree "cpu" nodes and
> > retrieves the corresponding CPUs hardware identifiers (MPIDR).
> > It sets the possible cpus and the cpu logical map values according to
> > the number of CPUs defined in the device tree and respective properties.
> >
> > The device tree HW identifiers are considered valid if all CPU nodes contain
> > a "reg" property and the DT defines a CPU node that matches the MPIDR[23:0]
> > of the boot CPU.
> >
> > The primary CPU is assigned cpu logical number 0 to keep the current convention
> > valid.
> >
> > Current bindings documentation is included in the patch:
> >
> > Documentation/devicetree/bindings/arm/cpus.txt
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>
> [...]
>
> > +List of possible "compatible" string ids:
> > +
> > +<arm, arm1020>
> > +<arm, arm1020e>
> > +<arm, arm1022>
> > +<arm, arm1026>
> > +<arm, arm720>
> > +<arm, arm740>
> > +<arm, arm7tdmi>
> > +<arm, arm920>
> > +<arm, arm922>
> > +<arm, arm925>
> > +<arm, arm926>
> > +<arm, arm940>
> > +<arm, arm946>
> > +<arm, arm9tdmi>
> > +<arm, fa526>
> > +<arm, feroceon>
> > +<arm, mohawk>
> > +<arm, sa110>
> > +<arm, sa1100>
> > +<arm, xsc3>
> > +<arm, xscale>
> > +<arm, cortex-a5>
> > +<arm, cortex-a7>
> > +<arm, cortex-a8>
> > +<arm, cortex-a9>
> > +<arm, cortex-a15>
> > +<arm, arm1136>
> > +<arm, arm11-mpcore>
>
> Is this supposed to be an exhaustive list? What about 1156 and 1176? Also,
> "arm11mpcore" should probably be used instead of "arm11-mpcore".
I added the list since IMHO defining a compatible property and not
defining a list of possible strings can encourage abuse. Happy to do
whatever DT guys think I should do with it.
I will add the processor version strings you suggested.
Thanks,
Lorenzo
^ permalink raw reply
* [PATCH 3/6] ASoC: wm8974: include MCLKDIV in pll_factors
From: Mark Brown @ 2012-11-09 14:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352469625-32024-4-git-send-email-s.trumtrar@pengutronix.de>
On Fri, Nov 09, 2012 at 03:00:22PM +0100, Steffen Trumtrar wrote:
> To calculate the integer part of the frequency ratio, the whole output
> path has to be considered (post and pre are optional):
> Ndiv = (pre * target * 4 * post) / source
> In the current implementation only the fixed- and pre-divider is
> considered, but the post-divider is omitted.
> To calculate Ndiv, this post divider has to be applied before any
> calculation happens. Otherwise Ndiv is considered to be to low in the
> later stages. This leads to a wrong value in the PLLN register, which
> in turn produces a wrong playback speed of the audio signal.
This changelog doesn't mention where you're using MCLKDIV here but it
does rather sound like the PLL configuration is not being done correctly
here. The expectation is that when the PLL is configured the raw output
frequency from the PLL is specified. The PLL is then specified as the
system clock with that rate and then any division required to make that
usable happens afterwards.
> + case WM8974_MCLKDIV_1:
> + reg = 1;
> + break;
Please do follow the Linux coding style for kernel code.
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* [PATCH 4/6] ASoC: wm8974: add SPI as a possible bus master
From: Steffen Trumtrar @ 2012-11-09 14:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109143841.GG23807@opensource.wolfsonmicro.com>
On Fri, Nov 09, 2012 at 02:38:42PM +0000, Mark Brown wrote:
> On Fri, Nov 09, 2012 at 03:00:23PM +0100, Steffen Trumtrar wrote:
>
> > The wm8974 can be controlled via i2c or spi. The current driver only supports
> > i2c. Add SPI as possible bus.
> >
> > As the driver has to distinguish the bus type, pass this info via the wm8974_priv.
> > This reverts c2562a8e3b5f871ad0b73caf98bb7541e8724efc, because the driver now
> > needs it back.
>
> Don't just quote raw commit IDs, *especially* not full ones, as they're
> completely illegible to humans. Someone reading the changelog needs to
> be able to understand what this commit is and why the driver needs it
> back.
>
Okay.
> > - ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C);
> > + ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8974->control_type);
>
> We should be converting things to regmap if we're going to do this -
> we're trying to phase out the ASoC-specific I/O and this makes the code
> simpler anyway as the core will just be able to get the regmap from the
> struct device without bouncing information around through the private
> data and so on.
I wasn't aware of that driver. That sounds way better than the private data stuff.
Regards,
Steffen
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply
* [PATCH v2 1/5] ARM: kernel: smp_setup_processor_id() updates
From: Lorenzo Pieralisi @ 2012-11-09 14:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109144446.GC17405@mudshark.cambridge.arm.com>
On Fri, Nov 09, 2012 at 02:44:46PM +0000, Will Deacon wrote:
> On Fri, Nov 09, 2012 at 02:34:10PM +0000, Lorenzo Pieralisi wrote:
> > This patch applies some basic changes to the smp_setup_processor_id()
> > ARM implementation to make the code that builds cpu_logical_map more
> > uniform across the kernel.
> >
> > The function now prints the full extent of the boot CPU MPIDR[23:0] and
> > initializes the cpu_logical_map for CPUs up to nr_cpu_ids.
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > ---
> > arch/arm/kernel/setup.c | 7 ++++---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> > index da1d1aa..ede7c84 100644
> > --- a/arch/arm/kernel/setup.c
> > +++ b/arch/arm/kernel/setup.c
> > @@ -426,13 +426,14 @@ int __cpu_logical_map[NR_CPUS];
> > void __init smp_setup_processor_id(void)
> > {
> > int i;
> > - u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
> > + u32 mpidr = read_cpuid_mpidr() & 0xffffff;
>
> We need that is_smp() check, otherwise we'll go and do a funky CP15
> operation on CPU's that might not be too happy about it.
It is there :-) I just added a local variable for mpidr to avoid reading
it again later on when printing. The change moved the is_smp() check
one line down.
Thanks,
Lorenzo
^ permalink raw reply
* [PATCH v2 1/5] ARM: kernel: smp_setup_processor_id() updates
From: Will Deacon @ 2012-11-09 14:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352471654-20207-2-git-send-email-lorenzo.pieralisi@arm.com>
On Fri, Nov 09, 2012 at 02:34:10PM +0000, Lorenzo Pieralisi wrote:
> This patch applies some basic changes to the smp_setup_processor_id()
> ARM implementation to make the code that builds cpu_logical_map more
> uniform across the kernel.
>
> The function now prints the full extent of the boot CPU MPIDR[23:0] and
> initializes the cpu_logical_map for CPUs up to nr_cpu_ids.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---
> arch/arm/kernel/setup.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index da1d1aa..ede7c84 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -426,13 +426,14 @@ int __cpu_logical_map[NR_CPUS];
> void __init smp_setup_processor_id(void)
> {
> int i;
> - u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
> + u32 mpidr = read_cpuid_mpidr() & 0xffffff;
We need that is_smp() check, otherwise we'll go and do a funky CP15
operation on CPU's that might not be too happy about it.
Will
^ permalink raw reply
* [PATCH v2 2/5] ARM: kernel: add device tree init map function
From: Will Deacon @ 2012-11-09 14:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352471654-20207-3-git-send-email-lorenzo.pieralisi@arm.com>
On Fri, Nov 09, 2012 at 02:34:11PM +0000, Lorenzo Pieralisi wrote:
> When booting through a device tree, the kernel cpu logical id map can be
> initialized using device tree data passed by FW or through an embedded blob.
>
> This patch adds a function that parses device tree "cpu" nodes and
> retrieves the corresponding CPUs hardware identifiers (MPIDR).
> It sets the possible cpus and the cpu logical map values according to
> the number of CPUs defined in the device tree and respective properties.
>
> The device tree HW identifiers are considered valid if all CPU nodes contain
> a "reg" property and the DT defines a CPU node that matches the MPIDR[23:0]
> of the boot CPU.
>
> The primary CPU is assigned cpu logical number 0 to keep the current convention
> valid.
>
> Current bindings documentation is included in the patch:
>
> Documentation/devicetree/bindings/arm/cpus.txt
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[...]
> +List of possible "compatible" string ids:
> +
> +<arm, arm1020>
> +<arm, arm1020e>
> +<arm, arm1022>
> +<arm, arm1026>
> +<arm, arm720>
> +<arm, arm740>
> +<arm, arm7tdmi>
> +<arm, arm920>
> +<arm, arm922>
> +<arm, arm925>
> +<arm, arm926>
> +<arm, arm940>
> +<arm, arm946>
> +<arm, arm9tdmi>
> +<arm, fa526>
> +<arm, feroceon>
> +<arm, mohawk>
> +<arm, sa110>
> +<arm, sa1100>
> +<arm, xsc3>
> +<arm, xscale>
> +<arm, cortex-a5>
> +<arm, cortex-a7>
> +<arm, cortex-a8>
> +<arm, cortex-a9>
> +<arm, cortex-a15>
> +<arm, arm1136>
> +<arm, arm11-mpcore>
Is this supposed to be an exhaustive list? What about 1156 and 1176? Also,
"arm11mpcore" should probably be used instead of "arm11-mpcore".
Will
^ permalink raw reply
* [PATCH 4/6] ASoC: wm8974: add SPI as a possible bus master
From: Mark Brown @ 2012-11-09 14:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352469625-32024-5-git-send-email-s.trumtrar@pengutronix.de>
On Fri, Nov 09, 2012 at 03:00:23PM +0100, Steffen Trumtrar wrote:
> The wm8974 can be controlled via i2c or spi. The current driver only supports
> i2c. Add SPI as possible bus.
>
> As the driver has to distinguish the bus type, pass this info via the wm8974_priv.
> This reverts c2562a8e3b5f871ad0b73caf98bb7541e8724efc, because the driver now
> needs it back.
Don't just quote raw commit IDs, *especially* not full ones, as they're
completely illegible to humans. Someone reading the changelog needs to
be able to understand what this commit is and why the driver needs it
back.
> - ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C);
> + ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8974->control_type);
We should be converting things to regmap if we're going to do this -
we're trying to phase out the ASoC-specific I/O and this makes the code
simpler anyway as the core will just be able to get the regmap from the
struct device without bouncing information around through the private
data and so on.
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* [PATCH v2 5/5] ARM: gic: use a private mapping for CPU target interfaces
From: Lorenzo Pieralisi @ 2012-11-09 14:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352471654-20207-1-git-send-email-lorenzo.pieralisi@arm.com>
From: Nicolas Pitre <nicolas.pitre@linaro.org>
The GIC interface numbering does not necessarily follow the logical
CPU numbering, especially for complex topologies such as multi-cluster
systems.
Fortunately we can easily probe the GIC to create a mapping as the
Interrupt Processor Targets Registers for the first 32 interrupts are
read-only, and each field returns a value that always corresponds to
the processor reading the register.
Initially all mappings target all CPUs in case an IPI is required to
boot secondary CPUs. It is refined as those CPUs discover what their
actual mapping is.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/common/gic.c | 45 ++++++++++++++++++++++++++++++++++++---------
1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 50c9eef..2203c92 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -70,6 +70,14 @@ struct gic_chip_data {
static DEFINE_RAW_SPINLOCK(irq_controller_lock);
/*
+ * The GIC mapping of CPU interfaces does not necessarily match
+ * the logical CPU numbering. Let's use a mapping as returned
+ * by the GIC itself.
+ */
+#define NR_GIC_CPU_IF 8
+static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
+
+/*
* Supported arch specific GIC irq extension.
* Default make them NULL.
*/
@@ -238,11 +246,11 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
u32 val, mask, bit;
- if (cpu >= 8 || cpu >= nr_cpu_ids)
+ if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
return -EINVAL;
mask = 0xff << shift;
- bit = 1 << (cpu_logical_map(cpu) + shift);
+ bit = gic_cpu_map[cpu] << shift;
raw_spin_lock(&irq_controller_lock);
val = readl_relaxed(reg) & ~mask;
@@ -349,11 +357,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
u32 cpumask;
unsigned int gic_irqs = gic->gic_irqs;
void __iomem *base = gic_data_dist_base(gic);
- u32 cpu = cpu_logical_map(smp_processor_id());
-
- cpumask = 1 << cpu;
- cpumask |= cpumask << 8;
- cpumask |= cpumask << 16;
writel_relaxed(0, base + GIC_DIST_CTRL);
@@ -366,6 +369,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
/*
* Set all global interrupts to this CPU only.
*/
+ cpumask = readl_relaxed(base + GIC_DIST_TARGET + 0);
for (i = 32; i < gic_irqs; i += 4)
writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
@@ -389,9 +393,25 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
{
void __iomem *dist_base = gic_data_dist_base(gic);
void __iomem *base = gic_data_cpu_base(gic);
+ unsigned int cpu_mask, cpu = smp_processor_id();
int i;
/*
+ * Get what the GIC says our CPU mask is.
+ */
+ BUG_ON(cpu >= NR_GIC_CPU_IF);
+ cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0);
+ gic_cpu_map[cpu] = cpu_mask;
+
+ /*
+ * Clear our mask from the other map entries in case they're
+ * still undefined.
+ */
+ for (i = 0; i < NR_GIC_CPU_IF; i++)
+ if (i != cpu)
+ gic_cpu_map[i] &= ~cpu_mask;
+
+ /*
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
*/
@@ -654,7 +674,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
{
irq_hw_number_t hwirq_base;
struct gic_chip_data *gic;
- int gic_irqs, irq_base;
+ int gic_irqs, irq_base, i;
BUG_ON(gic_nr >= MAX_GIC_NR);
@@ -692,6 +712,13 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
}
/*
+ * Initialize the CPU interface map to all CPUs.
+ * It will be refined as each CPU probes its ID.
+ */
+ for (i = 0; i < NR_GIC_CPU_IF; i++)
+ gic_cpu_map[i] = 0xff;
+
+ /*
* For primary GICs, skip over SGIs.
* For secondary GICs, skip over PPIs, too.
*/
@@ -746,7 +773,7 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
/* Convert our logical CPU mask into a physical one. */
for_each_cpu(cpu, mask)
- map |= 1 << cpu_logical_map(cpu);
+ map |= gic_cpu_map[cpu];
/*
* Ensure that stores to Normal memory are visible to the
--
1.7.12
^ permalink raw reply related
* [PATCH v2 4/5] ARM: kernel: add logical mappings look-up
From: Lorenzo Pieralisi @ 2012-11-09 14:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352471654-20207-1-git-send-email-lorenzo.pieralisi@arm.com>
In ARM SMP systems the MPIDR register ([23:0] bits) is used to uniquely
identify CPUs.
In order to retrieve the logical CPU index corresponding to a given
MPIDR value and guarantee a consistent translation throughout the kernel,
this patch adds a look-up based on the MPIDR[23:0] so that kernel subsystems
can use it whenever the logical cpu index corresponding to a given MPIDR
value is needed.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/include/asm/smp_plat.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 558d6c8..aaa61b6 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -5,6 +5,9 @@
#ifndef __ASMARM_SMP_PLAT_H
#define __ASMARM_SMP_PLAT_H
+#include <linux/cpumask.h>
+#include <linux/err.h>
+
#include <asm/cputype.h>
/*
@@ -48,5 +51,19 @@ static inline int cache_ops_need_broadcast(void)
*/
extern int __cpu_logical_map[];
#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
+/*
+ * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
+ * - mpidr: MPIDR[23:0] to be used for the look-up
+ *
+ * Returns the cpu logical index or -EINVAL on look-up error
+ */
+static inline int get_logical_index(u32 mpidr)
+{
+ int cpu;
+ for (cpu = 0; cpu < nr_cpu_ids; cpu++)
+ if (cpu_logical_map(cpu) == mpidr)
+ return cpu;
+ return -EINVAL;
+}
#endif
--
1.7.12
^ permalink raw reply related
* [PATCH v2 3/5] ARM: kernel: add cpu logical map DT init in setup_arch
From: Lorenzo Pieralisi @ 2012-11-09 14:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352471654-20207-1-git-send-email-lorenzo.pieralisi@arm.com>
As soon as the device tree is unflattened the cpu logical to physical
mapping is carried out in setup_arch to build a proper array of MPIDR and
corresponding logical indexes.
The mapping could have been carried out using the flattened DT blob and
related primitives, but since the mapping is not needed by early boot
code it can safely be executed when the device tree has been uncompressed to
its tree data structure.
This patch adds the arm_dt_init_cpu maps() function call in setup_arch().
If the kernel is not compiled with DT support the function is empty and
no logical mapping takes place through it; the mapping carried out in
smp_setup_processor_id() is left unchanged.
If DT is supported the mapping created in smp_setup_processor_id() is overriden.
The DT mapping also sets the possible cpus mask, hence platform
code need not set it again in the respective smp_init_cpus() functions.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/kernel/setup.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index ede7c84..8dc3340 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -759,6 +759,7 @@ void __init setup_arch(char **cmdline_p)
unflatten_device_tree();
+ arm_dt_init_cpu_maps();
#ifdef CONFIG_SMP
if (is_smp()) {
smp_set_ops(mdesc->smp);
--
1.7.12
^ permalink raw reply related
* [PATCH v2 2/5] ARM: kernel: add device tree init map function
From: Lorenzo Pieralisi @ 2012-11-09 14:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352471654-20207-1-git-send-email-lorenzo.pieralisi@arm.com>
When booting through a device tree, the kernel cpu logical id map can be
initialized using device tree data passed by FW or through an embedded blob.
This patch adds a function that parses device tree "cpu" nodes and
retrieves the corresponding CPUs hardware identifiers (MPIDR).
It sets the possible cpus and the cpu logical map values according to
the number of CPUs defined in the device tree and respective properties.
The device tree HW identifiers are considered valid if all CPU nodes contain
a "reg" property and the DT defines a CPU node that matches the MPIDR[23:0]
of the boot CPU.
The primary CPU is assigned cpu logical number 0 to keep the current convention
valid.
Current bindings documentation is included in the patch:
Documentation/devicetree/bindings/arm/cpus.txt
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
Documentation/devicetree/bindings/arm/cpus.txt | 84 ++++++++++++++++++++++++++
arch/arm/include/asm/prom.h | 2 +
arch/arm/kernel/devtree.c | 76 +++++++++++++++++++++++
3 files changed, 162 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/cpus.txt
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
new file mode 100644
index 0000000..83cd98a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -0,0 +1,84 @@
+* ARM CPUs binding description
+
+The device tree allows to describe the layout of CPUs in a system through
+the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+defining properties for every cpu.
+
+Bindings for CPU nodes follow the ePAPR standard, available from:
+
+http://devicetree.org
+
+For the ARM architecture every CPU node must contain the following properties:
+
+- reg : property matching the CPU MPIDR[23:0] register bits
+- compatible: must be set to "arm, <cpu-model>"
+ where <cpu-model> is the full processor name as used in the
+ processor Technical Reference Manual, eg:
+ - for a Cortex A9 processor
+ compatible = <arm, cortex-a9>;
+ - for a Cortex A15 processor
+ compatible = <arm, cortex-a15>;
+
+List of possible "compatible" string ids:
+
+<arm, arm1020>
+<arm, arm1020e>
+<arm, arm1022>
+<arm, arm1026>
+<arm, arm720>
+<arm, arm740>
+<arm, arm7tdmi>
+<arm, arm920>
+<arm, arm922>
+<arm, arm925>
+<arm, arm926>
+<arm, arm940>
+<arm, arm946>
+<arm, arm9tdmi>
+<arm, fa526>
+<arm, feroceon>
+<arm, mohawk>
+<arm, sa110>
+<arm, sa1100>
+<arm, xsc3>
+<arm, xscale>
+<arm, cortex-a5>
+<arm, cortex-a7>
+<arm, cortex-a8>
+<arm, cortex-a9>
+<arm, cortex-a15>
+<arm, arm1136>
+<arm, arm11-mpcore>
+
+Every cpu node is required to set its device_type to "cpu".
+
+Example:
+
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ CPU0: cpu at 0 {
+ device_type = "cpu";
+ compatible = <arm, cortex-a15>;
+ reg = <0x0>;
+ };
+
+ CPU1: cpu at 1 {
+ device_type = "cpu";
+ compatible = <arm, cortex-a15>;
+ reg = <0x1>;
+ };
+
+ CPU2: cpu at 100 {
+ device_type = "cpu";
+ compatible = <arm, cortex-a7>;
+ reg = <0x100>;
+ };
+
+ CPU3: cpu at 101 {
+ device_type = "cpu";
+ compatible = <arm, cortex-a7>;
+ reg = <0x101>;
+ };
+ };
diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h
index aeae9c6..8dd51dc 100644
--- a/arch/arm/include/asm/prom.h
+++ b/arch/arm/include/asm/prom.h
@@ -15,6 +15,7 @@
extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys);
extern void arm_dt_memblock_reserve(void);
+extern void __init arm_dt_init_cpu_maps(void);
#else /* CONFIG_OF */
@@ -24,6 +25,7 @@ static inline struct machine_desc *setup_machine_fdt(unsigned int dt_phys)
}
static inline void arm_dt_memblock_reserve(void) { }
+static inline void arm_dt_init_cpu_maps(void) { }
#endif /* CONFIG_OF */
#endif /* ASMARM_PROM_H */
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index bee7f9d..d64d222 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -19,8 +19,10 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
+#include <asm/cputype.h>
#include <asm/setup.h>
#include <asm/page.h>
+#include <asm/smp_plat.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@@ -61,6 +63,80 @@ void __init arm_dt_memblock_reserve(void)
}
}
+/*
+ * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
+ * and builds the cpu logical map array containing MPIDR values related to
+ * logical cpus
+ *
+ * Updates the cpu possible mask with the number of parsed cpu nodes
+ */
+void __init arm_dt_init_cpu_maps(void)
+{
+ struct device_node *cpu, *cpus;
+ u32 i, cpuidx = 1, mpidr = read_cpuid_mpidr() & 0xffffff;
+ u32 tmp_map[NR_CPUS];
+ bool bootcpu_valid = false;
+
+ cpus = of_find_node_by_path("/cpus");
+
+ if (!cpus)
+ return;
+
+ memset(tmp_map, 0, sizeof(tmp_map));
+
+ for_each_child_of_node(cpus, cpu) {
+ u32 hwid;
+
+ pr_debug(" * %s...\n", cpu->full_name);
+ /*
+ * A device tree containing CPU nodes with missing "reg"
+ * properties is considered invalid to build the
+ * cpu_logical_map.
+ */
+ if (of_property_read_u32(cpu, "reg", &hwid)) {
+ pr_debug(" * %s missing reg property\n",
+ cpu->full_name);
+ return;
+ }
+
+ /*
+ * Build a stashed array of MPIDR values. Numbering scheme
+ * requires that if detected the boot CPU must be assigned
+ * logical id 0. Other CPUs get sequential indexes starting
+ * from 1. If a CPU node with a reg property matching the
+ * boot CPU MPIDR is detected, this is recorded so that the
+ * logical map built from DT is validated and can be used
+ * to override the map created in smp_setup_processor_id().
+ */
+ if (hwid == mpidr) {
+ i = 0;
+ bootcpu_valid = true;
+ } else {
+ i = cpuidx++;
+ }
+
+ tmp_map[i] = hwid;
+
+ if (cpuidx > nr_cpu_ids)
+ break;
+ }
+
+ if (WARN(!bootcpu_valid, "DT CPU bindings are not valid,"
+ "fall back to default cpu_logical_map\n"))
+ return;
+
+ /*
+ * Since the boot CPU node contains proper data, and all nodes have
+ * a reg property, the DT CPU list can be considered valid and the
+ * logical map created in smp_setup_processor_id() can be overridden
+ */
+ for (i = 0; i < cpuidx; i++) {
+ set_cpu_possible(i, true);
+ cpu_logical_map(i) = tmp_map[i];
+ pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
+ }
+}
+
/**
* setup_machine_fdt - Machine setup when an dtb was passed to the kernel
* @dt_phys: physical address of dt blob
--
1.7.12
^ permalink raw reply related
* [PATCH v2 1/5] ARM: kernel: smp_setup_processor_id() updates
From: Lorenzo Pieralisi @ 2012-11-09 14:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352471654-20207-1-git-send-email-lorenzo.pieralisi@arm.com>
This patch applies some basic changes to the smp_setup_processor_id()
ARM implementation to make the code that builds cpu_logical_map more
uniform across the kernel.
The function now prints the full extent of the boot CPU MPIDR[23:0] and
initializes the cpu_logical_map for CPUs up to nr_cpu_ids.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/kernel/setup.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index da1d1aa..ede7c84 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -426,13 +426,14 @@ int __cpu_logical_map[NR_CPUS];
void __init smp_setup_processor_id(void)
{
int i;
- u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
+ u32 mpidr = read_cpuid_mpidr() & 0xffffff;
+ u32 cpu = is_smp() ? mpidr & 0xff : 0;
cpu_logical_map(0) = cpu;
- for (i = 1; i < NR_CPUS; ++i)
+ for (i = 1; i < nr_cpu_ids; ++i)
cpu_logical_map(i) = i == cpu ? 0 : i;
- printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu);
+ printk(KERN_INFO "Booting Linux on physical CPU 0x%x\n", mpidr);
}
static void __init setup_processor(void)
--
1.7.12
^ permalink raw reply related
* [PATCH v2 0/5] ARM: multi-cluster aware boot protocol
From: Lorenzo Pieralisi @ 2012-11-09 14:34 UTC (permalink / raw)
To: linux-arm-kernel
This series is v2, referred to this previous posting:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-October/125878.html
Changes in v2:
- Reworded and added compatible property to cpus.txt
- Replaced while loop in arm_dt_init_cpu_maps() with a combination of
of_find_node_by_path and for_each_child_of_node
- Replaced of_get_property with of_property_read_u32
- Added further checks for DT /cpu nodes and implemented stashed array
to avoid overwriting the cpu_logical_map if DT contains errors
- Added GIC CPU IF define in the GIC probing code
- Removed printk for boot CPU MPIDR and added a patch that prints the full
extent of MPIDR in smp_setup_processor_id()
- Updated smp_setup_processor_id() so that it uses nr_cpu_ids
- Dropped RFC tag
The introduction of multi-cluster ARM systems in SoC designs requires the
kernel to become cluster aware, so that it can be booted on every CPU in the
system and it can build an appropriate HW-to-logical cpu map.
Current code in the kernel, in particular the boot sequence, hinges upon a
sequential mapping of MPIDR values for cpus and related interrupt controller
CPU interfaces to logical cpu indexing.
This hypothesis is not valid when the concept of cluster is introduced since
the MPIDR cannot be represented as a single index and interrupt controller
CPU interfaces can be wired with a numbering scheme following per-SoC
design parameters which can be only detected through probing or device
tree representation.
Through the device tree and "cpu" nodes bindings, the kernel is provided
with HW values for MPIDR registers that allow the kernel to identify the
HW CPU ids that are present in the platform.
The GIC code has been extended to allow automatic detection of GIC CPU IF ids
at boot. IPIs are broadcast to all possible CPUs, and every time a secondary
CPU is booted, it initializes its own mask and clears itself from the mask of
all other logical CPUs.
The device tree bindings and GIC probing allow to boot the Linux kernel on any
CPU of a multi-cluster system without relying on a platform specific hook to
identify the number of CPUs and hypothesis on the sequential pattern of MPIDRs
and relative GIC CPU IF ids.
Pen release code for all converted platforms will need patching to extend the
current MPIDR range check; this will take place as soon as the bindings and
code for the multi-cluster boot protocol will be reviewed and accepted.
The patchset has been tested on:
- TC2 testchip
to boot a 5-core dual-cluster system on every possible CPU.
Lorenzo Pieralisi (4):
ARM: kernel: smp_setup_processor_id() updates
ARM: kernel: add device tree init map function
ARM: kernel: add cpu logical map DT init in setup_arch
ARM: kernel: add logical mappings look-up
Nicolas Pitre (1):
ARM: gic: use a private mapping for CPU target interfaces
Documentation/devicetree/bindings/arm/cpus.txt | 84 ++++++++++++++++++++++++++
arch/arm/common/gic.c | 45 +++++++++++---
arch/arm/include/asm/prom.h | 2 +
arch/arm/include/asm/smp_plat.h | 17 ++++++
arch/arm/kernel/devtree.c | 76 +++++++++++++++++++++++
arch/arm/kernel/setup.c | 8 ++-
6 files changed, 220 insertions(+), 12 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/cpus.txt
--
1.7.12
^ permalink raw reply
* [PATCHv2] ARM: OMAP4: USB: power down MUSB PHY during boot
From: Tero Kristo @ 2012-11-09 14:30 UTC (permalink / raw)
To: linux-arm-kernel
Commit c9e4412ab8eb8ef82d645d8749c4ce96ad490007 removed all of the USB
PHY functions for OMAP4, but this causes a problem with core retention
as the MUSB module remains enabled if omap-usb2 phy driver is not used.
This keeps the USB DPLL enabled and prevents l3_init pwrdm from idling.
Fixed by adding a minimal function back that disables the USB PHY during
boot.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
---
arch/arm/mach-omap2/omap_phy_internal.c | 32 +++++++++++++++++++++++++++++++
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index d992db8..9b56e5e 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -33,6 +33,38 @@
#include "soc.h"
#include "control.h"
+#define CONTROL_DEV_CONF 0x300
+#define PHY_PD 0x1
+
+/**
+ * omap4430_phy_power_down: disable MUSB PHY during early init
+ *
+ * OMAP4 MUSB PHY module is enabled by default on reset, but this will
+ * prevent core retention if not disabled by SW. USB driver will
+ * later on enable this, once and if the driver needs it.
+ */
+static int __init omap4430_phy_power_down(void)
+{
+ void __iomem *ctrl_base;
+
+ if (!cpu_is_omap44xx())
+ return 0;
+
+ ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
+ if (!ctrl_base) {
+ pr_err("control module ioremap failed\n");
+ return -ENOMEM;
+ }
+
+ /* Power down the phy */
+ __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
+
+ iounmap(ctrl_base);
+
+ return 0;
+}
+early_initcall(omap4430_phy_power_down);
+
void am35x_musb_reset(void)
{
u32 regval;
--
1.7.4.1
^ permalink raw reply related
* [PATCHv2] ARM: OMAP4: USB: power down MUSB PHY during boot
From: Felipe Balbi @ 2012-11-09 14:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352471435-9560-1-git-send-email-t-kristo@ti.com>
HI,
On Fri, Nov 09, 2012 at 04:30:35PM +0200, Tero Kristo wrote:
> Commit c9e4412ab8eb8ef82d645d8749c4ce96ad490007 removed all of the USB
> PHY functions for OMAP4, but this causes a problem with core retention
> as the MUSB module remains enabled if omap-usb2 phy driver is not used.
> This keeps the USB DPLL enabled and prevents l3_init pwrdm from idling.
>
> Fixed by adding a minimal function back that disables the USB PHY during
> boot.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: Felipe Balbi <balbi@ti.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Kevin Hilman <khilman@ti.com>
looks good to me. I would still suggest adding a REVISIT or FIXME note
stating that this should be moved to SCM driver eventually ;-)
Other than that:
Acked-by: Felipe Balbi <balbi@ti.com>
> ---
> arch/arm/mach-omap2/omap_phy_internal.c | 32 +++++++++++++++++++++++++++++++
> 1 files changed, 32 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
> index d992db8..9b56e5e 100644
> --- a/arch/arm/mach-omap2/omap_phy_internal.c
> +++ b/arch/arm/mach-omap2/omap_phy_internal.c
> @@ -33,6 +33,38 @@
> #include "soc.h"
> #include "control.h"
>
> +#define CONTROL_DEV_CONF 0x300
> +#define PHY_PD 0x1
> +
> +/**
> + * omap4430_phy_power_down: disable MUSB PHY during early init
> + *
> + * OMAP4 MUSB PHY module is enabled by default on reset, but this will
> + * prevent core retention if not disabled by SW. USB driver will
> + * later on enable this, once and if the driver needs it.
> + */
> +static int __init omap4430_phy_power_down(void)
> +{
> + void __iomem *ctrl_base;
> +
> + if (!cpu_is_omap44xx())
> + return 0;
> +
> + ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
> + if (!ctrl_base) {
> + pr_err("control module ioremap failed\n");
> + return -ENOMEM;
> + }
> +
> + /* Power down the phy */
> + __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
> +
> + iounmap(ctrl_base);
> +
> + return 0;
> +}
> +early_initcall(omap4430_phy_power_down);
> +
> void am35x_musb_reset(void)
> {
> u32 regval;
> --
> 1.7.4.1
>
--
balbi
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* [GIT PULL] ARM: OMAP: GPMC generic timing
From: Afzal Mohammed @ 2012-11-09 14:21 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 6ba54ab4a49bbad736b0254aa6bdf0cb83013815:
ARM: OMAP: Remove omap_init_consistent_dma_size() (2012-11-06 16:01:19 -0800)
are available in the git repository at:
git://gitorious.org/x0148406-public/linux-kernel.git tags/gpmc-generic-timing
for you to fetch changes up to 47acde16726080e5157b602f23937d00a04cd2ed:
ARM: OMAP2+: tusb6010: generic timing calculation (2012-11-09 18:07:23 +0530)
----------------------------------------------------------------
These changes provide a generic gpmc timing calculation method,
migrates existing peripherals that makes use of custom gpmc timing
calculation method to use the new generic one.
Generic routine has been verified for onenand async timing calculation
on omap3evm (with a local change to add onenand support). Generic
timing calculation method were verified for other peripherals by
simulation. Generic method has to be verified on peripherals supported
in mainline.
----------------------------------------------------------------
Afzal Mohammed (6):
ARM: OMAP2+: nand: remove redundant rounding
ARM: OMAP2+: gpmc: handle additional timings
ARM: OMAP2+: gpmc: generic timing calculation
ARM: OMAP2+: onenand: generic timing calculation
ARM: OMAP2+: smc91x: generic timing calculation
ARM: OMAP2+: tusb6010: generic timing calculation
Documentation/bus-devices/ti-gpmc.txt | 122 +++++++++++
arch/arm/mach-omap2/gpmc-nand.c | 26 +--
arch/arm/mach-omap2/gpmc-onenand.c | 143 ++++---------
arch/arm/mach-omap2/gpmc-smc91x.c | 43 ++--
arch/arm/mach-omap2/gpmc.c | 373 ++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/gpmc.h | 113 ++++++++--
arch/arm/mach-omap2/usb-tusb6010.c | 181 ++++-------------
7 files changed, 709 insertions(+), 292 deletions(-)
create mode 100644 Documentation/bus-devices/ti-gpmc.txt
^ permalink raw reply
* Migrating from lpc3130 to lpc3141 processor
From: Mridula Prakash @ 2012-11-09 14:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
We have migrated from the LPC3130 controller to LPC3141 controller. We have a code base full functional for LPC3131 processor, working on an apex boot loader, Linux Kernel 2.6.28.
The same code base when used on LPC3141 processor in DFU mode failed to upgrade.
Can you provide any specific changes related to kernel and bootloader that has to be taken care to boot the system?
If any patches are available for the same.
Thanks and Regards
Mridula Prakash
Larsen & Toubro Limited
www.larsentoubro.com
This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.
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* [PATCH 03/16] mm: check rb_subtree_gap correctness
From: Sasha Levin @ 2012-11-09 14:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352155633-8648-4-git-send-email-walken@google.com>
On 11/05/2012 05:47 PM, Michel Lespinasse wrote:
> When CONFIG_DEBUG_VM_RB is enabled, check that rb_subtree_gap is
> correctly set for every vma and that mm->highest_vm_end is also correct.
>
> Also add an explicit 'bug' variable to track if browse_rb() detected any
> invalid condition.
>
> Signed-off-by: Michel Lespinasse <walken@google.com>
> Reviewed-by: Rik van Riel <riel@redhat.com>
>
> ---
Hi all,
While fuzzing with trinity inside a KVM tools (lkvm) guest, using today's -next
kernel, I'm getting these:
[ 117.007714] free gap 7fba0dd1c000, correct 7fba0dcfb000
[ 117.019773] map_count 750 rb -1
[ 117.028362] ------------[ cut here ]------------
[ 117.029813] kernel BUG at mm/mmap.c:439!
[ 117.031024] invalid opcode: 0000 [#1] PREEMPT SMP DEBUG_PAGEALLOC
[ 117.032933] Dumping ftrace buffer:
[ 117.033972] (ftrace buffer empty)
[ 117.035085] CPU 4
[ 117.035676] Pid: 6859, comm: trinity-child46 Tainted: G W 3.7.0-rc4-next-20121109-sasha-00013-g9407f3c #124
[ 117.038217] RIP: 0010:[<ffffffff81236687>] [<ffffffff81236687>] validate_mm+0x297/0x2c0
[ 117.041056] RSP: 0018:ffff880016a4fdf8 EFLAGS: 00010296
[ 117.041056] RAX: 0000000000000013 RBX: 00000000ffffffff RCX: 0000000000000006
[ 117.041056] RDX: 0000000000005270 RSI: ffff880024120910 RDI: 0000000000000286
[ 117.052131] RBP: ffff880016a4fe48 R08: 0000000000000000 R09: 0000000000000000
[ 117.052131] R10: 0000000000000001 R11: 0000000000000000 R12: 00000000000002ee
[ 117.052131] R13: 00007fffea1fc000 R14: ffff88002412c000 R15: 0000000000000000
[ 117.052131] FS: 00007fba129db700(0000) GS:ffff880063600000(0000) knlGS:0000000000000000
[ 117.052131] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 117.052131] CR2: 0000000003323288 CR3: 00000000169b2000 CR4: 00000000000406e0
[ 117.052131] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[ 117.052131] DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
[ 117.052131] Process trinity-child46 (pid: 6859, threadinfo ffff880016a4e000, task ffff880024120000)
[ 117.052131] Stack:
[ 117.052131] ffffffff8489e201 ffffffff81235aa0 ffff88000885cac8 0000000100000000
[ 117.052131] ffffffff812361b9 ffff88002412c000 ffff88000885cac8 ffff88000885cdc8
[ 117.052131] ffff88000885cdd0 ffff88002412c000 ffff880016a4fe98 ffffffff812367b4
[ 117.052131] Call Trace:
[ 117.052131] [<ffffffff81235aa0>] ? vma_compute_subtree_gap+0x40/0x40
[ 117.052131] [<ffffffff812361b9>] ? vma_gap_update+0x19/0x30
[ 117.052131] [<ffffffff812367b4>] vma_link+0x94/0xe0
[ 117.052131] [<ffffffff812386c4>] do_brk+0x2c4/0x380
[ 117.052131] [<ffffffff812387bf>] ? sys_brk+0x3f/0x190
[ 117.052131] [<ffffffff812388ce>] sys_brk+0x14e/0x190
[ 117.052131] [<ffffffff83be2618>] tracesys+0xe1/0xe6
[ 117.052131] Code: d8 41 8b 76 60 39 de 74 1b 89 da 48 c7 c7 c6 d9 89 84 31 c0 e8 01 76 94 02 eb 10 66 0f 1f 84 00 00 00 00 00
8b 45 c8 85 c0 74 18 <0f> 0b 4c 8d 48 e0 48 8b 70 e0 31 db c7 45 cc 00 00 00 00 e9 f4
[ 117.052131] RIP [<ffffffff81236687>] validate_mm+0x297/0x2c0
[ 117.052131] RSP <ffff880016a4fdf8>
[ 117.136092] ---[ end trace 5ce250e0bf6d040c ]---
Note that they are very easy to reproduce.
Also, I see that lots of the code there has a local variable named 'bug' thats tracking
whether we should BUG() later on. Why does it work that way and the BUG() isn't immediate?
Thanks,
Sasha
^ permalink raw reply
* [PATCH v2] i2c: at91: add dma support
From: ludovic.desroches at atmel.com @ 2012-11-09 14:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Ludovic Desroches <ludovic.desroches@atmel.com>
Add dma support for Atmel TWI which is available on sam9x5 and later.
When using dma for reception, you have to read only n-2 bytes. The last
two bytes are read manually. Don't doing this should cause to send the
STOP command too late and then to get extra data in the receive
register.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
---
Changes:
- v2 (based on Russell feedback):
- replace DMA_TO_DEVICE/DMA_FROM_DEVICE by DMA_MEM_TO_DEV/DMA_DEV_TO_MEM
- don't check for tx_submit errors
- atmel dma header location has changed
drivers/i2c/busses/i2c-at91.c | 316 ++++++++++++++++++++++++++++++++++++++++--
1 file changed, 305 insertions(+), 11 deletions(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index aa59a25..f6fba9c 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -19,6 +19,8 @@
#include <linux/clk.h>
#include <linux/completion.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
@@ -30,6 +32,8 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
+#include <linux/platform_data/dma-atmel.h>
+
#define TWI_CLK_HZ 100000 /* max 400 Kbits/s */
#define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
@@ -65,9 +69,21 @@
#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
struct at91_twi_pdata {
- unsigned clk_max_div;
- unsigned clk_offset;
- bool has_unre_flag;
+ unsigned clk_max_div;
+ unsigned clk_offset;
+ bool has_unre_flag;
+ bool has_dma_support;
+ struct at_dma_slave dma_slave;
+};
+
+struct at91_twi_dma {
+ struct dma_chan *chan_rx;
+ struct dma_chan *chan_tx;
+ struct scatterlist sg;
+ struct dma_async_tx_descriptor *data_desc;
+ enum dma_transfer_direction direction;
+ bool buf_mapped;
+ bool xfer_in_progress;
};
struct at91_twi_dev {
@@ -79,10 +95,13 @@ struct at91_twi_dev {
size_t buf_len;
struct i2c_msg *msg;
int irq;
+ unsigned imr;
unsigned transfer_status;
struct i2c_adapter adapter;
unsigned twi_cwgr_reg;
struct at91_twi_pdata *pdata;
+ bool use_dma;
+ struct at91_twi_dma dma;
};
static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
@@ -101,6 +120,17 @@ static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY);
}
+static void at91_twi_irq_save(struct at91_twi_dev *dev)
+{
+ dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & 0x7;
+ at91_disable_twi_interrupts(dev);
+}
+
+static void at91_twi_irq_restore(struct at91_twi_dev *dev)
+{
+ at91_twi_write(dev, AT91_TWI_IER, dev->imr);
+}
+
static void at91_init_twi_bus(struct at91_twi_dev *dev)
{
at91_disable_twi_interrupts(dev);
@@ -137,6 +167,30 @@ static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
}
+static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
+{
+ struct at91_twi_dma *dma = &dev->dma;
+
+ at91_twi_irq_save(dev);
+
+ if (dma->xfer_in_progress) {
+ if (dma->direction == DMA_DEV_TO_MEM)
+ dma->chan_rx->device->device_control(dma->chan_rx,
+ DMA_TERMINATE_ALL, 0);
+ else
+ dma->chan_tx->device->device_control(dma->chan_tx,
+ DMA_TERMINATE_ALL, 0);
+ dma->xfer_in_progress = false;
+ }
+ if (dma->buf_mapped) {
+ dma_unmap_single(dev->dev, sg_dma_address(&dma->sg),
+ dev->buf_len, dma->direction);
+ dma->buf_mapped = false;
+ }
+
+ at91_twi_irq_restore(dev);
+}
+
static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
{
if (dev->buf_len <= 0)
@@ -153,6 +207,61 @@ static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
++dev->buf;
}
+static void at91_twi_write_data_dma_callback(void *data)
+{
+ struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
+
+ dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
+ dev->buf_len, DMA_MEM_TO_DEV);
+
+ at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
+}
+
+static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
+{
+ dma_addr_t dma_addr;
+ dma_cookie_t cookie;
+ struct dma_async_tx_descriptor *txdesc;
+ struct at91_twi_dma *dma = &dev->dma;
+ struct dma_chan *chan_tx = dma->chan_tx;
+
+ if (dev->buf_len <= 0)
+ return;
+
+ dma->direction = DMA_MEM_TO_DEV;
+
+ at91_twi_irq_save(dev);
+ dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
+ DMA_MEM_TO_DEV);
+ if (dma_mapping_error(dev->dev, dma_addr)) {
+ dev_err(dev->dev, "dma map failed\n");
+ return;
+ }
+ dma->buf_mapped = true;
+ at91_twi_irq_restore(dev);
+ sg_dma_len(&dma->sg) = dev->buf_len;
+ sg_dma_address(&dma->sg) = dma_addr;
+
+ txdesc = chan_tx->device->device_prep_slave_sg(chan_tx, &dma->sg,
+ 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK, NULL);
+ if (!txdesc) {
+ dev_err(dev->dev, "dma prep slave sg failed\n");
+ goto error;
+ }
+
+ txdesc->callback = at91_twi_write_data_dma_callback;
+ txdesc->callback_param = dev;
+
+ dma->xfer_in_progress = true;
+ cookie = txdesc->tx_submit(txdesc);
+ dma->chan_tx->device->device_issue_pending(chan_tx);
+
+ return;
+
+error:
+ at91_twi_dma_cleanup(dev);
+}
+
static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
{
if (dev->buf_len <= 0)
@@ -178,6 +287,62 @@ static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
++dev->buf;
}
+static void at91_twi_read_data_dma_callback(void *data)
+{
+ struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
+
+ dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
+ dev->buf_len, DMA_DEV_TO_MEM);
+
+ /* The last two bytes have to be read without using dma */
+ dev->buf += dev->buf_len - 2;
+ dev->buf_len = 2;
+ at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_RXRDY);
+}
+
+static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
+{
+ dma_addr_t dma_addr;
+ dma_cookie_t cookie;
+ struct dma_async_tx_descriptor *rxdesc;
+ struct at91_twi_dma *dma = &dev->dma;
+ struct dma_chan *chan_rx = dma->chan_rx;
+
+ dma->direction = DMA_DEV_TO_MEM;
+
+ /* Keep in mind that we won't use dma to read the last two bytes */
+ at91_twi_irq_save(dev);
+ dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len - 2,
+ DMA_DEV_TO_MEM);
+ if (dma_mapping_error(dev->dev, dma_addr)) {
+ dev_err(dev->dev, "dma map failed\n");
+ return;
+ }
+ dma->buf_mapped = true;
+ at91_twi_irq_restore(dev);
+ dma->sg.dma_address = dma_addr;
+ sg_dma_len(&dma->sg) = dev->buf_len - 2;
+
+ rxdesc = chan_rx->device->device_prep_slave_sg(chan_rx, &dma->sg,
+ 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK, NULL);
+ if (!rxdesc) {
+ dev_err(dev->dev, "dma prep slave sg failed\n");
+ goto error;
+ }
+
+ rxdesc->callback = at91_twi_read_data_dma_callback;
+ rxdesc->callback_param = dev;
+
+ dma->xfer_in_progress = true;
+ cookie = rxdesc->tx_submit(rxdesc);
+ dma->chan_rx->device->device_issue_pending(dma->chan_rx);
+
+ return;
+
+error:
+ at91_twi_dma_cleanup(dev);
+}
+
static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
{
struct at91_twi_dev *dev = dev_id;
@@ -224,12 +389,36 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN))
start_flags |= AT91_TWI_STOP;
at91_twi_write(dev, AT91_TWI_CR, start_flags);
- at91_twi_write(dev, AT91_TWI_IER,
+ /*
+ * When using dma, the last byte has to be read manually in
+ * order to not send the stop command too late and then
+ * to receive extra data. In practice, there are some issues
+ * if you use the dma to read n-1 bytes because of latency.
+ * Reading n-2 bytes with dma and the two last ones manually
+ * seems to be the best solution.
+ */
+ if (dev->use_dma && (dev->buf_len > 2)) {
+ at91_twi_read_data_dma(dev);
+ /*
+ * It is important to enable TXCOMP irq here because
+ * doing it only when transferring the last two bytes
+ * will mask NACK errors since TXCOMP is set when a
+ * NACK occurs.
+ */
+ at91_twi_write(dev, AT91_TWI_IER,
+ AT91_TWI_TXCOMP);
+ } else
+ at91_twi_write(dev, AT91_TWI_IER,
AT91_TWI_TXCOMP | AT91_TWI_RXRDY);
} else {
- at91_twi_write_next_byte(dev);
- at91_twi_write(dev, AT91_TWI_IER,
- AT91_TWI_TXCOMP | AT91_TWI_TXRDY);
+ if (dev->use_dma) {
+ at91_twi_write_data_dma(dev);
+ at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
+ } else {
+ at91_twi_write_next_byte(dev);
+ at91_twi_write(dev, AT91_TWI_IER,
+ AT91_TWI_TXCOMP | AT91_TWI_TXRDY);
+ }
}
ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
@@ -237,23 +426,31 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
if (ret == 0) {
dev_err(dev->dev, "controller timed out\n");
at91_init_twi_bus(dev);
- return -ETIMEDOUT;
+ ret = -ETIMEDOUT;
+ goto error;
}
if (dev->transfer_status & AT91_TWI_NACK) {
dev_dbg(dev->dev, "received nack\n");
- return -EREMOTEIO;
+ ret = -EREMOTEIO;
+ goto error;
}
if (dev->transfer_status & AT91_TWI_OVRE) {
dev_err(dev->dev, "overrun while reading\n");
- return -EIO;
+ ret = -EIO;
+ goto error;
}
if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
dev_err(dev->dev, "underrun while writing\n");
- return -EIO;
+ ret = -EIO;
+ goto error;
}
dev_dbg(dev->dev, "transfer complete\n");
return 0;
+
+error:
+ at91_twi_dma_cleanup(dev);
+ return ret;
}
static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
@@ -324,36 +521,42 @@ static struct at91_twi_pdata at91rm9200_config = {
.clk_max_div = 5,
.clk_offset = 3,
.has_unre_flag = true,
+ .has_dma_support = false,
};
static struct at91_twi_pdata at91sam9261_config = {
.clk_max_div = 5,
.clk_offset = 4,
.has_unre_flag = false,
+ .has_dma_support = false,
};
static struct at91_twi_pdata at91sam9260_config = {
.clk_max_div = 7,
.clk_offset = 4,
.has_unre_flag = false,
+ .has_dma_support = false,
};
static struct at91_twi_pdata at91sam9g20_config = {
.clk_max_div = 7,
.clk_offset = 4,
.has_unre_flag = false,
+ .has_dma_support = false,
};
static struct at91_twi_pdata at91sam9g10_config = {
.clk_max_div = 7,
.clk_offset = 4,
.has_unre_flag = false,
+ .has_dma_support = false,
};
static struct at91_twi_pdata at91sam9x5_config = {
.clk_max_div = 7,
.clk_offset = 4,
.has_unre_flag = false,
+ .has_dma_support = true,
};
static const struct platform_device_id at91_twi_devtypes[] = {
@@ -400,6 +603,90 @@ MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
#define atmel_twi_dt_ids NULL
#endif
+static bool __devinit filter(struct dma_chan *chan, void *slave)
+{
+ struct at_dma_slave *sl = slave;
+
+ if (sl->dma_dev == chan->device->dev) {
+ chan->private = sl;
+ return true;
+ } else {
+ return false;
+ }
+}
+
+static int __devinit at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
+{
+ int ret = 0;
+ struct at_dma_slave *sdata;
+ struct dma_slave_config slave_config;
+ struct at91_twi_dma *dma = &dev->dma;
+
+ sdata = &dev->pdata->dma_slave;
+
+ memset(&slave_config, 0, sizeof(slave_config));
+ slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
+ slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+ slave_config.src_maxburst = 1;
+ slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
+ slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+ slave_config.dst_maxburst = 1;
+ slave_config.device_fc = false;
+
+ if (sdata && sdata->dma_dev) {
+ dma_cap_mask_t mask;
+
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+ dma->chan_tx = dma_request_channel(mask, filter, sdata);
+ if (!dma->chan_tx) {
+ dev_err(dev->dev, "no DMA channel available for tx\n");
+ ret = -EBUSY;
+ goto error;
+ }
+ dma->chan_rx = dma_request_channel(mask, filter, sdata);
+ if (!dma->chan_rx) {
+ dev_err(dev->dev, "no DMA channel available for rx\n");
+ ret = -EBUSY;
+ goto error;
+ }
+ } else {
+ ret = -EINVAL;
+ goto error;
+ }
+
+ slave_config.direction = DMA_MEM_TO_DEV;
+ if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
+ dev_err(dev->dev, "failed to configure tx channel\n");
+ ret = -EINVAL;
+ goto error;
+ }
+
+ slave_config.direction = DMA_DEV_TO_MEM;
+ if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
+ dev_err(dev->dev, "failed to configure rx channel\n");
+ ret = -EINVAL;
+ goto error;
+ }
+
+ sg_init_table(&dma->sg, 1);
+ dma->buf_mapped = false;
+ dma->xfer_in_progress = false;
+
+ dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
+ dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
+
+ return ret;
+
+error:
+ dev_info(dev->dev, "can't use DMA\n");
+ if (dma->chan_rx)
+ dma_release_channel(dma->chan_rx);
+ if (dma->chan_tx)
+ dma_release_channel(dma->chan_tx);
+ return ret;
+}
+
static struct at91_twi_pdata * __devinit at91_twi_get_driver_data(
struct platform_device *pdev)
{
@@ -418,6 +705,7 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
struct at91_twi_dev *dev;
struct resource *mem;
int rc;
+ u32 phy_addr;
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
if (!dev)
@@ -428,6 +716,7 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mem)
return -ENODEV;
+ phy_addr = mem->start;
dev->pdata = at91_twi_get_driver_data(pdev);
if (!dev->pdata)
@@ -457,6 +746,11 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
}
clk_prepare_enable(dev->clk);
+ if (dev->pdata->has_dma_support) {
+ if (at91_twi_configure_dma(dev, phy_addr) == 0)
+ dev->use_dma = true;
+ }
+
at91_calc_twi_clock(dev, TWI_CLK_HZ);
at91_init_twi_bus(dev);
--
1.7.11.3
^ permalink raw reply related
* [GIT PULL] ARM: OMAP: DTS for 3.8 part 2
From: Benoit Cousson @ 2012-11-09 14:01 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tony,
Please pull some more OMAP5 and AM33xx data for 3.8.
Thanks,
Benoit
The following changes since commit 3b3132f7e80e3d786f8ad5d5b97d4b6122be9aaa:
Jon Hunter (1):
ARM: dts: OMAP5: Add counter node
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.8/dts_part2
Afzal Mohammed (1):
usb: musb: dsps: dt binding - add resources, example
Ajay Kumar Gupta (1):
ARM: dts: AM33XX: Add usbss node
AnilKumar Ch (10):
ARM: dts: AM33XX: Add pinmux configuration for matrix keypad to EVM
ARM: dts: AM33XX: Add matrix keypad device tree data to am335x-evm
ARM: dts: AM33XX: Add pinmux configuration for volume-keys to EVM
ARM: dts: AM33XX: Add volume-keys device tree data to am335x-evm
ARM: dts: AM33XX: Add pinmux configuration for user-leds to BONE
ARM: dts: AM33XX: Add user-leds device tree data to am335x-bone
ARM: dts: AM33XX: Add pinmux configuration for gpio-leds to EVMSK
ARM: dts: AM33XX: Add user-leds device tree data to am335x-evmsk
ARM: dts: AM33XX: Add pinmux configuration for gpio-keys to EVMSK
ARM: dts: AM33XX: Add push-buttons device tree data to am335x-evmsk
Benoit Cousson (1):
ARM: dts: Makefile: Add the am335x-evmsk target in dtbs list
Lokesh Vutla (3):
ARM: dts: omap5-evm: Fix size of memory defined for EVM
ARM: dts: omap5: EMIF device tree data for OMAP5 boards
ARM: dts: omap5-evm: LPDDR2 memory device details for EVM
Ricardo Neri (2):
ARM: dts: omap4-panda: Add pinmux configuration for HDMI
ARM: dts: omap4-sdp: Add pinmux configuration for HDMI
.../devicetree/bindings/usb/am33xx-usb.txt | 21 +++++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/am335x-bone.dts | 44 ++++++++++
arch/arm/boot/dts/am335x-evm.dts | 63 +++++++++++++++
arch/arm/boot/dts/am335x-evmsk.dts | 84 ++++++++++++++++++++
arch/arm/boot/dts/am33xx.dtsi | 17 ++++
arch/arm/boot/dts/omap4-panda-a4.dts | 17 ++++
arch/arm/boot/dts/omap4-panda-es.dts | 9 ++
arch/arm/boot/dts/omap4-panda.dts | 18 ++++
arch/arm/boot/dts/omap4-sdp-es23plus.dts | 17 ++++
arch/arm/boot/dts/omap4-sdp.dts | 18 ++++
arch/arm/boot/dts/omap5-evm.dts | 13 +++-
arch/arm/boot/dts/omap5.dtsi | 22 +++++
arch/arm/boot/dts/samsung_k3pe0e000b.dtsi | 67 ++++++++++++++++
14 files changed, 410 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/boot/dts/omap4-panda-a4.dts
create mode 100644 arch/arm/boot/dts/omap4-sdp-es23plus.dts
create mode 100644 arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
^ permalink raw reply
* [PATCH 6/6] ASoC: fsl: add imx-wm8974 machine driver
From: Steffen Trumtrar @ 2012-11-09 14:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352469625-32024-1-git-send-email-s.trumtrar@pengutronix.de>
This is the initial support for a wm8974 sound codec connected to an imx ssi.
It follows along the lines of the imx-sgtl5000 driver.
* only the playback dai link is implemented.
* DT only driver, working with the fsl_ssi driver and imx21 compatible
audmux
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
.../devicetree/bindings/sound/imx-audio-wm8974.txt | 48 ++++
sound/soc/fsl/Kconfig | 12 +
sound/soc/fsl/Makefile | 2 +
sound/soc/fsl/imx-wm8974.c | 233 ++++++++++++++++++++
4 files changed, 295 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-wm8974.txt
create mode 100644 sound/soc/fsl/imx-wm8974.c
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8974.txt b/Documentation/devicetree/bindings/sound/imx-audio-wm8974.txt
new file mode 100644
index 0000000..7e661e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-wm8974.txt
@@ -0,0 +1,48 @@
+Freescale i.MX audio complex with WM8974 codec
+
+Required properties:
+- compatible : "fsl,imx-audio-wm8974"
+- model : The user-visible name of this sound complex
+- ssi-controller : The phandle of the i.MX SSI controller (imx21 compatible)
+- audio-codec : The phandle of the WM8974 audio codec
+- audio-routing : A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the connection's sink,
+ the second being the connection's source. Valid names could be power
+ supplies, WM8974 pins, and the jacks on the board:
+
+ Power supplies:
+ * Mic Bias
+
+ WM8974 pins:
+ * MICN
+ * MICP
+ * AUX
+ * MONOOUT
+ * SPKOUTP
+ * SPKOUTN
+
+ Board connectors:
+ * Mic Jack
+ * Line In Jack
+ * Headphone Jack
+ * Line Out Jack
+ * Ext Spk
+
+- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
+- mux-ext-port : The external port of the i.MX audio muxer
+
+Note: The AUDMUX port numbering should start at 1, which is consistent with
+hardware manual.
+
+Example:
+
+sound {
+ compatible = "fsl,imx-audio-wm8974";
+ model = "wm8974";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&wm8974>;
+ audio-routing =
+ "Mic Jack", "Mic Bias",
+ mux-int-port = <1>;
+ mux-ext-port = <4>;
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 4563b28..19d9b31 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -179,4 +179,16 @@ config SND_SOC_IMX_MC13783
select SND_SOC_MC13783
select SND_SOC_IMX_PCM_DMA
+config SND_SOC_IMX_WM8974
+ tristate "SoC Audio support for i.MX boards with WM8974"
+ depends on OF && SPI
+ select SND_SOC_IMX_AUDMUX
+ select SND_SOC_IMX_PCM_DMA
+ select SND_SOC_FSL_SSI
+ select SND_SOC_FSL_UTILS
+ select SND_SOC_WM8974
+ help
+ Say Y here if you want to add support for SoC audio on an i.MX board with
+ a wm8974 codec.
+
endif # SND_IMX_SOC
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 5f3cf3f..1a8ac3d 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -42,6 +42,7 @@ snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
snd-soc-wm1133-ev1-objs := wm1133-ev1.o
snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
snd-soc-imx-mc13783-objs := imx-mc13783.o
+snd-soc-imx-wm8974-objs := imx-wm8974.o
obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
@@ -49,3 +50,4 @@ obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
obj-$(CONFIG_SND_SOC_IMX_MC13783) += snd-soc-imx-mc13783.o
+obj-$(CONFIG_SND_SOC_IMX_WM8974) += snd-soc-imx-wm8974.o
diff --git a/sound/soc/fsl/imx-wm8974.c b/sound/soc/fsl/imx-wm8974.c
new file mode 100644
index 0000000..02b239d
--- /dev/null
+++ b/sound/soc/fsl/imx-wm8974.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright (C) 2012 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ * Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <sound/soc.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/spi/spi.h>
+#include <linux/clk.h>
+
+#include "imx-audmux.h"
+#include "../codecs/wm8974.h"
+
+#define DRIVER_NAME "imx-wm8974"
+
+#define DAI_NAME_SIZE 32
+
+struct imx_wm8974_data {
+ struct snd_soc_dai_link dai;
+ struct snd_soc_card card;
+ char codec_dai_name[DAI_NAME_SIZE];
+ char platform_name[DAI_NAME_SIZE];
+ struct clk *codec_clk;
+ unsigned int clk_frequency;
+};
+
+static int imx_wm8974_dai_init(struct snd_soc_pcm_runtime *rtd)
+{
+ struct imx_wm8974_data *data = container_of(rtd->card,
+ struct imx_wm8974_data, card);
+ struct device *dev = rtd->card->dev;
+ int ret;
+
+ /* the pll stability peaks at N=8 and around 90MHz.
+ * This values are best reached with a 12.288MHz or
+ * 11.289MHz clock. As the first is closer to N=8 in
+ * more situations, chose 12.288MHz as the target clock
+ * (ref: datasheet section "Master Clock and Phase Locked Loop")*/
+ ret = snd_soc_dai_set_pll(rtd->codec_dai, 0, 0, data->clk_frequency,
+ 12288000);
+ if (ret) {
+ dev_err(dev, "couldn't set pll: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget imx_wm8974_dapm_widgets[] = {
+ SND_SOC_DAPM_MIC("Mic Jack", NULL),
+ SND_SOC_DAPM_SPK("Ext Spk", NULL),
+};
+
+static int __devinit imx_wm8974_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *ssi_np, *codec_np;
+ struct device_node *audmux_np;
+ struct platform_device *ssi_pdev;
+ struct spi_device *codec_pdev;
+ struct imx_wm8974_data *data;
+ int int_port, ext_port;
+ int ret;
+
+ ret = of_property_read_u32(np, "mux-int-port", &int_port);
+ if (ret) {
+ dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
+ return ret;
+ }
+ ret = of_property_read_u32(np, "mux-ext-port", &ext_port);
+ if (ret) {
+ dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
+ return ret;
+ }
+
+ /*
+ * The port numbering in the hardware manual starts at 1, while
+ * the audmux API expects it starts at 0.
+ */
+ int_port--;
+ ext_port--;
+
+ audmux_np = of_find_node_by_name(NULL, "audmux");
+ if (!audmux_np) {
+ dev_err(&pdev->dev, "audmux missing or invalid\n");
+ return ret;
+ }
+
+ if (of_device_is_compatible(audmux_np, "fsl,imx21-audmux")) {
+ ret = imx_audmux_v1_configure_port(int_port,
+ IMX_AUDMUX_V1_PCR_TFSDIR |
+ IMX_AUDMUX_V1_PCR_TCLKDIR |
+ IMX_AUDMUX_V1_PCR_TFCSEL(ext_port) |
+ IMX_AUDMUX_V1_PCR_RXDSEL(ext_port) |
+ IMX_AUDMUX_V1_PCR_SYN);
+ if (ret) {
+ dev_err(&pdev->dev, "audmux internal port setup failed\n");
+ return ret;
+ }
+ ret = imx_audmux_v1_configure_port(ext_port,
+ IMX_AUDMUX_V1_PCR_RXDSEL(int_port) |
+ IMX_AUDMUX_V1_PCR_SYN);
+ if (ret) {
+ dev_err(&pdev->dev, "audmux external port setup failed\n");
+ return ret;
+ }
+ } else {
+ dev_err(&pdev->dev, "audmux not compatible\n");
+ }
+ of_node_put(audmux_np);
+
+ ssi_np = of_parse_phandle(np, "ssi-controller", 0);
+ codec_np = of_parse_phandle(np, "audio-codec", 0);
+ if (!ssi_np || !codec_np) {
+ dev_err(&pdev->dev, "phandle missing or invalid\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ ssi_pdev = of_find_device_by_node(ssi_np);
+ if (!ssi_pdev) {
+ dev_err(&pdev->dev, "failed to find SSI platform device\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ codec_pdev = of_find_spi_device_by_node(codec_np);
+ if (!codec_pdev) {
+ dev_err(&pdev->dev, "failed to find codec platform device\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ data->codec_clk = clk_get(&codec_pdev->dev, NULL);
+ if (IS_ERR(data->codec_clk)) {
+ data->codec_clk = NULL;
+ ret = of_property_read_u32(codec_np, "clock-frequency",
+ &data->clk_frequency);
+ if (ret) {
+ dev_err(&codec_pdev->dev,
+ "clock-frequency missing or invalid\n");
+ goto fail;
+ }
+ } else {
+ data->clk_frequency = clk_get_rate(data->codec_clk);
+ clk_prepare_enable(data->codec_clk);
+ }
+
+ data->dai.name = "HiFi";
+ data->dai.stream_name = "HiFi";
+ data->dai.codec_dai_name = "wm8974-hifi";
+ data->dai.codec_of_node = codec_np;
+ data->dai.cpu_dai_name = dev_name(&ssi_pdev->dev);
+ data->dai.platform_name = "imx-pcm-audio";
+ data->dai.init = &imx_wm8974_dai_init;
+ data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBM_CFM;
+
+ data->card.dev = &pdev->dev;
+ ret = snd_soc_of_parse_card_name(&data->card, "model");
+ if (ret)
+ goto clk_fail;
+ ret = snd_soc_of_parse_audio_routing(&data->card, "audio-routing");
+ if (ret)
+ goto clk_fail;
+
+ data->card.name = "wm8974-hifi";
+ data->card.num_links = 1;
+ data->card.dai_link = &data->dai;
+ data->card.dapm_widgets = imx_wm8974_dapm_widgets;
+ data->card.num_dapm_widgets = ARRAY_SIZE(imx_wm8974_dapm_widgets);
+
+ ret = snd_soc_register_card(&data->card);
+ if (ret) {
+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+ goto clk_fail;
+ }
+
+ platform_set_drvdata(pdev, data);
+
+clk_fail:
+ clk_put(data->codec_clk);
+fail:
+ if (ssi_np)
+ of_node_put(ssi_np);
+ if (codec_np)
+ of_node_put(codec_np);
+ if (codec_pdev)
+ spi_dev_put(codec_pdev);
+ return ret;
+}
+
+static int __devexit imx_wm8974_remove(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = platform_get_drvdata(pdev);
+
+ snd_soc_unregister_card(card);
+
+ return 0;
+}
+
+static const struct of_device_id imx_wm8974_of_match[] __devinitconst = {
+ { .compatible = "fsl,imx-audio-wm8974", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_wm8974_of_match);
+
+static struct platform_driver imx_wm8974_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = imx_wm8974_of_match,
+ },
+ .probe = imx_wm8974_probe,
+ .remove = __devexit_p(imx_wm8974_remove),
+};
+module_platform_driver(imx_wm8974_driver);
+
+MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
+MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
1.7.10.4
^ permalink raw reply related
* [PATCH 5/6] ARM i.MX: rename ssi1 clock for imx27
From: Steffen Trumtrar @ 2012-11-09 14:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352469625-32024-1-git-send-email-s.trumtrar@pengutronix.de>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/mach-imx/clk-imx27.c | 2 +-
arch/arm/mach-imx/imx27-dt.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 366e5d5..d269532 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -236,7 +236,7 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
- clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
+ clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "10010000.ssi");
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0");
clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index e80d523..60eed17 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -29,6 +29,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
OF_DEV_AUXDATA("fsl,imx27-nand", MX27_NFC_BASE_ADDR, "mxc_nand.0", NULL),
+ OF_DEV_AUXDATA("fsl,imx21-ssi", MX27_SSI1_BASE_ADDR, "10010000.ssi", NULL),
{ /* sentinel */ }
};
--
1.7.10.4
^ permalink raw reply related
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