* [PATCH v4 3/9] pinctrl: single: support pinconf generic
From: Tony Lindgren @ 2012-11-09 21:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-4-git-send-email-haojian.zhuang@gmail.com>
Hi Haojian,
One more comment on this one..
* Haojian Zhuang <haojian.zhuang@gmail.com> [121107 07:21]:
> --- a/drivers/pinctrl/pinctrl-single.c
> +++ b/drivers/pinctrl/pinctrl-single.c
> @@ -1009,6 +1186,46 @@ static int __devinit pcs_probe(struct platform_device *pdev)
> pcs->bits_per_mux = of_property_read_bool(np,
> "pinctrl-single,bit-per-mux");
>
> + if (conf->nconfs) {
> + pcs_pinconf_ops.is_generic = true;
> + ret = of_property_read_u32(np,
> + "pinctrl-single,power-source-mask",
> + &pcs->psmask);
> + if (ret) {
> + pcs->psmask = PCS_OFF_DISABLED;
> + pcs->psshift = PCS_OFF_DISABLED;
> + } else
> + pcs->psshift = ffs(pcs->psmask) - 1;
> + ret = of_property_read_u32(np,
> + "pinctrl-single,bias-mask", &pcs->bmask);
> + if (ret) {
> + pcs->bmask = PCS_OFF_DISABLED;
> + pcs->bshift = PCS_OFF_DISABLED;
> + } else
> + pcs->bshift = ffs(pcs->bmask) - 1;
> + ret = of_property_read_u32(np,
> + "pinctrl-single,bias-disable", &pcs->bdis);
> + if (ret)
> + pcs->bdis = PCS_OFF_DISABLED;
> + ret = of_property_read_u32(np,
> + "pinctrl-single,bias-pull-up", &pcs->bpullup);
> + if (ret)
> + pcs->bpullup = PCS_OFF_DISABLED;
> + ret = of_property_read_u32(np,
> + "pinctrl-single,bias-pull-down",
> + &pcs->bpulldown);
> + if (ret)
> + pcs->bpulldown = PCS_OFF_DISABLED;
> + ret = of_property_read_u32(np,
> + "pinctrl-single,input-schmitt-mask",
> + &pcs->ismask);
> + if (ret) {
> + pcs->ismask = PCS_OFF_DISABLED;
> + pcs->isshift = PCS_OFF_DISABLED;
> + } else
> + pcs->isshift = ffs(pcs->ismask) - 1;
> + }
> +
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> if (!res) {
> dev_err(pcs->dev, "could not get resource\n");
I tried to make pinconf work with the omap CONTROL_PBIASLITE
register, but noticed that we need to change the binding to make
pinctrl-single,bits type controllers work.
Basically we need to move the pinconf properties to be defined
under pinctrl-single,pins and pinctrl-single,bits rather than being
pinmux controller instance specific properties.
In the pinctrl-single,bits case we have multiple pinconf masks
for a single register, like in the omap CONTROL_PBIASLITE example
we discussed earlier.
Then let's just have a single pinctrl driver instance specific
property pinctrl-single,pinconf that we can use to optimize out
the pinconf parsing for ranges that don't support pinconf.
Other than that, I think I'm finally done with my comments for
this patch, sorry it took so long and took so many emails.
Regards,
Tony
^ permalink raw reply
* [PATCH net-next 1/2] ARM: net: bpf_jit_32: add XOR instruction for BPF JIT
From: David Miller @ 2012-11-09 21:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121108012828.GA23143@thinkbox>
From: Daniel Borkmann <dxchgb@gmail.com>
Date: Thu, 8 Nov 2012 02:28:28 +0100
> This patch is a follow-up for patch "filter: add XOR instruction for use
> with X/K" that implements BPF ARM JIT parts for the BPF XOR operation.
>
> Signed-off-by: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
> Cc: Mircea Gherzan <mgherzan@gmail.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
Could an ARM person please review and ACK these two patches so that
I can toss them into net-next (where the dependency is)?
Thanks!
^ permalink raw reply
* [PATCH 15/26] ARM: omap2: clock: Add 24xx data using common struct clk
From: Paul Walmsley @ 2012-11-09 21:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109210543.17381.15878@nucleus>
On Fri, 9 Nov 2012, Mike Turquette wrote:
> Quoting Paul Walmsley (2012-11-09 12:32:59)
> > Here's another update on this one to add the twl.fck clock alias, recently
> > added by commit defa6be1c8216ed2d52d65db81a8a148e73be5f7 ("mfd: Fix
> > compile for twl-core.c by removing cpu_is_omap usage").
> >
>
> I'll post a new series to the list with these fixes rolled in.
Unless you've got other changes, no need to worry about it - will deal
with it here.
> Do you want me to squash the clkdm_clk_disable/usecount patch into
> another patch in the series or keep it separate? Separate might be good
> since we're going to replace that solution with some force-disable thing
> in the future.
Have moved that one up earlier in the patch stack and added the matching
cleanup to the last patch. Will repush the branch once it completes
testing again.
Re the upstream CCF support for this, would suggest adding the CCF support
for the new function pointer in this merge window (3.8) since it should
be relatively straightforward. Then during the 3.9 merge window, the
OMAP code can be switched over to use it.
- Paul
^ permalink raw reply
* [PATCH] ARM: add get_user() support for 8 byte types
From: Rob Clark @ 2012-11-09 21:17 UTC (permalink / raw)
To: linux-arm-kernel
From: Rob Clark <rob@ti.com>
A new atomic modeset/pageflip ioctl being developed in DRM requires
get_user() to work for 64bit types (in addition to just put_user()).
Signed-off-by: Rob Clark <rob@ti.com>
---
arch/arm/include/asm/uaccess.h | 25 ++++++++++++++++++++-----
arch/arm/lib/getuser.S | 17 ++++++++++++++++-
2 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 7e1f760..2e3fdb2 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -100,6 +100,7 @@ static inline void set_fs(mm_segment_t fs)
extern int __get_user_1(void *);
extern int __get_user_2(void *);
extern int __get_user_4(void *);
+extern int __get_user_8(void *);
#define __GUP_CLOBBER_1 "lr", "cc"
#ifdef CONFIG_CPU_USE_DOMAINS
@@ -108,6 +109,7 @@ extern int __get_user_4(void *);
#define __GUP_CLOBBER_2 "lr", "cc"
#endif
#define __GUP_CLOBBER_4 "lr", "cc"
+#define __GUP_CLOBBER_8 "lr", "cc"
#define __get_user_x(__r2,__p,__e,__l,__s) \
__asm__ __volatile__ ( \
@@ -122,22 +124,35 @@ extern int __get_user_4(void *);
({ \
unsigned long __limit = current_thread_info()->addr_limit - 1; \
register const typeof(*(p)) __user *__p asm("r0") = (p);\
- register unsigned long __r2 asm("r2"); \
register unsigned long __l asm("r1") = __limit; \
register int __e asm("r0"); \
switch (sizeof(*(__p))) { \
- case 1: \
+ case 1: { \
+ register unsigned long __r2 asm("r2"); \
__get_user_x(__r2, __p, __e, __l, 1); \
+ x = (typeof(*(p))) __r2; \
break; \
- case 2: \
+ } \
+ case 2: { \
+ register unsigned long __r2 asm("r2"); \
__get_user_x(__r2, __p, __e, __l, 2); \
+ x = (typeof(*(p))) __r2; \
break; \
- case 4: \
+ } \
+ case 4: { \
+ register unsigned long __r2 asm("r2"); \
__get_user_x(__r2, __p, __e, __l, 4); \
+ x = (typeof(*(p))) __r2; \
+ break; \
+ } \
+ case 8: { \
+ register unsigned long long __r2 asm("r2"); \
+ __get_user_x(__r2, __p, __e, __l, 8); \
+ x = (typeof(*(p))) __r2; \
break; \
+ } \
default: __e = __get_user_bad(); break; \
} \
- x = (typeof(*(p))) __r2; \
__e; \
})
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index 9b06bb4..d05285c 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -18,7 +18,7 @@
* Inputs: r0 contains the address
* r1 contains the address limit, which must be preserved
* Outputs: r0 is the error code
- * r2 contains the zero-extended value
+ * r2, r3 contains the zero-extended value
* lr corrupted
*
* No other registers must be altered. (see <asm/uaccess.h>
@@ -66,6 +66,19 @@ ENTRY(__get_user_4)
mov pc, lr
ENDPROC(__get_user_4)
+ENTRY(__get_user_8)
+ check_uaccess r0, 4, r1, r2, __get_user_bad
+#ifdef CONFIG_THUMB2_KERNEL
+5: TUSER(ldr) r2, [r0]
+6: TUSER(ldr) r3, [r0, #4]
+#else
+5: TUSER(ldr) r2, [r0], #4
+6: TUSER(ldr) r3, [r0]
+#endif
+ mov r0, #0
+ mov pc, lr
+ENDPROC(__get_user_8)
+
__get_user_bad:
mov r2, #0
mov r0, #-EFAULT
@@ -77,4 +90,6 @@ ENDPROC(__get_user_bad)
.long 2b, __get_user_bad
.long 3b, __get_user_bad
.long 4b, __get_user_bad
+ .long 5b, __get_user_bad
+ .long 6b, __get_user_bad
.popsection
--
1.8.0
^ permalink raw reply related
* [PATCH v2 00/26] Move OMAP2+ over to common clk framework
From: Paul Walmsley @ 2012-11-09 21:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352337181-29427-1-git-send-email-mturquette@ti.com>
Hi
With the fixes that have been posted, this is testing clean here. Mike
and Rajendra have put in months of work on these patches under
often-difficult conditions, and it's really great that we've arrived at
this point with zero obvious remaining regressions from the current code.
The branch has been posted for the time being at
git://git.pwsan.com/linux-2.6 in the branch 'common_clk_devel_3.8', with
the head at commit 376676b429cb6dc95c39cdac82b2be816ea22893, in case
anyone else wants to try it.
Anyway, barring any further regressions that haven't reared their ugly
heads yet, and barring anything truly horrible in the code or data that
I've missed so far, will take this branch from here. It still needs some
more work before it's ready to merge. The clockdomain usecounting fix
patch needs to be split and moved earlier in the patch stack so 'git
bisect' doesn't result in warnings and broken PM on OMAP3. And it all is
going to be rebased on the second set of PRCM cleanup patches at commit
b99db36cdf37decb1b5575c5f293d170cbbc53d6, which I'm assuming Tony is
planning to pull. Then will plan to send that pull request to Tony.
Then after that, if there's still time to merge some of the clock changes
that have showed up on the lists for 3.8, those will get stacked onto a
topic branch based on the branch that's sent to Tony.
- Paul
^ permalink raw reply
* [PATCH] ARM: OMAP2+: Prevent redefinition errors for soc.h
From: Tony Lindgren @ 2012-11-09 21:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509D2F77.6090702@ti.com>
* Jon Hunter <jon-hunter@ti.com> [121109 08:31]:
>
> On 11/09/2012 10:22 AM, Tony Lindgren wrote:
> > * Jon Hunter <jon-hunter@ti.com> [121109 08:21]:
> >> If the header soc.h is included more than once in a source (for example
> >> once directly by the source file and once indirectly by another header
> >> file), then the compiler will generate redefintion errors for the macros
> >> in soc.h. Prevent this by only allowing the content in soc.h to be
> >> included once.
> >>
> >> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
> >> ---
> >>
> >> Please note that I ran into this problem when rebasing my dmtimer fixes
> >> series [1] on Tony's Linux-OMAP master branch. I am including plat/cpu.h
> >> in dmtimer.h and I found several other files including dmtimer.h are also
> >> including soc.h and so generate a lot of errors.
> >>
> >> [1] http://marc.info/?l=linux-omap&m=135231490218361&w=2
> >
> > As these headers are private to mach-omap2, I'd rather not allow including
> > them more than once so we can eventually clean up the includes further.
> >
> > We should include the headers directly where used, except for the
> > legacy board-*.c files that will be going away anyways.
> >
> > Including the files directly should fix this easily, if not let me
> > know.
>
> The alternative fix is to ensure anyone including dmtimer.h also
> includes soc.h. However, I did not know if we should have such a
> dependency. If you are ok with that then that is what I will do for now.
> It is not a massive change.
Do you mean anything under mach-omap2/*.c including dmtimer.h also
needs to also include soc.h? If sounds OK to me as long as we don't
need to include soc.h outside mach-omap2.
Regards,
Tony
^ permalink raw reply
* [PATCH 04/11] ARM: set arch_gettimeoffset directly
From: Stephen Warren @ 2012-11-09 21:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509C3AE7.7030703@gmail.com>
On 11/08/2012 04:06 PM, Ryan Mallon wrote:
> On 09/11/12 08:01, Stephen Warren wrote:
>> remove ARM's struct sys_timer .offset function pointer, and instead
>> directly set the arch_gettimeoffset function pointer when the timer
>> driver is initialized. This requires multiplying all function results
>> by 1000, since the removed arm_gettimeoffset() did this. Also,
>> s/unsigned long/u32/ just to make the function prototypes exactly
>> match that of arch_gettimeoffset.
>> +static u32 ep93xx_gettimeoffset(void)
>> +{
>> + int offset;
>> +
>> + offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
>> +
>> + /* Calculate (1000000 / 983040) * offset. */
>
> This comment is now incorrect, it should say:
>
> /* Calculate (1000000000 / 983040) * offset */
>
> or perhaps to better explain what is being done:
>
> /*
> * Timer 4 is based on a 983.04 kHz reference clock,
> * so dividing by 983040 gives a milli-second value.
> * Refactor the calculation to avoid overflow.
> */
>
>> + return (offset + (53 * offset / 3072)) * 1000;
Thanks. I expanded on that slightly and went for:
/*
* Timer 4 is based on a 983.04 kHz reference clock,
* so dividing by 983040 gives the fraction of a second,
* so dividing by 0.983040 converts to uS.
* Refactor the calculation to avoid overflow.
* Finally, multiply by 1000 to give nS.
*/
^ permalink raw reply
* [PATCH 15/26] ARM: omap2: clock: Add 24xx data using common struct clk
From: Mike Turquette @ 2012-11-09 21:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1211092030360.20703@utopia.booyaka.com>
Quoting Paul Walmsley (2012-11-09 12:32:59)
> Here's another update on this one to add the twl.fck clock alias, recently
> added by commit defa6be1c8216ed2d52d65db81a8a148e73be5f7 ("mfd: Fix
> compile for twl-core.c by removing cpu_is_omap usage").
>
I'll post a new series to the list with these fixes rolled in. Do you
want me to squash the clkdm_clk_disable/usecount patch into another
patch in the series or keep it separate? Separate might be good since
we're going to replace that solution with some force-disable thing in
the future.
Regards,
Mike
>
> - Paul
>
> From: Rajendra Nayak <rnayak@ti.com>
> Date: Wed, 7 Nov 2012 21:09:35 -0700
> Subject: [PATCH] ARM: OMAP2: clock: Add 24xx data using common struct clk
>
> The patch is the output from a python script which converts
> from the old OMAP clk format to COMMON clk format using a
> JSON parser in between which was developed by Paul Walmsley.
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> [paul at pwsan.com: replace omap2_init_clksel_parent() with
> omap2_clksel_find_parent_index(); reflowed macros; dropped 243x clkdev
> aliases in 242x file; added recalc_rate fn ptrs to APLL clocks;
> fixed some checkpatch warnings]
> [mturquette at ti.com: removed deprecated variables from omap24x0_clk_init]
> Signed-off-by: Mike Turquette <mturquette@ti.com>
> [paul at pwsan.com: fixed boot crash due to missing clock init code; added twl.fck
> alias]
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
> arch/arm/mach-omap2/cclock2420_data.c | 1962 ++++++++++++++++++++++++++++++
> arch/arm/mach-omap2/cclock2430_data.c | 2076 ++++++++++++++++++++++++++++++++
> arch/arm/mach-omap2/cm-regbits-24xx.h | 5 +
> arch/arm/mach-omap2/prm-regbits-24xx.h | 2 +
> 4 files changed, 4045 insertions(+)
> create mode 100644 arch/arm/mach-omap2/cclock2420_data.c
> create mode 100644 arch/arm/mach-omap2/cclock2430_data.c
>
> diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
> new file mode 100644
> index 0000000..f1ee478
> --- /dev/null
> +++ b/arch/arm/mach-omap2/cclock2420_data.c
> @@ -0,0 +1,1962 @@
> +/*
> + * OMAP2420 clock data
> + *
> + * Copyright (C) 2005-2012 Texas Instruments, Inc.
> + * Copyright (C) 2004-2011 Nokia Corporation
> + *
> + * Contacts:
> + * Richard Woodruff <r-woodruff2@ti.com>
> + * Paul Walmsley
> + * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/io.h>
> +#include <linux/clk.h>
> +#include <linux/clk-private.h>
> +#include <linux/list.h>
> +
> +#include "soc.h"
> +#include "iomap.h"
> +#include "clock.h"
> +#include "clock2xxx.h"
> +#include "opp2xxx.h"
> +#include "cm2xxx.h"
> +#include "prm2xxx.h"
> +#include "prm-regbits-24xx.h"
> +#include "cm-regbits-24xx.h"
> +#include "sdrc.h"
> +#include "control.h"
> +
> +#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
> +
> +/*
> + * 2420 clock tree.
> + *
> + * NOTE:In many cases here we are assigning a 'default' parent. In
> + * many cases the parent is selectable. The set parent calls will
> + * also switch sources.
> + *
> + * Several sources are given initial rates which may be wrong, this will
> + * be fixed up in the init func.
> + *
> + * Things are broadly separated below by clock domains. It is
> + * noteworthy that most peripherals have dependencies on multiple clock
> + * domains. Many get their interface clocks from the L4 domain, but get
> + * functional clocks from fixed sources or other core domain derived
> + * clocks.
> + */
> +
> +DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
> +
> +DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
> +
> +DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
> +
> +static struct clk osc_ck;
> +
> +static const struct clk_ops osc_ck_ops = {
> + .recalc_rate = &omap2_osc_clk_recalc,
> +};
> +
> +static struct clk_hw_omap osc_ck_hw = {
> + .hw = {
> + .clk = &osc_ck,
> + },
> +};
> +
> +static struct clk osc_ck = {
> + .name = "osc_ck",
> + .ops = &osc_ck_ops,
> + .hw = &osc_ck_hw.hw,
> + .flags = CLK_IS_ROOT,
> +};
> +
> +DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
> +
> +static struct clk sys_ck;
> +
> +static const char *sys_ck_parent_names[] = {
> + "osc_ck",
> +};
> +
> +static const struct clk_ops sys_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .recalc_rate = &omap2xxx_sys_clk_recalc,
> +};
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
> +DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
> +
> +static struct dpll_data dpll_dd = {
> + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
> + .mult_mask = OMAP24XX_DPLL_MULT_MASK,
> + .div1_mask = OMAP24XX_DPLL_DIV_MASK,
> + .clk_bypass = &sys_ck,
> + .clk_ref = &sys_ck,
> + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
> + .enable_mask = OMAP24XX_EN_DPLL_MASK,
> + .max_multiplier = 1023,
> + .min_divider = 1,
> + .max_divider = 16,
> +};
> +
> +static struct clk dpll_ck;
> +
> +static const char *dpll_ck_parent_names[] = {
> + "sys_ck",
> +};
> +
> +static const struct clk_ops dpll_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .get_parent = &omap2_init_dpll_parent,
> + .recalc_rate = &omap2_dpllcore_recalc,
> + .round_rate = &omap2_dpll_round_rate,
> + .set_rate = &omap2_reprogram_dpllcore,
> +};
> +
> +static struct clk_hw_omap dpll_ck_hw = {
> + .hw = {
> + .clk = &dpll_ck,
> + },
> + .ops = &clkhwops_omap2xxx_dpll,
> + .dpll_data = &dpll_dd,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
> +
> +static struct clk core_ck;
> +
> +static const char *core_ck_parent_names[] = {
> + "dpll_ck",
> +};
> +
> +static const struct clk_ops core_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> +};
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
> +DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
> +
> +DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
> + CLK_DIVIDER_ONE_BASED, NULL);
> +
> +DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
> + CLK_DIVIDER_ONE_BASED, NULL);
> +
> +static struct clk aes_ick;
> +
> +static const char *aes_ick_parent_names[] = {
> + "l4_ck",
> +};
> +
> +static const struct clk_ops aes_ick_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_dflt_clk_enable,
> + .disable = &omap2_dflt_clk_disable,
> + .is_enabled = &omap2_dflt_clk_is_enabled,
> +};
> +
> +static struct clk_hw_omap aes_ick_hw = {
> + .hw = {
> + .clk = &aes_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
> + .enable_bit = OMAP24XX_EN_AES_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk apll54_ck;
> +
> +static const struct clk_ops apll54_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_clk_apll54_enable,
> + .disable = &omap2_clk_apll_disable,
> + .recalc_rate = &omap2_clk_apll54_recalc,
> +};
> +
> +static struct clk_hw_omap apll54_ck_hw = {
> + .hw = {
> + .clk = &apll54_ck,
> + },
> + .ops = &clkhwops_apll54,
> + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
> + .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
> + .flags = ENABLE_ON_INIT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
> +
> +static struct clk apll96_ck;
> +
> +static const struct clk_ops apll96_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_clk_apll96_enable,
> + .disable = &omap2_clk_apll_disable,
> + .recalc_rate = &omap2_clk_apll96_recalc,
> +};
> +
> +static struct clk_hw_omap apll96_ck_hw = {
> + .hw = {
> + .clk = &apll96_ck,
> + },
> + .ops = &clkhwops_apll96,
> + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
> + .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
> + .flags = ENABLE_ON_INIT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
> +
> +static struct clk func_96m_ck;
> +
> +static const char *func_96m_ck_parent_names[] = {
> + "apll96_ck",
> +};
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm");
> +DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops);
> +
> +static struct clk cam_fck;
> +
> +static const char *cam_fck_parent_names[] = {
> + "func_96m_ck",
> +};
> +
> +static struct clk_hw_omap cam_fck_hw = {
> + .hw = {
> + .clk = &cam_fck,
> + },
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_CAM_SHIFT,
> + .clkdm_name = "core_l3_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
> +
> +static struct clk cam_ick;
> +
> +static struct clk_hw_omap cam_ick_hw = {
> + .hw = {
> + .clk = &cam_ick,
> + },
> + .ops = &clkhwops_iclk,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_CAM_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk des_ick;
> +
> +static struct clk_hw_omap des_ick_hw = {
> + .hw = {
> + .clk = &des_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
> + .enable_bit = OMAP24XX_EN_DES_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static const struct clksel_rate dsp_fck_core_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 2, .val = 2, .flags = RATE_IN_24XX },
> + { .div = 3, .val = 3, .flags = RATE_IN_24XX },
> + { .div = 4, .val = 4, .flags = RATE_IN_24XX },
> + { .div = 6, .val = 6, .flags = RATE_IN_242X },
> + { .div = 8, .val = 8, .flags = RATE_IN_242X },
> + { .div = 12, .val = 12, .flags = RATE_IN_242X },
> + { .div = 0 }
> +};
> +
> +static const struct clksel dsp_fck_clksel[] = {
> + { .parent = &core_ck, .rates = dsp_fck_core_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *dsp_fck_parent_names[] = {
> + "core_ck",
> +};
> +
> +static const struct clk_ops dsp_fck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_dflt_clk_enable,
> + .disable = &omap2_dflt_clk_disable,
> + .is_enabled = &omap2_dflt_clk_is_enabled,
> + .recalc_rate = &omap2_clksel_recalc,
> + .set_rate = &omap2_clksel_set_rate,
> + .round_rate = &omap2_clksel_round_rate,
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
> + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
> + OMAP24XX_CLKSEL_DSP_MASK,
> + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
> + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
> + dsp_fck_parent_names, dsp_fck_ops);
> +
> +static const struct clksel dsp_ick_clksel[] = {
> + { .parent = &dsp_fck, .rates = dsp_ick_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *dsp_ick_parent_names[] = {
> + "dsp_fck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel,
> + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
> + OMAP24XX_CLKSEL_DSP_IF_MASK,
> + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
> + OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait,
> + dsp_ick_parent_names, dsp_fck_ops);
> +
> +static const struct clksel_rate dss1_fck_sys_rates[] = {
> + { .div = 1, .val = 0, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate dss1_fck_core_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 2, .val = 2, .flags = RATE_IN_24XX },
> + { .div = 3, .val = 3, .flags = RATE_IN_24XX },
> + { .div = 4, .val = 4, .flags = RATE_IN_24XX },
> + { .div = 5, .val = 5, .flags = RATE_IN_24XX },
> + { .div = 6, .val = 6, .flags = RATE_IN_24XX },
> + { .div = 8, .val = 8, .flags = RATE_IN_24XX },
> + { .div = 9, .val = 9, .flags = RATE_IN_24XX },
> + { .div = 12, .val = 12, .flags = RATE_IN_24XX },
> + { .div = 16, .val = 16, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel dss1_fck_clksel[] = {
> + { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
> + { .parent = &core_ck, .rates = dss1_fck_core_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *dss1_fck_parent_names[] = {
> + "sys_ck", "core_ck",
> +};
> +
> +static struct clk dss1_fck;
> +
> +static const struct clk_ops dss1_fck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_dflt_clk_enable,
> + .disable = &omap2_dflt_clk_disable,
> + .is_enabled = &omap2_dflt_clk_is_enabled,
> + .recalc_rate = &omap2_clksel_recalc,
> + .get_parent = &omap2_clksel_find_parent_index,
> + .set_parent = &omap2_clksel_set_parent,
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_DSS1_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_DSS1_SHIFT, NULL,
> + dss1_fck_parent_names, dss1_fck_ops);
> +
> +static const struct clksel_rate dss2_fck_sys_rates[] = {
> + { .div = 1, .val = 0, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate dss2_fck_48m_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate func_48m_apll96_rates[] = {
> + { .div = 2, .val = 0, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate func_48m_alt_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel func_48m_clksel[] = {
> + { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
> + { .parent = &alt_ck, .rates = func_48m_alt_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *func_48m_ck_parent_names[] = {
> + "apll96_ck", "alt_ck",
> +};
> +
> +static struct clk func_48m_ck;
> +
> +static const struct clk_ops func_48m_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .recalc_rate = &omap2_clksel_recalc,
> + .set_rate = &omap2_clksel_set_rate,
> + .round_rate = &omap2_clksel_round_rate,
> + .get_parent = &omap2_clksel_find_parent_index,
> + .set_parent = &omap2_clksel_set_parent,
> +};
> +
> +static struct clk_hw_omap func_48m_ck_hw = {
> + .hw = {
> + .clk = &func_48m_ck,
> + },
> + .clksel = func_48m_clksel,
> + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
> + .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
> +
> +static const struct clksel dss2_fck_clksel[] = {
> + { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
> + { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *dss2_fck_parent_names[] = {
> + "sys_ck", "func_48m_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_DSS2_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_DSS2_SHIFT, NULL,
> + dss2_fck_parent_names, dss1_fck_ops);
> +
> +static const char *func_54m_ck_parent_names[] = {
> + "apll54_ck", "alt_ck",
> +};
> +
> +DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
> + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
> + OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH,
> + 0x0, NULL);
> +
> +static struct clk dss_54m_fck;
> +
> +static const char *dss_54m_fck_parent_names[] = {
> + "func_54m_ck",
> +};
> +
> +static struct clk_hw_omap dss_54m_fck_hw = {
> + .hw = {
> + .clk = &dss_54m_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_TV_SHIFT,
> + .clkdm_name = "dss_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
> +
> +static struct clk dss_ick;
> +
> +static struct clk_hw_omap dss_ick_hw = {
> + .hw = {
> + .clk = &dss_ick,
> + },
> + .ops = &clkhwops_iclk,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
> + .clkdm_name = "dss_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk eac_fck;
> +
> +static struct clk_hw_omap eac_fck_hw = {
> + .hw = {
> + .clk = &eac_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP2420_EN_EAC_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops);
> +
> +static struct clk eac_ick;
> +
> +static struct clk_hw_omap eac_ick_hw = {
> + .hw = {
> + .clk = &eac_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP2420_EN_EAC_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk emul_ck;
> +
> +static struct clk_hw_omap emul_ck_hw = {
> + .hw = {
> + .clk = &emul_ck,
> + },
> + .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
> + .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
> +
> +static struct clk fac_fck;
> +
> +static const char *fac_fck_parent_names[] = {
> + "func_12m_ck",
> +};
> +
> +static struct clk_hw_omap fac_fck_hw = {
> + .hw = {
> + .clk = &fac_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_FAC_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
> +
> +static struct clk fac_ick;
> +
> +static struct clk_hw_omap fac_ick_hw = {
> + .hw = {
> + .clk = &fac_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_FAC_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static const struct clksel gfx_fck_clksel[] = {
> + { .parent = &core_l3_ck, .rates = gfx_l3_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *gfx_2d_fck_parent_names[] = {
> + "core_l3_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
> + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
> + OMAP_CLKSEL_GFX_MASK,
> + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
> + OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
> + gfx_2d_fck_parent_names, dsp_fck_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
> + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
> + OMAP_CLKSEL_GFX_MASK,
> + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
> + OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
> + gfx_2d_fck_parent_names, dsp_fck_ops);
> +
> +static struct clk gfx_ick;
> +
> +static const char *gfx_ick_parent_names[] = {
> + "core_l3_ck",
> +};
> +
> +static struct clk_hw_omap gfx_ick_hw = {
> + .hw = {
> + .clk = &gfx_ick,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
> + .enable_bit = OMAP_EN_GFX_SHIFT,
> + .clkdm_name = "gfx_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
> +
> +static struct clk gpios_fck;
> +
> +static const char *gpios_fck_parent_names[] = {
> + "func_32k_ck",
> +};
> +
> +static struct clk_hw_omap gpios_fck_hw = {
> + .hw = {
> + .clk = &gpios_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
> + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
> +
> +static struct clk wu_l4_ick;
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
> +DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
> +
> +static struct clk gpios_ick;
> +
> +static const char *gpios_ick_parent_names[] = {
> + "wu_l4_ick",
> +};
> +
> +static struct clk_hw_omap gpios_ick_hw = {
> + .hw = {
> + .clk = &gpios_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +static struct clk gpmc_fck;
> +
> +static struct clk_hw_omap gpmc_fck_hw = {
> + .hw = {
> + .clk = &gpmc_fck,
> + },
> + .ops = &clkhwops_iclk,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
> + .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
> + .flags = ENABLE_ON_INIT,
> + .clkdm_name = "core_l3_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
> +
> +static const struct clksel_rate gpt_alt_rates[] = {
> + { .div = 1, .val = 2, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel omap24xx_gpt_clksel[] = {
> + { .parent = &func_32k_ck, .rates = gpt_32k_rates },
> + { .parent = &sys_ck, .rates = gpt_sys_rates },
> + { .parent = &alt_ck, .rates = gpt_alt_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *gpt10_fck_parent_names[] = {
> + "func_32k_ck", "sys_ck", "alt_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT10_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt10_ick;
> +
> +static struct clk_hw_omap gpt10_ick_hw = {
> + .hw = {
> + .clk = &gpt10_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT11_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt11_ick;
> +
> +static struct clk_hw_omap gpt11_ick_hw = {
> + .hw = {
> + .clk = &gpt11_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT12_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt12_ick;
> +
> +static struct clk_hw_omap gpt12_ick_hw = {
> + .hw = {
> + .clk = &gpt12_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static const struct clk_ops gpt1_fck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_dflt_clk_enable,
> + .disable = &omap2_dflt_clk_disable,
> + .is_enabled = &omap2_dflt_clk_is_enabled,
> + .recalc_rate = &omap2_clksel_recalc,
> + .set_rate = &omap2_clksel_set_rate,
> + .round_rate = &omap2_clksel_round_rate,
> + .get_parent = &omap2_clksel_find_parent_index,
> + .set_parent = &omap2_clksel_set_parent,
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_GPT1_MASK,
> + OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
> + OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, gpt1_fck_ops);
> +
> +static struct clk gpt1_ick;
> +
> +static struct clk_hw_omap gpt1_ick_hw = {
> + .hw = {
> + .clk = &gpt1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT2_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt2_ick;
> +
> +static struct clk_hw_omap gpt2_ick_hw = {
> + .hw = {
> + .clk = &gpt2_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT3_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt3_ick;
> +
> +static struct clk_hw_omap gpt3_ick_hw = {
> + .hw = {
> + .clk = &gpt3_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT4_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt4_ick;
> +
> +static struct clk_hw_omap gpt4_ick_hw = {
> + .hw = {
> + .clk = &gpt4_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT5_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt5_ick;
> +
> +static struct clk_hw_omap gpt5_ick_hw = {
> + .hw = {
> + .clk = &gpt5_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT6_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt6_ick;
> +
> +static struct clk_hw_omap gpt6_ick_hw = {
> + .hw = {
> + .clk = &gpt6_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT7_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt7_ick;
> +
> +static struct clk_hw_omap gpt7_ick_hw = {
> + .hw = {
> + .clk = &gpt7_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT8_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt8_ick;
> +
> +static struct clk_hw_omap gpt8_ick_hw = {
> + .hw = {
> + .clk = &gpt8_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT9_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt9_ick;
> +
> +static struct clk_hw_omap gpt9_ick_hw = {
> + .hw = {
> + .clk = &gpt9_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk hdq_fck;
> +
> +static struct clk_hw_omap hdq_fck_hw = {
> + .hw = {
> + .clk = &hdq_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
> +
> +static struct clk hdq_ick;
> +
> +static struct clk_hw_omap hdq_ick_hw = {
> + .hw = {
> + .clk = &hdq_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk i2c1_fck;
> +
> +static struct clk_hw_omap i2c1_fck_hw = {
> + .hw = {
> + .clk = &i2c1_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP2420_EN_I2C1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops);
> +
> +static struct clk i2c1_ick;
> +
> +static struct clk_hw_omap i2c1_ick_hw = {
> + .hw = {
> + .clk = &i2c1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP2420_EN_I2C1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk i2c2_fck;
> +
> +static struct clk_hw_omap i2c2_fck_hw = {
> + .hw = {
> + .clk = &i2c2_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP2420_EN_I2C2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops);
> +
> +static struct clk i2c2_ick;
> +
> +static struct clk_hw_omap i2c2_ick_hw = {
> + .hw = {
> + .clk = &i2c2_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP2420_EN_I2C2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,
> + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
> + OMAP2420_CLKSEL_IVA_MASK,
> + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
> + OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait,
> + dsp_fck_parent_names, dsp_fck_ops);
> +
> +static struct clk iva1_mpu_int_ifck;
> +
> +static const char *iva1_mpu_int_ifck_parent_names[] = {
> + "iva1_ifck",
> +};
> +
> +static const struct clk_ops iva1_mpu_int_ifck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_dflt_clk_enable,
> + .disable = &omap2_dflt_clk_disable,
> + .is_enabled = &omap2_dflt_clk_is_enabled,
> + .recalc_rate = &omap_fixed_divisor_recalc,
> +};
> +
> +static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
> + .hw = {
> + .clk = &iva1_mpu_int_ifck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
> + .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
> + .clkdm_name = "iva1_clkdm",
> + .fixed_div = 2,
> +};
> +
> +DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names,
> + iva1_mpu_int_ifck_ops);
> +
> +static struct clk mailboxes_ick;
> +
> +static struct clk_hw_omap mailboxes_ick_hw = {
> + .hw = {
> + .clk = &mailboxes_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static const struct clksel_rate common_mcbsp_96m_rates[] = {
> + { .div = 1, .val = 0, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel mcbsp_fck_clksel[] = {
> + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
> + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *mcbsp1_fck_parent_names[] = {
> + "func_96m_ck", "mcbsp_clks",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
> + OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
> + OMAP2_MCBSP1_CLKS_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
> + mcbsp1_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk mcbsp1_ick;
> +
> +static struct clk_hw_omap mcbsp1_ick_hw = {
> + .hw = {
> + .clk = &mcbsp1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
> + OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
> + OMAP2_MCBSP2_CLKS_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
> + mcbsp1_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk mcbsp2_ick;
> +
> +static struct clk_hw_omap mcbsp2_ick_hw = {
> + .hw = {
> + .clk = &mcbsp2_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk mcspi1_fck;
> +
> +static const char *mcspi1_fck_parent_names[] = {
> + "func_48m_ck",
> +};
> +
> +static struct clk_hw_omap mcspi1_fck_hw = {
> + .hw = {
> + .clk = &mcspi1_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mcspi1_ick;
> +
> +static struct clk_hw_omap mcspi1_ick_hw = {
> + .hw = {
> + .clk = &mcspi1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk mcspi2_fck;
> +
> +static struct clk_hw_omap mcspi2_fck_hw = {
> + .hw = {
> + .clk = &mcspi2_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mcspi2_ick;
> +
> +static struct clk_hw_omap mcspi2_ick_hw = {
> + .hw = {
> + .clk = &mcspi2_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk mmc_fck;
> +
> +static struct clk_hw_omap mmc_fck_hw = {
> + .hw = {
> + .clk = &mmc_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP2420_EN_MMC_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mmc_ick;
> +
> +static struct clk_hw_omap mmc_ick_hw = {
> + .hw = {
> + .clk = &mmc_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP2420_EN_MMC_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
> + OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
> + OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
> + CLK_DIVIDER_ONE_BASED, NULL);
> +
> +static struct clk mpu_wdt_fck;
> +
> +static struct clk_hw_omap mpu_wdt_fck_hw = {
> + .hw = {
> + .clk = &mpu_wdt_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
> + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mpu_wdt_ick;
> +
> +static struct clk_hw_omap mpu_wdt_ick_hw = {
> + .hw = {
> + .clk = &mpu_wdt_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +static struct clk mspro_fck;
> +
> +static struct clk_hw_omap mspro_fck_hw = {
> + .hw = {
> + .clk = &mspro_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mspro_ick;
> +
> +static struct clk_hw_omap mspro_ick_hw = {
> + .hw = {
> + .clk = &mspro_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk omapctrl_ick;
> +
> +static struct clk_hw_omap omapctrl_ick_hw = {
> + .hw = {
> + .clk = &omapctrl_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
> + .flags = ENABLE_ON_INIT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +static struct clk pka_ick;
> +
> +static struct clk_hw_omap pka_ick_hw = {
> + .hw = {
> + .clk = &pka_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
> + .enable_bit = OMAP24XX_EN_PKA_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk rng_ick;
> +
> +static struct clk_hw_omap rng_ick_hw = {
> + .hw = {
> + .clk = &rng_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
> + .enable_bit = OMAP24XX_EN_RNG_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk sdma_fck;
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
> +DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
> +
> +static struct clk sdma_ick;
> +
> +static struct clk_hw_omap sdma_ick_hw = {
> + .hw = {
> + .clk = &sdma_ick,
> + },
> + .ops = &clkhwops_iclk,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
> + .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
> + .clkdm_name = "core_l3_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
> +
> +static struct clk sdrc_ick;
> +
> +static struct clk_hw_omap sdrc_ick_hw = {
> + .hw = {
> + .clk = &sdrc_ick,
> + },
> + .ops = &clkhwops_iclk,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
> + .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
> + .flags = ENABLE_ON_INIT,
> + .clkdm_name = "core_l3_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
> +
> +static struct clk sha_ick;
> +
> +static struct clk_hw_omap sha_ick_hw = {
> + .hw = {
> + .clk = &sha_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
> + .enable_bit = OMAP24XX_EN_SHA_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk ssi_l4_ick;
> +
> +static struct clk_hw_omap ssi_l4_ick_hw = {
> + .hw = {
> + .clk = &ssi_l4_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP24XX_EN_SSI_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 2, .val = 2, .flags = RATE_IN_24XX },
> + { .div = 3, .val = 3, .flags = RATE_IN_24XX },
> + { .div = 4, .val = 4, .flags = RATE_IN_24XX },
> + { .div = 6, .val = 6, .flags = RATE_IN_242X },
> + { .div = 8, .val = 8, .flags = RATE_IN_242X },
> + { .div = 0 }
> +};
> +
> +static const struct clksel ssi_ssr_sst_fck_clksel[] = {
> + { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *ssi_ssr_sst_fck_parent_names[] = {
> + "core_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
> + ssi_ssr_sst_fck_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_SSI_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
> + ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
> +
> +static struct clk sync_32k_ick;
> +
> +static struct clk_hw_omap sync_32k_ick_hw = {
> + .hw = {
> + .clk = &sync_32k_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
> + .flags = ENABLE_ON_INIT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +static const struct clksel_rate common_clkout_src_core_rates[] = {
> + { .div = 1, .val = 0, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate common_clkout_src_sys_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate common_clkout_src_96m_rates[] = {
> + { .div = 1, .val = 2, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate common_clkout_src_54m_rates[] = {
> + { .div = 1, .val = 3, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel common_clkout_src_clksel[] = {
> + { .parent = &core_ck, .rates = common_clkout_src_core_rates },
> + { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
> + { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
> + { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *sys_clkout_src_parent_names[] = {
> + "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
> + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
> + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
> + NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
> +
> +DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
> + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
> + OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
> + common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL,
> + OMAP2420_CLKOUT2_SOURCE_MASK,
> + OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT,
> + NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
> +
> +DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0,
> + OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT,
> + OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
> +
> +static struct clk uart1_fck;
> +
> +static struct clk_hw_omap uart1_fck_hw = {
> + .hw = {
> + .clk = &uart1_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_UART1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static struct clk uart1_ick;
> +
> +static struct clk_hw_omap uart1_ick_hw = {
> + .hw = {
> + .clk = &uart1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_UART1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk uart2_fck;
> +
> +static struct clk_hw_omap uart2_fck_hw = {
> + .hw = {
> + .clk = &uart2_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_UART2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static struct clk uart2_ick;
> +
> +static struct clk_hw_omap uart2_ick_hw = {
> + .hw = {
> + .clk = &uart2_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_UART2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk uart3_fck;
> +
> +static struct clk_hw_omap uart3_fck_hw = {
> + .hw = {
> + .clk = &uart3_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + .enable_bit = OMAP24XX_EN_UART3_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static struct clk uart3_ick;
> +
> +static struct clk_hw_omap uart3_ick_hw = {
> + .hw = {
> + .clk = &uart3_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP24XX_EN_UART3_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk usb_fck;
> +
> +static struct clk_hw_omap usb_fck_hw = {
> + .hw = {
> + .clk = &usb_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + .enable_bit = OMAP24XX_EN_USB_SHIFT,
> + .clkdm_name = "core_l3_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 2, .val = 2, .flags = RATE_IN_24XX },
> + { .div = 4, .val = 4, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel usb_l4_ick_clksel[] = {
> + { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *usb_l4_ick_parent_names[] = {
> + "core_l3_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_USB_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
> + usb_l4_ick_parent_names, dsp_fck_ops);
> +
> +static struct clk virt_prcm_set;
> +
> +static const char *virt_prcm_set_parent_names[] = {
> + "mpu_ck",
> +};
> +
> +static const struct clk_ops virt_prcm_set_ops = {
> + .recalc_rate = &omap2_table_mpu_recalc,
> + .set_rate = &omap2_select_table_rate,
> + .round_rate = &omap2_round_to_table_rate,
> +};
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
> +DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
> +
> +static const struct clksel_rate vlynq_fck_96m_rates[] = {
> + { .div = 1, .val = 0, .flags = RATE_IN_242X },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate vlynq_fck_core_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_242X },
> + { .div = 2, .val = 2, .flags = RATE_IN_242X },
> + { .div = 3, .val = 3, .flags = RATE_IN_242X },
> + { .div = 4, .val = 4, .flags = RATE_IN_242X },
> + { .div = 6, .val = 6, .flags = RATE_IN_242X },
> + { .div = 8, .val = 8, .flags = RATE_IN_242X },
> + { .div = 9, .val = 9, .flags = RATE_IN_242X },
> + { .div = 12, .val = 12, .flags = RATE_IN_242X },
> + { .div = 16, .val = 16, .flags = RATE_IN_242X },
> + { .div = 18, .val = 18, .flags = RATE_IN_242X },
> + { .div = 0 }
> +};
> +
> +static const struct clksel vlynq_fck_clksel[] = {
> + { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
> + { .parent = &core_ck, .rates = vlynq_fck_core_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *vlynq_fck_parent_names[] = {
> + "func_96m_ck", "core_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP2420_CLKSEL_VLYNQ_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait,
> + vlynq_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk vlynq_ick;
> +
> +static struct clk_hw_omap vlynq_ick_hw = {
> + .hw = {
> + .clk = &vlynq_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
> + .clkdm_name = "core_l3_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops);
> +
> +static struct clk wdt1_ick;
> +
> +static struct clk_hw_omap wdt1_ick_hw = {
> + .hw = {
> + .clk = &wdt1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +static struct clk wdt1_osc_ck;
> +
> +static const struct clk_ops wdt1_osc_ck_ops = {};
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
> +DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
> +
> +static struct clk wdt3_fck;
> +
> +static struct clk_hw_omap wdt3_fck_hw = {
> + .hw = {
> + .clk = &wdt3_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP2420_EN_WDT3_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops);
> +
> +static struct clk wdt3_ick;
> +
> +static struct clk_hw_omap wdt3_ick_hw = {
> + .hw = {
> + .clk = &wdt3_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP2420_EN_WDT3_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk wdt4_fck;
> +
> +static struct clk_hw_omap wdt4_fck_hw = {
> + .hw = {
> + .clk = &wdt4_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops);
> +
> +static struct clk wdt4_ick;
> +
> +static struct clk_hw_omap wdt4_ick_hw = {
> + .hw = {
> + .clk = &wdt4_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +/*
> + * clkdev integration
> + */
> +
> +static struct omap_clk omap2420_clks[] = {
> + /* external root sources */
> + CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
> + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
> + CLK(NULL, "osc_ck", &osc_ck, CK_242X),
> + CLK(NULL, "sys_ck", &sys_ck, CK_242X),
> + CLK(NULL, "alt_ck", &alt_ck, CK_242X),
> + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
> + /* internal analog sources */
> + CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
> + CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
> + CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
> + /* internal prcm root sources */
> + CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
> + CLK(NULL, "core_ck", &core_ck, CK_242X),
> + CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
> + CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
> + CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
> + CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
> + CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
> + CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
> + CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
> + CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
> + CLK(NULL, "emul_ck", &emul_ck, CK_242X),
> + /* mpu domain clocks */
> + CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
> + /* dsp domain clocks */
> + CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
> + CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
> + CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
> + CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
> + /* GFX domain clocks */
> + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
> + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
> + CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
> + /* DSS domain clocks */
> + CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
> + CLK(NULL, "dss_ick", &dss_ick, CK_242X),
> + CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
> + CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
> + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
> + /* L3 domain clocks */
> + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
> + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
> + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
> + /* L4 domain clocks */
> + CLK(NULL, "l4_ck", &l4_ck, CK_242X),
> + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
> + CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
> + /* virtual meta-group clock */
> + CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
> + /* general l4 interface ck, multi-parent functional clk */
> + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
> + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
> + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
> + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
> + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
> + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
> + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
> + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
> + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
> + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
> + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
> + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
> + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
> + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
> + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
> + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
> + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
> + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
> + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
> + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
> + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
> + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
> + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
> + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
> + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
> + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
> + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
> + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
> + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
> + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
> + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
> + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
> + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
> + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
> + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
> + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
> + CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
> + CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
> + CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
> + CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
> + CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
> + CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
> + CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
> + CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
> + CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
> + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
> + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
> + CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
> + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
> + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
> + CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
> + CLK(NULL, "cam_fck", &cam_fck, CK_242X),
> + CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
> + CLK(NULL, "cam_ick", &cam_ick, CK_242X),
> + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
> + CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
> + CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
> + CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
> + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
> + CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
> + CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
> + CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
> + CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
> + CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
> + CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
> + CLK(NULL, "fac_ick", &fac_ick, CK_242X),
> + CLK(NULL, "fac_fck", &fac_fck, CK_242X),
> + CLK(NULL, "eac_ick", &eac_ick, CK_242X),
> + CLK(NULL, "eac_fck", &eac_fck, CK_242X),
> + CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
> + CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
> + CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
> + CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
> + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
> + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
> + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
> + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
> + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
> + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
> + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
> + CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
> + CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
> + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
> + CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
> + CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
> + CLK(NULL, "des_ick", &des_ick, CK_242X),
> + CLK("omap-sham", "ick", &sha_ick, CK_242X),
> + CLK(NULL, "sha_ick", &sha_ick, CK_242X),
> + CLK("omap_rng", "ick", &rng_ick, CK_242X),
> + CLK(NULL, "rng_ick", &rng_ick, CK_242X),
> + CLK("omap-aes", "ick", &aes_ick, CK_242X),
> + CLK(NULL, "aes_ick", &aes_ick, CK_242X),
> + CLK(NULL, "pka_ick", &pka_ick, CK_242X),
> + CLK(NULL, "usb_fck", &usb_fck, CK_242X),
> + CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
> + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
> + CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
> + CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
> + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
> +};
> +
> +
> +static const char *enable_init_clks[] = {
> + "apll96_ck",
> + "apll54_ck",
> + "sync_32k_ick",
> + "omapctrl_ick",
> + "gpmc_fck",
> + "sdrc_ick",
> +};
> +
> +/*
> + * init code
> + */
> +
> +int __init omap2420_clk_init(void)
> +{
> + const struct prcm_config *prcm;
> + struct omap_clk *c;
> + unsigned long clkrate;
> +
> + prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
> + cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
> + cpu_mask = RATE_IN_242X;
> + rate_table = omap2420_rate_table;
> +
> + /* Check the MPU rate set by bootloader */
> + clkrate = omap2xxx_clk_get_core_rate(&dpll_ck_hw);
> + for (prcm = rate_table; prcm->mpu_speed; prcm++) {
> + if (!(prcm->flags & cpu_mask))
> + continue;
> + if (prcm->xtal_speed != sys_ck.rate)
> + continue;
> + if (prcm->dpll_speed <= clkrate)
> + break;
> + }
> +
> + curr_prcm_set = prcm;
> +
> + for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
> + c++) {
> + clkdev_add(&c->lk);
> + if (!__clk_init(NULL, c->lk.clk))
> + omap2_init_clk_hw_omap_clocks(c->lk.clk);
> + }
> +
> + omap2_clk_disable_autoidle_all();
> +
> + omap2_clk_enable_init_clocks(enable_init_clks,
> + ARRAY_SIZE(enable_init_clks));
> +
> + pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
> + (clk_get_rate(&sys_ck) / 1000000),
> + (clk_get_rate(&sys_ck) / 100000) % 10,
> + (clk_get_rate(&dpll_ck) / 1000000),
> + (clk_get_rate(&mpu_ck) / 1000000));
> +
> + return 0;
> +}
> diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
> new file mode 100644
> index 0000000..102fbba
> --- /dev/null
> +++ b/arch/arm/mach-omap2/cclock2430_data.c
> @@ -0,0 +1,2076 @@
> +/*
> + * OMAP2430 clock data
> + *
> + * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
> + * Copyright (C) 2004-2011 Nokia Corporation
> + *
> + * Contacts:
> + * Richard Woodruff <r-woodruff2@ti.com>
> + * Paul Walmsley
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/clk.h>
> +#include <linux/clk-private.h>
> +#include <linux/list.h>
> +
> +#include "soc.h"
> +#include "iomap.h"
> +#include "clock.h"
> +#include "clock2xxx.h"
> +#include "opp2xxx.h"
> +#include "cm2xxx.h"
> +#include "prm2xxx.h"
> +#include "prm-regbits-24xx.h"
> +#include "cm-regbits-24xx.h"
> +#include "sdrc.h"
> +#include "control.h"
> +
> +#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
> +
> +/*
> + * 2430 clock tree.
> + *
> + * NOTE:In many cases here we are assigning a 'default' parent. In
> + * many cases the parent is selectable. The set parent calls will
> + * also switch sources.
> + *
> + * Several sources are given initial rates which may be wrong, this will
> + * be fixed up in the init func.
> + *
> + * Things are broadly separated below by clock domains. It is
> + * noteworthy that most peripherals have dependencies on multiple clock
> + * domains. Many get their interface clocks from the L4 domain, but get
> + * functional clocks from fixed sources or other core domain derived
> + * clocks.
> + */
> +
> +DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
> +
> +DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
> +
> +DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
> +
> +static struct clk osc_ck;
> +
> +static const struct clk_ops osc_ck_ops = {
> + .enable = &omap2_enable_osc_ck,
> + .disable = omap2_disable_osc_ck,
> + .recalc_rate = &omap2_osc_clk_recalc,
> +};
> +
> +static struct clk_hw_omap osc_ck_hw = {
> + .hw = {
> + .clk = &osc_ck,
> + },
> +};
> +
> +static struct clk osc_ck = {
> + .name = "osc_ck",
> + .ops = &osc_ck_ops,
> + .hw = &osc_ck_hw.hw,
> + .flags = CLK_IS_ROOT,
> +};
> +
> +DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
> +
> +static struct clk sys_ck;
> +
> +static const char *sys_ck_parent_names[] = {
> + "osc_ck",
> +};
> +
> +static const struct clk_ops sys_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .recalc_rate = &omap2xxx_sys_clk_recalc,
> +};
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
> +DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
> +
> +static struct dpll_data dpll_dd = {
> + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
> + .mult_mask = OMAP24XX_DPLL_MULT_MASK,
> + .div1_mask = OMAP24XX_DPLL_DIV_MASK,
> + .clk_bypass = &sys_ck,
> + .clk_ref = &sys_ck,
> + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
> + .enable_mask = OMAP24XX_EN_DPLL_MASK,
> + .max_multiplier = 1023,
> + .min_divider = 1,
> + .max_divider = 16,
> +};
> +
> +static struct clk dpll_ck;
> +
> +static const char *dpll_ck_parent_names[] = {
> + "sys_ck",
> +};
> +
> +static const struct clk_ops dpll_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .get_parent = &omap2_init_dpll_parent,
> + .recalc_rate = &omap2_dpllcore_recalc,
> + .round_rate = &omap2_dpll_round_rate,
> + .set_rate = &omap2_reprogram_dpllcore,
> +};
> +
> +static struct clk_hw_omap dpll_ck_hw = {
> + .hw = {
> + .clk = &dpll_ck,
> + },
> + .ops = &clkhwops_omap2xxx_dpll,
> + .dpll_data = &dpll_dd,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
> +
> +static struct clk core_ck;
> +
> +static const char *core_ck_parent_names[] = {
> + "dpll_ck",
> +};
> +
> +static const struct clk_ops core_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> +};
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
> +DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
> +
> +DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
> + CLK_DIVIDER_ONE_BASED, NULL);
> +
> +DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
> + CLK_DIVIDER_ONE_BASED, NULL);
> +
> +static struct clk aes_ick;
> +
> +static const char *aes_ick_parent_names[] = {
> + "l4_ck",
> +};
> +
> +static const struct clk_ops aes_ick_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_dflt_clk_enable,
> + .disable = &omap2_dflt_clk_disable,
> + .is_enabled = &omap2_dflt_clk_is_enabled,
> +};
> +
> +static struct clk_hw_omap aes_ick_hw = {
> + .hw = {
> + .clk = &aes_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
> + .enable_bit = OMAP24XX_EN_AES_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk apll54_ck;
> +
> +static const struct clk_ops apll54_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_clk_apll54_enable,
> + .disable = &omap2_clk_apll_disable,
> + .recalc_rate = &omap2_clk_apll54_recalc,
> +};
> +
> +static struct clk_hw_omap apll54_ck_hw = {
> + .hw = {
> + .clk = &apll54_ck,
> + },
> + .ops = &clkhwops_apll54,
> + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
> + .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
> + .flags = ENABLE_ON_INIT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
> +
> +static struct clk apll96_ck;
> +
> +static const struct clk_ops apll96_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_clk_apll96_enable,
> + .disable = &omap2_clk_apll_disable,
> + .recalc_rate = &omap2_clk_apll96_recalc,
> +};
> +
> +static struct clk_hw_omap apll96_ck_hw = {
> + .hw = {
> + .clk = &apll96_ck,
> + },
> + .ops = &clkhwops_apll96,
> + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
> + .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
> + .flags = ENABLE_ON_INIT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
> +
> +static const char *func_96m_ck_parent_names[] = {
> + "apll96_ck", "alt_ck",
> +};
> +
> +DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0,
> + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT,
> + OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL);
> +
> +static struct clk cam_fck;
> +
> +static const char *cam_fck_parent_names[] = {
> + "func_96m_ck",
> +};
> +
> +static struct clk_hw_omap cam_fck_hw = {
> + .hw = {
> + .clk = &cam_fck,
> + },
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_CAM_SHIFT,
> + .clkdm_name = "core_l3_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
> +
> +static struct clk cam_ick;
> +
> +static struct clk_hw_omap cam_ick_hw = {
> + .hw = {
> + .clk = &cam_ick,
> + },
> + .ops = &clkhwops_iclk,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_CAM_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk des_ick;
> +
> +static struct clk_hw_omap des_ick_hw = {
> + .hw = {
> + .clk = &des_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
> + .enable_bit = OMAP24XX_EN_DES_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static const struct clksel_rate dsp_fck_core_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 2, .val = 2, .flags = RATE_IN_24XX },
> + { .div = 3, .val = 3, .flags = RATE_IN_24XX },
> + { .div = 4, .val = 4, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel dsp_fck_clksel[] = {
> + { .parent = &core_ck, .rates = dsp_fck_core_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *dsp_fck_parent_names[] = {
> + "core_ck",
> +};
> +
> +static struct clk dsp_fck;
> +
> +static const struct clk_ops dsp_fck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_dflt_clk_enable,
> + .disable = &omap2_dflt_clk_disable,
> + .is_enabled = &omap2_dflt_clk_is_enabled,
> + .recalc_rate = &omap2_clksel_recalc,
> + .set_rate = &omap2_clksel_set_rate,
> + .round_rate = &omap2_clksel_round_rate,
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
> + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
> + OMAP24XX_CLKSEL_DSP_MASK,
> + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
> + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
> + dsp_fck_parent_names, dsp_fck_ops);
> +
> +static const struct clksel_rate dss1_fck_sys_rates[] = {
> + { .div = 1, .val = 0, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate dss1_fck_core_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 2, .val = 2, .flags = RATE_IN_24XX },
> + { .div = 3, .val = 3, .flags = RATE_IN_24XX },
> + { .div = 4, .val = 4, .flags = RATE_IN_24XX },
> + { .div = 5, .val = 5, .flags = RATE_IN_24XX },
> + { .div = 6, .val = 6, .flags = RATE_IN_24XX },
> + { .div = 8, .val = 8, .flags = RATE_IN_24XX },
> + { .div = 9, .val = 9, .flags = RATE_IN_24XX },
> + { .div = 12, .val = 12, .flags = RATE_IN_24XX },
> + { .div = 16, .val = 16, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel dss1_fck_clksel[] = {
> + { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
> + { .parent = &core_ck, .rates = dss1_fck_core_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *dss1_fck_parent_names[] = {
> + "sys_ck", "core_ck",
> +};
> +
> +static const struct clk_ops dss1_fck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_dflt_clk_enable,
> + .disable = &omap2_dflt_clk_disable,
> + .is_enabled = &omap2_dflt_clk_is_enabled,
> + .recalc_rate = &omap2_clksel_recalc,
> + .get_parent = &omap2_clksel_find_parent_index,
> + .set_parent = &omap2_clksel_set_parent,
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_DSS1_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_DSS1_SHIFT, NULL,
> + dss1_fck_parent_names, dss1_fck_ops);
> +
> +static const struct clksel_rate dss2_fck_sys_rates[] = {
> + { .div = 1, .val = 0, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate dss2_fck_48m_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate func_48m_apll96_rates[] = {
> + { .div = 2, .val = 0, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate func_48m_alt_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel func_48m_clksel[] = {
> + { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
> + { .parent = &alt_ck, .rates = func_48m_alt_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *func_48m_ck_parent_names[] = {
> + "apll96_ck", "alt_ck",
> +};
> +
> +static struct clk func_48m_ck;
> +
> +static const struct clk_ops func_48m_ck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .recalc_rate = &omap2_clksel_recalc,
> + .set_rate = &omap2_clksel_set_rate,
> + .round_rate = &omap2_clksel_round_rate,
> + .get_parent = &omap2_clksel_find_parent_index,
> + .set_parent = &omap2_clksel_set_parent,
> +};
> +
> +static struct clk_hw_omap func_48m_ck_hw = {
> + .hw = {
> + .clk = &func_48m_ck,
> + },
> + .clksel = func_48m_clksel,
> + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
> + .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
> +
> +static const struct clksel dss2_fck_clksel[] = {
> + { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
> + { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *dss2_fck_parent_names[] = {
> + "sys_ck", "func_48m_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_DSS2_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_DSS2_SHIFT, NULL,
> + dss2_fck_parent_names, dss1_fck_ops);
> +
> +static const char *func_54m_ck_parent_names[] = {
> + "apll54_ck", "alt_ck",
> +};
> +
> +DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
> + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
> + OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL);
> +
> +static struct clk dss_54m_fck;
> +
> +static const char *dss_54m_fck_parent_names[] = {
> + "func_54m_ck",
> +};
> +
> +static struct clk_hw_omap dss_54m_fck_hw = {
> + .hw = {
> + .clk = &dss_54m_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_TV_SHIFT,
> + .clkdm_name = "dss_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
> +
> +static struct clk dss_ick;
> +
> +static struct clk_hw_omap dss_ick_hw = {
> + .hw = {
> + .clk = &dss_ick,
> + },
> + .ops = &clkhwops_iclk,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
> + .clkdm_name = "dss_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk emul_ck;
> +
> +static struct clk_hw_omap emul_ck_hw = {
> + .hw = {
> + .clk = &emul_ck,
> + },
> + .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
> + .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
> +
> +static struct clk fac_fck;
> +
> +static const char *fac_fck_parent_names[] = {
> + "func_12m_ck",
> +};
> +
> +static struct clk_hw_omap fac_fck_hw = {
> + .hw = {
> + .clk = &fac_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_FAC_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
> +
> +static struct clk fac_ick;
> +
> +static struct clk_hw_omap fac_ick_hw = {
> + .hw = {
> + .clk = &fac_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_FAC_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static const struct clksel gfx_fck_clksel[] = {
> + { .parent = &core_l3_ck, .rates = gfx_l3_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *gfx_2d_fck_parent_names[] = {
> + "core_l3_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
> + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
> + OMAP_CLKSEL_GFX_MASK,
> + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
> + OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
> + gfx_2d_fck_parent_names, dsp_fck_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
> + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
> + OMAP_CLKSEL_GFX_MASK,
> + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
> + OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
> + gfx_2d_fck_parent_names, dsp_fck_ops);
> +
> +static struct clk gfx_ick;
> +
> +static const char *gfx_ick_parent_names[] = {
> + "core_l3_ck",
> +};
> +
> +static struct clk_hw_omap gfx_ick_hw = {
> + .hw = {
> + .clk = &gfx_ick,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
> + .enable_bit = OMAP_EN_GFX_SHIFT,
> + .clkdm_name = "gfx_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
> +
> +static struct clk gpio5_fck;
> +
> +static const char *gpio5_fck_parent_names[] = {
> + "func_32k_ck",
> +};
> +
> +static struct clk_hw_omap gpio5_fck_hw = {
> + .hw = {
> + .clk = &gpio5_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops);
> +
> +static struct clk gpio5_ick;
> +
> +static struct clk_hw_omap gpio5_ick_hw = {
> + .hw = {
> + .clk = &gpio5_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk gpios_fck;
> +
> +static struct clk_hw_omap gpios_fck_hw = {
> + .hw = {
> + .clk = &gpios_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
> + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops);
> +
> +static struct clk wu_l4_ick;
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
> +DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
> +
> +static struct clk gpios_ick;
> +
> +static const char *gpios_ick_parent_names[] = {
> + "wu_l4_ick",
> +};
> +
> +static struct clk_hw_omap gpios_ick_hw = {
> + .hw = {
> + .clk = &gpios_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +static struct clk gpmc_fck;
> +
> +static struct clk_hw_omap gpmc_fck_hw = {
> + .hw = {
> + .clk = &gpmc_fck,
> + },
> + .ops = &clkhwops_iclk,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
> + .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
> + .flags = ENABLE_ON_INIT,
> + .clkdm_name = "core_l3_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
> +
> +static const struct clksel_rate gpt_alt_rates[] = {
> + { .div = 1, .val = 2, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel omap24xx_gpt_clksel[] = {
> + { .parent = &func_32k_ck, .rates = gpt_32k_rates },
> + { .parent = &sys_ck, .rates = gpt_sys_rates },
> + { .parent = &alt_ck, .rates = gpt_alt_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *gpt10_fck_parent_names[] = {
> + "func_32k_ck", "sys_ck", "alt_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT10_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt10_ick;
> +
> +static struct clk_hw_omap gpt10_ick_hw = {
> + .hw = {
> + .clk = &gpt10_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT11_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt11_ick;
> +
> +static struct clk_hw_omap gpt11_ick_hw = {
> + .hw = {
> + .clk = &gpt11_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT12_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt12_ick;
> +
> +static struct clk_hw_omap gpt12_ick_hw = {
> + .hw = {
> + .clk = &gpt12_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static const struct clk_ops gpt1_fck_ops = {
> + .init = &omap2_init_clk_clkdm,
> + .enable = &omap2_dflt_clk_enable,
> + .disable = &omap2_dflt_clk_disable,
> + .is_enabled = &omap2_dflt_clk_is_enabled,
> + .recalc_rate = &omap2_clksel_recalc,
> + .set_rate = &omap2_clksel_set_rate,
> + .round_rate = &omap2_clksel_round_rate,
> + .get_parent = &omap2_clksel_find_parent_index,
> + .set_parent = &omap2_clksel_set_parent,
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_GPT1_MASK,
> + OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
> + OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, gpt1_fck_ops);
> +
> +static struct clk gpt1_ick;
> +
> +static struct clk_hw_omap gpt1_ick_hw = {
> + .hw = {
> + .clk = &gpt1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT2_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt2_ick;
> +
> +static struct clk_hw_omap gpt2_ick_hw = {
> + .hw = {
> + .clk = &gpt2_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT3_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt3_ick;
> +
> +static struct clk_hw_omap gpt3_ick_hw = {
> + .hw = {
> + .clk = &gpt3_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT4_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt4_ick;
> +
> +static struct clk_hw_omap gpt4_ick_hw = {
> + .hw = {
> + .clk = &gpt4_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT5_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt5_ick;
> +
> +static struct clk_hw_omap gpt5_ick_hw = {
> + .hw = {
> + .clk = &gpt5_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT6_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt6_ick;
> +
> +static struct clk_hw_omap gpt6_ick_hw = {
> + .hw = {
> + .clk = &gpt6_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT7_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt7_ick;
> +
> +static struct clk_hw_omap gpt7_ick_hw = {
> + .hw = {
> + .clk = &gpt7_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk gpt8_fck;
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT8_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt8_ick;
> +
> +static struct clk_hw_omap gpt8_ick_hw = {
> + .hw = {
> + .clk = &gpt8_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
> + OMAP24XX_CLKSEL_GPT9_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
> + gpt10_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk gpt9_ick;
> +
> +static struct clk_hw_omap gpt9_ick_hw = {
> + .hw = {
> + .clk = &gpt9_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk hdq_fck;
> +
> +static struct clk_hw_omap hdq_fck_hw = {
> + .hw = {
> + .clk = &hdq_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
> +
> +static struct clk hdq_ick;
> +
> +static struct clk_hw_omap hdq_ick_hw = {
> + .hw = {
> + .clk = &hdq_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk i2c1_ick;
> +
> +static struct clk_hw_omap i2c1_ick_hw = {
> + .hw = {
> + .clk = &i2c1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP2420_EN_I2C1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk i2c2_ick;
> +
> +static struct clk_hw_omap i2c2_ick_hw = {
> + .hw = {
> + .clk = &i2c2_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP2420_EN_I2C2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk i2chs1_fck;
> +
> +static struct clk_hw_omap i2chs1_fck_hw = {
> + .hw = {
> + .clk = &i2chs1_fck,
> + },
> + .ops = &clkhwops_omap2430_i2chs_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops);
> +
> +static struct clk i2chs2_fck;
> +
> +static struct clk_hw_omap i2chs2_fck_hw = {
> + .hw = {
> + .clk = &i2chs2_fck,
> + },
> + .ops = &clkhwops_omap2430_i2chs_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops);
> +
> +static struct clk icr_ick;
> +
> +static struct clk_hw_omap icr_ick_hw = {
> + .hw = {
> + .clk = &icr_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP2430_EN_ICR_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +static const struct clksel dsp_ick_clksel[] = {
> + { .parent = &dsp_fck, .rates = dsp_ick_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *iva2_1_ick_parent_names[] = {
> + "dsp_fck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel,
> + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
> + OMAP24XX_CLKSEL_DSP_IF_MASK,
> + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
> + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
> + iva2_1_ick_parent_names, dsp_fck_ops);
> +
> +static struct clk mailboxes_ick;
> +
> +static struct clk_hw_omap mailboxes_ick_hw = {
> + .hw = {
> + .clk = &mailboxes_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static const struct clksel_rate common_mcbsp_96m_rates[] = {
> + { .div = 1, .val = 0, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel mcbsp_fck_clksel[] = {
> + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
> + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *mcbsp1_fck_parent_names[] = {
> + "func_96m_ck", "mcbsp_clks",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
> + OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
> + OMAP2_MCBSP1_CLKS_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
> + mcbsp1_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk mcbsp1_ick;
> +
> +static struct clk_hw_omap mcbsp1_ick_hw = {
> + .hw = {
> + .clk = &mcbsp1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
> + OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
> + OMAP2_MCBSP2_CLKS_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
> + mcbsp1_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk mcbsp2_ick;
> +
> +static struct clk_hw_omap mcbsp2_ick_hw = {
> + .hw = {
> + .clk = &mcbsp2_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel,
> + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
> + OMAP2_MCBSP3_CLKS_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait,
> + mcbsp1_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk mcbsp3_ick;
> +
> +static struct clk_hw_omap mcbsp3_ick_hw = {
> + .hw = {
> + .clk = &mcbsp3_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel,
> + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
> + OMAP2_MCBSP4_CLKS_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait,
> + mcbsp1_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk mcbsp4_ick;
> +
> +static struct clk_hw_omap mcbsp4_ick_hw = {
> + .hw = {
> + .clk = &mcbsp4_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel,
> + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
> + OMAP2_MCBSP5_CLKS_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait,
> + mcbsp1_fck_parent_names, dss1_fck_ops);
> +
> +static struct clk mcbsp5_ick;
> +
> +static struct clk_hw_omap mcbsp5_ick_hw = {
> + .hw = {
> + .clk = &mcbsp5_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk mcspi1_fck;
> +
> +static const char *mcspi1_fck_parent_names[] = {
> + "func_48m_ck",
> +};
> +
> +static struct clk_hw_omap mcspi1_fck_hw = {
> + .hw = {
> + .clk = &mcspi1_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mcspi1_ick;
> +
> +static struct clk_hw_omap mcspi1_ick_hw = {
> + .hw = {
> + .clk = &mcspi1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk mcspi2_fck;
> +
> +static struct clk_hw_omap mcspi2_fck_hw = {
> + .hw = {
> + .clk = &mcspi2_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mcspi2_ick;
> +
> +static struct clk_hw_omap mcspi2_ick_hw = {
> + .hw = {
> + .clk = &mcspi2_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk mcspi3_fck;
> +
> +static struct clk_hw_omap mcspi3_fck_hw = {
> + .hw = {
> + .clk = &mcspi3_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mcspi3_ick;
> +
> +static struct clk_hw_omap mcspi3_ick_hw = {
> + .hw = {
> + .clk = &mcspi3_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static const struct clksel_rate mdm_ick_core_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_243X },
> + { .div = 4, .val = 4, .flags = RATE_IN_243X },
> + { .div = 6, .val = 6, .flags = RATE_IN_243X },
> + { .div = 9, .val = 9, .flags = RATE_IN_243X },
> + { .div = 0 }
> +};
> +
> +static const struct clksel mdm_ick_clksel[] = {
> + { .parent = &core_ck, .rates = mdm_ick_core_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *mdm_ick_parent_names[] = {
> + "core_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel,
> + OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
> + OMAP2430_CLKSEL_MDM_MASK,
> + OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
> + OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
> + &clkhwops_iclk_wait, mdm_ick_parent_names,
> + dsp_fck_ops);
> +
> +static struct clk mdm_intc_ick;
> +
> +static struct clk_hw_omap mdm_intc_ick_hw = {
> + .hw = {
> + .clk = &mdm_intc_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk mdm_osc_ck;
> +
> +static struct clk_hw_omap mdm_osc_ck_hw = {
> + .hw = {
> + .clk = &mdm_osc_ck,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
> + .enable_bit = OMAP2430_EN_OSC_SHIFT,
> + .clkdm_name = "mdm_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops);
> +
> +static struct clk mmchs1_fck;
> +
> +static struct clk_hw_omap mmchs1_fck_hw = {
> + .hw = {
> + .clk = &mmchs1_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mmchs1_ick;
> +
> +static struct clk_hw_omap mmchs1_ick_hw = {
> + .hw = {
> + .clk = &mmchs1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk mmchs2_fck;
> +
> +static struct clk_hw_omap mmchs2_fck_hw = {
> + .hw = {
> + .clk = &mmchs2_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mmchs2_ick;
> +
> +static struct clk_hw_omap mmchs2_ick_hw = {
> + .hw = {
> + .clk = &mmchs2_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk mmchsdb1_fck;
> +
> +static struct clk_hw_omap mmchsdb1_fck_hw = {
> + .hw = {
> + .clk = &mmchsdb1_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mmchsdb2_fck;
> +
> +static struct clk_hw_omap mmchsdb2_fck_hw = {
> + .hw = {
> + .clk = &mmchsdb2_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops);
> +
> +DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
> + OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
> + OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
> + CLK_DIVIDER_ONE_BASED, NULL);
> +
> +static struct clk mpu_wdt_fck;
> +
> +static struct clk_hw_omap mpu_wdt_fck_hw = {
> + .hw = {
> + .clk = &mpu_wdt_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
> + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mpu_wdt_ick;
> +
> +static struct clk_hw_omap mpu_wdt_ick_hw = {
> + .hw = {
> + .clk = &mpu_wdt_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +static struct clk mspro_fck;
> +
> +static struct clk_hw_omap mspro_fck_hw = {
> + .hw = {
> + .clk = &mspro_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
> +
> +static struct clk mspro_ick;
> +
> +static struct clk_hw_omap mspro_ick_hw = {
> + .hw = {
> + .clk = &mspro_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk omapctrl_ick;
> +
> +static struct clk_hw_omap omapctrl_ick_hw = {
> + .hw = {
> + .clk = &omapctrl_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
> + .flags = ENABLE_ON_INIT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +static struct clk pka_ick;
> +
> +static struct clk_hw_omap pka_ick_hw = {
> + .hw = {
> + .clk = &pka_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
> + .enable_bit = OMAP24XX_EN_PKA_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk rng_ick;
> +
> +static struct clk_hw_omap rng_ick_hw = {
> + .hw = {
> + .clk = &rng_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
> + .enable_bit = OMAP24XX_EN_RNG_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk sdma_fck;
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
> +DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
> +
> +static struct clk sdma_ick;
> +
> +static struct clk_hw_omap sdma_ick_hw = {
> + .hw = {
> + .clk = &sdma_ick,
> + },
> + .ops = &clkhwops_iclk,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
> + .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
> + .clkdm_name = "core_l3_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
> +
> +static struct clk sdrc_ick;
> +
> +static struct clk_hw_omap sdrc_ick_hw = {
> + .hw = {
> + .clk = &sdrc_ick,
> + },
> + .ops = &clkhwops_iclk,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
> + .enable_bit = OMAP2430_EN_SDRC_SHIFT,
> + .flags = ENABLE_ON_INIT,
> + .clkdm_name = "core_l3_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
> +
> +static struct clk sha_ick;
> +
> +static struct clk_hw_omap sha_ick_hw = {
> + .hw = {
> + .clk = &sha_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
> + .enable_bit = OMAP24XX_EN_SHA_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk ssi_l4_ick;
> +
> +static struct clk_hw_omap ssi_l4_ick_hw = {
> + .hw = {
> + .clk = &ssi_l4_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP24XX_EN_SSI_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 2, .val = 2, .flags = RATE_IN_24XX },
> + { .div = 3, .val = 3, .flags = RATE_IN_24XX },
> + { .div = 4, .val = 4, .flags = RATE_IN_24XX },
> + { .div = 5, .val = 5, .flags = RATE_IN_243X },
> + { .div = 0 }
> +};
> +
> +static const struct clksel ssi_ssr_sst_fck_clksel[] = {
> + { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *ssi_ssr_sst_fck_parent_names[] = {
> + "core_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
> + ssi_ssr_sst_fck_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_SSI_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
> + ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
> +
> +static struct clk sync_32k_ick;
> +
> +static struct clk_hw_omap sync_32k_ick_hw = {
> + .hw = {
> + .clk = &sync_32k_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
> + .flags = ENABLE_ON_INIT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +static const struct clksel_rate common_clkout_src_core_rates[] = {
> + { .div = 1, .val = 0, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate common_clkout_src_sys_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate common_clkout_src_96m_rates[] = {
> + { .div = 1, .val = 2, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel_rate common_clkout_src_54m_rates[] = {
> + { .div = 1, .val = 3, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel common_clkout_src_clksel[] = {
> + { .parent = &core_ck, .rates = common_clkout_src_core_rates },
> + { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
> + { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
> + { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *sys_clkout_src_parent_names[] = {
> + "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
> + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
> + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
> + NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
> +
> +DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
> + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
> + OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
> +
> +static struct clk uart1_fck;
> +
> +static struct clk_hw_omap uart1_fck_hw = {
> + .hw = {
> + .clk = &uart1_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_UART1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static struct clk uart1_ick;
> +
> +static struct clk_hw_omap uart1_ick_hw = {
> + .hw = {
> + .clk = &uart1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_UART1_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk uart2_fck;
> +
> +static struct clk_hw_omap uart2_fck_hw = {
> + .hw = {
> + .clk = &uart2_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_UART2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static struct clk uart2_ick;
> +
> +static struct clk_hw_omap uart2_ick_hw = {
> + .hw = {
> + .clk = &uart2_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_UART2_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk uart3_fck;
> +
> +static struct clk_hw_omap uart3_fck_hw = {
> + .hw = {
> + .clk = &uart3_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + .enable_bit = OMAP24XX_EN_UART3_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static struct clk uart3_ick;
> +
> +static struct clk_hw_omap uart3_ick_hw = {
> + .hw = {
> + .clk = &uart3_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP24XX_EN_UART3_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +static struct clk usb_fck;
> +
> +static struct clk_hw_omap usb_fck_hw = {
> + .hw = {
> + .clk = &usb_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
> + .enable_bit = OMAP24XX_EN_USB_SHIFT,
> + .clkdm_name = "core_l3_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
> +
> +static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_24XX },
> + { .div = 2, .val = 2, .flags = RATE_IN_24XX },
> + { .div = 4, .val = 4, .flags = RATE_IN_24XX },
> + { .div = 0 }
> +};
> +
> +static const struct clksel usb_l4_ick_clksel[] = {
> + { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
> + { .parent = NULL },
> +};
> +
> +static const char *usb_l4_ick_parent_names[] = {
> + "core_l3_ck",
> +};
> +
> +DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
> + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
> + OMAP24XX_CLKSEL_USB_MASK,
> + OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
> + usb_l4_ick_parent_names, dsp_fck_ops);
> +
> +static struct clk usbhs_ick;
> +
> +static struct clk_hw_omap usbhs_ick_hw = {
> + .hw = {
> + .clk = &usbhs_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
> + .enable_bit = OMAP2430_EN_USBHS_SHIFT,
> + .clkdm_name = "core_l3_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops);
> +
> +static struct clk virt_prcm_set;
> +
> +static const char *virt_prcm_set_parent_names[] = {
> + "mpu_ck",
> +};
> +
> +static const struct clk_ops virt_prcm_set_ops = {
> + .recalc_rate = &omap2_table_mpu_recalc,
> + .set_rate = &omap2_select_table_rate,
> + .round_rate = &omap2_round_to_table_rate,
> +};
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
> +DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
> +
> +static struct clk wdt1_ick;
> +
> +static struct clk_hw_omap wdt1_ick_hw = {
> + .hw = {
> + .clk = &wdt1_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
> + .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
> + .clkdm_name = "wkup_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
> +
> +static struct clk wdt1_osc_ck;
> +
> +static const struct clk_ops wdt1_osc_ck_ops = {};
> +
> +DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
> +DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
> +
> +static struct clk wdt4_fck;
> +
> +static struct clk_hw_omap wdt4_fck_hw = {
> + .hw = {
> + .clk = &wdt4_fck,
> + },
> + .ops = &clkhwops_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
> + .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops);
> +
> +static struct clk wdt4_ick;
> +
> +static struct clk_hw_omap wdt4_ick_hw = {
> + .hw = {
> + .clk = &wdt4_ick,
> + },
> + .ops = &clkhwops_iclk_wait,
> + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
> + .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
> + .clkdm_name = "core_l4_clkdm",
> +};
> +
> +DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
> +
> +/*
> + * clkdev integration
> + */
> +
> +static struct omap_clk omap2430_clks[] = {
> + /* external root sources */
> + CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
> + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
> + CLK(NULL, "osc_ck", &osc_ck, CK_243X),
> + CLK("twl", "fck", &osc_ck, CK_243X),
> + CLK(NULL, "sys_ck", &sys_ck, CK_243X),
> + CLK(NULL, "alt_ck", &alt_ck, CK_243X),
> + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
> + /* internal analog sources */
> + CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
> + CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
> + CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
> + /* internal prcm root sources */
> + CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
> + CLK(NULL, "core_ck", &core_ck, CK_243X),
> + CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
> + CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
> + CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
> + CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
> + CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
> + CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
> + CLK(NULL, "emul_ck", &emul_ck, CK_243X),
> + /* mpu domain clocks */
> + CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
> + /* dsp domain clocks */
> + CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
> + CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
> + /* GFX domain clocks */
> + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
> + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
> + CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
> + /* Modem domain clocks */
> + CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
> + CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
> + /* DSS domain clocks */
> + CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
> + CLK(NULL, "dss_ick", &dss_ick, CK_243X),
> + CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
> + CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
> + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
> + /* L3 domain clocks */
> + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
> + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
> + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
> + /* L4 domain clocks */
> + CLK(NULL, "l4_ck", &l4_ck, CK_243X),
> + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
> + CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
> + /* virtual meta-group clock */
> + CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
> + /* general l4 interface ck, multi-parent functional clk */
> + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
> + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
> + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
> + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
> + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
> + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
> + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
> + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
> + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
> + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
> + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
> + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
> + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
> + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
> + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
> + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
> + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
> + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
> + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
> + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
> + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
> + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
> + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
> + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
> + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
> + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X),
> + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
> + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
> + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X),
> + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
> + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
> + CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X),
> + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
> + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
> + CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X),
> + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
> + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
> + CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X),
> + CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
> + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
> + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X),
> + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
> + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
> + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X),
> + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
> + CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
> + CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X),
> + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
> + CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
> + CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
> + CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
> + CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
> + CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
> + CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
> + CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
> + CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
> + CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
> + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X),
> + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
> + CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
> + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
> + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
> + CLK(NULL, "icr_ick", &icr_ick, CK_243X),
> + CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
> + CLK(NULL, "cam_fck", &cam_fck, CK_243X),
> + CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
> + CLK(NULL, "cam_ick", &cam_ick, CK_243X),
> + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
> + CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
> + CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
> + CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
> + CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
> + CLK(NULL, "fac_ick", &fac_ick, CK_243X),
> + CLK(NULL, "fac_fck", &fac_fck, CK_243X),
> + CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
> + CLK(NULL, "hdq_ick", &hdq_ick, CK_243X),
> + CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
> + CLK(NULL, "hdq_fck", &hdq_fck, CK_243X),
> + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
> + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X),
> + CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
> + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
> + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X),
> + CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
> + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
> + CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
> + CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
> + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
> + CLK(NULL, "des_ick", &des_ick, CK_243X),
> + CLK("omap-sham", "ick", &sha_ick, CK_243X),
> + CLK("omap_rng", "ick", &rng_ick, CK_243X),
> + CLK(NULL, "rng_ick", &rng_ick, CK_243X),
> + CLK("omap-aes", "ick", &aes_ick, CK_243X),
> + CLK(NULL, "pka_ick", &pka_ick, CK_243X),
> + CLK(NULL, "usb_fck", &usb_fck, CK_243X),
> + CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
> + CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
> + CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
> + CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X),
> + CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
> + CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
> + CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X),
> + CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
> + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
> + CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
> + CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
> + CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
> + CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X),
> + CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
> + CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X),
> + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
> + CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
> + CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
> + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X),
> +};
> +
> +static const char *enable_init_clks[] = {
> + "apll96_ck",
> + "apll54_ck",
> + "sync_32k_ick",
> + "omapctrl_ick",
> + "gpmc_fck",
> + "sdrc_ick",
> +};
> +
> +/*
> + * init code
> + */
> +
> +int __init omap2430_clk_init(void)
> +{
> + const struct prcm_config *prcm;
> + struct omap_clk *c;
> + unsigned long clkrate;
> +
> + prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
> + cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
> + cpu_mask = RATE_IN_243X;
> + rate_table = omap2430_rate_table;
> +
> + /* Check the MPU rate set by bootloader */
> + clkrate = omap2xxx_clk_get_core_rate(&dpll_ck_hw);
> + for (prcm = rate_table; prcm->mpu_speed; prcm++) {
> + if (!(prcm->flags & cpu_mask))
> + continue;
> + if (prcm->xtal_speed != sys_ck.rate)
> + continue;
> + if (prcm->dpll_speed <= clkrate)
> + break;
> + }
> + curr_prcm_set = prcm;
> +
> + for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
> + c++) {
> + clkdev_add(&c->lk);
> + if (!__clk_init(NULL, c->lk.clk))
> + omap2_init_clk_hw_omap_clocks(c->lk.clk);
> + }
> +
> + omap2_clk_disable_autoidle_all();
> +
> + omap2_clk_enable_init_clocks(enable_init_clks,
> + ARRAY_SIZE(enable_init_clks));
> +
> + pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
> + (clk_get_rate(&sys_ck) / 1000000),
> + (clk_get_rate(&sys_ck) / 100000) % 10,
> + (clk_get_rate(&dpll_ck) / 1000000),
> + (clk_get_rate(&mpu_ck) / 1000000));
> +
> + return 0;
> +}
> diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
> index 6862904..f3fcba2 100644
> --- a/arch/arm/mach-omap2/cm-regbits-24xx.h
> +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
> @@ -59,6 +59,7 @@
> /* CM_CLKSEL_MPU */
> #define OMAP24XX_CLKSEL_MPU_SHIFT 0
> #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
> +#define OMAP24XX_CLKSEL_MPU_WIDTH 5
>
> /* CM_CLKSTCTRL_MPU */
> #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
> @@ -237,8 +238,10 @@
> #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
> #define OMAP24XX_CLKSEL_L4_SHIFT 5
> #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
> +#define OMAP24XX_CLKSEL_L4_WIDTH 2
> #define OMAP24XX_CLKSEL_L3_SHIFT 0
> #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
> +#define OMAP24XX_CLKSEL_L3_WIDTH 5
>
> /* CM_CLKSEL2_CORE */
> #define OMAP24XX_CLKSEL_GPT12_SHIFT 22
> @@ -361,8 +364,10 @@
> #define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
> #define OMAP24XX_54M_SOURCE_SHIFT 5
> #define OMAP24XX_54M_SOURCE_MASK (1 << 5)
> +#define OMAP24XX_54M_SOURCE_WIDTH 1
> #define OMAP2430_96M_SOURCE_SHIFT 4
> #define OMAP2430_96M_SOURCE_MASK (1 << 4)
> +#define OMAP2430_96M_SOURCE_WIDTH 1
> #define OMAP24XX_48M_SOURCE_SHIFT 3
> #define OMAP24XX_48M_SOURCE_MASK (1 << 3)
> #define OMAP2430_ALTCLK_SOURCE_SHIFT 0
> diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
> index 638da6d..91aa510 100644
> --- a/arch/arm/mach-omap2/prm-regbits-24xx.h
> +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
> @@ -107,12 +107,14 @@
> #define OMAP2420_CLKOUT2_EN_MASK (1 << 15)
> #define OMAP2420_CLKOUT2_DIV_SHIFT 11
> #define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
> +#define OMAP2420_CLKOUT2_DIV_WIDTH 3
> #define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
> #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
> #define OMAP24XX_CLKOUT_EN_SHIFT 7
> #define OMAP24XX_CLKOUT_EN_MASK (1 << 7)
> #define OMAP24XX_CLKOUT_DIV_SHIFT 3
> #define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
> +#define OMAP24XX_CLKOUT_DIV_WIDTH 3
> #define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
> #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
>
> --
> 1.7.10.4
^ permalink raw reply
* [PATCH V2 11/11] ARM: delete struct sys_timer
From: Stephen Warren @ 2012-11-09 20:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352408516-21988-1-git-send-email-swarren@wwwdotorg.org>
From: Stephen Warren <swarren@nvidia.com>
Now that the only field in struct sys_timer is .init, delete the struct,
and replace the machine descriptor .timer field with the initialization
function itself.
This will enable moving timer drivers into drivers/clocksource without
having to place a public prototype of each struct sys_timer object into
include/linux; the intent is to create a single of_clocksource_init()
function that determines which timer driver to initialize by scanning
the device dtree, much like the proposed irqchip_init() at:
http://www.spinics.net/lists/arm-kernel/msg203686.html
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: Converted all platforms, not just Tegra.
This is based on next-20121107, so would need to be rebased to actually
apply. Arnd, Olof, what do you think the best plan for merging this into
arm-soc would be?
The patch is very large, so I've trimmed it for the mailing list, leaving
only the core ARM changes, changes outside arch/arm, and a couple platforms
which had slightly less routine changes. The full series can be found at:
git://nv-tegra.nvidia.com/user/swarren/linux-2.6 arm_timer_rework
It'd be great if maintainers could test this on their boards to make sure
I didn't make any silly mistakes, although there are far too many to Cc.
---
arch/arm/include/asm/mach/arch.h | 3 +--
arch/arm/include/asm/mach/time.h | 16 ----------------
arch/arm/kernel/time.c | 9 +--------
arch/arm/mach-at91/at91rm9200_time.c | 5 -----
arch/arm/mach-at91/at91sam926x_time.c | 6 +-----
arch/arm/mach-at91/at91x40_time.c | 5 -----
arch/arm/mach-at91/board-1arm.c | 2 +-
arch/arm/mach-at91/board-afeb-9260v1.c | 2 +-
arch/arm/mach-at91/board-cam60.c | 2 +-
arch/arm/mach-at91/board-carmeva.c | 2 +-
arch/arm/mach-at91/board-cpu9krea.c | 2 +-
arch/arm/mach-at91/board-cpuat91.c | 2 +-
arch/arm/mach-at91/board-csb337.c | 2 +-
arch/arm/mach-at91/board-csb637.c | 2 +-
arch/arm/mach-at91/board-dt.c | 2 +-
arch/arm/mach-at91/board-eb01.c | 2 +-
arch/arm/mach-at91/board-eb9200.c | 2 +-
arch/arm/mach-at91/board-ecbat91.c | 2 +-
arch/arm/mach-at91/board-eco920.c | 2 +-
arch/arm/mach-at91/board-flexibity.c | 2 +-
arch/arm/mach-at91/board-foxg20.c | 2 +-
arch/arm/mach-at91/board-gsia18s.c | 2 +-
arch/arm/mach-at91/board-kafa.c | 2 +-
arch/arm/mach-at91/board-kb9202.c | 2 +-
arch/arm/mach-at91/board-neocore926.c | 2 +-
arch/arm/mach-at91/board-pcontrol-g20.c | 2 +-
arch/arm/mach-at91/board-picotux200.c | 2 +-
arch/arm/mach-at91/board-qil-a9260.c | 2 +-
arch/arm/mach-at91/board-rm9200dk.c | 2 +-
arch/arm/mach-at91/board-rm9200ek.c | 2 +-
arch/arm/mach-at91/board-rsi-ews.c | 2 +-
arch/arm/mach-at91/board-sam9-l9260.c | 2 +-
arch/arm/mach-at91/board-sam9260ek.c | 2 +-
arch/arm/mach-at91/board-sam9261ek.c | 2 +-
arch/arm/mach-at91/board-sam9263ek.c | 2 +-
arch/arm/mach-at91/board-sam9g20ek.c | 4 ++--
arch/arm/mach-at91/board-sam9m10g45ek.c | 2 +-
arch/arm/mach-at91/board-sam9rlek.c | 2 +-
arch/arm/mach-at91/board-snapper9260.c | 2 +-
arch/arm/mach-at91/board-stamp9g20.c | 4 ++--
arch/arm/mach-at91/board-usb-a926x.c | 6 +++---
arch/arm/mach-at91/board-yl-9200.c | 2 +-
arch/arm/mach-at91/generic.h | 7 +++----
arch/arm/mach-bcm2835/bcm2835.c | 2 +-
arch/arm/mach-clps711x/autcpu12.c | 2 +-
arch/arm/mach-clps711x/cdb89712.c | 2 +-
arch/arm/mach-clps711x/clep7312.c | 2 +-
arch/arm/mach-clps711x/common.c | 6 +-----
arch/arm/mach-clps711x/common.h | 4 +---
arch/arm/mach-clps711x/edb7211.c | 2 +-
arch/arm/mach-clps711x/fortunet.c | 2 +-
arch/arm/mach-clps711x/p720t.c | 2 +-
arch/arm/mach-cns3xxx/cns3420vb.c | 2 +-
arch/arm/mach-cns3xxx/core.c | 6 +-----
arch/arm/mach-cns3xxx/core.h | 2 +-
arch/arm/mach-davinci/board-da830-evm.c | 2 +-
arch/arm/mach-davinci/board-da850-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-leopard.c | 2 +-
arch/arm/mach-davinci/board-dm365-evm.c | 2 +-
arch/arm/mach-davinci/board-dm644x-evm.c | 2 +-
arch/arm/mach-davinci/board-dm646x-evm.c | 4 ++--
arch/arm/mach-davinci/board-mityomapl138.c | 2 +-
arch/arm/mach-davinci/board-neuros-osd2.c | 2 +-
arch/arm/mach-davinci/board-omapl138-hawk.c | 2 +-
arch/arm/mach-davinci/board-sffsdr.c | 2 +-
arch/arm/mach-davinci/board-tnetv107x-evm.c | 2 +-
arch/arm/mach-davinci/include/mach/common.h | 4 +---
arch/arm/mach-davinci/time.c | 7 +------
arch/arm/mach-dove/cm-a510.c | 2 +-
arch/arm/mach-dove/common.c | 8 ++------
arch/arm/mach-dove/common.h | 2 +-
arch/arm/mach-dove/dove-db-setup.c | 2 +-
arch/arm/mach-ebsa110/core.c | 8 ++------
arch/arm/mach-ep93xx/adssphere.c | 2 +-
arch/arm/mach-ep93xx/core.c | 6 +-----
arch/arm/mach-ep93xx/edb93xx.c | 16 ++++++++--------
arch/arm/mach-ep93xx/gesbc9312.c | 2 +-
arch/arm/mach-ep93xx/include/mach/platform.h | 2 +-
arch/arm/mach-ep93xx/micro9.c | 8 ++++----
arch/arm/mach-ep93xx/simone.c | 2 +-
arch/arm/mach-ep93xx/snappercl15.c | 2 +-
arch/arm/mach-ep93xx/ts72xx.c | 2 +-
arch/arm/mach-ep93xx/vision_ep9307.c | 2 +-
arch/arm/mach-exynos/common.h | 2 +-
arch/arm/mach-exynos/mach-armlex4210.c | 2 +-
arch/arm/mach-exynos/mach-exynos4-dt.c | 2 +-
arch/arm/mach-exynos/mach-exynos5-dt.c | 2 +-
arch/arm/mach-exynos/mach-nuri.c | 2 +-
arch/arm/mach-exynos/mach-origen.c | 2 +-
arch/arm/mach-exynos/mach-smdk4x12.c | 4 ++--
arch/arm/mach-exynos/mach-smdkv310.c | 4 ++--
arch/arm/mach-exynos/mach-universal_c210.c | 2 +-
arch/arm/mach-exynos/mct.c | 6 +-----
| 2 +-
| 4 ++--
| 6 +-----
| 2 +-
| 6 +-----
| 2 +-
| 2 +-
arch/arm/mach-gemini/board-nas4220b.c | 6 +-----
arch/arm/mach-gemini/board-rut1xx.c | 6 +-----
arch/arm/mach-gemini/board-wbd111.c | 6 +-----
arch/arm/mach-gemini/board-wbd222.c | 6 +-----
arch/arm/mach-h720x/common.h | 4 ++--
arch/arm/mach-h720x/cpu-h7201.c | 6 +-----
arch/arm/mach-h720x/cpu-h7202.c | 6 +-----
arch/arm/mach-h720x/h7201-eval.c | 2 +-
arch/arm/mach-h720x/h7202-eval.c | 2 +-
arch/arm/mach-highbank/highbank.c | 6 +-----
arch/arm/mach-imx/imx27-dt.c | 16 ++++++----------
arch/arm/mach-imx/imx31-dt.c | 11 +----------
arch/arm/mach-imx/imx51-dt.c | 16 ++++++----------
arch/arm/mach-imx/mach-apf9328.c | 6 +-----
arch/arm/mach-imx/mach-armadillo5x0.c | 6 +-----
arch/arm/mach-imx/mach-bug.c | 6 +-----
arch/arm/mach-imx/mach-cpuimx27.c | 6 +-----
arch/arm/mach-imx/mach-cpuimx35.c | 6 +-----
arch/arm/mach-imx/mach-cpuimx51sd.c | 6 +-----
arch/arm/mach-imx/mach-eukrea_cpuimx25.c | 6 +-----
arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 6 +-----
arch/arm/mach-imx/mach-imx27ipcam.c | 6 +-----
arch/arm/mach-imx/mach-imx27lite.c | 6 +-----
arch/arm/mach-imx/mach-imx53.c | 16 ++++++----------
arch/arm/mach-imx/mach-imx6q.c | 6 +-----
arch/arm/mach-imx/mach-kzm_arm11_01.c | 6 +-----
arch/arm/mach-imx/mach-mx1ads.c | 8 ++------
arch/arm/mach-imx/mach-mx21ads.c | 6 +-----
arch/arm/mach-imx/mach-mx25_3ds.c | 6 +-----
arch/arm/mach-imx/mach-mx27_3ds.c | 6 +-----
arch/arm/mach-imx/mach-mx27ads.c | 6 +-----
arch/arm/mach-imx/mach-mx31_3ds.c | 6 +-----
arch/arm/mach-imx/mach-mx31ads.c | 6 +-----
arch/arm/mach-imx/mach-mx31lilly.c | 6 +-----
arch/arm/mach-imx/mach-mx31lite.c | 6 +-----
arch/arm/mach-imx/mach-mx31moboard.c | 6 +-----
arch/arm/mach-imx/mach-mx35_3ds.c | 6 +-----
arch/arm/mach-imx/mach-mx50_rdp.c | 6 +-----
arch/arm/mach-imx/mach-mx51_3ds.c | 6 +-----
arch/arm/mach-imx/mach-mx51_babbage.c | 6 +-----
arch/arm/mach-imx/mach-mxt_td60.c | 6 +-----
arch/arm/mach-imx/mach-pca100.c | 6 +-----
arch/arm/mach-imx/mach-pcm037.c | 6 +-----
arch/arm/mach-imx/mach-pcm038.c | 6 +-----
arch/arm/mach-imx/mach-pcm043.c | 6 +-----
arch/arm/mach-imx/mach-qong.c | 6 +-----
arch/arm/mach-imx/mach-scb9328.c | 6 +-----
arch/arm/mach-imx/mach-vpr200.c | 6 +-----
arch/arm/mach-integrator/integrator_ap.c | 16 ++++------------
arch/arm/mach-integrator/integrator_cp.c | 16 ++++------------
arch/arm/mach-iop13xx/iq81340mc.c | 6 +-----
arch/arm/mach-iop13xx/iq81340sc.c | 6 +-----
arch/arm/mach-iop32x/em7210.c | 6 +-----
arch/arm/mach-iop32x/glantank.c | 6 +-----
arch/arm/mach-iop32x/iq31244.c | 8 ++------
arch/arm/mach-iop32x/iq80321.c | 6 +-----
arch/arm/mach-iop32x/n2100.c | 6 +-----
arch/arm/mach-iop33x/iq80331.c | 6 +-----
arch/arm/mach-iop33x/iq80332.c | 6 +-----
arch/arm/mach-ixp4xx/avila-setup.c | 4 ++--
arch/arm/mach-ixp4xx/common.c | 4 ----
arch/arm/mach-ixp4xx/coyote-setup.c | 4 ++--
arch/arm/mach-ixp4xx/dsmg600-setup.c | 6 +-----
arch/arm/mach-ixp4xx/fsg-setup.c | 2 +-
arch/arm/mach-ixp4xx/gateway7001-setup.c | 2 +-
arch/arm/mach-ixp4xx/goramo_mlr.c | 2 +-
arch/arm/mach-ixp4xx/gtwx5715-setup.c | 2 +-
arch/arm/mach-ixp4xx/include/mach/platform.h | 3 ---
arch/arm/mach-ixp4xx/ixdp425-setup.c | 8 ++++----
arch/arm/mach-ixp4xx/nas100d-setup.c | 2 +-
arch/arm/mach-ixp4xx/nslu2-setup.c | 6 +-----
arch/arm/mach-ixp4xx/omixp-setup.c | 6 +++---
arch/arm/mach-ixp4xx/vulcan-setup.c | 2 +-
arch/arm/mach-ixp4xx/wg302v2-setup.c | 2 +-
arch/arm/mach-kirkwood/board-dt.c | 2 +-
arch/arm/mach-kirkwood/common.c | 6 +-----
arch/arm/mach-kirkwood/common.h | 2 +-
arch/arm/mach-kirkwood/d2net_v2-setup.c | 2 +-
arch/arm/mach-kirkwood/db88f6281-bp-setup.c | 2 +-
arch/arm/mach-kirkwood/dockstar-setup.c | 2 +-
arch/arm/mach-kirkwood/guruplug-setup.c | 2 +-
arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c | 2 +-
arch/arm/mach-kirkwood/netspace_v2-setup.c | 6 +++---
arch/arm/mach-kirkwood/netxbig_v2-setup.c | 4 ++--
arch/arm/mach-kirkwood/openrd-setup.c | 6 +++---
arch/arm/mach-kirkwood/rd88f6192-nas-setup.c | 2 +-
arch/arm/mach-kirkwood/rd88f6281-setup.c | 2 +-
arch/arm/mach-kirkwood/sheevaplug-setup.c | 4 ++--
arch/arm/mach-kirkwood/t5325-setup.c | 2 +-
arch/arm/mach-kirkwood/ts219-setup.c | 2 +-
arch/arm/mach-kirkwood/ts41x-setup.c | 2 +-
arch/arm/mach-ks8695/board-acs5k.c | 2 +-
arch/arm/mach-ks8695/board-dsm320.c | 2 +-
arch/arm/mach-ks8695/board-micrel.c | 2 +-
arch/arm/mach-ks8695/board-og.c | 10 +++++-----
arch/arm/mach-ks8695/board-sg.c | 6 +++---
arch/arm/mach-ks8695/generic.h | 2 +-
arch/arm/mach-ks8695/time.c | 6 +-----
arch/arm/mach-lpc32xx/common.h | 2 +-
arch/arm/mach-lpc32xx/phy3250.c | 2 +-
arch/arm/mach-lpc32xx/timer.c | 7 +------
arch/arm/mach-mmp/aspenite.c | 4 ++--
arch/arm/mach-mmp/avengers_lite.c | 2 +-
arch/arm/mach-mmp/brownstone.c | 2 +-
arch/arm/mach-mmp/common.h | 2 --
arch/arm/mach-mmp/flint.c | 2 +-
arch/arm/mach-mmp/gplugd.c | 2 +-
arch/arm/mach-mmp/include/mach/mmp2.h | 4 +---
arch/arm/mach-mmp/include/mach/pxa168.h | 4 +---
arch/arm/mach-mmp/include/mach/pxa910.h | 4 +---
arch/arm/mach-mmp/jasper.c | 2 +-
arch/arm/mach-mmp/mmp-dt.c | 8 ++------
arch/arm/mach-mmp/mmp2-dt.c | 6 +-----
arch/arm/mach-mmp/mmp2.c | 6 +-----
arch/arm/mach-mmp/pxa168.c | 6 +-----
arch/arm/mach-mmp/pxa910.c | 6 +-----
arch/arm/mach-mmp/tavorevb.c | 2 +-
arch/arm/mach-mmp/teton_bga.c | 2 +-
arch/arm/mach-mmp/ttc_dkb.c | 2 +-
arch/arm/mach-msm/board-dt-8660.c | 2 +-
arch/arm/mach-msm/board-dt-8960.c | 2 +-
arch/arm/mach-msm/board-halibut.c | 2 +-
arch/arm/mach-msm/board-mahimahi.c | 4 ++--
arch/arm/mach-msm/board-msm7x30.c | 6 +++---
arch/arm/mach-msm/board-qsd8x50.c | 4 ++--
arch/arm/mach-msm/board-sapphire.c | 4 ++--
arch/arm/mach-msm/board-trout.c | 2 +-
arch/arm/mach-msm/common.h | 8 ++++----
arch/arm/mach-msm/timer.c | 24 ++++--------------------
arch/arm/mach-mv78xx0/buffalo-wxl-setup.c | 2 +-
arch/arm/mach-mv78xx0/common.c | 6 +-----
arch/arm/mach-mv78xx0/common.h | 2 +-
arch/arm/mach-mv78xx0/db78x00-bp-setup.c | 2 +-
arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 2 +-
arch/arm/mach-mvebu/armada-370-xp.c | 6 +-----
arch/arm/mach-mxs/mach-mxs.c | 12 ++----------
arch/arm/mach-netx/generic.h | 3 +--
arch/arm/mach-netx/nxdb500.c | 2 +-
arch/arm/mach-netx/nxdkn.c | 2 +-
arch/arm/mach-netx/nxeb500hmi.c | 2 +-
arch/arm/mach-netx/time.c | 6 +-----
arch/arm/mach-nomadik/board-nhk8815.c | 6 +-----
arch/arm/mach-omap1/board-ams-delta.c | 2 +-
arch/arm/mach-omap1/board-fsample.c | 2 +-
arch/arm/mach-omap1/board-generic.c | 2 +-
arch/arm/mach-omap1/board-h2.c | 2 +-
arch/arm/mach-omap1/board-h3.c | 2 +-
arch/arm/mach-omap1/board-htcherald.c | 2 +-
arch/arm/mach-omap1/board-innovator.c | 2 +-
arch/arm/mach-omap1/board-nokia770.c | 2 +-
arch/arm/mach-omap1/board-osk.c | 2 +-
arch/arm/mach-omap1/board-palmte.c | 2 +-
arch/arm/mach-omap1/board-palmtt.c | 2 +-
arch/arm/mach-omap1/board-palmz71.c | 2 +-
arch/arm/mach-omap1/board-perseus2.c | 2 +-
arch/arm/mach-omap1/board-sx1.c | 2 +-
arch/arm/mach-omap1/board-voiceblue.c | 2 +-
arch/arm/mach-omap1/common.h | 2 +-
arch/arm/mach-omap1/time.c | 6 +-----
arch/arm/mach-omap2/board-2430sdp.c | 2 +-
arch/arm/mach-omap2/board-3430sdp.c | 2 +-
arch/arm/mach-omap2/board-3630sdp.c | 2 +-
arch/arm/mach-omap2/board-4430sdp.c | 2 +-
arch/arm/mach-omap2/board-am3517crane.c | 2 +-
arch/arm/mach-omap2/board-am3517evm.c | 2 +-
arch/arm/mach-omap2/board-apollon.c | 2 +-
arch/arm/mach-omap2/board-cm-t35.c | 4 ++--
arch/arm/mach-omap2/board-cm-t3517.c | 2 +-
arch/arm/mach-omap2/board-devkit8000.c | 2 +-
arch/arm/mach-omap2/board-generic.c | 12 ++++++------
arch/arm/mach-omap2/board-h4.c | 2 +-
arch/arm/mach-omap2/board-igep0020.c | 4 ++--
arch/arm/mach-omap2/board-ldp.c | 2 +-
arch/arm/mach-omap2/board-n8x0.c | 6 +++---
arch/arm/mach-omap2/board-omap3beagle.c | 2 +-
arch/arm/mach-omap2/board-omap3evm.c | 2 +-
arch/arm/mach-omap2/board-omap3logic.c | 4 ++--
arch/arm/mach-omap2/board-omap3pandora.c | 2 +-
arch/arm/mach-omap2/board-omap3stalker.c | 2 +-
arch/arm/mach-omap2/board-omap3touchbook.c | 2 +-
arch/arm/mach-omap2/board-omap4panda.c | 2 +-
arch/arm/mach-omap2/board-overo.c | 2 +-
arch/arm/mach-omap2/board-rm680.c | 4 ++--
arch/arm/mach-omap2/board-rx51.c | 2 +-
arch/arm/mach-omap2/board-ti8168evm.c | 4 ++--
arch/arm/mach-omap2/board-zoom.c | 4 ++--
arch/arm/mach-omap2/common.h | 12 ++++++------
arch/arm/mach-omap2/timer.c | 17 +++--------------
arch/arm/mach-orion5x/common.c | 6 +-----
arch/arm/mach-orion5x/common.h | 2 +-
arch/arm/mach-orion5x/d2net-setup.c | 4 ++--
arch/arm/mach-orion5x/db88f5281-setup.c | 2 +-
arch/arm/mach-orion5x/dns323-setup.c | 2 +-
arch/arm/mach-orion5x/edmini_v2-setup.c | 2 +-
arch/arm/mach-orion5x/kurobox_pro-setup.c | 4 ++--
arch/arm/mach-orion5x/ls-chl-setup.c | 2 +-
arch/arm/mach-orion5x/ls_hgl-setup.c | 2 +-
arch/arm/mach-orion5x/lsmini-setup.c | 2 +-
arch/arm/mach-orion5x/mss2-setup.c | 2 +-
arch/arm/mach-orion5x/mv2120-setup.c | 2 +-
arch/arm/mach-orion5x/net2big-setup.c | 2 +-
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c | 2 +-
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c | 2 +-
arch/arm/mach-orion5x/rd88f5182-setup.c | 2 +-
arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c | 2 +-
arch/arm/mach-orion5x/terastation_pro2-setup.c | 2 +-
arch/arm/mach-orion5x/ts209-setup.c | 2 +-
arch/arm/mach-orion5x/ts409-setup.c | 2 +-
arch/arm/mach-orion5x/ts78xx-setup.c | 2 +-
arch/arm/mach-orion5x/wnr854t-setup.c | 2 +-
arch/arm/mach-orion5x/wrt350n-v2-setup.c | 2 +-
arch/arm/mach-picoxcell/common.c | 2 +-
arch/arm/mach-picoxcell/common.h | 2 +-
arch/arm/mach-prima2/common.c | 2 +-
arch/arm/mach-prima2/common.h | 2 +-
arch/arm/mach-prima2/timer.c | 8 ++------
arch/arm/mach-pxa/balloon3.c | 2 +-
arch/arm/mach-pxa/capc7117.c | 2 +-
arch/arm/mach-pxa/cm-x2xx.c | 2 +-
arch/arm/mach-pxa/cm-x300.c | 2 +-
arch/arm/mach-pxa/colibri-pxa270.c | 4 ++--
arch/arm/mach-pxa/colibri-pxa300.c | 2 +-
arch/arm/mach-pxa/colibri-pxa320.c | 2 +-
arch/arm/mach-pxa/corgi.c | 6 +++---
arch/arm/mach-pxa/csb726.c | 2 +-
arch/arm/mach-pxa/em-x270.c | 4 ++--
arch/arm/mach-pxa/eseries.c | 12 ++++++------
arch/arm/mach-pxa/ezx.c | 12 ++++++------
arch/arm/mach-pxa/generic.h | 3 +--
arch/arm/mach-pxa/gumstix.c | 2 +-
arch/arm/mach-pxa/h5000.c | 2 +-
arch/arm/mach-pxa/himalaya.c | 2 +-
arch/arm/mach-pxa/hx4700.c | 2 +-
arch/arm/mach-pxa/icontrol.c | 2 +-
arch/arm/mach-pxa/idp.c | 2 +-
arch/arm/mach-pxa/littleton.c | 2 +-
arch/arm/mach-pxa/lpd270.c | 2 +-
arch/arm/mach-pxa/lubbock.c | 2 +-
arch/arm/mach-pxa/magician.c | 2 +-
arch/arm/mach-pxa/mainstone.c | 2 +-
arch/arm/mach-pxa/mioa701.c | 2 +-
arch/arm/mach-pxa/mp900.c | 2 +-
arch/arm/mach-pxa/palmld.c | 2 +-
arch/arm/mach-pxa/palmt5.c | 2 +-
arch/arm/mach-pxa/palmtc.c | 2 +-
arch/arm/mach-pxa/palmte2.c | 2 +-
arch/arm/mach-pxa/palmtreo.c | 4 ++--
arch/arm/mach-pxa/palmtx.c | 2 +-
arch/arm/mach-pxa/palmz72.c | 2 +-
arch/arm/mach-pxa/pcm027.c | 2 +-
arch/arm/mach-pxa/poodle.c | 2 +-
arch/arm/mach-pxa/pxa-dt.c | 2 +-
arch/arm/mach-pxa/raumfeld.c | 6 +++---
arch/arm/mach-pxa/saar.c | 2 +-
arch/arm/mach-pxa/saarb.c | 2 +-
arch/arm/mach-pxa/spitz.c | 6 +++---
arch/arm/mach-pxa/stargate2.c | 4 ++--
arch/arm/mach-pxa/tavorevb.c | 2 +-
arch/arm/mach-pxa/tavorevb3.c | 2 +-
arch/arm/mach-pxa/time.c | 6 +-----
arch/arm/mach-pxa/tosa.c | 2 +-
arch/arm/mach-pxa/trizeps4.c | 4 ++--
arch/arm/mach-pxa/viper.c | 2 +-
arch/arm/mach-pxa/vpac270.c | 2 +-
arch/arm/mach-pxa/xcep.c | 2 +-
arch/arm/mach-pxa/z2.c | 2 +-
arch/arm/mach-pxa/zeus.c | 2 +-
arch/arm/mach-pxa/zylonite.c | 2 +-
arch/arm/mach-realview/realview_eb.c | 6 +-----
arch/arm/mach-realview/realview_pb1176.c | 6 +-----
arch/arm/mach-realview/realview_pb11mp.c | 6 +-----
arch/arm/mach-realview/realview_pba8.c | 6 +-----
arch/arm/mach-realview/realview_pbx.c | 6 +-----
arch/arm/mach-rpc/riscpc.c | 4 ++--
arch/arm/mach-rpc/time.c | 7 +------
arch/arm/mach-s3c24xx/mach-amlm5900.c | 2 +-
arch/arm/mach-s3c24xx/mach-anubis.c | 2 +-
arch/arm/mach-s3c24xx/mach-at2440evb.c | 2 +-
arch/arm/mach-s3c24xx/mach-bast.c | 2 +-
arch/arm/mach-s3c24xx/mach-gta02.c | 2 +-
arch/arm/mach-s3c24xx/mach-h1940.c | 2 +-
arch/arm/mach-s3c24xx/mach-jive.c | 2 +-
arch/arm/mach-s3c24xx/mach-mini2440.c | 2 +-
arch/arm/mach-s3c24xx/mach-n30.c | 4 ++--
arch/arm/mach-s3c24xx/mach-nexcoder.c | 2 +-
arch/arm/mach-s3c24xx/mach-osiris.c | 2 +-
arch/arm/mach-s3c24xx/mach-otom.c | 2 +-
arch/arm/mach-s3c24xx/mach-qt2410.c | 2 +-
arch/arm/mach-s3c24xx/mach-rx1950.c | 2 +-
arch/arm/mach-s3c24xx/mach-rx3715.c | 2 +-
arch/arm/mach-s3c24xx/mach-smdk2410.c | 2 +-
arch/arm/mach-s3c24xx/mach-smdk2413.c | 6 +++---
arch/arm/mach-s3c24xx/mach-smdk2416.c | 2 +-
arch/arm/mach-s3c24xx/mach-smdk2440.c | 2 +-
arch/arm/mach-s3c24xx/mach-smdk2443.c | 2 +-
arch/arm/mach-s3c24xx/mach-tct_hammer.c | 2 +-
arch/arm/mach-s3c24xx/mach-vr1000.c | 2 +-
arch/arm/mach-s3c24xx/mach-vstms.c | 2 +-
arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-hmt.c | 2 +-
arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-ncp.c | 2 +-
arch/arm/mach-s3c64xx/mach-real6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-smartq5.c | 2 +-
arch/arm/mach-s3c64xx/mach-smartq7.c | 2 +-
arch/arm/mach-s3c64xx/mach-smdk6400.c | 2 +-
arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +-
arch/arm/mach-s5p64x0/mach-smdk6440.c | 2 +-
arch/arm/mach-s5p64x0/mach-smdk6450.c | 2 +-
arch/arm/mach-s5pc100/mach-smdkc100.c | 2 +-
arch/arm/mach-s5pv210/mach-aquila.c | 2 +-
arch/arm/mach-s5pv210/mach-goni.c | 2 +-
arch/arm/mach-s5pv210/mach-smdkc110.c | 2 +-
arch/arm/mach-s5pv210/mach-smdkv210.c | 2 +-
arch/arm/mach-s5pv210/mach-torbreck.c | 2 +-
arch/arm/mach-sa1100/assabet.c | 2 +-
arch/arm/mach-sa1100/badge4.c | 2 +-
arch/arm/mach-sa1100/cerf.c | 2 +-
arch/arm/mach-sa1100/collie.c | 2 +-
arch/arm/mach-sa1100/generic.h | 4 +---
arch/arm/mach-sa1100/h3100.c | 2 +-
arch/arm/mach-sa1100/h3600.c | 2 +-
arch/arm/mach-sa1100/hackkit.c | 2 +-
arch/arm/mach-sa1100/jornada720.c | 2 +-
arch/arm/mach-sa1100/lart.c | 2 +-
arch/arm/mach-sa1100/nanoengine.c | 2 +-
arch/arm/mach-sa1100/pleb.c | 2 +-
arch/arm/mach-sa1100/shannon.c | 2 +-
arch/arm/mach-sa1100/simpad.c | 2 +-
arch/arm/mach-sa1100/time.c | 6 +-----
arch/arm/mach-shark/core.c | 6 +-----
arch/arm/mach-shmobile/board-ag5evm.c | 2 +-
arch/arm/mach-shmobile/board-ap4evb.c | 2 +-
arch/arm/mach-shmobile/board-armadillo800eva.c | 5 +----
arch/arm/mach-shmobile/board-bonito.c | 5 +----
arch/arm/mach-shmobile/board-kota2.c | 2 +-
arch/arm/mach-shmobile/board-kzm9d.c | 2 +-
arch/arm/mach-shmobile/board-kzm9g.c | 2 +-
arch/arm/mach-shmobile/board-mackerel.c | 2 +-
arch/arm/mach-shmobile/board-marzen.c | 2 +-
arch/arm/mach-shmobile/include/mach/common.h | 5 ++++-
arch/arm/mach-shmobile/setup-emev2.c | 2 +-
arch/arm/mach-shmobile/setup-r8a7740.c | 11 +----------
arch/arm/mach-shmobile/setup-r8a7779.c | 5 +----
arch/arm/mach-shmobile/setup-sh7372.c | 7 ++-----
arch/arm/mach-shmobile/setup-sh73a0.c | 5 +----
arch/arm/mach-shmobile/timer.c | 6 +-----
arch/arm/mach-socfpga/socfpga.c | 2 +-
arch/arm/mach-spear13xx/include/mach/generic.h | 2 +-
arch/arm/mach-spear13xx/spear1310.c | 2 +-
arch/arm/mach-spear13xx/spear1340.c | 2 +-
arch/arm/mach-spear13xx/spear13xx.c | 6 +-----
arch/arm/mach-spear3xx/include/mach/generic.h | 2 +-
arch/arm/mach-spear3xx/spear300.c | 2 +-
arch/arm/mach-spear3xx/spear310.c | 2 +-
arch/arm/mach-spear3xx/spear320.c | 2 +-
arch/arm/mach-spear3xx/spear3xx.c | 6 +-----
arch/arm/mach-spear6xx/spear6xx.c | 8 ++------
arch/arm/mach-tegra/board-dt-tegra20.c | 2 +-
arch/arm/mach-tegra/board-dt-tegra30.c | 2 +-
arch/arm/mach-tegra/board.h | 2 +-
arch/arm/mach-tegra/timer.c | 6 +-----
arch/arm/mach-u300/core.c | 2 +-
arch/arm/mach-u300/timer.c | 10 +---------
arch/arm/mach-u300/timer.h | 2 +-
arch/arm/mach-ux500/board-mop500.c | 8 ++++----
arch/arm/mach-ux500/cpu-db8500.c | 2 +-
arch/arm/mach-ux500/include/mach/setup.h | 3 +--
arch/arm/mach-ux500/timer.c | 6 +-----
arch/arm/mach-versatile/core.c | 7 +------
arch/arm/mach-versatile/core.h | 2 +-
arch/arm/mach-versatile/versatile_ab.c | 2 +-
arch/arm/mach-versatile/versatile_dt.c | 2 +-
arch/arm/mach-versatile/versatile_pb.c | 2 +-
arch/arm/mach-vexpress/v2m.c | 12 ++----------
arch/arm/mach-vt8500/vt8500.c | 6 +-----
arch/arm/mach-w90x900/mach-nuc910evb.c | 2 +-
arch/arm/mach-w90x900/mach-nuc950evb.c | 2 +-
arch/arm/mach-w90x900/mach-nuc960evb.c | 2 +-
arch/arm/mach-w90x900/nuc9xx.h | 3 +--
arch/arm/mach-w90x900/time.c | 6 +-----
arch/arm/mach-zynq/common.c | 2 +-
arch/arm/mach-zynq/common.h | 2 +-
arch/arm/mach-zynq/timer.c | 9 +--------
arch/arm/plat-samsung/include/plat/cpu.h | 3 +--
arch/arm/plat-samsung/include/plat/s5p-time.h | 2 +-
arch/arm/plat-samsung/s5p-time.c | 6 +-----
arch/arm/plat-samsung/time.c | 6 +-----
drivers/clocksource/bcm2835_timer.c | 6 +-----
drivers/clocksource/dw_apb_timer_of.c | 6 +-----
include/linux/bcm2835_timer.h | 2 +-
include/linux/dw_apb_timer.h | 2 +-
494 files changed, 624 insertions(+), 1201 deletions(-)
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 917d4fc..308ad7d 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -12,7 +12,6 @@
struct tag;
struct meminfo;
-struct sys_timer;
struct pt_regs;
struct smp_operations;
#ifdef CONFIG_SMP
@@ -48,7 +47,7 @@ struct machine_desc {
void (*map_io)(void);/* IO mapping function */
void (*init_early)(void);
void (*init_irq)(void);
- struct sys_timer *timer; /* system tick timer */
+ void (*init_time)(void);
void (*init_machine)(void);
void (*init_late)(void);
#ifdef CONFIG_MULTI_IRQ_HANDLER
diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h
index d316d76..90c12e1 100644
--- a/arch/arm/include/asm/mach/time.h
+++ b/arch/arm/include/asm/mach/time.h
@@ -10,22 +10,6 @@
#ifndef __ASM_ARM_MACH_TIME_H
#define __ASM_ARM_MACH_TIME_H
-/*
- * This is our kernel timer structure.
- *
- * - init
- * Initialise the kernels jiffy timer source, claim interrupt
- * using setup_irq. This is called early on during initialisation
- * while interrupts are still disabled on the local CPU.
- * - offset
- * Return the timer offset in microseconds since the last timer
- * interrupt. Note: this must take account of any unprocessed
- * timer interrupt which may be pending.
- */
-struct sys_timer {
- void (*init)(void);
-};
-
extern void timer_tick(void);
struct timespec;
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index 0b51a7c..955d92d 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -30,11 +30,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-/*
- * Our system timer.
- */
-static struct sys_timer *system_timer;
-
#if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE) || \
defined(CONFIG_NVRAM) || defined(CONFIG_NVRAM_MODULE)
/* this needs a better home */
@@ -120,8 +115,6 @@ int __init register_persistent_clock(clock_access_fn read_boot,
void __init time_init(void)
{
- system_timer = machine_desc->timer;
- system_timer->init();
+ machine_desc->init_time();
sched_clock_postinit();
}
-
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index a8fce3c..3d2aa6f 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -628,6 +628,6 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
.init_irq = omap1_init_irq,
.init_machine = ams_delta_init,
.init_late = ams_delta_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 8b5800a..7a0f1f9 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -365,6 +365,6 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
.init_irq = omap1_init_irq,
.init_machine = omap_fsample_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 608e7d2..e1d9171 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -84,6 +84,6 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
.init_irq = omap1_init_irq,
.init_machine = omap_generic_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 9134b64..a7ed0ff 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -462,6 +462,6 @@ MACHINE_START(OMAP_H2, "TI-H2")
.init_irq = omap1_init_irq,
.init_machine = h2_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index bf213d1..ed08d75 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -455,6 +455,6 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
.init_irq = omap1_init_irq,
.init_machine = h3_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 356f816..35a2379 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -603,6 +603,6 @@ MACHINE_START(HERALD, "HTC Herald")
.init_irq = omap1_init_irq,
.init_machine = htcherald_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index c66334f..04513f5 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -459,6 +459,6 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
.init_irq = omap1_init_irq,
.init_machine = innovator_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 3e8ead6..d9fdb8a 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -254,6 +254,6 @@ MACHINE_START(NOKIA770, "Nokia 770")
.init_irq = omap1_init_irq,
.init_machine = omap_nokia770_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 872ea47..a7ce692 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -609,6 +609,6 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
.init_irq = omap1_init_irq,
.init_machine = osk_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 584b6fa..9337ffc 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -268,6 +268,6 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
.init_irq = omap1_init_irq,
.init_machine = omap_palmte_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index fbc986b..a9a88f9 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -314,6 +314,6 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
.init_irq = omap1_init_irq,
.init_machine = omap_palmtt_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 60d917a..e51b12c 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -330,6 +330,6 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
.init_irq = omap1_init_irq,
.init_machine = omap_palmz71_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 030bd48..f354f48 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -327,6 +327,6 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
.init_irq = omap1_init_irq,
.init_machine = omap_perseus2_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 1ebc7e0..d6c0c07 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -407,6 +407,6 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
.init_irq = omap1_init_irq,
.init_machine = omap_sx1_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = omap1_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index abf705f..6c116e1 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -289,6 +289,6 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
.init_irq = omap1_init_irq,
.init_machine = voiceblue_init,
.init_late = omap1_init_late,
- .timer = &omap1_timer,
+ .init_time = omap1_timer_init,
.restart = voiceblue_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index d6ac18d..933016b 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -76,7 +76,7 @@ extern void __init omap_check_revision(void);
extern void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd,
unsigned int ctrl);
-extern struct sys_timer omap1_timer;
+extern void omap1_timer_init(void);
#ifdef CONFIG_OMAP_32K_TIMER
extern int omap_32k_timer_init(void);
#else
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 4d4816f..1d4512f 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -236,12 +236,8 @@ static inline void omap_mpu_timer_init(void)
* Timer initialization
* ---------------------------------------------------------------------------
*/
-static void __init omap1_timer_init(void)
+void __init omap1_timer_init(void)
{
if (omap_32k_timer_init() != 0)
omap_mpu_timer_init();
}
-
-struct sys_timer omap1_timer = {
- .init = omap1_timer_init,
-};
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 3fc6d83..717c5b0 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -285,6 +285,6 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_2430sdp_init,
.init_late = omap2430_init_late,
- .timer = &omap2_timer,
+ .init_time = omap2_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 79fd904..d11c1d8 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -596,6 +596,6 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_3430sdp_init,
.init_late = omap3430_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 81871b1..d819935 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -211,6 +211,6 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_sdp_init,
.init_late = omap3630_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index fd80d97..45086a4 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -880,6 +880,6 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
.handle_irq = gic_handle_irq,
.init_machine = omap_4430sdp_init,
.init_late = omap4430_init_late,
- .timer = &omap4_timer,
+ .init_time = omap4_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 603503c..95012fd 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -92,6 +92,6 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
.handle_irq = omap3_intc_handle_irq,
.init_machine = am3517_crane_init,
.init_late = am35xx_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 96d6c5a..4994f9f 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -392,6 +392,6 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
.handle_irq = omap3_intc_handle_irq,
.init_machine = am3517_evm_init,
.init_late = am35xx_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 64cf1bd..ee7b610 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -337,6 +337,6 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_apollon_init,
.init_late = omap2420_init_late,
- .timer = &omap2_timer,
+ .init_time = omap2_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index cf9449b..5fbd927 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -752,7 +752,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
.handle_irq = omap3_intc_handle_irq,
.init_machine = cm_t35_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
@@ -765,6 +765,6 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
.handle_irq = omap3_intc_handle_irq,
.init_machine = cm_t3730_init,
.init_late = omap3630_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 2786647..b3baf67 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -297,6 +297,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
.handle_irq = omap3_intc_handle_irq,
.init_machine = cm_t3517_init,
.init_late = am35xx_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 933479e..ee5e61f 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -642,6 +642,6 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
.handle_irq = omap3_intc_handle_irq,
.init_machine = devkit8000_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_secure_timer,
+ .init_time = omap3_secure_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 601ecdf..2787cb6 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -55,7 +55,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
.init_irq = omap_intc_of_init,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
- .timer = &omap2_timer,
+ .init_time = omap2_timer_init,
.dt_compat = omap242x_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
@@ -74,7 +74,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
.init_irq = omap_intc_of_init,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
- .timer = &omap2_timer,
+ .init_time = omap2_timer_init,
.dt_compat = omap243x_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
@@ -93,7 +93,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
.init_irq = omap_intc_of_init,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_generic_init,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.dt_compat = omap3_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
@@ -112,7 +112,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
.init_irq = omap_intc_of_init,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_generic_init,
- .timer = &omap3_am33xx_timer,
+ .init_time = omap3_am33xx_timer_init,
.dt_compat = am33xx_boards_compat,
MACHINE_END
#endif
@@ -132,7 +132,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
.handle_irq = gic_handle_irq,
.init_machine = omap_generic_init,
.init_late = omap4430_init_late,
- .timer = &omap4_timer,
+ .init_time = omap4_timer_init,
.dt_compat = omap4_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
@@ -152,7 +152,7 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
.init_irq = omap_gic_of_init,
.handle_irq = gic_handle_irq,
.init_machine = omap_generic_init,
- .timer = &omap5_timer,
+ .init_time = omap5_timer_init,
.dt_compat = omap5_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index bd11b0a..c87df7a 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -385,6 +385,6 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_h4_init,
.init_late = omap2420_init_late,
- .timer = &omap2_timer,
+ .init_time = omap2_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index dbc705a..d524d61 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -650,7 +650,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = igep_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
@@ -663,6 +663,6 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
.handle_irq = omap3_intc_handle_irq,
.init_machine = igep_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 1164b10..95d546f 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -435,6 +435,6 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_ldp_init,
.init_late = omap3430_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index e3efcb8..5dbc236 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -689,7 +689,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
.handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.init_late = omap2420_init_late,
- .timer = &omap2_timer,
+ .init_time = omap2_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
@@ -702,7 +702,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
.handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.init_late = omap2420_init_late,
- .timer = &omap2_timer,
+ .init_time = omap2_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
@@ -715,6 +715,6 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
.handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.init_late = omap2420_init_late,
- .timer = &omap2_timer,
+ .init_time = omap2_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 5a3800d..c11ce03 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -544,6 +544,6 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_beagle_init,
.init_late = omap3_init_late,
- .timer = &omap3_secure_timer,
+ .init_time = omap3_secure_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 3c0b9a9..cffca23 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -756,6 +756,6 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_evm_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index e84e2a8..21062e7 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -231,7 +231,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3logic_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
@@ -244,6 +244,6 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3logic_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index ce31bd3..559580a 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -618,6 +618,6 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3pandora_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index ba11245..0502d80 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -426,6 +426,6 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_stalker_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_secure_timer,
+ .init_time = omap3_secure_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index a225d81..fc6a322 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -386,6 +386,6 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_touchbook_init,
.init_late = omap3430_init_late,
- .timer = &omap3_secure_timer,
+ .init_time = omap3_secure_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 8c00b99..c7cfed5 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -523,6 +523,6 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
.handle_irq = gic_handle_irq,
.init_machine = omap4_panda_init,
.init_late = omap4430_init_late,
- .timer = &omap4_timer,
+ .init_time = omap4_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 1cfb037..a3914ab 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -552,6 +552,6 @@ MACHINE_START(OVERO, "Gumstix Overo")
.handle_irq = omap3_intc_handle_irq,
.init_machine = overo_init,
.init_late = omap35xx_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 1997e0e..a79d140 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -147,7 +147,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = rm680_init,
.init_late = omap3630_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
@@ -160,6 +160,6 @@ MACHINE_START(NOKIA_RM696, "Nokia RM-696 board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = rm680_init,
.init_late = omap3630_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index c388aec..4904da8 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -126,6 +126,6 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = rx51_init,
.init_late = omap3430_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index 5e672c2..36460e1 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -43,7 +43,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
.map_io = ti81xx_map_io,
.init_early = ti81xx_init_early,
.init_irq = ti81xx_init_irq,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.init_machine = ti81xx_evm_init,
.init_late = ti81xx_init_late,
.restart = omap_prcm_restart,
@@ -55,7 +55,7 @@ MACHINE_START(TI8148EVM, "ti8148evm")
.map_io = ti81xx_map_io,
.init_early = ti81xx_init_early,
.init_irq = ti81xx_init_irq,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.init_machine = ti81xx_evm_init,
.init_late = ti81xx_init_late,
.restart = omap_prcm_restart,
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 8feb4d9..b716f05 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -137,7 +137,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_zoom_init,
.init_late = omap3430_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
@@ -150,6 +150,6 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_zoom_init,
.init_late = omap3630_init_late,
- .timer = &omap3_timer,
+ .init_time = omap3_timer_init,
.restart = omap_prcm_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index c925c80..24df338 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -137,12 +137,12 @@ static inline void omap5_map_common_io(void)
extern void omap2_init_common_infrastructure(void);
-extern struct sys_timer omap2_timer;
-extern struct sys_timer omap3_timer;
-extern struct sys_timer omap3_secure_timer;
-extern struct sys_timer omap3_am33xx_timer;
-extern struct sys_timer omap4_timer;
-extern struct sys_timer omap5_timer;
+extern void omap2_timer_init(void);
+extern void omap3_timer_init(void);
+extern void omap3_secure_timer_init(void);
+extern void omap3_am33xx_timer_init(void);
+extern void omap4_timer_init(void);
+extern void omap5_timer_init(void);
void omap2420_init_early(void);
void omap2430_init_early(void);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 565e575..6291bbf 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -435,33 +435,24 @@ static inline void __init realtime_counter_init(void)
#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
clksrc_nr, clksrc_src) \
-static void __init omap##name##_timer_init(void) \
+void __init omap##name##_timer_init(void) \
{ \
omap2_gp_clockevent_init((clkev_nr), clkev_src); \
omap2_clocksource_init((clksrc_nr), clksrc_src); \
}
-#define OMAP_SYS_TIMER(name) \
-struct sys_timer omap##name##_timer = { \
- .init = omap##name##_timer_init, \
-};
-
#ifdef CONFIG_ARCH_OMAP2
OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
-OMAP_SYS_TIMER(2)
#endif
#ifdef CONFIG_ARCH_OMAP3
OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
-OMAP_SYS_TIMER(3)
OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
2, OMAP3_MPU_SOURCE)
-OMAP_SYS_TIMER(3_secure)
#endif
#ifdef CONFIG_SOC_AM33XX
OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
-OMAP_SYS_TIMER(3_am33xx)
#endif
#ifdef CONFIG_ARCH_OMAP4
@@ -470,7 +461,7 @@ static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
OMAP44XX_LOCAL_TWD_BASE, 29);
#endif
-static void __init omap4_timer_init(void)
+void __init omap4_timer_init(void)
{
omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
@@ -490,11 +481,10 @@ static void __init omap4_timer_init(void)
}
#endif
}
-OMAP_SYS_TIMER(4)
#endif
#ifdef CONFIG_SOC_OMAP5
-static void __init omap5_timer_init(void)
+void __init omap5_timer_init(void)
{
int err;
@@ -506,7 +496,6 @@ static void __init omap5_timer_init(void)
if (err)
pr_err("%s: arch_timer_register failed %d\n", __func__, err);
}
-OMAP_SYS_TIMER(5)
#endif
/**
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 25eb88a..2809ce1 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -657,5 +657,5 @@ MACHINE_START(AG5EVM, "ag5evm")
.handle_irq = gic_handle_irq,
.init_machine = ag5evm_init,
.init_late = shmobile_init_late,
- .timer = &shmobile_timer,
+ .init_time = sh73a0_earlytimer_init,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 790dc68..2deda6c 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1489,5 +1489,5 @@ MACHINE_START(AP4EVB, "ap4evb")
.handle_irq = shmobile_handle_irq_intc,
.init_machine = ap4evb_init,
.init_late = sh7372_pm_init_late,
- .timer = &shmobile_timer,
+ .init_time = sh7372_earlytimer_init,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 499e6e3..95b20e9 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1224,9 +1224,6 @@ static void __init eva_earlytimer_init(void)
static void __init eva_add_early_devices(void)
{
r8a7740_add_early_devices();
-
- /* override timer setup with board-specific code */
- shmobile_timer.init = eva_earlytimer_init;
}
#define RESCNT2 IOMEM(0xe6188020)
@@ -1248,7 +1245,7 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
.handle_irq = shmobile_handle_irq_intc,
.init_machine = eva_init,
.init_late = shmobile_init_late,
- .timer = &shmobile_timer,
+ .init_time = eva_earlytimer_init,
.dt_compat = eva_boards_compat_dt,
.restart = eva_restart,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index cb8c994..331b7ce 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -499,9 +499,6 @@ static void __init bonito_earlytimer_init(void)
static void __init bonito_add_early_devices(void)
{
r8a7740_add_early_devices();
-
- /* override timer setup with board-specific code */
- shmobile_timer.init = bonito_earlytimer_init;
}
MACHINE_START(BONITO, "bonito")
@@ -511,5 +508,5 @@ MACHINE_START(BONITO, "bonito")
.handle_irq = shmobile_handle_irq_intc,
.init_machine = bonito_init,
.init_late = shmobile_init_late,
- .timer = &shmobile_timer,
+ .init_time = bonito_earlytimer_init,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index bf88f9a..2f24994 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -553,5 +553,5 @@ MACHINE_START(KOTA2, "kota2")
.handle_irq = gic_handle_irq,
.init_machine = kota2_init,
.init_late = shmobile_init_late,
- .timer = &shmobile_timer,
+ .init_time = sh73a0_earlytimer_init,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index b52bc0d..59be864 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -92,6 +92,6 @@ DT_MACHINE_START(KZM9D_DT, "kzm9d")
.handle_irq = gic_handle_irq,
.init_machine = kzm9d_add_standard_devices,
.init_late = shmobile_init_late,
- .timer = &shmobile_timer,
+ .init_time = shmobile_timer_init,
.dt_compat = kzm9d_boards_compat_dt,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index f63f2ee..8fd59e3 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -795,7 +795,7 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g")
.handle_irq = gic_handle_irq,
.init_machine = kzm_init,
.init_late = shmobile_init_late,
- .timer = &shmobile_timer,
+ .init_time = sh73a0_earlytimer_init,
.restart = kzm9g_restart,
.dt_compat = kzm9g_boards_compat_dt,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 39b8f2e..b61bfef 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1663,6 +1663,6 @@ DT_MACHINE_START(MACKEREL_DT, "mackerel")
.handle_irq = shmobile_handle_irq_intc,
.init_machine = mackerel_init,
.init_late = sh7372_pm_init_late,
- .timer = &shmobile_timer,
+ .init_time = sh7372_earlytimer_init,
.dt_compat = mackerel_boards_compat_dt,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 69f7f46..e6ed68d 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -201,5 +201,5 @@ MACHINE_START(MARZEN, "marzen")
.handle_irq = gic_handle_irq,
.init_machine = marzen_init,
.init_late = shmobile_init_late,
- .timer = &shmobile_timer,
+ .init_time = r8a7779_earlytimer_init,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index dfeca79..a57439e 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -2,7 +2,7 @@
#define __ARCH_MACH_COMMON_H
extern void shmobile_earlytimer_init(void);
-extern struct sys_timer shmobile_timer;
+extern void shmobile_timer_init(void);
extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
unsigned int mult, unsigned int div);
struct twd_local_timer;
@@ -20,6 +20,7 @@ extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
extern void sh7372_init_irq(void);
extern void sh7372_map_io(void);
+extern void sh7372_earlytimer_init(void);
extern void sh7372_add_early_devices(void);
extern void sh7372_add_standard_devices(void);
extern void sh7372_clock_init(void);
@@ -32,6 +33,7 @@ extern struct clk sh7372_extal2_clk;
extern void sh73a0_init_irq(void);
extern void sh73a0_map_io(void);
+extern void sh73a0_earlytimer_init(void);
extern void sh73a0_add_early_devices(void);
extern void sh73a0_add_standard_devices(void);
extern void sh73a0_clock_init(void);
@@ -50,6 +52,7 @@ extern void r8a7740_pinmux_init(void);
extern void r8a7779_init_irq(void);
extern void r8a7779_map_io(void);
+extern void r8a7779_earlytimer_init(void);
extern void r8a7779_add_early_devices(void);
extern void r8a7779_add_standard_devices(void);
extern void r8a7779_clock_init(void);
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index a47beeb..ea61cb6 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -467,7 +467,7 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
.init_irq = emev2_init_irq_dt,
.handle_irq = gic_handle_irq,
.init_machine = emev2_add_standard_devices_dt,
- .timer = &shmobile_timer,
+ .init_time = shmobile_timer_init,
.dt_compat = emev2_boards_compat_dt,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 6ac242c..c5b4003 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -711,12 +711,6 @@ void __init r8a7740_add_standard_devices(void)
rmobile_add_device_to_domain("A3SP", &i2c1_device);
}
-static void __init r8a7740_earlytimer_init(void)
-{
- r8a7740_clock_init(0);
- shmobile_earlytimer_init();
-}
-
void __init r8a7740_add_early_devices(void)
{
early_platform_add_devices(r8a7740_early_devices,
@@ -724,9 +718,6 @@ void __init r8a7740_add_early_devices(void)
/* setup early console here as well */
shmobile_setup_console();
-
- /* override timer setup with soc-specific code */
- shmobile_timer.init = r8a7740_earlytimer_init;
}
#ifdef CONFIG_USE_OF
@@ -769,7 +760,7 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
.init_irq = r8a7740_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = r8a7740_add_standard_devices_dt,
- .timer = &shmobile_timer,
+ .init_time = shmobile_timer_init,
.dt_compat = r8a7740_boards_compat_dt,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 7a1ad4f..a181ced 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -339,7 +339,7 @@ void __init r8a7779_add_standard_devices(void)
/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
void __init __weak r8a7779_register_twd(void) { }
-static void __init r8a7779_earlytimer_init(void)
+void __init r8a7779_earlytimer_init(void)
{
r8a7779_clock_init();
shmobile_earlytimer_init();
@@ -366,7 +366,4 @@ void __init r8a7779_add_early_devices(void)
* As a final step pass earlyprint=sh-sci.2,115200 on the kernel
* command line in case of the marzen board.
*/
-
- /* override timer setup with soc-specific code */
- shmobile_timer.init = r8a7779_earlytimer_init;
}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index a360111..0437471 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -1060,7 +1060,7 @@ void __init sh7372_add_standard_devices(void)
ARRAY_SIZE(domain_devices));
}
-static void __init sh7372_earlytimer_init(void)
+void __init sh7372_earlytimer_init(void)
{
sh7372_clock_init();
shmobile_earlytimer_init();
@@ -1073,9 +1073,6 @@ void __init sh7372_add_early_devices(void)
/* setup early console here as well */
shmobile_setup_console();
-
- /* override timer setup with soc-specific code */
- shmobile_timer.init = sh7372_earlytimer_init;
}
#ifdef CONFIG_USE_OF
@@ -1119,7 +1116,7 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
.init_irq = sh7372_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = sh7372_add_standard_devices_dt,
- .timer = &shmobile_timer,
+ .init_time = shmobile_timer_init,
.dt_compat = sh7372_boards_compat_dt,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index db99a4a..8c2d642 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -796,7 +796,7 @@ void __init sh73a0_add_standard_devices(void)
/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
void __init __weak sh73a0_register_twd(void) { }
-static void __init sh73a0_earlytimer_init(void)
+void __init sh73a0_earlytimer_init(void)
{
sh73a0_clock_init();
shmobile_earlytimer_init();
@@ -810,7 +810,4 @@ void __init sh73a0_add_early_devices(void)
/* setup early console here as well */
shmobile_setup_console();
-
- /* override timer setup with soc-specific code */
- shmobile_timer.init = sh73a0_earlytimer_init;
}
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index a689197..fdbe54a 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -60,10 +60,6 @@ void __init shmobile_earlytimer_init(void)
late_time_init = shmobile_late_time_init;
}
-static void __init shmobile_timer_init(void)
+void __init shmobile_timer_init(void)
{
}
-
-struct sys_timer shmobile_timer = {
- .init = shmobile_timer_init,
-};
diff --git a/drivers/clocksource/bcm2835_timer.c b/drivers/clocksource/bcm2835_timer.c
index bc19f12..7f796d8 100644
--- a/drivers/clocksource/bcm2835_timer.c
+++ b/drivers/clocksource/bcm2835_timer.c
@@ -101,7 +101,7 @@ static struct of_device_id bcm2835_time_match[] __initconst = {
{}
};
-static void __init bcm2835_time_init(void)
+void __init bcm2835_timer_init(void)
{
struct device_node *node;
void __iomem *base;
@@ -155,7 +155,3 @@ static void __init bcm2835_time_init(void)
pr_info("bcm2835: system timer (irq = %d)\n", irq);
}
-
-struct sys_timer bcm2835_timer = {
- .init = bcm2835_time_init,
-};
diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index f7dba5b..ab09ed3 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -107,7 +107,7 @@ static const struct of_device_id osctimer_ids[] __initconst = {
{},
};
-static void __init timer_init(void)
+void __init dw_apb_timer_init(void)
{
struct device_node *event_timer, *source_timer;
@@ -125,7 +125,3 @@ static void __init timer_init(void)
init_sched_clock();
}
-
-struct sys_timer dw_apb_timer = {
- .init = timer_init,
-};
diff --git a/include/linux/bcm2835_timer.h b/include/linux/bcm2835_timer.h
index 25680fe..ca17aa8 100644
--- a/include/linux/bcm2835_timer.h
+++ b/include/linux/bcm2835_timer.h
@@ -17,6 +17,6 @@
#include <asm/mach/time.h>
-extern struct sys_timer bcm2835_timer;
+extern void bcm2835_timer_init(void);
#endif
diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h
index 1148575..dd755ce 100644
--- a/include/linux/dw_apb_timer.h
+++ b/include/linux/dw_apb_timer.h
@@ -53,5 +53,5 @@ void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs);
cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs);
void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs);
-extern struct sys_timer dw_apb_timer;
+extern void dw_apb_timer_init(void);
#endif /* __DW_APB_TIMER_H__ */
--
1.7.0.4
^ permalink raw reply related
* [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks
From: Paul Walmsley @ 2012-11-09 20:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1211091951080.20703@utopia.booyaka.com>
On Fri, 9 Nov 2012, Paul Walmsley wrote:
> On Fri, 9 Nov 2012, Mike Turquette wrote:
>
> > But I'm OK with the below patch in the short term. I just have one
> > question: did you observe any PM regressions by skipping the clkdm
> > programming?
>
> It's still under test here but 3530ES3 Beagle passed the PM tests with it,
> with no obvious warnings.
OK I'm satisfied with this general fix. Will have to break it up into
pieces and move it earlier in the patch stack to ensure that PM doesn't
break in the middle of the series, but the idea seems reasonably sound for
short-term use. A clock should only be disabled during the
disable-unused-clocks phase if its usecount is zero and it's enabled in
the hardware. As far as I can tell, this can only happen when the clock
is enabled by the bootloader/ROM code/PPA, and never touched by the kernel
before the disable-unused-clocks phase. The only regression cases that
come to mind at the moment are:
1. CONFIG_PM=n and a clockdomain only contains unused clocks; or
2. CONFIG_PM=y and a clockdomain only contains unused clocks and that same
clockdomain does not support hardware-supervised autoidle or force-idle
In those cases, I'd assume the clockdomain would effectively get stuck on.
#1 we don't really care about since CONFIG_PM=n anyway. #2 is more of a
concern but it should disappear completely once hwmods are present for all
of the IP blocks on the device. (The presence of the hwmods will ensure
that every clock that matters from an idle-management perspective is
enabled at least once when the IP block is reset.) For this reason, it's
important to note that when the hwmod reset code is moved to run late in
the boot process, it will have to run before the unused clocks are
disabled.
One nice side-effect of this bug is that it highlighted that we're still
missing OMAP3 hwmods for the camera subsystem, and that the reset code for
the SAD2D module needs to be moved out of
arch/arm/mach-omap2/pm34xx.c:omap3_d2d_idle() and into something that can
be called from the hwmod reset code.
- Paul
^ permalink raw reply
* [PATCH 15/26] ARM: omap2: clock: Add 24xx data using common struct clk
From: Paul Walmsley @ 2012-11-09 20:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1211081532210.20703@utopia.booyaka.com>
Here's another update on this one to add the twl.fck clock alias, recently
added by commit defa6be1c8216ed2d52d65db81a8a148e73be5f7 ("mfd: Fix
compile for twl-core.c by removing cpu_is_omap usage").
- Paul
From: Rajendra Nayak <rnayak@ti.com>
Date: Wed, 7 Nov 2012 21:09:35 -0700
Subject: [PATCH] ARM: OMAP2: clock: Add 24xx data using common struct clk
The patch is the output from a python script which converts
from the old OMAP clk format to COMMON clk format using a
JSON parser in between which was developed by Paul Walmsley.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul at pwsan.com: replace omap2_init_clksel_parent() with
omap2_clksel_find_parent_index(); reflowed macros; dropped 243x clkdev
aliases in 242x file; added recalc_rate fn ptrs to APLL clocks;
fixed some checkpatch warnings]
[mturquette at ti.com: removed deprecated variables from omap24x0_clk_init]
Signed-off-by: Mike Turquette <mturquette@ti.com>
[paul at pwsan.com: fixed boot crash due to missing clock init code; added twl.fck
alias]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/cclock2420_data.c | 1962 ++++++++++++++++++++++++++++++
arch/arm/mach-omap2/cclock2430_data.c | 2076 ++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/cm-regbits-24xx.h | 5 +
arch/arm/mach-omap2/prm-regbits-24xx.h | 2 +
4 files changed, 4045 insertions(+)
create mode 100644 arch/arm/mach-omap2/cclock2420_data.c
create mode 100644 arch/arm/mach-omap2/cclock2430_data.c
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
new file mode 100644
index 0000000..f1ee478
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -0,0 +1,1962 @@
+/*
+ * OMAP2420 clock data
+ *
+ * Copyright (C) 2005-2012 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/list.h>
+
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm2xxx.h"
+#include "prm2xxx.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "control.h"
+
+#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
+
+/*
+ * 2420 clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ * many cases the parent is selectable. The set parent calls will
+ * also switch sources.
+ *
+ * Several sources are given initial rates which may be wrong, this will
+ * be fixed up in the init func.
+ *
+ * Things are broadly separated below by clock domains. It is
+ * noteworthy that most peripherals have dependencies on multiple clock
+ * domains. Many get their interface clocks from the L4 domain, but get
+ * functional clocks from fixed sources or other core domain derived
+ * clocks.
+ */
+
+DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
+
+static struct clk osc_ck;
+
+static const struct clk_ops osc_ck_ops = {
+ .recalc_rate = &omap2_osc_clk_recalc,
+};
+
+static struct clk_hw_omap osc_ck_hw = {
+ .hw = {
+ .clk = &osc_ck,
+ },
+};
+
+static struct clk osc_ck = {
+ .name = "osc_ck",
+ .ops = &osc_ck_ops,
+ .hw = &osc_ck_hw.hw,
+ .flags = CLK_IS_ROOT,
+};
+
+DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+static struct clk sys_ck;
+
+static const char *sys_ck_parent_names[] = {
+ "osc_ck",
+};
+
+static const struct clk_ops sys_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .recalc_rate = &omap2xxx_sys_clk_recalc,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
+
+static struct dpll_data dpll_dd = {
+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .mult_mask = OMAP24XX_DPLL_MULT_MASK,
+ .div1_mask = OMAP24XX_DPLL_DIV_MASK,
+ .clk_bypass = &sys_ck,
+ .clk_ref = &sys_ck,
+ .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_mask = OMAP24XX_EN_DPLL_MASK,
+ .max_multiplier = 1023,
+ .min_divider = 1,
+ .max_divider = 16,
+};
+
+static struct clk dpll_ck;
+
+static const char *dpll_ck_parent_names[] = {
+ "sys_ck",
+};
+
+static const struct clk_ops dpll_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .get_parent = &omap2_init_dpll_parent,
+ .recalc_rate = &omap2_dpllcore_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap2_reprogram_dpllcore,
+};
+
+static struct clk_hw_omap dpll_ck_hw = {
+ .hw = {
+ .clk = &dpll_ck,
+ },
+ .ops = &clkhwops_omap2xxx_dpll,
+ .dpll_data = &dpll_dd,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
+
+static struct clk core_ck;
+
+static const char *core_ck_parent_names[] = {
+ "dpll_ck",
+};
+
+static const struct clk_ops core_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
+
+DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
+ CLK_DIVIDER_ONE_BASED, NULL);
+
+DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
+ CLK_DIVIDER_ONE_BASED, NULL);
+
+static struct clk aes_ick;
+
+static const char *aes_ick_parent_names[] = {
+ "l4_ck",
+};
+
+static const struct clk_ops aes_ick_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+static struct clk_hw_omap aes_ick_hw = {
+ .hw = {
+ .clk = &aes_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_AES_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk apll54_ck;
+
+static const struct clk_ops apll54_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_clk_apll54_enable,
+ .disable = &omap2_clk_apll_disable,
+ .recalc_rate = &omap2_clk_apll54_recalc,
+};
+
+static struct clk_hw_omap apll54_ck_hw = {
+ .hw = {
+ .clk = &apll54_ck,
+ },
+ .ops = &clkhwops_apll54,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
+
+static struct clk apll96_ck;
+
+static const struct clk_ops apll96_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_clk_apll96_enable,
+ .disable = &omap2_clk_apll_disable,
+ .recalc_rate = &omap2_clk_apll96_recalc,
+};
+
+static struct clk_hw_omap apll96_ck_hw = {
+ .hw = {
+ .clk = &apll96_ck,
+ },
+ .ops = &clkhwops_apll96,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
+
+static struct clk func_96m_ck;
+
+static const char *func_96m_ck_parent_names[] = {
+ "apll96_ck",
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops);
+
+static struct clk cam_fck;
+
+static const char *cam_fck_parent_names[] = {
+ "func_96m_ck",
+};
+
+static struct clk_hw_omap cam_fck_hw = {
+ .hw = {
+ .clk = &cam_fck,
+ },
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_CAM_SHIFT,
+ .clkdm_name = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk cam_ick;
+
+static struct clk_hw_omap cam_ick_hw = {
+ .hw = {
+ .clk = &cam_ick,
+ },
+ .ops = &clkhwops_iclk,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_CAM_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk des_ick;
+
+static struct clk_hw_omap des_ick_hw = {
+ .hw = {
+ .clk = &des_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_DES_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate dsp_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_242X },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 12, .val = 12, .flags = RATE_IN_242X },
+ { .div = 0 }
+};
+
+static const struct clksel dsp_fck_clksel[] = {
+ { .parent = &core_ck, .rates = dsp_fck_core_rates },
+ { .parent = NULL },
+};
+
+static const char *dsp_fck_parent_names[] = {
+ "core_ck",
+};
+
+static const struct clk_ops dsp_fck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+ .recalc_rate = &omap2_clksel_recalc,
+ .set_rate = &omap2_clksel_set_rate,
+ .round_rate = &omap2_clksel_round_rate,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
+ OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ OMAP24XX_CLKSEL_DSP_MASK,
+ OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
+ dsp_fck_parent_names, dsp_fck_ops);
+
+static const struct clksel dsp_ick_clksel[] = {
+ { .parent = &dsp_fck, .rates = dsp_ick_rates },
+ { .parent = NULL },
+};
+
+static const char *dsp_ick_parent_names[] = {
+ "dsp_fck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel,
+ OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ OMAP24XX_CLKSEL_DSP_IF_MASK,
+ OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+ OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait,
+ dsp_ick_parent_names, dsp_fck_ops);
+
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate dss1_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel dss1_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
+ { .parent = &core_ck, .rates = dss1_fck_core_rates },
+ { .parent = NULL },
+};
+
+static const char *dss1_fck_parent_names[] = {
+ "sys_ck", "core_ck",
+};
+
+static struct clk dss1_fck;
+
+static const struct clk_ops dss1_fck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+ .recalc_rate = &omap2_clksel_recalc,
+ .get_parent = &omap2_clksel_find_parent_index,
+ .set_parent = &omap2_clksel_set_parent,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_DSS1_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_DSS1_SHIFT, NULL,
+ dss1_fck_parent_names, dss1_fck_ops);
+
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate func_48m_apll96_rates[] = {
+ { .div = 2, .val = 0, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate func_48m_alt_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel func_48m_clksel[] = {
+ { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+ { .parent = &alt_ck, .rates = func_48m_alt_rates },
+ { .parent = NULL },
+};
+
+static const char *func_48m_ck_parent_names[] = {
+ "apll96_ck", "alt_ck",
+};
+
+static struct clk func_48m_ck;
+
+static const struct clk_ops func_48m_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .recalc_rate = &omap2_clksel_recalc,
+ .set_rate = &omap2_clksel_set_rate,
+ .round_rate = &omap2_clksel_round_rate,
+ .get_parent = &omap2_clksel_find_parent_index,
+ .set_parent = &omap2_clksel_set_parent,
+};
+
+static struct clk_hw_omap func_48m_ck_hw = {
+ .hw = {
+ .clk = &func_48m_ck,
+ },
+ .clksel = func_48m_clksel,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
+
+static const struct clksel dss2_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
+ { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+ { .parent = NULL },
+};
+
+static const char *dss2_fck_parent_names[] = {
+ "sys_ck", "func_48m_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_DSS2_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_DSS2_SHIFT, NULL,
+ dss2_fck_parent_names, dss1_fck_ops);
+
+static const char *func_54m_ck_parent_names[] = {
+ "apll54_ck", "alt_ck",
+};
+
+DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
+ OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH,
+ 0x0, NULL);
+
+static struct clk dss_54m_fck;
+
+static const char *dss_54m_fck_parent_names[] = {
+ "func_54m_ck",
+};
+
+static struct clk_hw_omap dss_54m_fck_hw = {
+ .hw = {
+ .clk = &dss_54m_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_TV_SHIFT,
+ .clkdm_name = "dss_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
+
+static struct clk dss_ick;
+
+static struct clk_hw_omap dss_ick_hw = {
+ .hw = {
+ .clk = &dss_ick,
+ },
+ .ops = &clkhwops_iclk,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
+ .clkdm_name = "dss_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk eac_fck;
+
+static struct clk_hw_omap eac_fck_hw = {
+ .hw = {
+ .clk = &eac_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_EAC_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk eac_ick;
+
+static struct clk_hw_omap eac_ick_hw = {
+ .hw = {
+ .clk = &eac_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_EAC_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk emul_ck;
+
+static struct clk_hw_omap emul_ck_hw = {
+ .hw = {
+ .clk = &emul_ck,
+ },
+ .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
+ .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
+
+DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
+
+static struct clk fac_fck;
+
+static const char *fac_fck_parent_names[] = {
+ "func_12m_ck",
+};
+
+static struct clk_hw_omap fac_fck_hw = {
+ .hw = {
+ .clk = &fac_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_FAC_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk fac_ick;
+
+static struct clk_hw_omap fac_ick_hw = {
+ .hw = {
+ .clk = &fac_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_FAC_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel gfx_fck_clksel[] = {
+ { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+ { .parent = NULL },
+};
+
+static const char *gfx_2d_fck_parent_names[] = {
+ "core_l3_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
+ OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+ OMAP_CLKSEL_GFX_MASK,
+ OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+ OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
+ gfx_2d_fck_parent_names, dsp_fck_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
+ OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+ OMAP_CLKSEL_GFX_MASK,
+ OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+ OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
+ gfx_2d_fck_parent_names, dsp_fck_ops);
+
+static struct clk gfx_ick;
+
+static const char *gfx_ick_parent_names[] = {
+ "core_l3_ck",
+};
+
+static struct clk_hw_omap gfx_ick_hw = {
+ .hw = {
+ .clk = &gfx_ick,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+ .enable_bit = OMAP_EN_GFX_SHIFT,
+ .clkdm_name = "gfx_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
+
+static struct clk gpios_fck;
+
+static const char *gpios_fck_parent_names[] = {
+ "func_32k_ck",
+};
+
+static struct clk_hw_omap gpios_fck_hw = {
+ .hw = {
+ .clk = &gpios_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk wu_l4_ick;
+
+DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
+DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
+
+static struct clk gpios_ick;
+
+static const char *gpios_ick_parent_names[] = {
+ "wu_l4_ick",
+};
+
+static struct clk_hw_omap gpios_ick_hw = {
+ .hw = {
+ .clk = &gpios_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk gpmc_fck;
+
+static struct clk_hw_omap gpmc_fck_hw = {
+ .hw = {
+ .clk = &gpmc_fck,
+ },
+ .ops = &clkhwops_iclk,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
+
+static const struct clksel_rate gpt_alt_rates[] = {
+ { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel omap24xx_gpt_clksel[] = {
+ { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+ { .parent = &sys_ck, .rates = gpt_sys_rates },
+ { .parent = &alt_ck, .rates = gpt_alt_rates },
+ { .parent = NULL },
+};
+
+static const char *gpt10_fck_parent_names[] = {
+ "func_32k_ck", "sys_ck", "alt_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT10_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt10_ick;
+
+static struct clk_hw_omap gpt10_ick_hw = {
+ .hw = {
+ .clk = &gpt10_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT11_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt11_ick;
+
+static struct clk_hw_omap gpt11_ick_hw = {
+ .hw = {
+ .clk = &gpt11_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT12_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt12_ick;
+
+static struct clk_hw_omap gpt12_ick_hw = {
+ .hw = {
+ .clk = &gpt12_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clk_ops gpt1_fck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+ .recalc_rate = &omap2_clksel_recalc,
+ .set_rate = &omap2_clksel_set_rate,
+ .round_rate = &omap2_clksel_round_rate,
+ .get_parent = &omap2_clksel_find_parent_index,
+ .set_parent = &omap2_clksel_set_parent,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_GPT1_MASK,
+ OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, gpt1_fck_ops);
+
+static struct clk gpt1_ick;
+
+static struct clk_hw_omap gpt1_ick_hw = {
+ .hw = {
+ .clk = &gpt1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT2_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt2_ick;
+
+static struct clk_hw_omap gpt2_ick_hw = {
+ .hw = {
+ .clk = &gpt2_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT3_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt3_ick;
+
+static struct clk_hw_omap gpt3_ick_hw = {
+ .hw = {
+ .clk = &gpt3_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT4_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt4_ick;
+
+static struct clk_hw_omap gpt4_ick_hw = {
+ .hw = {
+ .clk = &gpt4_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT5_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt5_ick;
+
+static struct clk_hw_omap gpt5_ick_hw = {
+ .hw = {
+ .clk = &gpt5_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT6_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt6_ick;
+
+static struct clk_hw_omap gpt6_ick_hw = {
+ .hw = {
+ .clk = &gpt6_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT7_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt7_ick;
+
+static struct clk_hw_omap gpt7_ick_hw = {
+ .hw = {
+ .clk = &gpt7_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT8_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt8_ick;
+
+static struct clk_hw_omap gpt8_ick_hw = {
+ .hw = {
+ .clk = &gpt8_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT9_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt9_ick;
+
+static struct clk_hw_omap gpt9_ick_hw = {
+ .hw = {
+ .clk = &gpt9_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk hdq_fck;
+
+static struct clk_hw_omap hdq_fck_hw = {
+ .hw = {
+ .clk = &hdq_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk hdq_ick;
+
+static struct clk_hw_omap hdq_ick_hw = {
+ .hw = {
+ .clk = &hdq_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2c1_fck;
+
+static struct clk_hw_omap i2c1_fck_hw = {
+ .hw = {
+ .clk = &i2c1_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_I2C1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk i2c1_ick;
+
+static struct clk_hw_omap i2c1_ick_hw = {
+ .hw = {
+ .clk = &i2c1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_I2C1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2c2_fck;
+
+static struct clk_hw_omap i2c2_fck_hw = {
+ .hw = {
+ .clk = &i2c2_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_I2C2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk i2c2_ick;
+
+static struct clk_hw_omap i2c2_ick_hw = {
+ .hw = {
+ .clk = &i2c2_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_I2C2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,
+ OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ OMAP2420_CLKSEL_IVA_MASK,
+ OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait,
+ dsp_fck_parent_names, dsp_fck_ops);
+
+static struct clk iva1_mpu_int_ifck;
+
+static const char *iva1_mpu_int_ifck_parent_names[] = {
+ "iva1_ifck",
+};
+
+static const struct clk_ops iva1_mpu_int_ifck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+ .recalc_rate = &omap_fixed_divisor_recalc,
+};
+
+static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
+ .hw = {
+ .clk = &iva1_mpu_int_ifck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
+ .clkdm_name = "iva1_clkdm",
+ .fixed_div = 2,
+};
+
+DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names,
+ iva1_mpu_int_ifck_ops);
+
+static struct clk mailboxes_ick;
+
+static struct clk_hw_omap mailboxes_ick_hw = {
+ .hw = {
+ .clk = &mailboxes_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel mcbsp_fck_clksel[] = {
+ { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
+ { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
+ { .parent = NULL },
+};
+
+static const char *mcbsp1_fck_parent_names[] = {
+ "func_96m_ck", "mcbsp_clks",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+ OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+ OMAP2_MCBSP1_CLKS_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
+ mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp1_ick;
+
+static struct clk_hw_omap mcbsp1_ick_hw = {
+ .hw = {
+ .clk = &mcbsp1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+ OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+ OMAP2_MCBSP2_CLKS_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
+ mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp2_ick;
+
+static struct clk_hw_omap mcbsp2_ick_hw = {
+ .hw = {
+ .clk = &mcbsp2_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mcspi1_fck;
+
+static const char *mcspi1_fck_parent_names[] = {
+ "func_48m_ck",
+};
+
+static struct clk_hw_omap mcspi1_fck_hw = {
+ .hw = {
+ .clk = &mcspi1_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk mcspi1_ick;
+
+static struct clk_hw_omap mcspi1_ick_hw = {
+ .hw = {
+ .clk = &mcspi1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mcspi2_fck;
+
+static struct clk_hw_omap mcspi2_fck_hw = {
+ .hw = {
+ .clk = &mcspi2_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk mcspi2_ick;
+
+static struct clk_hw_omap mcspi2_ick_hw = {
+ .hw = {
+ .clk = &mcspi2_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mmc_fck;
+
+static struct clk_hw_omap mmc_fck_hw = {
+ .hw = {
+ .clk = &mmc_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_MMC_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk mmc_ick;
+
+static struct clk_hw_omap mmc_ick_hw = {
+ .hw = {
+ .clk = &mmc_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_MMC_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
+ OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+ OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
+ CLK_DIVIDER_ONE_BASED, NULL);
+
+static struct clk mpu_wdt_fck;
+
+static struct clk_hw_omap mpu_wdt_fck_hw = {
+ .hw = {
+ .clk = &mpu_wdt_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk mpu_wdt_ick;
+
+static struct clk_hw_omap mpu_wdt_ick_hw = {
+ .hw = {
+ .clk = &mpu_wdt_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk mspro_fck;
+
+static struct clk_hw_omap mspro_fck_hw = {
+ .hw = {
+ .clk = &mspro_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk mspro_ick;
+
+static struct clk_hw_omap mspro_ick_hw = {
+ .hw = {
+ .clk = &mspro_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk omapctrl_ick;
+
+static struct clk_hw_omap omapctrl_ick_hw = {
+ .hw = {
+ .clk = &omapctrl_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk pka_ick;
+
+static struct clk_hw_omap pka_ick_hw = {
+ .hw = {
+ .clk = &pka_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_PKA_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk rng_ick;
+
+static struct clk_hw_omap rng_ick_hw = {
+ .hw = {
+ .clk = &rng_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_RNG_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk sdma_fck;
+
+DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
+DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sdma_ick;
+
+static struct clk_hw_omap sdma_ick_hw = {
+ .hw = {
+ .clk = &sdma_ick,
+ },
+ .ops = &clkhwops_iclk,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
+ .clkdm_name = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sdrc_ick;
+
+static struct clk_hw_omap sdrc_ick_hw = {
+ .hw = {
+ .clk = &sdrc_ick,
+ },
+ .ops = &clkhwops_iclk,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sha_ick;
+
+static struct clk_hw_omap sha_ick_hw = {
+ .hw = {
+ .clk = &sha_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_SHA_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk ssi_l4_ick;
+
+static struct clk_hw_omap ssi_l4_ick_hw = {
+ .hw = {
+ .clk = &ssi_l4_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_SSI_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_242X },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+ { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+ { .parent = NULL },
+};
+
+static const char *ssi_ssr_sst_fck_parent_names[] = {
+ "core_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
+ ssi_ssr_sst_fck_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_SSI_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
+ ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
+
+static struct clk sync_32k_ick;
+
+static struct clk_hw_omap sync_32k_ick_hw = {
+ .hw = {
+ .clk = &sync_32k_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+ { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+ { .div = 1, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel common_clkout_src_clksel[] = {
+ { .parent = &core_ck, .rates = common_clkout_src_core_rates },
+ { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
+ { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+ { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+ { .parent = NULL },
+};
+
+static const char *sys_clkout_src_parent_names[] = {
+ "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
+ OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
+ OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
+ NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
+
+DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
+ OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
+ OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
+ common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL,
+ OMAP2420_CLKOUT2_SOURCE_MASK,
+ OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT,
+ NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
+
+DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0,
+ OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT,
+ OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static struct clk uart1_fck;
+
+static struct clk_hw_omap uart1_fck_hw = {
+ .hw = {
+ .clk = &uart1_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_UART1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart1_ick;
+
+static struct clk_hw_omap uart1_ick_hw = {
+ .hw = {
+ .clk = &uart1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_UART1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk uart2_fck;
+
+static struct clk_hw_omap uart2_fck_hw = {
+ .hw = {
+ .clk = &uart2_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_UART2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart2_ick;
+
+static struct clk_hw_omap uart2_ick_hw = {
+ .hw = {
+ .clk = &uart2_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_UART2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk uart3_fck;
+
+static struct clk_hw_omap uart3_fck_hw = {
+ .hw = {
+ .clk = &uart3_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP24XX_EN_UART3_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart3_ick;
+
+static struct clk_hw_omap uart3_ick_hw = {
+ .hw = {
+ .clk = &uart3_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_UART3_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk usb_fck;
+
+static struct clk_hw_omap usb_fck_hw = {
+ .hw = {
+ .clk = &usb_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP24XX_EN_USB_SHIFT,
+ .clkdm_name = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel usb_l4_ick_clksel[] = {
+ { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+ { .parent = NULL },
+};
+
+static const char *usb_l4_ick_parent_names[] = {
+ "core_l3_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_USB_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
+ usb_l4_ick_parent_names, dsp_fck_ops);
+
+static struct clk virt_prcm_set;
+
+static const char *virt_prcm_set_parent_names[] = {
+ "mpu_ck",
+};
+
+static const struct clk_ops virt_prcm_set_ops = {
+ .recalc_rate = &omap2_table_mpu_recalc,
+ .set_rate = &omap2_select_table_rate,
+ .round_rate = &omap2_round_to_table_rate,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
+DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
+
+static const struct clksel_rate vlynq_fck_96m_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_242X },
+ { .div = 0 }
+};
+
+static const struct clksel_rate vlynq_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_242X },
+ { .div = 2, .val = 2, .flags = RATE_IN_242X },
+ { .div = 3, .val = 3, .flags = RATE_IN_242X },
+ { .div = 4, .val = 4, .flags = RATE_IN_242X },
+ { .div = 6, .val = 6, .flags = RATE_IN_242X },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 9, .val = 9, .flags = RATE_IN_242X },
+ { .div = 12, .val = 12, .flags = RATE_IN_242X },
+ { .div = 16, .val = 16, .flags = RATE_IN_242X },
+ { .div = 18, .val = 18, .flags = RATE_IN_242X },
+ { .div = 0 }
+};
+
+static const struct clksel vlynq_fck_clksel[] = {
+ { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
+ { .parent = &core_ck, .rates = vlynq_fck_core_rates },
+ { .parent = NULL },
+};
+
+static const char *vlynq_fck_parent_names[] = {
+ "func_96m_ck", "core_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP2420_CLKSEL_VLYNQ_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait,
+ vlynq_fck_parent_names, dss1_fck_ops);
+
+static struct clk vlynq_ick;
+
+static struct clk_hw_omap vlynq_ick_hw = {
+ .hw = {
+ .clk = &vlynq_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
+ .clkdm_name = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt1_ick;
+
+static struct clk_hw_omap wdt1_ick_hw = {
+ .hw = {
+ .clk = &wdt1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt1_osc_ck;
+
+static const struct clk_ops wdt1_osc_ck_ops = {};
+
+DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
+DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
+
+static struct clk wdt3_fck;
+
+static struct clk_hw_omap wdt3_fck_hw = {
+ .hw = {
+ .clk = &wdt3_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_WDT3_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk wdt3_ick;
+
+static struct clk_hw_omap wdt3_ick_hw = {
+ .hw = {
+ .clk = &wdt3_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_WDT3_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt4_fck;
+
+static struct clk_hw_omap wdt4_fck_hw = {
+ .hw = {
+ .clk = &wdt4_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk wdt4_ick;
+
+static struct clk_hw_omap wdt4_ick_hw = {
+ .hw = {
+ .clk = &wdt4_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
+
+/*
+ * clkdev integration
+ */
+
+static struct omap_clk omap2420_clks[] = {
+ /* external root sources */
+ CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
+ CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
+ CLK(NULL, "osc_ck", &osc_ck, CK_242X),
+ CLK(NULL, "sys_ck", &sys_ck, CK_242X),
+ CLK(NULL, "alt_ck", &alt_ck, CK_242X),
+ CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
+ /* internal analog sources */
+ CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
+ CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
+ CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
+ /* internal prcm root sources */
+ CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
+ CLK(NULL, "core_ck", &core_ck, CK_242X),
+ CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
+ CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
+ CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
+ CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
+ CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
+ CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
+ CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
+ CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
+ CLK(NULL, "emul_ck", &emul_ck, CK_242X),
+ /* mpu domain clocks */
+ CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
+ /* dsp domain clocks */
+ CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
+ CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
+ CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
+ CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+ /* GFX domain clocks */
+ CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
+ CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
+ CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
+ /* DSS domain clocks */
+ CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
+ CLK(NULL, "dss_ick", &dss_ick, CK_242X),
+ CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
+ CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
+ CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
+ /* L3 domain clocks */
+ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
+ CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
+ CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
+ /* L4 domain clocks */
+ CLK(NULL, "l4_ck", &l4_ck, CK_242X),
+ CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
+ CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
+ /* virtual meta-group clock */
+ CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
+ /* general l4 interface ck, multi-parent functional clk */
+ CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
+ CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
+ CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
+ CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
+ CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
+ CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
+ CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
+ CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
+ CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
+ CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
+ CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
+ CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
+ CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
+ CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
+ CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
+ CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
+ CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
+ CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
+ CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
+ CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
+ CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
+ CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
+ CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
+ CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
+ CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
+ CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
+ CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
+ CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
+ CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
+ CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
+ CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
+ CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
+ CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
+ CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
+ CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
+ CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
+ CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
+ CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
+ CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
+ CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
+ CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
+ CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
+ CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
+ CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
+ CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
+ CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
+ CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
+ CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
+ CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
+ CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
+ CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
+ CLK(NULL, "cam_fck", &cam_fck, CK_242X),
+ CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
+ CLK(NULL, "cam_ick", &cam_ick, CK_242X),
+ CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
+ CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
+ CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
+ CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
+ CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
+ CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
+ CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
+ CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
+ CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
+ CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
+ CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
+ CLK(NULL, "fac_ick", &fac_ick, CK_242X),
+ CLK(NULL, "fac_fck", &fac_fck, CK_242X),
+ CLK(NULL, "eac_ick", &eac_ick, CK_242X),
+ CLK(NULL, "eac_fck", &eac_fck, CK_242X),
+ CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
+ CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
+ CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
+ CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
+ CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
+ CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
+ CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
+ CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
+ CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
+ CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
+ CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
+ CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
+ CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
+ CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
+ CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
+ CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
+ CLK(NULL, "des_ick", &des_ick, CK_242X),
+ CLK("omap-sham", "ick", &sha_ick, CK_242X),
+ CLK(NULL, "sha_ick", &sha_ick, CK_242X),
+ CLK("omap_rng", "ick", &rng_ick, CK_242X),
+ CLK(NULL, "rng_ick", &rng_ick, CK_242X),
+ CLK("omap-aes", "ick", &aes_ick, CK_242X),
+ CLK(NULL, "aes_ick", &aes_ick, CK_242X),
+ CLK(NULL, "pka_ick", &pka_ick, CK_242X),
+ CLK(NULL, "usb_fck", &usb_fck, CK_242X),
+ CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
+ CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
+ CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
+ CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
+ CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
+};
+
+
+static const char *enable_init_clks[] = {
+ "apll96_ck",
+ "apll54_ck",
+ "sync_32k_ick",
+ "omapctrl_ick",
+ "gpmc_fck",
+ "sdrc_ick",
+};
+
+/*
+ * init code
+ */
+
+int __init omap2420_clk_init(void)
+{
+ const struct prcm_config *prcm;
+ struct omap_clk *c;
+ unsigned long clkrate;
+
+ prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
+ cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
+ cpu_mask = RATE_IN_242X;
+ rate_table = omap2420_rate_table;
+
+ /* Check the MPU rate set by bootloader */
+ clkrate = omap2xxx_clk_get_core_rate(&dpll_ck_hw);
+ for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+ if (!(prcm->flags & cpu_mask))
+ continue;
+ if (prcm->xtal_speed != sys_ck.rate)
+ continue;
+ if (prcm->dpll_speed <= clkrate)
+ break;
+ }
+
+ curr_prcm_set = prcm;
+
+ for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
+ c++) {
+ clkdev_add(&c->lk);
+ if (!__clk_init(NULL, c->lk.clk))
+ omap2_init_clk_hw_omap_clocks(c->lk.clk);
+ }
+
+ omap2_clk_disable_autoidle_all();
+
+ omap2_clk_enable_init_clocks(enable_init_clks,
+ ARRAY_SIZE(enable_init_clks));
+
+ pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ (clk_get_rate(&sys_ck) / 1000000),
+ (clk_get_rate(&sys_ck) / 100000) % 10,
+ (clk_get_rate(&dpll_ck) / 1000000),
+ (clk_get_rate(&mpu_ck) / 1000000));
+
+ return 0;
+}
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
new file mode 100644
index 0000000..102fbba
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -0,0 +1,2076 @@
+/*
+ * OMAP2430 clock data
+ *
+ * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/list.h>
+
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm2xxx.h"
+#include "prm2xxx.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "control.h"
+
+#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
+
+/*
+ * 2430 clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ * many cases the parent is selectable. The set parent calls will
+ * also switch sources.
+ *
+ * Several sources are given initial rates which may be wrong, this will
+ * be fixed up in the init func.
+ *
+ * Things are broadly separated below by clock domains. It is
+ * noteworthy that most peripherals have dependencies on multiple clock
+ * domains. Many get their interface clocks from the L4 domain, but get
+ * functional clocks from fixed sources or other core domain derived
+ * clocks.
+ */
+
+DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
+
+static struct clk osc_ck;
+
+static const struct clk_ops osc_ck_ops = {
+ .enable = &omap2_enable_osc_ck,
+ .disable = omap2_disable_osc_ck,
+ .recalc_rate = &omap2_osc_clk_recalc,
+};
+
+static struct clk_hw_omap osc_ck_hw = {
+ .hw = {
+ .clk = &osc_ck,
+ },
+};
+
+static struct clk osc_ck = {
+ .name = "osc_ck",
+ .ops = &osc_ck_ops,
+ .hw = &osc_ck_hw.hw,
+ .flags = CLK_IS_ROOT,
+};
+
+DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+static struct clk sys_ck;
+
+static const char *sys_ck_parent_names[] = {
+ "osc_ck",
+};
+
+static const struct clk_ops sys_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .recalc_rate = &omap2xxx_sys_clk_recalc,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
+
+static struct dpll_data dpll_dd = {
+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .mult_mask = OMAP24XX_DPLL_MULT_MASK,
+ .div1_mask = OMAP24XX_DPLL_DIV_MASK,
+ .clk_bypass = &sys_ck,
+ .clk_ref = &sys_ck,
+ .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_mask = OMAP24XX_EN_DPLL_MASK,
+ .max_multiplier = 1023,
+ .min_divider = 1,
+ .max_divider = 16,
+};
+
+static struct clk dpll_ck;
+
+static const char *dpll_ck_parent_names[] = {
+ "sys_ck",
+};
+
+static const struct clk_ops dpll_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .get_parent = &omap2_init_dpll_parent,
+ .recalc_rate = &omap2_dpllcore_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap2_reprogram_dpllcore,
+};
+
+static struct clk_hw_omap dpll_ck_hw = {
+ .hw = {
+ .clk = &dpll_ck,
+ },
+ .ops = &clkhwops_omap2xxx_dpll,
+ .dpll_data = &dpll_dd,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
+
+static struct clk core_ck;
+
+static const char *core_ck_parent_names[] = {
+ "dpll_ck",
+};
+
+static const struct clk_ops core_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
+
+DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
+ CLK_DIVIDER_ONE_BASED, NULL);
+
+DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
+ CLK_DIVIDER_ONE_BASED, NULL);
+
+static struct clk aes_ick;
+
+static const char *aes_ick_parent_names[] = {
+ "l4_ck",
+};
+
+static const struct clk_ops aes_ick_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+};
+
+static struct clk_hw_omap aes_ick_hw = {
+ .hw = {
+ .clk = &aes_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_AES_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk apll54_ck;
+
+static const struct clk_ops apll54_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_clk_apll54_enable,
+ .disable = &omap2_clk_apll_disable,
+ .recalc_rate = &omap2_clk_apll54_recalc,
+};
+
+static struct clk_hw_omap apll54_ck_hw = {
+ .hw = {
+ .clk = &apll54_ck,
+ },
+ .ops = &clkhwops_apll54,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
+
+static struct clk apll96_ck;
+
+static const struct clk_ops apll96_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_clk_apll96_enable,
+ .disable = &omap2_clk_apll_disable,
+ .recalc_rate = &omap2_clk_apll96_recalc,
+};
+
+static struct clk_hw_omap apll96_ck_hw = {
+ .hw = {
+ .clk = &apll96_ck,
+ },
+ .ops = &clkhwops_apll96,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
+
+static const char *func_96m_ck_parent_names[] = {
+ "apll96_ck", "alt_ck",
+};
+
+DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0,
+ OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT,
+ OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL);
+
+static struct clk cam_fck;
+
+static const char *cam_fck_parent_names[] = {
+ "func_96m_ck",
+};
+
+static struct clk_hw_omap cam_fck_hw = {
+ .hw = {
+ .clk = &cam_fck,
+ },
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_CAM_SHIFT,
+ .clkdm_name = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk cam_ick;
+
+static struct clk_hw_omap cam_ick_hw = {
+ .hw = {
+ .clk = &cam_ick,
+ },
+ .ops = &clkhwops_iclk,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_CAM_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk des_ick;
+
+static struct clk_hw_omap des_ick_hw = {
+ .hw = {
+ .clk = &des_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_DES_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate dsp_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel dsp_fck_clksel[] = {
+ { .parent = &core_ck, .rates = dsp_fck_core_rates },
+ { .parent = NULL },
+};
+
+static const char *dsp_fck_parent_names[] = {
+ "core_ck",
+};
+
+static struct clk dsp_fck;
+
+static const struct clk_ops dsp_fck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+ .recalc_rate = &omap2_clksel_recalc,
+ .set_rate = &omap2_clksel_set_rate,
+ .round_rate = &omap2_clksel_round_rate,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
+ OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ OMAP24XX_CLKSEL_DSP_MASK,
+ OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
+ dsp_fck_parent_names, dsp_fck_ops);
+
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate dss1_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel dss1_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
+ { .parent = &core_ck, .rates = dss1_fck_core_rates },
+ { .parent = NULL },
+};
+
+static const char *dss1_fck_parent_names[] = {
+ "sys_ck", "core_ck",
+};
+
+static const struct clk_ops dss1_fck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+ .recalc_rate = &omap2_clksel_recalc,
+ .get_parent = &omap2_clksel_find_parent_index,
+ .set_parent = &omap2_clksel_set_parent,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_DSS1_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_DSS1_SHIFT, NULL,
+ dss1_fck_parent_names, dss1_fck_ops);
+
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate func_48m_apll96_rates[] = {
+ { .div = 2, .val = 0, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate func_48m_alt_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel func_48m_clksel[] = {
+ { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+ { .parent = &alt_ck, .rates = func_48m_alt_rates },
+ { .parent = NULL },
+};
+
+static const char *func_48m_ck_parent_names[] = {
+ "apll96_ck", "alt_ck",
+};
+
+static struct clk func_48m_ck;
+
+static const struct clk_ops func_48m_ck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .recalc_rate = &omap2_clksel_recalc,
+ .set_rate = &omap2_clksel_set_rate,
+ .round_rate = &omap2_clksel_round_rate,
+ .get_parent = &omap2_clksel_find_parent_index,
+ .set_parent = &omap2_clksel_set_parent,
+};
+
+static struct clk_hw_omap func_48m_ck_hw = {
+ .hw = {
+ .clk = &func_48m_ck,
+ },
+ .clksel = func_48m_clksel,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
+
+static const struct clksel dss2_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
+ { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+ { .parent = NULL },
+};
+
+static const char *dss2_fck_parent_names[] = {
+ "sys_ck", "func_48m_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_DSS2_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_DSS2_SHIFT, NULL,
+ dss2_fck_parent_names, dss1_fck_ops);
+
+static const char *func_54m_ck_parent_names[] = {
+ "apll54_ck", "alt_ck",
+};
+
+DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
+ OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL);
+
+static struct clk dss_54m_fck;
+
+static const char *dss_54m_fck_parent_names[] = {
+ "func_54m_ck",
+};
+
+static struct clk_hw_omap dss_54m_fck_hw = {
+ .hw = {
+ .clk = &dss_54m_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_TV_SHIFT,
+ .clkdm_name = "dss_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
+
+static struct clk dss_ick;
+
+static struct clk_hw_omap dss_ick_hw = {
+ .hw = {
+ .clk = &dss_ick,
+ },
+ .ops = &clkhwops_iclk,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
+ .clkdm_name = "dss_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk emul_ck;
+
+static struct clk_hw_omap emul_ck_hw = {
+ .hw = {
+ .clk = &emul_ck,
+ },
+ .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
+ .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
+
+DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
+
+static struct clk fac_fck;
+
+static const char *fac_fck_parent_names[] = {
+ "func_12m_ck",
+};
+
+static struct clk_hw_omap fac_fck_hw = {
+ .hw = {
+ .clk = &fac_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_FAC_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk fac_ick;
+
+static struct clk_hw_omap fac_ick_hw = {
+ .hw = {
+ .clk = &fac_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_FAC_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel gfx_fck_clksel[] = {
+ { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+ { .parent = NULL },
+};
+
+static const char *gfx_2d_fck_parent_names[] = {
+ "core_l3_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
+ OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+ OMAP_CLKSEL_GFX_MASK,
+ OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+ OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
+ gfx_2d_fck_parent_names, dsp_fck_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
+ OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+ OMAP_CLKSEL_GFX_MASK,
+ OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+ OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
+ gfx_2d_fck_parent_names, dsp_fck_ops);
+
+static struct clk gfx_ick;
+
+static const char *gfx_ick_parent_names[] = {
+ "core_l3_ck",
+};
+
+static struct clk_hw_omap gfx_ick_hw = {
+ .hw = {
+ .clk = &gfx_ick,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+ .enable_bit = OMAP_EN_GFX_SHIFT,
+ .clkdm_name = "gfx_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
+
+static struct clk gpio5_fck;
+
+static const char *gpio5_fck_parent_names[] = {
+ "func_32k_ck",
+};
+
+static struct clk_hw_omap gpio5_fck_hw = {
+ .hw = {
+ .clk = &gpio5_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops);
+
+static struct clk gpio5_ick;
+
+static struct clk_hw_omap gpio5_ick_hw = {
+ .hw = {
+ .clk = &gpio5_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk gpios_fck;
+
+static struct clk_hw_omap gpios_fck_hw = {
+ .hw = {
+ .clk = &gpios_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops);
+
+static struct clk wu_l4_ick;
+
+DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
+DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
+
+static struct clk gpios_ick;
+
+static const char *gpios_ick_parent_names[] = {
+ "wu_l4_ick",
+};
+
+static struct clk_hw_omap gpios_ick_hw = {
+ .hw = {
+ .clk = &gpios_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk gpmc_fck;
+
+static struct clk_hw_omap gpmc_fck_hw = {
+ .hw = {
+ .clk = &gpmc_fck,
+ },
+ .ops = &clkhwops_iclk,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
+
+static const struct clksel_rate gpt_alt_rates[] = {
+ { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel omap24xx_gpt_clksel[] = {
+ { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+ { .parent = &sys_ck, .rates = gpt_sys_rates },
+ { .parent = &alt_ck, .rates = gpt_alt_rates },
+ { .parent = NULL },
+};
+
+static const char *gpt10_fck_parent_names[] = {
+ "func_32k_ck", "sys_ck", "alt_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT10_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt10_ick;
+
+static struct clk_hw_omap gpt10_ick_hw = {
+ .hw = {
+ .clk = &gpt10_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT11_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt11_ick;
+
+static struct clk_hw_omap gpt11_ick_hw = {
+ .hw = {
+ .clk = &gpt11_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT12_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt12_ick;
+
+static struct clk_hw_omap gpt12_ick_hw = {
+ .hw = {
+ .clk = &gpt12_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clk_ops gpt1_fck_ops = {
+ .init = &omap2_init_clk_clkdm,
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+ .recalc_rate = &omap2_clksel_recalc,
+ .set_rate = &omap2_clksel_set_rate,
+ .round_rate = &omap2_clksel_round_rate,
+ .get_parent = &omap2_clksel_find_parent_index,
+ .set_parent = &omap2_clksel_set_parent,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_GPT1_MASK,
+ OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, gpt1_fck_ops);
+
+static struct clk gpt1_ick;
+
+static struct clk_hw_omap gpt1_ick_hw = {
+ .hw = {
+ .clk = &gpt1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT2_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt2_ick;
+
+static struct clk_hw_omap gpt2_ick_hw = {
+ .hw = {
+ .clk = &gpt2_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT3_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt3_ick;
+
+static struct clk_hw_omap gpt3_ick_hw = {
+ .hw = {
+ .clk = &gpt3_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT4_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt4_ick;
+
+static struct clk_hw_omap gpt4_ick_hw = {
+ .hw = {
+ .clk = &gpt4_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT5_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt5_ick;
+
+static struct clk_hw_omap gpt5_ick_hw = {
+ .hw = {
+ .clk = &gpt5_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT6_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt6_ick;
+
+static struct clk_hw_omap gpt6_ick_hw = {
+ .hw = {
+ .clk = &gpt6_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT7_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt7_ick;
+
+static struct clk_hw_omap gpt7_ick_hw = {
+ .hw = {
+ .clk = &gpt7_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk gpt8_fck;
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT8_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt8_ick;
+
+static struct clk_hw_omap gpt8_ick_hw = {
+ .hw = {
+ .clk = &gpt8_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ OMAP24XX_CLKSEL_GPT9_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
+ gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt9_ick;
+
+static struct clk_hw_omap gpt9_ick_hw = {
+ .hw = {
+ .clk = &gpt9_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk hdq_fck;
+
+static struct clk_hw_omap hdq_fck_hw = {
+ .hw = {
+ .clk = &hdq_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk hdq_ick;
+
+static struct clk_hw_omap hdq_ick_hw = {
+ .hw = {
+ .clk = &hdq_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2c1_ick;
+
+static struct clk_hw_omap i2c1_ick_hw = {
+ .hw = {
+ .clk = &i2c1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_I2C1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2c2_ick;
+
+static struct clk_hw_omap i2c2_ick_hw = {
+ .hw = {
+ .clk = &i2c2_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_I2C2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2chs1_fck;
+
+static struct clk_hw_omap i2chs1_fck_hw = {
+ .hw = {
+ .clk = &i2chs1_fck,
+ },
+ .ops = &clkhwops_omap2430_i2chs_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk i2chs2_fck;
+
+static struct clk_hw_omap i2chs2_fck_hw = {
+ .hw = {
+ .clk = &i2chs2_fck,
+ },
+ .ops = &clkhwops_omap2430_i2chs_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk icr_ick;
+
+static struct clk_hw_omap icr_ick_hw = {
+ .hw = {
+ .clk = &icr_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP2430_EN_ICR_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static const struct clksel dsp_ick_clksel[] = {
+ { .parent = &dsp_fck, .rates = dsp_ick_rates },
+ { .parent = NULL },
+};
+
+static const char *iva2_1_ick_parent_names[] = {
+ "dsp_fck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel,
+ OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ OMAP24XX_CLKSEL_DSP_IF_MASK,
+ OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
+ iva2_1_ick_parent_names, dsp_fck_ops);
+
+static struct clk mailboxes_ick;
+
+static struct clk_hw_omap mailboxes_ick_hw = {
+ .hw = {
+ .clk = &mailboxes_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel mcbsp_fck_clksel[] = {
+ { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
+ { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
+ { .parent = NULL },
+};
+
+static const char *mcbsp1_fck_parent_names[] = {
+ "func_96m_ck", "mcbsp_clks",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+ OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+ OMAP2_MCBSP1_CLKS_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
+ mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp1_ick;
+
+static struct clk_hw_omap mcbsp1_ick_hw = {
+ .hw = {
+ .clk = &mcbsp1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+ OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+ OMAP2_MCBSP2_CLKS_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
+ mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp2_ick;
+
+static struct clk_hw_omap mcbsp2_ick_hw = {
+ .hw = {
+ .clk = &mcbsp2_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+ OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+ OMAP2_MCBSP3_CLKS_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait,
+ mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp3_ick;
+
+static struct clk_hw_omap mcbsp3_ick_hw = {
+ .hw = {
+ .clk = &mcbsp3_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+ OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+ OMAP2_MCBSP4_CLKS_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait,
+ mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp4_ick;
+
+static struct clk_hw_omap mcbsp4_ick_hw = {
+ .hw = {
+ .clk = &mcbsp4_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+ OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+ OMAP2_MCBSP5_CLKS_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait,
+ mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp5_ick;
+
+static struct clk_hw_omap mcbsp5_ick_hw = {
+ .hw = {
+ .clk = &mcbsp5_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mcspi1_fck;
+
+static const char *mcspi1_fck_parent_names[] = {
+ "func_48m_ck",
+};
+
+static struct clk_hw_omap mcspi1_fck_hw = {
+ .hw = {
+ .clk = &mcspi1_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk mcspi1_ick;
+
+static struct clk_hw_omap mcspi1_ick_hw = {
+ .hw = {
+ .clk = &mcspi1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mcspi2_fck;
+
+static struct clk_hw_omap mcspi2_fck_hw = {
+ .hw = {
+ .clk = &mcspi2_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk mcspi2_ick;
+
+static struct clk_hw_omap mcspi2_ick_hw = {
+ .hw = {
+ .clk = &mcspi2_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mcspi3_fck;
+
+static struct clk_hw_omap mcspi3_fck_hw = {
+ .hw = {
+ .clk = &mcspi3_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk mcspi3_ick;
+
+static struct clk_hw_omap mcspi3_ick_hw = {
+ .hw = {
+ .clk = &mcspi3_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate mdm_ick_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_243X },
+ { .div = 4, .val = 4, .flags = RATE_IN_243X },
+ { .div = 6, .val = 6, .flags = RATE_IN_243X },
+ { .div = 9, .val = 9, .flags = RATE_IN_243X },
+ { .div = 0 }
+};
+
+static const struct clksel mdm_ick_clksel[] = {
+ { .parent = &core_ck, .rates = mdm_ick_core_rates },
+ { .parent = NULL },
+};
+
+static const char *mdm_ick_parent_names[] = {
+ "core_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel,
+ OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
+ OMAP2430_CLKSEL_MDM_MASK,
+ OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
+ OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
+ &clkhwops_iclk_wait, mdm_ick_parent_names,
+ dsp_fck_ops);
+
+static struct clk mdm_intc_ick;
+
+static struct clk_hw_omap mdm_intc_ick_hw = {
+ .hw = {
+ .clk = &mdm_intc_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mdm_osc_ck;
+
+static struct clk_hw_omap mdm_osc_ck_hw = {
+ .hw = {
+ .clk = &mdm_osc_ck,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
+ .enable_bit = OMAP2430_EN_OSC_SHIFT,
+ .clkdm_name = "mdm_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops);
+
+static struct clk mmchs1_fck;
+
+static struct clk_hw_omap mmchs1_fck_hw = {
+ .hw = {
+ .clk = &mmchs1_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk mmchs1_ick;
+
+static struct clk_hw_omap mmchs1_ick_hw = {
+ .hw = {
+ .clk = &mmchs1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mmchs2_fck;
+
+static struct clk_hw_omap mmchs2_fck_hw = {
+ .hw = {
+ .clk = &mmchs2_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk mmchs2_ick;
+
+static struct clk_hw_omap mmchs2_ick_hw = {
+ .hw = {
+ .clk = &mmchs2_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mmchsdb1_fck;
+
+static struct clk_hw_omap mmchsdb1_fck_hw = {
+ .hw = {
+ .clk = &mmchsdb1_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops);
+
+static struct clk mmchsdb2_fck;
+
+static struct clk_hw_omap mmchsdb2_fck_hw = {
+ .hw = {
+ .clk = &mmchsdb2_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops);
+
+DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
+ OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+ OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
+ CLK_DIVIDER_ONE_BASED, NULL);
+
+static struct clk mpu_wdt_fck;
+
+static struct clk_hw_omap mpu_wdt_fck_hw = {
+ .hw = {
+ .clk = &mpu_wdt_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops);
+
+static struct clk mpu_wdt_ick;
+
+static struct clk_hw_omap mpu_wdt_ick_hw = {
+ .hw = {
+ .clk = &mpu_wdt_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk mspro_fck;
+
+static struct clk_hw_omap mspro_fck_hw = {
+ .hw = {
+ .clk = &mspro_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk mspro_ick;
+
+static struct clk_hw_omap mspro_ick_hw = {
+ .hw = {
+ .clk = &mspro_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk omapctrl_ick;
+
+static struct clk_hw_omap omapctrl_ick_hw = {
+ .hw = {
+ .clk = &omapctrl_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk pka_ick;
+
+static struct clk_hw_omap pka_ick_hw = {
+ .hw = {
+ .clk = &pka_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_PKA_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk rng_ick;
+
+static struct clk_hw_omap rng_ick_hw = {
+ .hw = {
+ .clk = &rng_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_RNG_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk sdma_fck;
+
+DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
+DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sdma_ick;
+
+static struct clk_hw_omap sdma_ick_hw = {
+ .hw = {
+ .clk = &sdma_ick,
+ },
+ .ops = &clkhwops_iclk,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
+ .clkdm_name = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sdrc_ick;
+
+static struct clk_hw_omap sdrc_ick_hw = {
+ .hw = {
+ .clk = &sdrc_ick,
+ },
+ .ops = &clkhwops_iclk,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP2430_EN_SDRC_SHIFT,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sha_ick;
+
+static struct clk_hw_omap sha_ick_hw = {
+ .hw = {
+ .clk = &sha_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_SHA_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk ssi_l4_ick;
+
+static struct clk_hw_omap ssi_l4_ick_hw = {
+ .hw = {
+ .clk = &ssi_l4_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_SSI_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_243X },
+ { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+ { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+ { .parent = NULL },
+};
+
+static const char *ssi_ssr_sst_fck_parent_names[] = {
+ "core_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
+ ssi_ssr_sst_fck_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_SSI_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
+ ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
+
+static struct clk sync_32k_ick;
+
+static struct clk_hw_omap sync_32k_ick_hw = {
+ .hw = {
+ .clk = &sync_32k_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+ { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+ { .div = 1, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel common_clkout_src_clksel[] = {
+ { .parent = &core_ck, .rates = common_clkout_src_core_rates },
+ { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
+ { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+ { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+ { .parent = NULL },
+};
+
+static const char *sys_clkout_src_parent_names[] = {
+ "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
+ OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
+ OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
+ NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
+
+DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
+ OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
+ OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static struct clk uart1_fck;
+
+static struct clk_hw_omap uart1_fck_hw = {
+ .hw = {
+ .clk = &uart1_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_UART1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart1_ick;
+
+static struct clk_hw_omap uart1_ick_hw = {
+ .hw = {
+ .clk = &uart1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_UART1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk uart2_fck;
+
+static struct clk_hw_omap uart2_fck_hw = {
+ .hw = {
+ .clk = &uart2_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_UART2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart2_ick;
+
+static struct clk_hw_omap uart2_ick_hw = {
+ .hw = {
+ .clk = &uart2_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_UART2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk uart3_fck;
+
+static struct clk_hw_omap uart3_fck_hw = {
+ .hw = {
+ .clk = &uart3_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP24XX_EN_UART3_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart3_ick;
+
+static struct clk_hw_omap uart3_ick_hw = {
+ .hw = {
+ .clk = &uart3_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_UART3_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk usb_fck;
+
+static struct clk_hw_omap usb_fck_hw = {
+ .hw = {
+ .clk = &usb_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP24XX_EN_USB_SHIFT,
+ .clkdm_name = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel usb_l4_ick_clksel[] = {
+ { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+ { .parent = NULL },
+};
+
+static const char *usb_l4_ick_parent_names[] = {
+ "core_l3_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
+ OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ OMAP24XX_CLKSEL_USB_MASK,
+ OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
+ usb_l4_ick_parent_names, dsp_fck_ops);
+
+static struct clk usbhs_ick;
+
+static struct clk_hw_omap usbhs_ick_hw = {
+ .hw = {
+ .clk = &usbhs_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_USBHS_SHIFT,
+ .clkdm_name = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops);
+
+static struct clk virt_prcm_set;
+
+static const char *virt_prcm_set_parent_names[] = {
+ "mpu_ck",
+};
+
+static const struct clk_ops virt_prcm_set_ops = {
+ .recalc_rate = &omap2_table_mpu_recalc,
+ .set_rate = &omap2_select_table_rate,
+ .round_rate = &omap2_round_to_table_rate,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
+DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
+
+static struct clk wdt1_ick;
+
+static struct clk_hw_omap wdt1_ick_hw = {
+ .hw = {
+ .clk = &wdt1_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
+ .clkdm_name = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt1_osc_ck;
+
+static const struct clk_ops wdt1_osc_ck_ops = {};
+
+DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
+DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
+
+static struct clk wdt4_fck;
+
+static struct clk_hw_omap wdt4_fck_hw = {
+ .hw = {
+ .clk = &wdt4_fck,
+ },
+ .ops = &clkhwops_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops);
+
+static struct clk wdt4_ick;
+
+static struct clk_hw_omap wdt4_ick_hw = {
+ .hw = {
+ .clk = &wdt4_ick,
+ },
+ .ops = &clkhwops_iclk_wait,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
+
+/*
+ * clkdev integration
+ */
+
+static struct omap_clk omap2430_clks[] = {
+ /* external root sources */
+ CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
+ CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
+ CLK(NULL, "osc_ck", &osc_ck, CK_243X),
+ CLK("twl", "fck", &osc_ck, CK_243X),
+ CLK(NULL, "sys_ck", &sys_ck, CK_243X),
+ CLK(NULL, "alt_ck", &alt_ck, CK_243X),
+ CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
+ /* internal analog sources */
+ CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
+ CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
+ CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
+ /* internal prcm root sources */
+ CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
+ CLK(NULL, "core_ck", &core_ck, CK_243X),
+ CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
+ CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
+ CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
+ CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
+ CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
+ CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
+ CLK(NULL, "emul_ck", &emul_ck, CK_243X),
+ /* mpu domain clocks */
+ CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
+ /* dsp domain clocks */
+ CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
+ CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
+ /* GFX domain clocks */
+ CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
+ CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
+ CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
+ /* Modem domain clocks */
+ CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
+ CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
+ /* DSS domain clocks */
+ CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
+ CLK(NULL, "dss_ick", &dss_ick, CK_243X),
+ CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
+ CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
+ CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
+ /* L3 domain clocks */
+ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
+ CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
+ CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
+ /* L4 domain clocks */
+ CLK(NULL, "l4_ck", &l4_ck, CK_243X),
+ CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
+ CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
+ /* virtual meta-group clock */
+ CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
+ /* general l4 interface ck, multi-parent functional clk */
+ CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
+ CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
+ CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
+ CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
+ CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
+ CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
+ CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
+ CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
+ CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
+ CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
+ CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
+ CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
+ CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
+ CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
+ CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
+ CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
+ CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
+ CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
+ CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
+ CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
+ CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
+ CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
+ CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
+ CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
+ CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
+ CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X),
+ CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
+ CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
+ CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X),
+ CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
+ CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
+ CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X),
+ CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
+ CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
+ CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X),
+ CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
+ CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
+ CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X),
+ CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
+ CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
+ CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X),
+ CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
+ CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
+ CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X),
+ CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
+ CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
+ CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X),
+ CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
+ CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
+ CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
+ CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
+ CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
+ CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
+ CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
+ CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
+ CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
+ CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
+ CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X),
+ CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
+ CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
+ CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
+ CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
+ CLK(NULL, "icr_ick", &icr_ick, CK_243X),
+ CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
+ CLK(NULL, "cam_fck", &cam_fck, CK_243X),
+ CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
+ CLK(NULL, "cam_ick", &cam_ick, CK_243X),
+ CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
+ CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
+ CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
+ CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
+ CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
+ CLK(NULL, "fac_ick", &fac_ick, CK_243X),
+ CLK(NULL, "fac_fck", &fac_fck, CK_243X),
+ CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
+ CLK(NULL, "hdq_ick", &hdq_ick, CK_243X),
+ CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
+ CLK(NULL, "hdq_fck", &hdq_fck, CK_243X),
+ CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
+ CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X),
+ CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
+ CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
+ CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X),
+ CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
+ CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
+ CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
+ CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
+ CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
+ CLK(NULL, "des_ick", &des_ick, CK_243X),
+ CLK("omap-sham", "ick", &sha_ick, CK_243X),
+ CLK("omap_rng", "ick", &rng_ick, CK_243X),
+ CLK(NULL, "rng_ick", &rng_ick, CK_243X),
+ CLK("omap-aes", "ick", &aes_ick, CK_243X),
+ CLK(NULL, "pka_ick", &pka_ick, CK_243X),
+ CLK(NULL, "usb_fck", &usb_fck, CK_243X),
+ CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
+ CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
+ CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
+ CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X),
+ CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
+ CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
+ CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X),
+ CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
+ CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
+ CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
+ CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
+ CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
+ CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X),
+ CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
+ CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X),
+ CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
+ CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
+ CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
+ CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X),
+};
+
+static const char *enable_init_clks[] = {
+ "apll96_ck",
+ "apll54_ck",
+ "sync_32k_ick",
+ "omapctrl_ick",
+ "gpmc_fck",
+ "sdrc_ick",
+};
+
+/*
+ * init code
+ */
+
+int __init omap2430_clk_init(void)
+{
+ const struct prcm_config *prcm;
+ struct omap_clk *c;
+ unsigned long clkrate;
+
+ prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
+ cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
+ cpu_mask = RATE_IN_243X;
+ rate_table = omap2430_rate_table;
+
+ /* Check the MPU rate set by bootloader */
+ clkrate = omap2xxx_clk_get_core_rate(&dpll_ck_hw);
+ for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+ if (!(prcm->flags & cpu_mask))
+ continue;
+ if (prcm->xtal_speed != sys_ck.rate)
+ continue;
+ if (prcm->dpll_speed <= clkrate)
+ break;
+ }
+ curr_prcm_set = prcm;
+
+ for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
+ c++) {
+ clkdev_add(&c->lk);
+ if (!__clk_init(NULL, c->lk.clk))
+ omap2_init_clk_hw_omap_clocks(c->lk.clk);
+ }
+
+ omap2_clk_disable_autoidle_all();
+
+ omap2_clk_enable_init_clocks(enable_init_clks,
+ ARRAY_SIZE(enable_init_clks));
+
+ pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ (clk_get_rate(&sys_ck) / 1000000),
+ (clk_get_rate(&sys_ck) / 100000) % 10,
+ (clk_get_rate(&dpll_ck) / 1000000),
+ (clk_get_rate(&mpu_ck) / 1000000));
+
+ return 0;
+}
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 6862904..f3fcba2 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -59,6 +59,7 @@
/* CM_CLKSEL_MPU */
#define OMAP24XX_CLKSEL_MPU_SHIFT 0
#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
+#define OMAP24XX_CLKSEL_MPU_WIDTH 5
/* CM_CLKSTCTRL_MPU */
#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
@@ -237,8 +238,10 @@
#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
#define OMAP24XX_CLKSEL_L4_SHIFT 5
#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
+#define OMAP24XX_CLKSEL_L4_WIDTH 2
#define OMAP24XX_CLKSEL_L3_SHIFT 0
#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
+#define OMAP24XX_CLKSEL_L3_WIDTH 5
/* CM_CLKSEL2_CORE */
#define OMAP24XX_CLKSEL_GPT12_SHIFT 22
@@ -361,8 +364,10 @@
#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
#define OMAP24XX_54M_SOURCE_SHIFT 5
#define OMAP24XX_54M_SOURCE_MASK (1 << 5)
+#define OMAP24XX_54M_SOURCE_WIDTH 1
#define OMAP2430_96M_SOURCE_SHIFT 4
#define OMAP2430_96M_SOURCE_MASK (1 << 4)
+#define OMAP2430_96M_SOURCE_WIDTH 1
#define OMAP24XX_48M_SOURCE_SHIFT 3
#define OMAP24XX_48M_SOURCE_MASK (1 << 3)
#define OMAP2430_ALTCLK_SOURCE_SHIFT 0
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 638da6d..91aa510 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -107,12 +107,14 @@
#define OMAP2420_CLKOUT2_EN_MASK (1 << 15)
#define OMAP2420_CLKOUT2_DIV_SHIFT 11
#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
+#define OMAP2420_CLKOUT2_DIV_WIDTH 3
#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
#define OMAP24XX_CLKOUT_EN_SHIFT 7
#define OMAP24XX_CLKOUT_EN_MASK (1 << 7)
#define OMAP24XX_CLKOUT_DIV_SHIFT 3
#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
+#define OMAP24XX_CLKOUT_DIV_WIDTH 3
#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
--
1.7.10.4
^ permalink raw reply related
* [PATCH 03/16] mm: check rb_subtree_gap correctness
From: Hugh Dickins @ 2012-11-09 20:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509D0F86.30607@gmail.com>
On Fri, 9 Nov 2012, Sasha Levin wrote:
> On 11/05/2012 05:47 PM, Michel Lespinasse wrote:
> > When CONFIG_DEBUG_VM_RB is enabled, check that rb_subtree_gap is
> > correctly set for every vma and that mm->highest_vm_end is also correct.
> >
> > Also add an explicit 'bug' variable to track if browse_rb() detected any
> > invalid condition.
> >
> > Signed-off-by: Michel Lespinasse <walken@google.com>
> > Reviewed-by: Rik van Riel <riel@redhat.com>
> >
> > ---
>
> Hi all,
>
> While fuzzing with trinity inside a KVM tools (lkvm) guest, using today's -next
> kernel, I'm getting these:
>
>
> [ 117.007714] free gap 7fba0dd1c000, correct 7fba0dcfb000
> [ 117.019773] map_count 750 rb -1
> [ 117.028362] ------------[ cut here ]------------
> [ 117.029813] kernel BUG at mm/mmap.c:439!
> [ 117.031024] invalid opcode: 0000 [#1] PREEMPT SMP DEBUG_PAGEALLOC
> [ 117.032933] Dumping ftrace buffer:
> [ 117.033972] (ftrace buffer empty)
> [ 117.035085] CPU 4
> [ 117.035676] Pid: 6859, comm: trinity-child46 Tainted: G W 3.7.0-rc4-next-20121109-sasha-00013-g9407f3c #124
> [ 117.038217] RIP: 0010:[<ffffffff81236687>] [<ffffffff81236687>] validate_mm+0x297/0x2c0
> [ 117.041056] RSP: 0018:ffff880016a4fdf8 EFLAGS: 00010296
> [ 117.041056] RAX: 0000000000000013 RBX: 00000000ffffffff RCX: 0000000000000006
> [ 117.041056] RDX: 0000000000005270 RSI: ffff880024120910 RDI: 0000000000000286
> [ 117.052131] RBP: ffff880016a4fe48 R08: 0000000000000000 R09: 0000000000000000
> [ 117.052131] R10: 0000000000000001 R11: 0000000000000000 R12: 00000000000002ee
> [ 117.052131] R13: 00007fffea1fc000 R14: ffff88002412c000 R15: 0000000000000000
> [ 117.052131] FS: 00007fba129db700(0000) GS:ffff880063600000(0000) knlGS:0000000000000000
> [ 117.052131] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 117.052131] CR2: 0000000003323288 CR3: 00000000169b2000 CR4: 00000000000406e0
> [ 117.052131] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> [ 117.052131] DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
> [ 117.052131] Process trinity-child46 (pid: 6859, threadinfo ffff880016a4e000, task ffff880024120000)
> [ 117.052131] Stack:
> [ 117.052131] ffffffff8489e201 ffffffff81235aa0 ffff88000885cac8 0000000100000000
> [ 117.052131] ffffffff812361b9 ffff88002412c000 ffff88000885cac8 ffff88000885cdc8
> [ 117.052131] ffff88000885cdd0 ffff88002412c000 ffff880016a4fe98 ffffffff812367b4
> [ 117.052131] Call Trace:
> [ 117.052131] [<ffffffff81235aa0>] ? vma_compute_subtree_gap+0x40/0x40
> [ 117.052131] [<ffffffff812361b9>] ? vma_gap_update+0x19/0x30
> [ 117.052131] [<ffffffff812367b4>] vma_link+0x94/0xe0
> [ 117.052131] [<ffffffff812386c4>] do_brk+0x2c4/0x380
> [ 117.052131] [<ffffffff812387bf>] ? sys_brk+0x3f/0x190
> [ 117.052131] [<ffffffff812388ce>] sys_brk+0x14e/0x190
> [ 117.052131] [<ffffffff83be2618>] tracesys+0xe1/0xe6
> [ 117.052131] Code: d8 41 8b 76 60 39 de 74 1b 89 da 48 c7 c7 c6 d9 89 84 31 c0 e8 01 76 94 02 eb 10 66 0f 1f 84 00 00 00 00 00
> 8b 45 c8 85 c0 74 18 <0f> 0b 4c 8d 48 e0 48 8b 70 e0 31 db c7 45 cc 00 00 00 00 e9 f4
> [ 117.052131] RIP [<ffffffff81236687>] validate_mm+0x297/0x2c0
> [ 117.052131] RSP <ffff880016a4fdf8>
> [ 117.136092] ---[ end trace 5ce250e0bf6d040c ]---
>
> Note that they are very easy to reproduce.
>
> Also, I see that lots of the code there has a local variable named 'bug' thats tracking
> whether we should BUG() later on. Why does it work that way and the BUG() isn't immediate?
3.7.0-rc4-mm1 BUGged on mm/mmap.c:439 as soon as I tried to rebuild
that kernel with Alan's tty/vt/fb patch included, no fuzzing required.
free_gap 55551d077000, correct 55551ccd2000 in my case.
It should only be affecting the minority with CONFIG_DEBUG_VM_RB=y.
I've put #if 0 around the rb_subtree_gap checking block in browse_rb(),
and running okay so far with that - but not yet done much with it.
Hugh
^ permalink raw reply
* [PATCH V6 2/2] dmaengine: add helper function to request a slave DMA channel
From: Jon Hunter @ 2012-11-09 20:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350355144.1648.5259.camel@vkoul-udesk3>
On 10/15/2012 09:39 PM, Vinod Koul wrote:
> On Tue, 2012-10-16 at 10:43 +0800, Shawn Guo wrote:
>> On Tue, Sep 25, 2012 at 10:05:01AM +0530, Vinod Koul wrote:
>>> On Mon, 2012-09-24 at 17:25 -0500, Jon Hunter wrote:
>>>>> For DT bindings, I think the binding itself shouldn't change based on my
>>>>> work but I would like these same bindings to help build the DMA engine
>>>>> code mappings.
>>>>>
>>>>> Now would it make sense to NOT merge these changes for 3.7 and postpone
>>>>> to 3.8. I can host these patches on a topic branch and merge them when
>>>>> we are ready. I plan to spend some good amount of time on my work this
>>>>> week so we should be ready pretty soon.
>>>>> One these changes are merged, users can start moving to this scheme.
>>>>
>>>> I just wanted to see how things are progressing your side. Did you
>>>> create a topic branch for this? If so let me know where I can find it, I
>>>> did not find a branch on your infradead git tree.
>>>>
>>>> I wanted to pull in the latest patches for some testing.
>>> Sorry for delay, I had everything ready, but couldn't manage to commit
>>> and push. I have pushed to topic/dmaengine_dt, it is pushing out now...
>>>
>> Vinod,
>>
>> Looks it seemed 3.7-rc1. Does that mean we have to wait for 3.8, or
>> will it show on later -rc for 3.7?
> Yes this will be merged once we work out the common interface, otherwise
> we will end up redoing interfaces for all drivers.
Hi Vinod,
A few people have been asking me if getting device-tree support for DMA
engine is plan for record for v3.8. I know that you were working through
implementing a common interface and so I wanted to check how that is
going. Do you have any insight to when device-tree support may get added?
Cheers
Jon
^ permalink raw reply
* [PATCH] i2c: at91: fix SMBus quick command
From: Jean Delvare @ 2012-11-09 19:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352481797-3520-1-git-send-email-ludovic.desroches@atmel.com>
On Fri, 9 Nov 2012 18:23:17 +0100, ludovic.desroches at atmel.com wrote:
> I tested it with i2cdetect as you suggested. EEPROMs were detected but not
> other devices (lm75 and ds1337). I have exactly the same behavior by using
> i2c-gpio driver so I think there is no major issue on a driver point of view.
Note that i2cdetect uses a different probe command for EEPROM addresses
(0x50-0x57) than for other addresses by default. You can change this
default behavior with -q and -r for testing purposes.
--
Jean Delvare
^ permalink raw reply
* [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks
From: Paul Walmsley @ 2012-11-09 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109194023.17381.62227@nucleus>
On Fri, 9 Nov 2012, Mike Turquette wrote:
> But I'm OK with the below patch in the short term. I just have one
> question: did you observe any PM regressions by skipping the clkdm
> programming?
It's still under test here but 3530ES3 Beagle passed the PM tests with it,
with no obvious warnings.
- Paul
^ permalink raw reply
* [PATCH V2 03/14] ARM: OMAP3+: Implement timer workaround for errata i103 and i767
From: Jon Hunter @ 2012-11-09 19:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509BE3E4.8050008@ti.com>
On 11/08/2012 10:55 AM, Jon Hunter wrote:
>
> On 11/07/2012 05:43 PM, Santosh Shilimkar wrote:
>> On Wednesday 07 November 2012 05:28 PM, Jon Hunter wrote:
>>>
>>> On 11/07/2012 04:14 PM, Santosh Shilimkar wrote:
>>>
>>>> Looks sensible considering alternative WAs.
>>>>
>>>> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>
>>> Thanks. With further thought I think that it would be best to combine
>>> patches #2 and #3. Really the main motivation here is the errata
>>> workaround and without actually benchmarking the timer read I should
>>> not claim the improvement in overhead as stated in patch #2. So I
>>> have combined #2 and #3 and updated the changelog/comments
>>> appropriately. Let me know if you guys are ok with this.
>>>
>> Yep. Sounds good.
>
> Updated, removing the additional OMAP_CLKEVT/SRC_POSTEDMODE definitions.
Another minor update after rebasing on Tony's linux-omap master. I
needed to fix-up headers included.
Cheers
Jon
>From 0b2e3ef2cea7896f6466e010f9ab22a86a00bba1 Mon Sep 17 00:00:00 2001
From: Jon Hunter <jon-hunter@ti.com>
Date: Thu, 27 Sep 2012 12:47:43 -0500
Subject: [PATCH] ARM: OMAP3+: Implement timer workaround for errata i103 and
i767
Errata Titles:
i103: Delay needed to read some GP timer, WD timer and sync timer
registers after wakeup (OMAP3/4)
i767: Delay needed to read some GP timer registers after wakeup (OMAP5)
Description (i103/i767):
If a General Purpose Timer (GPTimer) is in posted mode
(TSICR [2].POSTED=1), due to internal resynchronizations, values read in
TCRR, TCAR1 and TCAR2 registers right after the timer interface clock
(L4) goes from stopped to active may not return the expected values. The
most common event leading to this situation occurs upon wake up from
idle.
GPTimer non-posted synchronization mode is not impacted by this
limitation.
Workarounds:
1). Disable posted mode
2). Use static dependency between timer clock domain and MPUSS clock
domain
3). Use no-idle mode when the timer is active
Workarounds #2 and #3 are not pratical from a power standpoint and so
workaround #1 has been implemented. Disabling posted mode adds some CPU
overhead for configuring and reading the timers as the CPU has to wait
for accesses to be re-synchronised within the timer. However, disabling
posted mode guarantees correct operation.
Please note that it is safe to use posted mode for timers if the counter
(TCRR) and capture (TCARx) registers will never be read. An example of
this is the clock-event system timer. This is used by the kernel to
schedule events however, the timers counter is never read and capture
registers are not used. Given that the kernel configures this timer
often yet never reads the counter register it is safe to enable posted
mode in this case. Hence, for the timer used for kernel clock-events,
posted mode is enabled by overriding the errata for devices that are
impacted by this defect.
For drivers using the timers that do not read the counter or capture
registers and wish to use posted mode, can override the errata and
enable posted mode by making the following function calls.
omap_dm_timer_override_errata(timer, OMAP_TIMER_ERRATA_I103_I767);
omap_dm_timer_enable_posted(timer);
Both dmtimers and watchdogs are impacted by this defect this patch only
implements the workaround for the dmtimer. Currently the watchdog driver
does not read the counter register and so no workaround is necessary.
Posted mode will be disabled for all OMAP2+ devices (including AM33xx)
using a GP timer as a clock-source timer to guarantee correct operation.
This is not necessary for OMAP24xx devices but the default clock-source
timer for OMAP24xx devices is the 32k-sync timer and not the GP timer
and so should not have any impact. This should be re-visited for future
devices if this errata is fixed.
Confirmed with Vaibhav Hiremath that this bug also impacts AM33xx
devices.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/timer.c | 35 +++++++++++++----
arch/arm/plat-omap/dmtimer.c | 60 ++++++++++++++++++++++++++++-
arch/arm/plat-omap/include/plat/dmtimer.h | 18 +++++++--
3 files changed, 100 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index a135d28..23ebe15 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -225,7 +225,8 @@ void __init omap_dmtimer_init(void)
static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
int gptimer_id,
const char *fck_source,
- const char *property)
+ const char *property,
+ int posted)
{
char name[10]; /* 10 = sizeof("gptXX_Xck0") */
const char *oh_name;
@@ -311,10 +312,15 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
}
__omap_dm_timer_init_regs(timer);
__omap_dm_timer_reset(timer, 1, 1);
- timer->posted = 1;
- timer->rate = clk_get_rate(timer->fclk);
+ if (posted)
+ omap_dm_timer_enable_posted(timer);
+ /* Check that the intended posted configuration matches the actual */
+ if (posted != timer->posted)
+ return -EINVAL;
+
+ timer->rate = clk_get_rate(timer->fclk);
timer->reserved = 1;
return res;
@@ -326,7 +332,17 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
{
int res;
- res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property);
+ omap_dm_timer_populate_errata(&clkev);
+
+ /*
+ * For clock-event timers we never read the timer counter and
+ * so we are not impacted by errata i103 and i767. Therefore,
+ * we can safely ignore this errata for clock-event timers.
+ */
+ omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
+
+ res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
+ OMAP_TIMER_POSTED);
BUG_ON(res);
omap2_gp_timer_irq.dev_id = &clkev;
@@ -360,7 +376,7 @@ static bool use_gptimer_clksrc;
static cycle_t clocksource_read_cycles(struct clocksource *cs)
{
return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
- OMAP_TIMER_POSTED);
+ OMAP_TIMER_NONPOSTED);
}
static struct clocksource clocksource_gpt = {
@@ -375,7 +391,7 @@ static u32 notrace dmtimer_read_sched_clock(void)
{
if (clksrc.reserved)
return __omap_dm_timer_read_counter(&clksrc,
- OMAP_TIMER_POSTED);
+ OMAP_TIMER_NONPOSTED);
return 0;
}
@@ -453,12 +469,15 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
{
int res;
- res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL);
+ omap_dm_timer_populate_errata(&clksrc);
+
+ res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
+ OMAP_TIMER_NONPOSTED);
BUG_ON(res);
__omap_dm_timer_load_start(&clksrc,
OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
- OMAP_TIMER_POSTED);
+ OMAP_TIMER_NONPOSTED);
setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 9dca23e..9a15123 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -43,6 +43,7 @@
#include <linux/of.h>
#include <linux/of_device.h>
+#include <plat/cpu.h>
#include <plat/dmtimer.h>
static u32 omap_reserved_systimers;
@@ -128,8 +129,8 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
}
__omap_dm_timer_reset(timer, 0, 0);
+ omap_dm_timer_enable_posted(timer);
omap_dm_timer_disable(timer);
- timer->posted = 1;
}
int omap_dm_timer_prepare(struct omap_dm_timer *timer)
@@ -173,6 +174,61 @@ int omap_dm_timer_reserve_systimer(int id)
return 0;
}
+/**
+ * omap_dm_timer_populate_errata - populate errata flags for a timer
+ * @timer: pointer to timer handle
+ *
+ * For a given timer, populate the timer errata flags that are specific to the
+ * OMAP device being used.
+ */
+void omap_dm_timer_populate_errata(struct omap_dm_timer *timer)
+{
+ timer->errata = 0;
+
+ if (cpu_class_is_omap1() || cpu_is_omap24xx())
+ return;
+
+ timer->errata = OMAP_TIMER_ERRATA_I103_I767;
+}
+
+/**
+ * omap_dm_timer_override_errata - override errata flags for a timer
+ * @timer: pointer to timer handle
+ * @errata: errata flags to be ignored
+ *
+ * For a given timer, override a timer errata by clearing the flags specified
+ * by the errata argument. A specific erratum should only be overridden for a
+ * timer if the timer is used in such a way the erratum has no impact.
+ */
+void omap_dm_timer_override_errata(struct omap_dm_timer *timer, u32 errata)
+{
+ timer->errata &= ~errata;
+}
+
+/*
+ * omap_dm_timer_enable_posted - enables write posted mode
+ * @timer: pointer to timer instance handle
+ *
+ * Enables the write posted mode for the timer. When posted mode is enabled
+ * writes to certain timer registers are immediately acknowledged by the
+ * internal bus and hence prevents stalling the CPU waiting for the write to
+ * complete. Enabling this feature can improve performance for writing to the
+ * timer registers.
+ */
+void omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
+{
+ if (timer->posted)
+ return;
+
+ if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
+ return;
+
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
+ OMAP_TIMER_CTRL_POSTED);
+ timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
+ timer->posted = OMAP_TIMER_POSTED;
+}
+
struct omap_dm_timer *omap_dm_timer_request(void)
{
struct omap_dm_timer *timer = NULL, *t;
@@ -805,6 +861,8 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
timer->irq = irq->start;
timer->pdev = pdev;
+ omap_dm_timer_populate_errata(timer);
+
/* Skip pm_runtime_enable for OMAP1 */
if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
pm_runtime_enable(dev);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 1bee0ac..2ebc8d6 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -66,6 +66,16 @@
#define OMAP_TIMER_NEEDS_RESET 0x10000000
#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
+/*
+ * timer errata flags
+ *
+ * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
+ * errata prevents us from using posted mode on these devices, unless the
+ * timer counter register is never read. For more details please refer to
+ * the OMAP3/4/5 errata documents.
+ */
+#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
+
struct omap_timer_capability_dev_attr {
u32 timer_capability;
};
@@ -102,6 +112,9 @@ struct dmtimer_platform_data {
};
int omap_dm_timer_reserve_systimer(int id);
+void omap_dm_timer_populate_errata(struct omap_dm_timer *timer);
+void omap_dm_timer_override_errata(struct omap_dm_timer *timer, u32 errata);
+void omap_dm_timer_enable_posted(struct omap_dm_timer *timer);
struct omap_dm_timer *omap_dm_timer_request(void);
struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
@@ -273,6 +286,7 @@ struct omap_dm_timer {
int ctx_loss_count;
int revision;
u32 capability;
+ u32 errata;
struct platform_device *pdev;
struct list_head node;
};
@@ -344,10 +358,6 @@ static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
l |= 1 << 2;
__raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
-
- /* Match hardware reset default of posted mode */
- __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
- OMAP_TIMER_CTRL_POSTED, 0);
}
static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
--
1.7.9.5
^ permalink raw reply related
* [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks
From: Mike Turquette @ 2012-11-09 19:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1211091906340.20703@utopia.booyaka.com>
Quoting Paul Walmsley (2012-11-09 11:08:00)
> On Fri, 9 Nov 2012, Paul Walmsley wrote:
>
> > On Thu, 8 Nov 2012, Mike Turquette wrote:
> >
> > > You're right. In my rush I glossed over the clkdm decrement part. In
> > > light of the suspend/resume issues I'm not sure this approach is really
> > > valid. I think getting to the bottom of those issues will give the
> > > final word.
> >
> > What do you think about something like this? It's still under test and
> > review here, but seems to avoid the warnings on 3530ES3 Beagle at least.
> >
> > The usage of __clk_get_enable_count() in this code still seems like a hack
> > to me. It would be better for the CCF to call a different clk_hw_ops
> > function pointer for the disable-unused-clocks case. But if you agree,
> > and plan to fix this, or have some other cleaner fix in mind for the near
> > future, then something like this seems reasonable for the short term to
> > me. What do you think?
>
For avoiding the WARNs, this seems fine to me. And I agree that a new
clk_ops function pointer is needed. Maybe something like,
void (*unused_disable)(struct clk_hw *hw);
But I'm OK with the below patch in the short term. I just have one
question: did you observe any PM regressions by skipping the clkdm
programming?
Thanks,
Mike
> Here's the patch. The changes to clkdm_clk_disable() are the important
> ones, the rest can be ignored for the purposes of this review.
>
>
> - Paul
>
> From: Mike Turquette <mturquette@ti.com>
> Date: Fri, 9 Nov 2012 11:28:42 -0700
> Subject: [PATCH] ARM: OMAP2+: clockdomain: bypass clockdomain handling when
> disabling unused clks
>
> The OMAP port to the common clk framework[1] resulted in spurious WARNs
> while disable unused clocks. This is due to _clkdm_clk_hwmod_disable
> catching clkdm->usecount's with a value of zero. Even less desirable it
> would not allow the clkdm_clk_disable function pointer to get called due
> to an early return of -ERANGE.
>
> This patch adds a check for such a corner case by skipping the WARN and
> early return in the event that clkdm->usecount and clk->enable_usecount
> are both zero. Presumably this could only happen during the check for
> unused clocks at boot-time.
>
> [1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824
>
> Signed-off-by: Mike Turquette <mturquette@ti.com>
> [paul at pwsan.com: split the hwmod and clock disable cases; modified the
> code to skip the clockdomain handling during the disable-unused-clocks phase]
> ---
> arch/arm/mach-omap2/clockdomain.c | 91 ++++++++++++++++++++++---------------
> 1 file changed, 54 insertions(+), 37 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
> index 64e5046..1bd0ff0 100644
> --- a/arch/arm/mach-omap2/clockdomain.c
> +++ b/arch/arm/mach-omap2/clockdomain.c
> @@ -22,6 +22,7 @@
> #include <linux/clk.h>
> #include <linux/limits.h>
> #include <linux/err.h>
> +#include <linux/clk-private.h>
>
> #include <linux/io.h>
>
> @@ -947,35 +948,6 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
> return 0;
> }
>
> -static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
> -{
> - unsigned long flags;
> -
> - if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
> - return -EINVAL;
> -
> - spin_lock_irqsave(&clkdm->lock, flags);
> -
> - if (atomic_read(&clkdm->usecount) == 0) {
> - spin_unlock_irqrestore(&clkdm->lock, flags);
> - WARN_ON(1); /* underflow */
> - return -ERANGE;
> - }
> -
> - if (atomic_dec_return(&clkdm->usecount) > 0) {
> - spin_unlock_irqrestore(&clkdm->lock, flags);
> - return 0;
> - }
> -
> - arch_clkdm->clkdm_clk_disable(clkdm);
> - pwrdm_state_switch(clkdm->pwrdm.ptr);
> - spin_unlock_irqrestore(&clkdm->lock, flags);
> -
> - pr_debug("clockdomain: %s: disabled\n", clkdm->name);
> -
> - return 0;
> -}
> -
> /**
> * clkdm_clk_enable - add an enabled downstream clock to this clkdm
> * @clkdm: struct clockdomain *
> @@ -1018,15 +990,39 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
> */
> int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
> {
> - /*
> - * XXX Rewrite this code to maintain a list of enabled
> - * downstream clocks for debugging purposes?
> - */
> + unsigned long flags;
> + int force_disable = 0;
>
> - if (!clk)
> + if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
> return -EINVAL;
>
> - return _clkdm_clk_hwmod_disable(clkdm);
> + spin_lock_irqsave(&clkdm->lock, flags);
> +
> + /* corner case: disabling unused clocks */
> + force_disable = (__clk_get_enable_count(clk) == 0) ? 1 : 0;
> + if (force_disable)
> + goto ccd_exit;
> +
> + if (atomic_read(&clkdm->usecount) == 0) {
> + spin_unlock_irqrestore(&clkdm->lock, flags);
> + WARN_ON(1); /* underflow */
> + return -ERANGE;
> + }
> +
> + if (atomic_dec_return(&clkdm->usecount) > 0) {
> + spin_unlock_irqrestore(&clkdm->lock, flags);
> + return 0;
> + }
> +
> + arch_clkdm->clkdm_clk_disable(clkdm);
> + pwrdm_state_switch(clkdm->pwrdm.ptr);
> +
> + pr_debug("clockdomain: %s: disabled\n", clkdm->name);
> +
> +ccd_exit:
> + spin_unlock_irqrestore(&clkdm->lock, flags);
> +
> + return 0;
> }
>
> /**
> @@ -1077,6 +1073,8 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
> */
> int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
> {
> + unsigned long flags;
> +
> /* The clkdm attribute does not exist yet prior OMAP4 */
> if (cpu_is_omap24xx() || cpu_is_omap34xx())
> return 0;
> @@ -1086,9 +1084,28 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
> * downstream hwmods for debugging purposes?
> */
>
> - if (!oh)
> + if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
> return -EINVAL;
>
> - return _clkdm_clk_hwmod_disable(clkdm);
> + spin_lock_irqsave(&clkdm->lock, flags);
> +
> + if (atomic_read(&clkdm->usecount) == 0) {
> + spin_unlock_irqrestore(&clkdm->lock, flags);
> + WARN_ON(1); /* underflow */
> + return -ERANGE;
> + }
> +
> + if (atomic_dec_return(&clkdm->usecount) > 0) {
> + spin_unlock_irqrestore(&clkdm->lock, flags);
> + return 0;
> + }
> +
> + arch_clkdm->clkdm_clk_disable(clkdm);
> + pwrdm_state_switch(clkdm->pwrdm.ptr);
> + spin_unlock_irqrestore(&clkdm->lock, flags);
> +
> + pr_debug("clockdomain: %s: disabled\n", clkdm->name);
> +
> + return 0;
> }
>
> --
> 1.7.10.4
^ permalink raw reply
* [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks
From: Paul Walmsley @ 2012-11-09 19:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1211091900250.20703@utopia.booyaka.com>
On Fri, 9 Nov 2012, Paul Walmsley wrote:
> On Thu, 8 Nov 2012, Mike Turquette wrote:
>
> > You're right. In my rush I glossed over the clkdm decrement part. In
> > light of the suspend/resume issues I'm not sure this approach is really
> > valid. I think getting to the bottom of those issues will give the
> > final word.
>
> What do you think about something like this? It's still under test and
> review here, but seems to avoid the warnings on 3530ES3 Beagle at least.
>
> The usage of __clk_get_enable_count() in this code still seems like a hack
> to me. It would be better for the CCF to call a different clk_hw_ops
> function pointer for the disable-unused-clocks case. But if you agree,
> and plan to fix this, or have some other cleaner fix in mind for the near
> future, then something like this seems reasonable for the short term to
> me. What do you think?
Here's the patch. The changes to clkdm_clk_disable() are the important
ones, the rest can be ignored for the purposes of this review.
- Paul
From: Mike Turquette <mturquette@ti.com>
Date: Fri, 9 Nov 2012 11:28:42 -0700
Subject: [PATCH] ARM: OMAP2+: clockdomain: bypass clockdomain handling when
disabling unused clks
The OMAP port to the common clk framework[1] resulted in spurious WARNs
while disable unused clocks. This is due to _clkdm_clk_hwmod_disable
catching clkdm->usecount's with a value of zero. Even less desirable it
would not allow the clkdm_clk_disable function pointer to get called due
to an early return of -ERANGE.
This patch adds a check for such a corner case by skipping the WARN and
early return in the event that clkdm->usecount and clk->enable_usecount
are both zero. Presumably this could only happen during the check for
unused clocks at boot-time.
[1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824
Signed-off-by: Mike Turquette <mturquette@ti.com>
[paul at pwsan.com: split the hwmod and clock disable cases; modified the
code to skip the clockdomain handling during the disable-unused-clocks phase]
---
arch/arm/mach-omap2/clockdomain.c | 91 ++++++++++++++++++++++---------------
1 file changed, 54 insertions(+), 37 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 64e5046..1bd0ff0 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -22,6 +22,7 @@
#include <linux/clk.h>
#include <linux/limits.h>
#include <linux/err.h>
+#include <linux/clk-private.h>
#include <linux/io.h>
@@ -947,35 +948,6 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
return 0;
}
-static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
-{
- unsigned long flags;
-
- if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
- return -EINVAL;
-
- spin_lock_irqsave(&clkdm->lock, flags);
-
- if (atomic_read(&clkdm->usecount) == 0) {
- spin_unlock_irqrestore(&clkdm->lock, flags);
- WARN_ON(1); /* underflow */
- return -ERANGE;
- }
-
- if (atomic_dec_return(&clkdm->usecount) > 0) {
- spin_unlock_irqrestore(&clkdm->lock, flags);
- return 0;
- }
-
- arch_clkdm->clkdm_clk_disable(clkdm);
- pwrdm_state_switch(clkdm->pwrdm.ptr);
- spin_unlock_irqrestore(&clkdm->lock, flags);
-
- pr_debug("clockdomain: %s: disabled\n", clkdm->name);
-
- return 0;
-}
-
/**
* clkdm_clk_enable - add an enabled downstream clock to this clkdm
* @clkdm: struct clockdomain *
@@ -1018,15 +990,39 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
*/
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
{
- /*
- * XXX Rewrite this code to maintain a list of enabled
- * downstream clocks for debugging purposes?
- */
+ unsigned long flags;
+ int force_disable = 0;
- if (!clk)
+ if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
return -EINVAL;
- return _clkdm_clk_hwmod_disable(clkdm);
+ spin_lock_irqsave(&clkdm->lock, flags);
+
+ /* corner case: disabling unused clocks */
+ force_disable = (__clk_get_enable_count(clk) == 0) ? 1 : 0;
+ if (force_disable)
+ goto ccd_exit;
+
+ if (atomic_read(&clkdm->usecount) == 0) {
+ spin_unlock_irqrestore(&clkdm->lock, flags);
+ WARN_ON(1); /* underflow */
+ return -ERANGE;
+ }
+
+ if (atomic_dec_return(&clkdm->usecount) > 0) {
+ spin_unlock_irqrestore(&clkdm->lock, flags);
+ return 0;
+ }
+
+ arch_clkdm->clkdm_clk_disable(clkdm);
+ pwrdm_state_switch(clkdm->pwrdm.ptr);
+
+ pr_debug("clockdomain: %s: disabled\n", clkdm->name);
+
+ccd_exit:
+ spin_unlock_irqrestore(&clkdm->lock, flags);
+
+ return 0;
}
/**
@@ -1077,6 +1073,8 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
*/
int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
{
+ unsigned long flags;
+
/* The clkdm attribute does not exist yet prior OMAP4 */
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return 0;
@@ -1086,9 +1084,28 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
* downstream hwmods for debugging purposes?
*/
- if (!oh)
+ if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
return -EINVAL;
- return _clkdm_clk_hwmod_disable(clkdm);
+ spin_lock_irqsave(&clkdm->lock, flags);
+
+ if (atomic_read(&clkdm->usecount) == 0) {
+ spin_unlock_irqrestore(&clkdm->lock, flags);
+ WARN_ON(1); /* underflow */
+ return -ERANGE;
+ }
+
+ if (atomic_dec_return(&clkdm->usecount) > 0) {
+ spin_unlock_irqrestore(&clkdm->lock, flags);
+ return 0;
+ }
+
+ arch_clkdm->clkdm_clk_disable(clkdm);
+ pwrdm_state_switch(clkdm->pwrdm.ptr);
+ spin_unlock_irqrestore(&clkdm->lock, flags);
+
+ pr_debug("clockdomain: %s: disabled\n", clkdm->name);
+
+ return 0;
}
--
1.7.10.4
^ permalink raw reply related
* [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks
From: Paul Walmsley @ 2012-11-09 19:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109011738.17381.88199@nucleus>
On Thu, 8 Nov 2012, Mike Turquette wrote:
> You're right. In my rush I glossed over the clkdm decrement part. In
> light of the suspend/resume issues I'm not sure this approach is really
> valid. I think getting to the bottom of those issues will give the
> final word.
What do you think about something like this? It's still under test and
review here, but seems to avoid the warnings on 3530ES3 Beagle at least.
The usage of __clk_get_enable_count() in this code still seems like a hack
to me. It would be better for the CCF to call a different clk_hw_ops
function pointer for the disable-unused-clocks case. But if you agree,
and plan to fix this, or have some other cleaner fix in mind for the near
future, then something like this seems reasonable for the short term to
me. What do you think?
- Paul
^ permalink raw reply
* [PATCH 1/6] spi: imx: specify spi base for device tree probe
From: Steffen Trumtrar @ 2012-11-09 19:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109163830.GP23807@opensource.wolfsonmicro.com>
On Fri, Nov 09, 2012 at 04:38:30PM +0000, Mark Brown wrote:
> On Fri, Nov 09, 2012 at 03:00:20PM +0100, Steffen Trumtrar wrote:
>
> > * This breaks compatibility with user space applications between non-DT and DT.
>
> > * On platforms that are in between DT and non-DT, it breaks registration of
> > devices via spi_board_info.
>
> > Use the same method as 7e6086d9e54a159a6257c02bb7fc5805c614aad2 does for gpios:
> > Use alias to identify the spi port, and then specify the base via the port id.
> > If alias is not defined in DT, allocate the base dynamically.
>
> This sounds like a fix userspace and/or complete your DT conversion
> problem...
Well, it may lead to problems in userspace and does lead to problems with an
incomplete DT support, but there are only so many hours in a day...
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 6/6] ASoC: fsl: add imx-wm8974 machine driver
From: Steffen Trumtrar @ 2012-11-09 18:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109153629.GK23807@opensource.wolfsonmicro.com>
On Fri, Nov 09, 2012 at 03:36:30PM +0000, Mark Brown wrote:
> On Fri, Nov 09, 2012 at 03:00:25PM +0100, Steffen Trumtrar wrote:
>
> > +static int imx_wm8974_dai_init(struct snd_soc_pcm_runtime *rtd)
> > +{
> > + struct imx_wm8974_data *data = container_of(rtd->card,
> > + struct imx_wm8974_data, card);
> > + struct device *dev = rtd->card->dev;
> > + int ret;
> > +
> > + /* the pll stability peaks at N=8 and around 90MHz.
> > + * This values are best reached with a 12.288MHz or
> > + * 11.289MHz clock. As the first is closer to N=8 in
> > + * more situations, chose 12.288MHz as the target clock
> > + * (ref: datasheet section "Master Clock and Phase Locked Loop")*/
> > + ret = snd_soc_dai_set_pll(rtd->codec_dai, 0, 0, data->clk_frequency,
> > + 12288000);
>
> This seems far from ideal - it's starting the PLL at system boot and
> just leaving it running. This will be power inefficient when the system
> is not playing audio as the PLL will be consuming power but not used for
> anything. You could also do the same thing with the MCLK.
>
> Note also that a 12.288MHz clock is only suitable for 8kHz based sample
> rates, for CD audio 44.1kHz based rates like most media files 11.2896MHz
> should be chosen. The driver may want to switch dynamically at runtime
> to support the widest possible range of rates.
>
Maybe I had a weird test system, but I only got correct audio with the
12.288 MHz clock from the PLL. And this was for 48Khz and 44Khz audio.
So, as the datasheet was not really that clear about the clock as you
are, I chose the above clock freq.
> > + data->codec_clk = clk_get(&codec_pdev->dev, NULL);
> > + if (IS_ERR(data->codec_clk)) {
>
> devm_clk_get() - this'd free the clock that's leaked on removal.
Okay
Regards,
Steffen
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH v3 1/7] ARM: OMAP2xxx: hwmod: Convert SHAM crypto device data to hwmod
From: Mark A. Greer @ 2012-11-09 18:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109180031.GQ6801@atomide.com>
On Fri, Nov 09, 2012 at 10:00:31AM -0800, Tony Lindgren wrote:
> * Paul Walmsley <paul@pwsan.com> [121109 09:13]:
> > On Fri, 9 Nov 2012, Mark A. Greer wrote:
> >
> > > On Fri, Nov 09, 2012 at 06:10:20PM +0200, Kasatkin, Dmitry wrote:
> > >
> > > > Why not using macros as it was before?
> > > >
> > > > OMAP24XX_SEC_SHA1MD5_BASE
> > >
> > > I am following the precedent set in the existing code of that file
> > > which uses the actual address instead of a macro (except for uart).
> > >
> > > I have no preference but I believe that is how Paul prefers it.
> > >
> > > Paul?
> >
> > My upstream prefers the raw addresses, I believe, under the rationale that
> > it allows the macro definitions to be removed from arch/arm/mach-omap2.
> > This reduces the total number of lines of code in that directory - and
> > this is currently an overriding concern of my upstreams.
> >
> > So, yes the address format in your patch is fine.
>
> Yes that should be the only place where that address is defined.
> If OMAP24XX_SEC_SHA1MD5_BASE is used in multiple locations, then
> it makes sense to define it in some local header.
According to my 'git grep', its the only place so the patch should be good.
Mark
--
^ permalink raw reply
* [PATCH] ARM: backtrace: avoid crash on large invalid fp value
From: Colin Cross @ 2012-11-09 18:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109105648.GA2048@linaro.org>
On Fri, Nov 9, 2012 at 2:56 AM, Dave Martin <dave.martin@linaro.org> wrote:
> On Thu, Nov 08, 2012 at 06:05:52PM -0800, Colin Cross wrote:
>> On Mon, Nov 5, 2012 at 2:54 AM, Dave Martin <dave.martin@linaro.org> wrote:
>> > On Fri, Nov 02, 2012 at 04:47:38PM -0700, Colin Cross wrote:
>> >> On Wed, Oct 10, 2012 at 4:15 AM, Dave Martin <dave.martin@linaro.org> wrote:
>> >> > On Tue, Oct 09, 2012 at 11:46:12PM -0700, Todd Poynor wrote:
>> >> >> Invalid frame pointer (signed) -4 <= fp <= -1 defeats check for too high
>> >> >> on overflow.
>> >> >>
>> >> >> Signed-off-by: Todd Poynor <toddpoynor@google.com>
>> >> >> ---
>> >> >> arch/arm/kernel/stacktrace.c | 2 +-
>> >> >> 1 files changed, 1 insertions(+), 1 deletions(-)
>> >> >>
>> >> >> diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
>> >> >> index 00f79e5..6315162 100644
>> >> >> --- a/arch/arm/kernel/stacktrace.c
>> >> >> +++ b/arch/arm/kernel/stacktrace.c
>> >> >> @@ -31,7 +31,7 @@ int notrace unwind_frame(struct stackframe *frame)
>> >> >> high = ALIGN(low, THREAD_SIZE);
>> >> >>
>> >> >> /* check current frame pointer is within bounds */
>> >> >> - if (fp < (low + 12) || fp + 4 >= high)
>> >> >> + if (fp < (low + 12) || fp >= high - 4)
>> >> >> return -EINVAL;
>> >> >>
>> >> >> /* restore the registers from the stack frame */
>> >> >
>> >> > sp and fp can still be complete garbage in the case of a corrupted frame,
>> >> > so low + 12 can still overflow and cause us to read beyond the stack base.
>> >> >
>> >> > A more robust patch might be as follows. This also checks for misaligned
>> >> > fp and sp values, since those indicate corruption and there can be no
>> >> > sensible way to interpret the resulting frame in that case.
>> >> >
>> >> > Also, according to the definition of current_thread_info(),
>> >> > IS_ALIGNED(sp, THREAD_SIZE) indicates a full stack extending from sp
>> >> > to sp + THREAD_SIZE, and not an empty stack extending from sp -
>> >> > THREAD_SIZE to sp. We cannot backtrace this situation anyway, since
>> >> > that would imply that the frame record extends beyond the stack...
>> >> > but this patch tidies it up in the interest of clarity.
>> >> >
>> >> > Cheers
>> >> > ---Dave
>> >> >
>> >> > (untested)
>> >> >
>> >> > diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
>> >> > index 00f79e5..fec82be 100644
>> >> > --- a/arch/arm/kernel/stacktrace.c
>> >> > +++ b/arch/arm/kernel/stacktrace.c
>> >> > @@ -28,10 +28,20 @@ int notrace unwind_frame(struct stackframe *frame)
>> >> >
>> >> > /* only go to a higher address on the stack */
>> >> > low = frame->sp;
>> >> > - high = ALIGN(low, THREAD_SIZE);
>> >> > + if (!IS_ALIGNED(fp, 4))
>> >> > + return -EINVAL;
>> >> > +
>> >> > + /*
>> >> > + * low + 1 here ensures that high > sp, consistent with the
>> >> > + * definition of current_thread_info().
>> >> > + * We subtract 1 to compute the highest allowable byte address.
>> >> > + * Otherwise, we might get high == 0 which would confuse our
>> >> > + * comparisons.
>> >> > + */
>> >> > + high = ALIGN(low + 1, THREAD_SIZE) - 1;
>>
>> ARM eabi stacks are full-descending, meaning that if the sp is a
>> multiple of THREAD_SIZE, the stack is empty. current_thread_info
>> takes a short-cut and assumes it can never be called on an empty
>> stack, but better not to propagate that anywhere else.
>
> The effect of the code is consistent with current_thread_info():
>
> low = THREAD_SIZE * X --> high = THREAD_SIZE * (X + 1) - 1
> low = THREAD_SIZE * (X + 1) - 1 --> high = THREAD_SIZE * (X + 1) - 1
>
> i.e., low = THREAD_SIZE * X is treated as a full stack.
current_thread_info() is assuming a sane stack, where the sp is
between [THREAD_SIZE * X + sizeof(struct thread_info), THREAD_SIZE *
(X + 1) - 8] (see THREAD_START_SP). It should never see sp =
THREAD_SIZE * X, so we shouldn't be copying its behavior in that case.
sp = THREAD_SIZE * x being a full stack would mean that the stack has
passed all the way through the struct thread_info stored at the lower
addresses of the stack, corrupting the task struct, saved registers,
and likely the stack too. On the other hand, sp = THREAD_SIZE * x
being an empty stack would mean somebody started a stack higher than
THREAD_START_SP. Neither one really makes sense, maybe I should just
validate the sp above the thread_info and below THREAD_START_SP.
> The comment relates to the case where the stack is right at the top
> of the address space: if we define high as ALIGN(low + 1, THREAD_SIZE),
> then high overflow to zero in this case, giving unexpected results
> for comparisons "some_address >= high".
>
> Definig high as the address of the last byte of the stack (instead of
> the first byte after the stack) avoids this kind of problem, providing
> that "some_address >= high" is rewritten as "some_address > high" in
> our comparisons.
I agree with using - 1 (or - 4) to prevent high wrapping, but maybe
capping at THREAD_START_SP would simplify the code.
> I don't know whether any stack will be at the top of the address space
> in practice, but I prefer to avoid unnecessary assumptions where
> possible.
>
>
> Do you agree with the code as-is, or does something need to be changed/
> clarified?
>
>> >> >
>> >> > /* check current frame pointer is within bounds */
>> >> > - if (fp < (low + 12) || fp + 4 >= high)
>> >> > + if (fp < 12 || fp - 12 < low || fp > high)
>> >> > return -EINVAL;
>> >> >
>> >> > /* restore the registers from the stack frame */
>> >> > @@ -39,6 +49,10 @@ int notrace unwind_frame(struct stackframe *frame)
>> >> > frame->sp = *(unsigned long *)(fp - 8);
>> >> > frame->pc = *(unsigned long *)(fp - 4);
>> >> >
>> >> > + /* Do not claim the frame is valid if if is obviously corrupt: */
>> >> > + if (!IS_ALIGNED(frame->fp, 4))
>> >> > + return -EINVAL;
>> >> > +
>> >> > return 0;
>> >> > }
>> >> > #endif
>> >> >
>> >> >
>> >> > _______________________________________________
>> >> > linux-arm-kernel mailing list
>> >> > linux-arm-kernel at lists.infradead.org
>> >> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>> >>
>> >> Dave or Todd, mind reposting this, or should I squash it into my
>> >> CONFIG_SMP stacktrace series?
>> >
>> > I'm happy for you to fold my patch into your series if you agree
>> > with it. Ideally, please fix my typo in the final comment ("if IT is
>> > obviously corrupt").
>> >
>> > Do I assume correctly that you are already testing this stuff?
>>
>> I've been testing it by repeatedly dumping the stack of a running
>> thread (cat /dev/urandom > /dev/null) and making sure it doesn't
>> panic, and by dumping all the threads in a idle system and making sure
>> they all end at the normal user or kernel thread initial frames
>> (do_exit, kernel_thread_exit, or ret_fast_syscall).
>
> OK -- that's good to know.
>
> I'm still assuming that you're rolling this into your series. Let me
> know if you want me to post a separate patch.
I'll squash it in to mine.
^ permalink raw reply
* [PATCH v3 1/7] ARM: OMAP2xxx: hwmod: Convert SHAM crypto device data to hwmod
From: Tony Lindgren @ 2012-11-09 18:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1211091709000.20703@utopia.booyaka.com>
* Paul Walmsley <paul@pwsan.com> [121109 09:13]:
> On Fri, 9 Nov 2012, Mark A. Greer wrote:
>
> > On Fri, Nov 09, 2012 at 06:10:20PM +0200, Kasatkin, Dmitry wrote:
> >
> > > Why not using macros as it was before?
> > >
> > > OMAP24XX_SEC_SHA1MD5_BASE
> >
> > I am following the precedent set in the existing code of that file
> > which uses the actual address instead of a macro (except for uart).
> >
> > I have no preference but I believe that is how Paul prefers it.
> >
> > Paul?
>
> My upstream prefers the raw addresses, I believe, under the rationale that
> it allows the macro definitions to be removed from arch/arm/mach-omap2.
> This reduces the total number of lines of code in that directory - and
> this is currently an overriding concern of my upstreams.
>
> So, yes the address format in your patch is fine.
Yes that should be the only place where that address is defined.
If OMAP24XX_SEC_SHA1MD5_BASE is used in multiple locations, then
it makes sense to define it in some local header.
Regards,
Tony
^ permalink raw reply
* [PATCH] i2c: at91: fix SMBus quick command
From: ludovic.desroches at atmel.com @ 2012-11-09 17:23 UTC (permalink / raw)
To: linux-arm-kernel
From: Ludovic Desroches <ludovic.desroches@atmel.com>
SMBus command was not performed. This patch fixes this issue. The timeout log
priority has been decreased to not make console dirty uselessly.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
---
Hi Wolfram,
It would be great if this patch could be included into 3.7. The driver was
claiming that it supports SMBus quick command but it was not true. Moreover,
with some IP versions, it could cause data corruption.
I tested it with i2cdetect as you suggested. EEPROMs were detected but not
other devices (lm75 and ds1337). I have exactly the same behavior by using
i2c-gpio driver so I think there is no major issue on a driver point of view.
Thanks.
Regards.
Ludovic
drivers/i2c/busses/i2c-at91.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index aa59a25..a6670eb 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -39,6 +39,7 @@
#define AT91_TWI_STOP 0x0002 /* Send a Stop Condition */
#define AT91_TWI_MSEN 0x0004 /* Master Transfer Enable */
#define AT91_TWI_SVDIS 0x0020 /* Slave Transfer Disable */
+#define AT91_TWI_QUICK 0x0040 /* SMBus quick command */
#define AT91_TWI_SWRST 0x0080 /* Software Reset */
#define AT91_TWI_MMR 0x0004 /* Master Mode Register */
@@ -212,7 +213,10 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
INIT_COMPLETION(dev->cmd_complete);
dev->transfer_status = 0;
- if (dev->msg->flags & I2C_M_RD) {
+
+ if (!dev->buf_len) {
+ at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
+ } else if (dev->msg->flags & I2C_M_RD) {
unsigned start_flags = AT91_TWI_START;
if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
@@ -235,7 +239,7 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
dev->adapter.timeout);
if (ret == 0) {
- dev_err(dev->dev, "controller timed out\n");
+ dev_dbg(dev->dev, "controller timed out\n");
at91_init_twi_bus(dev);
return -ETIMEDOUT;
}
--
1.7.11.3
^ permalink raw reply related
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