* [PATCH 03/14] ARM: SPEAr: DT: Update pinctrl list
From: Viresh Kumar @ 2012-11-11 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1352608333.git.viresh.kumar@linaro.org>
From: Vipul Kumar Samar <vipulkumar.samar@st.com>
This patch updates pinctrl configuration for SPEAr SoC's.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/spear1310-evb.dts | 23 +++++++++++++++++------
arch/arm/boot/dts/spear1340-evb.dts | 35 +++++++++++++++++++++--------------
arch/arm/boot/dts/spear320-evb.dts | 6 +-----
3 files changed, 39 insertions(+), 25 deletions(-)
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index dd4358b..08697ac 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -30,10 +30,14 @@
pinctrl-0 = <&state_default>;
state_default: pinmux {
- i2c0-pmx {
+ i2c0 {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
+ i2s0 {
+ st,pins = "i2s0_grp";
+ st,function = "i2s0";
+ };
i2s1 {
st,pins = "i2s1_grp";
st,function = "i2s1";
@@ -42,6 +46,10 @@
st,pins = "arm_gpio_grp";
st,function = "arm_gpio";
};
+ clcd {
+ st,pins = "clcd_grp" , "clcd_high_res";
+ st,function = "clcd";
+ };
eth {
st,pins = "gmii_grp";
st,function = "gmii";
@@ -74,11 +82,6 @@
st,pins = "i2c_1_2_grp";
st,function = "i2c_1_2";
};
- pci {
- st,pins = "pcie0_grp","pcie1_grp",
- "pcie2_grp";
- st,function = "pci";
- };
smii {
st,pins = "smii_0_1_2_grp";
st,function = "smii_0_1_2";
@@ -88,6 +91,14 @@
"nand_16bit_grp";
st,function = "nand";
};
+ sata {
+ st,pins = "sata0_grp";
+ st,function = "sata";
+ };
+ pcie {
+ st,pins = "pcie1_grp", "pcie2_grp";
+ st,function = "pci_express";
+ };
};
};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index c9a54e0..8e35c14 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -38,20 +38,15 @@
st,pins = "fsmc_8bit_grp";
st,function = "fsmc";
};
- kbd {
- st,pins = "keyboard_row_col_grp",
- "keyboard_col5_grp";
- st,function = "keyboard";
- };
uart0 {
- st,pins = "uart0_grp", "uart0_enh_grp";
+ st,pins = "uart0_grp";
st,function = "uart0";
};
- i2c0-pmx {
+ i2c0 {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
- i2c1-pmx {
+ i2c1 {
st,pins = "i2c1_grp";
st,function = "i2c1";
};
@@ -64,14 +59,9 @@
st,function = "spdif_out";
};
ssp0 {
- st,pins = "ssp0_grp", "ssp0_cs1_grp",
- "ssp0_cs3_grp";
+ st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp";
st,function = "ssp0";
};
- pwm {
- st,pins = "pwm2_grp", "pwm3_grp";
- st,function = "pwm";
- };
smi-pmx {
st,pins = "smi_grp";
st,function = "smi";
@@ -84,6 +74,18 @@
st,pins = "gmii_grp", "rgmii_grp";
st,function = "gmac";
};
+ cam0 {
+ st,pins = "cam0_grp";
+ st,function = "cam0";
+ };
+ cam1 {
+ st,pins = "cam1_grp";
+ st,function = "cam1";
+ };
+ cam2 {
+ st,pins = "cam2_grp";
+ st,function = "cam2";
+ };
cam3 {
st,pins = "cam3_grp";
st,function = "cam3";
@@ -108,6 +110,11 @@
st,pins = "sata_grp";
st,function = "sata";
};
+ pcie {
+ st,pins = "pcie_grp";
+ st,function = "pcie";
+ };
+
};
};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index 082328b..3f87cd0 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -76,13 +76,9 @@
st,function = "mii2";
};
pwm0_1 {
- st,pins = "pwm0_1_pin_14_15_grp";
+ st,pins = "pwm0_1_pin_37_38_grp";
st,function = "pwm0_1";
};
- pwm2 {
- st,pins = "pwm2_pin_13_grp";
- st,function = "pwm2";
- };
};
};
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH 04/14] ARM: SPEAr: DT: Update partition info for MTD devices
From: Viresh Kumar @ 2012-11-11 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1352608333.git.viresh.kumar@linaro.org>
From: Vipin Kumar <vipin.kumar@st.com>
This patch enhances partition information of MTD devices like fsmc-nand and
spear-smi.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/spear1310-evb.dts | 43 ++++++++++++++++++++++++++++++++-----
arch/arm/boot/dts/spear1340-evb.dts | 43 ++++++++++++++++++++++++++++++++-----
arch/arm/boot/dts/spear300-evb.dts | 18 +++++++++++-----
arch/arm/boot/dts/spear310-evb.dts | 18 +++++++++++-----
arch/arm/boot/dts/spear320-evb.dts | 18 +++++++++++-----
arch/arm/boot/dts/spear600-evb.dts | 18 +++++++++++-----
6 files changed, 128 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index 08697ac..2e2887b 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -120,6 +120,31 @@
fsmc: flash at b0000000 {
status = "okay";
+
+ partition at 0 {
+ label = "xloader";
+ reg = <0x0 0x80000>;
+ };
+ partition at 80000 {
+ label = "u-boot";
+ reg = <0x80000 0x140000>;
+ };
+ partition at 1C0000 {
+ label = "environment";
+ reg = <0x1C0000 0x40000>;
+ };
+ partition at 200000 {
+ label = "dtb";
+ reg = <0x200000 0x40000>;
+ };
+ partition at 240000 {
+ label = "linux";
+ reg = <0x240000 0xC00000>;
+ };
+ partition at E40000 {
+ label = "rootfs";
+ reg = <0xE40000 0x0>;
+ };
};
gmac0: eth at e2000000 {
@@ -146,15 +171,23 @@
};
partition at 10000 {
label = "u-boot";
- reg = <0x10000 0x40000>;
+ reg = <0x10000 0x50000>;
+ };
+ partition at 60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
+ };
+ partition at 70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
};
- partition at 50000 {
+ partition at 80000 {
label = "linux";
- reg = <0x50000 0x2c0000>;
+ reg = <0x80000 0x310000>;
};
- partition at 310000 {
+ partition at 390000 {
label = "rootfs";
- reg = <0x310000 0x4f0000>;
+ reg = <0x390000 0x0>;
};
};
};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index 8e35c14..8d6339d 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -128,6 +128,31 @@
fsmc: flash at b0000000 {
status = "okay";
+
+ partition at 0 {
+ label = "xloader";
+ reg = <0x0 0x200000>;
+ };
+ partition at 200000 {
+ label = "u-boot";
+ reg = <0x200000 0x200000>;
+ };
+ partition at 400000 {
+ label = "environment";
+ reg = <0x400000 0x100000>;
+ };
+ partition at 500000 {
+ label = "dtb";
+ reg = <0x500000 0x100000>;
+ };
+ partition at 600000 {
+ label = "linux";
+ reg = <0x600000 0xC00000>;
+ };
+ partition at 1200000 {
+ label = "rootfs";
+ reg = <0x1200000 0x0>;
+ };
};
gmac0: eth at e2000000 {
@@ -154,15 +179,23 @@
};
partition at 10000 {
label = "u-boot";
- reg = <0x10000 0x40000>;
+ reg = <0x10000 0x50000>;
+ };
+ partition at 60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
+ };
+ partition at 70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
};
- partition at 50000 {
+ partition at 80000 {
label = "linux";
- reg = <0x50000 0x2c0000>;
+ reg = <0x80000 0x310000>;
};
- partition at 310000 {
+ partition at 390000 {
label = "rootfs";
- reg = <0x310000 0x4f0000>;
+ reg = <0x390000 0x0>;
};
};
};
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index 1e7c7a8..b3265f6 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -100,15 +100,23 @@
};
partition at 10000 {
label = "u-boot";
- reg = <0x10000 0x40000>;
+ reg = <0x10000 0x50000>;
};
- partition at 50000 {
+ partition at 60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
+ };
+ partition at 70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
+ };
+ partition at 80000 {
label = "linux";
- reg = <0x50000 0x2c0000>;
+ reg = <0x80000 0x310000>;
};
- partition at 310000 {
+ partition at 390000 {
label = "rootfs";
- reg = <0x310000 0x4f0000>;
+ reg = <0x390000 0x0>;
};
};
};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index b00544e..b30fa0e 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -114,15 +114,23 @@
};
partition at 10000 {
label = "u-boot";
- reg = <0x10000 0x40000>;
+ reg = <0x10000 0x50000>;
};
- partition at 50000 {
+ partition at 60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
+ };
+ partition at 70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
+ };
+ partition at 80000 {
label = "linux";
- reg = <0x50000 0x2c0000>;
+ reg = <0x80000 0x310000>;
};
- partition at 310000 {
+ partition at 390000 {
label = "rootfs";
- reg = <0x310000 0x4f0000>;
+ reg = <0x390000 0x0>;
};
};
};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index 3f87cd0..a3061ad 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -118,15 +118,23 @@
};
partition at 10000 {
label = "u-boot";
- reg = <0x10000 0x40000>;
+ reg = <0x10000 0x50000>;
};
- partition at 50000 {
+ partition at 60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
+ };
+ partition at 70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
+ };
+ partition at 80000 {
label = "linux";
- reg = <0x50000 0x2c0000>;
+ reg = <0x80000 0x310000>;
};
- partition at 310000 {
+ partition at 390000 {
label = "rootfs";
- reg = <0x310000 0x4f0000>;
+ reg = <0x390000 0x0>;
};
};
};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 1119c22..16e4de4 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -49,15 +49,23 @@
};
partition at 10000 {
label = "u-boot";
- reg = <0x10000 0x40000>;
+ reg = <0x10000 0x50000>;
};
- partition at 50000 {
+ partition at 60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
+ };
+ partition at 70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
+ };
+ partition at 80000 {
label = "linux";
- reg = <0x50000 0x2c0000>;
+ reg = <0x80000 0x310000>;
};
- partition at 310000 {
+ partition at 390000 {
label = "rootfs";
- reg = <0x310000 0x4f0000>;
+ reg = <0x390000 0x0>;
};
};
};
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH 05/14] ARM: SPEAr: DT: Fix existing DT support
From: Viresh Kumar @ 2012-11-11 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1352608333.git.viresh.kumar@linaro.org>
From: Vipul Kumar Samar <vipulkumar.samar@st.com>
This patch fixes existing DT support for all SPEAr SoC's. This includes:
- Removing few nodes from board files
- Updating DT data of few nodes
- Updating ranges of few busses
- Moving devices to correct parent bus
Signed-off-by: Bhavna Yadav <bhavna.yadav@st.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/spear1310-evb.dts | 13 +++++--------
arch/arm/boot/dts/spear1310.dtsi | 14 +++++++-------
arch/arm/boot/dts/spear1340-evb.dts | 9 +++++----
arch/arm/boot/dts/spear1340.dtsi | 1 +
arch/arm/boot/dts/spear13xx.dtsi | 33 ++++++++++++++++++++++-----------
arch/arm/boot/dts/spear300.dtsi | 2 +-
arch/arm/boot/dts/spear320-evb.dts | 5 +----
arch/arm/boot/dts/spear320.dtsi | 4 ++--
arch/arm/boot/dts/spear3xx.dtsi | 2 +-
9 files changed, 45 insertions(+), 38 deletions(-)
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index 2e2887b..79a1654 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -192,10 +192,6 @@
};
};
- spi0: spi at e0100000 {
- status = "okay";
- };
-
ehci at e4800000 {
status = "okay";
};
@@ -229,10 +225,6 @@
status = "okay";
};
- i2c1: i2c at 5cd00000 {
- status = "okay";
- };
-
kbd at e0300000 {
linux,keymap = < 0x00000001
0x00010002
@@ -317,6 +309,7 @@
0x08080052 >;
autorepeat;
st,mode = <0>;
+ suspended_rate = <2000000>;
status = "okay";
};
@@ -328,6 +321,10 @@
status = "okay";
};
+ spi0: spi at e0100000 {
+ status = "okay";
+ };
+
wdt at ec800620 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index d5661ee..1e18f31 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -82,13 +82,6 @@
status = "disabled";
};
- spi1: spi at 5d400000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x5d400000 0x1000>;
- interrupts = <0 99 0x4>;
- status = "disabled";
- };
-
apb {
i2c1: i2c at 5cd00000 {
#address-cells = <1>;
@@ -153,6 +146,13 @@
status = "disabled";
};
+ spi1: spi at 5d400000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x5d400000 0x1000>;
+ interrupts = <0 99 0x4>;
+ status = "disabled";
+ };
+
serial at 5c800000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5c800000 0x1000>;
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index 8d6339d..4c5fa85 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -200,10 +200,6 @@
};
};
- spi0: spi at e0100000 {
- status = "okay";
- };
-
ehci at e4800000 {
status = "okay";
};
@@ -325,6 +321,7 @@
0x08080052 >;
autorepeat;
st,mode = <0>;
+ suspended_rate = <2000000>;
status = "okay";
};
@@ -340,6 +337,10 @@
status = "okay";
};
+ spi0: spi at e0100000 {
+ status = "okay";
+ };
+
wdt at ec800620 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 1604425..1446f1b 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -52,6 +52,7 @@
compatible = "snps,designware-i2c";
reg = <0xb4000000 0x1000>;
interrupts = <0 104 0x4>;
+ write-16bit;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index f7b84ac..4d35144 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -70,6 +70,8 @@
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
0xb0000000 0xb0000000 0x10000000
+ 0xd0000000 0xd0000000 0x02000000
+ 0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
sdhci at b3000000 {
@@ -81,7 +83,7 @@
cf at b2800000 {
compatible = "arasan,cf-spear1340";
- reg = <0xb2800000 0x100>;
+ reg = <0xb2800000 0x1000>;
interrupts = <0 29 0x4>;
status = "disabled";
};
@@ -113,6 +115,7 @@
0 23 0x4>;
st,ale-off = <0x20000>;
st,cle-off = <0x10000>;
+ st,mode = <2>;
status = "disabled";
};
@@ -134,17 +137,11 @@
status = "disabled";
};
- spi0: spi at e0100000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0xe0100000 0x1000>;
- interrupts = <0 31 0x4>;
- status = "disabled";
- };
-
ehci at e4800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe4800000 0x1000>;
interrupts = <0 64 0x4>;
+ usbh0_id = <0>;
status = "disabled";
};
@@ -152,6 +149,7 @@
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe5800000 0x1000>;
interrupts = <0 66 0x4>;
+ usbh1_id = <1>;
status = "disabled";
};
@@ -159,6 +157,7 @@
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe4000000 0x1000>;
interrupts = <0 65 0x4>;
+ usbh0_id = <0>;
status = "disabled";
};
@@ -166,6 +165,7 @@
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe5000000 0x1000>;
interrupts = <0 67 0x4>;
+ usbh1_id = <1>;
status = "disabled";
};
@@ -175,6 +175,8 @@
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
0xb0000000 0xb0000000 0x10000000
+ 0xd0000000 0xd0000000 0x02000000
+ 0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
gpio0: gpio at e0600000 {
@@ -215,8 +217,15 @@
status = "disabled";
};
+ spi0: spi at e0100000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0xe0100000 0x1000>;
+ interrupts = <0 31 0x4>;
+ status = "disabled";
+ };
+
rtc at e0580000 {
- compatible = "st,spear-rtc";
+ compatible = "st,spear600-rtc";
reg = <0xe0580000 0x1000>;
interrupts = <0 36 0x4>;
status = "disabled";
@@ -232,7 +241,7 @@
adc at e0080000 {
compatible = "st,spear600-adc";
reg = <0xe0080000 0x1000>;
- interrupts = <0 44 0x4>;
+ interrupts = <0 12 0x4>;
status = "disabled";
};
@@ -245,7 +254,8 @@
timer at ec800600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xec800600 0x20>;
- interrupts = <1 13 0x301>;
+ interrupts = <1 13 0x4>;
+ status = "disabled";
};
wdt at ec800620 {
@@ -257,6 +267,7 @@
thermal at e07008c4 {
compatible = "st,thermal-spear1340";
reg = <0xe07008c4 0x4>;
+ thermal_flags = <0x7000>;
};
};
};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
index ed3627c..fdac871 100644
--- a/arch/arm/boot/dts/spear300.dtsi
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -27,7 +27,7 @@
};
clcd at 60000000 {
- compatible = "arm,clcd-pl110", "arm,primecell";
+ compatible = "arm,pl110", "arm,primecell";
reg = <0x60000000 0x1000>;
interrupts = <30>;
status = "disabled";
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index a3061ad..d62ee20 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -82,10 +82,6 @@
};
};
- clcd at 90000000 {
- status = "okay";
- };
-
dma at fc400000 {
status = "okay";
};
@@ -99,6 +95,7 @@
};
sdhci at 70000000 {
+ power-gpio = <&gpiopinctrl 61 1>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 1f49d69..02113f3 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -27,7 +27,7 @@
};
clcd at 90000000 {
- compatible = "arm,clcd-pl110", "arm,primecell";
+ compatible = "arm,pl110", "arm,primecell";
reg = <0x90000000 0x1000>;
interrupts = <33>;
status = "disabled";
@@ -68,7 +68,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- ranges = <0xa0000000 0xa0000000 0x10000000
+ ranges = <0xa0000000 0xa0000000 0x20000000
0xd0000000 0xd0000000 0x30000000>;
i2c1: i2c at a7000000 {
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index 3a8bb57..b02721f 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -120,7 +120,7 @@
};
rtc at fc900000 {
- compatible = "st,spear-rtc";
+ compatible = "st,spear600-rtc";
reg = <0xfc900000 0x1000>;
interrupts = <10>;
status = "disabled";
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH 06/14] ARM: SPEAr: DT: Modify DT bindings for STMMAC
From: Viresh Kumar @ 2012-11-11 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1352608333.git.viresh.kumar@linaro.org>
From: Deepak Sikri <deepak.sikri@st.com>
This patch modifies the DT bindings for the GMAC IP existings for the
SPEAr family. The DT bindings now additionally pass the phy mode as a
configuration parameter for the ethernet device.
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/spear1310-evb.dts | 1 +
arch/arm/boot/dts/spear1310.dtsi | 4 ++++
arch/arm/boot/dts/spear1340-evb.dts | 1 +
arch/arm/boot/dts/spear3xx.dtsi | 1 +
arch/arm/boot/dts/spear600.dtsi | 1 +
5 files changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index 79a1654..a4ff5cb 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -148,6 +148,7 @@
};
gmac0: eth at e2000000 {
+ phy-mode = "gmii";
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 1e18f31..bd6b64b 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -55,6 +55,7 @@
reg = <0x5c400000 0x8000>;
interrupts = <0 95 0x4>;
interrupt-names = "macirq";
+ phy-mode = "mii";
status = "disabled";
};
@@ -63,6 +64,7 @@
reg = <0x5c500000 0x8000>;
interrupts = <0 96 0x4>;
interrupt-names = "macirq";
+ phy-mode = "mii";
status = "disabled";
};
@@ -71,6 +73,7 @@
reg = <0x5c600000 0x8000>;
interrupts = <0 97 0x4>;
interrupt-names = "macirq";
+ phy-mode = "rmii";
status = "disabled";
};
@@ -79,6 +82,7 @@
reg = <0x5c700000 0x8000>;
interrupts = <0 98 0x4>;
interrupt-names = "macirq";
+ phy-mode = "rgmii";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index 4c5fa85..63c352f 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -156,6 +156,7 @@
};
gmac0: eth at e2000000 {
+ phy-mode = "rgmii";
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index b02721f..4946360 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -53,6 +53,7 @@
reg = <0xe0800000 0x8000>;
interrupts = <23 22>;
interrupt-names = "macirq", "eth_wake_irq";
+ phy-mode = "mii";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index a3c36e4..f74feea 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -59,6 +59,7 @@
interrupt-parent = <&vic1>;
interrupts = <24 23>;
interrupt-names = "macirq", "eth_wake_irq";
+ phy-mode = "gmii";
status = "disabled";
};
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH 07/14] ARM: SPEAr: DT: add uart state to fix warning
From: Viresh Kumar @ 2012-11-11 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1352608333.git.viresh.kumar@linaro.org>
From: Vipul Kumar Samar <vipulkumar.samar@st.com>
amba-pl011 driver supports two pin state "default" and "sleep" and it
expect from dt to provide this pinctrl states and phandler otherwise it
gives a warning message.
To remove this warning message pass default state with null phandler to uart
pins in device node (In our case all the pins are configured in default states
so we pass null phandler to pins).
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/spear1310-evb.dts | 2 ++
arch/arm/boot/dts/spear1340-evb.dts | 4 ++++
arch/arm/boot/dts/spear300-evb.dts | 2 ++
arch/arm/boot/dts/spear310-evb.dts | 12 ++++++++++++
arch/arm/boot/dts/spear320-evb.dts | 6 ++++++
arch/arm/boot/dts/spear600-evb.dts | 4 ++++
6 files changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index a4ff5cb..c60c3f8 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -320,6 +320,8 @@
serial at e0000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
spi0: spi at e0100000 {
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index 63c352f..c6051dd 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -332,10 +332,14 @@
serial at e0000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial at b4100000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
spi0: spi at e0100000 {
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index b3265f6..5de1431 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -243,6 +243,8 @@
serial at d0000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
wdt at fc880000 {
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index b30fa0e..b096329 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -166,26 +166,38 @@
serial at d0000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial at b2000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial at b2080000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial at b2100000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial at b2180000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial at b2200000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
wdt at fc880000 {
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index d62ee20..02f06c5 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -179,14 +179,20 @@
serial at d0000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial at a3000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial at a4000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
wdt at fc880000 {
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 16e4de4..5e6ef03 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -73,10 +73,14 @@
apb {
serial at d0000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial at d0080000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
i2c at d0200000 {
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH 08/14] ARM: SPEAr: DT: Update device nodes
From: Viresh Kumar @ 2012-11-11 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1352608333.git.viresh.kumar@linaro.org>
From: Shiraz Hashim <shiraz.hashim@st.com>
This patch adds multiple device nodes for SPEAr machines and boards.
Signed-off-by: Bhavna Yadav <bhavna.yadav@st.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/spear1310-evb.dts | 89 +++++++++++++++++++
arch/arm/boot/dts/spear1310.dtsi | 2 +
arch/arm/boot/dts/spear1340-evb.dts | 172 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/spear1340.dtsi | 46 ++++++++++
arch/arm/boot/dts/spear13xx.dtsi | 39 ++++++++
arch/arm/boot/dts/spear320.dtsi | 11 +++
arch/arm/boot/dts/spear3xx.dtsi | 2 +
arch/arm/boot/dts/spear600-evb.dts | 24 +++++
arch/arm/boot/dts/spear600.dtsi | 15 ++++
9 files changed, 400 insertions(+)
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index c60c3f8..56ea6d5 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -147,6 +147,20 @@
};
};
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button at 1 {
+ label = "wakeup";
+ linux,code = <0x100>;
+ gpios = <&gpio0 7 0x4>;
+ debounce-interval = <20>;
+ gpio-key,wakeup = <1>;
+ };
+ };
+
gmac0: eth at e2000000 {
phy-mode = "gmii";
status = "okay";
@@ -326,6 +340,81 @@
spi0: spi at e0100000 {
status = "okay";
+ num-cs = <3>;
+ cs-gpios = <&gpio1 7 0>, <&spics 0>, <&spics 1>;
+
+ stmpe610 at 0 {
+ status = "okay";
+ compatible = "st,stmpe610";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpha;
+ pl022,hierarchy = <0>;
+ pl022,interface = <0>;
+ pl022,slave-tx-disable;
+ pl022,com-mode = <0>;
+ pl022,rx-level-trig = <0>;
+ pl022,tx-level-trig = <0>;
+ pl022,ctrl-len = <0x7>;
+ pl022,wait-state = <0>;
+ pl022,duplex = <0>;
+ id = <0>;
+ blocks = <4>;
+ irq_over_gpio;
+ irq-gpios = <&gpio1 6 0x4>;
+ irq-trigger = <0x2>;
+
+ stmpe610-ts {
+ compatible = "stmpe,ts";
+ reg = <0>;
+ ts,sample-time = <4>;
+ ts,mod-12b = <1>;
+ ts,ref-sel = <0>;
+ ts,adc-freq = <1>;
+ ts,ave-ctrl = <1>;
+ ts,touch-det-delay = <2>;
+ ts,settling = <2>;
+ ts,fraction-z = <7>;
+ ts,i-drive = <1>;
+ };
+ };
+
+ m25p80 at 1 {
+ status = "okay";
+ compatible = "st,m25p80";
+ reg = <1>;
+ spi-max-frequency = <12000000>;
+ spi-cpol;
+ spi-cpha;
+ pl022,hierarchy = <0>;
+ pl022,interface = <0>;
+ pl022,slave-tx-disable;
+ pl022,com-mode = <0x2>;
+ pl022,rx-level-trig = <0>;
+ pl022,tx-level-trig = <0>;
+ pl022,ctrl-len = <0x11>;
+ pl022,wait-state = <0>;
+ pl022,duplex = <0>;
+ };
+
+ spidev at 2 {
+ status = "okay";
+ compatible = "spidev";
+ reg = <2>;
+ spi-max-frequency = <25000000>;
+ spi-cpha;
+ pl022,hierarchy = <0>;
+ pl022,interface = <0>;
+ pl022,slave-tx-disable;
+ pl022,com-mode = <0x2>;
+ pl022,rx-level-trig = <0>;
+ pl022,tx-level-trig = <0>;
+ pl022,ctrl-len = <0x11>;
+ pl022,wait-state = <0>;
+ pl022,duplex = <0>;
+ };
};
wdt at ec800620 {
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index bd6b64b..8fb22b9 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -154,6 +154,8 @@
compatible = "arm,pl022", "arm,primecell";
reg = <0x5d400000 0x1000>;
interrupts = <0 99 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index c6051dd..c0a3677 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -118,6 +118,10 @@
};
};
+ ahci at b1000000 {
+ status = "okay";
+ };
+
dma at ea800000 {
status = "okay";
};
@@ -205,10 +209,37 @@
status = "okay";
};
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button at 1 {
+ label = "wakeup";
+ linux,code = <0x100>;
+ gpios = <&gpio1 1 0x4>;
+ debounce-interval = <20>;
+ gpio-key,wakeup = <1>;
+ };
+ };
+
ehci at e5800000 {
status = "okay";
};
+ i2s0: i2s-play at b2400000 {
+ status = "okay";
+ };
+
+ i2s1: i2s-rec at b2000000 {
+ status = "okay";
+ };
+
+ incodec: dir-hifi {
+ compatible = "dummy,dir-hifi";
+ status = "okay";
+ };
+
ohci at e4000000 {
status = "okay";
};
@@ -217,11 +248,43 @@
status = "okay";
};
+ outcodec: dit-hifi {
+ compatible = "dummy,dit-hifi";
+ status = "okay";
+ };
+
+ sound {
+ compatible = "spear,spear-evb";
+ audio-controllers = <&spdif0 &spdif1 &i2s0 &i2s1>;
+ audio-codecs = <&incodec &outcodec &sta529 &sta529>;
+ codec_dai_name = "dir-hifi", "dit-hifi", "sta529-audio", "sta529-audio";
+ stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap";
+ dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm";
+ nr_controllers = <4>;
+ status = "okay";
+ };
+
+ spdif0: spdif-in at d0100000 {
+ status = "okay";
+ };
+
+ spdif1: spdif-out at d0000000 {
+ status = "okay";
+ };
+
apb {
adc at e0080000 {
status = "okay";
};
+ i2s-play at b2400000 {
+ status = "okay";
+ };
+
+ i2s-rec at b2000000 {
+ status = "okay";
+ };
+
gpio0: gpio at e0600000 {
status = "okay";
};
@@ -232,10 +295,39 @@
i2c0: i2c at e0280000 {
status = "okay";
+
+ sta529: sta529 at 1a {
+ compatible = "st,sta529";
+ reg = <0x1a>;
+ };
};
i2c1: i2c at b4000000 {
status = "okay";
+
+ eeprom0 at 56 {
+ compatible = "st,eeprom";
+ reg = <0x56>;
+ };
+
+ stmpe801 at 41 {
+ compatible = "st,stmpe801";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x41>;
+ irq-over-gpio;
+ irq-gpios = <&gpio0 4 0x4>;
+ id = <0>;
+ blocks = <1>;
+ irq-trigger = <0x2>;
+
+ stmpegpio: stmpe-gpio {
+ compatible = "stmpe,gpio";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
};
kbd at e0300000 {
@@ -344,6 +436,86 @@
spi0: spi at e0100000 {
status = "okay";
+ num-cs = <3>;
+ cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>,
+ <&gpiopinctrl 85 0>;
+
+ m25p80 at 0 {
+ status = "okay";
+ compatible = "m25p80";
+ reg = <0>;
+ spi-max-frequency = <12000000>;
+ spi-cpol;
+ spi-cpha;
+ pl022,hierarchy = <0>;
+ pl022,interface = <0>;
+ pl022,slave-tx-disable;
+ pl022,com-mode = <0x2>;
+ pl022,rx-level-trig = <0>;
+ pl022,tx-level-trig = <0>;
+ pl022,ctrl-len = <0x11>;
+ pl022,wait-state = <0>;
+ pl022,duplex = <0>;
+ };
+
+ stmpe610 at 1 {
+ status = "okay";
+ compatible = "st,stmpe610";
+ spi-max-frequency = <1000000>;
+ spi-cpha;
+ reg = <1>;
+ pl022,hierarchy = <0>;
+ pl022,interface = <0>;
+ pl022,slave-tx-disable;
+ pl022,com-mode = <0>;
+ pl022,rx-level-trig = <0>;
+ pl022,tx-level-trig = <0>;
+ pl022,ctrl-len = <0x7>;
+ pl022,wait-state = <0>;
+ pl022,duplex = <0>;
+ irq-over-gpio;
+ irq-gpios = <&gpiopinctrl 100 0>;
+ id = <0>;
+ blocks = <4>;
+ irq-trigger = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ stmpe610-ts {
+ compatible = "stmpe,ts";
+ reg = <0>;
+ ts,sample-time = <4>;
+ ts,mod-12b = <1>;
+ ts,ref-sel = <0>;
+ ts,adc-freq = <1>;
+ ts,ave-ctrl = <1>;
+ ts,touch-det-delay = <2>;
+ ts,settling = <2>;
+ ts,fraction-z = <7>;
+ ts,i-drive = <1>;
+ };
+ };
+
+ spidev at 2 {
+ status = "okay";
+ compatible = "spidev";
+ reg = <2>;
+ spi-max-frequency = <25000000>;
+ spi-cpha;
+ pl022,hierarchy = <0>;
+ pl022,interface = <0>;
+ pl022,slave-tx-disable;
+ pl022,com-mode = <0x2>;
+ pl022,rx-level-trig = <0>;
+ pl022,tx-level-trig = <0>;
+ pl022,ctrl-len = <0x11>;
+ pl022,wait-state = <0>;
+ pl022,duplex = <0>;
+ };
+ };
+
+ timer at ec800600 {
+ status = "okay";
};
wdt at ec800620 {
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 1446f1b..0d3eb4f 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -38,9 +38,55 @@
status = "disabled";
};
+ i2s-play at b2400000 {
+ compatible = "snps,designware-i2s";
+ reg = <0xb2400000 0x10000>;
+ interrupt-names = "play_irq";
+ interrupts = <0 98 0x4
+ 0 99 0x4>;
+ play;
+ channel = <8>;
+ status = "disabled";
+ };
+
+ i2s-rec at b2000000 {
+ compatible = "snps,designware-i2s";
+ reg = <0xb2000000 0x10000>;
+ interrupt-names = "record_irq";
+ interrupts = <0 100 0x4
+ 0 101 0x4>;
+ record;
+ channel = <8>;
+ status = "disabled";
+ };
+
+ pwm: pwm at e0180000 {
+ compatible ="st,spear13xx-pwm";
+ reg = <0xe0180000 0x1000>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ spdif-in at d0100000 {
+ compatible = "st,spdif-in";
+ reg = < 0xd0100000 0x20000
+ 0xd0110000 0x10000 >;
+ interrupts = <0 84 0x4>;
+ status = "disabled";
+ };
+
+ spdif-out at d0000000 {
+ compatible = "st,spdif-out";
+ reg = <0xd0000000 0x20000>;
+ interrupts = <0 85 0x4>;
+ status = "disabled";
+ };
+
spi1: spi at 5d400000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x5d400000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 99 0x4>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4d35144..2e650f9 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -64,6 +64,18 @@
bootargs = "console=ttyAMA0,115200";
};
+ cpufreq {
+ compatible = "st,cpufreq";
+ cpufreq_tbl = < 166000
+ 200000
+ 250000
+ 300000
+ 400000
+ 500000
+ 600000 >;
+ status = "disable";
+ };
+
ahb {
#address-cells = <1>;
#size-cells = <1>;
@@ -128,6 +140,13 @@
status = "disabled";
};
+ pcm {
+ compatible = "st,pcm-audio";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ status = "disable";
+ };
+
smi: flash at ea000000 {
compatible = "st,spear600-smi";
#address-cells = <1>;
@@ -217,9 +236,29 @@
status = "disabled";
};
+ i2s at e0180000 {
+ compatible = "st,designware-i2s";
+ reg = <0xe0180000 0x1000>;
+ interrupt-names = "play_irq", "record_irq";
+ interrupts = <0 10 0x4
+ 0 11 0x4 >;
+ status = "disabled";
+ };
+
+ i2s at e0200000 {
+ compatible = "st,designware-i2s";
+ reg = <0xe0200000 0x1000>;
+ interrupt-names = "play_irq", "record_irq";
+ interrupts = <0 26 0x4
+ 0 53 0x4>;
+ status = "disabled";
+ };
+
spi0: spi at e0100000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xe0100000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 31 0x4>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 02113f3..582ded7 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -55,15 +55,26 @@
spi1: spi at a5000000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xa5000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
spi2: spi at a6000000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xa6000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
+ pwm: pwm at a8000000 {
+ compatible ="st,spear-pwm";
+ reg = <0xa8000000 0x1000>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
apb {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index 4946360..c2a852d 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -70,6 +70,8 @@
compatible = "arm,pl022", "arm,primecell";
reg = <0xd0100000 0x1000>;
interrupts = <20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 5e6ef03..d865a89 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,15 +24,35 @@
};
ahb {
+ clcd at fc200000 {
+ status = "okay";
+ };
+
dma at fc400000 {
status = "okay";
};
+ ehci at e1800000 {
+ status = "okay";
+ };
+
+ ehci at e2000000 {
+ status = "okay";
+ };
+
gmac: ethernet at e0800000 {
phy-mode = "gmii";
status = "okay";
};
+ ohci at e1900000 {
+ status = "okay";
+ };
+
+ ohci at e2100000 {
+ status = "okay";
+ };
+
smi: flash at fc000000 {
status = "okay";
clock-rate=<50000000>;
@@ -83,6 +103,10 @@
pinctrl-0 = <>;
};
+ rtc at fc900000 {
+ status = "okay";
+ };
+
i2c at d0200000 {
clock-frequency = <400000>;
status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index f74feea..e051dde 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
#interrupt-cells = <1>;
};
+ clcd at fc200000 {
+ compatible = "arm,pl110", "arm,primecell";
+ reg = <0xfc200000 0x1000>;
+ interrupt-parent = <&vic1>;
+ interrupts = <12>;
+ status = "disabled";
+ };
+
dma at fc400000 {
compatible = "arm,pl080", "arm,primecell";
reg = <0xfc400000 0x1000>;
@@ -179,6 +187,13 @@
status = "disabled";
};
+ rtc at fc900000 {
+ compatible = "st,spear600-rtc";
+ reg = <0xfc900000 0x1000>;
+ interrupts = <10>;
+ status = "disabled";
+ };
+
timer at f0000000 {
compatible = "st,spear-timer";
reg = <0xf0000000 0x400>;
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH 09/14] ARM: SPEAr1310: Move 1310 specific misc register into machine specific files
From: Viresh Kumar @ 2012-11-11 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1352608333.git.viresh.kumar@linaro.org>
From: Vipul Kumar Samar <vipulkumar.samar@st.com>
This patch moves some global macro definitions to the files where they are used.
Its a step towards removing spear.h completely later on.
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/mach-spear13xx/include/mach/spear.h | 8 --------
arch/arm/mach-spear13xx/spear1310.c | 5 +++++
drivers/clk/spear/spear1310_clock.c | 1 +
3 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 07d90ac..7cfa681 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -47,14 +47,6 @@
#define DMAC1_BASE UL(0xEB000000)
#define MCIF_CF_BASE UL(0xB2800000)
-/* Devices present in SPEAr1310 */
-#ifdef CONFIG_MACH_SPEAR1310
-#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
-#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
-#define SPEAR1310_RAS_BASE UL(0xD8400000)
-#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
-#endif /* CONFIG_MACH_SPEAR1310 */
-
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE UART_BASE
#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 9fbbfc5..593a756 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -27,6 +27,11 @@
#define SPEAR1310_SATA1_BASE UL(0xB1800000)
#define SPEAR1310_SATA2_BASE UL(0xB4000000)
+#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
+#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
+#define SPEAR1310_RAS_BASE UL(0xD8400000)
+#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
+
/* ssp device registration */
static struct pl022_ssp_controller ssp1_plat_data = {
.bus_id = 0,
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 0fcec2a..cf7e176 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -20,6 +20,7 @@
#include <mach/spear.h>
#include "clk.h"
+#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
/* PLL related registers and bit values */
#define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210)
/* PLL_CFG bit values */
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH 10/14] ARM: SPEAr13xx: Remove fields not required for ssp controller
From: Viresh Kumar @ 2012-11-11 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1352608333.git.viresh.kumar@linaro.org>
From: Shiraz Hashim <shiraz.hashim@st.com>
Few fields are not required to be programmed in platform data of spi controller
now, as it comes via DT. Remove them.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/mach-spear13xx/spear1310.c | 2 --
arch/arm/mach-spear13xx/spear13xx.c | 2 --
2 files changed, 4 deletions(-)
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 593a756..451f3b1 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -34,9 +34,7 @@
/* ssp device registration */
static struct pl022_ssp_controller ssp1_plat_data = {
- .bus_id = 0,
.enable_dma = 0,
- .num_chipselect = 3,
};
/* Add SPEAr1310 auxdata to pass platform data */
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 5633d69..c4af775 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -57,12 +57,10 @@ static struct dw_dma_slave ssp_dma_param[] = {
};
struct pl022_ssp_controller pl022_plat_data = {
- .bus_id = 0,
.enable_dma = 1,
.dma_filter = dw_dma_filter,
.dma_rx_param = &ssp_dma_param[1],
.dma_tx_param = &ssp_dma_param[0],
- .num_chipselect = 3,
};
/* CF device registration */
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH 11/14] ARM: SPEAr1310: Fix AUXDATA for compact flash controller
From: Viresh Kumar @ 2012-11-11 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1352608333.git.viresh.kumar@linaro.org>
From: Vipul Kumar Samar <vipulkumar.samar@st.com>
This patch fixes the platform data for compact flash controller.
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/mach-spear13xx/spear1310.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 451f3b1..02f4724 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -15,6 +15,7 @@
#include <linux/amba/pl022.h>
#include <linux/of_platform.h>
+#include <linux/pata_arasan_cf_data.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -32,6 +33,12 @@
#define SPEAR1310_RAS_BASE UL(0xD8400000)
#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
+static struct arasan_cf_pdata cf_pdata = {
+ .cf_if_clk = CF_IF_CLK_166M,
+ .quirk = CF_BROKEN_UDMA,
+ .dma_priv = &cf_dma_priv,
+};
+
/* ssp device registration */
static struct pl022_ssp_controller ssp1_plat_data = {
.enable_dma = 0,
@@ -39,7 +46,7 @@ static struct pl022_ssp_controller ssp1_plat_data = {
/* Add SPEAr1310 auxdata to pass platform data */
static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
- OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
+ OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata),
OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH 12/14] ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT
From: Viresh Kumar @ 2012-11-11 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1352608333.git.viresh.kumar@linaro.org>
From: Shiraz Hashim <shiraz.hashim@st.com>
SPEAr3xx architecture includes shared/multiplexed irqs for certain set
of devices. The multiplexor provides a single interrupt to parent
interrupt controller (VIC) on behalf of a group of devices.
There can be multiple groups available on SPEAr3xx variants but not
exceeding 4. The number of devices in a group can differ, further they
may share same set of status/mask registers spanning across different
bit masks. Also in some cases the group may not have enable or other
registers. This makes software little complex.
Present implementation was non-DT and had few complex data structures to
decipher banks, number of irqs supported, mask and registers involved.
This patch simplifies the overall design and convert it in to DT. It
also removes all registration from individual SoC files and bring them
in to common shirq.c.
Also updated the corresponding documentation for DT binding of shirq.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
.../devicetree/bindings/arm/spear/shirq.txt | 48 ++++
arch/arm/mach-spear3xx/include/mach/irqs.h | 10 +-
arch/arm/mach-spear3xx/spear300.c | 103 -------
arch/arm/mach-spear3xx/spear310.c | 202 --------------
arch/arm/mach-spear3xx/spear320.c | 204 --------------
arch/arm/mach-spear3xx/spear3xx.c | 4 +
arch/arm/plat-spear/include/plat/shirq.h | 35 +--
arch/arm/plat-spear/shirq.c | 305 +++++++++++++++++----
8 files changed, 320 insertions(+), 591 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/spear/shirq.txt
diff --git a/Documentation/devicetree/bindings/arm/spear/shirq.txt b/Documentation/devicetree/bindings/arm/spear/shirq.txt
new file mode 100644
index 0000000..13fbb88
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear/shirq.txt
@@ -0,0 +1,48 @@
+* SPEAr Shared IRQ layer (shirq)
+
+SPEAr3xx architecture includes shared/multiplexed irqs for certain set
+of devices. The multiplexor provides a single interrupt to parent
+interrupt controller (VIC) on behalf of a group of devices.
+
+There can be multiple groups available on SPEAr3xx variants but not
+exceeding 4. The number of devices in a group can differ, further they
+may share same set of status/mask registers spanning across different
+bit masks. Also in some cases the group may not have enable or other
+registers. This makes software little complex.
+
+A single node in the device tree is used to describe the shared
+interrupt multiplexor (one node for all groups). A group in the
+interrupt controller shares config/control registers with other groups.
+For example, a 32-bit interrupt enable/disable config register can
+accommodate upto 4 interrupt groups.
+
+Required properties:
+ - compatible: should be, either of
+ - "st,spear300-shirq"
+ - "st,spear310-shirq"
+ - "st,spear320-shirq"
+ - interrupt-controller: Identifies the node as an interrupt controller.
+ - #interrupt-cells: should be <1> which basically contains the offset
+ (starting from 0) of interrupts for all the groups.
+ - reg: Base address and size of shirq registers.
+ - interrupts: The list of interrupts generated by the groups which are
+ then connected to a parent interrupt controller. Each group is
+ associated with one of the interrupts, hence number of interrupts (to
+ parent) is equal to number of groups. The format of the interrupt
+ specifier depends in the interrupt parent controller.
+
+ Optional properties:
+ - interrupt-parent: pHandle of the parent interrupt controller, if not
+ inherited from the parent node.
+
+Example:
+
+The following is an example from the SPEAr320 SoC dtsi file.
+
+shirq: interrupt-controller at 0xb3000000 {
+ compatible = "st,spear320-shirq";
+ reg = <0xb3000000 0x1000>;
+ interrupts = <28 29 30 1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+};
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 803de76..f95e5b2 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,14 +14,6 @@
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
-/* FIXME: probe all these from DT */
-#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
-#define SPEAR3XX_IRQ_GEN_RAS_1 28
-#define SPEAR3XX_IRQ_GEN_RAS_2 29
-#define SPEAR3XX_IRQ_GEN_RAS_3 30
-#define SPEAR3XX_IRQ_VIC_END 32
-#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
-
-#define NR_IRQS 160
+#define NR_IRQS 256
#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 6ec3005..a69cbfd 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -17,102 +17,9 @@
#include <linux/of_platform.h>
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
-#include <plat/shirq.h>
#include <mach/generic.h>
#include <mach/spear.h>
-/* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE UL(0x50000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR300_INT_ENB_MASK_REG 0x54
-#define SPEAR300_INT_STS_MASK_REG 0x58
-#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
-#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
-#define SPEAR300_I2S_IRQ_MASK (1 << 2)
-#define SPEAR300_TDM_IRQ_MASK (1 << 3)
-#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
-#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
-#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
-#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
-#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
-
-#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
-
-#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
-
-
-/* SPEAr300 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
-
-/* spear3xx shared irq */
-static struct shirq_dev_config shirq_ras1_config[] = {
- {
- .virq = SPEAR300_VIRQ_IT_PERS_S,
- .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
- .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_IT_CHANGE_S,
- .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
- .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_I2S,
- .enb_mask = SPEAR300_I2S_IRQ_MASK,
- .status_mask = SPEAR300_I2S_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_TDM,
- .enb_mask = SPEAR300_TDM_IRQ_MASK,
- .status_mask = SPEAR300_TDM_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_CAMERA_L,
- .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
- .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_CAMERA_F,
- .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
- .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_CAMERA_V,
- .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
- .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_KEYBOARD,
- .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
- .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_GPIO1,
- .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
- .status_mask = SPEAR300_GPIO1_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_ras1 = {
- .irq = SPEAR3XX_IRQ_GEN_RAS_1,
- .dev_config = shirq_ras1_config,
- .dev_count = ARRAY_SIZE(shirq_ras1_config),
- .regs = {
- .enb_reg = SPEAR300_INT_ENB_MASK_REG,
- .status_reg = SPEAR300_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
- .clear_reg = -1,
- },
-};
-
/* DMAC platform data's slave info */
struct pl08x_channel_data spear300_dma_info[] = {
{
@@ -285,21 +192,11 @@ static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
static void __init spear300_dt_init(void)
{
- int ret;
-
pl080_plat_data.slave_channels = spear300_dma_info;
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
of_platform_populate(NULL, of_default_bus_match_table,
spear300_auxdata_lookup, NULL);
-
- /* shared irq registration */
- shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
- if (shirq_ras1.regs.base) {
- ret = spear_shirq_register(&shirq_ras1);
- if (ret)
- pr_err("Error registering Shared IRQ\n");
- }
}
static const char * const spear300_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 1d0e435..b963ebb 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -18,7 +18,6 @@
#include <linux/of_platform.h>
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
-#include <plat/shirq.h>
#include <mach/generic.h>
#include <mach/spear.h>
@@ -27,176 +26,6 @@
#define SPEAR310_UART3_BASE UL(0xB2100000)
#define SPEAR310_UART4_BASE UL(0xB2180000)
#define SPEAR310_UART5_BASE UL(0xB2200000)
-#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR310_INT_STS_MASK_REG 0x04
-#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
-#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
-#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
-#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
-#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
-#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
-#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
-#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
-#define SPEAR310_UART1_IRQ_MASK (1 << 8)
-#define SPEAR310_UART2_IRQ_MASK (1 << 9)
-#define SPEAR310_UART3_IRQ_MASK (1 << 10)
-#define SPEAR310_UART4_IRQ_MASK (1 << 11)
-#define SPEAR310_UART5_IRQ_MASK (1 << 12)
-#define SPEAR310_EMI_IRQ_MASK (1 << 13)
-#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
-#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
-#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
-
-#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
-#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
-#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
-#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
-
-/* SPEAr310 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
-#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
-
-
-/* spear3xx shared irq */
-static struct shirq_dev_config shirq_ras1_config[] = {
- {
- .virq = SPEAR310_VIRQ_SMII0,
- .status_mask = SPEAR310_SMII0_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_SMII1,
- .status_mask = SPEAR310_SMII1_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_SMII2,
- .status_mask = SPEAR310_SMII2_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_SMII3,
- .status_mask = SPEAR310_SMII3_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
- .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
- .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
- .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
- .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_ras1 = {
- .irq = SPEAR3XX_IRQ_GEN_RAS_1,
- .dev_config = shirq_ras1_config,
- .dev_count = ARRAY_SIZE(shirq_ras1_config),
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR310_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
- .clear_reg = -1,
- },
-};
-
-static struct shirq_dev_config shirq_ras2_config[] = {
- {
- .virq = SPEAR310_VIRQ_UART1,
- .status_mask = SPEAR310_UART1_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_UART2,
- .status_mask = SPEAR310_UART2_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_UART3,
- .status_mask = SPEAR310_UART3_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_UART4,
- .status_mask = SPEAR310_UART4_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_UART5,
- .status_mask = SPEAR310_UART5_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_ras2 = {
- .irq = SPEAR3XX_IRQ_GEN_RAS_2,
- .dev_config = shirq_ras2_config,
- .dev_count = ARRAY_SIZE(shirq_ras2_config),
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR310_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
- .clear_reg = -1,
- },
-};
-
-static struct shirq_dev_config shirq_ras3_config[] = {
- {
- .virq = SPEAR310_VIRQ_EMI,
- .status_mask = SPEAR310_EMI_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_ras3 = {
- .irq = SPEAR3XX_IRQ_GEN_RAS_3,
- .dev_config = shirq_ras3_config,
- .dev_count = ARRAY_SIZE(shirq_ras3_config),
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR310_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
- .clear_reg = -1,
- },
-};
-
-static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
- {
- .virq = SPEAR310_VIRQ_TDM_HDLC,
- .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_RS485_0,
- .status_mask = SPEAR310_RS485_0_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_RS485_1,
- .status_mask = SPEAR310_RS485_1_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_intrcomm_ras = {
- .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
- .dev_config = shirq_intrcomm_ras_config,
- .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR310_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
- .clear_reg = -1,
- },
-};
/* DMAC platform data's slave info */
struct pl08x_channel_data spear310_dma_info[] = {
@@ -405,42 +234,11 @@ static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
static void __init spear310_dt_init(void)
{
- void __iomem *base;
- int ret;
-
pl080_plat_data.slave_channels = spear310_dma_info;
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
of_platform_populate(NULL, of_default_bus_match_table,
spear310_auxdata_lookup, NULL);
-
- /* shared irq registration */
- base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
- if (base) {
- /* shirq 1 */
- shirq_ras1.regs.base = base;
- ret = spear_shirq_register(&shirq_ras1);
- if (ret)
- pr_err("Error registering Shared IRQ 1\n");
-
- /* shirq 2 */
- shirq_ras2.regs.base = base;
- ret = spear_shirq_register(&shirq_ras2);
- if (ret)
- pr_err("Error registering Shared IRQ 2\n");
-
- /* shirq 3 */
- shirq_ras3.regs.base = base;
- ret = spear_shirq_register(&shirq_ras3);
- if (ret)
- pr_err("Error registering Shared IRQ 3\n");
-
- /* shirq 4 */
- shirq_intrcomm_ras.regs.base = base;
- ret = spear_shirq_register(&shirq_intrcomm_ras);
- if (ret)
- pr_err("Error registering Shared IRQ 4\n");
- }
}
static const char * const spear310_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index fd823c6..707504b 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -19,7 +19,6 @@
#include <linux/of_platform.h>
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
-#include <plat/shirq.h>
#include <mach/generic.h>
#include <mach/spear.h>
@@ -28,184 +27,6 @@
#define SPEAR320_SSP0_BASE UL(0xA5000000)
#define SPEAR320_SSP1_BASE UL(0xA6000000)
-/* Interrupt registers offsets and masks */
-#define SPEAR320_INT_STS_MASK_REG 0x04
-#define SPEAR320_INT_CLR_MASK_REG 0x04
-#define SPEAR320_INT_ENB_MASK_REG 0x08
-#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
-#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
-#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
-#define SPEAR320_EMI_IRQ_MASK (1 << 7)
-#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
-#define SPEAR320_SPP_IRQ_MASK (1 << 9)
-#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
-#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
-#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
-#define SPEAR320_UART1_IRQ_MASK (1 << 13)
-#define SPEAR320_UART2_IRQ_MASK (1 << 14)
-#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
-#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
-#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
-#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
-#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
-#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
-#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
-
-#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
-#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
-#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
-
-/* SPEAr320 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
-#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
-#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
-
-/* spear3xx shared irq */
-static struct shirq_dev_config shirq_ras1_config[] = {
- {
- .virq = SPEAR320_VIRQ_EMI,
- .status_mask = SPEAR320_EMI_IRQ_MASK,
- .clear_mask = SPEAR320_EMI_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_CLCD,
- .status_mask = SPEAR320_CLCD_IRQ_MASK,
- .clear_mask = SPEAR320_CLCD_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_SPP,
- .status_mask = SPEAR320_SPP_IRQ_MASK,
- .clear_mask = SPEAR320_SPP_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_ras1 = {
- .irq = SPEAR3XX_IRQ_GEN_RAS_1,
- .dev_config = shirq_ras1_config,
- .dev_count = ARRAY_SIZE(shirq_ras1_config),
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR320_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
- .clear_reg = SPEAR320_INT_CLR_MASK_REG,
- .reset_to_clear = 1,
- },
-};
-
-static struct shirq_dev_config shirq_ras3_config[] = {
- {
- .virq = SPEAR320_VIRQ_PLGPIO,
- .enb_mask = SPEAR320_GPIO_IRQ_MASK,
- .status_mask = SPEAR320_GPIO_IRQ_MASK,
- .clear_mask = SPEAR320_GPIO_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_I2S_PLAY,
- .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
- .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
- .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_I2S_REC,
- .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
- .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
- .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_ras3 = {
- .irq = SPEAR3XX_IRQ_GEN_RAS_3,
- .dev_config = shirq_ras3_config,
- .dev_count = ARRAY_SIZE(shirq_ras3_config),
- .regs = {
- .enb_reg = SPEAR320_INT_ENB_MASK_REG,
- .reset_to_enb = 1,
- .status_reg = SPEAR320_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
- .clear_reg = SPEAR320_INT_CLR_MASK_REG,
- .reset_to_clear = 1,
- },
-};
-
-static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
- {
- .virq = SPEAR320_VIRQ_CANU,
- .status_mask = SPEAR320_CAN_U_IRQ_MASK,
- .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_CANL,
- .status_mask = SPEAR320_CAN_L_IRQ_MASK,
- .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_UART1,
- .status_mask = SPEAR320_UART1_IRQ_MASK,
- .clear_mask = SPEAR320_UART1_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_UART2,
- .status_mask = SPEAR320_UART2_IRQ_MASK,
- .clear_mask = SPEAR320_UART2_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_SSP1,
- .status_mask = SPEAR320_SSP1_IRQ_MASK,
- .clear_mask = SPEAR320_SSP1_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_SSP2,
- .status_mask = SPEAR320_SSP2_IRQ_MASK,
- .clear_mask = SPEAR320_SSP2_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_SMII0,
- .status_mask = SPEAR320_SMII0_IRQ_MASK,
- .clear_mask = SPEAR320_SMII0_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_MII1_SMII1,
- .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
- .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
- .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
- .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
- .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
- .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_I2C1,
- .status_mask = SPEAR320_I2C1_IRQ_MASK,
- .clear_mask = SPEAR320_I2C1_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_intrcomm_ras = {
- .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
- .dev_config = shirq_intrcomm_ras_config,
- .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR320_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
- .clear_reg = SPEAR320_INT_CLR_MASK_REG,
- .reset_to_clear = 1,
- },
-};
-
/* DMAC platform data's slave info */
struct pl08x_channel_data spear320_dma_info[] = {
{
@@ -416,36 +237,11 @@ static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
static void __init spear320_dt_init(void)
{
- void __iomem *base;
- int ret;
-
pl080_plat_data.slave_channels = spear320_dma_info;
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
of_platform_populate(NULL, of_default_bus_match_table,
spear320_auxdata_lookup, NULL);
-
- /* shared irq registration */
- base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
- if (base) {
- /* shirq 1 */
- shirq_ras1.regs.base = base;
- ret = spear_shirq_register(&shirq_ras1);
- if (ret)
- pr_err("Error registering Shared IRQ 1\n");
-
- /* shirq 3 */
- shirq_ras3.regs.base = base;
- ret = spear_shirq_register(&shirq_ras3);
- if (ret)
- pr_err("Error registering Shared IRQ 3\n");
-
- /* shirq 4 */
- shirq_intrcomm_ras.regs.base = base;
- ret = spear_shirq_register(&shirq_intrcomm_ras);
- if (ret)
- pr_err("Error registering Shared IRQ 4\n");
- }
}
static const char * const spear320_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 98144ba..781aec9 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -20,6 +20,7 @@
#include <asm/hardware/pl080.h>
#include <asm/hardware/vic.h>
#include <plat/pl080.h>
+#include <plat/shirq.h>
#include <mach/generic.h>
#include <mach/spear.h>
@@ -121,6 +122,9 @@ struct sys_timer spear3xx_timer = {
static const struct of_device_id vic_of_match[] __initconst = {
{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+ { .compatible = "st,spear300-shirq", .data = spear3xx_shirq_of_init, },
+ { .compatible = "st,spear310-shirq", .data = spear3xx_shirq_of_init, },
+ { .compatible = "st,spear320-shirq", .data = spear3xx_shirq_of_init, },
{ /* Sentinel */ }
};
diff --git a/arch/arm/plat-spear/include/plat/shirq.h b/arch/arm/plat-spear/include/plat/shirq.h
index 88a7fbd..1215afe 100644
--- a/arch/arm/plat-spear/include/plat/shirq.h
+++ b/arch/arm/plat-spear/include/plat/shirq.h
@@ -18,24 +18,8 @@
#include <linux/types.h>
/*
- * struct shirq_dev_config: shared irq device configuration
- *
- * virq: virtual irq number of device
- * enb_mask: enable mask of device
- * status_mask: status mask of device
- * clear_mask: clear mask of device
- */
-struct shirq_dev_config {
- u32 virq;
- u32 enb_mask;
- u32 status_mask;
- u32 clear_mask;
-};
-
-/*
* struct shirq_regs: shared irq register configuration
*
- * base: base address of shared irq register
* enb_reg: enable register offset
* reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
* status_reg: status register offset
@@ -44,11 +28,9 @@ struct shirq_dev_config {
* reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
*/
struct shirq_regs {
- void __iomem *base;
u32 enb_reg;
u32 reset_to_enb;
u32 status_reg;
- u32 status_reg_mask;
u32 clear_reg;
u32 reset_to_clear;
};
@@ -57,17 +39,24 @@ struct shirq_regs {
* struct spear_shirq: shared irq structure
*
* irq: hardware irq number
- * dev_config: array of device config structures which are using "irq" line
- * dev_count: size of dev_config array
+ * irq_base: base irq in linux domain
+ * irq_nr: no. of shared interrupts in a particular block
+ * irq_bit_off: starting bit offset in the status register
+ * invalid_irq: irq group is currently disabled
+ * base: base address of shared irq register
* regs: register configuration for shared irq block
*/
struct spear_shirq {
u32 irq;
- struct shirq_dev_config *dev_config;
- u32 dev_count;
+ u32 irq_base;
+ u32 irq_nr;
+ u32 irq_bit_off;
+ int invalid_irq;
+ void __iomem *base;
struct shirq_regs regs;
};
-int spear_shirq_register(struct spear_shirq *shirq);
+int __init spear3xx_shirq_of_init(struct device_node *np,
+ struct device_node *parent);
#endif /* __PLAT_SHIRQ_H */
diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c
index 853e891..3912646 100644
--- a/arch/arm/plat-spear/shirq.c
+++ b/arch/arm/plat-spear/shirq.c
@@ -10,56 +10,182 @@
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <linux/spinlock.h>
#include <plat/shirq.h>
-struct spear_shirq *shirq;
static DEFINE_SPINLOCK(lock);
-static void shirq_irq_mask(struct irq_data *d)
+/* spear300 shared irq registers offsets and masks */
+#define SPEAR300_INT_ENB_MASK_REG 0x54
+#define SPEAR300_INT_STS_MASK_REG 0x58
+
+static struct spear_shirq spear300_shirq_ras1 = {
+ .irq_nr = 9,
+ .irq_bit_off = 0,
+ .regs = {
+ .enb_reg = SPEAR300_INT_ENB_MASK_REG,
+ .status_reg = SPEAR300_INT_STS_MASK_REG,
+ .clear_reg = -1,
+ },
+};
+
+static struct spear_shirq *spear300_shirq_blocks[] = {
+ &spear300_shirq_ras1,
+};
+
+/* spear310 shared irq registers offsets and masks */
+#define SPEAR310_INT_STS_MASK_REG 0x04
+
+static struct spear_shirq spear310_shirq_ras1 = {
+ .irq_nr = 8,
+ .irq_bit_off = 0,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .clear_reg = -1,
+ },
+};
+
+static struct spear_shirq spear310_shirq_ras2 = {
+ .irq_nr = 5,
+ .irq_bit_off = 8,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .clear_reg = -1,
+ },
+};
+
+static struct spear_shirq spear310_shirq_ras3 = {
+ .irq_nr = 1,
+ .irq_bit_off = 13,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .clear_reg = -1,
+ },
+};
+
+static struct spear_shirq spear310_shirq_intrcomm_ras = {
+ .irq_nr = 3,
+ .irq_bit_off = 14,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .clear_reg = -1,
+ },
+};
+
+static struct spear_shirq *spear310_shirq_blocks[] = {
+ &spear310_shirq_ras1,
+ &spear310_shirq_ras2,
+ &spear310_shirq_ras3,
+ &spear310_shirq_intrcomm_ras,
+};
+
+/* spear320 shared irq registers offsets and masks */
+#define SPEAR320_INT_STS_MASK_REG 0x04
+#define SPEAR320_INT_CLR_MASK_REG 0x04
+#define SPEAR320_INT_ENB_MASK_REG 0x08
+
+static struct spear_shirq spear320_shirq_ras1 = {
+ .irq_nr = 3,
+ .irq_bit_off = 7,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
+ .reset_to_clear = 1,
+ },
+};
+
+static struct spear_shirq spear320_shirq_ras2 = {
+ .irq_nr = 1,
+ .irq_bit_off = 10,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
+ .reset_to_clear = 1,
+ },
+};
+
+static struct spear_shirq spear320_shirq_ras3 = {
+ .irq_nr = 3,
+ .irq_bit_off = 0,
+ .invalid_irq = 1,
+ .regs = {
+ .enb_reg = SPEAR320_INT_ENB_MASK_REG,
+ .reset_to_enb = 1,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
+ .reset_to_clear = 1,
+ },
+};
+
+static struct spear_shirq spear320_shirq_intrcomm_ras = {
+ .irq_nr = 11,
+ .irq_bit_off = 11,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
+ .reset_to_clear = 1,
+ },
+};
+
+static struct spear_shirq *spear320_shirq_blocks[] = {
+ &spear320_shirq_ras3,
+ &spear320_shirq_ras1,
+ &spear320_shirq_ras2,
+ &spear320_shirq_intrcomm_ras,
+};
+
+static void shirq_irq_mask_unmask(struct irq_data *d, bool mask)
{
struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
- u32 val, id = d->irq - shirq->dev_config[0].virq;
+ u32 val, offset = d->irq - shirq->irq_base;
unsigned long flags;
- if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
+ if (shirq->regs.enb_reg == -1)
return;
spin_lock_irqsave(&lock, flags);
- val = readl(shirq->regs.base + shirq->regs.enb_reg);
- if (shirq->regs.reset_to_enb)
- val |= shirq->dev_config[id].enb_mask;
+ val = readl(shirq->base + shirq->regs.enb_reg);
+
+ if (mask ^ shirq->regs.reset_to_enb)
+ val &= ~(0x1 << shirq->irq_bit_off << offset);
else
- val &= ~(shirq->dev_config[id].enb_mask);
- writel(val, shirq->regs.base + shirq->regs.enb_reg);
+ val |= 0x1 << shirq->irq_bit_off << offset;
+
+ writel(val, shirq->base + shirq->regs.enb_reg);
spin_unlock_irqrestore(&lock, flags);
+
}
-static void shirq_irq_unmask(struct irq_data *d)
+static void shirq_irq_mask(struct irq_data *d)
{
- struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
- u32 val, id = d->irq - shirq->dev_config[0].virq;
- unsigned long flags;
-
- if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
- return;
+ shirq_irq_mask_unmask(d, 1);
+}
- spin_lock_irqsave(&lock, flags);
- val = readl(shirq->regs.base + shirq->regs.enb_reg);
- if (shirq->regs.reset_to_enb)
- val &= ~(shirq->dev_config[id].enb_mask);
- else
- val |= shirq->dev_config[id].enb_mask;
- writel(val, shirq->regs.base + shirq->regs.enb_reg);
- spin_unlock_irqrestore(&lock, flags);
+static void shirq_irq_unmask(struct irq_data *d)
+{
+ shirq_irq_mask_unmask(d, 0);
}
static struct irq_chip shirq_chip = {
- .name = "spear_shirq",
+ .name = "spear-shirq",
.irq_ack = shirq_irq_mask,
.irq_mask = shirq_irq_mask,
.irq_unmask = shirq_irq_unmask,
@@ -67,52 +193,131 @@ static struct irq_chip shirq_chip = {
static void shirq_handler(unsigned irq, struct irq_desc *desc)
{
- u32 i, val, mask;
+ u32 i, j, val, mask, tmp;
+ struct irq_chip *chip;
struct spear_shirq *shirq = irq_get_handler_data(irq);
- desc->irq_data.chip->irq_ack(&desc->irq_data);
- while ((val = readl(shirq->regs.base + shirq->regs.status_reg) &
- shirq->regs.status_reg_mask)) {
- for (i = 0; (i < shirq->dev_count) && val; i++) {
- if (!(shirq->dev_config[i].status_mask & val))
+ chip = irq_get_chip(irq);
+ chip->irq_ack(&desc->irq_data);
+
+ mask = ((0x1 << shirq->irq_nr) - 1) << shirq->irq_bit_off;
+ while ((val = readl(shirq->base + shirq->regs.status_reg) &
+ mask)) {
+
+ val >>= shirq->irq_bit_off;
+ for (i = 0, j = 1; i < shirq->irq_nr; i++, j <<= 1) {
+
+ if (!(j & val))
continue;
- generic_handle_irq(shirq->dev_config[i].virq);
+ generic_handle_irq(shirq->irq_base + i);
/* clear interrupt */
- val &= ~shirq->dev_config[i].status_mask;
- if ((shirq->regs.clear_reg == -1) ||
- shirq->dev_config[i].clear_mask == -1)
+ if (shirq->regs.clear_reg == -1)
continue;
- mask = readl(shirq->regs.base + shirq->regs.clear_reg);
+
+ tmp = readl(shirq->base + shirq->regs.clear_reg);
if (shirq->regs.reset_to_clear)
- mask &= ~shirq->dev_config[i].clear_mask;
+ tmp &= ~(j << shirq->irq_bit_off);
else
- mask |= shirq->dev_config[i].clear_mask;
- writel(mask, shirq->regs.base + shirq->regs.clear_reg);
+ tmp |= (j << shirq->irq_bit_off);
+ writel(tmp, shirq->base + shirq->regs.clear_reg);
}
}
- desc->irq_data.chip->irq_unmask(&desc->irq_data);
+ chip->irq_unmask(&desc->irq_data);
}
-int spear_shirq_register(struct spear_shirq *shirq)
+static void __init spear_shirq_register(struct spear_shirq *shirq)
{
int i;
- if (!shirq || !shirq->dev_config || !shirq->regs.base)
- return -EFAULT;
-
- if (!shirq->dev_count)
- return -EINVAL;
+ if (shirq->invalid_irq)
+ return;
irq_set_chained_handler(shirq->irq, shirq_handler);
- for (i = 0; i < shirq->dev_count; i++) {
- irq_set_chip_and_handler(shirq->dev_config[i].virq,
+ for (i = 0; i < shirq->irq_nr; i++) {
+ irq_set_chip_and_handler(shirq->irq_base + i,
&shirq_chip, handle_simple_irq);
- set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID);
- irq_set_chip_data(shirq->dev_config[i].virq, shirq);
+ set_irq_flags(shirq->irq_base + i, IRQF_VALID);
+ irq_set_chip_data(shirq->irq_base + i, shirq);
}
irq_set_handler_data(shirq->irq, shirq);
+}
+
+static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
+ void __iomem *base, struct device_node *np)
+{
+ int i, irq_base, hwirq = 0, irq_nr = 0;
+ static struct irq_domain *shirq_domain;
+
+ for (i = 0; i < block_nr; i++)
+ irq_nr += shirq_blocks[i]->irq_nr;
+
+ irq_base = irq_alloc_descs(-1, 0, irq_nr, 0);
+ if (IS_ERR_VALUE(irq_base)) {
+ pr_err("%s: irq desc alloc failed\n", __func__);
+ return -ENXIO;
+ }
+
+ shirq_domain = irq_domain_add_legacy(np, irq_nr, irq_base, 0,
+ &irq_domain_simple_ops, NULL);
+ if (WARN_ON(!shirq_domain)) {
+ pr_warn("%s: irq domain init failed\n", __func__);
+ irq_free_descs(irq_base, irq_nr);
+ return -ENXIO;
+ }
+
+ for (i = 0; i < block_nr; i++) {
+ shirq_blocks[i]->base = base;
+ shirq_blocks[i]->irq_base = irq_find_mapping(shirq_domain,
+ hwirq);
+ shirq_blocks[i]->irq = irq_of_parse_and_map(np, i);
+
+ spear_shirq_register(shirq_blocks[i]);
+ hwirq += shirq_blocks[i]->irq_nr;
+ }
+
return 0;
}
+
+int __init spear3xx_shirq_of_init(struct device_node *np,
+ struct device_node *parent)
+{
+ struct spear_shirq **shirq_blocks;
+ void __iomem *base;
+ int block_nr, ret;
+
+ base = of_iomap(np, 0);
+ if (!base) {
+ pr_err("%s: failed to map shirq registers\n", __func__);
+ return -ENXIO;
+ }
+
+ if (of_device_is_compatible(np, "st,spear300-shirq")) {
+ shirq_blocks = spear300_shirq_blocks;
+ block_nr = ARRAY_SIZE(spear300_shirq_blocks);
+ } else if (of_device_is_compatible(np, "st,spear310-shirq")) {
+ shirq_blocks = spear310_shirq_blocks;
+ block_nr = ARRAY_SIZE(spear310_shirq_blocks);
+ } else if (of_device_is_compatible(np, "st,spear320-shirq")) {
+ shirq_blocks = spear320_shirq_blocks;
+ block_nr = ARRAY_SIZE(spear320_shirq_blocks);
+ } else {
+ pr_err("%s: unknown platform\n", __func__);
+ ret = -EINVAL;
+ goto unmap;
+ }
+
+ ret = shirq_init(shirq_blocks, block_nr, base, np);
+ if (ret) {
+ pr_err("%s: shirq initialization failed\n", __func__);
+ goto unmap;
+ }
+
+ return ret;
+
+unmap:
+ iounmap(base);
+ return ret;
+}
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH 13/14] ARM: SPEAr3xx: DT: add shirq node for interrupt multiplexor
From: Viresh Kumar @ 2012-11-11 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1352608333.git.viresh.kumar@linaro.org>
From: Shiraz Hashim <shiraz.hashim@st.com>
shirq layer has been adapted to DT, add corresponding nodes in all
SPEAr3xx variants.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/spear300.dtsi | 12 ++++++++++++
arch/arm/boot/dts/spear310.dtsi | 18 ++++++++++++++++++
arch/arm/boot/dts/spear320.dtsi | 24 ++++++++++++++++++++++--
3 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
index fdac871..090adc6 100644
--- a/arch/arm/boot/dts/spear300.dtsi
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -52,6 +52,14 @@
status = "disabled";
};
+ shirq: interrupt-controller at 0x50000000 {
+ compatible = "st,spear300-shirq";
+ reg = <0x50000000 0x1000>;
+ interrupts = <28>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
apb {
#address-cells = <1>;
#size-cells = <1>;
@@ -64,12 +72,16 @@
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0xa9000000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
kbd at a0000000 {
compatible = "st,spear300-kbd";
reg = <0xa0000000 0x1000>;
+ interrupts = <7>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index 62fc4fb..0527e3a 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -39,6 +39,14 @@
status = "disabled";
};
+ shirq: interrupt-controller at 0xb4000000 {
+ compatible = "st,spear310-shirq";
+ reg = <0xb4000000 0x1000>;
+ interrupts = <28 29 30 1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
apb {
#address-cells = <1>;
#size-cells = <1>;
@@ -49,30 +57,40 @@
serial at b2000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2000000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
serial at b2080000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2080000 0x1000>;
+ interrupts = <9>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
serial at b2100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2100000 0x1000>;
+ interrupts = <10>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
serial at b2180000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2180000 0x1000>;
+ interrupts = <11>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
serial at b2200000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2200000 0x1000>;
+ interrupts = <12>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 582ded7..52b9c05 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -29,7 +29,8 @@
clcd at 90000000 {
compatible = "arm,pl110", "arm,primecell";
reg = <0x90000000 0x1000>;
- interrupts = <33>;
+ interrupts = <8>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
@@ -48,13 +49,24 @@
sdhci at 70000000 {
compatible = "st,sdhci-spear";
reg = <0x70000000 0x100>;
- interrupts = <29>;
+ interrupts = <10>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
+ shirq: interrupt-controller at 0xb3000000 {
+ compatible = "st,spear320-shirq";
+ reg = <0xb3000000 0x1000>;
+ interrupts = <30 28 29 1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
spi1: spi at a5000000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xa5000000 0x1000>;
+ interrupts = <15>;
+ interrupt-parent = <&shirq>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -63,6 +75,8 @@
spi2: spi at a6000000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xa6000000 0x1000>;
+ interrupts = <16>;
+ interrupt-parent = <&shirq>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -87,18 +101,24 @@
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xa7000000 0x1000>;
+ interrupts = <21>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
serial at a3000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xa3000000 0x1000>;
+ interrupts = <13>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
serial at a4000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xa4000000 0x1000>;
+ interrupts = <14>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
};
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH 14/14] ARM: SPEAr320: DT: Add SPEAr 320 HMI board support
From: Viresh Kumar @ 2012-11-11 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1352608333.git.viresh.kumar@linaro.org>
From: Shiraz Hashim <shiraz.hashim@st.com>
This adds support for SPEAr320-HMI board.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/spear320-hmi.dts | 305 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-spear3xx/spear320.c | 1 +
3 files changed, 308 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/spear320-hmi.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b994045..c3295b2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -84,7 +84,8 @@ dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
spear1340-evb.dtb
dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear310-evb.dtb \
- spear320-evb.dtb
+ spear320-evb.dtb \
+ spear320-hmi.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/spear320-hmi.dts
new file mode 100644
index 0000000..3075d2d
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-hmi.dts
@@ -0,0 +1,305 @@
+/*
+ * DTS file for SPEAr320 Evaluation Baord
+ *
+ * Copyright 2012 Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear320.dtsi"
+
+/ {
+ model = "ST SPEAr320 HMI Board";
+ compatible = "st,spear320-hmi", "st,spear320";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory {
+ reg = <0 0x40000000>;
+ };
+
+ ahb {
+ pinmux at b3000000 {
+ st,pinmux-mode = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ i2c0 {
+ st,pins = "i2c0_grp";
+ st,function = "i2c0";
+ };
+ ssp0 {
+ st,pins = "ssp0_grp";
+ st,function = "ssp0";
+ };
+ uart0 {
+ st,pins = "uart0_grp";
+ st,function = "uart0";
+ };
+ clcd {
+ st,pins = "clcd_grp";
+ st,function = "clcd";
+ };
+ fsmc {
+ st,pins = "fsmc_8bit_grp";
+ st,function = "fsmc";
+ };
+ sdhci {
+ st,pins = "sdhci_cd_12_grp";
+ st,function = "sdhci";
+ };
+ i2s {
+ st,pins = "i2s_grp";
+ st,function = "i2s";
+ };
+ uart1 {
+ st,pins = "uart1_grp";
+ st,function = "uart1";
+ };
+ uart2 {
+ st,pins = "uart2_grp";
+ st,function = "uart2";
+ };
+ can0 {
+ st,pins = "can0_grp";
+ st,function = "can0";
+ };
+ can1 {
+ st,pins = "can1_grp";
+ st,function = "can1";
+ };
+ mii0_1 {
+ st,pins = "rmii0_1_grp";
+ st,function = "mii0_1";
+ };
+ pwm0_1 {
+ st,pins = "pwm0_1_pin_37_38_grp";
+ st,function = "pwm0_1";
+ };
+ pwm2 {
+ st,pins = "pwm2_pin_34_grp";
+ st,function = "pwm2";
+ };
+ };
+ };
+
+ clcd at 90000000 {
+ status = "okay";
+ };
+
+ dma at fc400000 {
+ status = "okay";
+ };
+
+ ehci at e1800000 {
+ status = "okay";
+ };
+
+ fsmc: flash at 4c000000 {
+ status = "okay";
+
+ partition at 0 {
+ label = "xloader";
+ reg = <0x0 0x80000>;
+ };
+ partition at 80000 {
+ label = "u-boot";
+ reg = <0x80000 0x140000>;
+ };
+ partition at 1C0000 {
+ label = "environment";
+ reg = <0x1C0000 0x40000>;
+ };
+ partition at 200000 {
+ label = "dtb";
+ reg = <0x200000 0x40000>;
+ };
+ partition at 240000 {
+ label = "linux";
+ reg = <0x240000 0xC00000>;
+ };
+ partition at E40000 {
+ label = "rootfs";
+ reg = <0xE40000 0x0>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button at 1 {
+ label = "user button 1";
+ linux,code = <0x100>;
+ gpios = <&stmpegpio 3 0x4>;
+ debounce-interval = <20>;
+ gpio-key,wakeup = <1>;
+ };
+
+ button at 2 {
+ label = "user button 2";
+ linux,code = <0x200>;
+ gpios = <&stmpegpio 2 0x4>;
+ debounce-interval = <20>;
+ gpio-key,wakeup = <1>;
+ };
+ };
+
+ ohci at e1900000 {
+ status = "okay";
+ };
+
+ ohci at e2100000 {
+ status = "okay";
+ };
+
+ pwm: pwm at a8000000 {
+ status = "okay";
+ };
+
+ sdhci at 70000000 {
+ power-gpio = <&gpiopinctrl 50 1>;
+ power_always_enb;
+ status = "okay";
+ };
+
+ smi: flash at fc000000 {
+ status = "okay";
+ clock-rate=<50000000>;
+
+ flash at f8000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xf8000000 0x800000>;
+ st,smi-fast-mode;
+
+ partition at 0 {
+ label = "xloader";
+ reg = <0x0 0x10000>;
+ };
+ partition at 10000 {
+ label = "u-boot";
+ reg = <0x10000 0x50000>;
+ };
+ partition at 60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
+ };
+ partition at 70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
+ };
+ partition at 80000 {
+ label = "linux";
+ reg = <0x80000 0x310000>;
+ };
+ partition at 390000 {
+ label = "rootfs";
+ reg = <0x390000 0x0>;
+ };
+ };
+ };
+
+ spi0: spi at d0100000 {
+ status = "okay";
+ };
+
+ spi1: spi at a5000000 {
+ status = "okay";
+ };
+
+ spi2: spi at a6000000 {
+ status = "okay";
+ };
+
+ usbd at e1100000 {
+ status = "okay";
+ };
+
+ apb {
+ gpio0: gpio at fc980000 {
+ status = "okay";
+ };
+
+ gpio at b3000000 {
+ status = "okay";
+ };
+
+ i2c0: i2c at d0180000 {
+ status = "okay";
+
+ stmpe811 at 41 {
+ compatible = "st,stmpe811";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x41>;
+ irq-over-gpio;
+ irq-gpios = <&gpiopinctrl 29 0x4>;
+ id = <0>;
+ blocks = <0x5>;
+ irq-trigger = <0x1>;
+
+ stmpegpio: stmpe-gpio {
+ compatible = "stmpe,gpio";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,norequest-mask = <0xF3>;
+ };
+
+ stmpe610-ts {
+ compatible = "stmpe,ts";
+ reg = <0>;
+ ts,sample-time = <4>;
+ ts,mod-12b = <1>;
+ ts,ref-sel = <0>;
+ ts,adc-freq = <1>;
+ ts,ave-ctrl = <1>;
+ ts,touch-det-delay = <3>;
+ ts,settling = <4>;
+ ts,fraction-z = <7>;
+ ts,i-drive = <1>;
+ };
+ };
+ };
+
+ i2c1: i2c at a7000000 {
+ status = "okay";
+ };
+
+ rtc at fc900000 {
+ status = "okay";
+ };
+
+ serial at d0000000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ };
+
+ serial at a3000000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ };
+
+ serial at a4000000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ };
+
+ wdt at fc880000 {
+ status = "okay";
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 707504b..66e3a0c 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -247,6 +247,7 @@ static void __init spear320_dt_init(void)
static const char * const spear320_dt_board_compat[] = {
"st,spear320",
"st,spear320-evb",
+ "st,spear320-hmi",
NULL,
};
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH] ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER
From: Igor Grinberg @ 2012-11-11 9:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121108162004.GA6801@atomide.com>
On 11/08/12 18:20, Tony Lindgren wrote:
> * Igor Grinberg <grinberg@compulab.co.il> [121107 23:15]:
>> On 11/07/12 19:33, Tony Lindgren wrote:
>>>
>>> I think this should be the default for the timers as that counter
>>> does not stop during deeper idle states.
>>
>> Well, it is the default as you can see from the patch.
>> The problem is that for boards that for some reason do not have
>> the 32k wired and rely on MPU/GP timer source, the default will not work
>> and currently there is no way for board to specify which timer source
>> it can use.
>
> Yes. I was just wondering if we can avoid patching all the board
> files by doing it the other way around by introducing a new
> omap_gp_timer rather than renaming all the existing ones?
Is the renaming that bad? One line per machine_desc structure?
Of course we can skip the renaming, but then it will be less consistent
and will not reflect the actual timer source used.
I tried to make it flexible as much as possible and self explanatory.
So above are my considerations, but at this point in time I don't really
care if we rename them or just add a new one, but we have to get rid of
the ugly fall back.
>
>> We have discussed this in San Diego (remember?) and you actually proposed
>> this way as a solution. Well, may be I took it a bit further than you
>> thought, but this is because the board code cannot know which timer source
>> should be used at runtime and the fall back described below, does not work.
>
> Yes thanks I agree we should get rid of that Kconfig option for sure.
>
>>>> --- a/arch/arm/mach-omap2/board-2430sdp.c
>>>> +++ b/arch/arm/mach-omap2/board-2430sdp.c
>>>> @@ -284,6 +284,6 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
>>>> .handle_irq = omap2_intc_handle_irq,
>>>> .init_machine = omap_2430sdp_init,
>>>> .init_late = omap2430_init_late,
>>>> - .timer = &omap2_timer,
>>>> + .timer = &omap2_sync32k_timer,
>>>> .restart = omap_prcm_restart,
>>>> MACHINE_END
>>>> --- a/arch/arm/mach-omap2/board-3430sdp.c
>>>> +++ b/arch/arm/mach-omap2/board-3430sdp.c
>>>> @@ -596,6 +596,6 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
>>>> .handle_irq = omap3_intc_handle_irq,
>>>> .init_machine = omap_3430sdp_init,
>>>> .init_late = omap3430_init_late,
>>>> - .timer = &omap3_timer,
>>>> + .timer = &omap3_sync32k_timer,
>>>> .restart = omap_prcm_restart,
>>>> MACHINE_END
>>> ...
>>>
>>> Can't we assume that the default timer is omap[234]_sync32k_timer to
>>> avoid renaming the timer entries in all the board files?
>>
>> Hmmm...
>> How will this work with the macros defining the sys_timer structure?
>> I would also not want to hide the exact timer used under the default name.
>
> Can't you just add a new sys_timer (or a new macro) for GP only setups?
Of course I can... but I tried to create a flexible generic code, so
no meter how a board will be wired, you just need to specify which timer source
it uses and be done with it.
>
>>> Then we just need a new timer entries for the hardware that does
>>> not have the sycn32k_timer available?
>>
>> Well, I tried to make it small patch just for the hardware that needs it,
>> but I always found some corner case where, IMHO, this does not work/look good.
>
> Can you explain a bit further?
Yes, OMAP4 has its own "local" timer function, OMAP5 - the real time timer
function, we have that fall back from 32k to gptimer for AM33xx and we also
have the use_gptimer_clksrc parameter.
All the above call the same timer source init functions at the end.
>
> I guess what I'm after is just to avoid renaming the existing
> timers in the board-*.c files and only rename the ones that
> need gp timer only.
This means: get rid of the 32k to gptimer fall back.
I've got your point, will cook something shortly.
--
Regards,
Igor.
^ permalink raw reply
* [PATCH v5 0/6] Move rest of omap-iommu to live in drivers/iommu
From: Ohad Ben-Cohen @ 2012-11-11 9:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121102192221.4253.34303.stgit@muffinssi.local>
On Fri, Nov 2, 2012 at 9:23 PM, Tony Lindgren <tony@atomide.com> wrote:
> We need to move the iommu code to live under drivers
> for arm common zImage support.
For the iommu changes in the entire series:
Acked-by: Ohad Ben-Cohen <ohad@wizery.com>
Joerg, it might relieve some pain if this will go through Tony's tree,
as there are some OMAP platform iommu changes coming in from Omar as
well (part of which might have already been merged in the omap
branches). Hope it's ok with both of you guys?
Omar, do you still have any iommu changes coming in ? Can we get
everything merged to the same tree ?
Thanks!
Ohad.
^ permalink raw reply
* [PATCH 02/11] time: convert arch_gettimeoffset to a pointer
From: Geert Uytterhoeven @ 2012-11-11 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352408516-21988-4-git-send-email-swarren@wwwdotorg.org>
On Thu, Nov 8, 2012 at 10:01 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Currently, whenever CONFIG_ARCH_USES_GETTIMEOFFSET is enabled, each
> arch core provides a single implementation of arch_gettimeoffset(). In
> many cases, different sub-architectures, different machines, or
> different timer providers exist, and so the arch ends up implementing
> arch_gettimeoffset() as a call-through-pointer anyway. Examples are
> ARM, Cris, M68K, and it's arguable that the remaining architectures,
> M32R and Blackfin, should be doing this anyway.
>
> Modify arch_gettimeoffset so that it itself is a function pointer, which
> the arch initializes. This will allow later changes to move the
> initialization of this function into individual machine support or timer
> drivers. This is particularly useful for code in drivers/clocksource
> which should rely on an arch-independant mechanism to register their
> implementation of arch_gettimeoffset().
>
> This patch also converts the Cris architecture to set arch_gettimeoffset
> directly to the final implementation in time_init(), because Cris already
> had separate time_init() functions per sub-architecture. M68K and ARM
> are converted to set arch_gettimeoffset the final implementation in later
> patches, because they already have function pointers in place for this
> purpose.
>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Mike Frysinger <vapier@gentoo.org>
> Cc: Mikael Starvik <starvik@axis.com>
> Cc: Jesper Nilsson <jesper.nilsson@axis.com>
> Cc: Hirokazu Takata <takata@linux-m32r.org>
> Cc: Geert Uytterhoeven <geert@linux-m68k.org>
The m68k changes look ok, so
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Cc: John Stultz <johnstul@us.ibm.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH 03/11] m68k: set arch_gettimeoffset directly
From: Geert Uytterhoeven @ 2012-11-11 9:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352408516-21988-5-git-send-email-swarren@wwwdotorg.org>
On Thu, Nov 8, 2012 at 10:01 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> remove m68k's mach_gettimeoffset function pointer, and instead directly
> set the arch_gettimeoffset function pointer. This requires multiplying
> all function results by 1000, since the removed m68k_gettimeoffset() did
> this. Also, s/unsigned long/u32/ just to make the function prototypes
> exactly match that of arch_gettimeoffset.
>
> Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Cc: Philip Blundell <philb@gnu.org>
> Cc: Joshua Thompson <funaho@jurai.org>
> Cc: Sam Creasey <sammy@sammy.net>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> arch/m68k/amiga/config.c | 10 +++++-----
> arch/m68k/apollo/config.c | 9 ++++-----
> arch/m68k/atari/config.c | 4 ++--
> arch/m68k/atari/time.c | 6 +++---
> arch/m68k/bvme6000/config.c | 10 +++++-----
> arch/m68k/hp300/config.c | 2 +-
> arch/m68k/hp300/time.c | 4 ++--
> arch/m68k/hp300/time.h | 2 +-
> arch/m68k/include/asm/machdep.h | 2 +-
> arch/m68k/kernel/setup_mm.c | 1 -
> arch/m68k/kernel/time.c | 9 ---------
> arch/m68k/mac/config.c | 4 ++--
> arch/m68k/mac/via.c | 4 ++--
> arch/m68k/mvme147/config.c | 8 ++++----
> arch/m68k/mvme16x/config.c | 8 ++++----
> arch/m68k/q40/config.c | 8 ++++----
> arch/m68k/sun3/config.c | 4 ++--
> arch/m68k/sun3/intersil.c | 4 ++--
> arch/m68k/sun3x/config.c | 2 +-
> arch/m68k/sun3x/time.c | 2 +-
> arch/m68k/sun3x/time.h | 2 +-
> 21 files changed, 47 insertions(+), 58 deletions(-)
>
> diff --git a/arch/m68k/amiga/config.c b/arch/m68k/amiga/config.c
> index ee01b7a..b819390 100644
> --- a/arch/m68k/amiga/config.c
> +++ b/arch/m68k/amiga/config.c
> @@ -95,7 +95,7 @@ static void amiga_sched_init(irq_handler_t handler);
> static void amiga_get_model(char *model);
> static void amiga_get_hardware_list(struct seq_file *m);
> /* amiga specific timer functions */
> -static unsigned long amiga_gettimeoffset(void);
> +static u32 amiga_gettimeoffset(void);
> extern void amiga_mksound(unsigned int count, unsigned int ticks);
> static void amiga_reset(void);
> extern void amiga_init_sound(void);
> @@ -377,7 +377,7 @@ void __init config_amiga(void)
> mach_init_IRQ = amiga_init_IRQ;
> mach_get_model = amiga_get_model;
> mach_get_hardware_list = amiga_get_hardware_list;
> - mach_gettimeoffset = amiga_gettimeoffset;
> + arch_gettimeoffset = amiga_gettimeoffset;
>
> /*
> * default MAX_DMA=0xffffffff on all machines. If we don't do so, the SCSI
> @@ -482,10 +482,10 @@ static void __init amiga_sched_init(irq_handler_t timer_routine)
> #define TICK_SIZE 10000
>
> /* This is always executed with interrupts disabled. */
> -static unsigned long amiga_gettimeoffset(void)
> +static u32 amiga_gettimeoffset(void)
> {
> unsigned short hi, lo, hi2;
> - unsigned long ticks, offset = 0;
> + u32 ticks, offset = 0;
>
> /* read CIA B timer A current value */
> hi = ciab.tahi;
> @@ -507,7 +507,7 @@ static unsigned long amiga_gettimeoffset(void)
> ticks = jiffy_ticks - ticks;
> ticks = (10000 * ticks) / jiffy_ticks;
>
> - return ticks + offset;
> + return (ticks + offset) * 1000;
> }
>
> static void amiga_reset(void) __noreturn;
> diff --git a/arch/m68k/apollo/config.c b/arch/m68k/apollo/config.c
> index f5565d6..3ea56b9 100644
> --- a/arch/m68k/apollo/config.c
> +++ b/arch/m68k/apollo/config.c
> @@ -26,7 +26,7 @@ u_long apollo_model;
>
> extern void dn_sched_init(irq_handler_t handler);
> extern void dn_init_IRQ(void);
> -extern unsigned long dn_gettimeoffset(void);
> +extern u32 dn_gettimeoffset(void);
> extern int dn_dummy_hwclk(int, struct rtc_time *);
> extern int dn_dummy_set_clock_mmss(unsigned long);
> extern void dn_dummy_reset(void);
> @@ -151,7 +151,7 @@ void __init config_apollo(void)
>
> mach_sched_init=dn_sched_init; /* */
> mach_init_IRQ=dn_init_IRQ;
> - mach_gettimeoffset = dn_gettimeoffset;
> + arch_gettimeoffset = dn_gettimeoffset;
> mach_max_dma_address = 0xffffffff;
> mach_hwclk = dn_dummy_hwclk; /* */
> mach_set_clock_mmss = dn_dummy_set_clock_mmss; /* */
> @@ -203,10 +203,9 @@ void dn_sched_init(irq_handler_t timer_routine)
> pr_err("Couldn't register timer interrupt\n");
> }
>
> -unsigned long dn_gettimeoffset(void) {
> -
> +u32 dn_gettimeoffset(void)
> +{
> return 0xdeadbeef;
> -
> }
>
> int dn_dummy_hwclk(int op, struct rtc_time *t) {
> diff --git a/arch/m68k/atari/config.c b/arch/m68k/atari/config.c
> index d8eb327..037c11c 100644
> --- a/arch/m68k/atari/config.c
> +++ b/arch/m68k/atari/config.c
> @@ -74,7 +74,7 @@ static void atari_heartbeat(int on);
>
> /* atari specific timer functions (in time.c) */
> extern void atari_sched_init(irq_handler_t);
> -extern unsigned long atari_gettimeoffset (void);
> +extern u32 atari_gettimeoffset(void);
> extern int atari_mste_hwclk (int, struct rtc_time *);
> extern int atari_tt_hwclk (int, struct rtc_time *);
> extern int atari_mste_set_clock_mmss (unsigned long);
> @@ -204,7 +204,7 @@ void __init config_atari(void)
> mach_init_IRQ = atari_init_IRQ;
> mach_get_model = atari_get_model;
> mach_get_hardware_list = atari_get_hardware_list;
> - mach_gettimeoffset = atari_gettimeoffset;
> + arch_gettimeoffset = atari_gettimeoffset;
> mach_reset = atari_reset;
> mach_max_dma_address = 0xffffff;
> #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE)
> diff --git a/arch/m68k/atari/time.c b/arch/m68k/atari/time.c
> index c0cc68a..da8f981 100644
> --- a/arch/m68k/atari/time.c
> +++ b/arch/m68k/atari/time.c
> @@ -42,9 +42,9 @@ atari_sched_init(irq_handler_t timer_routine)
> #define TICK_SIZE 10000
>
> /* This is always executed with interrupts disabled. */
> -unsigned long atari_gettimeoffset (void)
> +u32 atari_gettimeoffset(void)
> {
> - unsigned long ticks, offset = 0;
> + u32 ticks, offset = 0;
>
> /* read MFP timer C current value */
> ticks = st_mfp.tim_dt_c;
> @@ -57,7 +57,7 @@ unsigned long atari_gettimeoffset (void)
> ticks = INT_TICKS - ticks;
> ticks = ticks * 10000L / INT_TICKS;
>
> - return ticks + offset;
> + return (ticks + offset) * 1000;
> }
>
>
> diff --git a/arch/m68k/bvme6000/config.c b/arch/m68k/bvme6000/config.c
> index 0bf850a..8943aa4 100644
> --- a/arch/m68k/bvme6000/config.c
> +++ b/arch/m68k/bvme6000/config.c
> @@ -38,7 +38,7 @@
>
> static void bvme6000_get_model(char *model);
> extern void bvme6000_sched_init(irq_handler_t handler);
> -extern unsigned long bvme6000_gettimeoffset (void);
> +extern u32 bvme6000_gettimeoffset(void);
> extern int bvme6000_hwclk (int, struct rtc_time *);
> extern int bvme6000_set_clock_mmss (unsigned long);
> extern void bvme6000_reset (void);
> @@ -110,7 +110,7 @@ void __init config_bvme6000(void)
> mach_max_dma_address = 0xffffffff;
> mach_sched_init = bvme6000_sched_init;
> mach_init_IRQ = bvme6000_init_IRQ;
> - mach_gettimeoffset = bvme6000_gettimeoffset;
> + arch_gettimeoffset = bvme6000_gettimeoffset;
> mach_hwclk = bvme6000_hwclk;
> mach_set_clock_mmss = bvme6000_set_clock_mmss;
> mach_reset = bvme6000_reset;
> @@ -216,13 +216,13 @@ void bvme6000_sched_init (irq_handler_t timer_routine)
> * results...
> */
>
> -unsigned long bvme6000_gettimeoffset (void)
> +u32 bvme6000_gettimeoffset(void)
> {
> volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
> volatile PitRegsPtr pit = (PitRegsPtr)BVME_PIT_BASE;
> unsigned char msr = rtc->msr & 0xc0;
> unsigned char t1int, t1op;
> - unsigned long v = 800000, ov;
> + u32 v = 800000, ov;
>
> rtc->msr = 0; /* Ensure timer registers accessible */
>
> @@ -246,7 +246,7 @@ unsigned long bvme6000_gettimeoffset (void)
> v += 10000; /* Int pending, + 10ms */
> rtc->msr = msr;
>
> - return v;
> + return v * 1000;
> }
>
> /*
> diff --git a/arch/m68k/hp300/config.c b/arch/m68k/hp300/config.c
> index bf16af1..b7609f7 100644
> --- a/arch/m68k/hp300/config.c
> +++ b/arch/m68k/hp300/config.c
> @@ -251,7 +251,7 @@ void __init config_hp300(void)
> mach_sched_init = hp300_sched_init;
> mach_init_IRQ = hp300_init_IRQ;
> mach_get_model = hp300_get_model;
> - mach_gettimeoffset = hp300_gettimeoffset;
> + arch_gettimeoffset = hp300_gettimeoffset;
> mach_hwclk = hp300_hwclk;
> mach_get_ss = hp300_get_ss;
> mach_reset = hp300_reset;
> diff --git a/arch/m68k/hp300/time.c b/arch/m68k/hp300/time.c
> index 29a71be..749543b 100644
> --- a/arch/m68k/hp300/time.c
> +++ b/arch/m68k/hp300/time.c
> @@ -46,7 +46,7 @@ static irqreturn_t hp300_tick(int irq, void *dev_id)
> return vector(irq, NULL);
> }
>
> -unsigned long hp300_gettimeoffset(void)
> +u32 hp300_gettimeoffset(void)
> {
> /* Read current timer 1 value */
> unsigned char lsb, msb1, msb2;
> @@ -59,7 +59,7 @@ unsigned long hp300_gettimeoffset(void)
> /* A carry happened while we were reading. Read it again */
> lsb = in_8(CLOCKBASE + 7);
> ticks = INTVAL - ((msb2 << 8) | lsb);
> - return (USECS_PER_JIFFY * ticks) / INTVAL;
> + return ((USECS_PER_JIFFY * ticks) / INTVAL) * 1000;
> }
>
> void __init hp300_sched_init(irq_handler_t vector)
> diff --git a/arch/m68k/hp300/time.h b/arch/m68k/hp300/time.h
> index 7b98242..f5583ec 100644
> --- a/arch/m68k/hp300/time.h
> +++ b/arch/m68k/hp300/time.h
> @@ -1,2 +1,2 @@
> extern void hp300_sched_init(irq_handler_t vector);
> -extern unsigned long hp300_gettimeoffset(void);
> +extern u32 hp300_gettimeoffset(void);
> diff --git a/arch/m68k/include/asm/machdep.h b/arch/m68k/include/asm/machdep.h
> index 825c1c8..953ca21 100644
> --- a/arch/m68k/include/asm/machdep.h
> +++ b/arch/m68k/include/asm/machdep.h
> @@ -3,6 +3,7 @@
>
> #include <linux/seq_file.h>
> #include <linux/interrupt.h>
> +#include <linux/time.h>
>
> struct pt_regs;
> struct mktime;
> @@ -16,7 +17,6 @@ extern void (*mach_init_IRQ) (void);
> extern void (*mach_get_model) (char *model);
> extern void (*mach_get_hardware_list) (struct seq_file *m);
> /* machine dependent timer functions */
> -extern unsigned long (*mach_gettimeoffset)(void);
> extern int (*mach_hwclk)(int, struct rtc_time*);
> extern unsigned int (*mach_get_ss)(void);
> extern int (*mach_get_rtc_pll)(struct rtc_pll_info *);
> diff --git a/arch/m68k/kernel/setup_mm.c b/arch/m68k/kernel/setup_mm.c
> index d872ce4..80cfbe5 100644
> --- a/arch/m68k/kernel/setup_mm.c
> +++ b/arch/m68k/kernel/setup_mm.c
> @@ -84,7 +84,6 @@ void (*mach_init_IRQ) (void) __initdata = NULL;
> void (*mach_get_model) (char *model);
> void (*mach_get_hardware_list) (struct seq_file *m);
> /* machine dependent timer functions */
> -unsigned long (*mach_gettimeoffset) (void);
> int (*mach_hwclk) (int, struct rtc_time*);
> EXPORT_SYMBOL(mach_hwclk);
> int (*mach_set_clock_mmss) (unsigned long);
> diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c
> index c2994c8..bea6bcf 100644
> --- a/arch/m68k/kernel/time.c
> +++ b/arch/m68k/kernel/time.c
> @@ -82,11 +82,6 @@ void read_persistent_clock(struct timespec *ts)
>
> #ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
>
> -static u32 m68k_gettimeoffset(void)
> -{
> - return mach_gettimeoffset() * 1000;
> -}
> -
> static int __init rtc_init(void)
> {
> struct platform_device *pdev;
> @@ -104,9 +99,5 @@ module_init(rtc_init);
>
> void __init time_init(void)
> {
> -#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
> - arch_gettimeoffset = m68k_gettimeoffset;
> -#endif
> -
> mach_sched_init(timer_interrupt);
> }
> diff --git a/arch/m68k/mac/config.c b/arch/m68k/mac/config.c
> index d9f62e0..afb95d5 100644
> --- a/arch/m68k/mac/config.c
> +++ b/arch/m68k/mac/config.c
> @@ -52,7 +52,7 @@ struct mac_booter_data mac_bi_data;
> static unsigned long mac_orig_videoaddr;
>
> /* Mac specific timer functions */
> -extern unsigned long mac_gettimeoffset(void);
> +extern u32 mac_gettimeoffset(void);
> extern int mac_hwclk(int, struct rtc_time *);
> extern int mac_set_clock_mmss(unsigned long);
> extern void iop_preinit(void);
> @@ -177,7 +177,7 @@ void __init config_mac(void)
> mach_sched_init = mac_sched_init;
> mach_init_IRQ = mac_init_IRQ;
> mach_get_model = mac_get_model;
> - mach_gettimeoffset = mac_gettimeoffset;
> + arch_gettimeoffset = mac_gettimeoffset;
> mach_hwclk = mac_hwclk;
> mach_set_clock_mmss = mac_set_clock_mmss;
> mach_reset = mac_reset;
> diff --git a/arch/m68k/mac/via.c b/arch/m68k/mac/via.c
> index 2d85662..5d1458b 100644
> --- a/arch/m68k/mac/via.c
> +++ b/arch/m68k/mac/via.c
> @@ -327,7 +327,7 @@ void via_debug_dump(void)
> * TBI: get time offset between scheduling timer ticks
> */
>
> -unsigned long mac_gettimeoffset (void)
> +u32 mac_gettimeoffset(void)
> {
> unsigned long ticks, offset = 0;
>
> @@ -341,7 +341,7 @@ unsigned long mac_gettimeoffset (void)
> ticks = MAC_CLOCK_TICK - ticks;
> ticks = ticks * 10000L / MAC_CLOCK_TICK;
>
> - return ticks + offset;
> + return (ticks + offset) * 1000;
> }
>
> /*
> diff --git a/arch/m68k/mvme147/config.c b/arch/m68k/mvme147/config.c
> index a41c091..1c62628 100644
> --- a/arch/m68k/mvme147/config.c
> +++ b/arch/m68k/mvme147/config.c
> @@ -37,7 +37,7 @@
>
> static void mvme147_get_model(char *model);
> extern void mvme147_sched_init(irq_handler_t handler);
> -extern unsigned long mvme147_gettimeoffset (void);
> +extern u32 mvme147_gettimeoffset(void);
> extern int mvme147_hwclk (int, struct rtc_time *);
> extern int mvme147_set_clock_mmss (unsigned long);
> extern void mvme147_reset (void);
> @@ -88,7 +88,7 @@ void __init config_mvme147(void)
> mach_max_dma_address = 0x01000000;
> mach_sched_init = mvme147_sched_init;
> mach_init_IRQ = mvme147_init_IRQ;
> - mach_gettimeoffset = mvme147_gettimeoffset;
> + arch_gettimeoffset = mvme147_gettimeoffset;
> mach_hwclk = mvme147_hwclk;
> mach_set_clock_mmss = mvme147_set_clock_mmss;
> mach_reset = mvme147_reset;
> @@ -127,7 +127,7 @@ void mvme147_sched_init (irq_handler_t timer_routine)
>
> /* This is always executed with interrupts disabled. */
> /* XXX There are race hazards in this code XXX */
> -unsigned long mvme147_gettimeoffset (void)
> +u32 mvme147_gettimeoffset(void)
> {
> volatile unsigned short *cp = (volatile unsigned short *)0xfffe1012;
> unsigned short n;
> @@ -137,7 +137,7 @@ unsigned long mvme147_gettimeoffset (void)
> n = *cp;
>
> n -= PCC_TIMER_PRELOAD;
> - return (unsigned long)n * 25 / 4;
> + return ((unsigned long)n * 25 / 4) * 1000;
> }
>
> static int bcd2int (unsigned char b)
> diff --git a/arch/m68k/mvme16x/config.c b/arch/m68k/mvme16x/config.c
> index b6d7d8a..080a342 100644
> --- a/arch/m68k/mvme16x/config.c
> +++ b/arch/m68k/mvme16x/config.c
> @@ -43,7 +43,7 @@ static MK48T08ptr_t volatile rtc = (MK48T08ptr_t)MVME_RTC_BASE;
>
> static void mvme16x_get_model(char *model);
> extern void mvme16x_sched_init(irq_handler_t handler);
> -extern unsigned long mvme16x_gettimeoffset (void);
> +extern u32 mvme16x_gettimeoffset(void);
> extern int mvme16x_hwclk (int, struct rtc_time *);
> extern int mvme16x_set_clock_mmss (unsigned long);
> extern void mvme16x_reset (void);
> @@ -289,7 +289,7 @@ void __init config_mvme16x(void)
> mach_max_dma_address = 0xffffffff;
> mach_sched_init = mvme16x_sched_init;
> mach_init_IRQ = mvme16x_init_IRQ;
> - mach_gettimeoffset = mvme16x_gettimeoffset;
> + arch_gettimeoffset = mvme16x_gettimeoffset;
> mach_hwclk = mvme16x_hwclk;
> mach_set_clock_mmss = mvme16x_set_clock_mmss;
> mach_reset = mvme16x_reset;
> @@ -405,9 +405,9 @@ void mvme16x_sched_init (irq_handler_t timer_routine)
>
>
> /* This is always executed with interrupts disabled. */
> -unsigned long mvme16x_gettimeoffset (void)
> +u32 mvme16x_gettimeoffset(void)
> {
> - return (*(volatile unsigned long *)0xfff42008);
> + return (*(volatile u32 *)0xfff42008) * 1000;
> }
>
> int bcd2int (unsigned char b)
> diff --git a/arch/m68k/q40/config.c b/arch/m68k/q40/config.c
> index 1adb5b7..658542b 100644
> --- a/arch/m68k/q40/config.c
> +++ b/arch/m68k/q40/config.c
> @@ -40,7 +40,7 @@ extern void q40_init_IRQ(void);
> static void q40_get_model(char *model);
> extern void q40_sched_init(irq_handler_t handler);
>
> -static unsigned long q40_gettimeoffset(void);
> +static u32 q40_gettimeoffset(void);
> static int q40_hwclk(int, struct rtc_time *);
> static unsigned int q40_get_ss(void);
> static int q40_set_clock_mmss(unsigned long);
> @@ -170,7 +170,7 @@ void __init config_q40(void)
> mach_sched_init = q40_sched_init;
>
> mach_init_IRQ = q40_init_IRQ;
> - mach_gettimeoffset = q40_gettimeoffset;
> + arch_gettimeoffset = q40_gettimeoffset;
> mach_hwclk = q40_hwclk;
> mach_get_ss = q40_get_ss;
> mach_get_rtc_pll = q40_get_rtc_pll;
> @@ -204,9 +204,9 @@ int q40_parse_bootinfo(const struct bi_record *rec)
> }
>
>
> -static unsigned long q40_gettimeoffset(void)
> +static u32 q40_gettimeoffset(void)
> {
> - return 5000 * (ql_ticks != 0);
> + return 5000 * (ql_ticks != 0) * 1000;
> }
>
>
> diff --git a/arch/m68k/sun3/config.c b/arch/m68k/sun3/config.c
> index 2ca25bd..f59ec58 100644
> --- a/arch/m68k/sun3/config.c
> +++ b/arch/m68k/sun3/config.c
> @@ -36,7 +36,7 @@
>
> char sun3_reserved_pmeg[SUN3_PMEGS_NUM];
>
> -extern unsigned long sun3_gettimeoffset(void);
> +extern u32 sun3_gettimeoffset(void);
> static void sun3_sched_init(irq_handler_t handler);
> extern void sun3_get_model (char* model);
> extern int sun3_hwclk(int set, struct rtc_time *t);
> @@ -141,7 +141,7 @@ void __init config_sun3(void)
> mach_sched_init = sun3_sched_init;
> mach_init_IRQ = sun3_init_IRQ;
> mach_reset = sun3_reboot;
> - mach_gettimeoffset = sun3_gettimeoffset;
> + arch_gettimeoffset = sun3_gettimeoffset;
> mach_get_model = sun3_get_model;
> mach_hwclk = sun3_hwclk;
> mach_halt = sun3_halt;
> diff --git a/arch/m68k/sun3/intersil.c b/arch/m68k/sun3/intersil.c
> index 94fe801..889829e 100644
> --- a/arch/m68k/sun3/intersil.c
> +++ b/arch/m68k/sun3/intersil.c
> @@ -23,9 +23,9 @@
> #define START_VAL (INTERSIL_RUN | INTERSIL_INT_ENABLE | INTERSIL_24H_MODE)
>
> /* does this need to be implemented? */
> -unsigned long sun3_gettimeoffset(void)
> +u32 sun3_gettimeoffset(void)
> {
> - return 1;
> + return 1000;
> }
>
>
> diff --git a/arch/m68k/sun3x/config.c b/arch/m68k/sun3x/config.c
> index dd306c8..0532d64 100644
> --- a/arch/m68k/sun3x/config.c
> +++ b/arch/m68k/sun3x/config.c
> @@ -48,7 +48,7 @@ void __init config_sun3x(void)
> mach_sched_init = sun3x_sched_init;
> mach_init_IRQ = sun3_init_IRQ;
>
> - mach_gettimeoffset = sun3x_gettimeoffset;
> + arch_gettimeoffset = sun3x_gettimeoffset;
> mach_reset = sun3x_reboot;
>
> mach_hwclk = sun3x_hwclk;
> diff --git a/arch/m68k/sun3x/time.c b/arch/m68k/sun3x/time.c
> index 1d0a724..c8eb08a 100644
> --- a/arch/m68k/sun3x/time.c
> +++ b/arch/m68k/sun3x/time.c
> @@ -71,7 +71,7 @@ int sun3x_hwclk(int set, struct rtc_time *t)
> return 0;
> }
> /* Not much we can do here */
> -unsigned long sun3x_gettimeoffset (void)
> +u32 sun3x_gettimeoffset(void)
> {
> return 0L;
> }
> diff --git a/arch/m68k/sun3x/time.h b/arch/m68k/sun3x/time.h
> index 6909e12..a4f9126 100644
> --- a/arch/m68k/sun3x/time.h
> +++ b/arch/m68k/sun3x/time.h
> @@ -2,7 +2,7 @@
> #define SUN3X_TIME_H
>
> extern int sun3x_hwclk(int set, struct rtc_time *t);
> -unsigned long sun3x_gettimeoffset (void);
> +u32 sun3x_gettimeoffset(void);
> void sun3x_sched_init(irq_handler_t vector);
>
> struct mostek_dt {
> --
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER
From: Igor Grinberg @ 2012-11-11 11:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509BDAF5.1010703@ti.com>
On 11/08/12 18:16, Jon Hunter wrote:
>
> On 11/08/2012 01:59 AM, Igor Grinberg wrote:
>> On 11/07/12 23:36, Jon Hunter wrote:
>>> Hi Igor,
>>>
>>> On 11/07/2012 08:42 AM, Igor Grinberg wrote:
>>>> CONFIG_OMAP_32K_TIMER is kind of standing on the single zImage way.
>>>> Make OMAP2+ timer code independant from the CONFIG_OMAP_32K_TIMER
>>>> setting.
>>>> To remove the dependancy, several conversions/additions had to be done:
>>>> 1) Timer structures and initialization functions are named by the platform
>>>> name and the clock source in use. The decision which timer is
>>>> used is done statically from the machine_desc structure. In the
>>>> future it should come from DT.
>>>> 2) Settings under the CONFIG_OMAP_32K_TIMER option are expanded into
>>>> separate timer structures along with the timer init functions.
>>>> This removes the CONFIG_OMAP_32K_TIMER on OMAP2+ timer code.
>>>> 3) Since we have all the timers defined inside machine_desc structure
>>>> and we no longer need the fallback to gp_timer clock source in case
>>>> 32k_timer clock source is unavailable (namely on AM33xx), we no
>>>> longer need the #ifdef around __omap2_sync32k_clocksource_init()
>>>> function. Remove the #ifdef CONFIG_OMAP_32K_TIMER around the
>>>> __omap2_sync32k_clocksource_init() function.
>>>>
>>>> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
>>>> Cc: Jon Hunter <jon-hunter@ti.com>
>>>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> Cc: Vaibhav Hiremath <hvaibhav@ti.com>
>>>
>>> [snip]
>>>
>>>> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
>>>> index 684d2fc..a4ad7a0 100644
>>>> --- a/arch/arm/mach-omap2/timer.c
>>>> +++ b/arch/arm/mach-omap2/timer.c
>>>> @@ -63,20 +63,8 @@
>>>> #define OMAP2_32K_SOURCE "func_32k_ck"
>>>> #define OMAP3_32K_SOURCE "omap_32k_fck"
>>>> #define OMAP4_32K_SOURCE "sys_32k_ck"
>>>> -
>>>> -#ifdef CONFIG_OMAP_32K_TIMER
>>>> -#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
>>>> -#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
>>>> -#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
>>>> -#define OMAP3_SECURE_TIMER 12
>>>> #define TIMER_PROP_SECURE "ti,timer-secure"
>>>> -#else
>>>> -#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
>>>> -#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
>>>> -#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
>>>> -#define OMAP3_SECURE_TIMER 1
>>>> -#define TIMER_PROP_SECURE "ti,timer-alwon"
>>>> -#endif
>>>> +#define TIMER_PROP_ALWON "ti,timer-alwon"
>>>
>>> Nit-pick, can we drop the TIMER_PROP_SECURE/ALWON and use the
>>> "ti,timer-secure" and "ti,timer-alwon" directly?
>>>
>>> Initially, I also defined TIMER_PROP_ALWON and Rob Herring's feedback
>>> was to drop this and use the property string directly to remove any
>>> abstraction.
>>
>> Well, I don't understand what do you mean by "any abstraction".
>> The purpose of defining those two was to eliminate multiple occurrences
>> of the string in the code, so for example if someone decides to change the
>> property string for some currently unknown reason - it will be easy and small.
>> Defines are a common practice for that, no?
>> If you still think it should be inlined, I will do.
>
> I understand your point, but right now I don't anticipate that we will
> have many options here and so I think that we should drop these.
>
>>>> #define REALTIME_COUNTER_BASE 0x48243200
>>>> #define INCREMENTER_NUMERATOR_OFFSET 0x10
>>>> @@ -216,7 +204,7 @@ void __init omap_dmtimer_init(void)
>>>>
>>>> /* If we are a secure device, remove any secure timer nodes */
>>>> if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
>>>> - np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
>>>> + np = omap_get_timer_dt(omap_timer_match, TIMER_PROP_SECURE);
>>>> if (np)
>>>> of_node_put(np);
>>>> }
>>>> @@ -378,9 +366,8 @@ static u32 notrace dmtimer_read_sched_clock(void)
>>>> return 0;
>>>> }
>>>>
>>>> -#ifdef CONFIG_OMAP_32K_TIMER
>>>> /* Setup free-running counter for clocksource */
>>>> -static int __init omap2_sync32k_clocksource_init(void)
>>>> +static int __init __omap2_sync32k_clocksource_init(void)
>>>
>>> Not sure I follow why you renamed this function here ...
>>
>> I didn't want to add unused arguments to this function, so I've made a
>> wrapper below to have both the sync32k and the gp functions have the same
>> signature (argument list) and be called from a single macro.
>> Anyway, see below.
>
> Ok.
>
>>>
>>>> {
>>>> int ret;
>>>> struct device_node *np = NULL;
>>>> @@ -439,15 +426,9 @@ static int __init omap2_sync32k_clocksource_init(void)
>>>>
>>>> return ret;
>>>> }
>>>> -#else
>>>> -static inline int omap2_sync32k_clocksource_init(void)
>>>> -{
>>>> - return -ENODEV;
>>>> -}
>>>> -#endif
>>>>
>>>> -static void __init omap2_gptimer_clocksource_init(int gptimer_id,
>>>> - const char *fck_source)
>>>> +static void __init omap2_gp_clocksource_init(int gptimer_id,
>>>> + const char *fck_source)
>>>
>>> Nit, I personally prefer keeping gptimer, because gp just means
>>> "general-purpose" and does not imply a timer per-se.
>>
>> I've made this change, so we will not get something like:
>> omapx_gptimer_timer_init(), but this really does not meter to me,
>> so no problem will do for v2.
>
> Thanks.
>
>>>
>>>> {
>>>> int res;
>>>>
>>>> @@ -466,23 +447,10 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
>>>> gptimer_id, clksrc.rate);
>>>> }
>>>>
>>>> -static void __init omap2_clocksource_init(int gptimer_id,
>>>> - const char *fck_source)
>>>> +static void __init omap2_sync32k_clocksource_init(int gptimer_id,
>>>> + const char *fck_source)
>>>> {
>>>> - /*
>>>> - * First give preference to kernel parameter configuration
>>>> - * by user (clocksource="gp_timer").
>>>> - *
>>>> - * In case of missing kernel parameter for clocksource,
>>>> - * first check for availability for 32k-sync timer, in case
>>>> - * of failure in finding 32k_counter module or registering
>>>> - * it as clocksource, execution will fallback to gp-timer.
>>>> - */
>>>> - if (use_gptimer_clksrc == true)
>>>> - omap2_gptimer_clocksource_init(gptimer_id, fck_source);
>>>> - else if (omap2_sync32k_clocksource_init())
>>>> - /* Fall back to gp-timer code */
>>>> - omap2_gptimer_clocksource_init(gptimer_id, fck_source);
>>>> + __omap2_sync32k_clocksource_init();
>>>> }
>>>
>>> ... this just appears to be a wrapper function, but I don't see why this
>>> is needed? Do we need this wrapper?
>>
>> no, not really, just consider the explanation above.
>> I will remove the wrapper for v2.
>
> Ok, thanks.
>
>>>
>>>> #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
>>>> @@ -563,52 +531,64 @@ static inline void __init realtime_counter_init(void)
>>>> {}
>>>> #endif
>>>>
>>>> -#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
>>>> - clksrc_nr, clksrc_src) \
>>>> -static void __init omap##name##_timer_init(void) \
>>>> +#define OMAP_SYS_TIMER_INIT(n, clksrc_name, clkev_nr, clkev_src, \
>>>> + clkev_prop, clksrc_nr, clksrc_src) \
>>>> +static void __init omap##n##_##clksrc_name##_timer_init(void) \
>>>
>>>
>>>> { \
>>>> omap_dmtimer_init(); \
>>>> omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
>>>> - omap2_clocksource_init((clksrc_nr), clksrc_src); \
>>>> + \
>>>> + if (use_gptimer_clksrc) \
>>>> + omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
>>>> + else \
>>>> + omap2_##clksrc_name##_clocksource_init((clksrc_nr), \
>>>> + clksrc_src); \
>>>
>>> Something here seems a little odd. If "clksrc_name" is "gp", then the
>>> if-else parts will call the same function. Or am I missing something here?
>>
>> Yes, you are right - this is odd.
>> What do you think of:
>>
>> if (use_gptimer_clksrc) {
>> omap2_gp_clocksource_init((clksrc_nr), clksrc_src);
>> return;
>> }
>> omap2_##clksrc_name##_clocksource_init((clksrc_nr), clksrc_src);
>
> Yes, but it still seems a little odd that we could have ...
>
> if (use_gptimer_clksrc) {
> omap2_gp_clocksource_init((clksrc_nr), clksrc_src);
> return;
> }
> omap2_gp_clocksource_init((clksrc_nr), clksrc_src);
Yes, of course I understand your point, but that's how macro expansion work.
The only idea left in my mind is to move the check for use_gptimer_clksrc
to the omap2_sync32k_clocksource_init() function, but I don't like it, as
omap2_sync32k_clocksource_init() function should deal with the sync32k init
and if use_gptimer_clksrc is set, the function should not be called at all.
I really don't think this is a problem.
Do you have another idea how we can reuse the macro and
not have the above oddness?
>
>>>
>>> I think that I prefer how it works today where we call just
>>> omap2_clocksource_init(), and it determines whether to use the gptimer
>>> or the 32k-sync.
>>
>> There is no reliable way to determine which source should be used in runtime
>> for boards that do not have the 32k oscillator wired.
>
> Hmmm ... well for OMAP devices the 32kHz clock is mandatory AFAIK. At
> least for OMAP devices and I would need to check on the AM33xx but I
> would imagine they are the same. Which devices are you referring to
> where the 32kHz is optional?
As Paul already mentioned, AM35xx can work without the external 32kHz
oscillator.
>
>>> For OMAP I think that it is fine to default to the 32k-sync and then if
>>> the gptimer is selected, it uses the higher frequency sys_clk as the
>>> timer source.
>>
>> I agree for the 32k-sync as a default, but gptimer will not be selected
>> on SoC that have 32k while board does not have the 32k wired.
>
> Ok, again let me know which device(s) this applies too.
So we already have two devices: AM35xx and AM33xx, right?
>
>>>
>>> For AMxxx, devices, sync-32k does not exist, and so I understand it does
>>> not work the same.
>>>
>>> I am wondering if the use_gptimer_clksrc, should become
>>> use_sysclk_clksrc, and then ...
>>>
>>> For OMAP ...
>>> use_sysclk_clksrc = 0 --> use sync-32k (default)
>>> use_sysclk_clksrc = 1 --> use gptimer with sys_clk
>>>
>>> For AM33xx ...
>>> use_sysclk_clksrc = 0 --> use gptimer with 32khz clock (default)
>>> use_sysclk_clksrc = 1 --> use gptimer with sys_clk
>>
>> Well, this is more or less how it works today, but it does not consider
>> the board wiring information that after all defines which source should
>> be used. (Not all boards out there are clones of beagles and evms...)
>> And the generic code should be flexible enough
>> to enable any legal configuration.
>
> My whole thought here was that the 32kHz is always present. If that is
> not the case then I would agree this would not work.
We have also, another case where, you don't want to use the 32k as a source
and use sys_clk to have higher precision.
>
>>>
>>>> }
>>>>
>>>> -#define OMAP_SYS_TIMER(name) \
>>>> -struct sys_timer omap##name##_timer = { \
>>>> - .init = omap##name##_timer_init, \
>>>> -};
>>>> +#define OMAP_SYS_TIMER(n, clksrc) \
>>>> +struct sys_timer omap##n##_##clksrc##_timer = { \
>>>> + .init = omap##n##_##clksrc##_timer_init, \
>>>> +}
>>>>
>>>> #ifdef CONFIG_ARCH_OMAP2
>>>> -OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, "ti,timer-alwon",
>>>> - 2, OMAP2_MPU_SOURCE)
>>>> -OMAP_SYS_TIMER(2)
>>>> +OMAP_SYS_TIMER_INIT(2, sync32k, 1, OMAP2_32K_SOURCE, TIMER_PROP_ALWON,
>>>> + 2, OMAP2_MPU_SOURCE);
>>>> +OMAP_SYS_TIMER(2, sync32k);
>>>> +OMAP_SYS_TIMER_INIT(2, gp, 1, OMAP2_MPU_SOURCE, TIMER_PROP_ALWON,
>>>> + 2, OMAP2_MPU_SOURCE);
>>>> +OMAP_SYS_TIMER(2, gp);
>>>
>>> It would be good if we can avoid having two timer_init functions for
>>> each OMAP generation.
>>
>> Yes, but then we will not have the right description of the hardware
>> but IMHO workarounds on workarounds on...
>>
>> There are several clock sources - all can be used,
>> why not have them described and ready for use?
>
> Well we really want to simplify this code and so I was thinking that if
> a device has a 32k-sync timer AND there is a 32kHz source, then what's
> the point in having an option to use a gptimer with a 32kHz source for
> that device?
Hmmm, that how it is done currently (before my patch),
or do I miss something?
> I guess I don't see the benefit there, at least for OMAP2-5
> devices specifically.
Well, this allows certain hardware variants to work properly.
Isn't this a benefit?
--
Regards,
Igor.
^ permalink raw reply
* [PATCH] ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER
From: Igor Grinberg @ 2012-11-11 11:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509C050C.6010201@ti.com>
On 11/08/12 21:16, Jon Hunter wrote:
>
> On 11/08/2012 12:59 PM, Hiremath, Vaibhav wrote:
>> On Fri, Nov 09, 2012 at 00:24:23, Hunter, Jon wrote:
>>>
>>> On 11/08/2012 01:59 AM, Igor Grinberg wrote:
>>>
>>> [snip]
>>>
>>>> There is no reliable way to determine which source should be used in runtime
>>>> for boards that do not have the 32k oscillator wired.
>>>
>>> So thinking about this some more and given that we are moving away from
>>> board files, if a board does not provide a 32kHz clock source, then this
>>> should be reflected in the device-tree source file for that board.
>>> Hence, at boot time we should be able to determine if a 32kHz clock
>>> source can be used.
>>>
>>
>> Let me feed some more thoughts here :)
>>
>> The way it is being detected currently is based on timer idle status bit.
>> I am worried that, this is the only option we have.
>
> Why not use device-tree to indicate the presence of a 32k clock source?
> This seems like a board level configuration and so device-tree seems to
> be the perfect place for this IMO.
Well, that is what my commit message says...
--
Regards,
Igor.
^ permalink raw reply
* [PATCH] ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER
From: Igor Grinberg @ 2012-11-11 11:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509BFB4E.2090802@ti.com>
On 11/08/12 20:34, Jon Hunter wrote:
>
> On 11/08/2012 12:17 PM, Paul Walmsley wrote:
>> On Thu, 8 Nov 2012, Jon Hunter wrote:
>>
>>> On 11/08/2012 11:58 AM, Paul Walmsley wrote:
>>>> On Thu, 8 Nov 2012, Jon Hunter wrote:
>>>>
>>>>> Igor was mentioning a h/w scenario where the 32kHz source is not
>>>>> present. However, I am not sure which devices support this and is
>>>>> applicable too.
>>>>
>>>> Pretty sure Igor is referring to the AM3517/3505. This is very poorly
>>>> documented, but can be observed in the AM3517 TRM Rev B (SPRUGR0B) Figure
>>>> 4-23 "PRM Clock Generator" and the AM3517 DM Rev C (SPRS550C) Section 4
>>>> "Clock Specifications".
>>>
>>> But AFAICT, even in that h/w configuration the internal 32k
>>> oscillator will be used
>>
>> Just to clarify, there's no internal 32k oscillator used on the 3517/3505;
>> just a divider from the HF clock.
>
> Ah yes I see that now!
>
>>> and so the gptimer will still have a 32k clock source.
>>
>> That's a good question and you might want to check with Igor on that one,
>> the AM3517 TRM conflicts with the DM as to whether it's available to the
>> GPTIMER or not :-(
>
> Well the external 32k and internal divided down version go through the
> same mux and so that seems to imply either they are both available to
> the gptimer or neither is.
Yep, but the /800 do not get you the 32768...
and that makes the timer suck.
Of course this can be dealt with in the clock subsystem
(I remember Paul said that he will look into that), but it will take time.
Also, what about having the sys_clk instead of 32k for higher precision?
Is that possible already (without my patch)?
--
Regards,
Igor.
^ permalink raw reply
* [PATCH 03/11] m68k: set arch_gettimeoffset directly
From: Phil Blundell @ 2012-11-11 11:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352408516-21988-5-git-send-email-swarren@wwwdotorg.org>
On Thu, 2012-11-08 at 14:01 -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> remove m68k's mach_gettimeoffset function pointer, and instead directly
> set the arch_gettimeoffset function pointer. This requires multiplying
> all function results by 1000, since the removed m68k_gettimeoffset() did
> this. Also, s/unsigned long/u32/ just to make the function prototypes
> exactly match that of arch_gettimeoffset.
>
> Cc: Geert Uytterhoeven <geert@linux-m68k.org>
> Cc: Philip Blundell <philb@gnu.org>
Acked-by: Phil Blundell <philb@gnu.org>
> Cc: Joshua Thompson <funaho@jurai.org>
> Cc: Sam Creasey <sammy@sammy.net>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
^ permalink raw reply
* [PATCH] RFC: pinctrl: grab default handler with bus notifiers
From: Linus Walleij @ 2012-11-11 12:22 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This makes the pinctrl subsystem auto-grab the pinctrl handle and
set the "default" (PINCTRL_STATE_DEFAULT) state for every device
that is present on the platform or AMBA (PrimeCell) bus right
before probe. This will account for the lion's share of embedded
silicon devcies. The behaviour is achieved using bus notifiers
on the platform and AMBA (PrimeCell) busses.
A modification of the semantics for pinctrl_get() is also done:
previously if the pinctrl handle for a certain device was already
taken, the pinctrl core would return an error. Now, since the
core may have already default-grabbed the handle and set its
state to "default", if the handle was already taken, this will
be disregarded and the located, previously instanitated handle
will be returned to the caller.
This way all code in drivers explicitly requesting their pinctrl
handlers will still be functional, and drivers that want to
explicitly retrieve and switch their handles can still do that.
But if the desired functionality is just boilerplate of this
type in the probe() function:
struct pinctrl *p;
p = devm_pinctrl_get_select_default(&dev);
if (IS_ERR(p)) {
if (PTR_ERR(p) == -EPROBE_DEFER)
return -EPROBE_DEFER;
dev_warn(&dev, "no pinctrl handle\n");
}
The discussion began with the addition of such boilerplate
to the omap4 keypad driver:
http://marc.info/?l=linux-input&m=135091157719300&w=2
Notice that the patch disregards deferral as per above:
if the pin controller returns -EPROBE_DEFER, there is no
way to send that back to the device core using notifiers,
so in cases where the probe ordering is to be controlled,
drivers still need to add the above pin control handling
code. So this mechanism will basically be optimistic, and
to be really sure that you don't have a deferred probe
on your pins, you still need to explicitly request the
pins.
This patch alone does not solve the entire dilemma faced:
whether code should be distributed into the drivers or
if it should be centralized to e.g. a PM domain. But it
solves the immediate issue of the addition of boilerplate
to a lot of drivers that just want to grab the default
state. As mentioned, they can later explicitly retrieve
the handle and set different states, and this could as
well be done by e.g. PM domains as it is only related
to a certain struct device * pointer.
Another solution that was discussed was whether to move
the default pinctrl handle and state grab to the device
core as an optional field in struct device itself, but
I'd like to first propose this less intrusive mechanism.
CC: Felipe Balbi <balbi@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mitch Bradley <wmb@firmworks.com>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Rickard Andersson <rickard.andersson@stericsson.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Documentation/pinctrl.txt | 24 +++++++++++++++++--
drivers/pinctrl/core.c | 60 +++++++++++++++++++++++++++++++++++++++++++++--
2 files changed, 80 insertions(+), 4 deletions(-)
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index da40efb..b6c27b1 100644
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -972,6 +972,19 @@ pinmux core.
Pin control requests from drivers
=================================
+When a device driver is about to probe on the platform or AMBA (PrimeCell)
+bus, the pinctrl core will automatically attempt to issue
+pinctrl_get_select_default() on these devices using the bus notification
+mechanism. This way driver writers do not need to add any of the
+boilerplate code of the type found below. However when doing fine-grained
+state selection and not using the "default" state, you may have to do
+some device driver handling of the pinctrl handles and states.
+
+So if you just want to put the pins for a certain platform or AMBA device
+into the default state and be done with it, there is nothing you need to
+do besides providing the proper mapping table. The device core will take
+care of the rest.
+
Generally it is discouraged to let individual drivers get and enable pin
control. So if possible, handle the pin control in platform code or some other
place where you have access to all the affected struct device * pointers. In
@@ -1097,8 +1110,8 @@ situations that can be electrically unpleasant, you will certainly want to
mux in and bias pins in a certain way before the GPIO subsystems starts to
deal with them.
-The above can be hidden: using pinctrl hogs, the pin control driver may be
-setting up the config and muxing for the pins when it is probing,
+The above can be hidden: using device notifiers, the pinctrl core may be
+setting up the config and muxing for the pins when the device is probing,
nevertheless orthogonal to the GPIO subsystem.
But there are also situations where it makes sense for the GPIO subsystem
@@ -1144,6 +1157,13 @@ PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
This gives the exact same result as the above construction.
+This should not be used for any kind of device which is represented in
+the device model. For platform and AMBA (PrimeCell) devices, such as found
+in many SoC:s, the pinctrl core will listen to notifications from these
+buses and attempt to do pinctrl_get_select_default() for these devices
+right before their device drivers are probed, so hogging these will just
+make the model look strange.
+
Runtime pinmuxing
=================
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 71db586..bdb2300 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -26,6 +26,9 @@
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/machine.h>
+#include <linux/notifier.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
#include "core.h"
#include "devicetree.h"
#include "pinmux.h"
@@ -684,9 +687,16 @@ static struct pinctrl *pinctrl_get_locked(struct device *dev)
if (WARN_ON(!dev))
return ERR_PTR(-EINVAL);
+ /*
+ * See if somebody else (such as the pinctrl core, using the
+ * notifiers) has already obtained a handle to the pinctrl for
+ * this device. In that case, return another pointer to it.
+ */
p = find_pinctrl(dev);
- if (p != NULL)
- return ERR_PTR(-EBUSY);
+ if (p != NULL) {
+ dev_dbg(dev, "obtain a copy of previously claimed pinctrl\n");
+ return p;
+ }
return create_pinctrl(dev);
}
@@ -1026,6 +1036,52 @@ void pinctrl_unregister_map(struct pinctrl_map const *map)
}
}
+static int pinctrl_device_notify(struct notifier_block *nb,
+ unsigned long action, void *data)
+{
+ struct device *dev = data;
+ struct pinctrl *p;
+
+ switch (action) {
+ case BUS_NOTIFY_BIND_DRIVER:
+ /*
+ * Hog pins right before a driver is about to be bound to
+ * the device
+ */
+ p = devm_pinctrl_get_select_default(dev);
+ if (IS_ERR_OR_NULL(p)) {
+ dev_dbg(dev, "no pinctrl handle or default state\n");
+ return 0;
+ }
+ dev_dbg(dev, "pinctrl core obtained default pinctrl\n");
+ break;
+ case BUS_NOTIFY_UNBOUND_DRIVER:
+ break;
+ }
+
+ return 0;
+}
+
+static struct notifier_block pinctrl_device_nb = {
+ .notifier_call = pinctrl_device_notify,
+};
+
+static int __init pinctrl_notifiers_init(void)
+{
+ bus_register_notifier(&platform_bus_type, &pinctrl_device_nb);
+#ifdef CONFIG_ARM_AMBA
+ bus_register_notifier(&amba_bustype, &pinctrl_device_nb);
+#endif
+ return 0;
+}
+
+/*
+ * The AMBA bus registers in the postcore_initcall() so we need to
+ * register our notifiers right after that so we can fetch pins for
+ * e.g. TTY drivers that will be registered in the arch_initcall() next.
+ */
+postcore_initcall_sync(pinctrl_notifiers_init);
+
#ifdef CONFIG_DEBUG_FS
static int pinctrl_pins_show(struct seq_file *s, void *what)
--
1.7.11.3
^ permalink raw reply related
* [PATCHv2] Input: omap4-keypad: Add pinctrl support
From: Linus Walleij @ 2012-11-11 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdawAdbwackZeST4iDkFZx9-exhTVoUzAABaWr1G89tATg@mail.gmail.com>
On Thu, Nov 1, 2012 at 3:01 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Thu, Nov 1, 2012 at 1:07 PM, Mark Brown
> <broonie@opensource.wolfsonmicro.com> wrote:
>> On Thu, Nov 01, 2012 at 09:54:00AM +0100, Linus Walleij wrote:
>
>> For the pin hogging I'd actually been thinking separately that we should
>> just have the device core do a devm_pinctrl_get_set_default() prior to
>> probing the device and store the result in the struct device. That
>> would immediately remove almost all of the current pinctrl users, users
>> that do need to do things with the data or check the result can then
>> pick up the pinctrl pointer from the device struct.
>
> I never thought of that. This sounds like it would work.
So I've looked closer at this.
> And the good thing is that this is a clean cut so we
> will centralized code without having to decide right now
> how to handle the pm idle/sleep cases.
>
> Talking here with Kevin Hilman on my left and Grant
> Likely on my right (they're physically here) there is some
> worry about stashing stuff into struct device.
>
> What if I retrieve this in the pinctrl subsystem using
> bus notifiers and then expose the struct pinctrl * to
> the clients by using pinctrl_get() and when you get
> such a handle in your probe() you know that the
> pinctrl subsystem has already fetched the handle and
> set it to "default" at that point?
I have sent out an RFC for this approach. It actually
works quite well on the U300 for example.
However as stated in the patch we run into another
problem: what if the pinctrl provider returns
-EDEFER_PROBE?
(The same will be true for clocks, regulators etc I
guess...)
If I use notifiers like this, I cannot return -EPROBE_DEFER
to the core. :-(
The PM domains seem to be built on the notification
mechanism as well (AFAICT), so it will not allow drivers to
defer their probes, as it is an optional layer after all.
As a matter of fact it seems that there is an implicit
assumption in PM domains that the resources that
are taken there cannot defer any probing, so they are
assumed to always be present. Is this correct?
If so, any resources that may be deferred (such as
pinctrl) can never be handled in PM domains. Only
simple stuff that the SoC controls directly e.g through
some fixed register pokes to voltage domains.
So then the only option that remains to centralize
pinctrl handling is indeed to do that in the device core,
before probe(). I need to know Greg's feelings about that.
At the same time this sort of give me the feeling that
we might be doing something wrong. The distributed
nature of deferred probes will become quite elusive
if the deferral request comes from some place
before probe() is even called on the driver.
Please check my RFC patch and tell me above errors
in the above reasoning....
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] Add support for generic BCM SoC chipsets
From: Christian Daudt @ 2012-11-11 13:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509C7771.9020400@wwwdotorg.org>
On 12-11-08 07:24 PM, Stephen Warren wrote:
> On 11/08/2012 09:13 AM, Christian Daudt wrote:
>> In order to start upstreaming Broadcom SoC support, create
>> a starting hierarchy, arch and dts files.
>> The first support SoC family that is planned is the
>> BCM281XX (BCM28145/28150/28155) family of dual A9 mobile SoC cores
>> This code is just the skeleton code for get the machine upstreamed. It
>> has been made MULTIPLATFORM compatible.
> Christian,
>
> Is the intent for this to support other BCM SoCs in the future, such as
> the bcm2835 in the Raspberry Pi, and the mach-bcm476x which Domenico
> Andreoli recently sent patches for? It'd be awesome if Broadcom could
> provide MMC and USB drivers for the bcm2835 for example.
Yes and no :) The intent is to support other BCM SoCs in the future, but
Broadcom has a fair number of ARM based SoCs. My primary focus is on the
ones from my group within Broadcom (mobile SoCs), but the plan is to
bring in others as feasible, and collaborate with other upstreaming work
being done for BCM SoCs.
As for bcm2835 MMC and USB, we will be upstreaming MMC and USB
bcm281xx as part of this effort and while I haven't checked the bcm2835
guts (it comes from a different team within Broadcom) I suspect it might
share the same IP blocks, which would make it fairly easy to extend our
work to add 2835 support. Stay tuned !
>> arch/arm/boot/dts/capri-brt.dts | 32 +++++++++++
>> arch/arm/boot/dts/capri.dtsi | 50 +++++++++++++++++
> What does the name "capri" refer to? I assume it's a code-name for the
> SoC/series. My inclination is that naming those files bcm28145.dtsi and
> bcm28145-brt.dts (or 28150/28155 as appropriate) might be a little more
> obvious to people unfamiliar with the code-names.
Yes, capri is a code name. I've gone back and forth on this one. I think
I'll change it to bcm281xx.dtsi and bcm28160-brt.dts, which then refers
to the family for the dtsi and the specific chip for the dts.
>> diff --git a/arch/arm/boot/dts/capri-brt.dts b/arch/arm/boot/dts/capri-brt.dts
>> +/ {
>> + model = "Capri BRT board";
>> + compatible = "bcm,capri";
> The individual board file's compatible property should contain both a
> board-specific value and the generic SoC value. This allows the SoC
> support in the kernel to match on the generic SoC compatible value, yet
> still allow the kernel to match the board-specific value in case any
> quirks are required. For example,
>
> compatible = "bcm,brt", "bcm,capri";
>
> (assuming that "brt" is the full board name)
I will change this based on the above convention i.e.:
compatible = "bcm, bcm28160-brt", "bcm, bcm281xx";
>> + interrupt-parent =<&gic>;
> That's already in capri.dtsi; there's no advantage to repeating it.
ok, removed.
>> + memory {
>> + device_type = "memory";
> That property already exists in skeleton.dtsi, which is included via
> capri.dtsi.
ok, removed.
>> diff --git a/arch/arm/boot/dts/capri.dtsi b/arch/arm/boot/dts/capri.dtsi
>> + gic: interrupt-controller at 3ff00100 {
>> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
> The commit description says it's an A9 not an A15.
changed.
>> + uart at 3e000000 {
>> + compatible = "snps,dw-apb-uart";
> You probably want to include SoC-specific compatible values for all the
> IP blocks too.
I don't follow this part. Do you mean to replace that line with
something like 'compatible = "snps,sw-apb-uart", "bcm, bcm28x11-uart"' ?
If so, I don't think that that is necessary - right now there is nothing
BCM specific about this.
> There need to be device tree bindings written to describe to contents of
> all these device-tree files; see Documentation/devicetree/bindings/.
Added a bcm281xx description.
>> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
>> +config ARCH_BCM
>> + bool "Broadcom SoC" if ARCH_MULTI_V7
>> + depends on MMU
>> + select CPU_V7
>> + select ARM_GIC
>> + select GENERIC_GPIO
>> + select GPIO_BCM
>> + select ARCH_REQUIRE_GPIOLIB
>> + select GENERIC_TIME
>> + select GENERIC_CLOCKEVENTS
>> + select TICK_ONESHOT
>> + select ARM_ERRATA_754322
>> + select ARM_ERRATA_764369 if SMP
>> + select SPARSE_IRQ
> Those select statements should be alphabetically sorted.
done
>> diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c
>> +
>> +
>> +
>> +
>> +
> Nit: A couple of instances of multiple newlines, but not a big deal.
>
done.
thanks,
csd
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* [PATCH RFT 1/2] pinctrl: dove: Fix dove_audio1_ctrl_set when BIT(0|1|2|3) of config is clear
From: Axel Lin @ 2012-11-11 13:44 UTC (permalink / raw)
To: linux-arm-kernel
Current implementation in dove_audio1_ctrl_set() does not clear corresponding
register bit if BIT(0|1|2|3) of config is clear. Fix it.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
---
Hi,
I don't have this hardware.
I'd appreciate if someone can review and test this patch.
This resend also CC Sebastian Hesselbarth and linux-arm-kernel.
Thanks,
Axel
drivers/pinctrl/mvebu/pinctrl-dove.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c
index ffe74b2..e5cc694 100644
--- a/drivers/pinctrl/mvebu/pinctrl-dove.c
+++ b/drivers/pinctrl/mvebu/pinctrl-dove.c
@@ -236,12 +236,23 @@ static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
if (config & BIT(0))
gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
+ else
+ gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO;
+
if (config & BIT(1))
gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
+ else
+ gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN;
+
if (config & BIT(2))
sspc1 |= DOVE_SSP_ON_AU1;
+ else
+ sspc1 &= ~DOVE_SSP_ON_AU1;
+
if (config & BIT(3))
mpp4 |= DOVE_AU1_GPIO_SEL;
+ else
+ mpp4 &= ~DOVE_AU1_GPIO_SEL;
writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
writel(sspc1, DOVE_SSP_CTRL_STATUS_1);
--
1.7.9.5
^ permalink raw reply related
* [PATCH RFT 2/2] pinctrl: dove: Checking valid config in dove_audio1_ctrl_set
From: Axel Lin @ 2012-11-11 13:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352641495.3113.1.camel@phoenix>
Move the code checking valid config to dove_audio1_ctrl_set(), this ensures we
always set valid config. And then dove_audio1_ctrl_get() always returns correct
config.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
---
drivers/pinctrl/mvebu/pinctrl-dove.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c
index e5cc694..a393790 100644
--- a/drivers/pinctrl/mvebu/pinctrl-dove.c
+++ b/drivers/pinctrl/mvebu/pinctrl-dove.c
@@ -217,12 +217,6 @@ static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
*config |= BIT(0);
- /* SSP/TWSI only if I2S1 not set*/
- if ((*config & BIT(3)) == 0)
- *config &= ~(BIT(2) | BIT(0));
- /* TWSI only if SPDIFO not set*/
- if ((*config & BIT(1)) == 0)
- *config &= ~BIT(0);
return 0;
}
@@ -234,6 +228,13 @@ static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+ /* SSP/TWSI only if I2S1 not set*/
+ if ((config & BIT(3)) == 0)
+ config &= ~(BIT(2) | BIT(0));
+ /* TWSI only if SPDIFO not set*/
+ if ((config & BIT(1)) == 0)
+ config &= ~BIT(0);
+
if (config & BIT(0))
gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
else
--
1.7.9.5
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