* [PATCH] ARM: add get_user() support for 8 byte types
From: Will Deacon @ 2012-11-12 10:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352495853-9790-1-git-send-email-rob.clark@linaro.org>
On Fri, Nov 09, 2012 at 09:17:33PM +0000, Rob Clark wrote:
> From: Rob Clark <rob@ti.com>
>
> A new atomic modeset/pageflip ioctl being developed in DRM requires
> get_user() to work for 64bit types (in addition to just put_user()).
>
> Signed-off-by: Rob Clark <rob@ti.com>
> ---
> arch/arm/include/asm/uaccess.h | 25 ++++++++++++++++++++-----
> arch/arm/lib/getuser.S | 17 ++++++++++++++++-
> 2 files changed, 36 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
> index 7e1f760..2e3fdb2 100644
> --- a/arch/arm/include/asm/uaccess.h
> +++ b/arch/arm/include/asm/uaccess.h
> @@ -100,6 +100,7 @@ static inline void set_fs(mm_segment_t fs)
> extern int __get_user_1(void *);
> extern int __get_user_2(void *);
> extern int __get_user_4(void *);
> +extern int __get_user_8(void *);
>
> #define __GUP_CLOBBER_1 "lr", "cc"
> #ifdef CONFIG_CPU_USE_DOMAINS
> @@ -108,6 +109,7 @@ extern int __get_user_4(void *);
> #define __GUP_CLOBBER_2 "lr", "cc"
> #endif
> #define __GUP_CLOBBER_4 "lr", "cc"
> +#define __GUP_CLOBBER_8 "lr", "cc"
>
> #define __get_user_x(__r2,__p,__e,__l,__s) \
> __asm__ __volatile__ ( \
> @@ -122,22 +124,35 @@ extern int __get_user_4(void *);
> ({ \
> unsigned long __limit = current_thread_info()->addr_limit - 1; \
> register const typeof(*(p)) __user *__p asm("r0") = (p);\
> - register unsigned long __r2 asm("r2"); \
> register unsigned long __l asm("r1") = __limit; \
> register int __e asm("r0"); \
> switch (sizeof(*(__p))) { \
> - case 1: \
> + case 1: { \
> + register unsigned long __r2 asm("r2"); \
> __get_user_x(__r2, __p, __e, __l, 1); \
> + x = (typeof(*(p))) __r2; \
> break; \
> - case 2: \
> + } \
> + case 2: { \
> + register unsigned long __r2 asm("r2"); \
> __get_user_x(__r2, __p, __e, __l, 2); \
> + x = (typeof(*(p))) __r2; \
> break; \
> - case 4: \
> + } \
> + case 4: { \
> + register unsigned long __r2 asm("r2"); \
> __get_user_x(__r2, __p, __e, __l, 4); \
> + x = (typeof(*(p))) __r2; \
> + break; \
> + } \
> + case 8: { \
> + register unsigned long long __r2 asm("r2"); \
Does this matter? For EABI, we'll pass in (r2, r3) and it's all handcrafted
asm, so the compiler shouldn't care much. For OABI, I think you may have to
do some more work to get the two words where you want them.
> + __get_user_x(__r2, __p, __e, __l, 8); \
> + x = (typeof(*(p))) __r2; \
> break; \
> + } \
> default: __e = __get_user_bad(); break; \
> } \
> - x = (typeof(*(p))) __r2; \
> __e; \
> })
>
> diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
> index 9b06bb4..d05285c 100644
> --- a/arch/arm/lib/getuser.S
> +++ b/arch/arm/lib/getuser.S
> @@ -18,7 +18,7 @@
> * Inputs: r0 contains the address
> * r1 contains the address limit, which must be preserved
> * Outputs: r0 is the error code
> - * r2 contains the zero-extended value
> + * r2, r3 contains the zero-extended value
> * lr corrupted
> *
> * No other registers must be altered. (see <asm/uaccess.h>
> @@ -66,6 +66,19 @@ ENTRY(__get_user_4)
> mov pc, lr
> ENDPROC(__get_user_4)
>
> +ENTRY(__get_user_8)
> + check_uaccess r0, 4, r1, r2, __get_user_bad
Shouldn't you be passing 8 here, so that we validate the correct range?
> +#ifdef CONFIG_THUMB2_KERNEL
> +5: TUSER(ldr) r2, [r0]
> +6: TUSER(ldr) r3, [r0, #4]
> +#else
> +5: TUSER(ldr) r2, [r0], #4
> +6: TUSER(ldr) r3, [r0]
> +#endif
This doesn't work for EABI big-endian systems.
Will
^ permalink raw reply
* [PATCH 02/11] time: convert arch_gettimeoffset to a pointer
From: Jesper Nilsson @ 2012-11-12 10:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352408516-21988-4-git-send-email-swarren@wwwdotorg.org>
On Thu, Nov 08, 2012 at 10:01:47PM +0100, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Currently, whenever CONFIG_ARCH_USES_GETTIMEOFFSET is enabled, each
> arch core provides a single implementation of arch_gettimeoffset(). In
> many cases, different sub-architectures, different machines, or
> different timer providers exist, and so the arch ends up implementing
> arch_gettimeoffset() as a call-through-pointer anyway. Examples are
> ARM, Cris, M68K, and it's arguable that the remaining architectures,
> M32R and Blackfin, should be doing this anyway.
>
> Modify arch_gettimeoffset so that it itself is a function pointer, which
> the arch initializes. This will allow later changes to move the
> initialization of this function into individual machine support or timer
> drivers. This is particularly useful for code in drivers/clocksource
> which should rely on an arch-independant mechanism to register their
> implementation of arch_gettimeoffset().
>
> This patch also converts the Cris architecture to set arch_gettimeoffset
> directly to the final implementation in time_init(), because Cris already
> had separate time_init() functions per sub-architecture. M68K and ARM
> are converted to set arch_gettimeoffset the final implementation in later
> patches, because they already have function pointers in place for this
> purpose.
>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Mike Frysinger <vapier@gentoo.org>
> Cc: Mikael Starvik <starvik@axis.com>
For the cris parts:
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
> Cc: Hirokazu Takata <takata@linux-m32r.org>
> Cc: Geert Uytterhoeven <geert@linux-m68k.org>
> Cc: John Stultz <johnstul@us.ibm.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> arch/arm/kernel/time.c | 6 +++++-
> arch/blackfin/kernel/time.c | 6 +++++-
> arch/cris/arch-v10/kernel/time.c | 6 ++++--
> arch/cris/kernel/time.c | 11 -----------
> arch/m32r/kernel/time.c | 4 +++-
> arch/m68k/kernel/time.c | 16 ++++++++++------
> include/linux/time.h | 4 +---
> kernel/time/timekeeping.c | 20 +++++++++++++++++---
> 8 files changed, 45 insertions(+), 28 deletions(-)
>
> diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
> index 09be0c3..b0190b4 100644
> --- a/arch/arm/kernel/time.c
> +++ b/arch/arm/kernel/time.c
> @@ -70,7 +70,7 @@ EXPORT_SYMBOL(profile_pc);
> #endif
>
> #ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
> -u32 arch_gettimeoffset(void)
> +static u32 arm_gettimeoffset(void)
> {
> if (system_timer->offset != NULL)
> return system_timer->offset() * 1000;
> @@ -164,6 +164,10 @@ device_initcall(timer_init_syscore_ops);
>
> void __init time_init(void)
> {
> +#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
> + arch_gettimeoffset = arm_gettimeoffset;
> +#endif
> +
> system_timer = machine_desc->timer;
> system_timer->init();
> sched_clock_postinit();
> diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
> index 2310b24..3126b92 100644
> --- a/arch/blackfin/kernel/time.c
> +++ b/arch/blackfin/kernel/time.c
> @@ -85,7 +85,7 @@ time_sched_init(irqreturn_t(*timer_routine) (int, void *))
> /*
> * Should return useconds since last timer tick
> */
> -u32 arch_gettimeoffset(void)
> +static u32 blackfin_gettimeoffset(void)
> {
> unsigned long offset;
> unsigned long clocks_per_jiffy;
> @@ -141,6 +141,10 @@ void read_persistent_clock(struct timespec *ts)
>
> void __init time_init(void)
> {
> +#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
> + arch_gettimeoffset = blackfin_gettimeoffset;
> +#endif
> +
> #ifdef CONFIG_RTC_DRV_BFIN
> /* [#2663] hack to filter junk RTC values that would cause
> * userspace to have to deal with time values greater than
> diff --git a/arch/cris/arch-v10/kernel/time.c b/arch/cris/arch-v10/kernel/time.c
> index 162892f..fce7c54 100644
> --- a/arch/cris/arch-v10/kernel/time.c
> +++ b/arch/cris/arch-v10/kernel/time.c
> @@ -55,9 +55,9 @@ unsigned long get_ns_in_jiffie(void)
> return ns;
> }
>
> -unsigned long do_slow_gettimeoffset(void)
> +static u32 cris_v10_gettimeoffset(void)
> {
> - unsigned long count;
> + u32 count;
>
> /* The timer interrupt comes from Etrax timer 0. In order to get
> * better precision, we check the current value. It might have
> @@ -191,6 +191,8 @@ static struct irqaction irq2 = {
> void __init
> time_init(void)
> {
> + arch_gettimeoffset = cris_v10_gettimeoffset;
> +
> /* probe for the RTC and read it if it exists
> * Before the RTC can be probed the loops_per_usec variable needs
> * to be initialized to make usleep work. A better value for
> diff --git a/arch/cris/kernel/time.c b/arch/cris/kernel/time.c
> index b063c92..fe6acda 100644
> --- a/arch/cris/kernel/time.c
> +++ b/arch/cris/kernel/time.c
> @@ -39,17 +39,6 @@
> extern unsigned long loops_per_jiffy; /* init/main.c */
> unsigned long loops_per_usec;
>
> -
> -#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
> -extern unsigned long do_slow_gettimeoffset(void);
> -static unsigned long (*do_gettimeoffset)(void) = do_slow_gettimeoffset;
> -
> -u32 arch_gettimeoffset(void)
> -{
> - return do_gettimeoffset();
> -}
> -#endif
> -
> int set_rtc_mmss(unsigned long nowtime)
> {
> D(printk(KERN_DEBUG "set_rtc_mmss(%lu)\n", nowtime));
> diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c
> index 84dd040..1a15f81 100644
> --- a/arch/m32r/kernel/time.c
> +++ b/arch/m32r/kernel/time.c
> @@ -57,7 +57,7 @@ extern void smp_local_timer_interrupt(void);
>
> static unsigned long latch;
>
> -u32 arch_gettimeoffset(void)
> +static u32 m32r_gettimeoffset(void)
> {
> unsigned long elapsed_time = 0; /* [us] */
>
> @@ -165,6 +165,8 @@ void read_persistent_clock(struct timespec *ts)
>
> void __init time_init(void)
> {
> + arch_gettimeoffset = m32r_gettimeoffset;
> +
> #if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \
> || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \
> || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
> diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c
> index 5d0bcaa..c2994c8 100644
> --- a/arch/m68k/kernel/time.c
> +++ b/arch/m68k/kernel/time.c
> @@ -80,14 +80,9 @@ void read_persistent_clock(struct timespec *ts)
> }
> }
>
> -void __init time_init(void)
> -{
> - mach_sched_init(timer_interrupt);
> -}
> -
> #ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
>
> -u32 arch_gettimeoffset(void)
> +static u32 m68k_gettimeoffset(void)
> {
> return mach_gettimeoffset() * 1000;
> }
> @@ -106,3 +101,12 @@ static int __init rtc_init(void)
> module_init(rtc_init);
>
> #endif /* CONFIG_ARCH_USES_GETTIMEOFFSET */
> +
> +void __init time_init(void)
> +{
> +#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
> + arch_gettimeoffset = m68k_gettimeoffset;
> +#endif
> +
> + mach_sched_init(timer_interrupt);
> +}
> diff --git a/include/linux/time.h b/include/linux/time.h
> index 4d358e9..05e32a7 100644
> --- a/include/linux/time.h
> +++ b/include/linux/time.h
> @@ -142,9 +142,7 @@ void timekeeping_inject_sleeptime(struct timespec *delta);
> * finer then tick granular time.
> */
> #ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
> -extern u32 arch_gettimeoffset(void);
> -#else
> -static inline u32 arch_gettimeoffset(void) { return 0; }
> +extern u32 (*arch_gettimeoffset)(void);
> #endif
>
> extern void do_gettimeofday(struct timeval *tv);
> diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c
> index e424970..9d00ace 100644
> --- a/kernel/time/timekeeping.c
> +++ b/kernel/time/timekeeping.c
> @@ -140,6 +140,20 @@ static void tk_setup_internals(struct timekeeper *tk, struct clocksource *clock)
> }
>
> /* Timekeeper helper functions. */
> +
> +#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
> +u32 (*arch_gettimeoffset)(void);
> +
> +u32 gettimeoffset(void)
> +{
> + if (likely(arch_gettimeoffset))
> + return arch_gettimeoffset();
> + return 0;
> +}
> +#else
> +static inline u32 gettimeoffset(void) { return 0; }
> +#endif
> +
> static inline s64 timekeeping_get_ns(struct timekeeper *tk)
> {
> cycle_t cycle_now, cycle_delta;
> @@ -157,7 +171,7 @@ static inline s64 timekeeping_get_ns(struct timekeeper *tk)
> nsec >>= tk->shift;
>
> /* If arch requires, add in gettimeoffset() */
> - return nsec + arch_gettimeoffset();
> + return nsec + gettimeoffset();
> }
>
> static inline s64 timekeeping_get_ns_raw(struct timekeeper *tk)
> @@ -177,7 +191,7 @@ static inline s64 timekeeping_get_ns_raw(struct timekeeper *tk)
> nsec = clocksource_cyc2ns(cycle_delta, clock->mult, clock->shift);
>
> /* If arch requires, add in gettimeoffset() */
> - return nsec + arch_gettimeoffset();
> + return nsec + gettimeoffset();
> }
>
> /* must hold write on timekeeper.lock */
> @@ -211,7 +225,7 @@ static void timekeeping_forward_now(struct timekeeper *tk)
> tk->xtime_nsec += cycle_delta * tk->mult;
>
> /* If arch requires, add in gettimeoffset() */
> - tk->xtime_nsec += (u64)arch_gettimeoffset() << tk->shift;
> + tk->xtime_nsec += (u64)gettimeoffset() << tk->shift;
>
> tk_normalize_xtime(tk);
>
> --
> 1.7.0.4
/^JN - Jesper Nilsson
--
Jesper Nilsson -- jesper.nilsson at axis.com
^ permalink raw reply
* [PATCH 12/11] ARM: OMAP: Fix relative includes for fpga.h
From: Benoit Cousson @ 2012-11-12 10:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121031215252.GB15766@atomide.com>
Hi Tony,
After rebasing on top of your omap-for-v3.8/tmp-merge, I realized that this patch is generating a build break due to removal of the fpga.h include from debug-leds.c.
arch/arm/plat-omap/debug-leds.c: In function 'fpga_probe':
arch/arm/plat-omap/debug-leds.c:114:9: error: 'H2P2_DBG_FPGA_SIZE' undeclared (first use in this function)
arch/arm/plat-omap/debug-leds.c:114:9: note: each undeclared identifier is reported only once for each function it appears in
It does not appear with the omap2plus_config but will appear if you enable the NEW_LEDS support that enable OMAP_DEBUG_LEDS.
I'm not sure why the size is still hard coded. In theory, assuming the resource is properly initialized, resource_size should be usable.
The patch below is fixing that.
Regards,
Benoit
---
>From 81e1c3dddd1cd78b1f5a04983cf920b287764f11 Mon Sep 17 00:00:00 2001
From: Benoit Cousson <b-cousson@ti.com>
Date: Mon, 12 Nov 2012 11:44:03 +0100
Subject: [PATCH] ARM: OMAP: debug-leds: Use resource_size instead of hard coded macro
The debug-leds driver should not rely on hard coded macro for
the iomem size but use the resource size instead.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
---
arch/arm/plat-omap/debug-leds.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index c43ea21..aa7ebc6 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -111,7 +111,7 @@ static int fpga_probe(struct platform_device *pdev)
if (!iomem)
return -ENODEV;
- fpga = ioremap(iomem->start, H2P2_DBG_FPGA_SIZE);
+ fpga = ioremap(iomem->start, resource_size(iomem));
__raw_writew(0xff, &fpga->leds);
for (i = 0; i < ARRAY_SIZE(dbg_leds); i++) {
--
1.7.0.4
^ permalink raw reply related
* [PATCH] Set bit 22 in the PL310 (cache controller) AuxCtlr register
From: Will Deacon @ 2012-11-12 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121112064547.GN32313@localhost.localdomain>
On Mon, Nov 12, 2012 at 06:45:47AM +0000, Shiraz Hashim wrote:
> On Fri, Nov 09, 2012 at 09:54:01AM +0000, Will Deacon wrote:
> > On Fri, Nov 09, 2012 at 04:01:52AM +0000, Shiraz Hashim wrote:
> > > From: Catalin Marinas <catalin.marinas@arm.com>
> > >
> > > Clearing bit 22 in the PL310 Auxiliary Control register (shared
> > > attribute override enable) has the side effect of transforming Normal
> > > Shared Non-cacheable reads into Cacheable no-allocate reads.
> > >
> > > Coherent DMA buffers in Linux always have a Cacheable alias via the
> > > kernel linear mapping and the processor can speculatively load cache
> > > lines into the PL310 controller. With bit 22 cleared, Non-cacheable
> > > reads would unexpectedly hit such cache lines leading to buffer
> > > corruption.
> >
> > Is this still the case with recent kernels? I thought the dma-mapping/cma
> > work avoided the cacheable alias, but perhaps I'm mistaken.
>
> I haven't used CMA but DMA mappings are still normal memory
> non-cacheable.
Ok, so trawling through the list reveals we only have this issue for normal
DMA mappings and not with CMA:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-October/124276.html
I wonder whether we shouldn't just fix that, rather than work around it with
a PL310-specific hack?
Will
^ permalink raw reply
* [PATCH 05/10] arn: at91: move at91_tc.h to arch/arm/mach-at91
From: Nicolas Ferre @ 2012-11-12 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352287374-25176-5-git-send-email-plagnioj@jcrosoft.com>
Hi,
Beware: subject has typo: s/arn/ARM/
Also, care about capital letters for "ARM" => to all patches of the series.
Bye,
On 11/07/2012 12:22 PM, Jean-Christophe PLAGNIOL-VILLARD :
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> arch/arm/mach-at91/{include/mach => }/at91_tc.h | 0
> arch/arm/mach-at91/at91x40_time.c | 3 ++-
> 2 files changed, 2 insertions(+), 1 deletion(-)
> rename arch/arm/mach-at91/{include/mach => }/at91_tc.h (100%)
>
> diff --git a/arch/arm/mach-at91/include/mach/at91_tc.h b/arch/arm/mach-at91/at91_tc.h
> similarity index 100%
> rename from arch/arm/mach-at91/include/mach/at91_tc.h
> rename to arch/arm/mach-at91/at91_tc.h
> diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
> index ee06d7b..0e57e44 100644
> --- a/arch/arm/mach-at91/at91x40_time.c
> +++ b/arch/arm/mach-at91/at91x40_time.c
> @@ -26,7 +26,8 @@
> #include <linux/io.h>
> #include <mach/hardware.h>
> #include <asm/mach/time.h>
> -#include <mach/at91_tc.h>
> +
> +#include "at91_tc.h"
>
> #define at91_tc_read(field) \
> __raw_readl(AT91_IO_P2V(AT91_TC) + field)
>
--
Nicolas Ferre
^ permalink raw reply
* [PATCH] ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER
From: Benoit Cousson @ 2012-11-12 11:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EB71352@DBDE01.ent.ti.com>
Hi Vaibhav,
On 11/12/2012 11:38 AM, Hiremath, Vaibhav wrote:
> On Fri, Nov 09, 2012 at 00:46:28, Hunter, Jon wrote:
>>
>> On 11/08/2012 12:59 PM, Hiremath, Vaibhav wrote:
>>> On Fri, Nov 09, 2012 at 00:24:23, Hunter, Jon wrote:
>>>>
>>>> On 11/08/2012 01:59 AM, Igor Grinberg wrote:
>>>>
>>>> [snip]
>>>>
>>>>> There is no reliable way to determine which source should be used in runtime
>>>>> for boards that do not have the 32k oscillator wired.
>>>>
>>>> So thinking about this some more and given that we are moving away from
>>>> board files, if a board does not provide a 32kHz clock source, then this
>>>> should be reflected in the device-tree source file for that board.
>>>> Hence, at boot time we should be able to determine if a 32kHz clock
>>>> source can be used.
>>>>
>>>
>>> Let me feed some more thoughts here :)
>>>
>>> The way it is being detected currently is based on timer idle status bit.
>>> I am worried that, this is the only option we have.
>>
>> Why not use device-tree to indicate the presence of a 32k clock source?
>> This seems like a board level configuration and so device-tree seems to
>> be the perfect place for this IMO.
>>
>
> I think I agree with you, but for this to happen in clean way, its time to
> start populating clock-nodes in DT, don't you think? Something like,
>
>
> clocks {
> rtc_clk: clk at X {
> compatible = "crystal-32k, per-32k, xyz";
> clock-frequency = <32768>;
> };
> ...
> };
>
> Timer {
>
> ref-clock = <&rtc_clk>;
> };
>
> What do you think?
That's indeed the proper way to do it, since this is a pure board level
parameter and we do have the binding to express that.
We just have to add that in the DTS:-)
Regards,
Benoit
^ permalink raw reply
* [PATCH] mm: dmapool: use provided gfp flags for all dma_alloc_coherent() calls
From: Soeren Moch @ 2012-11-12 11:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121112103820.GX22029@lunn.ch>
On 12.11.2012 11:38, Andrew Lunn wrote:
> On Mon, Nov 12, 2012 at 10:48:02AM +0100, Soeren Moch wrote:
>> On 11.11.2012 18:22, Andrew Lunn wrote:
>>> On Thu, Nov 08, 2012 at 07:38:57AM +0100, Marek Szyprowski wrote:
>>>> dmapool always calls dma_alloc_coherent() with GFP_ATOMIC flag,
>> regardless
>>>> the flags provided by the caller. This causes excessive pruning of
>>>> emergency memory pools without any good reason. This patch
>> changes the code
>>>> to correctly use gfp flags provided by the dmapool caller. This should
>>>> solve the dmapool usage on ARM architecture, where GFP_ATOMIC DMA
>>>> allocations can be served only from the special, very limited
>> memory pool.
>>>> Reported-by: Soren Moch <smoch@web.de>
>> Please use
>> Reported-by: Soeren Moch <smoch@web.de>
>>
>>>> Reported-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>> Tested-by: Andrew Lunn <andrew@lunn.ch>
>>>
>>> I tested this on a Kirkwood QNAP after removing the call to
>>> init_dma_coherent_pool_size().
>>>
>>> Andrew
>> Tested-by: Soeren Moch <smoch@web.de>
>>
>> Now I had a chance to test this patch on my Kirkwood guruplug
>> system with linux-3.6.6 . It is running much better now, but with the
>> original 256K coherent pool size I still see errors after several hours
>> of runtime:
>>
>> Nov 12 09:42:32 guru kernel: ERROR: 256 KiB atomic DMA coherent pool
>> is too small!
>> Nov 12 09:42:32 guru kernel: Please increase it with coherent_pool=
>> kernel parameter!
> Hi Soeren
>
> Could you tell us what DVB devices you are using.
>
> Thanks
> Andrew
from lsusb:
Bus 001 Device 005: ID 0ccd:00b2 TerraTec Electronic GmbH
Bus 001 Device 006: ID 2040:5200 Hauppauge
Bus 001 Device 009: ID 2304:0242 Pinnacle Systems, Inc.
If you want to check the drivers, I recommend to start with "em28xx".
Regards,
Soeren
^ permalink raw reply
* [PATCH] i.MX25 devicetree support
From: Sascha Hauer @ 2012-11-12 11:21 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
The following is another round of patches adding i.MX25 devicetree
support. Since the clock numbers are exported to the devicetree I
added a patch to add the missing clock gates to this series, so that
we have to expect less changes (or better additions) to the clock
bindings later. This series is based on and tested with the Ka-Ro
TX25 board for which support is also included in this series.
Sascha
The following changes since commit 53640f41b97792b0889bb70f26f99c06743162a1:
Merge remote-tracking branch 'arm-soc/imx/multiplatform' into imx25-dt (2012-11-12 12:08:12 +0100)
are available in the git repository at:
git://git.pengutronix.de/git/imx/linux-2.6.git imx25-dt
for you to fetch changes up to 62300cbf982a5aba4ef22c5c68e1f658e8b324aa:
ARM i.MX: Add Ka-Ro TX25 devicetree (2012-11-12 12:11:27 +0100)
----------------------------------------------------------------
Sascha Hauer (4):
ARM i.MX25: Add missing clock gates
ARM i.MX25: Add devicetree support
ARM i.MX25: Add devicetree
ARM i.MX: Add Ka-Ro TX25 devicetree
.../devicetree/bindings/clock/imx25-clock.txt | 162 ++++++
arch/arm/boot/dts/imx25-karo-tx25.dts | 44 ++
arch/arm/boot/dts/imx25.dtsi | 515 ++++++++++++++++++++
arch/arm/mach-imx/Kconfig | 7 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/clk-imx25.c | 119 ++++-
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/imx25-dt.c | 48 ++
8 files changed, 885 insertions(+), 12 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/imx25-clock.txt
create mode 100644 arch/arm/boot/dts/imx25-karo-tx25.dts
create mode 100644 arch/arm/boot/dts/imx25.dtsi
create mode 100644 arch/arm/mach-imx/imx25-dt.c
^ permalink raw reply
* [PATCH 1/4] ARM i.MX25: Add missing clock gates
From: Sascha Hauer @ 2012-11-12 11:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352719321-23541-1-git-send-email-s.hauer@pengutronix.de>
This completes the list of clock gates on the i.MX25. There are
several clocks marked as reserved in the datasheet, but nevertheless
used in the Freescale kernel. Add some comments to their positions
and add 'reservedx' entries to the clk enum. This way we can replace
them with the real names should we need them later. Adding the reserved
entry names will help us keeping the clk numbers when moving to devicetree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clk-imx25.c | 63 +++++++++++++++++++++++++++++++++++------
1 file changed, 55 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index bc88580..78a754f 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -64,14 +64,20 @@ enum mx25_clks {
per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
- csi_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per, gpt_ipg_per, i2c_ipg_per,
- lcdc_ipg_per, nfc_ipg_per, ssi1_ipg_per, ssi2_ipg_per, uart_ipg_per,
- csi_ahb, esdhc1_ahb, esdhc2_ahb, fec_ahb, lcdc_ahb, sdma_ahb,
- usbotg_ahb, can1_ipg, can2_ipg, csi_ipg, cspi1_ipg, cspi2_ipg,
- cspi3_ipg, dryice_ipg, esdhc1_ipg, esdhc2_ipg, fec_ipg, iim_ipg,
- kpp_ipg, lcdc_ipg, pwm1_ipg, pwm2_ipg, pwm3_ipg, pwm4_ipg, sdma_ipg,
- ssi1_ipg, ssi2_ipg, tsc_ipg, uart1_ipg, uart2_ipg, uart3_ipg,
- uart4_ipg, uart5_ipg, wdt_ipg, clk_max
+ csi_ipg_per, epit_ipg_per, esai_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per,
+ gpt_ipg_per, i2c_ipg_per, lcdc_ipg_per, nfc_ipg_per, owire_ipg_per,
+ pwm_ipg_per, sim1_ipg_per, sim2_ipg_per, ssi1_ipg_per, ssi2_ipg_per,
+ uart_ipg_per, ata_ahb, reserved1, csi_ahb, emi_ahb, esai_ahb, esdhc1_ahb,
+ esdhc2_ahb, fec_ahb, lcdc_ahb, rtic_ahb, sdma_ahb, slcdc_ahb, usbotg_ahb,
+ reserved2, reserved3, reserved4, reserved5, can1_ipg, can2_ipg, csi_ipg,
+ cspi1_ipg, cspi2_ipg, cspi3_ipg, dryice_ipg, ect_ipg, epit1_ipg, epit2_ipg,
+ reserved6, esdhc1_ipg, esdhc2_ipg, fec_ipg, reserved7, reserved8, reserved9,
+ gpt1_ipg, gpt2_ipg, gpt3_ipg, gpt4_ipg, reserved10, reserved11, reserved12,
+ iim_ipg, reserved13, reserved14, kpp_ipg, lcdc_ipg, reserved15, pwm1_ipg,
+ pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg,
+ sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg,
+ uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17,
+ wdt_ipg, clk_max
};
static struct clk *clk[clk_max];
@@ -123,22 +129,36 @@ int __init mx25_clocks_init(void)
clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6);
clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6);
clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0);
+ clk[epit_ipg_per] = imx_clk_gate("epit_ipg_per", "per1", ccm(CCM_CGCR0), 1);
+ clk[esai_ipg_per] = imx_clk_gate("esai_ipg_per", "per2", ccm(CCM_CGCR0), 2);
clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0), 3);
clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4);
clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5);
clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6);
clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7);
clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8);
+ clk[owire_ipg_per] = imx_clk_gate("owire_ipg_per", "per9", ccm(CCM_CGCR0), 9);
+ clk[pwm_ipg_per] = imx_clk_gate("pwm_ipg_per", "per10", ccm(CCM_CGCR0), 10);
+ clk[sim1_ipg_per] = imx_clk_gate("sim1_ipg_per", "per11", ccm(CCM_CGCR0), 11);
+ clk[sim2_ipg_per] = imx_clk_gate("sim2_ipg_per", "per12", ccm(CCM_CGCR0), 12);
clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);
+ clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16);
+ /* CCM_CGCR0(17): reserved */
clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18);
+ clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19);
+ clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20);
clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21);
clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22);
clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23);
clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24);
+ clk[rtic_ahb] = imx_clk_gate("rtic_ahb", "ahb", ccm(CCM_CGCR0), 25);
clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26);
+ clk[slcdc_ahb] = imx_clk_gate("slcdc_ahb", "ahb", ccm(CCM_CGCR0), 27);
clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28);
+ /* CCM_CGCR0(29-31): reserved */
+ /* CCM_CGCR1(0): reserved in datasheet, used as audmux in FSL kernel */
clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2);
clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3);
clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4);
@@ -146,17 +166,41 @@ int __init mx25_clocks_init(void)
clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6);
clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7);
clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8);
+ clk[ect_ipg] = imx_clk_gate("ect_ipg", "ipg", ccm(CCM_CGCR1), 9);
+ clk[epit1_ipg] = imx_clk_gate("epit1_ipg", "ipg", ccm(CCM_CGCR1), 10);
+ clk[epit2_ipg] = imx_clk_gate("epit2_ipg", "ipg", ccm(CCM_CGCR1), 11);
+ /* CCM_CGCR1(12): reserved in datasheet, used as esai in FSL kernel */
clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13);
clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14);
clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15);
+ /* CCM_CGCR1(16): reserved in datasheet, used as gpio1 in FSL kernel */
+ /* CCM_CGCR1(17): reserved in datasheet, used as gpio2 in FSL kernel */
+ /* CCM_CGCR1(18): reserved in datasheet, used as gpio3 in FSL kernel */
+ clk[gpt1_ipg] = imx_clk_gate("gpt1_ipg", "ipg", ccm(CCM_CGCR1), 19);
+ clk[gpt2_ipg] = imx_clk_gate("gpt2_ipg", "ipg", ccm(CCM_CGCR1), 20);
+ clk[gpt3_ipg] = imx_clk_gate("gpt3_ipg", "ipg", ccm(CCM_CGCR1), 21);
+ clk[gpt4_ipg] = imx_clk_gate("gpt4_ipg", "ipg", ccm(CCM_CGCR1), 22);
+ /* CCM_CGCR1(23): reserved in datasheet, used as i2c1 in FSL kernel */
+ /* CCM_CGCR1(24): reserved in datasheet, used as i2c2 in FSL kernel */
+ /* CCM_CGCR1(25): reserved in datasheet, used as i2c3 in FSL kernel */
clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26);
+ /* CCM_CGCR1(27): reserved in datasheet, used as iomuxc in FSL kernel */
+ /* CCM_CGCR1(28): reserved in datasheet, used as kpp in FSL kernel */
clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28);
clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29);
+ /* CCM_CGCR1(30): reserved in datasheet, used as owire in FSL kernel */
clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31);
clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2), 0);
clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2), 1);
clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2), 2);
+ clk[rngb_ipg] = imx_clk_gate("rngb_ipg", "ipg", ccm(CCM_CGCR2), 3);
+ /* CCM_CGCR2(4): reserved in datasheet, used as rtic in FSL kernel */
+ clk[scc_ipg] = imx_clk_gate("scc_ipg", "ipg", ccm(CCM_CGCR2), 5);
clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2), 6);
+ clk[sim1_ipg] = imx_clk_gate("sim1_ipg", "ipg", ccm(CCM_CGCR2), 7);
+ clk[sim2_ipg] = imx_clk_gate("sim2_ipg", "ipg", ccm(CCM_CGCR2), 8);
+ clk[slcdc_ipg] = imx_clk_gate("slcdc_ipg", "ipg", ccm(CCM_CGCR2), 9);
+ clk[spba_ipg] = imx_clk_gate("spba_ipg", "ipg", ccm(CCM_CGCR2), 10);
clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11);
clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12);
clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13);
@@ -165,6 +209,7 @@ int __init mx25_clocks_init(void)
clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16);
clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17);
clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18);
+ /* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */
clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
for (i = 0; i < ARRAY_SIZE(clk); i++)
@@ -172,6 +217,8 @@ int __init mx25_clocks_init(void)
pr_err("i.MX25 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
+ clk_prepare_enable(clk[emi_ahb]);
+
/* i.mx25 has the i.mx21 type uart */
clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
--
1.7.10.4
^ permalink raw reply related
* [PATCH 2/4] ARM i.MX25: Add devicetree support
From: Sascha Hauer @ 2012-11-12 11:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352719321-23541-1-git-send-email-s.hauer@pengutronix.de>
This adds a i.MX25 dt machine descriptor and changes the clock
support to optionally initialize from dt.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/Kconfig | 7 ++++++
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/clk-imx25.c | 56 ++++++++++++++++++++++++++++++++++++++---
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/imx25-dt.c | 48 +++++++++++++++++++++++++++++++++++
5 files changed, 109 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-imx/imx25-dt.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index f1bf610..ff702c3 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -272,6 +272,13 @@ config MACH_EUKREA_MBIMXSD25_BASEBOARD
endchoice
+config MACH_IMX25_DT
+ bool "Support i.MX25 platforms from device tree"
+ select SOC_IMX25
+ help
+ Include support for Freescale i.MX25 based platforms
+ using the device tree for discovery
+
comment "MX27 platforms:"
config MACH_MX27ADS
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index fe47b71..0634b31 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
+obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
# i.MX27 based machines
obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 78a754f..b197aa7 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -23,6 +23,9 @@
#include <linux/io.h>
#include <linux/clkdev.h>
#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include "clk.h"
#include "common.h"
@@ -55,6 +58,8 @@
#define ccm(x) (CRM_BASE + (x))
+static struct clk_onecell_data clk_data;
+
static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
static const char *per_sel_clks[] = { "ahb", "upll", };
@@ -82,12 +87,12 @@ enum mx25_clks {
static struct clk *clk[clk_max];
-int __init mx25_clocks_init(void)
+static int __init __mx25_clocks_init(unsigned long osc_rate)
{
int i;
clk[dummy] = imx_clk_fixed("dummy", 0);
- clk[osc] = imx_clk_fixed("osc", 24000000);
+ clk[osc] = imx_clk_fixed("osc", osc_rate);
clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL));
clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
@@ -219,6 +224,16 @@ int __init mx25_clocks_init(void)
clk_prepare_enable(clk[emi_ahb]);
+ clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
+ clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
+
+ return 0;
+}
+
+int __init mx25_clocks_init(void)
+{
+ __mx25_clocks_init(24000000);
+
/* i.mx25 has the i.mx21 type uart */
clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
@@ -230,8 +245,6 @@ int __init mx25_clocks_init(void)
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
- clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
- clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
@@ -289,5 +302,40 @@ int __init mx25_clocks_init(void)
clk_register_clkdev(clk[iim_ipg], "iim", NULL);
mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
+
+ return 0;
+}
+
+int __init mx25_clocks_init_dt(void)
+{
+ struct device_node *np;
+ void __iomem *base;
+ int irq;
+ unsigned long osc_rate = 24000000;
+
+ /* retrieve the freqency of fixed clocks from device tree */
+ for_each_compatible_node(np, NULL, "fixed-clock") {
+ u32 rate;
+ if (of_property_read_u32(np, "clock-frequency", &rate))
+ continue;
+
+ if (of_device_is_compatible(np, "fsl,imx-osc"))
+ osc_rate = rate;
+ }
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
+ clk_data.clks = clk;
+ clk_data.clk_num = ARRAY_SIZE(clk);
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+ __mx25_clocks_init(osc_rate);
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt");
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+ irq = irq_of_parse_and_map(np, 0);
+
+ mxc_timer_init(base, irq);
+
return 0;
}
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index ef8db6b..7191ab4 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -66,6 +66,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
unsigned long ckih1, unsigned long ckih2);
extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
unsigned long ckih1, unsigned long ckih2);
+extern int mx25_clocks_init_dt(void);
extern int mx27_clocks_init_dt(void);
extern int mx31_clocks_init_dt(void);
extern int mx51_clocks_init_dt(void);
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
new file mode 100644
index 0000000..e17dfbc
--- /dev/null
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irq.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include "common.h"
+#include "mx25.h"
+
+static void __init imx25_dt_init(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void __init imx25_timer_init(void)
+{
+ mx25_clocks_init_dt();
+}
+
+static struct sys_timer imx25_timer = {
+ .init = imx25_timer_init,
+};
+
+static const char * const imx25_dt_board_compat[] __initconst = {
+ "fsl,imx25",
+ NULL
+};
+
+DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
+ .map_io = mx25_map_io,
+ .init_early = imx25_init_early,
+ .init_irq = mx25_init_irq,
+ .handle_irq = imx25_handle_irq,
+ .timer = &imx25_timer,
+ .init_machine = imx25_dt_init,
+ .dt_compat = imx25_dt_board_compat,
+ .restart = mxc_restart,
+MACHINE_END
--
1.7.10.4
^ permalink raw reply related
* [PATCH 3/4] ARM i.MX25: Add devicetree
From: Sascha Hauer @ 2012-11-12 11:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352719321-23541-1-git-send-email-s.hauer@pengutronix.de>
This adds a i.MX25 dtsi file along with the i.MX25 clock tree
documentation. The devicetree should be fairly complete for:
- uart
- fec
- i2c
- spi
- pwm
- nand
- gpio
- wdog
- esdhc
- flexcan
The more exotic devices currently miss clock bindings.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
---
.../devicetree/bindings/clock/imx25-clock.txt | 162 ++++++
arch/arm/boot/dts/imx25.dtsi | 515 ++++++++++++++++++++
2 files changed, 677 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx25-clock.txt
create mode 100644 arch/arm/boot/dts/imx25.dtsi
diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.txt b/Documentation/devicetree/bindings/clock/imx25-clock.txt
new file mode 100644
index 0000000..c2a3525
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx25-clock.txt
@@ -0,0 +1,162 @@
+* Clock bindings for Freescale i.MX25
+
+Required properties:
+- compatible: Should be "fsl,imx25-ccm"
+- reg: Address and length of the register set
+- interrupts: Should contain CCM interrupt
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. The following is a full list of i.MX25
+clocks and IDs.
+
+ Clock ID
+ ---------------------------
+ dummy 0
+ osc 1
+ mpll 2
+ upll 3
+ mpll_cpu_3_4 4
+ cpu_sel 5
+ cpu 6
+ ahb 7
+ usb_div 8
+ ipg 9
+ per0_sel 10
+ per1_sel 11
+ per2_sel 12
+ per3_sel 13
+ per4_sel 14
+ per5_sel 15
+ per6_sel 16
+ per7_sel 17
+ per8_sel 18
+ per9_sel 19
+ per10_sel 20
+ per11_sel 21
+ per12_sel 22
+ per13_sel 23
+ per14_sel 24
+ per15_sel 25
+ per0 26
+ per1 27
+ per2 28
+ per3 29
+ per4 30
+ per5 31
+ per6 32
+ per7 33
+ per8 34
+ per9 35
+ per10 36
+ per11 37
+ per12 38
+ per13 39
+ per14 40
+ per15 41
+ csi_ipg_per 42
+ epit_ipg_per 43
+ esai_ipg_per 44
+ esdhc1_ipg_per 45
+ esdhc2_ipg_per 46
+ gpt_ipg_per 47
+ i2c_ipg_per 48
+ lcdc_ipg_per 49
+ nfc_ipg_per 50
+ owire_ipg_per 51
+ pwm_ipg_per 52
+ sim1_ipg_per 53
+ sim2_ipg_per 54
+ ssi1_ipg_per 55
+ ssi2_ipg_per 56
+ uart_ipg_per 57
+ ata_ahb 58
+ reserved 59
+ csi_ahb 60
+ emi_ahb 61
+ esai_ahb 62
+ esdhc1_ahb 63
+ esdhc2_ahb 64
+ fec_ahb 65
+ lcdc_ahb 66
+ rtic_ahb 67
+ sdma_ahb 68
+ slcdc_ahb 69
+ usbotg_ahb 70
+ reserved 71
+ reserved 72
+ reserved 73
+ reserved 74
+ can1_ipg 75
+ can2_ipg 76
+ csi_ipg 77
+ cspi1_ipg 78
+ cspi2_ipg 79
+ cspi3_ipg 80
+ dryice_ipg 81
+ ect_ipg 82
+ epit1_ipg 83
+ epit2_ipg 84
+ reserved 85
+ esdhc1_ipg 86
+ esdhc2_ipg 87
+ fec_ipg 88
+ reserved 89
+ reserved 90
+ reserved 91
+ gpt1_ipg 92
+ gpt2_ipg 93
+ gpt3_ipg 94
+ gpt4_ipg 95
+ reserved 96
+ reserved 97
+ reserved 98
+ iim_ipg 99
+ reserved 100
+ reserved 101
+ kpp_ipg 102
+ lcdc_ipg 103
+ reserved 104
+ pwm1_ipg 105
+ pwm2_ipg 106
+ pwm3_ipg 107
+ pwm4_ipg 108
+ rngb_ipg 109
+ reserved 110
+ scc_ipg 111
+ sdma_ipg 112
+ sim1_ipg 113
+ sim2_ipg 114
+ slcdc_ipg 115
+ spba_ipg 116
+ ssi1_ipg 117
+ ssi2_ipg 118
+ tsc_ipg 119
+ uart1_ipg 120
+ uart2_ipg 121
+ uart3_ipg 122
+ uart4_ipg 123
+ uart5_ipg 124
+ reserved 125
+ wdt_ipg 126
+
+Examples:
+
+clks: ccm at 53f80000 {
+ compatible = "fsl,imx25-ccm";
+ reg = <0x53f80000 0x4000>;
+ interrupts = <31>;
+ clock-output-names = ...
+ "uart_ipg",
+ "uart_serial",
+ ...;
+};
+
+uart1: serial at 43f90000 {
+ compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+ reg = <0x43f90000 0x4000>;
+ interrupts = <45>;
+ clocks = <&clks 79>, <&clks 50>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
new file mode 100644
index 0000000..e1b13eb
--- /dev/null
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -0,0 +1,515 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ usb0 = &usbotg;
+ usb1 = &usbhost1;
+ };
+
+ asic: asic-interrupt-controller at 68000000 {
+ compatible = "fsl,imx25-asic", "fsl,avic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x68000000 0x8000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc {
+ compatible = "fsl,imx-osc", "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&asic>;
+ ranges;
+
+ aips at 43f00000 { /* AIPS1 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x43f00000 0x100000>;
+ ranges;
+
+ i2c1: i2c at 43f80000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
+ reg = <0x43f80000 0x4000>;
+ clocks = <&clks 48>;
+ clock-names = "";
+ interrupts = <3>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 43f84000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
+ reg = <0x43f84000 0x4000>;
+ clocks = <&clks 48>;
+ clock-names = "";
+ interrupts = <10>;
+ status = "disabled";
+ };
+
+ can1: can at 43f88000 {
+ compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
+ reg = <0x43f88000 0x4000>;
+ interrupts = <43>;
+ clocks = <&clks 75>, <&clks 75>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ can2: can at 43f8c000 {
+ compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
+ reg = <0x43f8c000 0x4000>;
+ interrupts = <44>;
+ clocks = <&clks 76>, <&clks 76>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart1: serial at 43f90000 {
+ compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+ reg = <0x43f90000 0x4000>;
+ interrupts = <45>;
+ clocks = <&clks 120>, <&clks 57>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart2: serial at 43f94000 {
+ compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+ reg = <0x43f94000 0x4000>;
+ interrupts = <32>;
+ clocks = <&clks 121>, <&clks 57>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ i2c2: i2c at 43f98000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
+ reg = <0x43f98000 0x4000>;
+ clocks = <&clks 48>;
+ clock-names = "";
+ interrupts = <4>;
+ status = "disabled";
+ };
+
+ owire at 43f9c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x43f9c000 0x4000>;
+ clocks = <&clks 51>;
+ clock-names = "";
+ interrupts = <2>;
+ status = "disabled";
+ };
+
+ spi1: cspi at 43fa4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
+ reg = <0x43fa4000 0x4000>;
+ clocks = <&clks 62>;
+ clock-names = "ipg";
+ interrupts = <14>;
+ status = "disabled";
+ };
+
+ kpp at 43fa8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x43fa8000 0x4000>;
+ clocks = <&clks 102>;
+ clock-names = "";
+ interrupts = <24>;
+ status = "disabled";
+ };
+
+ iomuxc at 43fac000{
+ compatible = "fsl,imx25-iomuxc";
+ reg = <0x43fac000 0x4000>;
+ };
+
+ audmux at 43fb0000 {
+ compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
+ reg = <0x43fb0000 0x4000>;
+ status = "disabled";
+ };
+ };
+
+ spba at 50000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x50000000 0x40000>;
+ ranges;
+
+ spi3: cspi at 50004000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
+ reg = <0x50004000 0x4000>;
+ interrupts = <0>;
+ clocks = <&clks 80>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ uart4: serial at 50008000 {
+ compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+ reg = <0x50008000 0x4000>;
+ interrupts = <5>;
+ clocks = <&clks 123>, <&clks 57>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart3: serial at 5000c000 {
+ compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+ reg = <0x5000c000 0x4000>;
+ interrupts = <18>;
+ clocks = <&clks 122>, <&clks 57>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ spi2: cspi at 50010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
+ reg = <0x50010000 0x4000>;
+ clocks = <&clks 79>;
+ clock-names = "ipg";
+ interrupts = <13>;
+ status = "disabled";
+ };
+
+ ssi2: ssi at 50014000 {
+ compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
+ reg = <0x50014000 0x4000>;
+ interrupts = <11>;
+ status = "disabled";
+ };
+
+ esai at 50018000 {
+ reg = <0x50018000 0x4000>;
+ interrupts = <7>;
+ };
+
+ uart5: serial at 5002c000 {
+ compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+ reg = <0x5002c000 0x4000>;
+ interrupts = <40>;
+ clocks = <&clks 124>, <&clks 57>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ tsc: tsc at 50030000 {
+ compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
+ reg = <0x50030000 0x4000>;
+ interrupts = <46>;
+ clocks = <&clks 119>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ ssi1: ssi at 50034000 {
+ compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
+ reg = <0x50034000 0x4000>;
+ interrupts = <12>;
+ status = "disabled";
+ };
+
+ fec: ethernet at 50038000 {
+ compatible = "fsl,imx25-fec";
+ reg = <0x50038000 0x4000>;
+ interrupts = <57>;
+ clocks = <&clks 88>, <&clks 65>;
+ clock-names = "ipg", "ahb";
+ status = "disabled";
+ };
+ };
+
+ aips at 53f00000 { /* AIPS2 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x53f00000 0x100000>;
+ ranges;
+
+ clks: ccm at 53f80000 {
+ compatible = "fsl,imx25-ccm";
+ reg = <0x53f80000 0x4000>;
+ interrupts = <31>;
+ #clock-cells = <1>;
+ };
+
+ gpt4: timer at 53f84000 {
+ compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
+ reg = <0x53f84000 0x4000>;
+ clocks = <&clks 9>, <&clks 45>;
+ clock-names = "ipg", "per";
+ interrupts = <1>;
+ };
+
+ gpt3: timer at 53f88000 {
+ compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
+ reg = <0x53f88000 0x4000>;
+ clocks = <&clks 9>, <&clks 47>;
+ clock-names = "ipg", "per";
+ interrupts = <29>;
+ };
+
+ gpt2: timer at 53f8c000 {
+ compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
+ reg = <0x53f8c000 0x4000>;
+ clocks = <&clks 9>, <&clks 47>;
+ clock-names = "ipg", "per";
+ interrupts = <53>;
+ };
+
+ gpt1: timer at 53f90000 {
+ compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
+ reg = <0x53f90000 0x4000>;
+ clocks = <&clks 9>, <&clks 47>;
+ clock-names = "ipg", "per";
+ interrupts = <54>;
+ };
+
+ epit1: timer at 53f94000 {
+ compatible = "fsl,imx25-epit";
+ reg = <0x53f94000 0x4000>;
+ interrupts = <28>;
+ };
+
+ epit2: timer at 53f98000 {
+ compatible = "fsl,imx25-epit";
+ reg = <0x53f98000 0x4000>;
+ interrupts = <27>;
+ };
+
+ gpio4: gpio at 53f9c000 {
+ compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
+ reg = <0x53f9c000 0x4000>;
+ interrupts = <23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pwm2: pwm at 53fa0000 {
+ compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
+ #pwm-cells = <2>;
+ reg = <0x53fa0000 0x4000>;
+ clocks = <&clks 106>, <&clks 36>;
+ clock-names = "ipg", "per";
+ interrupts = <36>;
+ };
+
+ gpio3: gpio at 53fa4000 {
+ compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
+ reg = <0x53fa4000 0x4000>;
+ interrupts = <16>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pwm3: pwm at 53fa8000 {
+ compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
+ #pwm-cells = <2>;
+ reg = <0x53fa8000 0x4000>;
+ clocks = <&clks 107>, <&clks 36>;
+ clock-names = "ipg", "per";
+ interrupts = <41>;
+ };
+
+ esdhc1: esdhc at 53fb4000 {
+ compatible = "fsl,imx25-esdhc";
+ reg = <0x53fb4000 0x4000>;
+ interrupts = <9>;
+ clocks = <&clks 86>, <&clks 63>, <&clks 45>;
+ clock-names = "ipg", "ahb", "per";
+ status = "disabled";
+ };
+
+ esdhc2: esdhc at 53fb8000 {
+ compatible = "fsl,imx25-esdhc";
+ reg = <0x53fb8000 0x4000>;
+ interrupts = <8>;
+ clocks = <&clks 87>, <&clks 64>, <&clks 46>;
+ clock-names = "ipg", "ahb", "per";
+ status = "disabled";
+ };
+
+ lcdc at 53fbc000 {
+ reg = <0x53fbc000 0x4000>;
+ interrupts = <39>;
+ clocks = <&clks 103>, <&clks 66>, <&clks 49>;
+ clock-names = "ipg", "ahb", "per";
+ status = "disabled";
+ };
+
+ slcdc at 53fc0000 {
+ reg = <0x53fc0000 0x4000>;
+ interrupts = <38>;
+ status = "disabled";
+ };
+
+ pwm4: pwm at 53fc8000 {
+ compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
+ reg = <0x53fc8000 0x4000>;
+ clocks = <&clks 108>, <&clks 36>;
+ clock-names = "ipg", "per";
+ interrupts = <42>;
+ };
+
+ gpio1: gpio at 53fcc000 {
+ compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
+ reg = <0x53fcc000 0x4000>;
+ interrupts = <52>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 53fd0000 {
+ compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
+ reg = <0x53fd0000 0x4000>;
+ interrupts = <51>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sdma at 53fd4000 {
+ compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
+ reg = <0x53fd4000 0x4000>;
+ clocks = <&clks 112>, <&clks 68>;
+ clock-names = "ipg", "ahb";
+ interrupts = <34>;
+ };
+
+ wdog at 53fdc000 {
+ compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
+ reg = <0x53fdc000 0x4000>;
+ clocks = <&clks 126>;
+ clock-names = "";
+ interrupts = <55>;
+ };
+
+ pwm1: pwm at 53fe0000 {
+ compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
+ #pwm-cells = <2>;
+ reg = <0x53fe0000 0x4000>;
+ clocks = <&clks 105>, <&clks 36>;
+ clock-names = "ipg", "per";
+ interrupts = <26>;
+ };
+
+ usbphy1: usbphy at 1 {
+ compatible = "nop-usbphy";
+ status = "disabled";
+ };
+
+ usbphy2: usbphy at 2 {
+ compatible = "nop-usbphy";
+ status = "disabled";
+ };
+
+ usbotg: usb at 53ff4000 {
+ compatible = "fsl,imx25-usb", "fsl,imx27-usb";
+ reg = <0x53ff4000 0x0200>;
+ interrupts = <37>;
+ clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+ clock-names = "ipg", "ahb", "per";
+ fsl,usbmisc = <&usbmisc 0>;
+ status = "disabled";
+ };
+
+ usbhost1: usb at 53ff4400 {
+ compatible = "fsl,imx25-usb", "fsl,imx27-usb";
+ reg = <0x53ff4400 0x0200>;
+ interrupts = <35>;
+ clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+ clock-names = "ipg", "ahb", "per";
+ fsl,usbmisc = <&usbmisc 1>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc at 53ff4600 {
+ #index-cells = <1>;
+ compatible = "fsl,imx25-usbmisc";
+ clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+ clock-names = "ipg", "ahb", "per";
+ reg = <0x53ff4600 0x00f>;
+ status = "disabled";
+ };
+
+ dryice at 53ffc000 {
+ compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
+ reg = <0x53ffc000 0x4000>;
+ clocks = <&clks 81>;
+ clock-names = "ipg";
+ interrupts = <25>;
+ };
+ };
+
+ emi at 80000000 {
+ compatible = "fsl,emi-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80000000 0x3b002000>;
+ ranges;
+
+ nand at bb000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "fsl,imx25-nand";
+ reg = <0xbb000000 0x2000>;
+ clocks = <&clks 50>;
+ clock-names = "";
+ interrupts = <33>;
+ status = "disabled";
+ };
+ };
+ };
+};
--
1.7.10.4
^ permalink raw reply related
* [PATCH 4/4] ARM i.MX: Add Ka-Ro TX25 devicetree
From: Sascha Hauer @ 2012-11-12 11:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352719321-23541-1-git-send-email-s.hauer@pengutronix.de>
Basic support for the Ka-Ro i.MX25 based TX25 board.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Lothar Wa?mann <LW@KARO-electronics.de>
---
arch/arm/boot/dts/imx25-karo-tx25.dts | 44 +++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 arch/arm/boot/dts/imx25-karo-tx25.dts
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
new file mode 100644
index 0000000..d81f8a0
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx25.dtsi"
+
+/ {
+ model = "Ka-Ro TX25";
+ compatible = "karo,imx25-tx25", "fsl,imx25";
+
+ memory {
+ reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
+ };
+
+ soc {
+ aips at 43f00000 {
+ uart1: serial at 43f90000 {
+ status = "okay";
+ };
+ };
+
+ spba at 50000000 {
+ fec: ethernet at 50038000 {
+ status = "okay";
+ phy-mode = "rmii";
+ };
+ };
+
+ emi at 80000000 {
+ nand at bb000000 {
+ nand-on-flash-bbt;
+ status = "okay";
+ };
+ };
+ };
+};
--
1.7.10.4
^ permalink raw reply related
* [PATCH] arm: zynq: add system level control register manager
From: Michal Simek @ 2012-11-12 11:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121108160125.GA5550@kryptos>
Hi guys,
first of all sorry for late answer.
> -----Original Message-----
> From: Josh Cartwright [mailto:joshc at eso.teric.us]
> Sent: Thursday, November 08, 2012 5:01 PM
> To: Daniel Borkmann; Arnd Bergmann
> Cc: Michal Simek; linux-arm-kernel at lists.infradead.org; John Linn; Josh
> Cartwright
> Subject: Re: [PATCH] arm: zynq: add system level control register manager
>
> On Wed, Oct 31, 2012 at 07:36:12PM +0100, Daniel Borkmann wrote:
> > This patch for the Xilinx Zynq ARM architecture adds management of
> > system level control register. The code is taken from the
> > Xilinx-internal Linux Git tree and cleaned up a bit for mainline
> > integration. Besides others, this patch is needed in order to
> > integrate further drivers for Zynq such as the Zynq xemacps networking
> > device driver. The patch is aganst the latest arm-soc tree.
> >
> > Signed-off-by: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
> > Cc: Michal Simek <michals@xilinx.com>
> > Cc: John Linn <john.linn@xilinx.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > ---
>
> Hey Daniel-
>
> These changes will conflict with my pending clk patchset [1], as I'm introducing
> bindings for the SLCR (and its clk interfaces).
>
> It seems like a hefty chunk of the out-of-tree slcr driver is related to configuring
> MIO. I think it would be really nice if this driver was reworked to use the pinctrl
> subsystem, and also to provide suitable device tree bindings.
Agree with Josh.
>
> But, at an even higher level, it would be nice to have a coordinated plan for
> getting better Zynq support upstream. My implicit plan (so
> far) has been:
>
> 1. Initial cleanup [get the thing booting] (done)
> 2. Figure out clk drivers and bindings (pending)
I will comment it today.
> 3. Figure out MIO pinctrl support and bindings (?)
We will look at this topic more closely.
> 4. Adapting out-of-tree peripheral drivers according to 2 & 3 (?)
This will take some time.
> 5. Add support for SMP (?)
I can't see any problem why we shouldn't add this after drivers.
Cleaning mach-zynq can be done in parallel.
>
> Step 4 has a dependency on 2 and 3, of course, the point being that we get those
> into a state where we are happy with them before moving all of the peripherals
> over. I believe step 5 can be done in parallel to the others.
Ok. Here it is.
Thanks,
Michal
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^ permalink raw reply
* [PATCH 1/2] ARM: kirkwood: Add Plat'Home OpenBlocks A6 support
From: Nobuhiro Iwamatsu @ 2012-11-12 11:46 UTC (permalink / raw)
To: linux-arm-kernel
Add support for Plat'Home OpenBlocks A6 using the device tree
where possible.
This commit supports SATA, USB, ether and serial console.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 39 ++++++++++++
arch/arm/configs/kirkwood_defconfig | 1 +
arch/arm/mach-kirkwood/Kconfig | 7 +++
arch/arm/mach-kirkwood/Makefile | 1 +
arch/arm/mach-kirkwood/board-dt.c | 4 ++
arch/arm/mach-kirkwood/board-openblocks_a6.c | 86 ++++++++++++++++++++++++++
arch/arm/mach-kirkwood/common.h | 6 ++
8 files changed, 146 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/kirkwood-openblocks_a6.dts
create mode 100644 arch/arm/mach-kirkwood/board-openblocks_a6.c
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b994045..ce053a4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -41,7 +41,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
kirkwood-lschlv2.dtb \
kirkwood-lsxhl.dtb \
kirkwood-ts219-6281.dtb \
- kirkwood-ts219-6282.dtb
+ kirkwood-ts219-6282.dtb \
+ kirkwood-openblocks_a6.dtb
dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
msm8960-cdp.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
new file mode 100644
index 0000000..6493edc
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -0,0 +1,39 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+ model = "Plat'Home OpenBlocksA6";
+ compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/nfs ip=bootp";
+ };
+
+ ocp at f1000000 {
+ serial at 12000 {
+ clock-frequency = <200000000>;
+ status = "ok";
+ };
+
+ serial at 12100 {
+ clock-frequency = <200000000>;
+ status = "ok";
+ };
+
+ nand at 3000000 {
+ chip-delay = <25>;
+ status = "ok";
+ };
+
+ sata at 80000 {
+ nr-ports = <1>;
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 74eee0c..8b5988c 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -27,6 +27,7 @@ CONFIG_MACH_GOFLEXNET_DT=y
CONFIG_MACH_LSXL_DT=y
CONFIG_MACH_IOMEGA_IX2_200_DT=y
CONFIG_MACH_KM_KIRKWOOD_DT=y
+CONFIG_MACH_OPENBLOCKS_A6_DT=y
CONFIG_MACH_TS219=y
CONFIG_MACH_TS41X=y
CONFIG_MACH_DOCKSTAR=y
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 50bca50..830bb5c 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -130,6 +130,13 @@ config MACH_KM_KIRKWOOD_DT
Say 'Y' here if you want your kernel to support the
Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
+config MACH_OPENBLOCKS_A6_DT
+ bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
+ select ARCH_KIRKWOOD_DT
+ help
+ Say 'Y' here if you want your kernel to support the
+ Plat'Home OpenBlocks A6 (Flattened Device Tree).
+
config MACH_TS219
bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 294779f..ee38f9d 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_MACH_GOFLEXNET_DT) += board-goflexnet.o
obj-$(CONFIG_MACH_LSXL_DT) += board-lsxl.o
obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += board-iomega_ix2_200.o
obj-$(CONFIG_MACH_KM_KIRKWOOD_DT) += board-km_kirkwood.o
+obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT) += board-openblocks_a6.o
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index d94872f..c3aa0e2 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -94,6 +94,9 @@ static void __init kirkwood_dt_init(void)
if (of_machine_is_compatible("keymile,km_kirkwood"))
km_kirkwood_init();
+ if (of_machine_is_compatible("plathome,openblocks-a6"))
+ openblocks_a6_init();
+
of_platform_populate(NULL, kirkwood_dt_match_table,
kirkwood_auxdata_lookup, NULL);
}
@@ -110,6 +113,7 @@ static const char *kirkwood_dt_board_compat[] = {
"buffalo,lsxl",
"iom,ix2-200",
"keymile,km_kirkwood",
+ "plathome,openblocks-a6",
NULL
};
diff --git a/arch/arm/mach-kirkwood/board-openblocks_a6.c b/arch/arm/mach-kirkwood/board-openblocks_a6.c
new file mode 100644
index 0000000..ee6f4c6
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-openblocks_a6.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2012 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * arch/arm/mach-kirkwood/board-openblocks_a6.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data openblocks_ge00_data = {
+ .phy_addr = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int openblocks_a6_mpp_config[] __initdata = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ /* MPP7_GPO, */
+ MPP8_UART1_RTS,
+ MPP9_UART1_CTS,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ /* MPP12_GPIO, */
+ MPP13_UART1_TXD,
+ MPP14_UART1_RXD,
+ MPP15_UART0_RTS,
+ MPP16_UART0_CTS,
+ /* MPP17_GPIO, */
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO, /* CFG 0 */
+ MPP21_GPIO, /* CFG 1 */
+ MPP22_GPIO, /* CFG 2 */
+ MPP23_GPIO, /* CFG 3 */
+ MPP24_GPIO, /* GPIO 0 */
+ MPP25_GPIO, /* GPIO 1 */
+ MPP26_GPIO, /* GPIO 2 */
+ MPP27_GPIO, /* GPIO 3 */
+ MPP28_GPIO, /* GPIO 4 */
+ MPP29_GPIO, /* GPIO 5 */
+ MPP30_GPIO, /* GPIO 6 */
+ MPP31_GPIO, /* GPIO 7 */
+ /* MPP32_GPIO, */
+ /* MPP33_GPO, */
+ /* MPP34_GPIO, */
+ /* MPP35_GPIO, */
+ MPP36_TW1_SDA,
+ MPP37_TW1_SCK,
+ MPP38_GPIO, /* INIT */
+ MPP39_GPIO, /* USB OC */
+ /* MPP40_GPIO, */
+ MPP41_GPIO, /* LED: Red */
+ MPP42_GPIO, /* LED: Yellow */
+ MPP43_GPIO, /* LED: Green */
+ /* MPP44_GPIO, */
+ /* MPP45_GPIO, */
+ /* MPP46_GPIO, */
+ /* MPP47_GPIO, */
+ /* MPP48_GPIO, */
+ /* MPP49_GPIO, */
+ 0,
+};
+
+void __init openblocks_a6_init(void)
+{
+ /*
+ * Basic setup. Needs to be called early.
+ */
+ kirkwood_mpp_conf(openblocks_a6_mpp_config);
+ kirkwood_uart0_init();
+ kirkwood_ehci_init();
+ kirkwood_ge00_init(&openblocks_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index bcffd7c..0d0159e 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -112,6 +112,12 @@ void km_kirkwood_init(void);
static inline void km_kirkwood_init(void) {};
#endif
+#ifdef CONFIG_MACH_OPENBLOCKS_A6_DT
+void openblocks_a6_init(void);
+#else
+static inline void openblocks_a6_init(void) {};
+#endif
+
/* early init functions not converted to fdt yet */
char *kirkwood_id(void);
void kirkwood_l2_init(void);
--
1.7.10.4
^ permalink raw reply related
* [PATCH v2 2/5] ARM: kernel: add device tree init map function
From: Lorenzo Pieralisi @ 2012-11-12 11:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121112103713.GA7982@e106331-lin.cambridge.arm.com>
Hi Mark,
On Mon, Nov 12, 2012 at 10:38:09AM +0000, Mark Rutland wrote:
> On Fri, Nov 09, 2012 at 02:34:11PM +0000, Lorenzo Pieralisi wrote:
> > When booting through a device tree, the kernel cpu logical id map can be
> > initialized using device tree data passed by FW or through an embedded blob.
> >
> > This patch adds a function that parses device tree "cpu" nodes and
> > retrieves the corresponding CPUs hardware identifiers (MPIDR).
> > It sets the possible cpus and the cpu logical map values according to
> > the number of CPUs defined in the device tree and respective properties.
> >
> > The device tree HW identifiers are considered valid if all CPU nodes contain
> > a "reg" property and the DT defines a CPU node that matches the MPIDR[23:0]
> > of the boot CPU.
> >
> > The primary CPU is assigned cpu logical number 0 to keep the current convention
> > valid.
> >
> > Current bindings documentation is included in the patch:
> >
> > Documentation/devicetree/bindings/arm/cpus.txt
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > ---
> > Documentation/devicetree/bindings/arm/cpus.txt | 84 ++++++++++++++++++++++++++
> > arch/arm/include/asm/prom.h | 2 +
> > arch/arm/kernel/devtree.c | 76 +++++++++++++++++++++++
> > 3 files changed, 162 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/arm/cpus.txt
> >
> > diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> > new file mode 100644
> > index 0000000..83cd98a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> > @@ -0,0 +1,84 @@
> > +* ARM CPUs binding description
> > +
> > +The device tree allows to describe the layout of CPUs in a system through
> > +the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> > +defining properties for every cpu.
> > +
> > +Bindings for CPU nodes follow the ePAPR standard, available from:
> > +
> > +http://devicetree.org
> > +
> > +For the ARM architecture every CPU node must contain the following properties:
> > +
> > +- reg : property matching the CPU MPIDR[23:0] register bits
> > +- compatible: must be set to "arm, <cpu-model>"
> > + where <cpu-model> is the full processor name as used in the
> > + processor Technical Reference Manual, eg:
> > + - for a Cortex A9 processor
> > + compatible = <arm, cortex-a9>;
> > + - for a Cortex A15 processor
> > + compatible = <arm, cortex-a15>;
> > +
> > +List of possible "compatible" string ids:
> > +
> > +<arm, arm1020>
> > +<arm, arm1020e>
> > +<arm, arm1022>
> > +<arm, arm1026>
> > +<arm, arm720>
> > +<arm, arm740>
> > +<arm, arm7tdmi>
> > +<arm, arm920>
> > +<arm, arm922>
> > +<arm, arm925>
> > +<arm, arm926>
> > +<arm, arm940>
> > +<arm, arm946>
> > +<arm, arm9tdmi>
> > +<arm, fa526>
> > +<arm, feroceon>
> > +<arm, mohawk>
> > +<arm, sa110>
> > +<arm, sa1100>
> > +<arm, xsc3>
> > +<arm, xscale>
> > +<arm, cortex-a5>
> > +<arm, cortex-a7>
> > +<arm, cortex-a8>
> > +<arm, cortex-a9>
> > +<arm, cortex-a15>
> > +<arm, arm1136>
> > +<arm, arm11-mpcore>
> > +
>
> Is there any reason for the spaces in the compatible string? No other binding
> seems to do this.
>
> Is <STRING> a valid dts format? Should these not be "STRING" instead?
>
> For consistency, it would be nice to have the compatible strings tab-indented
> as in Documentation/devicetree/bindings/arm/pmu.txt.
You are absolutely right on all points, I will update the description.
Thanks,
Lorenzo
^ permalink raw reply
* [PATCH 2/8] ARM: zynq: move ttc timer code to drivers/clocksource
From: Michal Simek @ 2012-11-12 11:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121105214753.GB1254@beefymiracle.amer.corp.natinst.com>
2012/11/5 Josh Cartwright <josh.cartwright@ni.com>:
> On Mon, Nov 05, 2012 at 12:22:55PM +0100, Michal Simek wrote:
>> 2012/10/29 Josh Cartwright <josh.cartwright@ni.com>:
>> > Suggested cleanup by Arnd Bergmann. Move the ttc timer.c code to
>> > drivers/clocksource, and out of the mach-zynq directory.
>> >
>> > The common.h (which only held the timer declaration) was renamed to
>> > xilinx_ttc.h and moved into include/linux.
>> >
>> > Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
>> > Cc: Arnd Bergmann <arnd@arndb.de>
>> > ---
>> > arch/arm/mach-zynq/Makefile | 2 +-
>> > arch/arm/mach-zynq/common.c | 2 +-
>> > drivers/clocksource/Makefile | 1 +
>> > arch/arm/mach-zynq/timer.c => drivers/clocksource/xilinx_ttc.c | 1 -
>> > arch/arm/mach-zynq/common.h => include/linux/xilinx_ttc.h | 4 ++--
>> > 5 files changed, 5 insertions(+), 5 deletions(-)
>> > rename arch/arm/mach-zynq/timer.c => drivers/clocksource/xilinx_ttc.c (99%)
>> > rename arch/arm/mach-zynq/common.h => include/linux/xilinx_ttc.h (91%)
>>
>> Not going to apply this patch till there is clean way how to move all
>> drivers there. Especially I don't like to add xilinx_ttc.h to
>> include/linux folder.
>
> Okay; I think it's best to defer the moving of the ttc driver from this
> patchset. It is not a dependency of the clk driver support stuff.
> If you agree, I can spin up a v2 of the patchset w/o this change, and
> without the serial CONFIG_OF stuff. Should v2 contain the patches
> you've already pulled into testing?
Sure and I see you have done which is good.
Thanks,
Michal
^ permalink raw reply
* [PATCH 03/16] mm: check rb_subtree_gap correctness
From: Michel Lespinasse @ 2012-11-12 11:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509D0F86.30607@gmail.com>
On Fri, Nov 9, 2012 at 6:13 AM, Sasha Levin <levinsasha928@gmail.com> wrote:
> While fuzzing with trinity inside a KVM tools (lkvm) guest, using today's -next
> kernel, I'm getting these:
>
> [ 117.007714] free gap 7fba0dd1c000, correct 7fba0dcfb000
> [ 117.019773] map_count 750 rb -1
> [ 117.028362] ------------[ cut here ]------------
> [ 117.029813] kernel BUG at mm/mmap.c:439!
>
> Note that they are very easy to reproduce.
Thanks for the report. I had trouble reproducing this on Friday, but
after Hugh came up with an easy test case I think I have it figured
out. I sent out a proposed fix as "[PATCH 0/3] fix missing
rb_subtree_gap updates on vma insert/erase". Let's follow up the
discussion there if necessary.
Cheers,
--
Michel "Walken" Lespinasse
A program is never fully debugged until the last user dies.
^ permalink raw reply
* [PATCH v2 2/5] clk: Add support for fundamental zynq clks
From: Michal Simek @ 2012-11-12 11:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121108232807.GG18904@xsjpsgb1010.xilinx.com>
> -----Original Message-----
> From: Soren Brinkmann [mailto:soren.brinkmann at xilinx.com]
> Sent: Friday, November 09, 2012 12:28 AM
> To: Josh Cartwright
> Cc: Mike Turquette; Rob Herring; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; Michal Simek; John Linn; arm at kernel.org
> Subject: Re: [PATCH v2 2/5] clk: Add support for fundamental zynq clks
>
> One note below:
>
> On Wed, Oct 31, 2012 at 12:58:52PM -0600, Josh Cartwright wrote:
> > Provide simplified models for the necessary clocks on the zynq-7000
> > platform. Currently, the PLLs, the CPU clock network, and the basic
> > peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled.
> >
> > OF bindings are also provided and documented.
> >
> > Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
> > ---
> > .../devicetree/bindings/clock/zynq-7000.txt | 55 +++
> > drivers/clk/clk-zynq.c | 383 +++++++++++++++++++++
> > include/linux/clk/zynq.h | 24 ++
> > 3 files changed, 462 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/clock/zynq-7000.txt
> > create mode 100644 drivers/clk/clk-zynq.c create mode 100644
> > include/linux/clk/zynq.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt
> > b/Documentation/devicetree/bindings/clock/zynq-7000.txt
> > new file mode 100644
> > index 0000000..23ae1db
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
> > @@ -0,0 +1,55 @@
> > +Device Tree Clock bindings for the Zynq 7000 EPP
> > +
> > +The Zynq EPP has several different clk providers, each with there own
> bindings.
> > +The purpose of this document is to document their usage.
> > +
> > +See clock_bindings.txt for more information on the generic clock bindings.
> > +See Chapter 25 of Zynq TRM for more information about Zynq clocks.
> > +
> > +== PLLs ==
> > +
> > +Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
> > +
> > +Required properties:
> > +- #clock-cells : shall be 0 (only one clock is output from this node)
> > +- compatible : "xlnx,zynq-pll"
> > +- reg : pair of u32 values, which are the address offsets within the SLCR
> > + of the relevant PLL_CTRL register and PLL_CFG register
> > +respectively
> > +- clocks : phandle for parent clock. should be the phandle for
> > +ps_clk
> > +
> > +Optional properties:
> > +- clock-output-names : name of the output clock
> > +
> > +Example:
> > + armpll: armpll {
> > + #clock-cells = <0>;
> > + compatible = "xlnx,zynq-pll";
> > + clocks = <&ps_clk>;
> > + reg = <0x100 0x110>;
> > + clock-output-names = "armpll";
> > + };
> > +
> > +== Peripheral clocks ==
> > +
> > +Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
> > +
> > +Required properties:
> > +- #clock-cells : shall be 1
> > +- compatible : "xlnx,zynq-periph-clock"
> > +- reg : a single u32 value, describing the offset within the SLCR where
> > + the CLK_CTRL register is found for this peripheral
> > +- clocks : phandle for parent clocks. should hold phandles for
> > + the IO_PLL, ARM_PLL, and DDR_PLL in order
> > +- clock-output-names : names of the output clock(s). For peripherals that
> have
> > + two output clocks (for example, the UART), two clocks
> > + should be listed.
> > +
> > +Example:
> > + uart_clk: uart_clk {
> > + #clock-cells = <1>;
> > + compatible = "xlnx,zynq-periph-clock";
> > + clocks = <&iopll &armpll &ddrpll>;
> > + reg = <0x154>;
> > + clock-output-names = "uart0_ref_clk",
> > + "uart1_ref_clk";
> > + };
> > diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c new file
> > mode 100644 index 0000000..de8b586
> > --- /dev/null
> > +++ b/drivers/clk/clk-zynq.c
> > @@ -0,0 +1,383 @@
> > +/*
> > + * Copyright (c) 2012 National Instruments
> > + *
> > + * Josh Cartwright <josh.cartwright@ni.com>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > +modify it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2, as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope it will be useful, but
> > +WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> > +or
> > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
> > +License for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > +along with
> > + * this program. If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +#include <linux/io.h>
> > +#include <linux/of.h>
> > +#include <linux/slab.h>
> > +#include <linux/kernel.h>
> > +#include <linux/clk-provider.h>
> > +
> > +static void __iomem *slcr_base;
> > +
> > +struct zynq_pll_clk {
> > + struct clk_hw hw;
> > + void __iomem *pll_ctrl;
> > + void __iomem *pll_cfg;
> > +};
> > +
> > +#define to_zynq_pll_clk(hw) container_of(hw, struct zynq_pll_clk, hw)
> > +
> > +#define CTRL_PLL_FDIV(x) ((x) >> 12)
> > +
> > +static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
> > + unsigned long parent_rate)
> > +{
> > + struct zynq_pll_clk *pll = to_zynq_pll_clk(hw);
> > + return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl));
> > +}
> > +
> > +static const struct clk_ops zynq_pll_clk_ops = {
> > + .recalc_rate = zynq_pll_recalc_rate,
> > +};
> > +
> > +static void __init zynq_pll_clk_setup(struct device_node *np) {
> > + struct clk_init_data init;
> > + struct zynq_pll_clk *pll;
> > + const char *parent_name;
> > + struct clk *clk;
> > + u32 regs[2];
> > + int ret;
> > +
> > + ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs));
> > + if (WARN_ON(ret))
> > + return;
> > +
> > + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> > + if (WARN_ON(!pll))
> > + return;
> > +
> > + pll->pll_ctrl = slcr_base + regs[0];
> > + pll->pll_cfg = slcr_base + regs[1];
> > +
> > + of_property_read_string(np, "clock-output-names", &init.name);
> > +
> > + init.ops = &zynq_pll_clk_ops;
> > + parent_name = of_clk_get_parent_name(np, 0);
> > + init.parent_names = &parent_name;
> > + init.num_parents = 1;
> > +
> > + pll->hw.init = &init;
> > +
> > + clk = clk_register(NULL, &pll->hw);
> > + if (WARN_ON(IS_ERR(clk)))
> > + return;
> > +
> > + ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
> > + if (WARN_ON(ret))
> > + return;
> > +}
> > +
> > +struct zynq_periph_clk {
> > + struct clk_hw hw;
> > + struct clk_onecell_data onecell_data;
> > + struct clk *gates[2];
> > + void __iomem *clk_ctrl;
> > + spinlock_t clkact_lock;
> > +};
> > +
> > +#define to_zynq_periph_clk(hw) container_of(hw, struct zynq_periph_clk,
> hw)
> > +
> > +static const u8 periph_clk_parent_map[] = {
> > + 0, 0, 1, 2
> > +};
> > +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 3) >> 4])
> I think this should be:
> #define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >>
> 4])
>
Josh: Any comment?
Thanks,
Michal
^ permalink raw reply
* [PATCH v2 1/5] ARM: zynq: dts: split up device tree
From: Michal Simek @ 2012-11-12 12:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <052ad319f1599baa9a2fc840726a98f573e08672.1352400580.git.josh.cartwright@ni.com>
Hi Josh,
2012/10/31 Josh Cartwright <josh.cartwright@ni.com>:
> The purpose of the created zynq-7000.dtsi file is to describe the
> hardware common to all Zynq 7000-based boards. Also, get rid of the
> zynq-ep107 device tree, since it is not hardware anyone can purchase.
>
> Add a zc702 dts file based on the zynq-7000.dtsi. Add it to the
> dts/Makefile so it is built with the 'dtbs' target.
>
> Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> .../boot/dts/{zynq-ep107.dts => zynq-7000.dtsi} | 19 +++-----------
> arch/arm/boot/dts/zynq-zc702.dts | 30 ++++++++++++++++++++++
> arch/arm/mach-zynq/common.c | 3 ++-
> 4 files changed, 36 insertions(+), 17 deletions(-)
> rename arch/arm/boot/dts/{zynq-ep107.dts => zynq-7000.dtsi} (79%)
> create mode 100644 arch/arm/boot/dts/zynq-zc702.dts
We have had discussion about this dtsi stuff and also based on our
previous discussion
all trying to convince me that this solution is right solution.
I still have doubts but I will apply it to arm-next tree and we can
revisit it in future.
Thanks,
Michal
^ permalink raw reply
* [PATCH 1/2] ARM: kirkwood: Add Plat'Home OpenBlocks A6 support
From: Andrew Lunn @ 2012-11-12 12:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352720819-21923-1-git-send-email-iwamatsu@nigauri.org>
Hi Nobuhiro
This is a good start. A few comments below.
On Mon, Nov 12, 2012 at 08:46:59PM +0900, Nobuhiro Iwamatsu wrote:
> Add support for Plat'Home OpenBlocks A6 using the device tree
> where possible.
> This commit supports SATA, USB, ether and serial console.
>
> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 39 ++++++++++++
> arch/arm/configs/kirkwood_defconfig | 1 +
> arch/arm/mach-kirkwood/Kconfig | 7 +++
> arch/arm/mach-kirkwood/Makefile | 1 +
> arch/arm/mach-kirkwood/board-dt.c | 4 ++
> arch/arm/mach-kirkwood/board-openblocks_a6.c | 86 ++++++++++++++++++++++++++
> arch/arm/mach-kirkwood/common.h | 6 ++
> 8 files changed, 146 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/kirkwood-openblocks_a6.dts
> create mode 100644 arch/arm/mach-kirkwood/board-openblocks_a6.c
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index b994045..ce053a4 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -41,7 +41,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
> kirkwood-lschlv2.dtb \
> kirkwood-lsxhl.dtb \
> kirkwood-ts219-6281.dtb \
> - kirkwood-ts219-6282.dtb
> + kirkwood-ts219-6282.dtb \
> + kirkwood-openblocks_a6.dtb
> dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
> msm8960-cdp.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
> diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
> new file mode 100644
> index 0000000..6493edc
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
> @@ -0,0 +1,39 @@
> +/dts-v1/;
> +
> +/include/ "kirkwood.dtsi"
> +
> +/ {
> + model = "Plat'Home OpenBlocksA6";
> + compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood";
Ah, interesting. A 88f6283. I'm a bit surprised this actually works!
This variant is not listed in kirkwood_id(). So do you see messages
like:
"Device-Unknown"
and
"MPP setup: unknown kirkwood variant"
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x20000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/nfs ip=bootp";
Please remove root=/dev/nfs and ip=bootp. We want the box to boot on
its own without help from the network.
> + };
> +
> + ocp at f1000000 {
> + serial at 12000 {
> + clock-frequency = <200000000>;
> + status = "ok";
> + };
> +
> + serial at 12100 {
> + clock-frequency = <200000000>;
> + status = "ok";
> + };
> +
> + nand at 3000000 {
> + chip-delay = <25>;
> + status = "ok";
> + };
> +
> + sata at 80000 {
> + nr-ports = <1>;
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
> index 74eee0c..8b5988c 100644
> --- a/arch/arm/configs/kirkwood_defconfig
> +++ b/arch/arm/configs/kirkwood_defconfig
> @@ -27,6 +27,7 @@ CONFIG_MACH_GOFLEXNET_DT=y
> CONFIG_MACH_LSXL_DT=y
> CONFIG_MACH_IOMEGA_IX2_200_DT=y
> CONFIG_MACH_KM_KIRKWOOD_DT=y
> +CONFIG_MACH_OPENBLOCKS_A6_DT=y
> CONFIG_MACH_TS219=y
> CONFIG_MACH_TS41X=y
> CONFIG_MACH_DOCKSTAR=y
> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
> index 50bca50..830bb5c 100644
> --- a/arch/arm/mach-kirkwood/Kconfig
> +++ b/arch/arm/mach-kirkwood/Kconfig
> @@ -130,6 +130,13 @@ config MACH_KM_KIRKWOOD_DT
> Say 'Y' here if you want your kernel to support the
> Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
>
> +config MACH_OPENBLOCKS_A6_DT
> + bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
> + select ARCH_KIRKWOOD_DT
> + help
> + Say 'Y' here if you want your kernel to support the
> + Plat'Home OpenBlocks A6 (Flattened Device Tree).
> +
> config MACH_TS219
> bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
> help
> diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
> index 294779f..ee38f9d 100644
> --- a/arch/arm/mach-kirkwood/Makefile
> +++ b/arch/arm/mach-kirkwood/Makefile
> @@ -31,3 +31,4 @@ obj-$(CONFIG_MACH_GOFLEXNET_DT) += board-goflexnet.o
> obj-$(CONFIG_MACH_LSXL_DT) += board-lsxl.o
> obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += board-iomega_ix2_200.o
> obj-$(CONFIG_MACH_KM_KIRKWOOD_DT) += board-km_kirkwood.o
> +obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT) += board-openblocks_a6.o
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index d94872f..c3aa0e2 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -94,6 +94,9 @@ static void __init kirkwood_dt_init(void)
> if (of_machine_is_compatible("keymile,km_kirkwood"))
> km_kirkwood_init();
>
> + if (of_machine_is_compatible("plathome,openblocks-a6"))
> + openblocks_a6_init();
> +
> of_platform_populate(NULL, kirkwood_dt_match_table,
> kirkwood_auxdata_lookup, NULL);
> }
> @@ -110,6 +113,7 @@ static const char *kirkwood_dt_board_compat[] = {
> "buffalo,lsxl",
> "iom,ix2-200",
> "keymile,km_kirkwood",
> + "plathome,openblocks-a6",
> NULL
> };
>
> diff --git a/arch/arm/mach-kirkwood/board-openblocks_a6.c b/arch/arm/mach-kirkwood/board-openblocks_a6.c
> new file mode 100644
> index 0000000..ee6f4c6
> --- /dev/null
> +++ b/arch/arm/mach-kirkwood/board-openblocks_a6.c
> @@ -0,0 +1,86 @@
> +/*
> + * Copyright 2012 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
> + *
> + * arch/arm/mach-kirkwood/board-openblocks_a6.c
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/mv643xx_eth.h>
> +#include <linux/clk.h>
> +#include <linux/clk-private.h>
> +#include "common.h"
> +#include "mpp.h"
> +
> +static struct mv643xx_eth_platform_data openblocks_ge00_data = {
> + .phy_addr = MV643XX_ETH_PHY_ADDR(0),
> +};
> +
> +static unsigned int openblocks_a6_mpp_config[] __initdata = {
> + MPP0_NF_IO2,
> + MPP1_NF_IO3,
> + MPP2_NF_IO4,
> + MPP3_NF_IO5,
> + MPP4_NF_IO6,
> + MPP5_NF_IO7,
> + MPP6_SYSRST_OUTn,
> + /* MPP7_GPO, */
Any reason not to actually have MPP7_GPO here?
Is it being used as a GPO line?
Same question for all the other commented out GPIOs.
> + MPP8_UART1_RTS,
> + MPP9_UART1_CTS,
> + MPP10_UART0_TXD,
> + MPP11_UART0_RXD,
> + /* MPP12_GPIO, */
> + MPP13_UART1_TXD,
> + MPP14_UART1_RXD,
> + MPP15_UART0_RTS,
> + MPP16_UART0_CTS,
> + /* MPP17_GPIO, */
> + MPP18_NF_IO0,
> + MPP19_NF_IO1,
> + MPP20_GPIO, /* CFG 0 */
> + MPP21_GPIO, /* CFG 1 */
> + MPP22_GPIO, /* CFG 2 */
> + MPP23_GPIO, /* CFG 3 */
Are these four above DIP switches?
> + MPP24_GPIO, /* GPIO 0 */
> + MPP25_GPIO, /* GPIO 1 */
> + MPP26_GPIO, /* GPIO 2 */
> + MPP27_GPIO, /* GPIO 3 */
> + MPP28_GPIO, /* GPIO 4 */
> + MPP29_GPIO, /* GPIO 5 */
> + MPP30_GPIO, /* GPIO 6 */
> + MPP31_GPIO, /* GPIO 7 */
> + /* MPP32_GPIO, */
> + /* MPP33_GPO, */
> + /* MPP34_GPIO, */
> + /* MPP35_GPIO, */
> + MPP36_TW1_SDA,
> + MPP37_TW1_SCK,
> + MPP38_GPIO, /* INIT */
> + MPP39_GPIO, /* USB OC */
> + /* MPP40_GPIO, */
> + MPP41_GPIO, /* LED: Red */
> + MPP42_GPIO, /* LED: Yellow */
> + MPP43_GPIO, /* LED: Green */
> + /* MPP44_GPIO, */
> + /* MPP45_GPIO, */
> + /* MPP46_GPIO, */
> + /* MPP47_GPIO, */
> + /* MPP48_GPIO, */
> + /* MPP49_GPIO, */
> + 0,
> +};
> +
> +void __init openblocks_a6_init(void)
> +{
> + /*
> + * Basic setup. Needs to be called early.
> + */
> + kirkwood_mpp_conf(openblocks_a6_mpp_config);
> + kirkwood_uart0_init();
You don't need this. The DT description is enough to get the uart
working.
> + kirkwood_ehci_init();
> + kirkwood_ge00_init(&openblocks_ge00_data);
> +}
> diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
> index bcffd7c..0d0159e 100644
> --- a/arch/arm/mach-kirkwood/common.h
> +++ b/arch/arm/mach-kirkwood/common.h
> @@ -112,6 +112,12 @@ void km_kirkwood_init(void);
> static inline void km_kirkwood_init(void) {};
> #endif
>
> +#ifdef CONFIG_MACH_OPENBLOCKS_A6_DT
> +void openblocks_a6_init(void);
> +#else
> +static inline void openblocks_a6_init(void) {};
> +#endif
> +
> /* early init functions not converted to fdt yet */
> char *kirkwood_id(void);
> void kirkwood_l2_init(void);
> --
> 1.7.10.4
>
^ permalink raw reply
* [PATCH] ARM: tegra: enable data prefetch on L2
From: Peter De Schrijver @ 2012-11-12 12:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352251597-2936-1-git-send-email-josephl@nvidia.com>
On Wed, Nov 07, 2012 at 02:26:37AM +0100, Joseph Lo wrote:
> Enable the data prefetch on L2. The bit28 in aux ctrl register.
>
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> ---
> arch/arm/mach-tegra/common.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
> index c25746e..c3dee56 100644
> --- a/arch/arm/mach-tegra/common.c
> +++ b/arch/arm/mach-tegra/common.c
> @@ -124,7 +124,7 @@ static void __init tegra_init_cache(void)
>
> cache_type = readl(p + L2X0_CACHE_TYPE);
> aux_ctrl = (cache_type & 0x700) << (17-8);
> - aux_ctrl |= 0x6C000001;
> + aux_ctrl |= 0x7C000001;
Just found out that we should also set bit 22 as per
http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6395%2F1
Stephen, should I send a seperate patch for that?
Cheers,
Peter.
^ permalink raw reply
* [PATCH] ARM: tegra: retain L2 content over CPU suspend/resume
From: Peter De Schrijver @ 2012-11-12 12:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352194377-6209-1-git-send-email-josephl@nvidia.com>
On Tue, Nov 06, 2012 at 10:32:57AM +0100, Joseph Lo wrote:
> The L2 RAM is in different power domain from the CPU cluster. So the
> L2 content can be retained over CPU suspend/resume. To do that, we
> need to disable L2 after the MMU is disabled, and enable L2 before
> the MMU is enabled. But the L2 controller is in the same power domain
> with the CPU cluster. We need to restore it's settings and re-enable
> it after the power be resumed.
>
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> ---
> arch/arm/mach-tegra/common.c | 6 +++++-
> arch/arm/mach-tegra/headsmp.S | 11 +++++++++++
> arch/arm/mach-tegra/pm.c | 2 --
> arch/arm/mach-tegra/pm.h | 2 ++
> arch/arm/mach-tegra/sleep.S | 7 +++++++
> arch/arm/mach-tegra/sleep.h | 28 ++++++++++++++++++++++++++++
> 6 files changed, 53 insertions(+), 3 deletions(-)
Apart from the missing define:
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
^ permalink raw reply
* [PATCH] ARM: implement optimized percpu variable access
From: Rob Herring @ 2012-11-12 13:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121112102354.GA2346@mudshark.cambridge.arm.com>
On 11/12/2012 04:23 AM, Will Deacon wrote:
> Hi Rob,
>
> On Sun, Nov 11, 2012 at 03:20:40AM +0000, Rob Herring wrote:
>> From: Rob Herring <rob.herring@calxeda.com>
>>
>> Use the previously unused TPIDRPRW register to store percpu offsets.
>> TPIDRPRW is only accessible in PL1, so it can only be used in the kernel.
>>
>> This saves 2 loads for each percpu variable access which should yield
>> improved performance, but the improvement has not been quantified.
>
> The patch looks largely fine to me (one minor comment below), but we should
> try and see what the performance difference is like on a few cores before
> merging this. Have you tried something like hackbench to see if the
> difference is measurable there? If not, I guess we'll need something more
> targetted.
Thanks for the suggestion. I'll give it a try.
>> diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h
>> new file mode 100644
>> index 0000000..9eb7372
>> --- /dev/null
>> +++ b/arch/arm/include/asm/percpu.h
>> @@ -0,0 +1,44 @@
>> +/*
>> + * Copyright 2012 Calxeda, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +#ifndef _ASM_ARM_PERCPU_H_
>> +#define _ASM_ARM_PERCPU_H_
>> +
>> +/*
>> + * Same as asm-generic/percpu.h, except that we store the per cpu offset
>> + * in the TPIDRPRW.
>> + */
>> +#if defined(CONFIG_SMP) && (__LINUX_ARM_ARCH__ >= 6)
>> +
>> +static inline void set_my_cpu_offset(unsigned long off)
>> +{
>> + asm volatile("mcr p15, 0, %0, c13, c0, 4 @ set TPIDRPRW" : : "r" (off) : "cc" );
>> +}
>
> You don't need the "cc" here.
You would think so, but the compiler drops this instruction if you
don't. set_cr does the same thing.
Rob
^ permalink raw reply
* [RFC 3/6] sched: pack small tasks
From: Vincent Guittot @ 2012-11-12 13:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109164631.GA16082@e103034-lin>
On 9 November 2012 17:46, Morten Rasmussen <Morten.Rasmussen@arm.com> wrote:
> On Fri, Nov 02, 2012 at 10:53:47AM +0000, Santosh Shilimkar wrote:
>> On Monday 29 October 2012 06:42 PM, Vincent Guittot wrote:
>> > On 24 October 2012 17:20, Santosh Shilimkar <santosh.shilimkar@ti.com> wrote:
>> >> Vincent,
>> >>
>> >> Few comments/questions.
>> >>
>> >>
>> >> On Sunday 07 October 2012 01:13 PM, Vincent Guittot wrote:
>> >>>
>> >>> During sched_domain creation, we define a pack buddy CPU if available.
>> >>>
>> >>> On a system that share the powerline at all level, the buddy is set to -1
>> >>>
>> >>> On a dual clusters / dual cores system which can powergate each core and
>> >>> cluster independantly, the buddy configuration will be :
>> >>> | CPU0 | CPU1 | CPU2 | CPU3 |
>> >>> -----------------------------------
>> >>> buddy | CPU0 | CPU0 | CPU0 | CPU2 |
>> >>
>> >> ^
>> >> Is that a typo ? Should it be CPU2 instead of
>> >> CPU0 ?
>> >
>> > No it's not a typo.
>> > The system packs at each scheduling level. It starts to pack in
>> > cluster because each core can power gate independently so CPU1 tries
>> > to pack its tasks in CPU0 and CPU3 in CPU2. Then, it packs at CPU
>> > level so CPU2 tries to pack in the cluster of CPU0 and CPU0 packs in
>> > itself
>> >
>> I get it. Though in above example a task may migrate from say
>> CPU3->CPU2->CPU0 as part of packing. I was just thinking whether
>> moving such task from say CPU3 to CPU0 might be best instead.
>
> To me it seems suboptimal to pack the task twice, but the alternative is
> not good either. If you try to move the task directly to CPU0 you may
> miss packing opportunities if CPU0 is already busy, while CPU2 might
> have enough capacity to take it. It would probably be better to check
> the business of CPU0 and then back off and try CPU2 if CP0 is busy. This
> would require a buddy list for each CPU rather just a single buddy and
> thus might become expensive.
>
>>
>> >>
>> >>> Small tasks tend to slip out of the periodic load balance.
>> >>> The best place to choose to migrate them is at their wake up.
>> >>>
>> >> I have tried this series since I was looking at some of these packing
>> >> bits. On Mobile workloads like OSIdle with Screen ON, MP3, gallary,
>> >> I did see some additional filtering of threads with this series
>> >> but its not making much difference in power. More on this below.
>> >
>> > Can I ask you which configuration you have used ? how many cores and
>> > cluster ? Can they be power gated independently ?
>> >
>> I have been trying with couple of setups. Dual Core ARM machine and
>> Quad core X86 box with single package thought most of the mobile
>> workload analysis I was doing on ARM machine. On both setups
>> CPUs can be gated independently.
>>
>> >>
>> >>
>> >>> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
>> >>> ---
>> >>> kernel/sched/core.c | 1 +
>> >>> kernel/sched/fair.c | 109
>> >>> ++++++++++++++++++++++++++++++++++++++++++++++++++
>> >>> kernel/sched/sched.h | 1 +
>> >>> 3 files changed, 111 insertions(+)
>> >>>
>> >>> diff --git a/kernel/sched/core.c b/kernel/sched/core.c
>> >>> index dab7908..70cadbe 100644
>> >>> --- a/kernel/sched/core.c
>> >>> +++ b/kernel/sched/core.c
>> >>> @@ -6131,6 +6131,7 @@ cpu_attach_domain(struct sched_domain *sd, struct
>> >>> root_domain *rd, int cpu)
>> >>> rcu_assign_pointer(rq->sd, sd);
>> >>> destroy_sched_domains(tmp, cpu);
>> >>>
>> >>> + update_packing_domain(cpu);
>> >>> update_top_cache_domain(cpu);
>> >>> }
>> >>>
>> >>> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
>> >>> index 4f4a4f6..8c9d3ed 100644
>> >>> --- a/kernel/sched/fair.c
>> >>> +++ b/kernel/sched/fair.c
>> >>> @@ -157,6 +157,63 @@ void sched_init_granularity(void)
>> >>> update_sysctl();
>> >>> }
>> >>>
>> >>> +
>> >>> +/*
>> >>> + * Save the id of the optimal CPU that should be used to pack small tasks
>> >>> + * The value -1 is used when no buddy has been found
>> >>> + */
>> >>> +DEFINE_PER_CPU(int, sd_pack_buddy);
>> >>> +
>> >>> +/* Look for the best buddy CPU that can be used to pack small tasks
>> >>> + * We make the assumption that it doesn't wort to pack on CPU that share
>> >>> the
>> >>
>> >> s/wort/worth
>> >
>> > yes
>> >
>> >>
>> >>> + * same powerline. We looks for the 1st sched_domain without the
>> >>> + * SD_SHARE_POWERLINE flag. Then We look for the sched_group witht the
>> >>> lowest
>> >>> + * power per core based on the assumption that their power efficiency is
>> >>> + * better */
>> >>
>> >> Commenting style..
>> >> /*
>> >> *
>> >> */
>> >>
>> >
>> > yes
>> >
>> >> Can you please expand the why the assumption is right ?
>> >> "it doesn't wort to pack on CPU that share the same powerline"
>> >
>> > By "share the same power-line", I mean that the CPUs can't power off
>> > independently. So if some CPUs can't power off independently, it's
>> > worth to try to use most of them to race to idle.
>> >
>> In that case I suggest we use different word here. Power line can be
>> treated as voltage line, power domain.
>> May be SD_SHARE_CPU_POWERDOMAIN ?
>>
>
> How about just SD_SHARE_POWERDOMAIN ?
It looks better than SD_SHARE_POWERLINE. I will replace the name
>
>> >>
>> >> Think about a scenario where you have quad core, ducal cluster system
>> >>
>> >> |Cluster1| |cluster 2|
>> >> | CPU0 | CPU1 | CPU2 | CPU3 | | CPU0 | CPU1 | CPU2 | CPU3 |
>> >>
>> >>
>> >> Both clusters run from same voltage rail and have same PLL
>> >> clocking them. But the cluster have their own power domain
>> >> and all CPU's can power gate them-self to low power states.
>> >> Clusters also have their own level2 caches.
>> >>
>> >> In this case, you will still save power if you try to pack
>> >> load on one cluster. No ?
>> >
>> > yes, I need to update the description of SD_SHARE_POWERLINE because
>> > I'm afraid I was not clear enough. SD_SHARE_POWERLINE includes the
>> > power gating capacity of each core. For your example above, the
>> > SD_SHARE_POWERLINE shoud be cleared at both MC and CPU level.
>> >
>> Thanks for clarification.
>>
>> >>
>> >>
>> >>> +void update_packing_domain(int cpu)
>> >>> +{
>> >>> + struct sched_domain *sd;
>> >>> + int id = -1;
>> >>> +
>> >>> + sd = highest_flag_domain(cpu, SD_SHARE_POWERLINE);
>> >>> + if (!sd)
>> >>> + sd = rcu_dereference_check_sched_domain(cpu_rq(cpu)->sd);
>> >>> + else
>> >>> + sd = sd->parent;
>> >>> +
>> >>> + while (sd) {
>> >>> + struct sched_group *sg = sd->groups;
>> >>> + struct sched_group *pack = sg;
>> >>> + struct sched_group *tmp = sg->next;
>> >>> +
>> >>> + /* 1st CPU of the sched domain is a good candidate */
>> >>> + if (id == -1)
>> >>> + id = cpumask_first(sched_domain_span(sd));
>> >>> +
>> >>> + /* loop the sched groups to find the best one */
>> >>> + while (tmp != sg) {
>> >>> + if (tmp->sgp->power * sg->group_weight <
>> >>> + sg->sgp->power *
>> >>> tmp->group_weight)
>> >>> + pack = tmp;
>> >>> + tmp = tmp->next;
>> >>> + }
>> >>> +
>> >>> + /* we have found a better group */
>> >>> + if (pack != sg)
>> >>> + id = cpumask_first(sched_group_cpus(pack));
>> >>> +
>> >>> + /* Look for another CPU than itself */
>> >>> + if ((id != cpu)
>> >>> + || ((sd->parent) && !(sd->parent->flags &&
>> >>> SD_LOAD_BALANCE)))
>> >>
>> >> Is the condition "!(sd->parent->flags && SD_LOAD_BALANCE)" for
>> >> big.LITTLE kind of system where SD_LOAD_BALANCE may not be used ?
>> >
>> > No, packing small tasks is part of the load balance so if the
>> > LOAD_BALANCE flag is cleared, we will not try to pack which is a kind
>> > of load balance. There is no link with big.LITTLE
>> >
>> Now it make sense to me.
>>
>> >>
>> >>
>> >>> + break;
>> >>> +
>> >>> + sd = sd->parent;
>> >>> + }
>> >>> +
>> >>> + pr_info(KERN_INFO "CPU%d packing on CPU%d\n", cpu, id);
>> >>> + per_cpu(sd_pack_buddy, cpu) = id;
>> >>> +}
>> >>> +
>> >>> #if BITS_PER_LONG == 32
>> >>> # define WMULT_CONST (~0UL)
>> >>> #else
>> >>> @@ -3073,6 +3130,55 @@ static int select_idle_sibling(struct task_struct
>> >>> *p, int target)
>> >>> return target;
>> >>> }
>> >>>
>> >>> +static inline bool is_buddy_busy(int cpu)
>> >>> +{
>> >>> + struct rq *rq = cpu_rq(cpu);
>> >>> +
>> >>> + /*
>> >>> + * A busy buddy is a CPU with a high load or a small load with a
>> >>> lot of
>> >>> + * running tasks.
>> >>> + */
>> >>> + return ((rq->avg.usage_avg_sum << rq->nr_running) >
>> >>> + rq->avg.runnable_avg_period);
>> >>
>> >> I agree busy CPU is the one with high load, but many small threads may
>> >> not make CPU fully busy, right ? Should we just stick to the load
>> >> parameter alone here ?
>> >
>> > IMO, the busy state of a CPU isn't only the load but also how many
>> > threads are waiting for running on it. This formula tries to take into
>> > account both inputs. If you have dozen of small tasks on a CPU, the
>> > latency can be large even if the tasks are small.
>> >
>> Sure. Your point is to avoid throttling and probably use race for
>> idle.
>>
>> >>
>> >>
>> >>> +}
>> >>> +
>> >>> +static inline bool is_light_task(struct task_struct *p)
>> >>> +{
>> >>> + /* A light task runs less than 25% in average */
>> >>> + return ((p->se.avg.usage_avg_sum << 2) <
>> >>> p->se.avg.runnable_avg_period);
>> >>> +}
>> >>
>> >> Since the whole packing logic relies on the light threads only, the
>> >> overall effectiveness is not significant. Infact with multiple tries on
>> >> Dual core system, I didn't see any major improvement in power. I think
>> >> we need to be more aggressive here. From the cover letter, I noticed
>> >> that, you were concerned about any performance drop due to packing and
>> >> may be that is the reason you chose the conservative threshold. But the
>> >> fact is, if we want to save meaningful power, there will be slight
>> >> performance drop which is expected.
>> >
>> > I think that everybody agrees that packing small tasks will save power
>> > whereas it seems to be not so obvious for heavy task. But I may have
>> > set the threshold a bit too low
>> >
>> I agree on packing saves power part for sure.
>>
>
> I'm not fully convinced that packing always saves power. For systems
> with multiple cpu clusters where each cluster is a power domain and the
> cpus have no individual power saving states it would probably be more
> power efficient to spread the tasks and hope for more opportunities for
> hitting cluster shutdown. If all tasks are packed on one cpu it will
> keep the whole cluster up, while the remaining cpus are idling without
> possibility for entering efficient power states.
>
> Regards,
> Morten
>
>> > Up to which load, you would like to pack on 1 core of your dual core system ?
>> > Can you provide more details of your load ? Have you got a trace that
>> > you can share ?
>> >
>> More than how much load to pack, I was more looking from the power
>> savings delta we can achieve by doing it. Some of the usecases like
>> osidle, mp3, gallary are already very low power and that might be
>> the reason I didn't notice major mA delta. Though the perf
>> traces did show some filtering even at 25 % load. i tried upto
>> 50 % threshold to see the effectiveness and there was more
>> improvement and hence the suggestion about aggressiveness.
>>
>> May be you can try some of these use-cases on your setup instead of
>> synthetic workload and see the results.
>>
>> Regards
>> Santosh
>>
>>
>>
>>
>> _______________________________________________
>> linaro-dev mailing list
>> linaro-dev at lists.linaro.org
>> http://lists.linaro.org/mailman/listinfo/linaro-dev
>>
>
^ permalink raw reply
* [PATCH] ARM: implement optimized percpu variable access
From: Will Deacon @ 2012-11-12 13:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A0F390.7060800@gmail.com>
On Mon, Nov 12, 2012 at 01:03:12PM +0000, Rob Herring wrote:
> On 11/12/2012 04:23 AM, Will Deacon wrote:
> >> +static inline void set_my_cpu_offset(unsigned long off)
> >> +{
> >> + asm volatile("mcr p15, 0, %0, c13, c0, 4 @ set TPIDRPRW" : : "r" (off) : "cc" );
> >> +}
> >
> > You don't need the "cc" here.
>
> You would think so, but the compiler drops this instruction if you
> don't. set_cr does the same thing.
Whoa, that sounds suspicious... if the thing is marked volatile GCC
shouldn't optimise it away if it's reachable. Which toolchain are you
using?
Will
^ permalink raw reply
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