* [PATCH v6 4/7] arm: mvebu: add Ethernet controllers using mvneta driver for Armada 370/XP
From: Thomas Petazzoni @ 2012-11-13 15:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352818843-4457-1-git-send-email-thomas.petazzoni@free-electrons.com>
The Armada 370 SoC has two network units, while the Armada XP has four
network units. The first two network units are common to both the
Armada XP and Armada 370, so they are added to armada-370-xp.dtsi,
while the other two network units are specific to the Armada XP and
therefore added to armada-xp.dtsi.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/boot/dts/armada-370-xp.dtsi | 21 +++++++++++++++++++++
arch/arm/boot/dts/armada-xp.dtsi | 14 ++++++++++++++
2 files changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index b113e0b..0cd3331 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -68,6 +68,27 @@
compatible = "marvell,armada-addr-decoding-controller";
reg = <0xd0020000 0x258>;
};
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0xd0072004 0x4>;
+ };
+
+ ethernet at d0070000 {
+ compatible = "marvell,armada-370-neta";
+ reg = <0xd0070000 0x2500>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ ethernet at d0074000 {
+ compatible = "marvell,armada-370-neta";
+ reg = <0xd0074000 0x2500>;
+ interrupts = <10>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 71d6b5d..3bbbccf 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -51,5 +51,19 @@
compatible = "marvell,armada-370-xp-system-controller";
reg = <0xd0018200 0x500>;
};
+
+ ethernet at d0030000 {
+ compatible = "marvell,armada-370-neta";
+ reg = <0xd0030000 0x2500>;
+ interrupts = <12>;
+ status = "disabled";
+ };
+
+ ethernet at d0034000 {
+ compatible = "marvell,armada-370-neta";
+ reg = <0xd0034000 0x2500>;
+ interrupts = <14>;
+ status = "disabled";
+ };
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH v6 5/7] arm: mvebu: enable Ethernet controllers on Armada 370/XP eval boards
From: Thomas Petazzoni @ 2012-11-13 15:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352818843-4457-1-git-send-email-thomas.petazzoni@free-electrons.com>
This patch enables the two network interfaces of the Armada 370
official Marvell evaluation platform, and the four network interfaces
of the Armada XP official Marvell evaluation platform.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/boot/dts/armada-370-db.dts | 23 +++++++++++++++++++
arch/arm/boot/dts/armada-xp-db.dts | 43 +++++++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index fffd5c2..76362f7 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -38,5 +38,28 @@
clock-frequency = <600000000>;
status = "okay";
};
+
+ mdio {
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ };
+ };
+
+ ethernet at d0070000 {
+ clock-frequency = <200000000>;
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+ ethernet at d0074000 {
+ clock-frequency = <200000000>;
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index b1fc728..b614bd0 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -46,5 +46,48 @@
clock-frequency = <250000000>;
status = "okay";
};
+
+ mdio {
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy at 2 {
+ reg = <25>;
+ };
+
+ phy3: ethernet-phy at 3 {
+ reg = <27>;
+ };
+ };
+
+ ethernet at d0070000 {
+ clock-frequency = <250000000>;
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+ ethernet at d0074000 {
+ clock-frequency = <250000000>;
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ };
+ ethernet at d0030000 {
+ clock-frequency = <250000000>;
+ status = "okay";
+ phy = <&phy2>;
+ phy-mode = "sgmii";
+ };
+ ethernet at d0034000 {
+ clock-frequency = <250000000>;
+ status = "okay";
+ phy = <&phy3>;
+ phy-mode = "sgmii";
+ };
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH v6 6/7] arm: mvebu: enable Ethernet controllers on OpenBlocks AX3-4 platform
From: Thomas Petazzoni @ 2012-11-13 15:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352818843-4457-1-git-send-email-thomas.petazzoni@free-electrons.com>
The PlatHome OpenBlocks AX3-4 platform has 4 Ethernet ports, connected
to a single quad-port PHY through SGMII.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index cb86853..bb8d83c 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -65,5 +65,48 @@
linux,default-trigger = "heartbeat";
};
};
+
+ mdio {
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy at 2 {
+ reg = <2>;
+ };
+
+ phy3: ethernet-phy at 3 {
+ reg = <3>;
+ };
+ };
+
+ ethernet at d0070000 {
+ clock-frequency = <250000000>;
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "sgmii";
+ };
+ ethernet at d0074000 {
+ clock-frequency = <250000000>;
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "sgmii";
+ };
+ ethernet at d0030000 {
+ clock-frequency = <250000000>;
+ status = "okay";
+ phy = <&phy2>;
+ phy-mode = "sgmii";
+ };
+ ethernet at d0034000 {
+ clock-frequency = <250000000>;
+ status = "okay";
+ phy = <&phy3>;
+ phy-mode = "sgmii";
+ };
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH v6 7/7] arm: mvebu: enable Ethernet controllers on Mirabox platform
From: Thomas Petazzoni @ 2012-11-13 15:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352818843-4457-1-git-send-email-thomas.petazzoni@free-electrons.com>
The Globalscale Mirabox platform has two Ethernet interfaces,
connected to the SoC with a RGMII interface.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/boot/dts/armada-370-mirabox.dts | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 9eef8dd..8554dbe 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -33,5 +33,26 @@
clock-frequency = <600000000>;
status = "okay";
};
+ mdio {
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ };
+ };
+ ethernet at d0070000 {
+ clock-frequency = <200000000>;
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+ ethernet at d0074000 {
+ clock-frequency = <200000000>;
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ };
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH] ARM: add get_user() support for 8 byte types
From: Rob Clark @ 2012-11-13 15:00 UTC (permalink / raw)
To: linux-arm-kernel
From: Rob Clark <rob@ti.com>
A new atomic modeset/pageflip ioctl being developed in DRM requires
get_user() to work for 64bit types (in addition to just put_user()).
v1: original
v2: pass correct size to check_uaccess, and better handling of narrowing
double word read with __get_user_xb() (Russell King's suggestion)
Signed-off-by: Rob Clark <rob@ti.com>
---
arch/arm/include/asm/uaccess.h | 18 +++++++++++++++++-
arch/arm/lib/getuser.S | 17 ++++++++++++++++-
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 7e1f760..e2236ad 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -100,6 +100,7 @@ static inline void set_fs(mm_segment_t fs)
extern int __get_user_1(void *);
extern int __get_user_2(void *);
extern int __get_user_4(void *);
+extern int __get_user_8(void *);
#define __GUP_CLOBBER_1 "lr", "cc"
#ifdef CONFIG_CPU_USE_DOMAINS
@@ -108,6 +109,7 @@ extern int __get_user_4(void *);
#define __GUP_CLOBBER_2 "lr", "cc"
#endif
#define __GUP_CLOBBER_4 "lr", "cc"
+#define __GUP_CLOBBER_8 "lr", "cc"
#define __get_user_x(__r2,__p,__e,__l,__s) \
__asm__ __volatile__ ( \
@@ -118,11 +120,19 @@ extern int __get_user_4(void *);
: "0" (__p), "r" (__l) \
: __GUP_CLOBBER_##__s)
+/* narrowing a double-word get into a single 32bit word register: */
+#ifdef BIG_ENDIAN
+#define __get_user_xb(__r2,__p,__e,__l,__s) \
+ __get_user_x(__r2,(uintptr_t)__p + 4,__e,__l,__s)
+#else
+#define __get_user_xb __get_user_x
+#endif
+
#define __get_user_check(x,p) \
({ \
unsigned long __limit = current_thread_info()->addr_limit - 1; \
register const typeof(*(p)) __user *__p asm("r0") = (p);\
- register unsigned long __r2 asm("r2"); \
+ register typeof(x) __r2 asm("r2"); \
register unsigned long __l asm("r1") = __limit; \
register int __e asm("r0"); \
switch (sizeof(*(__p))) { \
@@ -135,6 +145,12 @@ extern int __get_user_4(void *);
case 4: \
__get_user_x(__r2, __p, __e, __l, 4); \
break; \
+ case 8: \
+ if (sizeof((x)) < 8) \
+ __get_user_xb(__r2, __p, __e, __l, 4); \
+ else \
+ __get_user_x(__r2, __p, __e, __l, 8); \
+ break; \
default: __e = __get_user_bad(); break; \
} \
x = (typeof(*(p))) __r2; \
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index 9b06bb4..ed98707 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -18,7 +18,7 @@
* Inputs: r0 contains the address
* r1 contains the address limit, which must be preserved
* Outputs: r0 is the error code
- * r2 contains the zero-extended value
+ * r2, r3 contains the zero-extended value
* lr corrupted
*
* No other registers must be altered. (see <asm/uaccess.h>
@@ -66,6 +66,19 @@ ENTRY(__get_user_4)
mov pc, lr
ENDPROC(__get_user_4)
+ENTRY(__get_user_8)
+ check_uaccess r0, 8, r1, r2, __get_user_bad
+#ifdef CONFIG_THUMB2_KERNEL
+5: TUSER(ldr) r2, [r0]
+6: TUSER(ldr) r3, [r0, #4]
+#else
+5: TUSER(ldr) r2, [r0], #4
+6: TUSER(ldr) r3, [r0]
+#endif
+ mov r0, #0
+ mov pc, lr
+ENDPROC(__get_user_8)
+
__get_user_bad:
mov r2, #0
mov r0, #-EFAULT
@@ -77,4 +90,6 @@ ENDPROC(__get_user_bad)
.long 2b, __get_user_bad
.long 3b, __get_user_bad
.long 4b, __get_user_bad
+ .long 5b, __get_user_bad
+ .long 6b, __get_user_bad
.popsection
--
1.8.0
^ permalink raw reply related
* [PATCH V2 4/5] arm: mm: Added support for PJ4B cpu and init routines
From: Gregory CLEMENT @ 2012-11-13 15:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351545108-18954-5-git-send-email-gregory.clement@free-electrons.com>
Russell,
Do you have any comments on this patch?
Else do you agree to give your acked-by?
Thanks,
Gregory
On 10/29/2012 10:11 PM, Gregory CLEMENT wrote:
> From: Yehuda Yitschak <yehuday@marvell.com>
>
> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
> arch/arm/mach-mvebu/Kconfig | 2 +-
> arch/arm/mm/Kconfig | 4 ++++
> arch/arm/mm/proc-v7.S | 43 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 48 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index 17d246b..9bfaa0c 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -22,7 +22,7 @@ config MVEBU_CLK_CPU
> config MACH_ARMADA_370_XP
> bool
> select ARMADA_370_XP_TIMER
> - select CPU_V7
> + select CPU_PJ4B
>
> config MACH_ARMADA_370
> bool "Marvell Armada 370 boards"
> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> index 94186b6..3fd629d 100644
> --- a/arch/arm/mm/Kconfig
> +++ b/arch/arm/mm/Kconfig
> @@ -352,6 +352,10 @@ config CPU_PJ4
> select ARM_THUMBEE
> select CPU_V7
>
> +config CPU_PJ4B
> + bool
> + select CPU_V7
> +
> # ARMv6
> config CPU_V6
> bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 846d279..1a373c2 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -169,6 +169,39 @@ __v7_ca15mp_setup:
> orreq r0, r0, r10 @ Enable CPU-specific SMP bits
> mcreq p15, 0, r0, c1, c0, 1
> #endif
> +
> +__v7_pj4b_setup:
> +#ifdef CONFIG_CPU_PJ4B
> + /* Auxiliary Debug Modes Control 1 Register */
> + mrc p15, 1, r0, c15, c1, 1
> + orr r0, r0, #(1 << 16) @ Disable data transfer for clean line.
> + orr r0, r0, #(1 << 5) @ Enable the back off of STREX instr
> + orr r0, r0, #(1 << 8) @ Disable Internal Parity Handling
> + bic r0, r0, #(1 << 2) @ Disable Static BP
> + mcr p15, 1, r0, c15, c1, 1
> +
> + /* Auxiliary Debug Modes Control 2 Register */
> + mrc p15, 1, r0, c15, c1, 2
> + bic r0, r0, #(1 << 23) @ Enable fast LDR.
> + orr r0, r0, #(1 << 25) @ Dont interleave write and snoop data.
> + orr r0, r0, #(1 << 27) @ Disable Critical Word First feature.
> + orr r0, r0, #(1 << 29) @ Disable outstanding non cacheable request
> + orr r0, r0, #(1 << 30) @ L1 replacement - Strict round robin
> + mcr p15, 1, r0, c15, c1, 2
> +
> + /* Auxiliary Functional Modes Control Register 0 */
> + mrc p15, 1, r0, c15, c2, 0
> + orr r0, r0, #(1 << 2) @ Support L1 parity checking
> + orr r0, r0, #(1 << 8) @ Broadcast Cache and TLB maintenance
> + mcr p15, 1, r0, c15, c2, 0
> +
> + /* Auxiliary Debug Modes Control 0 Register */
> + mrc p15, 1, r0, c15, c1, 0
> + orr r0, r0, #(1 << 22) @ WFI/WFE - serve the DVM and back to idle
> + mcr p15, 1, r0, c15, c1, 0
> +
> +#endif /* CONFIG_CPU_PJ4B */
> +
> __v7_setup:
> adr r12, __v7_setup_stack @ the local stack
> stmia r12, {r0-r5, r7, r9, r11, lr}
> @@ -342,6 +375,16 @@ __v7_ca9mp_proc_info:
> .long 0xff0ffff0
> __v7_proc __v7_ca9mp_setup
> .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
> +
> + /*
> + * Marvell PJ4B processor.
> + */
> + .type __v7_pj4b_proc_info, #object
> +__v7_pj4b_proc_info:
> + .long 0x562f5842
> + .long 0xffffffff
> + __v7_proc __v7_pj4b_setup
> + .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
> #endif /* CONFIG_ARM_LPAE */
>
> /*
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* OMAP baseline test results for v3.7-rc3
From: Mark Jackson @ 2012-11-13 15:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5098DC9E.3090307@mimc.co.uk>
On 06/11/12 09:47, Mark Jackson wrote:
> On 06/11/12 06:16, Hiremath, Vaibhav wrote:
>>
>> Where is your DTB? Is it appended to Kernel image?
>> Can you try below sequence/commands from u-boot?
>>
>>
>> mmc rescan 0
>> fatload mmc 0 80000000 am335x-bone.dtb
>> fatload mmc 0 81000000 uImage
>> setenv bootargs console=ttyO0,115200n8 mem=256M root=/dev/mmcblk0p2 rw noinitrd rootfstype=ext3 rootwait earlyprink=serial
>> sendln 'bootm 81000000 - 80000000'
>>
>>
>>
>> To build DTB files, use "make dtbs" command on your kernel home directory.
>
> That works ... great !!
>
> But now I'm confused, since I thought the DTB was appended to the uImage file.
>
> I have the following in my .config:-
>
> ARM_ATAG_DTB_COMPAT=y
> ARM_APPENDED_DTB=y
> ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
>
> And then I create my uImage file using:-
>
> $ make -j 8 ARCH=arm CROSS_COMPILE=arm-linux- uImage
> $ make -j 8 ARCH=arm CROSS_COMPILE=arm-linux- am335x-bone.dtb
> $ cat arch/arm/boot/uImage arch/arm/boot/am335x-bone.dtb > arch/arm/boot/uImage-dtb.am335x-bone
> $ cp arch/arm/boot/uImage-dtb.am335x-bone /media/boot/uImage
>
> Do you now have to load the DTB as a separate file ?
>
> Or should the appended DTB still work ?
Any update on this ?
Cheers
Mark J.
^ permalink raw reply
* [PATCH v6 2/7] net: mvneta: driver for Marvell Armada 370/XP network unit
From: Joe Perches @ 2012-11-13 15:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352818843-4457-3-git-send-email-thomas.petazzoni@free-electrons.com>
On Tue, 2012-11-13 at 16:00 +0100, Thomas Petazzoni wrote:
> This patch contains a new network driver for the network unit of the
> ARM Marvell Armada 370 and the Armada XP. Both SoCs use the PJ4B
> processor, a Marvell-developed ARM core that implements the ARMv7
> instruction set.
This looks very clean to me.
trivial:
some of the logging doesn't use terminating newlines.
> +static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
> +{
[]
> + if (mtu > 9676) {
> + netdev_info(dev, "Illegal MTU value %d, round to 9676", mtu);
[]
> + if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
> + netdev_info(dev, "Illegal MTU value %d, rounding to %d",
missing newlines
> +static int __devinit mvneta_probe(struct platform_device *pdev)
[]
> + if (register_netdev(dev)) {
> + dev_err(&pdev->dev, "failed to register\n");
> + err = ENOMEM;
> + goto err_base;
> + }
[]
> + dev_info(&pdev->dev, "%s, mac: %pM\n", dev->name,
> + dev->dev_addr);
You could use netdev_info here
netdev_info(dev, "mac: %pM\n", dev->dev_addr);
^ permalink raw reply
* OMAP baseline test results for v3.7-rc3
From: Paul Walmsley @ 2012-11-13 15:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A266C2.4030303@mimc.co.uk>
On Tue, 13 Nov 2012, Mark Jackson wrote:
> On 06/11/12 09:47, Mark Jackson wrote:
>
> > That works ... great !!
> >
> > But now I'm confused, since I thought the DTB was appended to the uImage file.
The DTB is appended to the zImage file. You then need to convert the
product of the concatenation to uImage format.
So ...
> > I have the following in my .config:-
> >
> > ARM_ATAG_DTB_COMPAT=y
> > ARM_APPENDED_DTB=y
> > ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
> >
> > And then I create my uImage file using:-
> >
> > $ make -j 8 ARCH=arm CROSS_COMPILE=arm-linux- uImage
> > $ make -j 8 ARCH=arm CROSS_COMPILE=arm-linux- am335x-bone.dtb
instead of this:
> > $ cat arch/arm/boot/uImage arch/arm/boot/am335x-bone.dtb > arch/arm/boot/uImage-dtb.am335x-bone
> > $ cp arch/arm/boot/uImage-dtb.am335x-bone /media/boot/uImage
something like this is what you need to do instead:
$ cat arch/arm/boot/zImage arch/arm/boot/am335x-bone.dtb > arch/arm/boot/zImage-dtb.am335x-bone
$ scripts/mkuboot.sh -A arm -O linux -C none -T kernel -a 0x80008000 -e 0x80008000 -n 'Linux' -d arch/arm/boot/zImage-dtb.am335x-bone arch/arm/boot/uImage-dtb.am335x-bone
> > Do you now have to load the DTB as a separate file ?
> >
> > Or should the appended DTB still work ?
Appended DTBs work fine on the testbed here.
- Paul
^ permalink raw reply
* [PATCH v2] i2c: at91: fix SMBus quick command
From: ludovic.desroches at atmel.com @ 2012-11-13 15:43 UTC (permalink / raw)
To: linux-arm-kernel
From: Ludovic Desroches <ludovic.desroches@atmel.com>
The driver claims to support SMBus quick command but it was not the case.
This patch fixes this issue.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
---
Hi Wolfram,
Thanks to Jean explanation about i2cdetect and eeprom behavior, I realized
that the first version of the patch was incorrect. This time all the i2c
devices are detected with i2cdetect -q.
I hope this fix could go into 3.7 since the driver claims SMBus quick
capability but it doesn't support it. Moreover without it i2cdetect find
imaginary devices, and with some IP versions, trying to send 0 byte can cause
issue when writing data to an EEPROM.
Regards
Ludovic
Changes since v1:
* enable txcomp irq to have a correct behavior
drivers/i2c/busses/i2c-at91.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index f471747..e9c926c 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -44,6 +44,7 @@
#define AT91_TWI_STOP 0x0002 /* Send a Stop Condition */
#define AT91_TWI_MSEN 0x0004 /* Master Transfer Enable */
#define AT91_TWI_SVDIS 0x0020 /* Slave Transfer Disable */
+#define AT91_TWI_QUICK 0x0040 /* SMBus quick command */
#define AT91_TWI_SWRST 0x0080 /* Software Reset */
#define AT91_TWI_MMR 0x0004 /* Master Mode Register */
@@ -386,7 +387,11 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
INIT_COMPLETION(dev->cmd_complete);
dev->transfer_status = 0;
- if (dev->msg->flags & I2C_M_RD) {
+
+ if (!dev->buf_len) {
+ at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
+ at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
+ } else if (dev->msg->flags & I2C_M_RD) {
unsigned start_flags = AT91_TWI_START;
if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
--
1.7.11.3
^ permalink raw reply related
* [PATCH v2 0/3] GPIO driver to turn power off
From: Andrew Lunn @ 2012-11-13 15:44 UTC (permalink / raw)
To: linux-arm-kernel
A few of the Kirkwood systems use a GPIO line to turn the power off on
shutdown. They request the GPIO line in the board setup code,
optionally setting it as an output and driving it inactive. They then
register a function for pm_power_off. At the end of the shutdown, this
function is called. The GPIO line is configured as an output, if not
already so, and then driven active. In order to cover the use case of
edges rather then levels, triggering power off, the GPIO line is then
toggled active and later inactive. This should allow the driver to be
used by PXA which also has boards using the same scheme.
The driver code was initially developed by Jamie Lentin and extended
to cover the PXA case by Andrew Lunn.
v1 -> v2: Moved to drivers/power/reset
Andrew Lunn (2):
ARM: Kirkwood: Convert DNSKW to use gpio-poweroff.
ARM: Kirkwood: Convert IB62x0 to use gpio-poweroff.
Jamie Lentin (1):
power: Add simple poweroff-gpio driver
.../devicetree/bindings/gpio/gpio-poweroff.txt | 22 ++++
arch/arm/boot/dts/kirkwood-dnskw.dtsi | 5 +
arch/arm/boot/dts/kirkwood-ib62x0.dts | 6 +
arch/arm/mach-kirkwood/Kconfig | 4 +
arch/arm/mach-kirkwood/board-dnskw.c | 12 --
arch/arm/mach-kirkwood/board-ib62x0.c | 13 --
drivers/power/Kconfig | 3 +
drivers/power/Makefile | 1 +
drivers/power/reset/Kconfig | 15 +++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/gpio-poweroff.c | 129 ++++++++++++++++++++
11 files changed, 186 insertions(+), 25 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
create mode 100644 drivers/power/reset/Kconfig
create mode 100644 drivers/power/reset/Makefile
create mode 100644 drivers/power/reset/gpio-poweroff.c
--
1.7.10.4
^ permalink raw reply
* [PATCH v2 1/3] power: Add simple poweroff-gpio driver
From: Andrew Lunn @ 2012-11-13 15:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352821485-10032-1-git-send-email-andrew@lunn.ch>
From: Jamie Lentin <jm@lentin.co.uk>
Given appropriate devicetree bindings, this driver registers a
pm_power_off function to set a GPIO line high/low to power down
your board.
Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
.../devicetree/bindings/gpio/gpio-poweroff.txt | 22 ++++
drivers/power/Kconfig | 3 +
drivers/power/Makefile | 1 +
drivers/power/reset/Kconfig | 15 +++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/gpio-poweroff.c | 129 ++++++++++++++++++++
6 files changed, 171 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
create mode 100644 drivers/power/reset/Kconfig
create mode 100644 drivers/power/reset/Makefile
create mode 100644 drivers/power/reset/gpio-poweroff.c
diff --git a/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt b/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
new file mode 100644
index 0000000..558cdf3
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
@@ -0,0 +1,22 @@
+GPIO line that should be set high/low to power off a device
+
+Required properties:
+- compatible : should be "gpio-poweroff".
+- gpios : The GPIO to set high/low, see "gpios property" in
+ Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be
+ low to power down the board set it to "Active Low", otherwise set
+ gpio to "Active High".
+
+Optional properties:
+- input : Initially configure the GPIO line as an input. Only reconfigure
+ it to an output when the pm_power_off function is called. If this optional
+ property is not specified, the GPIO is initialized as an output in its
+ inactive state.
+
+
+Examples:
+
+gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio 4 0>; /* GPIO 4 Active Low */
+};
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 49a8939..b1d956d 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -335,6 +335,9 @@ config AB8500_BATTERY_THERM_ON_BATCTRL
help
Say Y to enable battery temperature measurements using
thermistor connected on BATCTRL ADC.
+
+source "drivers/power/reset/Kconfig"
+
endif # POWER_SUPPLY
source "drivers/power/avs/Kconfig"
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index b949cf8..f1d99f4 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_CHARGER_MAX8997) += max8997_charger.o
obj-$(CONFIG_CHARGER_MAX8998) += max8998_charger.o
obj-$(CONFIG_POWER_AVS) += avs/
obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o
+obj-$(CONFIG_POWER_RESET) += reset/
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
new file mode 100644
index 0000000..6461b48
--- /dev/null
+++ b/drivers/power/reset/Kconfig
@@ -0,0 +1,15 @@
+menuconfig POWER_RESET
+ bool "Board level reset or power off"
+ help
+ Provides a number of drivers which either reset a complete board
+ or shut it down, by manipulating the main power supply on the board.
+
+ Say Y here to enable board reset and power off
+
+config POWER_RESET_GPIO
+ bool "GPIO power-off driver"
+ depends on OF_GPIO && POWER_RESET
+ help
+ This driver supports turning off your board via a GPIO line.
+ If your board needs a GPIO high/low to power down, say Y and
+ create a binding in your devicetree.
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
new file mode 100644
index 0000000..751488a
--- /dev/null
+++ b/drivers/power/reset/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
diff --git a/drivers/power/reset/gpio-poweroff.c b/drivers/power/reset/gpio-poweroff.c
new file mode 100644
index 0000000..101ad57
--- /dev/null
+++ b/drivers/power/reset/gpio-poweroff.c
@@ -0,0 +1,129 @@
+/*
+ * Toggles a GPIO pin to power down a device
+ *
+ * Jamie Lentin <jm@lentin.co.uk>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * Copyright (C) 2012 Jamie Lentin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
+#include <linux/module.h>
+
+/*
+ * Hold configuration here, cannot be more than one instance of the driver
+ * since pm_power_off itself is global.
+ */
+static int gpio_num = -1;
+static int gpio_active_low;
+
+static void gpio_poweroff_do_poweroff(void)
+{
+ BUG_ON(gpio_num == -1);
+
+ /* drive it active */
+ gpio_direction_output(gpio_num, !gpio_active_low);
+ mdelay(100);
+ /* rising edge or drive inactive */
+ gpio_set_value(gpio_num, gpio_active_low);
+ mdelay(100);
+ /* falling edge */
+ gpio_set_value(gpio_num, !gpio_active_low);
+
+ /* give it some time */
+ mdelay(100);
+
+ WARN_ON(1);
+}
+
+static int __devinit gpio_poweroff_probe(struct platform_device *pdev)
+{
+ enum of_gpio_flags flags;
+ bool input = false;
+ int ret;
+
+ /* If a pm_power_off function has already been added, leave it alone */
+ if (pm_power_off != NULL) {
+ pr_err("%s: pm_power_off function already registered",
+ __func__);
+ return -EBUSY;
+ }
+
+ gpio_num = of_get_gpio_flags(pdev->dev.of_node, 0, &flags);
+ if (gpio_num < 0) {
+ pr_err("%s: Could not get GPIO configuration: %d",
+ __func__, gpio_num);
+ return -ENODEV;
+ }
+ gpio_active_low = flags & OF_GPIO_ACTIVE_LOW;
+
+ if (of_get_property(pdev->dev.of_node, "input", NULL))
+ input = true;
+
+ ret = gpio_request(gpio_num, "poweroff-gpio");
+ if (ret) {
+ pr_err("%s: Could not get GPIO %d", __func__, gpio_num);
+ return ret;
+ }
+ if (input) {
+ if (gpio_direction_input(gpio_num)) {
+ pr_err("Could not set direction of GPIO %d to input",
+ gpio_num);
+ goto err;
+ }
+ } else {
+ if (gpio_direction_output(gpio_num, gpio_active_low)) {
+ pr_err("Could not set direction of GPIO %d", gpio_num);
+ goto err;
+ }
+ }
+
+ pm_power_off = &gpio_poweroff_do_poweroff;
+ return 0;
+
+err:
+ gpio_free(gpio_num);
+ return -ENODEV;
+}
+
+static int __devexit gpio_poweroff_remove(struct platform_device *pdev)
+{
+ if (gpio_num != -1)
+ gpio_free(gpio_num);
+ if (pm_power_off == &gpio_poweroff_do_poweroff)
+ pm_power_off = NULL;
+
+ return 0;
+}
+
+static const struct of_device_id of_gpio_poweroff_match[] = {
+ { .compatible = "gpio-poweroff", },
+ {},
+};
+
+static struct platform_driver gpio_poweroff_driver = {
+ .probe = gpio_poweroff_probe,
+ .remove = __devexit_p(gpio_poweroff_remove),
+ .driver = {
+ .name = "poweroff-gpio",
+ .owner = THIS_MODULE,
+ .of_match_table = of_gpio_poweroff_match,
+ },
+};
+
+module_platform_driver(gpio_poweroff_driver);
+
+MODULE_AUTHOR("Jamie Lentin <jm@lentin.co.uk>");
+MODULE_DESCRIPTION("GPIO poweroff driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:poweroff-gpio");
--
1.7.10.4
^ permalink raw reply related
* [PATCH v2 2/3] ARM: Kirkwood: Convert DNSKW to use gpio-poweroff.
From: Andrew Lunn @ 2012-11-13 15:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352821485-10032-1-git-send-email-andrew@lunn.ch>
Also enable the gpio-poweroff driver when DT is used.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jamie Lentin <jm@lentin.co.uk>
---
arch/arm/boot/dts/kirkwood-dnskw.dtsi | 5 +++++
arch/arm/mach-kirkwood/Kconfig | 4 ++++
arch/arm/mach-kirkwood/board-dnskw.c | 12 ------------
3 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 9b32d02..22aa07a 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -35,6 +35,11 @@
6000 2>;
};
+ gpio_poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio1 4 0>;
+ };
+
ocp at f1000000 {
sata at 80000 {
status = "okay";
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 50bca50..e0d26fe 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -46,7 +46,11 @@ config MACH_GURUPLUG
config ARCH_KIRKWOOD_DT
bool "Marvell Kirkwood Flattened Device Tree"
+ select POWER_SUPPLY
+ select POWER_RESET
+ select POWER_RESET_GPIO
select USE_OF
+
help
Say 'Y' here if you want your kernel to support the
Marvell Kirkwood using flattened device tree.
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 43d16d6..549369e 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -57,11 +57,6 @@ static unsigned int dnskw_mpp_config[] __initdata = {
0
};
-static void dnskw_power_off(void)
-{
- gpio_set_value(36, 1);
-}
-
/* Register any GPIO for output and set the value */
static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
{
@@ -81,13 +76,6 @@ void __init dnskw_init(void)
kirkwood_ehci_init();
kirkwood_ge00_init(&dnskw_ge00_data);
- /* Register power-off GPIO. */
- if (gpio_request(36, "dnskw:power:off") == 0
- && gpio_direction_output(36, 0) == 0)
- pm_power_off = dnskw_power_off;
- else
- pr_err("dnskw: failed to configure power-off GPIO\n");
-
/* Ensure power is supplied to both HDDs */
dnskw_gpio_register(39, "dnskw:power:sata0", 1);
dnskw_gpio_register(40, "dnskw:power:sata1", 1);
--
1.7.10.4
^ permalink raw reply related
* [PATCH v2 3/3] ARM: Kirkwood: Convert IB62x0 to use gpio-poweroff.
From: Andrew Lunn @ 2012-11-13 15:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352821485-10032-1-git-send-email-andrew@lunn.ch>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
arch/arm/boot/dts/kirkwood-ib62x0.dts | 6 ++++++
arch/arm/mach-kirkwood/board-ib62x0.c | 13 -------------
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 66794ed..9b0e2e3 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -79,4 +79,10 @@
gpios = <&gpio0 27 0>;
};
};
+ gpio_poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio0 24 1>;
+ };
+
+
};
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
index cfc47f8..7b8adf5 100644
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ b/arch/arm/mach-kirkwood/board-ib62x0.c
@@ -17,7 +17,6 @@
#include <linux/mtd/partitions.h>
#include <linux/ata_platform.h>
#include <linux/mv643xx_eth.h>
-#include <linux/gpio.h>
#include <linux/input.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -25,8 +24,6 @@
#include "common.h"
#include "mpp.h"
-#define IB62X0_GPIO_POWER_OFF 24
-
static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
};
@@ -49,11 +46,6 @@ static unsigned int ib62x0_mpp_config[] __initdata = {
0
};
-static void ib62x0_power_off(void)
-{
- gpio_set_value(IB62X0_GPIO_POWER_OFF, 1);
-}
-
void __init ib62x0_init(void)
{
/*
@@ -63,9 +55,4 @@ void __init ib62x0_init(void)
kirkwood_ehci_init();
kirkwood_ge00_init(&ib62x0_ge00_data);
- if (gpio_request(IB62X0_GPIO_POWER_OFF, "ib62x0:power:off") == 0 &&
- gpio_direction_output(IB62X0_GPIO_POWER_OFF, 0) == 0)
- pm_power_off = ib62x0_power_off;
- else
- pr_err("board-ib62x0: failed to configure power-off GPIO\n");
}
--
1.7.10.4
^ permalink raw reply related
* [PATCH v6 2/7] net: mvneta: driver for Marvell Armada 370/XP network unit
From: Thomas Petazzoni @ 2012-11-13 15:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352820622.24230.31.camel@joe-AO722>
Joe,
On Tue, 13 Nov 2012 07:30:22 -0800, Joe Perches wrote:
> On Tue, 2012-11-13 at 16:00 +0100, Thomas Petazzoni wrote:
> > This patch contains a new network driver for the network unit of the
> > ARM Marvell Armada 370 and the Armada XP. Both SoCs use the PJ4B
> > processor, a Marvell-developed ARM core that implements the ARMv7
> > instruction set.
>
> This looks very clean to me.
Thanks!
With the below fixes, may I get your formal Acked-by on the driver
patch?
> trivial:
> some of the logging doesn't use terminating newlines.
>
> > +static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
> > +{
> []
> > + if (mtu > 9676) {
> > + netdev_info(dev, "Illegal MTU value %d, round to 9676", mtu);
> []
> > + if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
> > + netdev_info(dev, "Illegal MTU value %d, rounding to %d",
>
> missing newlines
>
> > +static int __devinit mvneta_probe(struct platform_device *pdev)
> []
> > + if (register_netdev(dev)) {
> > + dev_err(&pdev->dev, "failed to register\n");
> > + err = ENOMEM;
> > + goto err_base;
> > + }
> []
> > + dev_info(&pdev->dev, "%s, mac: %pM\n", dev->name,
> > + dev->dev_addr);
>
> You could use netdev_info here
>
> netdev_info(dev, "mac: %pM\n", dev->dev_addr);
Thanks for those comments, I'll wait a bit to see if any other comment
shows up before tomorrow, and I'll send a v7 with those issues fixed.
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 2/3] ARM: prima2: Replace include linux/module.h with linux/export.h
From: Syam Sidhardhan @ 2012-11-13 15:49 UTC (permalink / raw)
To: linux-arm-kernel
include <linux/export.h> is the right to go here.
Signed-off-by: Syam Sidhardhan <s.syam@samsung.com>
---
arch/arm/mach-prima2/pm.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index fb5a791..f4a2270 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -9,7 +9,7 @@
#include <linux/kernel.h>
#include <linux/suspend.h>
#include <linux/slab.h>
-#include <linux/module.h>
+#include <linux/export.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
--
1.7.4.1
^ permalink raw reply related
* OMAP baseline test results for v3.7-rc3
From: Mark Jackson @ 2012-11-13 15:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1211131531430.22487@utopia.booyaka.com>
On 13/11/12 15:35, Paul Walmsley wrote:
>
> instead of this:
>
>>> $ cat arch/arm/boot/uImage arch/arm/boot/am335x-bone.dtb > arch/arm/boot/uImage-dtb.am335x-bone
>>> $ cp arch/arm/boot/uImage-dtb.am335x-bone /media/boot/uImage
>
> something like this is what you need to do instead:
>
> $ cat arch/arm/boot/zImage arch/arm/boot/am335x-bone.dtb > arch/arm/boot/zImage-dtb.am335x-bone
> $ scripts/mkuboot.sh -A arm -O linux -C none -T kernel -a 0x80008000 -e 0x80008000 -n 'Linux' -d arch/arm/boot/zImage-dtb.am335x-bone arch/arm/boot/uImage-dtb.am335x-bone
Works like a charm ... thanks.
Mark J.
^ permalink raw reply
* [PATCH v6 2/7] net: mvneta: driver for Marvell Armada 370/XP network unit
From: Joe Perches @ 2012-11-13 15:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121113164658.03ae12f8@skate>
On Tue, 2012-11-13 at 16:46 +0100, Thomas Petazzoni wrote:
> On Tue, 13 Nov 2012 07:30:22 -0800, Joe Perches wrote:
> > On Tue, 2012-11-13 at 16:00 +0100, Thomas Petazzoni wrote:
> > > This patch contains a new network driver for the network unit of the
> > > ARM Marvell Armada 370 and the Armada XP. Both SoCs use the PJ4B
> > > processor, a Marvell-developed ARM core that implements the ARMv7
> > > instruction set.
> >
> > This looks very clean to me.
>
> Thanks!
>
> With the below fixes, may I get your formal Acked-by on the driver
> patch?
Hi Thomas.
I'm not one that believe there's much value in acks.
I don't have a card, I didn't test it, so I don't
know that it works.
The code style/readability looks pretty good to me.
> > trivial:
> > some of the logging doesn't use terminating newlines.
> > You could use netdev_info
[]
> Thanks for those comments, I'll wait a bit to see if any other comment
> shows up before tomorrow, and I'll send a v7 with those issues fixed.
These trivialities aren't any kind of blocking issue.
Perhaps David will apply it as is and you could send
a follow up patch later.
^ permalink raw reply
* OMAP baseline test results for v3.7-rc5
From: Igor Mazanov @ 2012-11-13 16:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1211121921160.12551@utopia.booyaka.com>
Paul Walmsley wrote:
> Here are some basic OMAP test results for Linux v3.7-rc5.
> Logs and other details at:
>
> http://www.pwsan.com/omap/testlogs/test_v3.7-rc5/20121111081034/
>
>
> Passing tests
> -------------
>
> Boot to userspace (9/11): 2420n800, 2430sdp, 3517evm, 3530es3beagle,
> 3730beaglexm, 37xxevm, 4430es2panda, 5912osk, am335xbone
>
> PM ret/off, suspend + dynamic idle (2/4): 3730beaglexm, 37xxevm
>
>
> Failing tests: fixed by posted patches
> --------------------------------------
>
> Boot tests:
>
> * 3530ES3 Beagle: I2C timeouts during userspace init
> - Intermittent, appears on 5 out of 6 boots here
> - Aaro Koskinen observes this also on N900
> - Appears to be caused by commit 3db11feffc1ad2ab9dea27789e6b5b3032827adc
> - http://marc.info/?l=linux-arm-kernel&m=135071372426971&w=2
> - http://marc.info/?l=linux-omap&m=135197877112220&w=2
> - Revert posted, pending I2C maintainers:
> - http://marc.info/?l=linux-arm-kernel&m=135221953727077&w=2
>
> PM tests:
>
> * 3530es3beagle: hangs during off-mode dynamic idle test
> - Appears to be caused by commit 6c31b2150ff96755d24e0ab6d6fea08a7bf5c44c:
> - http://marc.info/?l=linux-omap&m=135075364705188&w=2
> - Fixed by http://www.spinics.net/lists/arm-kernel/msg202116.html
>
> Other:
>
> * 2420N800: powers down 30 seconds after boot
> - Presumably due to missing CBUS patches for watchdog control
> - http://lkml.org/lkml/2012/9/3/265
>
> * 4430es2panda: omap_hwmod: mcpdm: cannot be enabled for reset (3)
> - clock source is from an external I2C-controlled source
> - must skip reset until the switchover to hwmod late init
> - http://www.spinics.net/lists/arm-kernel/msg178138.html
>
>
> Failing tests: needing investigation
> ------------------------------------
>
> Boot tests:
>
> * CM-T3517: L3 in-band error with IPSS during boot
> - Cause unknown but see http://marc.info/?l=linux-omap&m=134833869730129&w=2
> - Longstanding issue; does not occur on the 3517EVM
>
> * 3517EVM & CM-T3517: boot hangs with NFS root
> - Likely some Kconfig, board file, and PM issues with EMAC
>
> * CM-T3517: boot hangs with MMC boot
> - Due to missing MMC setup in board file
>
> Other:
>
> * 4430es2panda: omap_hwmod: l3_instr: _wait_target_disable failed
> - Unknown cause; could be due to the lack of hierarchical enable/disable
> in hwmod code
> - Jon Hunter reports this does not appear with the same X-loader/bootloader
> on his 4430ES2.3 Panda, so could be ES-level dependent
>
>
> Failing tests: needing local investigation (may be due to testbed issues)
> -------------------------------------------------------------------------
>
> Boot tests:
>
> * AM335x Beaglebone: omap2plus_defconfig kernels don't boot
> - May be fixed now, pending retest:
> - http://marc.info/?l=linux-omap&m=135082257727502&w=2
> - Not yet part of the automated test suite
> * May be due to an old U-boot with FDT support problems used here?
> Pending local investigation and re-test
I have the same result with omap2plus_defconfig and kernel 3.7.0-rc5. I dumped
the kernel log buffer via JTAG and can send this log if it could be useful.
>
> * 4460pandaes: boot fails early
> - Appears to be due to X-loader problems here
> - Need to note the X-loader version so we know it's broken
>
> PM tests:
>
> * 3730 Beagle XM: does not serial wake from off-idle suspend when console
> UART doesn't clock gate ("debug ignore_loglevel")
> - Not shown in the current test logs; cause unknown
> - Pending re-test
>
>
> vmlinux object size
> (delta in bytes from test_v3.7-rc4 (3d70f8c617a436c7146ecb81df2265b4626dfe89)):
> text data bss total kernel
> +500 -8 0 +492 am33xx_only
> +456 +16 0 +472 n800_multi_omap2xxx
> +424 +16 0 +440 n800_only_a
> +164 0 0 +164 omap1_defconfig
> +164 0 0 +164 omap1_defconfig_1510innovator_only
> +164 0 0 +164 omap1_defconfig_5912osk_only
> +940 -8 0 +932 omap2plus_defconfig
> +796 -8 0 +788 omap2plus_defconfig_2430sdp_only
> +940 +24 0 +964 omap2plus_defconfig_cpupm
> +940 -8 0 +932 omap2plus_defconfig_no_pm
> +940 +16 0 +956 omap2plus_defconfig_omap2_4_only
> +820 +16 0 +836 omap2plus_defconfig_omap3_4_only
> +20 +8 +48 +76 rmk_omap3430_ldp_allnoconfig
> +124 0 0 +124 rmk_omap3430_ldp_oldconfig
> +20 +8 +48 +76 rmk_omap4430_sdp_allnoconfig
> +124 +8 0 +132 rmk_omap4430_sdp_oldconfig
>
>
> - Paul
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH 0/2] L2CC shared mutex with ARM TZ
From: Etienne CARRIERE @ 2012-11-13 16:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Etienne Carriere <etienne.carriere@stericsson.com>
Dear all,
A need for a shared mutex between linux and TrustZone has raised on ST-Ericsson ux500 platforms and coming ux600 platforms.
This patch series shows how we intend to modify ARM L2 cache driver to allow platforms to register a shared mutex between Linux and TrustZone code.
The 1st patch contains the target modifications in L2X0 driver in the kernel main track.
The 2nd patch (romcode-shared_mutex.c) is an example of how such feature could be used by platform specific code.
This patch does not target merge on kernel main track.
Patch were extracted from local kernel tree and may not apply straight on pristine kernel tree. I hope they clearly describe our purpose.
In the hope to get your feedback,
Regards.
Etienne Carriere (2)
arm: mm: l2cc external shared mutex support
mach-ux500: tee: l2cc TEE shared mutex support
arch/arm/include/asm/outercache.h | 9 ++++
arch/arm/mm/cache-l2x0.c | 87 +++++++++++++++++++++++++++++----------
arch/arm/mach-ux500/romcode-shared_mutex.c | 111 +++++++++++++++++++++++++++++
3 files changed, 185 insertions(+), 22 deletions(-)
--
1.7.11.3
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* [PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ
From: Etienne CARRIERE @ 2012-11-13 16:08 UTC (permalink / raw)
To: linux-arm-kernel
From: Etienne Carriere <etienne.carriere@stericsson.com>
Secure code in TrustZone space may need to perform L2 cache
maintenance operations. A shared mutex is required to synchronize
linux l2cc maintenance and TZ l2cc maintenance.
The TZ mutex is an "arch_spinlock": a 32bit DDR cell (ARMv7-A mutex).
Linux L2 cache driver must lock TZ mutex if enabled.
Signed-off-by: Etienne Carriere <etienne.carriere@stericsson.com>
---
arch/arm/include/asm/outercache.h | 9 ++++
arch/arm/mm/cache-l2x0.c | 87 +++++++++++++++++++++++++++++----------
2 files changed, 74 insertions(+), 22 deletions(-)
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index 53426c6..7aa5eac 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -35,6 +35,7 @@ struct outer_cache_fns {
#endif
void (*set_debug)(unsigned long);
void (*resume)(void);
+ bool (*tz_mutex)(unsigned long);
};
#ifdef CONFIG_OUTER_CACHE
@@ -81,6 +82,13 @@ static inline void outer_resume(void)
outer_cache.resume();
}
+static inline bool outer_tz_mutex(unsigned long addr)
+{
+ if (outer_cache.tz_mutex)
+ return outer_cache.tz_mutex(addr);
+ return false;
+}
+
#else
static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
@@ -92,6 +100,7 @@ static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
static inline void outer_flush_all(void) { }
static inline void outer_inv_all(void) { }
static inline void outer_disable(void) { }
+static inline bool outer_tz_mutex(unsigned long addr) { return false; }
#endif
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index a53fd2a..eacdc74 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -41,6 +41,26 @@ struct l2x0_of_data {
void (*resume)(void);
};
+/*
+ * arch_spinlock (single 32bit DDR mutex cell) pointer to synchronise
+ * L2CC maintenance between linux world and secure world (ARM TZ).
+ */
+arch_spinlock_t *l2x0_tz_mutex;
+
+#define l2x0_spin_lock_irqsave(flags) \
+ do { \
+ raw_spin_lock_irqsave(&l2x0_lock, flags); \
+ if (l2x0_tz_mutex) \
+ arch_spin_lock(l2x0_tz_mutex); \
+ } while (0)
+
+#define l2x0_spin_unlock_irqrestore(flags) \
+ do { \
+ if (l2x0_tz_mutex) \
+ arch_spin_unlock(l2x0_tz_mutex); \
+ raw_spin_unlock_irqrestore(&l2x0_lock, flags); \
+ } while (0)
+
static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
{
/* wait for cache operation by line or way to complete */
@@ -126,9 +146,9 @@ static void l2x0_cache_sync(void)
{
unsigned long flags;
- raw_spin_lock_irqsave(&l2x0_lock, flags);
+ l2x0_spin_lock_irqsave(flags);
cache_sync();
- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ l2x0_spin_unlock_irqrestore(flags);
}
static void __l2x0_flush_all(void)
@@ -145,9 +165,9 @@ static void l2x0_flush_all(void)
unsigned long flags;
/* clean all ways */
- raw_spin_lock_irqsave(&l2x0_lock, flags);
+ l2x0_spin_lock_irqsave(flags);
__l2x0_flush_all();
- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ l2x0_spin_unlock_irqrestore(flags);
}
static void l2x0_clean_all(void)
@@ -155,11 +175,11 @@ static void l2x0_clean_all(void)
unsigned long flags;
/* clean all ways */
- raw_spin_lock_irqsave(&l2x0_lock, flags);
+ l2x0_spin_lock_irqsave(flags);
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
cache_sync();
- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ l2x0_spin_unlock_irqrestore(flags);
}
static void l2x0_inv_all(void)
@@ -167,13 +187,13 @@ static void l2x0_inv_all(void)
unsigned long flags;
/* invalidate all ways */
- raw_spin_lock_irqsave(&l2x0_lock, flags);
+ l2x0_spin_lock_irqsave(flags);
/* Invalidating when L2 is enabled is a nono */
BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
cache_sync();
- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ l2x0_spin_unlock_irqrestore(flags);
}
static void l2x0_inv_range(unsigned long start, unsigned long end)
@@ -181,7 +201,7 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
void __iomem *base = l2x0_base;
unsigned long flags;
- raw_spin_lock_irqsave(&l2x0_lock, flags);
+ l2x0_spin_lock_irqsave(flags);
if (start & (CACHE_LINE_SIZE - 1)) {
start &= ~(CACHE_LINE_SIZE - 1);
debug_writel(0x03);
@@ -206,13 +226,13 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
}
if (blk_end < end) {
- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
- raw_spin_lock_irqsave(&l2x0_lock, flags);
+ l2x0_spin_unlock_irqrestore(flags);
+ l2x0_spin_lock_irqsave(flags);
}
}
cache_wait(base + L2X0_INV_LINE_PA, 1);
cache_sync();
- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ l2x0_spin_unlock_irqrestore(flags);
}
static void l2x0_clean_range(unsigned long start, unsigned long end)
@@ -225,7 +245,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
return;
}
- raw_spin_lock_irqsave(&l2x0_lock, flags);
+ l2x0_spin_lock_irqsave(flags);
start &= ~(CACHE_LINE_SIZE - 1);
while (start < end) {
unsigned long blk_end = start + min(end - start, 4096UL);
@@ -236,13 +256,13 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
}
if (blk_end < end) {
- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
- raw_spin_lock_irqsave(&l2x0_lock, flags);
+ l2x0_spin_unlock_irqrestore(flags);
+ l2x0_spin_lock_irqsave(flags);
}
}
cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
cache_sync();
- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ l2x0_spin_unlock_irqrestore(flags);
}
static void l2x0_flush_range(unsigned long start, unsigned long end)
@@ -255,7 +275,7 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
return;
}
- raw_spin_lock_irqsave(&l2x0_lock, flags);
+ l2x0_spin_lock_irqsave(flags);
start &= ~(CACHE_LINE_SIZE - 1);
while (start < end) {
unsigned long blk_end = start + min(end - start, 4096UL);
@@ -268,24 +288,24 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
debug_writel(0x00);
if (blk_end < end) {
- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
- raw_spin_lock_irqsave(&l2x0_lock, flags);
+ l2x0_spin_unlock_irqrestore(flags);
+ l2x0_spin_lock_irqsave(flags);
}
}
cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
cache_sync();
- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ l2x0_spin_unlock_irqrestore(flags);
}
static void l2x0_disable(void)
{
unsigned long flags;
- raw_spin_lock_irqsave(&l2x0_lock, flags);
+ l2x0_spin_lock_irqsave(flags);
__l2x0_flush_all();
writel_relaxed(0, l2x0_base + L2X0_CTRL);
dsb();
- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ l2x0_spin_unlock_irqrestore(flags);
}
static void l2x0_unlock(u32 cache_id)
@@ -307,6 +327,28 @@ static void l2x0_unlock(u32 cache_id)
}
}
+/* Enable/disable external mutex shared with TZ code */
+static bool l2x0_tz_mutex_cfg(unsigned long addr)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&l2x0_lock, flags);
+
+ if (addr && l2x0_tz_mutex && (addr != (uint)l2x0_tz_mutex)) {
+ raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ pr_err("%s: a TZ mutex is already enabled\n", __func__);
+ return false;
+ }
+
+ l2x0_tz_mutex = (arch_spinlock_t *)addr;
+ /* insure mutex ptr is updated before lock is released */
+ smp_wmb();
+
+ raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ pr_debug("\n%s: %sable TZ mutex\n\n", __func__, (addr) ? "en" : "dis");
+ return true;
+}
+
void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
{
u32 aux;
@@ -380,6 +422,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
outer_cache.inv_all = l2x0_inv_all;
outer_cache.disable = l2x0_disable;
outer_cache.set_debug = l2x0_set_debug;
+ outer_cache.tz_mutex = l2x0_tz_mutex_cfg;
printk(KERN_INFO "%s cache controller enabled\n", type);
printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
--
1.7.11.3
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* [PATCH 2/2] mach-ux500: L2CC shared mutex with ARM TZ
From: Etienne CARRIERE @ 2012-11-13 16:08 UTC (permalink / raw)
To: linux-arm-kernel
From: Etienne Carriere <etienne.carriere@stericsson.com>
L2 cache mutex is allocated in DDR from TZ/TEE.
Linux retrieves its physical address using from TEE API.
It maps it to the kernel address space.
Mutex needs to be cacheable, as configured in TZ MMU mapping
Once configured from TEE, enable its use by l2cc driver.
This patch assumes no L2 cache maintenance is request to TEE
inside the time frame from linux early boot to this "late_initcall
of "romcode-sm" probing. The SW architecture insures that.
This patch is an example of how ux500 plans to load the TZ shared
mutex into outer cache driver.
This patch cannot hit kernel main track. It targets internal kernel
Trees with enabled TEE driver (API to TZ world).
Signed-off-by: carriere etienne <etienne.carriere@stericsson.com>
---
arch/arm/mach-ux500/romcode-shared_mutex.c | 111 +++++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm/mach-ux500/romcode-shared_mutex.c b/arch/arm/mach-ux500/romcode-shared_mutex.c
new file mode 100644
index 0000000..a09df72
--- /dev/null
+++ b/arch/arm/mach-ux500/romcode-shared_mutex.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2012
+ * License terms: GNU General Public License (GPL), version 2
+ * Author: Etienne Carriere <etienne.carriere@stericsson.com> for ST-Ericsson.
+ *
+ * ROM code Mutex Configuration for A9 exclusive load and store operation
+ * for l2 cache maintenance.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/tee.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <asm/outercache.h>
+
+#define BASS_ROMCODE_SHARED_MUTEX 0
+
+#define UUID_TEE_TA_START_LOW 0xBC765EDE
+#define UUID_TEE_TA_START_MID 0x6724
+#define UUID_TEE_TA_START_HIGH 0x11DF
+#define UUID_TEE_TA_START_CLOCKSEQ \
+ {0x8E, 0x12, 0xEC, 0xDB, 0xDF, 0xD7, 0x20, 0x85}
+
+static int __devinit shared_mutex_config_probe(struct platform_device *pdev)
+{
+ struct tee_operation op;
+ struct tee_session sess;
+ struct tee_context ctx;
+ uint32_t mutex_type = BASS_ROMCODE_SHARED_MUTEX;
+ unsigned int paddr;
+ void __iomem *vaddr;
+ int err, ori;
+
+ /* Selects trustzone application needed for the job. */
+ struct tee_uuid static_uuid = {
+ UUID_TEE_TA_START_LOW,
+ UUID_TEE_TA_START_MID,
+ UUID_TEE_TA_START_HIGH,
+ UUID_TEE_TA_START_CLOCKSEQ,
+ };
+
+ err = teec_initialize_context(NULL, &ctx);
+ if (err) {
+ pr_err("%s: context init failed, 0x%X\n", __func__, err);
+ err = -EINVAL;
+ goto out;
+ }
+
+ err = teec_open_session(&ctx, &sess, &static_uuid,
+ TEEC_LOGIN_PUBLIC, NULL, NULL, &ori);
+ if (err) {
+ pr_err("%s: session failed, 0x%X/0x%X\n", __func__, err, ori);
+ err = -EINVAL;
+ goto out1;
+ }
+
+ memset(&op, 0, sizeof(op));
+ op.param[0].tmpref.buffer = (void *)&paddr;
+ op.param[0].tmpref.size = sizeof(uint32_t *);
+ op.param[1].tmpref.buffer = (void *)&mutex_type;
+ op.param[1].tmpref.size = sizeof(uint32_t);
+ op.types = TEEC_PARAM_TYPES(TEEC_MEMREF_TEMP_OUTPUT,
+ TEEC_MEMREF_TEMP_INPUT, TEEC_NONE, TEEC_NONE);
+
+ err = teec_invoke_command(&sess, TEE_STA_CONF_SHARED_MUTEX, &op, &ori);
+ if (err) {
+ pr_err("%s: init failed, 0x%X/0x%X", __func__, err, ori);
+ err = -EINVAL;
+ goto out2;
+ }
+
+ vaddr = ioremap_cached((unsigned long)paddr, SZ_1K);
+ if (vaddr == NULL) {
+ pr_err("%s: mutex map failed, 0x%X\n", __func__, paddr);
+ err = -EIO;
+ goto out2;
+ }
+
+ if (!outer_tz_mutex((unsigned long)vaddr)) {
+ pr_err("%s: load mutex 0x%08X failed\n", __func__, (uint)vaddr);
+ err = -EIO;
+ }
+out2:
+ (void)teec_close_session(&sess);
+out1:
+ (void)teec_finalize_context(&ctx);
+out:
+ return err;
+}
+
+static struct platform_driver romcode_sm_driver = {
+ .driver = {
+ .name = "romcode-sm",
+ .owner = THIS_MODULE,
+ },
+ .probe = shared_mutex_config_probe,
+};
+
+static int __init shared_mutex_config_init(void)
+{
+ return platform_driver_register(&romcode_sm_driver);
+}
+
+/* Wait for TEE driver to be initialized. */
+late_initcall(shared_mutex_config_init);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("TZ shared mutex config");
--
1.7.11.3
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^ permalink raw reply related
* [PATCH] ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER
From: Jon Hunter @ 2012-11-13 16:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A20F64.4010902@compulab.co.il>
On 11/13/2012 03:14 AM, Igor Grinberg wrote:
> On 11/12/12 21:15, Jon Hunter wrote:
>>
>> On 11/11/2012 05:28 AM, Igor Grinberg wrote:
>>>
>>>
>>> On 11/08/12 21:16, Jon Hunter wrote:
>>>>
>>>> On 11/08/2012 12:59 PM, Hiremath, Vaibhav wrote:
>>>>> On Fri, Nov 09, 2012 at 00:24:23, Hunter, Jon wrote:
>>>>>>
>>>>>> On 11/08/2012 01:59 AM, Igor Grinberg wrote:
>>>>>>
>>>>>> [snip]
>>>>>>
>>>>>>> There is no reliable way to determine which source should be used in runtime
>>>>>>> for boards that do not have the 32k oscillator wired.
>>>>>>
>>>>>> So thinking about this some more and given that we are moving away from
>>>>>> board files, if a board does not provide a 32kHz clock source, then this
>>>>>> should be reflected in the device-tree source file for that board.
>>>>>> Hence, at boot time we should be able to determine if a 32kHz clock
>>>>>> source can be used.
>>>>>>
>>>>>
>>>>> Let me feed some more thoughts here :)
>>>>>
>>>>> The way it is being detected currently is based on timer idle status bit.
>>>>> I am worried that, this is the only option we have.
>>>>
>>>> Why not use device-tree to indicate the presence of a 32k clock source?
>>>> This seems like a board level configuration and so device-tree seems to
>>>> be the perfect place for this IMO.
>>>
>>> Well, that is what my commit message says...
>>
>> Sorry, but that was not clear to me from whats in the commit message.
>
> From the commit message:
> "1) Timer structures and initialization functions are named by the platform
> name and the clock source in use. The decision which timer is
> used is done statically from the machine_desc structure. In the
> future it should come from DT."
>
> The last sentence has it.
Right, but it does not go into the details. It would be good to have
added a comment to the effect of "some boards do not have a 32k clock
source and in the future this should be handled by device-tree".
> The transition to DT is not immediate and we can't (still) neglect
> the non-DT setups.
Absolutely, but I am trying to understand if there are boards being
"neglected". I see now that your CM-T3517 would be. This was not clear
from your patch as even the CM-T3517 board was being configured to the
use the sync32k timer. So from looking at your patch I did not see any
neglected boards, however, I understand your motivation to add all these
init functions so that boards could be customised easily.
>> Should we be doing this now instead of adding all these static timer
>> init functions?
>
> I don't see this as "adding ...", I see this as expanding the setup
> which was previously hidden by the CONFIG_OMAP_32K_TIMER option.
>
>>
>> Are there any boards today (supported in the kernel that is), that don't
>> support a 32k?
>
> Yes, starting from revision 1.2, CM-T3517 does not have the 32k.
Thanks, this is the exact information I was looking for. You should put
this in your commit message to highlight the fact that there are boards
that don't have a 32k clock source.
I am familiar with the OMAP devices, but less familiar with these AMxxxx
derivatives (as I don't work with these) and so it is good to put these
specifics in the commit message.
Cheers
Jon
^ permalink raw reply
* [GIT PULL] ARM: OMAP2+: clock: convert to common clock framework
From: Paul Walmsley @ 2012-11-13 16:49 UTC (permalink / raw)
To: linux-arm-kernel
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hi Tony
The following changes since commit c9d501e5cb0238910337213e12a09127221c35d8:
Merge tag 'omap-cleanup-b2-for-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.8/cleanup-prcm (2012-11-09 14:13:43 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git tags/omap-cleanup-c-for-3.8
for you to fetch changes up to f9ae32a74f0242cbef76d9baa10993d707be1714:
ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts (2012-11-12 19:18:51 -0700)
- ----------------------------------------------------------------
Convert the OMAP2+ clock code and data to rely on the common
clock framework for internal bookkeeping and the driver API.
Basic test logs for this branch on top of Tony's cleanup-prcm branch
at commit c9d501e5cb0238910337213e12a09127221c35d8 are here:
http://www.pwsan.com/omap/testlogs/common_clk_devel_3.8_rebase/20121112192516/
However, cleanup-prcm at c9d501e5 does not include some fixes
that are needed for a successful test. With several reverts,
fixes, and workarounds applied, the following test logs were
obtained:
http://www.pwsan.com/omap/testlogs/TEST_common_clk_devel_3.8_rebase/20121112192300/
which indicate that the series tests cleanly.
N.B. The common clock data addition patches result in many
checkpatch warnings of the form "WARNING: static const char *
array should probably be static const char * const". However, it
appears that resolving these would require changes to the CCF
itself. So the resolution of these warnings is being postponed
until that can be coordinated.
These patches result in a ~55KiB increase in runtime kernel memory
usage when booting omap2plus_defconfig kernels.
- ----------------------------------------------------------------
vmlinux object size
(delta in bytes from TEST_cleanup-prcm_c9d501e5_v3.7-rc (c9d501e5cb0238910337213e12a09127221c35d8)):
text data bss total kernel
+17493 +1264 0 +18757 am33xx_only
+16437 +7224 +72 +23733 n800_multi_omap2xxx
+12137 +3464 +72 +15673 n800_only_a
0 0 0 0 omap1_defconfig
0 0 0 0 omap1_defconfig_1510innovator_only
0 0 0 0 omap1_defconfig_5912osk_only
+39185 +17328 0 +56513 omap2plus_defconfig
+13397 +3728 +64 +17189 omap2plus_defconfig_2430sdp_only
+38945 +17200 +64 +56209 omap2plus_defconfig_cpupm
+35733 +20392 +64 +56189 omap2plus_defconfig_no_pm
+34693 +9616 +64 +44373 omap2plus_defconfig_omap2_4_only
+30777 +8616 +64 +39457 omap2plus_defconfig_omap3_4_only
+12780 +20340 -1400 +31720 rmk_omap3430_ldp_allnoconfig
+21613 +8688 +64 +30365 rmk_omap3430_ldp_oldconfig
+12780 +20340 -1400 +31720 rmk_omap4430_sdp_allnoconfig
+8937 +3656 +64 +12657 rmk_omap4430_sdp_oldconfig
Boot-time memory difference
(delta in bytes from TEST_cleanup-prcm_c9d501e5_v3.7-rc (c9d501e5cb0238910337213e12a09127221c35d8))
avail rsrvd high freed board kconfig
-20k 20k . . 2420n800 omap2plus_defconfig
-56k 56k . . 2430sdp omap2plus_defconfig
-56k 56k . . 3517evm omap2plus_defconfig
-56k 56k . . 3530es3beagle omap2plus_defconfig
-56k 56k . . 3730beaglexm omap2plus_defconfig
-56k 56k . . 37xxevm omap2plus_defconfig
-56k 56k . . 4430es2panda omap2plus_defconfig
-16k 16k . . am335xbone omap2plus_defconfig
-56k 56k . . cmt3517 omap2plus_defconfig
Mike Turquette (3):
ARM: OMAP4: clock: Convert to common clk
ARM: OMAP2+: clockdomain: bypass clockdomain handling when disabling unused clks
ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts
Paul Walmsley (7):
ARM: OMAP2xxx: clock: add APLL rate recalculation functions
ARM: OMAP2+: clock: add OMAP CCF convenience macros to mach-omap2/clock.h
ARM: OMAP44xx: clock: drop obsolete clock data
ARM: OMAP3xxx: clk: drop obsolete clock data
ARM: AM33xx: clock: drop obsolete clock data
ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections
ARM: OMAP2xxx: clock: drop obsolete clock data
Rajendra Nayak (15):
ARM: OMAP: clock: Nuke plat/clock.c & reuse struct clk as clk_hw_omap
ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses
ARM: OMAP3: clock: Convert to common clk
ARM: OMAP2: clock: Convert to common clk
ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable autoidle
ARM: OMAP: clock: Define a function to enable clocks at init
ARM: OMAP: clock: Get rid of some clkdm assocations within clks
ARM: OMAP4: clock: Add 44xx data using common struct clk
ARM: OMAP3: clock: Add 3xxx data using common struct clk
ARM: OMAP2: clock: Add 24xx data using common struct clk
ARM: OMAP: clock: Switch to COMMON clk
ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP4: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP3: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP2: clock: Cleanup !CONFIG_COMMON_CLK parts
Vaibhav Hiremath (2):
ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions
ARM: AM33XX: clock: add clock data in common clock format
arch/arm/mach-omap2/Kconfig | 5 +
arch/arm/mach-omap2/Makefile | 10 +-
arch/arm/mach-omap2/cclock2420_data.c | 1950 ++++++++++++++
arch/arm/mach-omap2/cclock2430_data.c | 2065 +++++++++++++++
arch/arm/mach-omap2/cclock33xx_data.c | 961 +++++++
arch/arm/mach-omap2/cclock3xxx_data.c | 3595 +++++++++++++++++++++++++
arch/arm/mach-omap2/cclock44xx_data.c | 1987 ++++++++++++++
arch/arm/mach-omap2/clkt2xxx_apll.c | 62 +-
arch/arm/mach-omap2/clkt2xxx_dpll.c | 8 +-
arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 13 +-
arch/arm/mach-omap2/clkt2xxx_osc.c | 13 +-
arch/arm/mach-omap2/clkt2xxx_sys.c | 7 +-
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 9 +-
arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 8 +-
arch/arm/mach-omap2/clkt_clksel.c | 194 +-
arch/arm/mach-omap2/clkt_dpll.c | 28 +-
arch/arm/mach-omap2/clkt_iclk.c | 30 +-
arch/arm/mach-omap2/clock.c | 910 ++-----
arch/arm/mach-omap2/clock.h | 329 +--
arch/arm/mach-omap2/clock2420_data.c | 1972 --------------
arch/arm/mach-omap2/clock2430.c | 8 +-
arch/arm/mach-omap2/clock2430_data.c | 2071 ---------------
arch/arm/mach-omap2/clock2xxx.c | 1 +
arch/arm/mach-omap2/clock2xxx.h | 41 +-
arch/arm/mach-omap2/clock33xx_data.c | 1107 --------
arch/arm/mach-omap2/clock34xx.c | 51 +-
arch/arm/mach-omap2/clock3517.c | 24 +-
arch/arm/mach-omap2/clock36xx.c | 22 +-
arch/arm/mach-omap2/clock36xx.h | 2 +-
arch/arm/mach-omap2/clock3xxx.c | 6 +-
arch/arm/mach-omap2/clock3xxx.h | 6 +-
arch/arm/mach-omap2/clock3xxx_data.c | 3613 --------------------------
arch/arm/mach-omap2/clock44xx_data.c | 3398 ------------------------
arch/arm/mach-omap2/clock_common_data.c | 22 +-
arch/arm/mach-omap2/clockdomain.c | 89 +-
arch/arm/mach-omap2/cm-regbits-24xx.h | 5 +
arch/arm/mach-omap2/cm-regbits-34xx.h | 31 +
arch/arm/mach-omap2/cm2xxx_3xxx.h | 1 +
arch/arm/mach-omap2/dpll3xxx.c | 183 +-
arch/arm/mach-omap2/dpll44xx.c | 21 +-
arch/arm/mach-omap2/io.c | 9 +
arch/arm/mach-omap2/omap_hwmod.c | 63 +-
arch/arm/mach-omap2/pm24xx.c | 4 +-
arch/arm/mach-omap2/prm-regbits-24xx.h | 2 +
arch/arm/mach-omap2/prm-regbits-34xx.h | 1 +
arch/arm/mach-omap2/prm2xxx_3xxx.h | 1 +
arch/arm/mach-omap2/scrm44xx.h | 2 +
47 files changed, 11482 insertions(+), 13458 deletions(-)
create mode 100644 arch/arm/mach-omap2/cclock2420_data.c
create mode 100644 arch/arm/mach-omap2/cclock2430_data.c
create mode 100644 arch/arm/mach-omap2/cclock33xx_data.c
create mode 100644 arch/arm/mach-omap2/cclock3xxx_data.c
create mode 100644 arch/arm/mach-omap2/cclock44xx_data.c
delete mode 100644 arch/arm/mach-omap2/clock2420_data.c
delete mode 100644 arch/arm/mach-omap2/clock2430_data.c
delete mode 100644 arch/arm/mach-omap2/clock33xx_data.c
delete mode 100644 arch/arm/mach-omap2/clock3xxx_data.c
delete mode 100644 arch/arm/mach-omap2/clock44xx_data.c
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^ permalink raw reply
* [PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ
From: Russell King - ARM Linux @ 2012-11-13 17:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0154077FE026E54BB093CA7EB3FD1AE32B57AF1B59@SAFEX1MAIL3.st.com>
On Tue, Nov 13, 2012 at 05:08:14PM +0100, Etienne CARRIERE wrote:
> From: Etienne Carriere <etienne.carriere@stericsson.com>
>
> Secure code in TrustZone space may need to perform L2 cache
> maintenance operations. A shared mutex is required to synchronize
> linux l2cc maintenance and TZ l2cc maintenance.
>
> The TZ mutex is an "arch_spinlock": a 32bit DDR cell (ARMv7-A mutex).
> Linux L2 cache driver must lock TZ mutex if enabled.
>...
> +#define l2x0_spin_lock_irqsave(flags) \
> + do { \
> + raw_spin_lock_irqsave(&l2x0_lock, flags); \
> + if (l2x0_tz_mutex) \
> + arch_spin_lock(l2x0_tz_mutex); \
> + } while (0)
Right, so, what this tells me is that the implementation of the spinlock
in the secure software is potentially the same as the kernel's spinlock.
The kernel's spinlock implementation is GPL'd. If the secure side spinlock
implementation is a copy of the kernel's spinlock implementation, then that
implementation is also GPL'd, which, as it is linked with the rest of the
secure software, either the whole of the secure software suite is GPL'd
_or_ it is in violation of the GPL.
I think someone has some explaining to do.
^ permalink raw reply
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