* [PATCH V2 3/3] clocksource: time-armada-370-xp converted to clk framework
From: John Stultz @ 2012-11-13 18:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121030115223.18780.29992@nucleus>
On 10/30/2012 04:52 AM, Mike Turquette wrote:
> Quoting Gregory CLEMENT (2012-10-01 14:12:06)
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> I'm not sure this patch should go through me. Perhaps John Stultz?
I can apply it to my tree, but really none of it is generic, so in the
future I'd almost rather someone who could reasonably audit the changes
for correctness merge it instead (although I always appreciate being
Cc'ed into the loop).
thanks
-john
^ permalink raw reply
* OMAP baseline test results for v3.7-rc4
From: Kevin Hilman @ 2012-11-13 18:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1211092347520.20703@utopia.booyaka.com>
Paul Walmsley <paul@pwsan.com> writes:
> On Fri, 9 Nov 2012, Kevin Hilman wrote:
>
>> I found that disabling MMC in the config made the tests pass again, so
>> then bisected it down to the commit below removing SYSCONFIG
>> accesses[2]. I haven't had the time to find out exactly the cause, but
>> clearly the code that was removed was doing something that hwmod is not
>> taking care of automatically.
>>
>> Venkat, Felipe, could you please investigate this and hopefully get a
>> fix out for v3.7-rc?
>
> This one might fix it -- it fixes another PM bug in the v3.7-rcs involving
> the same commit:
>
> http://git.kernel.org/?p=linux/kernel/git/pjw/omap-pending.git;a=commit;h=613ad0e98c3596cd2524172fae2a795c3fc57e4a
>
Indeed, that fixes it. Somehow I thought I was already including that
fix, but I wasn't.
Thanks,
Kevin
^ permalink raw reply
* arm: mvebu: Pull request for 'marvell-boards' branch
From: Jason Cooper @ 2012-11-13 18:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352740839-13586-1-git-send-email-thomas.petazzoni@free-electrons.com>
Thomas,
Nice to see a pull request from you guys!
Comments below:
On Mon, Nov 12, 2012 at 06:20:33PM +0100, Thomas Petazzoni wrote:
> Jason, Andrew,
>
> The following changes since commit 77b67063bb6bce6d475e910d3b886a606d0d91f7:
>
> Linux 3.7-rc5 (2012-11-11 13:44:33 +0100)
>
> are available in the git repository at:
>
> git at github.com:MISL-EBU-System-SW/mainline-public.git marvell-boards
>
> for you to fetch changes up to 39325a96e1d082bf71b7a4d9ac2d5806f80c6d13:
>
> arm: mvebu: add LED support in defconfig (2012-11-12 18:13:41 +0100)
>
> ----------------------------------------------------------------
I'd like to see a signed tag in here. If you could have gregory send me
a signed email with all the fingerprints you guys traded at ELCE, I'd
appreciate it.
In the future, could you please break these up into the following
branches:
> Gregory CLEMENT (1):
> arm: mvebu: support for the Globalscale Mirabox board
boards
> Thomas Petazzoni (5):
> arm: mvebu: fix compatible string in armada-370-xp.dtsi
> arm: mvebu: don't list all boards in dt compat field for Armada 370/XP
> arm: mvebu: fix typo in machine name for Armada 370/XP
cleanup (also, if any are fixing problems found in older kernels, please
add a CC to stable as appropriate)
> arm: mvebu: support for the PlatHome OpenBlocks AX3-4 board
boards
> arm: mvebu: add LED support in defconfig
defconfig
That would really help me out. Otherwise, I have to pull this branch
and cherry-pick the patches into different branches. Which kind of
defeats the purpose of the pull request. ;-)
thx,
Jason.
^ permalink raw reply
* [PATCH] arm: zynq: add system level control register manager
From: John Linn @ 2012-11-13 18:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121113183338.GJ1718@beefymiracle.amer.corp.natinst.com>
> -----Original Message-----
> From: Josh Cartwright [mailto:josh.cartwright at ni.com]
> Sent: Tuesday, November 13, 2012 10:34 AM
> To: Michal Simek
> Cc: Josh Cartwright; Daniel Borkmann; Arnd Bergmann; linux-arm-kernel at lists.infradead.org; John Linn
> Subject: Re: [PATCH] arm: zynq: add system level control register manager
>
> On Mon, Nov 12, 2012 at 11:35:46AM +0000, Michal Simek wrote:
> > > 3. Figure out MIO pinctrl support and bindings (?)
> >
> > We will look at this topic more closely.
>
> For some clarification: are you (or someone at Xilinx) actively looking
> at this?
Hi Josh,
No one is looking at it that I know of (other than maybe Michal). Our previous thinking was that this was low priority as the first stage boot loader sets up the MIO prior to the kernel running. U-boot needs the MIO setup for some set of devices also.
I don't know the use cases for dynamic MIO, or I'm just misunderstanding what the pinctrl really does. Do designers often build a board to deal with being able use the pins for multiple purposes?
Thanks
John
>
> Thanks,
> Josh
^ permalink raw reply
* [PATCH] arm: zynq: add system level control register manager
From: Josh Cartwright @ 2012-11-13 18:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAD6jFUQC+HPCT11_nWckUkhzgQtPkxLcqcTxbVb==kFmwCaTwA@mail.gmail.com>
On Fri, Nov 09, 2012 at 10:49:07AM +0100, Daniel Borkmann wrote:
> On Thu, Nov 8, 2012 at 5:01 PM, Josh Cartwright <joshc@eso.teric.us> wrote:
> > On Wed, Oct 31, 2012 at 07:36:12PM +0100, Daniel Borkmann wrote:
> >> This patch for the Xilinx Zynq ARM architecture adds management of system
> >> level control register. The code is taken from the Xilinx-internal Linux
> >> Git tree and cleaned up a bit for mainline integration. Besides others,
> >> this patch is needed in order to integrate further drivers for Zynq such as
> >> the Zynq xemacps networking device driver. The patch is aganst the latest
> >> arm-soc tree.
> >>
> >> Signed-off-by: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
> >> Cc: Michal Simek <michals@xilinx.com>
> >> Cc: John Linn <john.linn@xilinx.com>
> >> Cc: Arnd Bergmann <arnd@arndb.de>
> >> ---
> >
> > These changes will conflict with my pending clk patchset [1], as I'm
> > introducing bindings for the SLCR (and its clk interfaces).
>
> Oops, okay. Then your's has priority, of course.
I did not mean to discourage. I just meant to say that we should work
out how this work can be done on top of the clk changes.
> > It seems like a hefty chunk of the out-of-tree slcr driver is related to
> > configuring MIO. I think it would be really nice if this driver was
> > reworked to use the pinctrl subsystem, and also to provide suitable
> > device tree bindings.
>
> Agreed. If there's a chance to help with further Zynq integration and
> to develop this driver with testing on Qemu for ARM Zynq, I'd like to
> give it a try. (The board is a bit expensive as a hobby only.)
My concern is that, especially regarding the configuration of MIO, being
able to do adequate testing will require real hardware. It isn't clear
to me what the state of qemu's slcr/mio model is.
Josh
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^ permalink raw reply
* [PATCH] arm: zynq: add system level control register manager
From: Josh Cartwright @ 2012-11-13 18:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5b1971ea-9ad9-4f58-841e-a3efb7cf905d@CO1EHSMHS022.ehs.local>
On Mon, Nov 12, 2012 at 11:35:46AM +0000, Michal Simek wrote:
> > 3. Figure out MIO pinctrl support and bindings (?)
>
> We will look at this topic more closely.
For some clarification: are you (or someone at Xilinx) actively looking
at this?
Thanks,
Josh
^ permalink raw reply
* [PATCH 8/8] ARM: OMAP: Move plat/dmtimer.h to plat-omap/dmtimer.h
From: Jon Hunter @ 2012-11-13 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352830403-1706-1-git-send-email-jon-hunter@ti.com>
Move plat/dmtimer.h to plat-omap/dmtimer.h in order to support a single
zImage for ARM devices.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/mach-omap1/pm.c | 2 +-
arch/arm/mach-omap1/timer.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 +-
arch/arm/mach-omap2/timer.c | 2 +-
arch/arm/plat-omap/dmtimer.c | 2 +-
arch/arm/plat-omap/include/plat-omap/dmtimer.h | 420 ++++++++++++++++++++
arch/arm/plat-omap/include/plat/dmtimer.h | 414 -------------------
drivers/staging/tidspbridge/core/dsp-clock.c | 2 +-
10 files changed, 428 insertions(+), 422 deletions(-)
create mode 100644 arch/arm/plat-omap/include/plat-omap/dmtimer.h
delete mode 100644 arch/arm/plat-omap/include/plat/dmtimer.h
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 66d663a..ecc1f76 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -53,7 +53,7 @@
#include <mach/tc.h>
#include <mach/mux.h>
#include <plat-omap/dma-omap.h>
-#include <plat/dmtimer.h>
+#include <plat-omap/dmtimer.h>
#include <mach/irqs.h>
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index bde7a35..0089fb7 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -29,7 +29,7 @@
#include <mach/irqs.h>
-#include <plat/dmtimer.h>
+#include <plat-omap/dmtimer.h>
#define OMAP1610_GPTIMER1_BASE 0xfffb1400
#define OMAP1610_GPTIMER2_BASE 0xfffb1c00
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 0db8f45..a4169b6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -11,7 +11,7 @@
#include <linux/platform_data/gpio-omap.h>
#include <plat-omap/dma-omap.h>
-#include <plat/dmtimer.h>
+#include <plat-omap/dmtimer.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include "omap_hwmod.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index addc1c2..ff835ed 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -24,7 +24,7 @@
#include "l4_3xxx.h"
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/dmtimer.h>
+#include <plat-omap/dmtimer.h>
#include <plat/iommu.h>
#include "am35xx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 399f4ce..2750efe 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -27,7 +27,7 @@
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dmtimer.h>
+#include <plat-omap/dmtimer.h>
#include <plat/iommu.h>
#include "omap_hwmod.h"
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 4daa8b4..b8ee64a 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -50,7 +50,7 @@
#include "omap_hwmod.h"
#include "omap_device.h"
#include <plat/counter-32k.h>
-#include <plat/dmtimer.h>
+#include <plat-omap/dmtimer.h>
#include "omap-pm.h"
#include "soc.h"
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 89585c2..a1d45c7 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -46,7 +46,7 @@
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
-#include <plat/dmtimer.h>
+#include <plat-omap/dmtimer.h>
static u32 omap_reserved_systimers;
static LIST_HEAD(omap_timer_list);
diff --git a/arch/arm/plat-omap/include/plat-omap/dmtimer.h b/arch/arm/plat-omap/include/plat-omap/dmtimer.h
new file mode 100644
index 0000000..abe073f
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat-omap/dmtimer.h
@@ -0,0 +1,420 @@
+/*
+ * arch/arm/plat-omap/include/plat-omap/dmtimer.h
+ *
+ * OMAP Dual-Mode Timers
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Platform device conversion and hwmod support.
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
+ * PWM and clock framwork support by Timo Teras.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#ifndef __ASM_ARCH_DMTIMER_H
+#define __ASM_ARCH_DMTIMER_H
+
+/* clock sources */
+#define OMAP_TIMER_SRC_SYS_CLK 0x00
+#define OMAP_TIMER_SRC_32_KHZ 0x01
+#define OMAP_TIMER_SRC_EXT_CLK 0x02
+
+/* timer interrupt enable bits */
+#define OMAP_TIMER_INT_CAPTURE (1 << 2)
+#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
+#define OMAP_TIMER_INT_MATCH (1 << 0)
+
+/* trigger types */
+#define OMAP_TIMER_TRIGGER_NONE 0x00
+#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
+#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
+
+/* posted mode types */
+#define OMAP_TIMER_NONPOSTED 0x00
+#define OMAP_TIMER_POSTED 0x01
+
+/* timer capabilities used in hwmod database */
+#define OMAP_TIMER_SECURE 0x80000000
+#define OMAP_TIMER_ALWON 0x40000000
+#define OMAP_TIMER_HAS_PWM 0x20000000
+#define OMAP_TIMER_NEEDS_RESET 0x10000000
+#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
+
+/*
+ * timer errata flags
+ *
+ * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
+ * errata prevents us from using posted mode on these devices, unless the
+ * timer counter register is never read. For more details please refer to
+ * the OMAP3/4/5 errata documents.
+ */
+#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
+
+struct omap_timer_capability_dev_attr {
+ u32 timer_capability;
+};
+
+struct timer_regs {
+ u32 tidr;
+ u32 tier;
+ u32 twer;
+ u32 tclr;
+ u32 tcrr;
+ u32 tldr;
+ u32 ttrg;
+ u32 twps;
+ u32 tmar;
+ u32 tcar1;
+ u32 tsicr;
+ u32 tcar2;
+ u32 tpir;
+ u32 tnir;
+ u32 tcvr;
+ u32 tocr;
+ u32 towr;
+};
+
+struct omap_dm_timer {
+ int id;
+ int irq;
+ struct clk *fclk;
+
+ void __iomem *io_base;
+ void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
+ void __iomem *irq_ena; /* irq enable */
+ void __iomem *irq_dis; /* irq disable, only on v2 ip */
+ void __iomem *pend; /* write pending */
+ void __iomem *func_base; /* function register base */
+
+ unsigned long rate;
+ unsigned reserved:1;
+ unsigned posted:1;
+ struct timer_regs context;
+ int (*get_context_loss_count)(struct device *);
+ int ctx_loss_count;
+ int revision;
+ u32 capability;
+ u32 errata;
+ struct platform_device *pdev;
+ struct list_head node;
+};
+
+int omap_dm_timer_reserve_systimer(int id);
+struct omap_dm_timer *omap_dm_timer_request(void);
+struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
+struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
+int omap_dm_timer_free(struct omap_dm_timer *timer);
+void omap_dm_timer_enable(struct omap_dm_timer *timer);
+void omap_dm_timer_disable(struct omap_dm_timer *timer);
+
+int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
+
+u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
+struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
+
+int omap_dm_timer_trigger(struct omap_dm_timer *timer);
+int omap_dm_timer_start(struct omap_dm_timer *timer);
+int omap_dm_timer_stop(struct omap_dm_timer *timer);
+
+int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
+int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
+ unsigned int value);
+int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
+ unsigned int value);
+int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
+ unsigned int match);
+int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle,
+ int trigger);
+int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
+
+int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
+ unsigned int value);
+int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask);
+
+unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
+int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
+unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
+int omap_dm_timer_write_counter(struct omap_dm_timer *timer,
+ unsigned int value);
+
+int omap_dm_timers_active(void);
+
+/*
+ * Do not use the defines below, they are not needed. They should be only
+ * used by dmtimer.c and sys_timer related code.
+ */
+
+/*
+ * The interrupt registers are different between v1 and v2 ip.
+ * These registers are offsets from timer->iobase.
+ */
+#define OMAP_TIMER_ID_OFFSET 0x00
+#define OMAP_TIMER_OCP_CFG_OFFSET 0x10
+
+#define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14
+#define OMAP_TIMER_V1_STAT_OFFSET 0x18
+#define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c
+
+#define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24
+#define OMAP_TIMER_V2_IRQSTATUS 0x28
+#define OMAP_TIMER_V2_IRQENABLE_SET 0x2c
+#define OMAP_TIMER_V2_IRQENABLE_CLR 0x30
+
+/*
+ * The functional registers have a different base on v1 and v2 ip.
+ * These registers are offsets from timer->func_base. The func_base
+ * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
+ *
+ */
+#define OMAP_TIMER_V2_FUNC_OFFSET 0x14
+
+#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
+#define _OMAP_TIMER_CTRL_OFFSET 0x24
+#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
+#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
+#define OMAP_TIMER_CTRL_PT (1 << 12)
+#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
+#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
+#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
+#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
+#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
+#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
+#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
+#define OMAP_TIMER_CTRL_POSTED (1 << 2)
+#define OMAP_TIMER_CTRL_AR (1 << 1) /* autoreload enable */
+#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
+#define _OMAP_TIMER_COUNTER_OFFSET 0x28
+#define _OMAP_TIMER_LOAD_OFFSET 0x2c
+#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
+#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
+#define WP_NONE 0 /* no write pending bit */
+#define WP_TCLR (1 << 0)
+#define WP_TCRR (1 << 1)
+#define WP_TLDR (1 << 2)
+#define WP_TTGR (1 << 3)
+#define WP_TMAR (1 << 4)
+#define WP_TPIR (1 << 5)
+#define WP_TNIR (1 << 6)
+#define WP_TCVR (1 << 7)
+#define WP_TOCR (1 << 8)
+#define WP_TOWR (1 << 9)
+#define _OMAP_TIMER_MATCH_OFFSET 0x38
+#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
+#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
+#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
+#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
+#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
+#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
+#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
+#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
+
+/* register offsets with the write pending bit encoded */
+#define WPSHIFT 16
+
+#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
+ | (WP_TCLR << WPSHIFT))
+
+#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
+ | (WP_TCRR << WPSHIFT))
+
+#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
+ | (WP_TLDR << WPSHIFT))
+
+#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
+ | (WP_TTGR << WPSHIFT))
+
+#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
+ | (WP_TMAR << WPSHIFT))
+
+#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
+ | (WP_TPIR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
+ | (WP_TNIR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
+ | (WP_TCVR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
+ (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
+ (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
+
+static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
+ int posted)
+{
+ if (posted)
+ while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
+ cpu_relax();
+
+ return __raw_readl(timer->func_base + (reg & 0xff));
+}
+
+static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
+ u32 reg, u32 val, int posted)
+{
+ if (posted)
+ while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
+ cpu_relax();
+
+ __raw_writel(val, timer->func_base + (reg & 0xff));
+}
+
+static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
+{
+ u32 tidr;
+
+ /* Assume v1 ip if bits [31:16] are zero */
+ tidr = __raw_readl(timer->io_base);
+ if (!(tidr >> 16)) {
+ timer->revision = 1;
+ timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
+ timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
+ timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
+ timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
+ timer->func_base = timer->io_base;
+ } else {
+ timer->revision = 2;
+ timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
+ timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
+ timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
+ timer->pend = timer->io_base +
+ _OMAP_TIMER_WRITE_PEND_OFFSET +
+ OMAP_TIMER_V2_FUNC_OFFSET;
+ timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
+ }
+}
+
+/*
+ * __omap_dm_timer_enable_posted - enables write posted mode
+ * @timer: pointer to timer instance handle
+ *
+ * Enables the write posted mode for the timer. When posted mode is enabled
+ * writes to certain timer registers are immediately acknowledged by the
+ * internal bus and hence prevents stalling the CPU waiting for the write to
+ * complete. Enabling this feature can improve performance for writing to the
+ * timer registers.
+ */
+static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
+{
+ if (timer->posted)
+ return;
+
+ if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
+ return;
+
+ __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
+ OMAP_TIMER_CTRL_POSTED, 0);
+ timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
+ timer->posted = OMAP_TIMER_POSTED;
+}
+
+/**
+ * __omap_dm_timer_override_errata - override errata flags for a timer
+ * @timer: pointer to timer handle
+ * @errata: errata flags to be ignored
+ *
+ * For a given timer, override a timer errata by clearing the flags
+ * specified by the errata argument. A specific erratum should only be
+ * overridden for a timer if the timer is used in such a way the erratum
+ * has no impact.
+ */
+static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
+ u32 errata)
+{
+ timer->errata &= ~errata;
+}
+
+static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
+ int posted, unsigned long rate)
+{
+ u32 l;
+
+ l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
+ if (l & OMAP_TIMER_CTRL_ST) {
+ l &= ~0x1;
+ __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
+#ifdef CONFIG_ARCH_OMAP2PLUS
+ /* Readback to make sure write has completed */
+ __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
+ /*
+ * Wait for functional clock period x 3.5 to make sure that
+ * timer is stopped
+ */
+ udelay(3500000 / rate + 1);
+#endif
+ }
+
+ /* Ack possibly pending interrupt */
+ __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
+}
+
+static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
+ u32 ctrl, unsigned int load,
+ int posted)
+{
+ __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
+ __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
+}
+
+static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
+ unsigned int value)
+{
+ __raw_writel(value, timer->irq_ena);
+ __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
+}
+
+static inline unsigned int
+__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
+{
+ return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
+}
+
+static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
+ unsigned int value)
+{
+ __raw_writel(value, timer->irq_stat);
+}
+
+#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
deleted file mode 100644
index a3fbc48..0000000
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ /dev/null
@@ -1,414 +0,0 @@
-/*
- * arch/arm/plat-omap/include/plat/dmtimer.h
- *
- * OMAP Dual-Mode Timers
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- * Tarun Kanti DebBarma <tarun.kanti@ti.com>
- * Thara Gopinath <thara@ti.com>
- *
- * Platform device conversion and hwmod support.
- *
- * Copyright (C) 2005 Nokia Corporation
- * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
- * PWM and clock framwork support by Timo Teras.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-
-#ifndef __ASM_ARCH_DMTIMER_H
-#define __ASM_ARCH_DMTIMER_H
-
-/* clock sources */
-#define OMAP_TIMER_SRC_SYS_CLK 0x00
-#define OMAP_TIMER_SRC_32_KHZ 0x01
-#define OMAP_TIMER_SRC_EXT_CLK 0x02
-
-/* timer interrupt enable bits */
-#define OMAP_TIMER_INT_CAPTURE (1 << 2)
-#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
-#define OMAP_TIMER_INT_MATCH (1 << 0)
-
-/* trigger types */
-#define OMAP_TIMER_TRIGGER_NONE 0x00
-#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
-#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
-
-/* posted mode types */
-#define OMAP_TIMER_NONPOSTED 0x00
-#define OMAP_TIMER_POSTED 0x01
-
-/* timer capabilities used in hwmod database */
-#define OMAP_TIMER_SECURE 0x80000000
-#define OMAP_TIMER_ALWON 0x40000000
-#define OMAP_TIMER_HAS_PWM 0x20000000
-#define OMAP_TIMER_NEEDS_RESET 0x10000000
-#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
-
-/*
- * timer errata flags
- *
- * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
- * errata prevents us from using posted mode on these devices, unless the
- * timer counter register is never read. For more details please refer to
- * the OMAP3/4/5 errata documents.
- */
-#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
-
-struct omap_timer_capability_dev_attr {
- u32 timer_capability;
-};
-
-struct timer_regs {
- u32 tidr;
- u32 tier;
- u32 twer;
- u32 tclr;
- u32 tcrr;
- u32 tldr;
- u32 ttrg;
- u32 twps;
- u32 tmar;
- u32 tcar1;
- u32 tsicr;
- u32 tcar2;
- u32 tpir;
- u32 tnir;
- u32 tcvr;
- u32 tocr;
- u32 towr;
-};
-
-struct omap_dm_timer {
- int id;
- int irq;
- struct clk *fclk;
-
- void __iomem *io_base;
- void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
- void __iomem *irq_ena; /* irq enable */
- void __iomem *irq_dis; /* irq disable, only on v2 ip */
- void __iomem *pend; /* write pending */
- void __iomem *func_base; /* function register base */
-
- unsigned long rate;
- unsigned reserved:1;
- unsigned posted:1;
- struct timer_regs context;
- int (*get_context_loss_count)(struct device *);
- int ctx_loss_count;
- int revision;
- u32 capability;
- u32 errata;
- struct platform_device *pdev;
- struct list_head node;
-};
-
-int omap_dm_timer_reserve_systimer(int id);
-struct omap_dm_timer *omap_dm_timer_request(void);
-struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
-struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
-int omap_dm_timer_free(struct omap_dm_timer *timer);
-void omap_dm_timer_enable(struct omap_dm_timer *timer);
-void omap_dm_timer_disable(struct omap_dm_timer *timer);
-
-int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
-
-u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
-struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
-
-int omap_dm_timer_trigger(struct omap_dm_timer *timer);
-int omap_dm_timer_start(struct omap_dm_timer *timer);
-int omap_dm_timer_stop(struct omap_dm_timer *timer);
-
-int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
-int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
-int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
-int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
-
-int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
-int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask);
-
-unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
-int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
-unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
-int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
-
-int omap_dm_timers_active(void);
-
-/*
- * Do not use the defines below, they are not needed. They should be only
- * used by dmtimer.c and sys_timer related code.
- */
-
-/*
- * The interrupt registers are different between v1 and v2 ip.
- * These registers are offsets from timer->iobase.
- */
-#define OMAP_TIMER_ID_OFFSET 0x00
-#define OMAP_TIMER_OCP_CFG_OFFSET 0x10
-
-#define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14
-#define OMAP_TIMER_V1_STAT_OFFSET 0x18
-#define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c
-
-#define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24
-#define OMAP_TIMER_V2_IRQSTATUS 0x28
-#define OMAP_TIMER_V2_IRQENABLE_SET 0x2c
-#define OMAP_TIMER_V2_IRQENABLE_CLR 0x30
-
-/*
- * The functional registers have a different base on v1 and v2 ip.
- * These registers are offsets from timer->func_base. The func_base
- * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
- *
- */
-#define OMAP_TIMER_V2_FUNC_OFFSET 0x14
-
-#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
-#define _OMAP_TIMER_CTRL_OFFSET 0x24
-#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
-#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
-#define OMAP_TIMER_CTRL_PT (1 << 12)
-#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
-#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
-#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
-#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
-#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
-#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
-#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
-#define OMAP_TIMER_CTRL_POSTED (1 << 2)
-#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
-#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
-#define _OMAP_TIMER_COUNTER_OFFSET 0x28
-#define _OMAP_TIMER_LOAD_OFFSET 0x2c
-#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
-#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
-#define WP_NONE 0 /* no write pending bit */
-#define WP_TCLR (1 << 0)
-#define WP_TCRR (1 << 1)
-#define WP_TLDR (1 << 2)
-#define WP_TTGR (1 << 3)
-#define WP_TMAR (1 << 4)
-#define WP_TPIR (1 << 5)
-#define WP_TNIR (1 << 6)
-#define WP_TCVR (1 << 7)
-#define WP_TOCR (1 << 8)
-#define WP_TOWR (1 << 9)
-#define _OMAP_TIMER_MATCH_OFFSET 0x38
-#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
-#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
-#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
-#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
-#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
-#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
-#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
-#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
-
-/* register offsets with the write pending bit encoded */
-#define WPSHIFT 16
-
-#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
- | (WP_TCLR << WPSHIFT))
-
-#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
- | (WP_TCRR << WPSHIFT))
-
-#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
- | (WP_TLDR << WPSHIFT))
-
-#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
- | (WP_TTGR << WPSHIFT))
-
-#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
- | (WP_TMAR << WPSHIFT))
-
-#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
- | (WP_TPIR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
- | (WP_TNIR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
- | (WP_TCVR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
- (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
- (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
-
-static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
- int posted)
-{
- if (posted)
- while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
- cpu_relax();
-
- return __raw_readl(timer->func_base + (reg & 0xff));
-}
-
-static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
- u32 reg, u32 val, int posted)
-{
- if (posted)
- while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
- cpu_relax();
-
- __raw_writel(val, timer->func_base + (reg & 0xff));
-}
-
-static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
-{
- u32 tidr;
-
- /* Assume v1 ip if bits [31:16] are zero */
- tidr = __raw_readl(timer->io_base);
- if (!(tidr >> 16)) {
- timer->revision = 1;
- timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
- timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
- timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
- timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
- timer->func_base = timer->io_base;
- } else {
- timer->revision = 2;
- timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
- timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
- timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
- timer->pend = timer->io_base +
- _OMAP_TIMER_WRITE_PEND_OFFSET +
- OMAP_TIMER_V2_FUNC_OFFSET;
- timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
- }
-}
-
-/*
- * __omap_dm_timer_enable_posted - enables write posted mode
- * @timer: pointer to timer instance handle
- *
- * Enables the write posted mode for the timer. When posted mode is enabled
- * writes to certain timer registers are immediately acknowledged by the
- * internal bus and hence prevents stalling the CPU waiting for the write to
- * complete. Enabling this feature can improve performance for writing to the
- * timer registers.
- */
-static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
-{
- if (timer->posted)
- return;
-
- if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
- return;
-
- __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
- OMAP_TIMER_CTRL_POSTED, 0);
- timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
- timer->posted = OMAP_TIMER_POSTED;
-}
-
-/**
- * __omap_dm_timer_override_errata - override errata flags for a timer
- * @timer: pointer to timer handle
- * @errata: errata flags to be ignored
- *
- * For a given timer, override a timer errata by clearing the flags
- * specified by the errata argument. A specific erratum should only be
- * overridden for a timer if the timer is used in such a way the erratum
- * has no impact.
- */
-static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
- u32 errata)
-{
- timer->errata &= ~errata;
-}
-
-static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
- int posted, unsigned long rate)
-{
- u32 l;
-
- l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
- if (l & OMAP_TIMER_CTRL_ST) {
- l &= ~0x1;
- __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
-#ifdef CONFIG_ARCH_OMAP2PLUS
- /* Readback to make sure write has completed */
- __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
- /*
- * Wait for functional clock period x 3.5 to make sure that
- * timer is stopped
- */
- udelay(3500000 / rate + 1);
-#endif
- }
-
- /* Ack possibly pending interrupt */
- __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
-}
-
-static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
- u32 ctrl, unsigned int load,
- int posted)
-{
- __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
- __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
-}
-
-static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
- unsigned int value)
-{
- __raw_writel(value, timer->irq_ena);
- __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
-}
-
-static inline unsigned int
-__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
-{
- return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
-}
-
-static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
- unsigned int value)
-{
- __raw_writel(value, timer->irq_stat);
-}
-
-#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/drivers/staging/tidspbridge/core/dsp-clock.c b/drivers/staging/tidspbridge/core/dsp-clock.c
index b647207..6bb0300 100644
--- a/drivers/staging/tidspbridge/core/dsp-clock.c
+++ b/drivers/staging/tidspbridge/core/dsp-clock.c
@@ -22,7 +22,7 @@
/* ----------------------------------- Host OS */
#include <dspbridge/host_os.h>
-#include <plat/dmtimer.h>
+#include <plat-omap/dmtimer.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
/* ----------------------------------- DSP/BIOS Bridge */
--
1.7.9.5
^ permalink raw reply related
* [PATCH 7/8] ARM: OMAP: Remove unnecessary inclusion of dmtimer.h
From: Jon Hunter @ 2012-11-13 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352830403-1706-1-git-send-email-jon-hunter@ti.com>
Some source files are including dmtimer.h but not actually using any dmtimer
definitions or functions. Therefore, remove the inclusion dmtimer.h from these
source files.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/mach-omap1/timer32k.c | 1 -
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 -
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1 -
arch/arm/mach-omap2/pm-debug.c | 1 -
drivers/staging/tidspbridge/core/ue_deh.c | 1 -
5 files changed, 5 deletions(-)
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 8936819..41152fa 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -51,7 +51,6 @@
#include <asm/mach/time.h>
#include <plat/counter-32k.h>
-#include <plat/dmtimer.h>
#include <mach/hardware.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a8b3368..e8efe3d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -17,7 +17,6 @@
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <plat-omap/dma-omap.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index dc768c5..32d17e3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,7 +18,6 @@
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <plat-omap/dma-omap.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod.h"
#include "mmc.h"
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 3cf4fdf..e2c291f 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -30,7 +30,6 @@
#include "clock.h"
#include "powerdomain.h"
#include "clockdomain.h"
-#include <plat/dmtimer.h>
#include "omap-pm.h"
#include "soc.h"
diff --git a/drivers/staging/tidspbridge/core/ue_deh.c b/drivers/staging/tidspbridge/core/ue_deh.c
index 3d28b23..6aea6f1 100644
--- a/drivers/staging/tidspbridge/core/ue_deh.c
+++ b/drivers/staging/tidspbridge/core/ue_deh.c
@@ -19,7 +19,6 @@
#include <linux/kernel.h>
#include <linux/interrupt.h>
-#include <plat/dmtimer.h>
#include <dspbridge/dbdefs.h>
#include <dspbridge/dspdeh.h>
--
1.7.9.5
^ permalink raw reply related
* [PATCH 6/8] ARM: OMAP: Add platform data header for DMTIMERs
From: Jon Hunter @ 2012-11-13 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352830403-1706-1-git-send-email-jon-hunter@ti.com>
Move definition of dmtimer platform data structure in to its own header
under <linux/platform_data>.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/mach-omap1/timer.c | 1 +
arch/arm/mach-omap2/timer.c | 2 ++
arch/arm/plat-omap/dmtimer.c | 2 ++
arch/arm/plat-omap/include/plat/dmtimer.h | 8 -------
include/linux/platform_data/dmtimer-omap.h | 31 ++++++++++++++++++++++++++++
5 files changed, 36 insertions(+), 8 deletions(-)
create mode 100644 include/linux/platform_data/dmtimer-omap.h
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index cdeb9d3..bde7a35 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -25,6 +25,7 @@
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
+#include <linux/platform_data/dmtimer-omap.h>
#include <mach/irqs.h>
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 1a662df..4daa8b4 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -39,6 +39,8 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/dmtimer-omap.h>
#include <asm/mach/time.h>
#include <asm/smp_twd.h>
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index efe4774..89585c2 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -43,6 +43,8 @@
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/dmtimer-omap.h>
#include <plat/dmtimer.h>
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index b3cd91b..a3fbc48 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -124,14 +124,6 @@ struct omap_dm_timer {
struct list_head node;
};
-struct dmtimer_platform_data {
- /* set_timer_src - Only used for OMAP1 devices */
- int (*set_timer_src)(struct platform_device *pdev, int source);
- u32 timer_errata;
- u32 timer_capability;
- int (*get_context_loss_count)(struct device *);
-};
-
int omap_dm_timer_reserve_systimer(int id);
struct omap_dm_timer *omap_dm_timer_request(void);
struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
diff --git a/include/linux/platform_data/dmtimer-omap.h b/include/linux/platform_data/dmtimer-omap.h
new file mode 100644
index 0000000..a19b78d
--- /dev/null
+++ b/include/linux/platform_data/dmtimer-omap.h
@@ -0,0 +1,31 @@
+/*
+ * DMTIMER platform data for TI OMAP platforms
+ *
+ * Copyright (C) 2012 Texas Instruments
+ * Author: Jon Hunter <jon-hunter@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __PLATFORM_DATA_DMTIMER_OMAP_H__
+#define __PLATFORM_DATA_DMTIMER_OMAP_H__
+
+struct dmtimer_platform_data {
+ /* set_timer_src - Only used for OMAP1 devices */
+ int (*set_timer_src)(struct platform_device *pdev, int source);
+ u32 timer_capability;
+ u32 timer_errata;
+ int (*get_context_loss_count)(struct device *);
+};
+
+#endif /* __PLATFORM_DATA_DMTIMER_OMAP_H__ */
--
1.7.9.5
^ permalink raw reply related
* [PATCH 5/8] ARM: OMAP: Remove unnecessary omap_dm_timer structure declaration
From: Jon Hunter @ 2012-11-13 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352830403-1706-1-git-send-email-jon-hunter@ti.com>
Remove unnecessary declaration of structure omap_dm_timer from dmtimer.h and
move the actual declaration of structure omap_dm_timer towards top of dmtimer.h
to avoid any compilation errors.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/plat-omap/include/plat/dmtimer.h | 52 ++++++++++++++---------------
1 file changed, 25 insertions(+), 27 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index b60e2b6..b3cd91b 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -79,8 +79,6 @@ struct omap_timer_capability_dev_attr {
u32 timer_capability;
};
-struct omap_dm_timer;
-
struct timer_regs {
u32 tidr;
u32 tier;
@@ -101,6 +99,31 @@ struct timer_regs {
u32 towr;
};
+struct omap_dm_timer {
+ int id;
+ int irq;
+ struct clk *fclk;
+
+ void __iomem *io_base;
+ void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
+ void __iomem *irq_ena; /* irq enable */
+ void __iomem *irq_dis; /* irq disable, only on v2 ip */
+ void __iomem *pend; /* write pending */
+ void __iomem *func_base; /* function register base */
+
+ unsigned long rate;
+ unsigned reserved:1;
+ unsigned posted:1;
+ struct timer_regs context;
+ int (*get_context_loss_count)(struct device *);
+ int ctx_loss_count;
+ int revision;
+ u32 capability;
+ u32 errata;
+ struct platform_device *pdev;
+ struct list_head node;
+};
+
struct dmtimer_platform_data {
/* set_timer_src - Only used for OMAP1 devices */
int (*set_timer_src)(struct platform_device *pdev, int source);
@@ -260,31 +283,6 @@ int omap_dm_timers_active(void);
#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
-struct omap_dm_timer {
- int id;
- int irq;
- struct clk *fclk;
-
- void __iomem *io_base;
- void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
- void __iomem *irq_ena; /* irq enable */
- void __iomem *irq_dis; /* irq disable, only on v2 ip */
- void __iomem *pend; /* write pending */
- void __iomem *func_base; /* function register base */
-
- unsigned long rate;
- unsigned reserved:1;
- unsigned posted:1;
- struct timer_regs context;
- int (*get_context_loss_count)(struct device *);
- int ctx_loss_count;
- int revision;
- u32 capability;
- u32 errata;
- struct platform_device *pdev;
- struct list_head node;
-};
-
static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
int posted)
{
--
1.7.9.5
^ permalink raw reply related
* [PATCH 4/8] ARM: OMAP2+: Remove unnecessary local variable in timer code
From: Jon Hunter @ 2012-11-13 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352830403-1706-1-git-send-email-jon-hunter@ti.com>
The function omap_dm_timer_init_one() declares two local variables of
type int that are used to store the return value of functions called.
One such local variable is sufficient and so remove one of these local
variables.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/mach-omap2/timer.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index e9fcc5f..1a662df 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -246,8 +246,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
struct device_node *np;
struct omap_hwmod *oh;
struct resource irq, mem;
- int res = 0;
- int r;
+ int r = 0;
if (of_have_populated_dt()) {
np = omap_get_timer_dt(omap_timer_match, NULL);
@@ -307,10 +306,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
src = clk_get(NULL, fck_source);
if (IS_ERR(src)) {
- res = -EINVAL;
+ r = -EINVAL;
} else {
- res = clk_set_parent(timer->fclk, src);
- if (IS_ERR_VALUE(res))
+ r = clk_set_parent(timer->fclk, src);
+ if (IS_ERR_VALUE(r))
pr_warn("%s: %s cannot set source\n",
__func__, oh->name);
clk_put(src);
@@ -331,7 +330,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
timer->rate = clk_get_rate(timer->fclk);
timer->reserved = 1;
- return res;
+ return r;
}
static void __init omap2_gp_clockevent_init(int gptimer_id,
--
1.7.9.5
^ permalink raw reply related
* [PATCH 3/8] ARM: OMAP: Don't store timers physical address
From: Jon Hunter @ 2012-11-13 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352830403-1706-1-git-send-email-jon-hunter@ti.com>
The OMAP2+ system timer code stores the physical address of the timer
but never uses it. Remove this and clean-up the code by removing the
local variable "size" and changing the names of the local variables
mem_rsrc and irq_rsrc to mem and irq, respectively.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/mach-omap2/timer.c | 13 +++++--------
arch/arm/plat-omap/include/plat/dmtimer.h | 1 -
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 099e406..e9fcc5f 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -245,8 +245,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
const char *oh_name;
struct device_node *np;
struct omap_hwmod *oh;
- struct resource irq_rsrc, mem_rsrc;
- size_t size;
+ struct resource irq, mem;
int res = 0;
int r;
@@ -280,20 +279,18 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
if (!of_have_populated_dt()) {
r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
- &irq_rsrc);
+ &irq);
if (r)
return -ENXIO;
- timer->irq = irq_rsrc.start;
+ timer->irq = irq.start;
r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
- &mem_rsrc);
+ &mem);
if (r)
return -ENXIO;
- timer->phys_base = mem_rsrc.start;
- size = mem_rsrc.end - mem_rsrc.start;
/* Static mapping, never released */
- timer->io_base = ioremap(timer->phys_base, size);
+ timer->io_base = ioremap(mem.start, mem.end - mem.start);
}
if (!timer->io_base)
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 40383b6..b60e2b6 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -261,7 +261,6 @@ int omap_dm_timers_active(void);
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
struct omap_dm_timer {
- unsigned long phys_base;
int id;
int irq;
struct clk *fclk;
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/8] ARM: OMAP: Define omap_dm_timer_prepare function as static
From: Jon Hunter @ 2012-11-13 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352830403-1706-1-git-send-email-jon-hunter@ti.com>
The omap_dm_timer_prepare function is a local function only used in the
dmtimer.c file. Therefore, make this a static function and remove its
declaration from the dmtimer.h file.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/plat-omap/dmtimer.c | 2 +-
arch/arm/plat-omap/include/plat/dmtimer.h | 2 --
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 4c28452..efe4774 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -128,7 +128,7 @@ static int omap_dm_timer_reset(struct omap_dm_timer *timer)
return 0;
}
-int omap_dm_timer_prepare(struct omap_dm_timer *timer)
+static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
{
int rc;
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index c5c890d..40383b6 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -286,8 +286,6 @@ struct omap_dm_timer {
struct list_head node;
};
-int omap_dm_timer_prepare(struct omap_dm_timer *timer);
-
static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
int posted)
{
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/8] ARM: OMAP: Clean-up dmtimer reset code
From: Jon Hunter @ 2012-11-13 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352830403-1706-1-git-send-email-jon-hunter@ti.com>
Only OMAP1 devices use the omap_dm_timer_reset() and so require the
omap_dm_timer_wait_for_reset() and __omap_dm_timer_reset() functions.
Therefore combine these into a single function called omap_dm_timer_reset()
and simplify the code.
The omap_dm_timer_reset() function is now the only place that is using the
omap_dm_timer structure member "sys_stat". Therefore, remove this member and
just use the register offset definition to simplify and clean-up the code. The
TISTAT register is only present on revision 1 timers and so check for this in
the omap_dm_timer_reset() function.
Please note that for OMAP1 devices, the TIOCP_CFG register does not have the
clock-activity field and so when we reset the timer for an OMAP1 device we
only need to configure the idle-mode field in the TIOCP_CFG register.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/plat-omap/dmtimer.c | 50 ++++++++++++++++++-----------
arch/arm/plat-omap/include/plat/dmtimer.h | 23 -------------
2 files changed, 31 insertions(+), 42 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 9deeb30..4c28452 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -99,32 +99,39 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer)
timer->context.tclr);
}
-static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
+static int omap_dm_timer_reset(struct omap_dm_timer *timer)
{
- int c;
+ u32 l, timeout = 100000;
- if (!timer->sys_stat)
- return;
+ if (timer->revision != 1)
+ return -EINVAL;
- c = 0;
- while (!(__raw_readl(timer->sys_stat) & 1)) {
- c++;
- if (c > 100000) {
- printk(KERN_ERR "Timer failed to reset\n");
- return;
- }
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
+
+ do {
+ l = __omap_dm_timer_read(timer,
+ OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
+ } while (!l && timeout--);
+
+ if (!timeout) {
+ dev_err(&timer->pdev->dev, "Timer failed to reset\n");
+ return -ETIMEDOUT;
}
-}
-static void omap_dm_timer_reset(struct omap_dm_timer *timer)
-{
- omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
- omap_dm_timer_wait_for_reset(timer);
- __omap_dm_timer_reset(timer, 0, 0);
+ /* Configure timer for smart-idle mode */
+ l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
+ l |= 0x2 << 0x3;
+ __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
+
+ timer->posted = 0;
+
+ return 0;
}
int omap_dm_timer_prepare(struct omap_dm_timer *timer)
{
+ int rc;
+
/*
* FIXME: OMAP1 devices do not use the clock framework for dmtimers so
* do not call clk_get() for these devices.
@@ -140,8 +147,13 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer)
omap_dm_timer_enable(timer);
- if (timer->capability & OMAP_TIMER_NEEDS_RESET)
- omap_dm_timer_reset(timer);
+ if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
+ rc = omap_dm_timer_reset(timer);
+ if (rc) {
+ omap_dm_timer_disable(timer);
+ return rc;
+ }
+ }
__omap_dm_timer_enable_posted(timer);
omap_dm_timer_disable(timer);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 05a36e1..c5c890d 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -267,7 +267,6 @@ struct omap_dm_timer {
struct clk *fclk;
void __iomem *io_base;
- void __iomem *sys_stat; /* TISTAT timer status */
void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
void __iomem *irq_ena; /* irq enable */
void __iomem *irq_dis; /* irq disable, only on v2 ip */
@@ -317,8 +316,6 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
tidr = __raw_readl(timer->io_base);
if (!(tidr >> 16)) {
timer->revision = 1;
- timer->sys_stat = timer->io_base +
- OMAP_TIMER_V1_SYS_STAT_OFFSET;
timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
@@ -326,7 +323,6 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
timer->func_base = timer->io_base;
} else {
timer->revision = 2;
- timer->sys_stat = NULL;
timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
@@ -337,25 +333,6 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
}
}
-/* Assumes the source clock has been set by caller */
-static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
- int autoidle, int wakeup)
-{
- u32 l;
-
- l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
- l |= 0x02 << 3; /* Set to smart-idle mode */
- l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
-
- if (autoidle)
- l |= 0x1 << 0;
-
- if (wakeup)
- l |= 1 << 2;
-
- __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
-}
-
/*
* __omap_dm_timer_enable_posted - enables write posted mode
* @timer: pointer to timer instance handle
--
1.7.9.5
^ permalink raw reply related
* [PATCH 0/8] ARM: OMAP: Clean-up DMTIMER
From: Jon Hunter @ 2012-11-13 18:13 UTC (permalink / raw)
To: linux-arm-kernel
This series cleans-up the DMTIMER code and moves the DMTIMER header
from plat/dmtimer.h to plat-omap/dmtimer.h in preparation for single
zImage support.
This series in based upon DMTIMER fixes series [1].
Tested on OMAP5912 OSK, OMAP3430 Beagle and OMAP4430 Panda.
Testing includes ...
1. Booting kernel on above boards
2. Checking the timer counter is incrementing when configuring and starting
a timer
3. Checking the timer overflow interrupt when timer expires.
4. Using different clock sources to operate the timer with.
This has also been boot tested on the AM335x Beagle Bone.
[1] http://marc.info/?l=linux-omap&m=135275633628412&w=2
Jon Hunter (8):
ARM: OMAP: Clean-up dmtimer reset code
ARM: OMAP: Define omap_dm_timer_prepare function as static
ARM: OMAP: Don't store timers physical address
ARM: OMAP2+: Remove unnecessary local variable in timer code
ARM: OMAP: Remove unnecessary omap_dm_timer structure declaration
ARM: OMAP: Add platform data header for DMTIMERs
ARM: OMAP: Remove unnecessary inclusion of dmtimer.h
ARM: OMAP: Move plat/dmtimer.h to plat-omap/dmtimer.h
arch/arm/mach-omap1/pm.c | 2 +-
arch/arm/mach-omap1/timer.c | 3 +-
arch/arm/mach-omap1/timer32k.c | 1 -
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 -
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1 -
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 +-
arch/arm/mach-omap2/pm-debug.c | 1 -
arch/arm/mach-omap2/timer.c | 28 +-
arch/arm/plat-omap/dmtimer.c | 56 ++-
arch/arm/plat-omap/include/plat-omap/dmtimer.h | 420 ++++++++++++++++++
arch/arm/plat-omap/include/plat/dmtimer.h | 450 --------------------
drivers/staging/tidspbridge/core/dsp-clock.c | 2 +-
drivers/staging/tidspbridge/core/ue_deh.c | 1 -
include/linux/platform_data/dmtimer-omap.h | 31 ++
16 files changed, 506 insertions(+), 497 deletions(-)
create mode 100644 arch/arm/plat-omap/include/plat-omap/dmtimer.h
delete mode 100644 arch/arm/plat-omap/include/plat/dmtimer.h
create mode 100644 include/linux/platform_data/dmtimer-omap.h
--
1.7.9.5
^ permalink raw reply
* [PATCH v2] Add support for generic BCM SoC chipsets
From: Christian Daudt @ 2012-11-13 17:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121112151720.GG28327@n2100.arm.linux.org.uk>
On 12-11-12 07:17 AM, Russell King - ARM Linux wrote:
> On Sun, Nov 11, 2012 at 06:57:14AM -0800, Christian Daudt wrote:
>> +#include <linux/of_irq.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/init.h>
>> +#include <linux/device.h>
>> +#include <linux/platform_device.h>
>> +#include <asm/io.h>
> Please use linux/io.h rather than asm/io.h throughout your patch sets.
> However, I don't see anything in this file which requires this header,
> so it's better off being removed entirely.
>
that will be required later, but you're right. It is not being used at
this point so I've removed it.
thanks,
csd
^ permalink raw reply
* [PATCH v2] Add support for generic BCM SoC chipsets
From: Christian Daudt @ 2012-11-13 17:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A12EA4.90001@wwwdotorg.org>
On 12-11-12 09:15 AM, Stephen Warren wrote:
> On 11/12/2012 10:05 AM, Arnd Bergmann wrote:
>> On Monday 12 November 2012, Domenico Andreoli wrote:
>>> On Mon, Nov 12, 2012 at 03:00:57PM +0000, Arnd Bergmann wrote:
>>>> On Sunday 11 November 2012, Stephen Warren wrote:
>>>>>> I'm following the other mobile ARM SoCs which all have a single mach-
>>>>>> directory for various families of chips (mach-tegra, mach-omap2,
>>>>>> etc...). Plus the intent is to have a single set of mach files that
>>>>>> works across bcm SoCs, so it is preferable to keep it in a single mach-bcm.
>>>>> It's quite possible to create one directory now, e.g. mach-bcm281xx, and
>>>>> then when consolidation with other mach-bcm* happens, merge all those
>>>>> directories into a single mach-bcm. I would tend to prefer (but only
>>>>> lightly) using mach-bcm281xx now and then renaming later, unless you
>>>>> plan on expanding the SoC support in the pretty near future.
>>>> I think the main question is how many files we expect to see in the
>>>> platform directories for each of bcm3528, bcm281xx and bcm476x. Right
>>>> now, my feeling is that each of them can be a single file, since most
>>>> of the stuff that has traditionally been in mach-* directories is
>>>> moving out to drivers now.
>>> I expect only DT-only stuff will be mainlined so one directory
>>> (plat-brcm?) should be ok, right?
>> Right. The usual naming is to use 'mach-*' for one platform, and 'plat-*'
>> for stuff that spreads multiple 'mach-*' directories. In this case, the
>> name I would expect is either 'mach-bcm' as Christian suggested, or
>> 'mach-brcm' if people have strong opinions in favor of that, but not
>> 'plat-brcm'.
>>
>>>> You still have to work out how you want to maintain that directory though,
>>>> either just having per-file maintainers, or having multiple people
>>>> take responsible for the entire directory.
>>> I'd like to take care of the bcm476x and related drivers unless Broadcom
>>> wants to do it.
>> Yes, of course.
>>
>>> Let me know in which directory.
>> I'll let you work that out with Stephen and Christian. I think just
>> 'mach-bcm' is sufficent, but I think the three of you should come to
>> an agreement first.
> I don't really have too strong of a preference. If the eventual intent
> is for the directory to host all ARM Broadcom SoCs, then mach-bcm seems
> reasonable.
>
Ok, sounds like sticking to mach-bcm has sufficient acks. What I was
thinking of doing is, once mach-bcm had been introduced, to propose to
pull in the 476x and 2835 into also, to do some consolidation. And have
the separate files can keep separate owners - we'd just have Kconfig +
Makefile shared most likely.
Or not. Ultimately I don't mind keeping 2835 and 476x as separate
mach- either. Those are v6 SoCs, and at this point I have no plans on
working on mobile v6 SoCs, only v7 onwards. So we can also say that
mach-bcm is for v7+ SoCs and v6 SoCs keep their existing mach- dirs for now.
I personally have no strong preference either, just went with mach-bcm
because, as Arnd mentioned, going forward these are going to be mostly
empty dirs if we stick to one dir per chipset family. So unless there
are strong objections, I'll just stick to mach-bcm for my patches, and
if Stephen and/or Domenico want to consolidate into a single dir later,
we can do that. If not, we can stick to these 3 dirs.
Thanks,
csd
^ permalink raw reply
* [GIT PULL 1/6] omap cleanup fixes for v3.8 merge window
From: Tony Lindgren @ 2012-11-13 17:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121113010539.GZ6801@atomide.com>
* Tony Lindgren <tony@atomide.com> [121112 17:07]:
> * Tony Lindgren <ton@atomide.com> [121112 17:01]:
> > The following changes since commit edf8dde393f879fc2d8c22d4bc01ff8d37b80e1a:
> >
> > Merge branch 'linus' into omap-for-v3.8/cleanup-headers-prepare-multiplatform-v3 (2012-11-09 14:58:01 -0800)
> >
> > are available in the git repository at:
> >
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.8/cleanup-fixes-signed
> >
> > for you to fetch changes up to e05cf58d50e3ce3601ebf753728eee0df759e38f:
> >
> > ARM: OMAP2+: remove duplicated include from board-overo.c (2012-11-12 14:02:48 -0800)
> >
> > ----------------------------------------------------------------
> > Minor fixes to the clean-up done for ARM common multi-platform
> > support for omaps.
>
> FYI, some of the pull requests after this one may break
> compile for omap2plus_defconfig when merging them in.
>
> I suggest you pull requests 2 - 6 with --no-commit option and
> make sure it builds after each pull if you have a chance.
> Or I can follow up with fixes if needed.
>
> If in doubt, I've pushded omap-for-v3.8/tmp-merge that's a
> merge of v3.7-rc5 + recently pulled omap fixes + these pull
> requests merged together for reference.
Hmm looks like requests 2 - 6 never made it to the lists
for whatever reason. I'll resend these, no changes have been
made to the pull requests.
Regards,
Tony
^ permalink raw reply
* [PATCH v4 9/9] pinctrl: single: dump pinmux register value
From: Tony Lindgren @ 2012-11-13 17:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdYRvEzTr6kOE6XYmrKiztJ0F+HUFCv8Jd+m2c-AOFooAw@mail.gmail.com>
* Linus Walleij <linus.walleij@linaro.org> [121113 05:10]:
> On Thu, Nov 8, 2012 at 2:25 AM, Tony Lindgren <tony@atomide.com> wrote:
>
> > * Haojian Zhuang <haojian.zhuang@gmail.com> [121107 07:22]:
> >> Dump pinmux register value, not only function part in the pinmux
> >> register.
> >>
> >> Also fix the issue on caluclating pin offset. The last parameter
> >> should be pin number, not register offset.
> >
> > Acked-by: Tony Lindgren <tony@atomide.com>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> Shall I apply this to the pinctrl tree?
Yes please.
Regards,
Tony
^ permalink raw reply
* [PATCH v4 2/9] pinctrl: single: support gpio request and free
From: Tony Lindgren @ 2012-11-13 17:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdbJzjZGLmCA+2mw6ahAVUXuhdpysnyiK7nuj8PLh_QNXg@mail.gmail.com>
* Linus Walleij <linus.walleij@linaro.org> [121113 05:09]:
> On Wed, Nov 7, 2012 at 11:27 PM, Tony Lindgren <tony@atomide.com> wrote:
> > * Haojian Zhuang <haojian.zhuang@gmail.com> [121107 07:21]:
> >> Marvell's PXA/MMP silicon also match the behavior of pinctrl-single.
> >> Each pin binds to one register. A lot of pins could be configured
> >> as gpio.
> >>
> >> Now add these properties in below.
> >> <gpio range phandle>:
> >> include "pinctrl-single,gpio" & "pinctrl,gpio-func" properties.
> >>
> >> pinctrl-single,gpio: <gpio base, npins in range, register offset>
> >>
> >> pinctrl-single,gpio-func: <gpio function value in mux>
> >>
> >> pinctrl-single,gpio-ranges: phandle list of gpio range array
> >
> > This one looks OK to me now:
> >
> > Acked-by: Tony Lindgren <tony@atomide.com>
> >
>
> So:
> - Will this patch in isolation apply to my pinctrl tree?
> - In that case, do you want me to apply it?
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
I guess the best way to go is if Linus applies this and
the debugfs fix one into some immutable pinctrl branch that
various SoC branches can pull in as needed.
The generic pinconf patch still needs few updates.
Regards,
Tony
^ permalink raw reply
* [PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ
From: Dave Martin @ 2012-11-13 17:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0154077FE026E54BB093CA7EB3FD1AE32B57AF1B59@SAFEX1MAIL3.st.com>
On Tue, Nov 13, 2012 at 04:08:14PM +0000, Etienne CARRIERE wrote:
> From: Etienne Carriere <etienne.carriere@stericsson.com>
>
>
>
> Secure code in TrustZone space may need to perform L2 cache
>
> maintenance operations. A shared mutex is required to synchronize
>
> linux l2cc maintenance and TZ l2cc maintenance.
1) Why is this not a denial-of-service risk? (i.e., why can the Normal
World not simply hold the mutex forever?)
2) The memory types on both sides have to be _exactly_ the same, not
just "cached", otherwise unpredictable behaviour may occur when accessing
the mutex. It is not obvious how this is ensured.
3) Many people seem to delegate L2 cache maintenence requests via SMC
in these situations. Can you do that instead?
Cheers
---Dave
> The TZ mutex is an "arch_spinlock": a 32bit DDR cell (ARMv7-A mutex).
>
> Linux L2 cache driver must lock TZ mutex if enabled.
>
>
>
> Signed-off-by: Etienne Carriere <etienne.carriere@stericsson.com>
>
> ---
>
> arch/arm/include/asm/outercache.h | 9 ++++
>
> arch/arm/mm/cache-l2x0.c | 87 +++++++++++++++++++++++++++++----------
>
> 2 files changed, 74 insertions(+), 22 deletions(-)
>
>
>
> diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/
> outercache.h
>
> index 53426c6..7aa5eac 100644
>
> --- a/arch/arm/include/asm/outercache.h
>
> +++ b/arch/arm/include/asm/outercache.h
>
> @@ -35,6 +35,7 @@ struct outer_cache_fns {
>
> #endif
>
> void (*set_debug)(unsigned long);
>
> void (*resume)(void);
>
> + bool (*tz_mutex)(unsigned long);
>
> };
>
> #ifdef CONFIG_OUTER_CACHE
>
> @@ -81,6 +82,13 @@ static inline void outer_resume(void)
>
> outer_cache.resume();
>
> }
>
> +static inline bool outer_tz_mutex(unsigned long addr)
>
> +{
>
> + if (outer_cache.tz_mutex)
>
> + return outer_cache.tz_mutex(addr);
>
> + return false;
>
> +}
>
> +
>
> #else
>
> static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
>
> @@ -92,6 +100,7 @@ static inline void outer_flush_range(phys_addr_t start,
> phys_addr_t end)
>
> static inline void outer_flush_all(void) { }
>
> static inline void outer_inv_all(void) { }
>
> static inline void outer_disable(void) { }
>
> +static inline bool outer_tz_mutex(unsigned long addr) { return false; }
>
> #endif
>
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>
> index a53fd2a..eacdc74 100644
>
> --- a/arch/arm/mm/cache-l2x0.c
>
> +++ b/arch/arm/mm/cache-l2x0.c
>
> @@ -41,6 +41,26 @@ struct l2x0_of_data {
>
> void (*resume)(void);
>
> };
>
> +/*
>
> + * arch_spinlock (single 32bit DDR mutex cell) pointer to synchronise
>
> + * L2CC maintenance between linux world and secure world (ARM TZ).
>
> + */
>
> +arch_spinlock_t *l2x0_tz_mutex;
>
> +
>
> +#define l2x0_spin_lock_irqsave(flags) \
>
> + do
> {
> \
>
> + raw_spin_lock_irqsave(&l2x0_lock, flags);
> \
>
> + if (l2x0_tz_mutex)
> \
>
> + arch_spin_lock(l2x0_tz_mutex);
> \
>
> + } while (0)
>
> +
>
> +#define l2x0_spin_unlock_irqrestore(flags) \
>
> + do
> {
> \
>
> + if (l2x0_tz_mutex)
> \
>
> + arch_spin_unlock(l2x0_tz_mutex);
> \
>
> + raw_spin_unlock_irqrestore(&l2x0_lock, flags);
> \
>
> + } while (0)
>
> +
>
> static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
>
> {
>
> /* wait for cache operation by line or way to complete */
>
> @@ -126,9 +146,9 @@ static void l2x0_cache_sync(void)
>
> {
>
> unsigned long flags;
>
> - raw_spin_lock_irqsave(&l2x0_lock, flags);
>
> + l2x0_spin_lock_irqsave(flags);
>
> cache_sync();
>
> - raw_spin_unlock_irqrestore(&l2x0_lock, flags);
>
> + l2x0_spin_unlock_irqrestore(flags);
>
> }
>
> static void __l2x0_flush_all(void)
>
> @@ -145,9 +165,9 @@ static void l2x0_flush_all(void)
>
> unsigned long flags;
>
> /* clean all ways */
>
> - raw_spin_lock_irqsave(&l2x0_lock, flags);
>
> + l2x0_spin_lock_irqsave(flags);
>
> __l2x0_flush_all();
>
> - raw_spin_unlock_irqrestore(&l2x0_lock, flags);
>
> + l2x0_spin_unlock_irqrestore(flags);
>
> }
>
> static void l2x0_clean_all(void)
>
> @@ -155,11 +175,11 @@ static void l2x0_clean_all(void)
>
> unsigned long flags;
>
> /* clean all ways */
>
> - raw_spin_lock_irqsave(&l2x0_lock, flags);
>
> + l2x0_spin_lock_irqsave(flags);
>
> writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
>
> cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
>
> cache_sync();
>
> - raw_spin_unlock_irqrestore(&l2x0_lock, flags);
>
> + l2x0_spin_unlock_irqrestore(flags);
>
> }
>
> static void l2x0_inv_all(void)
>
> @@ -167,13 +187,13 @@ static void l2x0_inv_all(void)
>
> unsigned long flags;
>
> /* invalidate all ways */
>
> - raw_spin_lock_irqsave(&l2x0_lock, flags);
>
> + l2x0_spin_lock_irqsave(flags);
>
> /* Invalidating when L2 is enabled is a nono */
>
> BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
>
> writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
>
> cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
>
> cache_sync();
>
> - raw_spin_unlock_irqrestore(&l2x0_lock, flags);
>
> + l2x0_spin_unlock_irqrestore(flags);
>
> }
>
> static void l2x0_inv_range(unsigned long start, unsigned long end)
>
> @@ -181,7 +201,7 @@ static void l2x0_inv_range(unsigned long start, unsigned
> long end)
>
> void __iomem *base = l2x0_base;
>
> unsigned long flags;
>
> - raw_spin_lock_irqsave(&l2x0_lock, flags);
>
> + l2x0_spin_lock_irqsave(flags);
>
> if (start & (CACHE_LINE_SIZE - 1)) {
>
> start &= ~(CACHE_LINE_SIZE - 1);
>
> debug_writel(0x03);
>
> @@ -206,13 +226,13 @@ static void l2x0_inv_range(unsigned long start, unsigned
> long end)
>
> }
>
> if (blk_end < end) {
>
> - raw_spin_unlock_irqrestore(&
> l2x0_lock, flags);
>
> - raw_spin_lock_irqsave(&
> l2x0_lock, flags);
>
> + l2x0_spin_unlock_irqrestore
> (flags);
>
> + l2x0_spin_lock_irqsave(flags);
>
> }
>
> }
>
> cache_wait(base + L2X0_INV_LINE_PA, 1);
>
> cache_sync();
>
> - raw_spin_unlock_irqrestore(&l2x0_lock, flags);
>
> + l2x0_spin_unlock_irqrestore(flags);
>
> }
>
> static void l2x0_clean_range(unsigned long start, unsigned long end)
>
> @@ -225,7 +245,7 @@ static void l2x0_clean_range(unsigned long start, unsigned
> long end)
>
> return;
>
> }
>
> - raw_spin_lock_irqsave(&l2x0_lock, flags);
>
> + l2x0_spin_lock_irqsave(flags);
>
> start &= ~(CACHE_LINE_SIZE - 1);
>
> while (start < end) {
>
> unsigned long blk_end = start + min(end - start,
> 4096UL);
>
> @@ -236,13 +256,13 @@ static void l2x0_clean_range(unsigned long start,
> unsigned long end)
>
> }
>
> if (blk_end < end) {
>
> - raw_spin_unlock_irqrestore(&
> l2x0_lock, flags);
>
> - raw_spin_lock_irqsave(&
> l2x0_lock, flags);
>
> + l2x0_spin_unlock_irqrestore
> (flags);
>
> + l2x0_spin_lock_irqsave(flags);
>
> }
>
> }
>
> cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
>
> cache_sync();
>
> - raw_spin_unlock_irqrestore(&l2x0_lock, flags);
>
> + l2x0_spin_unlock_irqrestore(flags);
>
> }
>
> static void l2x0_flush_range(unsigned long start, unsigned long end)
>
> @@ -255,7 +275,7 @@ static void l2x0_flush_range(unsigned long start, unsigned
> long end)
>
> return;
>
> }
>
> - raw_spin_lock_irqsave(&l2x0_lock, flags);
>
> + l2x0_spin_lock_irqsave(flags);
>
> start &= ~(CACHE_LINE_SIZE - 1);
>
> while (start < end) {
>
> unsigned long blk_end = start + min(end - start,
> 4096UL);
>
> @@ -268,24 +288,24 @@ static void l2x0_flush_range(unsigned long start,
> unsigned long end)
>
> debug_writel(0x00);
>
> if (blk_end < end) {
>
> - raw_spin_unlock_irqrestore(&
> l2x0_lock, flags);
>
> - raw_spin_lock_irqsave(&
> l2x0_lock, flags);
>
> + l2x0_spin_unlock_irqrestore
> (flags);
>
> + l2x0_spin_lock_irqsave(flags);
>
> }
>
> }
>
> cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
>
> cache_sync();
>
> - raw_spin_unlock_irqrestore(&l2x0_lock, flags);
>
> + l2x0_spin_unlock_irqrestore(flags);
>
> }
>
> static void l2x0_disable(void)
>
> {
>
> unsigned long flags;
>
> - raw_spin_lock_irqsave(&l2x0_lock, flags);
>
> + l2x0_spin_lock_irqsave(flags);
>
> __l2x0_flush_all();
>
> writel_relaxed(0, l2x0_base + L2X0_CTRL);
>
> dsb();
>
> - raw_spin_unlock_irqrestore(&l2x0_lock, flags);
>
> + l2x0_spin_unlock_irqrestore(flags);
>
> }
>
> static void l2x0_unlock(u32 cache_id)
>
> @@ -307,6 +327,28 @@ static void l2x0_unlock(u32 cache_id)
>
> }
>
> }
>
> +/* Enable/disable external mutex shared with TZ code */
>
> +static bool l2x0_tz_mutex_cfg(unsigned long addr)
>
> +{
>
> + unsigned long flags;
>
> +
>
> + raw_spin_lock_irqsave(&l2x0_lock, flags);
>
> +
>
> + if (addr && l2x0_tz_mutex && (addr != (uint)l2x0_tz_mutex)) {
>
> + raw_spin_unlock_irqrestore(&l2x0_lock, flags);
>
> + pr_err("%s: a TZ mutex is already enabled\n",
> __func__);
>
> + return false;
>
> + }
>
> +
>
> + l2x0_tz_mutex = (arch_spinlock_t *)addr;
>
> + /* insure mutex ptr is updated before lock is released */
>
> + smp_wmb();
>
> +
>
> + raw_spin_unlock_irqrestore(&l2x0_lock, flags);
>
> + pr_debug("\n%s: %sable TZ mutex\n\n", __func__, (addr) ? "en" :
> "dis");
>
> + return true;
>
> +}
>
> +
>
> void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
>
> {
>
> u32 aux;
>
> @@ -380,6 +422,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32
> aux_mask)
>
> outer_cache.inv_all = l2x0_inv_all;
>
> outer_cache.disable = l2x0_disable;
>
> outer_cache.set_debug = l2x0_set_debug;
>
> + outer_cache.tz_mutex = l2x0_tz_mutex_cfg;
>
> printk(KERN_INFO "%s cache controller enabled\n", type);
>
> printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL
> 0x%08x, Cache size: %d B\n",
>
>
>
> --
>
> 1.7.11.3
>
>
>
^ permalink raw reply
* [GIT PULL] ARM: OMAP: DMTIMER fixes
From: Jon Hunter @ 2012-11-13 17:16 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit d308ba50a1234b299a00e63a95e61fdeb2f1a2df:
Merge branch 'omap-for-v3.8/cleanup-headers-prepare-multiplatform-v3' into omap-for-v3.8/dt (2012-11-09 14:58:34 -0800)
are available in the git repository at:
git at github.com:jonhunter/linux.git fixes-timer
for you to fetch changes up to b1538832191d59e29b1077e64cf416a7617b45bc:
ARM: OMAP: Remove __omap_dm_timer_set_source function (2012-11-12 16:23:57 -0600)
----------------------------------------------------------------
Several fixes for the OMAP DMTIMER driver including ...
1. Adding workaround for OMAP3+ errata i103/i767
2. Fixing posted mode support
3. Spurious interrupts when using match interrupt
4. HWMOD fixes for timers
5. Unnecessary restoration of read-only registers
6. Adds function for disabling timer interrupts
7. Fixing timer1 reset for OMAP1
----------------------------------------------------------------
Jon Hunter (13):
ARM: OMAP: Add DMTIMER definitions for posted mode
ARM: OMAP3+: Implement timer workaround for errata i103 and i767
ARM: OMAP: Fix timer posted mode support
ARM: OMAP3: Correct HWMOD DMTIMER SYSC register declarations
ARM: OMAP2/3: Define HWMOD software reset status for DMTIMERs
ARM: OMAP2+: Don't use __omap_dm_timer_reset()
ARM: OMAP: Fix dmtimer reset for timer1
ARM: OMAP: Don't restore of DMTIMER TISTAT register
ARM: OMAP: Don't restore DMTIMER interrupt status register
ARM: OMAP: Fix spurious interrupts when using timer match feature
ARM: OMAP: Add dmtimer interrupt disable function
ARM: OMAP: Remove unnecessary call to clk_get()
ARM: OMAP: Remove __omap_dm_timer_set_source function
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 15 +++-
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 41 +++++------
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 4 +
arch/arm/mach-omap2/timer.c | 70 +++++++++++++-----
arch/arm/plat-omap/dmtimer.c | 77 ++++++++++++--------
arch/arm/plat-omap/include/plat/dmtimer.h | 72 +++++++++++++-----
6 files changed, 188 insertions(+), 91 deletions(-)
^ permalink raw reply
* [PATCH] bindings: i2c: use consistent naming for i2c binding descriptions
From: Wolfram Sang @ 2012-11-13 17:16 UTC (permalink / raw)
To: linux-arm-kernel
Filenames of devictree binding documentation seems to be arbitrary and
for me it is unneeded hazzle to find the corresponding documentation for
a specific driver.
Naming the description the same as the driver is a lot easier and makes
sense to me since the driver defines the binding it understands.
Also, remove a reference in one source to the binding documentation, since path
information easily gets stale.
Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
Cc: Rob Herring <robherring2@gmail.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
---
I think it would be helpful if other subsystems would follow if we can agree on
this pattern.
Thanks,
Wolfram
.../bindings/i2c/{atmel-i2c.txt => i2c-at91.txt} | 0
.../bindings/i2c/{davinci.txt => i2c-davinci.txt} | 0
.../bindings/i2c/{gpio-i2c.txt => i2c-gpio.txt} | 0
.../bindings/i2c/{fsl-imx-i2c.txt => i2c-imx.txt} | 0
.../bindings/i2c/{fsl-i2c.txt => i2c-mpc.txt} | 0
.../devicetree/bindings/i2c/{mux.txt => i2c-mux.txt} | 0
.../devicetree/bindings/i2c/i2c-mv64xxx.txt | 18 ++++++++++++++++++
.../bindings/i2c/{nomadik.txt => i2c-nomadik.txt} | 0
.../bindings/i2c/{cavium-i2c.txt => i2c-octeon.txt} | 0
.../bindings/i2c/{omap-i2c.txt => i2c-omap.txt} | 0
.../devicetree/bindings/i2c/{pnx.txt => i2c-pnx.txt} | 0
.../i2c/{ce4100-i2c.txt => i2c-pxa-pci-ce4100.txt} | 0
.../bindings/i2c/{mrvl-i2c.txt => i2c-pxa.txt} | 18 ------------------
.../i2c/{samsung-i2c.txt => i2c-s3c2410.txt} | 0
.../bindings/i2c/{sirf-i2c.txt => i2c-sirf.txt} | 0
.../i2c/{arm-versatile.txt => i2c-versatile.txt} | 0
.../bindings/i2c/{xiic.txt => i2c-xiic.txt} | 0
drivers/i2c/busses/i2c-ocores.c | 4 ----
18 files changed, 18 insertions(+), 22 deletions(-)
rename Documentation/devicetree/bindings/i2c/{atmel-i2c.txt => i2c-at91.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{davinci.txt => i2c-davinci.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{gpio-i2c.txt => i2c-gpio.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{fsl-imx-i2c.txt => i2c-imx.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{fsl-i2c.txt => i2c-mpc.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{mux.txt => i2c-mux.txt} (100%)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
rename Documentation/devicetree/bindings/i2c/{nomadik.txt => i2c-nomadik.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{cavium-i2c.txt => i2c-octeon.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{omap-i2c.txt => i2c-omap.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{pnx.txt => i2c-pnx.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{ce4100-i2c.txt => i2c-pxa-pci-ce4100.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{mrvl-i2c.txt => i2c-pxa.txt} (70%)
rename Documentation/devicetree/bindings/i2c/{samsung-i2c.txt => i2c-s3c2410.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{sirf-i2c.txt => i2c-sirf.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{arm-versatile.txt => i2c-versatile.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{xiic.txt => i2c-xiic.txt} (100%)
diff --git a/Documentation/devicetree/bindings/i2c/atmel-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/atmel-i2c.txt
rename to Documentation/devicetree/bindings/i2c/i2c-at91.txt
diff --git a/Documentation/devicetree/bindings/i2c/davinci.txt b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/davinci.txt
rename to Documentation/devicetree/bindings/i2c/i2c-davinci.txt
diff --git a/Documentation/devicetree/bindings/i2c/gpio-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-gpio.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/gpio-i2c.txt
rename to Documentation/devicetree/bindings/i2c/i2c-gpio.txt
diff --git a/Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-imx.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt
rename to Documentation/devicetree/bindings/i2c/i2c-imx.txt
diff --git a/Documentation/devicetree/bindings/i2c/fsl-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-mpc.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/fsl-i2c.txt
rename to Documentation/devicetree/bindings/i2c/i2c-mpc.txt
diff --git a/Documentation/devicetree/bindings/i2c/mux.txt b/Documentation/devicetree/bindings/i2c/i2c-mux.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/mux.txt
rename to Documentation/devicetree/bindings/i2c/i2c-mux.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
new file mode 100644
index 0000000..f46d928
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
@@ -0,0 +1,18 @@
+
+* Marvell MV64XXX I2C controller
+
+Required properties :
+
+ - reg : Offset and length of the register set for the device
+ - compatible : Should be "marvell,mv64xxx-i2c"
+ - interrupts : The interrupt number
+ - clock-frequency : Desired I2C bus clock frequency in Hz.
+
+Examples:
+
+ i2c at 11000 {
+ compatible = "marvell,mv64xxx-i2c";
+ reg = <0x11000 0x20>;
+ interrupts = <29>;
+ clock-frequency = <100000>;
+ };
diff --git a/Documentation/devicetree/bindings/i2c/nomadik.txt b/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/nomadik.txt
rename to Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
diff --git a/Documentation/devicetree/bindings/i2c/cavium-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-octeon.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/cavium-i2c.txt
rename to Documentation/devicetree/bindings/i2c/i2c-octeon.txt
diff --git a/Documentation/devicetree/bindings/i2c/omap-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-omap.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/omap-i2c.txt
rename to Documentation/devicetree/bindings/i2c/i2c-omap.txt
diff --git a/Documentation/devicetree/bindings/i2c/pnx.txt b/Documentation/devicetree/bindings/i2c/i2c-pnx.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/pnx.txt
rename to Documentation/devicetree/bindings/i2c/i2c-pnx.txt
diff --git a/Documentation/devicetree/bindings/i2c/ce4100-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/ce4100-i2c.txt
rename to Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt
diff --git a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
similarity index 70%
rename from Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
rename to Documentation/devicetree/bindings/i2c/i2c-pxa.txt
index 0f79450..12b78ac 100644
--- a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
@@ -31,21 +31,3 @@ Examples:
reg = <0xd4025000 0x1000>;
interrupts = <58>;
};
-
-* Marvell MV64XXX I2C controller
-
-Required properties :
-
- - reg : Offset and length of the register set for the device
- - compatible : Should be "marvell,mv64xxx-i2c"
- - interrupts : The interrupt number
- - clock-frequency : Desired I2C bus clock frequency in Hz.
-
-Examples:
-
- i2c at 11000 {
- compatible = "marvell,mv64xxx-i2c";
- reg = <0x11000 0x20>;
- interrupts = <29>;
- clock-frequency = <100000>;
- };
diff --git a/Documentation/devicetree/bindings/i2c/samsung-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/samsung-i2c.txt
rename to Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
diff --git a/Documentation/devicetree/bindings/i2c/sirf-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-sirf.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/sirf-i2c.txt
rename to Documentation/devicetree/bindings/i2c/i2c-sirf.txt
diff --git a/Documentation/devicetree/bindings/i2c/arm-versatile.txt b/Documentation/devicetree/bindings/i2c/i2c-versatile.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/arm-versatile.txt
rename to Documentation/devicetree/bindings/i2c/i2c-versatile.txt
diff --git a/Documentation/devicetree/bindings/i2c/xiic.txt b/Documentation/devicetree/bindings/i2c/i2c-xiic.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/xiic.txt
rename to Documentation/devicetree/bindings/i2c/i2c-xiic.txt
diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
index bffd550..15da1ac 100644
--- a/drivers/i2c/busses/i2c-ocores.c
+++ b/drivers/i2c/busses/i2c-ocores.c
@@ -9,10 +9,6 @@
* kind, whether express or implied.
*/
-/*
- * This driver can be used from the device tree, see
- * Documentation/devicetree/bindings/i2c/ocore-i2c.txt
- */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
--
1.7.10.4
^ permalink raw reply related
* [PATCH V2 2/11] time: convert arch_gettimeoffset to a pointer
From: Stephen Warren @ 2012-11-13 17:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A16BD3.5010707@us.ibm.com>
On 11/12/2012 02:36 PM, John Stultz wrote:
> On 11/12/2012 12:51 PM, Stephen Warren wrote:
>> Currently, whenever CONFIG_ARCH_USES_GETTIMEOFFSET is enabled, each
>> arch core provides a single implementation of arch_gettimeoffset(). In
>> many cases, different sub-architectures, different machines, or
>> different timer providers exist, and so the arch ends up implementing
>> arch_gettimeoffset() as a call-through-pointer anyway. Examples are
>> ARM, Cris, M68K, and it's arguable that the remaining architectures,
>> M32R and Blackfin, should be doing this anyway.
>>
>> Modify arch_gettimeoffset so that it itself is a function pointer, which
>> the arch initializes. This will allow later changes to move the
>> initialization of this function into individual machine support or timer
>> drivers. This is particularly useful for code in drivers/clocksource
>> which should rely on an arch-independant mechanism to register their
>> implementation of arch_gettimeoffset().
...
> One last thing to watch out for: If you're trying to build a kernel that
> mixes clocksource support with get_arch_timeoffset, you'll need to
> rework the #ifdef in update_wall_time(), since we currently assume with
> get_arch_timeoffset() that you're using tick + interpolation, so every
> call to update_wall_time() only moves time forward by one jiffy.
OK. I don't have any immediate plans to do that, although I wouldn't be
surprised if we (the ARM community in general) end up wanting to do that
at some point. It all depends on which ARM sub-architectures end up
getting converted to the multi-platform zImage support I guess.
> Otherwise, thanks for the name tweak. Going through the arm-soc tree is
> fine with me.
>
> Acked-by: John Stultz <johnstul@us.ibm.com>
Thanks.
^ permalink raw reply
* [PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ
From: Russell King - ARM Linux @ 2012-11-13 17:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0154077FE026E54BB093CA7EB3FD1AE32B57AF1B59@SAFEX1MAIL3.st.com>
On Tue, Nov 13, 2012 at 05:08:14PM +0100, Etienne CARRIERE wrote:
> From: Etienne Carriere <etienne.carriere@stericsson.com>
>
> Secure code in TrustZone space may need to perform L2 cache
> maintenance operations. A shared mutex is required to synchronize
> linux l2cc maintenance and TZ l2cc maintenance.
>
> The TZ mutex is an "arch_spinlock": a 32bit DDR cell (ARMv7-A mutex).
> Linux L2 cache driver must lock TZ mutex if enabled.
>...
> +#define l2x0_spin_lock_irqsave(flags) \
> + do { \
> + raw_spin_lock_irqsave(&l2x0_lock, flags); \
> + if (l2x0_tz_mutex) \
> + arch_spin_lock(l2x0_tz_mutex); \
> + } while (0)
Right, so, what this tells me is that the implementation of the spinlock
in the secure software is potentially the same as the kernel's spinlock.
The kernel's spinlock implementation is GPL'd. If the secure side spinlock
implementation is a copy of the kernel's spinlock implementation, then that
implementation is also GPL'd, which, as it is linked with the rest of the
secure software, either the whole of the secure software suite is GPL'd
_or_ it is in violation of the GPL.
I think someone has some explaining to do.
^ permalink raw reply
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