* [PATCH] ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER
From: Igor Grinberg @ 2012-11-14 7:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A271A7.2000305@ti.com>
On 11/13/12 18:13, Jon Hunter wrote:
>
> On 11/13/2012 03:14 AM, Igor Grinberg wrote:
>> On 11/12/12 21:15, Jon Hunter wrote:
>>>
>>> On 11/11/2012 05:28 AM, Igor Grinberg wrote:
>>>>
>>>>
>>>> On 11/08/12 21:16, Jon Hunter wrote:
>>>>>
>>>>> On 11/08/2012 12:59 PM, Hiremath, Vaibhav wrote:
>>>>>> On Fri, Nov 09, 2012 at 00:24:23, Hunter, Jon wrote:
>>>>>>>
>>>>>>> On 11/08/2012 01:59 AM, Igor Grinberg wrote:
>>>>>>>
>>>>>>> [snip]
>>>>>>>
>>>>>>>> There is no reliable way to determine which source should be used in runtime
>>>>>>>> for boards that do not have the 32k oscillator wired.
>>>>>>>
>>>>>>> So thinking about this some more and given that we are moving away from
>>>>>>> board files, if a board does not provide a 32kHz clock source, then this
>>>>>>> should be reflected in the device-tree source file for that board.
>>>>>>> Hence, at boot time we should be able to determine if a 32kHz clock
>>>>>>> source can be used.
>>>>>>>
>>>>>>
>>>>>> Let me feed some more thoughts here :)
>>>>>>
>>>>>> The way it is being detected currently is based on timer idle status bit.
>>>>>> I am worried that, this is the only option we have.
>>>>>
>>>>> Why not use device-tree to indicate the presence of a 32k clock source?
>>>>> This seems like a board level configuration and so device-tree seems to
>>>>> be the perfect place for this IMO.
>>>>
>>>> Well, that is what my commit message says...
>>>
>>> Sorry, but that was not clear to me from whats in the commit message.
>>
>> From the commit message:
>> "1) Timer structures and initialization functions are named by the platform
>> name and the clock source in use. The decision which timer is
>> used is done statically from the machine_desc structure. In the
>> future it should come from DT."
>>
>> The last sentence has it.
>
> Right, but it does not go into the details. It would be good to have
> added a comment to the effect of "some boards do not have a 32k clock
> source and in the future this should be handled by device-tree".
Ok.
>
>> The transition to DT is not immediate and we can't (still) neglect
>> the non-DT setups.
>
> Absolutely, but I am trying to understand if there are boards being
> "neglected". I see now that your CM-T3517 would be. This was not clear
> from your patch as even the CM-T3517 board was being configured to the
> use the sync32k timer. So from looking at your patch I did not see any
> neglected boards, however, I understand your motivation to add all these
> init functions so that boards could be customised easily.
I did not changed the CM-T3517, because I believe it should be done
in a separate patch.
>
>>> Should we be doing this now instead of adding all these static timer
>>> init functions?
>>
>> I don't see this as "adding ...", I see this as expanding the setup
>> which was previously hidden by the CONFIG_OMAP_32K_TIMER option.
>>
>>>
>>> Are there any boards today (supported in the kernel that is), that don't
>>> support a 32k?
>>
>> Yes, starting from revision 1.2, CM-T3517 does not have the 32k.
>
> Thanks, this is the exact information I was looking for. You should put
> this in your commit message to highlight the fact that there are boards
> that don't have a 32k clock source.
>
> I am familiar with the OMAP devices, but less familiar with these AMxxxx
> derivatives (as I don't work with these) and so it is good to put these
> specifics in the commit message.
Ok.
--
Regards,
Igor.
^ permalink raw reply
* [PATCH 1/6] ARM/dts: omap4-panda: Add pinmux configuration for HDMI
From: Tomi Valkeinen @ 2012-11-14 7:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A29B12.9030906@ti.com>
Hi,
On 2012-11-13 21:10, Ricardo Neri wrote:
> Hi Tomi,
>
> On 11/05/2012 07:14 AM, Tomi Valkeinen wrote:
>> From: Ricardo Neri <ricardo.neri@ti.com>
>>
>> Add the pinmux configuration for HDMI and TPD12S015A. Configure the
>> gpios for the TPD12S015A and SDA, SCL and CEC for HDMI.
>
> Do you plan to upstream the complete DT-boot support for DSS
> (specifically, HDMI) for 3.8? I am asking so that I can upstream the
> audio part.
No. This series will enable DSS with DT boot on panda and sdp boards,
but it's achieved by a hack, as the DSS configuration still comes from
platform data.
To get full DSS DT support we need to pretty much rewrite the dss panel
device handling and adapt to common panel framework (which isn't ready yet).
Tomi
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^ permalink raw reply
* [PATCH v3 7/7] crypto: omap_sham: Remove usage of private DMA API
From: Kasatkin, Dmitry @ 2012-11-14 7:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121109171745.GB13898@animalcreek.com>
On Fri, Nov 9, 2012 at 9:17 AM, Mark A. Greer <mgreer@animalcreek.com> wrote:
> On Fri, Nov 09, 2012 at 06:28:16PM +0200, Kasatkin, Dmitry wrote:
>> On Wed, Nov 7, 2012 at 4:57 AM, Mark A. Greer <mgreer@animalcreek.com> wrote:
>> > From: "Mark A. Greer" <mgreer@animalcreek.com>
>> >
>> > Remove usage of the private OMAP DMA API.
>> > The dmaengine API will be used instead.
>> >
>> > CC: Russell King <rmk+kernel@arm.linux.org.uk>
>> > CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
>> > Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
>> > ---
>> > drivers/crypto/omap-sham.c | 117 ---------------------------------------------
>> > 1 file changed, 117 deletions(-)
>> >
>> > diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
>> > index b57277c..ebb5255 100644
>> > --- a/drivers/crypto/omap-sham.c
>> > +++ b/drivers/crypto/omap-sham.c
>
>> > @@ -807,18 +762,6 @@ static int omap_sham_handle_queue(struct omap_sham_dev *dd,
>> > if (err)
>> > goto err1;
>> >
>> > -#ifdef OMAP_SHAM_DMA_PRIVATE
>> > - omap_set_dma_dest_params(dd->dma_lch, 0,
>> > - OMAP_DMA_AMODE_CONSTANT,
>> > - dd->phys_base + SHA_REG_DIN(0), 0, 16);
>> > -
>> > - omap_set_dma_dest_burst_mode(dd->dma_lch,
>> > - OMAP_DMA_DATA_BURST_16);
>> > -
>> > - omap_set_dma_src_burst_mode(dd->dma_lch,
>> > - OMAP_DMA_DATA_BURST_4);
>>
>> Burst mode significantly improves performance.
>> How do you configure burst mode with new API?
>
> This is (or should be) taken care of by the dmaengine infrastructure.
> I've noted that there's an issue and there is a discussion about it
> here:
>
> http://www.spinics.net/lists/linux-omap/msg79855.html
>
> We probably need to extend the dmaengine API to allow API-users to
> request specific tweaks/optimizations/whatever but that's MHO.
>
Hello,
I am in favor of new APIs.
The only my concern is that it performs worse..
Is it possible to keep burst mode setting there?
- Dmitry
> Mark
> --
^ permalink raw reply
* [PATCH] ARM: S3C64XX: Add missing device selects for Cragganmore
From: Mark Brown @ 2012-11-14 7:52 UTC (permalink / raw)
To: linux-arm-kernel
Previously unnoticed due to selection by other machines.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
---
arch/arm/mach-s3c64xx/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 63e7ae3..131c862 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -294,6 +294,7 @@ config MACH_WLF_CRAGG_6410
select S3C64XX_SETUP_SDHCI
select S3C64XX_SETUP_SPI
select S3C64XX_SETUP_USB_PHY
+ select S3C_DEV_FB
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
@@ -304,6 +305,7 @@ config MACH_WLF_CRAGG_6410
select S3C_DEV_WDT
select SAMSUNG_DEV_ADC
select SAMSUNG_DEV_KEYPAD
+ select SAMSUNG_DEV_PWM
select SAMSUNG_GPIO_EXTRA128
help
Machine support for the Wolfson Cragganmore S3C6410 variant.
--
1.7.10.4
^ permalink raw reply related
* arch-vt8500 and wm8850 support
From: Tony Prisk @ 2012-11-14 7:54 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd,
Just looking for a little advice re: adding support for the WM8850
variant.
At the moment we have the ARM926 variants under ARCH_VT8500. The WM8850
is ARMv7, but uses all the same drivers as the ARM926 versions. At the
moment, all the drivers depend on ARCH_VT8500.
The obvious solution (to me at least) seems to be to have 3 groups -
ARCH_VT8500 keeps everything it has now except 'select CPU_ARM926T', and
we add 2 additional groups - the first for all the current models, which
selects CPU_ARM926T and ARCH_VT8500, and a second for WM8850 which
selects CPU_V7 and ARCH_VT8500.
The other option seems to be to add WM8850 as ARCH_newmodel, but that
would require patching all the driver Kconfigs to depends on ARCH_VT8500
|| ARCH_newmodel.
Interested in your feedback.
Regards
Tony P
^ permalink raw reply
* usb clock not found on imx27 when using dt
From: s.hauer at pengutronix.de @ 2012-11-14 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A2B0E8.2040603@yahoo.fr>
On Tue, Nov 13, 2012 at 09:43:20PM +0100, trem wrote:
> On 13/11/12 08:38, s.hauer at pengutronix.de wrote:
> >>>Please investigate in using the chipidea driver. This will be the way
> >>>forward for i.MX.
> >>
> >>I use the chipidea driver for the usb.
> >>
> >>The main issue is that the chipidea driver don't found the clock :
> >>
> >>[ 0.761693] imx_usb mxc-ehci.0: Failed to get clock, err=-2
> >>[ 0.767620] imx_usb: probe of mxc-ehci.0 failed with error -2
> >>
> >>The driver ci13xxx_imx request the clock in the probe function
> >>in the following line:
> >>data->clk = devm_clk_get(&pdev->dev, NULL);
> >>calling: clk = clk_get(dev, id);
> >>calling: clk_get_sys(dev_id, con_id);
> >>calling: clk_find(dev_id, con_id);
> >>with dev_id = mxc-ehci.0 and con_id = NULL
> >>This last function fail to found a clock.
> >>
> >>In the function mx27_clocks_init, several mxc-ehci.0
> >>clocks are registered, but all with a con_id.
> >>
> >>So the function clk_find fails.
> >>
> >>As I'm not really sure of the dts, I don't know if the problem
> >>is in the dts or in the driver (maybe both).
> >
> >You have to register the lookups for the chipidea driver with
> >clk_register_clkdev(). The lookups are only what the name suggests:
> >lookups. They are no clocks by themselves. This means that you have to
> >add another lookup which matches the device name.
>
> Thanks for this help, I've added three "clocks" for the chipidea driver :
> clk_register_clkdev(clk[usb_div], NULL, "mxc-ehci.0");
That does not fit to the chipidea driver. The third argument has to
match the device name (which is the output of dev_name), so in your case
it must be something like 'imx_usb.0' (I don't know if that's correct,
please just add a printk("%s\n", dev_name(dev)); to the chipidea driver
to get the correct string)
Other than that I suggest that you read through drivers/clk/clkdev.c
to see how clock lookups are matched against devices, specifically:
/*
* Find the correct struct clk for the device and connection ID.
* We do slightly fuzzy matching here:
* An entry with a NULL ID is assumed to be a wildcard.
* If an entry has a device ID, it must match
* If an entry has a connection ID, it must match
* Then we take the most specific entry - with the following
* order of precedence: dev+con > dev only > con only.
*/
/**
* clk_register_clkdev - register one clock lookup for a struct clk
* @clk: struct clk to associate with all clk_lookups
* @con_id: connection ID string on device
* @dev_id: format string describing device name
*
* con_id or dev_id may be NULL as a wildcard, just as in the rest of
* clkdev.
*/
> [ 0.754044] usbserial: USB Serial support registered for pl2303
> [ 0.762611] Unhandled fault: external abort on non-linefetch (0x008) at 0xf4424100
> [ 0.770227] Internal error: : 8 [#1] PREEMPT ARM
> [ 0.774861] Modules linked in:
> [ 0.777950] CPU: 0 Not tainted (3.7.0-rc5-ge917a67 #2)
> [ 0.783469] PC is at ci_hdrc_probe+0xcc/0x430
> [ 0.787853] LR is at devm_kzalloc+0x4c/0x64
This seems to be something else. Are you sure you are beyond the clk_get
point? I can't imagine this given the lookup you registered.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 0/4] iommu/exynos: Fixes and Enhancements of System MMU driver with DT
From: Cho KyongHo @ 2012-11-14 8:50 UTC (permalink / raw)
To: linux-arm-kernel
The current exynos-iommu(System MMU) driver does not work autonomously
since it is lack of support for power management of peripheral blocks.
For example, MFC device driver must ensure that its System MMU is disabled
before MFC block is power-down not to invalidate IOTLB in the System MMU
when I/O memory mapping is changed. Because A System MMU is resides in the
same H/W block, access to control registers of System MMU while the H/W
block is turned off must be prohibited.
This set of changes solves the above problem with setting each System MMUs
as the parent of the device which owns the System MMU to recieve the
information when the device is turned off or turned on.
Another big change to the driver is the support for devicetree.
The bindings for System MMU is described in
Documentation/devicetree/bindings/arm/samsung/system-mmu.txt
In addition, this patchset also includes several bug fixes and enhancements
of the current driver.
Patch summary:
[PATCH 1/4] ARM: EXYNOS: remove system mmu initialization from arch/arm/ tree
[PATCH 2/4] ARM: EXYNOS: Add clk_ops for gating clocks of System MMU
[PATCH 3/4] ARM: EXYNOS: add System MMU definition to DT
[PATCH 4/4] iommu/exynos: enhancements of System MMU driver with DT
Diffstats:
.../devicetree/bindings/arm/samsung/system-mmu.txt | 42 +
arch/arm/boot/dts/exynos4210.dtsi | 96 ++
arch/arm/boot/dts/exynos4x12.dtsi | 124 ++
arch/arm/boot/dts/exynos5250.dtsi | 152 ++-
arch/arm/mach-exynos/Kconfig | 5 -
arch/arm/mach-exynos/Makefile | 1 -
arch/arm/mach-exynos/clock-exynos4.c | 41 +-
arch/arm/mach-exynos/clock-exynos4210.c | 9 +-
arch/arm/mach-exynos/clock-exynos4212.c | 23 +-
arch/arm/mach-exynos/clock-exynos5.c | 87 +-
arch/arm/mach-exynos/dev-sysmmu.c | 274 ----
arch/arm/mach-exynos/include/mach/sysmmu.h | 66 -
arch/arm/mach-exynos/mach-exynos4-dt.c | 34 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 30 +
drivers/iommu/Kconfig | 17 +-
drivers/iommu/Makefile | 2 +-
drivers/iommu/exynos-iommu.c | 1420 +++++++++++++++-----
17 files changed, 1652 insertions(+), 771 deletions(-)
^ permalink raw reply
* [PATCH 1/4] ARM: EXYNOS: remove system mmu initialization from arch/arm/ tree
From: Cho KyongHo @ 2012-11-14 8:51 UTC (permalink / raw)
To: linux-arm-kernel
This removes System MMU initialization from arch/arm/mach-exynos/
to move them to DT and the exynos-iommu driver except gating clock
definitions.
Signed-off-by: KyongHo Cho <pullip.cho@samsung.com>
---
arch/arm/mach-exynos/Kconfig | 5 -
arch/arm/mach-exynos/Makefile | 1 -
arch/arm/mach-exynos/clock-exynos4.c | 41 +++--
arch/arm/mach-exynos/clock-exynos4210.c | 9 +-
arch/arm/mach-exynos/clock-exynos4212.c | 23 ++-
arch/arm/mach-exynos/clock-exynos5.c | 62 ++++---
arch/arm/mach-exynos/dev-sysmmu.c | 274 -----------------------------
arch/arm/mach-exynos/include/mach/sysmmu.h | 66 -------
arch/arm/mach-exynos/mach-exynos4-dt.c | 34 ++++
arch/arm/mach-exynos/mach-exynos5-dt.c | 30 ++++
10 files changed, 137 insertions(+), 408 deletions(-)
delete mode 100644 arch/arm/mach-exynos/dev-sysmmu.c
delete mode 100644 arch/arm/mach-exynos/include/mach/sysmmu.h
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index bb3b09a..d5157d7 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -94,11 +94,6 @@ config EXYNOS4_SETUP_FIMD0
help
Common setup code for FIMD0.
-config EXYNOS_DEV_SYSMMU
- bool
- help
- Common setup code for SYSTEM MMU in EXYNOS platforms
-
config EXYNOS4_DEV_DWMCI
bool
help
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 1797dee..7460ba2 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -53,7 +53,6 @@ obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
-obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index efead60..c81a0ca 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -24,7 +24,6 @@
#include <mach/map.h>
#include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
#include "common.h"
#include "clock-exynos4.h"
@@ -709,53 +708,53 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 14),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.0",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.1",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.2",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 4),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.3",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 11),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.4",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 4),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.5",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 7),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.6",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 8),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.7",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 9),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.8",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 10),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.10",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 4),
}
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index fed4c26..19af9f7 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -26,7 +26,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
#include "common.h"
#include "clock-exynos4.h"
@@ -129,13 +128,13 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.9",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 3),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.11",
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4),
}, {
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 8fba0b5..529476f 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -26,7 +26,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
#include "common.h"
#include "clock-exynos4.h"
@@ -111,21 +110,31 @@ static struct clksrc_clk clksrcs[] = {
static struct clk init_clocks_off[] = {
{
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.9",
.enable = exynos4_clk_ip_dmc_ctrl,
.ctrlbit = (1 << 24),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.12",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (7 << 8),
}, {
- .name = SYSMMU_CLOCK_NAME2,
- .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.13",
.enable = exynos4212_clk_ip_isp1_ctrl,
.ctrlbit = (1 << 4),
}, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.14",
+ .enable = exynos4212_clk_ip_isp0_ctrl,
+ .ctrlbit = (1 << 11),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.15",
+ .enable = exynos4212_clk_ip_isp0_ctrl,
+ .ctrlbit = (1 << 12),
+ }, {
.name = "flite",
.devname = "exynos-fimc-lite.0",
.enable = exynos4212_clk_ip_isp0_ctrl,
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index e48d7c2..9e815ae 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -24,7 +24,6 @@
#include <mach/map.h>
#include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
#include "common.h"
@@ -852,73 +851,78 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 3),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.0",
.enable = &exynos5_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.1",
.enable = &exynos5_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.2",
.enable = &exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 9)
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.3",
.enable = &exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 7),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.4",
.enable = &exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 6)
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.5",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 7),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.6",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 8),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.7",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 9),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.8",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 10),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.9",
.enable = &exynos5_clk_ip_isp0_ctrl,
.ctrlbit = (0x3F << 8),
}, {
- .name = SYSMMU_CLOCK_NAME2,
- .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.10",
.enable = &exynos5_clk_ip_isp1_ctrl,
.ctrlbit = (0xF << 4),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(camif0, 12),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.11",
+ .enable = &exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 8)
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.12",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 11),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(camif1, 13),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.13",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 12),
}, {
- .name = SYSMMU_CLOCK_NAME,
- .devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.14",
.enable = &exynos5_clk_ip_acp_ctrl,
.ctrlbit = (1 << 7)
}
diff --git a/arch/arm/mach-exynos/dev-sysmmu.c b/arch/arm/mach-exynos/dev-sysmmu.c
deleted file mode 100644
index c5b1ea3..0000000
--- a/arch/arm/mach-exynos/dev-sysmmu.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* linux/arch/arm/mach-exynos/dev-sysmmu.c
- *
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS - System MMU support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-
-#include <plat/cpu.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/sysmmu.h>
-
-static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
-
-#define SYSMMU_PLATFORM_DEVICE(ipname, devid) \
-static struct sysmmu_platform_data platdata_##ipname = { \
- .dbgname = #ipname, \
-}; \
-struct platform_device SYSMMU_PLATDEV(ipname) = \
-{ \
- .name = SYSMMU_DEVNAME_BASE, \
- .id = devid, \
- .dev = { \
- .dma_mask = &exynos_sysmmu_dma_mask, \
- .coherent_dma_mask = DMA_BIT_MASK(32), \
- .platform_data = &platdata_##ipname, \
- }, \
-}
-
-SYSMMU_PLATFORM_DEVICE(mfc_l, 0);
-SYSMMU_PLATFORM_DEVICE(mfc_r, 1);
-SYSMMU_PLATFORM_DEVICE(tv, 2);
-SYSMMU_PLATFORM_DEVICE(jpeg, 3);
-SYSMMU_PLATFORM_DEVICE(rot, 4);
-SYSMMU_PLATFORM_DEVICE(fimc0, 5); /* fimc* and gsc* exist exclusively */
-SYSMMU_PLATFORM_DEVICE(fimc1, 6);
-SYSMMU_PLATFORM_DEVICE(fimc2, 7);
-SYSMMU_PLATFORM_DEVICE(fimc3, 8);
-SYSMMU_PLATFORM_DEVICE(gsc0, 5);
-SYSMMU_PLATFORM_DEVICE(gsc1, 6);
-SYSMMU_PLATFORM_DEVICE(gsc2, 7);
-SYSMMU_PLATFORM_DEVICE(gsc3, 8);
-SYSMMU_PLATFORM_DEVICE(isp, 9);
-SYSMMU_PLATFORM_DEVICE(fimd0, 10);
-SYSMMU_PLATFORM_DEVICE(fimd1, 11);
-SYSMMU_PLATFORM_DEVICE(camif0, 12);
-SYSMMU_PLATFORM_DEVICE(camif1, 13);
-SYSMMU_PLATFORM_DEVICE(2d, 14);
-
-#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
-
-#define SYSMMU_RESOURCE(core, ipname) \
- static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
-
-#define DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
- DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem), \
- DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
-
-#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq) \
- SYSMMU_RESOURCE(core, ipname) { \
- DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
- }
-
-struct sysmmu_resource_map {
- struct platform_device *pdev;
- struct resource *res;
- u32 rnum;
- struct device *pdd;
- char *clocknames;
-};
-
-#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) { \
- .pdev = &SYSMMU_PLATDEV(ipname), \
- .res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
- .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
- .clocknames = SYSMMU_CLOCK_NAME, \
-}
-
-#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) { \
- .pdev = &SYSMMU_PLATDEV(ipname), \
- .res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
- .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
- .clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
-}
-
-#ifdef CONFIG_EXYNOS_DEV_PD
-#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) { \
- .pdev = &SYSMMU_PLATDEV(ipname), \
- .res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
- .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
- .clocknames = SYSMMU_CLOCK_NAME, \
- .pdd = &exynos##core##_device_pd[pd].dev, \
-}
-
-#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
- .pdev = &SYSMMU_PLATDEV(ipname), \
- .res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
- .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
- .clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
- .pdd = &exynos##core##_device_pd[pd].dev, \
-}
-#else
-#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) \
- SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
-#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) \
- SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
-
-#endif /* CONFIG_EXYNOS_DEV_PD */
-
-#ifdef CONFIG_ARCH_EXYNOS4
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0, FIMC0, FIMC0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1, FIMC1, FIMC1);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2, FIMC2, FIMC2);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3, FIMC3, FIMC3);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg, JPEG, JPEG);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d, G2D, 2D);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv, TV, TV_M0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp, 2D_ACP, 2D);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot, ROTATOR, ROTATOR);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0, FIMD0, LCD0_M0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1, FIMD1, LCD1_M1);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0, FIMC_LITE0, FIMC_LITE0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1, FIMC_LITE1, FIMC_LITE1);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_r, MFC_R, MFC_M0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_l, MFC_L, MFC_M1);
-SYSMMU_RESOURCE(EXYNOS4, isp) {
- DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_ISP, FIMC_ISP),
- DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_DRC, FIMC_DRC),
- DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_FD, FIMC_FD),
- DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
-};
-
-static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
- SYSMMU_RESOURCE_MAPPING_PD(4, fimc0, fimc0, PD_CAM),
- SYSMMU_RESOURCE_MAPPING_PD(4, fimc1, fimc1, PD_CAM),
- SYSMMU_RESOURCE_MAPPING_PD(4, fimc2, fimc2, PD_CAM),
- SYSMMU_RESOURCE_MAPPING_PD(4, fimc3, fimc3, PD_CAM),
- SYSMMU_RESOURCE_MAPPING_PD(4, tv, tv, PD_TV),
- SYSMMU_RESOURCE_MAPPING_PD(4, mfc_r, mfc_r, PD_MFC),
- SYSMMU_RESOURCE_MAPPING_PD(4, mfc_l, mfc_l, PD_MFC),
- SYSMMU_RESOURCE_MAPPING_PD(4, rot, rot, PD_LCD0),
- SYSMMU_RESOURCE_MAPPING_PD(4, jpeg, jpeg, PD_CAM),
- SYSMMU_RESOURCE_MAPPING_PD(4, fimd0, fimd0, PD_LCD0),
-};
-
-static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
- SYSMMU_RESOURCE_MAPPING_PD(4, 2d, 2d, PD_LCD0),
- SYSMMU_RESOURCE_MAPPING_PD(4, fimd1, fimd1, PD_LCD1),
-};
-
-static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
- SYSMMU_RESOURCE_MAPPING(4, 2d, 2d_acp),
- SYSMMU_RESOURCE_MAPPING_PD(4, camif0, flite0, PD_ISP),
- SYSMMU_RESOURCE_MAPPING_PD(4, camif1, flite1, PD_ISP),
- SYSMMU_RESOURCE_MAPPING_PD(4, isp, isp, PD_ISP),
-};
-#endif /* CONFIG_ARCH_EXYNOS4 */
-
-#ifdef CONFIG_ARCH_EXYNOS5
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg, JPEG, JPEG);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1, FIMD1, FIMD1);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d, 2D, 2D);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot, ROTATOR, ROTATOR);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv, TV, TV);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0, LITE0, LITE0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1, LITE1, LITE1);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0, GSC0, GSC0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1, GSC1, GSC1);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2, GSC2, GSC2);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3, GSC3, GSC3);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_r, MFC_R, MFC_R);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_l, MFC_L, MFC_L);
-SYSMMU_RESOURCE(EXYNOS5, isp) {
- DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
- DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
- DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
- DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
- DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
- DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
- DEFINE_SYSMMU_RESOURCE(EXYNOS5, ODC, ODC),
- DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
- DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
- DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
-};
-
-static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
- SYSMMU_RESOURCE_MAPPING(5, jpeg, jpeg),
- SYSMMU_RESOURCE_MAPPING(5, fimd1, fimd1),
- SYSMMU_RESOURCE_MAPPING(5, 2d, 2d),
- SYSMMU_RESOURCE_MAPPING(5, rot, rot),
- SYSMMU_RESOURCE_MAPPING_PD(5, tv, tv, PD_DISP1),
- SYSMMU_RESOURCE_MAPPING_PD(5, camif0, flite0, PD_GSCL),
- SYSMMU_RESOURCE_MAPPING_PD(5, camif1, flite1, PD_GSCL),
- SYSMMU_RESOURCE_MAPPING_PD(5, gsc0, gsc0, PD_GSCL),
- SYSMMU_RESOURCE_MAPPING_PD(5, gsc1, gsc1, PD_GSCL),
- SYSMMU_RESOURCE_MAPPING_PD(5, gsc2, gsc2, PD_GSCL),
- SYSMMU_RESOURCE_MAPPING_PD(5, gsc3, gsc3, PD_GSCL),
- SYSMMU_RESOURCE_MAPPING_PD(5, mfc_r, mfc_r, PD_MFC),
- SYSMMU_RESOURCE_MAPPING_PD(5, mfc_l, mfc_l, PD_MFC),
- SYSMMU_RESOURCE_MAPPING_MCPD(5, isp, isp, PD_ISP, mc_platdata),
-};
-#endif /* CONFIG_ARCH_EXYNOS5 */
-
-static int __init init_sysmmu_platform_device(void)
-{
- int i, j;
- struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
- int nmap[2] = {0, 0};
-
-#ifdef CONFIG_ARCH_EXYNOS5
- if (soc_is_exynos5250()) {
- resmap[0] = sysmmu_resmap5;
- nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
- nmap[1] = 0;
- }
-#endif
-
-#ifdef CONFIG_ARCH_EXYNOS4
- if (resmap[0] == NULL) {
- resmap[0] = sysmmu_resmap4;
- nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
- }
-
- if (soc_is_exynos4210()) {
- resmap[1] = sysmmu_resmap4210;
- nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
- }
-
- if (soc_is_exynos4412() || soc_is_exynos4212()) {
- resmap[1] = sysmmu_resmap4212;
- nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
- }
-#endif
-
- for (j = 0; j < 2; j++) {
- for (i = 0; i < nmap[j]; i++) {
- struct sysmmu_resource_map *map;
- struct sysmmu_platform_data *platdata;
-
- map = &resmap[j][i];
-
- map->pdev->dev.parent = map->pdd;
-
- platdata = map->pdev->dev.platform_data;
- platdata->clockname = map->clocknames;
-
- if (platform_device_add_resources(map->pdev, map->res,
- map->rnum)) {
- pr_err("%s: Failed to add device resources for "
- "%s.%d\n", __func__,
- map->pdev->name, map->pdev->id);
- continue;
- }
-
- if (platform_device_register(map->pdev)) {
- pr_err("%s: Failed to register %s.%d\n",
- __func__, map->pdev->name,
- map->pdev->id);
- }
- }
- }
-
- return 0;
-}
-arch_initcall(init_sysmmu_platform_device);
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
deleted file mode 100644
index 88a4543..0000000
--- a/arch/arm/mach-exynos/include/mach/sysmmu.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS - System MMU support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
-#define _ARM_MACH_EXYNOS_SYSMMU_H_
-
-struct sysmmu_platform_data {
- char *dbgname;
- /* comma(,) separated list of clock names for clock gating */
- char *clockname;
-};
-
-#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
-
-#define SYSMMU_CLOCK_NAME "sysmmu"
-#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
-
-#ifdef CONFIG_EXYNOS_DEV_SYSMMU
-#include <linux/device.h>
-struct platform_device;
-
-#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
-
-extern struct platform_device SYSMMU_PLATDEV(mfc_l);
-extern struct platform_device SYSMMU_PLATDEV(mfc_r);
-extern struct platform_device SYSMMU_PLATDEV(tv);
-extern struct platform_device SYSMMU_PLATDEV(jpeg);
-extern struct platform_device SYSMMU_PLATDEV(rot);
-extern struct platform_device SYSMMU_PLATDEV(fimc0);
-extern struct platform_device SYSMMU_PLATDEV(fimc1);
-extern struct platform_device SYSMMU_PLATDEV(fimc2);
-extern struct platform_device SYSMMU_PLATDEV(fimc3);
-extern struct platform_device SYSMMU_PLATDEV(gsc0);
-extern struct platform_device SYSMMU_PLATDEV(gsc1);
-extern struct platform_device SYSMMU_PLATDEV(gsc2);
-extern struct platform_device SYSMMU_PLATDEV(gsc3);
-extern struct platform_device SYSMMU_PLATDEV(isp);
-extern struct platform_device SYSMMU_PLATDEV(fimd0);
-extern struct platform_device SYSMMU_PLATDEV(fimd1);
-extern struct platform_device SYSMMU_PLATDEV(camif0);
-extern struct platform_device SYSMMU_PLATDEV(camif1);
-extern struct platform_device SYSMMU_PLATDEV(2d);
-
-#ifdef CONFIG_IOMMU_API
-static inline void platform_set_sysmmu(
- struct device *sysmmu, struct device *dev)
-{
- dev->archdata.iommu = sysmmu;
-}
-#endif
-
-#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
-#define platform_set_sysmmu(sysmmu, dev) do { } while (0)
-#endif
-
-#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
-
-#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 8858068..14e5f84 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -79,6 +79,40 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
"exynos-tmu", NULL),
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
+ "exynos-sysmmu.0", NULL), /* MFC_L */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
+ "exynos-sysmmu.1", NULL), /* MFC_R */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
+ "exynos-sysmmu.2", NULL), /* TV */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
+ "exynos-sysmmu.3", NULL), /* JPEG */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
+ "exynos-sysmmu.4", NULL), /* ROTATOR */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
+ "exynos-sysmmu.5", NULL), /* FIMC0 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
+ "exynos-sysmmu.6", NULL), /* FIMC1 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
+ "exynos-sysmmu.7", NULL), /* FIMC2 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
+ "exynos-sysmmu.8", NULL), /* FIMC3 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
+ "exynos-sysmmu.9", NULL), /* G2D(4210) */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
+ "exynos-sysmmu.9", NULL), /* G2D(4x12) */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
+ "exynos-sysmmu.10", NULL), /* FIMD0 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
+ "exynos-sysmmu.11", NULL), /* FIMD1(4210) */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
+ "exynos-sysmmu.12", NULL), /* IS0(4x12) */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
+ "exynos-sysmmu.13", NULL), /* IS1(4x12) */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
+ "exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
+ "exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
{},
};
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ed37273..98c6b25 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -86,6 +86,36 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
"exynos5-hdmi", NULL),
OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
"exynos5-mixer", NULL),
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
+ "exynos-sysmmu.0", "mfc"), /* MFC_L */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
+ "exynos-sysmmu.1", "mfc"), /* MFC_R */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
+ "exynos-sysmmu.2", NULL), /* TV */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
+ "exynos-sysmmu.3", "jpeg"), /* JPEG */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
+ "exynos-sysmmu.4", NULL), /* ROTATOR */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
+ "exynos-sysmmu.5", "gscl"), /* GSCL0 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
+ "exynos-sysmmu.6", "gscl"), /* GSCL1 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
+ "exynos-sysmmu.7", "gscl"), /* GSCL2 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
+ "exynos-sysmmu.8", "gscl"), /* GSCL3 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
+ "exynos-sysmmu.9", NULL), /* FIMC-IS0 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
+ "exynos-sysmmu.10", NULL), /* FIMC-IS1 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
+ "exynos-sysmmu.11", NULL), /* FIMD1 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
+ "exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
+ "exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
+ "exynos-sysmmu.14", NULL), /* G2D */
{},
};
--
1.8.0
^ permalink raw reply related
* [PATCH 2/4] ARM: EXYNOS: Add clk_ops for gating clocks of System MMU
From: Cho KyongHo @ 2012-11-14 8:51 UTC (permalink / raw)
To: linux-arm-kernel
Touching some System MMU needs its master devices' clock to be enabled
before. This commit adds clk_ops.set_parent of gating clocks of System
MMU to ensure gating clocks of System MMU's mater devices are enabled
when enabling gating clocks of System MMU.
Signed-off-by: KyongHo Cho <pullip.cho@samsung.com>
---
arch/arm/mach-exynos/clock-exynos5.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 9e815ae..9dfb845 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -613,6 +613,16 @@ static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
};
+static int exynos5_gate_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ clk->parent = parent;
+ return 0;
+}
+
+static struct clk_ops exynos5_gate_clk_ops = {
+ .set_parent = exynos5_gate_clk_set_parent
+};
+
static struct clk exynos5_init_clocks_off[] = {
{
.name = "timers",
@@ -854,76 +864,91 @@ static struct clk exynos5_init_clocks_off[] = {
.name = "sysmmu",
.devname = "exynos-sysmmu.0",
.enable = &exynos5_clk_ip_mfc_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 1),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.1",
.enable = &exynos5_clk_ip_mfc_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 2),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.2",
.enable = &exynos5_clk_ip_disp1_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 9)
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.3",
.enable = &exynos5_clk_ip_gen_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 7),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.4",
.enable = &exynos5_clk_ip_gen_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 6)
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.5",
.enable = &exynos5_clk_ip_gscl_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 7),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.6",
.enable = &exynos5_clk_ip_gscl_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 8),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.7",
.enable = &exynos5_clk_ip_gscl_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 9),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.8",
.enable = &exynos5_clk_ip_gscl_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 10),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.9",
.enable = &exynos5_clk_ip_isp0_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (0x3F << 8),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.10",
.enable = &exynos5_clk_ip_isp1_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (0xF << 4),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.11",
.enable = &exynos5_clk_ip_disp1_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 8)
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.12",
.enable = &exynos5_clk_ip_gscl_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 11),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.13",
.enable = &exynos5_clk_ip_gscl_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 12),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.14",
.enable = &exynos5_clk_ip_acp_ctrl,
+ .ops = &exynos5_gate_clk_ops,
.ctrlbit = (1 << 7)
}
};
--
1.8.0
^ permalink raw reply related
* [PATCH 3/4] ARM: EXYNOS: add System MMU definition to DT
From: Cho KyongHo @ 2012-11-14 8:51 UTC (permalink / raw)
To: linux-arm-kernel
This commit adds System MMU nodes to DT of Exynos SoCs.
Signed-off-by: KyongHo Cho <pullip.cho@samsung.com>
---
.../devicetree/bindings/arm/samsung/system-mmu.txt | 42 ++++++
arch/arm/boot/dts/exynos4210.dtsi | 96 ++++++++++++++
arch/arm/boot/dts/exynos4x12.dtsi | 124 +++++++++++++++++
arch/arm/boot/dts/exynos5250.dtsi | 147 ++++++++++++++++++++-
4 files changed, 407 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/samsung/system-mmu.txt
diff --git a/Documentation/devicetree/bindings/arm/samsung/system-mmu.txt
b/Documentation/devicetree/bindings/arm/samsung/system-mmu.txt
new file mode 100644
index 0000000..5115c39
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/system-mmu.txt
@@ -0,0 +1,42 @@
+* Samsung Exynos System MMU
+
+Samsung's Exynos architecture includes System MMU that enables scattered
+physical chunks to be visible as a contiguous region to DMA-capabile peripheral
+devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
+
+System MMU is a sort of IOMMU and support identical translation table format to
+ARMv7 translation tables with minimum set of page properties including access
+permissions, shareability and security protection. In addition System MMU has
+another capabilities like L2 TLB or block-fetch buffers to minimize translation
+latency
+
+Each System MMU is included in the H/W block of a peripheral device. Thus, it is
+important to specify that a System MMU is dedicated to which peripheral device
+before using System MMU. System initialization must specify the relationships
+between a System MMU and a peripheral device that owns the System MMU.
+
+Some device drivers may control several peripheral devices with a single device
+descriptor like MFC. Since handling a System MMU with IOMMU API requires a
+device descriptor that needs the System MMU, it is best to combine the System
+MMUs of the peripheral devices and control them with a single System MMU device
+descriptor. If it is unable to combine them into a single device descriptor,
+they can be linked with each other by the means of device.parent relationship.
+
+Required properties:
+- compatible: Should be "samsung,exynos-sysmmu".
+- reg: Tuples of base address and size of System MMU registers. The number of
+ tuples can be more than one if two or more System MMUs are controlled
+ by a single device descriptor.
+- interrupt-parent: The phandle of the interrupt controller of System MMU
+- interrupts: Tuples of numbers that indicates the interrupt source. The
+ number of elements in the tuple is dependent upon
+ 'interrupt-parent' property. The number of tuples in this property
+ must be the same with 'reg' property.
+
+Optional properties:
+- mmuname: Strings of the name of System MMU for debugging purpose. The number
+ of strings must be the same with the number of tuples in 'reg'
+ property.
+- mmu-master: phandle to the device node that owns System MMU. Only the device
+ that is specified whith this property can control System MMU with
+ IOMMU API.
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 939f639..d7a7a06 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -71,4 +71,100 @@
reg = <0x100C0000 0x100>;
interrupts = <2 4>;
};
+
+ sysmmu-mfcL {
+ mmuname = "mfc_l";
+ reg = <0x13620000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 5>;
+ };
+
+ sysmmu-mfcR {
+ mmuname = "mfc_r";
+ reg = <0x13630000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 6>;
+ };
+
+ sysmmu-tv {
+ mmuname = "tv";
+ reg = <0x13E20000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 4>;
+ };
+
+ sysmmu-fimc0 {
+ mmuname = "fimc0";
+ reg = <0x11A20000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 2>;
+ };
+
+ sysmmu-fimc1 {
+ mmuname = "fimc1";
+ reg = <0x11A30000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 3>;
+ };
+
+ sysmmu-fimc2 {
+ mmuname = "fimc2";
+ reg = <0x11A40000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 4>;
+ };
+
+ sysmmu-fimc3 {
+ mmuname = "fimc3";
+ reg = <0x11A50000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 5>;
+ };
+
+ sysmmu-jpeg {
+ mmuname = "jpeg";
+ reg = <0x11A60000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 6>;
+ };
+
+ sysmmu-g2d {
+ mmuname = "g2d";
+ reg = <0x12A20000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 7>;
+ };
+
+ sysmmu-rotator {
+ mmuname = "rotator";
+ reg = <0x12A30000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 0>;
+ };
+
+ sysmmu-fimd0 {
+ mmuname = "fimd0";
+ reg = <0x11E20000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 2>;
+ };
+
+ sysmmu-fimd1 {
+ mmuname = "fimd1";
+ reg = <0x12220000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 3>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 179a62e..0490836 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -66,4 +66,128 @@
reg = <0x106E0000 0x1000>;
interrupts = <0 72 0>;
};
+
+ sysmmu-mfcL {
+ mmuname = "mfc_l";
+ reg = <0x13620000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 5>;
+ };
+
+ sysmmu-mfcR {
+ mmuname = "mfc_r";
+ reg = <0x13630000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 6>;
+ };
+
+ sysmmu-tv {
+ mmuname = "tv";
+ reg = <0x13E20000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 4>;
+ };
+
+ sysmmu-fimc0 {
+ mmuname = "fimc0";
+ reg = <0x11A20000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 2>;
+ };
+
+ sysmmu-fimc1 {
+ mmuname = "fimc1";
+ reg = <0x11A30000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 3>;
+ };
+
+ sysmmu-fimc2 {
+ mmuname = "fimc2";
+ reg = <0x11A40000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 4>;
+ };
+
+ sysmmu-fimc3 {
+ mmuname = "fimc3";
+ reg = <0x11A50000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 5>;
+ };
+
+ sysmmu-jpeg {
+ mmuname = "jpeg";
+ reg = <0x11A60000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 6>;
+ };
+
+ sysmmu-g2d {
+ mmuname = "g2d";
+ reg = <0x10A40000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 7>;
+ };
+
+ sysmmu-rotator {
+ mmuname = "rotator";
+ reg = <0x12A30000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 0>;
+ };
+
+ sysmmu-fimd0 {
+ mmuname = "fimd0";
+ reg = <0x11E20000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <5 2>;
+ };
+
+ sysmmu-is0 {
+ mmuname = "isp", "drc", "fd";
+ reg = <0x12260000 0x1000
+ 0x12270000 0x1000
+ 0x122A0000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <16 2
+ 16 3
+ 16 4>;
+ };
+
+ sysmmu-is1 {
+ mmuname = "ispcpu";
+ reg = <0x122B0000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <16 5>;
+ };
+
+ sysmmu-flite0 {
+ mmuname = "fimc-lite0";
+ reg = <0x123B0000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <16 0>;
+ };
+
+ sysmmu-flite1 {
+ mmuname = "fimc-lite1";
+ reg = <0x123C0000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <16 1>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index cf6a02d..7d1eaa3 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -62,7 +62,7 @@
interrupts = <0 42 0>;
};
- codec at 11000000 {
+ mfc: codec at 11000000 {
compatible = "samsung,mfc-v6";
reg = <0x11000000 0x10000>;
interrupts = <0 96 0>;
@@ -547,9 +547,152 @@
interrupts = <0 95 0>;
};
- mixer {
+ mixer: mixer {
compatible = "samsung,exynos5-mixer";
reg = <0x14450000 0x10000>;
interrupts = <0 94 0>;
};
+
+ sysmmu-mfcL {
+ mmuname = "mfc_l";
+ reg = <0x11210000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <8 5>;
+ mmu-master = <&mfc>;
+ };
+
+ sysmmu-mfcR {
+ mmuname = "mfc_r";
+ reg = <0x11200000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <6 2>;
+ mmu-master = <&mfc>;
+ };
+
+ sysmmu-tv {
+ mmuname = "tv";
+ reg = <0x14650000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <7 4>;
+ mmu-master = <&mixer>;
+ };
+
+ sysmmu-gsc0 {
+ mmuname = "gsc0";
+ reg = <0x13E80000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <2 0>;
+ mmu-master = <&gsc_0>;
+ };
+
+ sysmmu-gsc1 {
+ mmuname = "gsc1";
+ reg = <0x13E90000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <2 2>;
+ mmu-master = <&gsc_1>;
+ };
+
+ sysmmu-gsc2 {
+ mmuname = "gsc2";
+ reg = <0x13EA0000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <2 4>;
+ mmu-master = <&gsc_2>;
+ };
+
+ sysmmu-gsc3 {
+ mmuname = "gsc3";
+ reg = <0x13EB0000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <2 6>;
+ mmu-master = <&gsc_3>;
+ };
+
+ sysmmu-fimd1 {
+ mmuname = "fimd1";
+ reg = <0x14640000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <3 2>;
+ };
+
+ sysmmu-rotator {
+ mmuname = "rotator";
+ reg = <0x11D40000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 0>;
+ };
+
+ sysmmu-is0 {
+ mmuname = "isp", "drc", "scalerc", "scalerp", "fd", "mcu";
+ reg = < 0x13260000 0x1000
+ 0x13270000 0x1000
+ 0x13280000 0x1000
+ 0x13290000 0x1000
+ 0x132A0000 0x1000
+ 0x132B0000 0x1000 >;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <10 6
+ 11 6
+ 5 2
+ 3 6
+ 5 0
+ 5 4>;
+ };
+
+ sysmmu-is1 {
+ mmuname = "odc", "dis0", "dis1", "3dnr";
+ reg = < 0x132C0000 0x1000
+ 0x132D0000 0x1000
+ 0x132E0000 0x1000
+ 0x132F0000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <11 0
+ 10 4
+ 9 4
+ 5 6>;
+ };
+
+ sysmmu-2d {
+ mmuname = "2d";
+ reg = <0x10A60000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <24 5>;
+ };
+
+ sysmmu-jpeg {
+ mmuname = "jpeg";
+ reg = <0x11F20000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <4 2>;
+ };
+
+ sysmmu-flite0 {
+ mmuname = "flite0";
+ reg = <0x13C40000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <3 4>;
+ };
+
+ sysmmu-flite1 {
+ mmuname = "flite1";
+ reg = <0x13C50000 0x1000>;
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <24 1>;
+ };
};
--
1.8.0
^ permalink raw reply related
* [PATCH 4/4] iommu/exynos: enhancements of System MMU driver with DT
From: Cho KyongHo @ 2012-11-14 8:51 UTC (permalink / raw)
To: linux-arm-kernel
This commit enhances power management of System MMU and its client
devices with the following changes:
- Each System MMU device becomes the parent device of its client
device while probe(). Thus, exynos-iommu driver must be initialized
before client devices.
- System MMU driver does not pm_runtime_get/put() by itself and runtime
power gating is performed by client devices.
- System is safe when suspend/resume without any care by client device
drivers.
In addition, System MMUs can be seperate into several groups that are
belongs to a single client device like FIMC-IS block. If such blocks are
controlled by a single device descriptor, all System MMUs in the blocks
must be enabled/disabled by a single device descriptor. The problem is
that clock gating and power gating may be not the same among all System
MMUs in the blocks. Thus, System MMUs are grouped by clock gating and
power gating and they are chained by parent-child relationships.
exynos-iommu driver now also supports debugfs to identify the state of
each System MMU.
The last big change is to support DT. The desription of the properties
of DT nodes are described in the source file.
Signed-off-by: KyongHo Cho <pullip.cho@samsung.com>
---
drivers/iommu/Kconfig | 17 +-
drivers/iommu/exynos-iommu.c | 1420 +++++++++++++++++++++++++++++++-----------
2 files changed, 1077 insertions(+), 360 deletions(-)
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index e39f9db..548fdf0 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -168,7 +168,7 @@ config TEGRA_IOMMU_SMMU
config EXYNOS_IOMMU
bool "Exynos IOMMU Support"
- depends on ARCH_EXYNOS && EXYNOS_DEV_SYSMMU
+ depends on ARCH_EXYNOS
select IOMMU_API
help
Support for the IOMMU(System MMU) of Samsung Exynos application
@@ -178,6 +178,21 @@ config EXYNOS_IOMMU
If unsure, say N here.
+config EXYNOS_IOMMU_TLBINV_BY_ENTRY
+ bool "TLB invalidation in iommu_unmap() call"
+ depends on EXYNOS_IOMMU
+ default y
+ help
+ TLB must be invalidated whenever a mapping information is removed from
+ the page table and iommu_ops.unmap() is the proper place to invoke
+ TLB invalidation. Since iommu_ops.unmap() is called per a page
+ table entry, TLB invalidation can be invoked hundreds of times for
+ unmapping just one IO region that consists of hundreds of pages.
+ It is rather efficient not to invalidate TLB by entry but invalidate
+ the entire TLB.
+ Say n if your IO region mapper calls exynos_sysmmu_tlb_invalidate()
+ directly not to perform TLB invalidation by entry.
+
config EXYNOS_IOMMU_DEBUG
bool "Debugging log for Exynos IOMMU"
depends on EXYNOS_IOMMU
diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index 7fe44f8..acf6486 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -1,6 +1,6 @@
/* linux/drivers/iommu/exynos_iommu.c
*
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
@@ -12,24 +12,29 @@
#define DEBUG
#endif
+#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/interrupt.h>
-#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/mm.h>
-#include <linux/iommu.h>
#include <linux/errno.h>
-#include <linux/list.h>
#include <linux/memblock.h>
#include <linux/export.h>
+#include <linux/fs.h>
+#include <linux/seq_file.h>
+#include <linux/debugfs.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/iommu.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
#include <asm/cacheflush.h>
-#include <asm/pgtable.h>
-#include <mach/sysmmu.h>
+#define MODULE_NAME "exynos-sysmmu"
/* We does not consider super section mapping (16MB) */
#define SECT_ORDER 20
@@ -80,6 +85,13 @@
#define CTRL_BLOCK 0x7
#define CTRL_DISABLE 0x0
+#define CFG_LRU 0x1
+#define CFG_QOS(n) ((n & 0xF) << 7)
+#define CFG_MASK 0x0050FFFF /* Selecting bit 0-15, 20, 22 */
+#define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */
+#define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */
+#define CFG_SHAREABLE (1 << 12) /* System MMU 3.x only */
+
#define REG_MMU_CTRL 0x000
#define REG_MMU_CFG 0x004
#define REG_MMU_STATUS 0x008
@@ -96,10 +108,31 @@
#define REG_MMU_VERSION 0x034
-#define REG_PB0_SADDR 0x04C
-#define REG_PB0_EADDR 0x050
-#define REG_PB1_SADDR 0x054
-#define REG_PB1_EADDR 0x058
+#define MMU_MAJ_VER(reg) (reg >> 28)
+#define MMU_MIN_VER(reg) ((reg >> 21) & 0x7F)
+
+#define MAX_NUM_PBUF 3
+
+#define NUM_MINOR_OF_SYSMMU_V3 4
+
+static void *sysmmu_placeholder; /* Inidcate if a device is System MMU */
+
+#define is_sysmmu(sysmmu) (sysmmu->archdata.iommu == &sysmmu_placeholder)
+#define has_sysmmu(dev) \
+ (dev->parent && dev->archdata.iommu && is_sysmmu(dev->parent))
+#define for_each_sysmmu(dev, sysmmu) \
+ for (sysmmu = dev->parent; sysmmu && is_sysmmu(sysmmu); \
+ sysmmu = sysmmu->parent)
+#define for_each_sysmmu_until(dev, sysmmu, until) \
+ for (sysmmu = dev->parent; sysmmu != until; sysmmu = sysmmu->parent)
+
+/* Offset of prefetch buffer setting registers are different
+ * between SysMMU 3.1 and 3.2
+ */
+static unsigned short
+ pbuf_offset[NUM_MINOR_OF_SYSMMU_V3] = {0x04C, 0x04C, 0x070, 0x000};
+
+static struct kmem_cache *lv2table_kmem_cache;
static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
{
@@ -124,16 +157,6 @@ enum exynos_sysmmu_inttype {
SYSMMU_FAULTS_NUM
};
-/*
- * @itype: type of fault.
- * @pgtable_base: the physical address of page table base. This is 0 if @itype
- * is SYSMMU_BUSERROR.
- * @fault_addr: the device (virtual) address that the System MMU tried to
- * translated. This is 0 if @itype is SYSMMU_BUSERROR.
- */
-typedef int (*sysmmu_fault_handler_t)(enum exynos_sysmmu_inttype itype,
- unsigned long pgtable_base, unsigned long fault_addr);
-
static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
REG_PAGE_FAULT_ADDR,
REG_AR_FAULT_ADDR,
@@ -157,27 +180,64 @@ static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
"UNKNOWN FAULT"
};
-struct exynos_iommu_domain {
- struct list_head clients; /* list of sysmmu_drvdata.node */
- unsigned long *pgtable; /* lv1 page table, 16KB */
- short *lv2entcnt; /* free lv2 entry counter for each section */
- spinlock_t lock; /* lock for this structure */
- spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
+/*
+ * @itype: type of fault.
+ * @pgtable_base: the physical address of page table base. This is 0 if @itype
+ * is SYSMMU_BUSERROR.
+ * @fault_addr: the device (virtual) address that the System MMU tried to
+ * translated. This is 0 if @itype is SYSMMU_BUSERROR.
+ */
+typedef int (*sysmmu_fault_handler_t)(struct device *dev,
+ const char *mmuname,
+ enum exynos_sysmmu_inttype itype,
+ unsigned long pgtable_base,
+ unsigned long fault_addr);
+/* exynos_iommu_owner
+ * Metadata attached to the owner of a group of System MMUs that belong
+ * to the same owner device.
+ */
+struct exynos_iommu_owner {
+ struct list_head client; /* entry of exynos_iommu_domain.clients */
+ struct device *dev;
+ spinlock_t lock; /* Lock to preserve consistency of System MMU */
+};
+
+struct sysmmu_version {
+ unsigned char major; /* major = 0 means that driver must use MMU_VERSION
+ register instead of this structure */
+ unsigned char minor;
+};
+
+struct sysmmu_prefbuf {
+ unsigned long base;
+ unsigned long size;
};
struct sysmmu_drvdata {
- struct list_head node; /* entry of exynos_iommu_domain.clients */
struct device *sysmmu; /* System MMU's device descriptor */
- struct device *dev; /* Owner of system MMU */
- char *dbgname;
+ struct device *master; /* Client device that needs System MMU */
int nsfrs;
- void __iomem **sfrbases;
- struct clk *clk[2];
+ struct clk *clk;
int activations;
- rwlock_t lock;
- struct iommu_domain *domain;
+ struct iommu_domain *domain; /* domain given to iommu_attach_device() */
sysmmu_fault_handler_t fault_handler;
unsigned long pgtable;
+ struct sysmmu_version ver; /* mach/sysmmu.h */
+ spinlock_t lock;
+ struct sysmmu_prefbuf pbufs[MAX_NUM_PBUF];
+ int num_pbufs;
+ struct dentry *debugfs_root;
+ bool runtime_active;
+ const char **mmuname;
+ void __iomem *sfrbases[0];
+};
+
+struct exynos_iommu_domain {
+ struct list_head clients; /* list of sysmmu_drvdata.node */
+ unsigned long *pgtable; /* lv1 page table, 16KB */
+ short *lv2entcnt; /* free lv2 entry counter for each section */
+ spinlock_t lock; /* lock for this structure */
+ spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
};
static bool set_sysmmu_active(struct sysmmu_drvdata *data)
@@ -199,6 +259,25 @@ static bool is_sysmmu_active(struct sysmmu_drvdata *data)
return data->activations > 0;
}
+static unsigned int __sysmmu_version(struct sysmmu_drvdata *drvdata,
+ int idx, unsigned int *minor)
+{
+ unsigned int major;
+
+ if (drvdata->ver.major == 0) {
+ major = readl(
+ drvdata->sfrbases[idx] + REG_MMU_VERSION);
+ if (minor)
+ *minor = MMU_MIN_VER(major);
+ major = MMU_MAJ_VER(major);
+ } else {
+ major = drvdata->ver.major;
+ if (minor)
+ *minor = drvdata->ver.minor;
+ }
+ return major;
+}
+
static void sysmmu_unblock(void __iomem *sfrbase)
{
__raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
@@ -225,12 +304,6 @@ static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
__raw_writel(0x1, sfrbase + REG_MMU_FLUSH);
}
-static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
- unsigned long iova)
-{
- __raw_writel((iova & SPAGE_MASK) | 1, sfrbase + REG_MMU_FLUSH_ENTRY);
-}
-
static void __sysmmu_set_ptbase(void __iomem *sfrbase,
unsigned long pgd)
{
@@ -240,85 +313,239 @@ static void __sysmmu_set_ptbase(void __iomem *sfrbase,
__sysmmu_tlb_invalidate(sfrbase);
}
-static void __sysmmu_set_prefbuf(void __iomem *sfrbase, unsigned long base,
- unsigned long size, int idx)
+static void __sysmmu_set_prefbuf(void __iomem *pbufbase, unsigned long base,
+ unsigned long size, int idx)
{
- __raw_writel(base, sfrbase + REG_PB0_SADDR + idx * 8);
- __raw_writel(size - 1 + base, sfrbase + REG_PB0_EADDR + idx * 8);
+ __raw_writel(base, pbufbase + idx * 8);
+ __raw_writel(size - 1 + base, pbufbase + 4 + idx * 8);
}
-void exynos_sysmmu_set_prefbuf(struct device *dev,
- unsigned long base0, unsigned long size0,
- unsigned long base1, unsigned long size1)
+static void __exynos_sysmmu_set_pbuf_ver31(struct sysmmu_drvdata *drvdata,
+ int idx, int nbufs, struct sysmmu_prefbuf prefbuf[])
{
- struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
- unsigned long flags;
- int i;
+ unsigned long cfg =
+ __raw_readl(drvdata->sfrbases[idx] + REG_MMU_CFG) & CFG_MASK;
+
+ if (nbufs > 1) {
+ unsigned long base = prefbuf[1].base;
+ unsigned long end = prefbuf[1].base + prefbuf[1].size;
+
+ /* merging buffers from the second to the last */
+ while (nbufs-- > 2) {
+ base = min(base, prefbuf[nbufs - 1].base);
+ end = max(end, prefbuf[nbufs - 1].base +
+ prefbuf[nbufs - 1].size);
+ }
- BUG_ON((base0 + size0) <= base0);
- BUG_ON((size1 > 0) && ((base1 + size1) <= base1));
+ /* Separate PB mode */
+ cfg |= 2 << 28;
- read_lock_irqsave(&data->lock, flags);
- if (!is_sysmmu_active(data))
- goto finish;
+ __sysmmu_set_prefbuf(drvdata->sfrbases[idx] + pbuf_offset[1],
+ base, end - base, 1);
- for (i = 0; i < data->nsfrs; i++) {
- if ((readl(data->sfrbases[i] + REG_MMU_VERSION) >> 28) == 3) {
- if (!sysmmu_block(data->sfrbases[i]))
- continue;
-
- if (size1 == 0) {
- if (size0 <= SZ_128K) {
- base1 = base0;
- size1 = size0;
- } else {
- size1 = size0 -
- ALIGN(size0 / 2, SZ_64K);
- size0 = size0 - size1;
- base1 = base0 + size0;
- }
+ drvdata->num_pbufs = 2;
+ drvdata->pbufs[0] = prefbuf[0];
+ drvdata->pbufs[1] = prefbuf[1];
+
+ } else {
+ /* Combined PB mode */
+ cfg |= 3 << 28;
+ drvdata->num_pbufs = 1;
+ drvdata->pbufs[0] = prefbuf[0];
+ }
+
+ __raw_writel(cfg, drvdata->sfrbases[idx] + REG_MMU_CFG);
+
+ __sysmmu_set_prefbuf(drvdata->sfrbases[idx] + pbuf_offset[1],
+ prefbuf[0].base, prefbuf[0].size, 0);
+}
+
+static void __exynos_sysmmu_set_pbuf_ver32(struct sysmmu_drvdata *drvdata,
+ int idx, int nbufs, struct sysmmu_prefbuf prefbuf[])
+{
+ unsigned long cfg =
+ __raw_readl(drvdata->sfrbases[idx] + REG_MMU_CFG) & CFG_MASK;
+
+ cfg |= 7 << 16; /* enabling PB0 ~ PB2 */
+
+ switch (nbufs) {
+ case 1:
+ {
+ /* Combined PB mode (0 ~ 2) */
+ cfg |= 1 << 19;
+ __sysmmu_set_prefbuf(drvdata->sfrbases[idx] + pbuf_offset[2],
+ prefbuf[0].base, prefbuf[0].size, 0);
+ drvdata->num_pbufs = 1;
+ drvdata->pbufs[0] = prefbuf[0];
+ break;
+ }
+ case 2:
+ {
+ /* Combined PB mode (0 ~ 1) */
+ cfg |= 1 << 21;
+ __sysmmu_set_prefbuf(drvdata->sfrbases[idx] + pbuf_offset[2],
+ prefbuf[0].base, prefbuf[0].size, 0);
+ __sysmmu_set_prefbuf(drvdata->sfrbases[idx] + pbuf_offset[2],
+ prefbuf[1].base, prefbuf[1].size, 2);
+ drvdata->num_pbufs = 2;
+ drvdata->pbufs[0] = prefbuf[0];
+ drvdata->pbufs[1] = prefbuf[1];
+ break;
+ }
+ case 3:
+ {
+ /* Finding largest buffer and set it to prefbuf 2 */
+ int i, j, k = 0;
+ for (j = 1; j < 3; j++)
+ if (prefbuf[j].size > prefbuf[0].size)
+ k = j;
+ /* Set to k-th buf to prefbuf 2 */
+ __sysmmu_set_prefbuf(drvdata->sfrbases[idx] + pbuf_offset[2],
+ prefbuf[k].base, prefbuf[k].size, 2);
+
+ /* Set other buffers to prefbuf 0 and 1 */
+ for (i = 0, j = 0; i < 3; i++) {
+ if (i != k) {
+ /*set i-th buffer to j-th prefbuf */
+ __sysmmu_set_prefbuf(
+ drvdata->sfrbases[idx] + pbuf_offset[2],
+ prefbuf[i].base, prefbuf[i].size,
+ j++);
}
+ }
+ drvdata->num_pbufs = 3;
+ drvdata->pbufs[0] = prefbuf[0];
+ drvdata->pbufs[1] = prefbuf[1];
+ drvdata->pbufs[2] = prefbuf[2];
+ break;
+ }
+ default:
+ {
+ unsigned long base = prefbuf[2].base;
+ unsigned long end = prefbuf[2].base + prefbuf[2].size;
+
+ /* Merging all buffers from the third to the last */
+ while (nbufs-- > 3) {
+ base = min(base, prefbuf[nbufs - 1].base);
+ end = max(end, prefbuf[nbufs - 1].base +
+ prefbuf[nbufs - 1].size);
+ }
+ __sysmmu_set_prefbuf(drvdata->sfrbases[idx] + pbuf_offset[2],
+ prefbuf[0].base, prefbuf[0].size, 0);
+ __sysmmu_set_prefbuf(drvdata->sfrbases[idx] + pbuf_offset[2],
+ prefbuf[1].base, prefbuf[1].size, 1);
+ __sysmmu_set_prefbuf(drvdata->sfrbases[idx] + pbuf_offset[2],
+ base, end - base, 2);
+ drvdata->num_pbufs = 3;
+ drvdata->pbufs[0] = prefbuf[0];
+ drvdata->pbufs[1] = prefbuf[1];
+ drvdata->pbufs[2] = prefbuf[2];
+ }
+ } /* switch (nbufs) */
+
+ __raw_writel(cfg, drvdata->sfrbases[idx] + REG_MMU_CFG);
+}
+
+static void __exynos_sysmmu_set_pbuf_ver33(struct sysmmu_drvdata *drvdata,
+ int idx, int nbufs, struct sysmmu_prefbuf prefbuf[])
+{
+ WARN(1, "System MMU ver. 3.3 is not available now\n");
+}
+
+static void (*func_set_pbuf[NUM_MINOR_OF_SYSMMU_V3])
+ (struct sysmmu_drvdata *, int, int, struct sysmmu_prefbuf []) = {
+ __exynos_sysmmu_set_pbuf_ver31,
+ __exynos_sysmmu_set_pbuf_ver31,
+ __exynos_sysmmu_set_pbuf_ver32,
+ __exynos_sysmmu_set_pbuf_ver33,
+};
+
+void exynos_sysmmu_set_pbuf(struct device *dev, int nbufs,
+ struct sysmmu_prefbuf prefbuf[])
+{
+ struct device *sysmmu;
+ int nsfrs;
+
+ if (WARN_ON(nbufs < 1))
+ return;
+
+ for_each_sysmmu(dev, sysmmu) {
+ unsigned long flags;
+ struct sysmmu_drvdata *drvdata;
- __sysmmu_set_prefbuf(
- data->sfrbases[i], base0, size0, 0);
- __sysmmu_set_prefbuf(
- data->sfrbases[i], base1, size1, 1);
+ drvdata = dev_get_drvdata(sysmmu);
- sysmmu_unblock(data->sfrbases[i]);
+ spin_lock_irqsave(&drvdata->lock, flags);
+ if (!is_sysmmu_active(drvdata)) {
+ spin_unlock_irqrestore(&drvdata->lock, flags);
+ continue;
+ }
+
+ for (nsfrs = 0; nsfrs < drvdata->nsfrs; nsfrs++) {
+ unsigned int maj, min;
+
+ maj = __sysmmu_version(drvdata, nsfrs, &min);
+
+ BUG_ON(min > 3);
+
+ if (sysmmu_block(drvdata->sfrbases[nsfrs])) {
+ func_set_pbuf[min](drvdata, nsfrs,
+ nbufs, prefbuf);
+ sysmmu_unblock(drvdata->sfrbases[nsfrs]);
+ }
+ } /* while (nsfrs < drvdata->nsfrs) */
+ spin_unlock_irqrestore(&drvdata->lock, flags);
+ }
+}
+
+static void __sysmmu_restore_state(struct sysmmu_drvdata *drvdata)
+{
+ int i, min;
+
+ for (i = 0; i < drvdata->nsfrs; i++) {
+ if (__sysmmu_version(drvdata, i, &min) == 3) {
+ if (sysmmu_block(drvdata->sfrbases[i])) {
+ func_set_pbuf[min](drvdata, i,
+ drvdata->num_pbufs, drvdata->pbufs);
+ sysmmu_unblock(drvdata->sfrbases[i]);
+ }
}
}
-finish:
- read_unlock_irqrestore(&data->lock, flags);
}
static void __set_fault_handler(struct sysmmu_drvdata *data,
sysmmu_fault_handler_t handler)
{
- unsigned long flags;
-
- write_lock_irqsave(&data->lock, flags);
data->fault_handler = handler;
- write_unlock_irqrestore(&data->lock, flags);
}
void exynos_sysmmu_set_fault_handler(struct device *dev,
sysmmu_fault_handler_t handler)
{
- struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+ struct exynos_iommu_owner *owner = dev->archdata.iommu;
+ struct device *sysmmu;
+ unsigned long flags;
+
+ spin_lock_irqsave(&owner->lock, flags);
- __set_fault_handler(data, handler);
+ for_each_sysmmu(dev, sysmmu)
+ __set_fault_handler(dev_get_drvdata(sysmmu), handler);
+
+ spin_unlock_irqrestore(&owner->lock, flags);
}
-static int default_fault_handler(enum exynos_sysmmu_inttype itype,
- unsigned long pgtable_base, unsigned long fault_addr)
+static int default_fault_handler(struct device *dev, const char *mmuname,
+ enum exynos_sysmmu_inttype itype,
+ unsigned long pgtable_base,
+ unsigned long fault_addr)
{
unsigned long *ent;
if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
itype = SYSMMU_FAULT_UNKNOWN;
- pr_err("%s occurred at 0x%lx(Page table base: 0x%lx)\n",
- sysmmu_fault_name[itype], fault_addr, pgtable_base);
+ pr_err("%s occured@0x%lx by '%s'(Page table base: 0x%lx)\n",
+ sysmmu_fault_name[itype], fault_addr, mmuname, pgtable_base);
ent = section_entry(__va(pgtable_base), fault_addr);
pr_err("\tLv1 entry: 0x%lx\n", *ent);
@@ -338,366 +565,642 @@ static int default_fault_handler(enum exynos_sysmmu_inttype itype,
static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
{
/* SYSMMU is in blocked when interrupt occurred. */
- struct sysmmu_drvdata *data = dev_id;
- struct resource *irqres;
- struct platform_device *pdev;
+ struct sysmmu_drvdata *drvdata = dev_id;
+ struct exynos_iommu_owner *owner = NULL;
enum exynos_sysmmu_inttype itype;
unsigned long addr = -1;
-
+ const char *mmuname = NULL;
int i, ret = -ENOSYS;
- read_lock(&data->lock);
+ if (drvdata->master)
+ owner = drvdata->master->archdata.iommu;
+
+ if (owner)
+ spin_lock(&owner->lock);
- WARN_ON(!is_sysmmu_active(data));
+ WARN_ON(!is_sysmmu_active(drvdata));
- pdev = to_platform_device(data->sysmmu);
- for (i = 0; i < (pdev->num_resources / 2); i++) {
- irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+ for (i = 0; i < drvdata->nsfrs; i++) {
+ struct resource *irqres;
+ irqres = platform_get_resource(
+ to_platform_device(drvdata->sysmmu),
+ IORESOURCE_IRQ, i);
if (irqres && ((int)irqres->start == irq))
break;
}
- if (i == pdev->num_resources) {
+ if (i == drvdata->nsfrs) {
itype = SYSMMU_FAULT_UNKNOWN;
} else {
itype = (enum exynos_sysmmu_inttype)
- __ffs(__raw_readl(data->sfrbases[i] + REG_INT_STATUS));
+ __ffs(__raw_readl(
+ drvdata->sfrbases[i] + REG_INT_STATUS));
if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
itype = SYSMMU_FAULT_UNKNOWN;
else
addr = __raw_readl(
- data->sfrbases[i] + fault_reg_offset[itype]);
+ drvdata->sfrbases[i] + fault_reg_offset[itype]);
}
- if (data->domain)
- ret = report_iommu_fault(data->domain, data->dev,
- addr, itype);
+ if (drvdata->domain) /* owner is always set if drvdata->domain exists */
+ ret = report_iommu_fault(drvdata->domain,
+ owner->dev, addr, itype);
+
+ if ((ret == -ENOSYS) && drvdata->fault_handler) {
+ unsigned long base = drvdata->pgtable;
+ mmuname = (drvdata->mmuname) ? drvdata->mmuname[i]
+ : dev_name(drvdata->sysmmu);
- if ((ret == -ENOSYS) && data->fault_handler) {
- unsigned long base = data->pgtable;
if (itype != SYSMMU_FAULT_UNKNOWN)
base = __raw_readl(
- data->sfrbases[i] + REG_PT_BASE_ADDR);
- ret = data->fault_handler(itype, base, addr);
+ drvdata->sfrbases[i] + REG_PT_BASE_ADDR);
+ ret = drvdata->fault_handler(
+ owner ? owner->dev : drvdata->sysmmu,
+ mmuname, itype, base, addr);
}
if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
- __raw_writel(1 << itype, data->sfrbases[i] + REG_INT_CLEAR);
+ __raw_writel(1 << itype, drvdata->sfrbases[i] + REG_INT_CLEAR);
else
- dev_dbg(data->sysmmu, "(%s) %s is not handled.\n",
- data->dbgname, sysmmu_fault_name[itype]);
+ dev_dbg(owner ? owner->dev : drvdata->sysmmu,
+ "%s is not handled by %s\n",
+ sysmmu_fault_name[itype],
+ dev_name(drvdata->sysmmu));
- if (itype != SYSMMU_FAULT_UNKNOWN)
- sysmmu_unblock(data->sfrbases[i]);
+ sysmmu_unblock(drvdata->sfrbases[i]);
- read_unlock(&data->lock);
+ if (owner)
+ spin_unlock(&owner->lock);
return IRQ_HANDLED;
}
-static bool __exynos_sysmmu_disable(struct sysmmu_drvdata *data)
+static void __sysmmu_disable_nocount(struct sysmmu_drvdata *drvdata)
{
- unsigned long flags;
- bool disabled = false;
int i;
- write_lock_irqsave(&data->lock, flags);
+ for (i = 0; i < drvdata->nsfrs; i++)
+ __raw_writel(CTRL_DISABLE,
+ drvdata->sfrbases[i] + REG_MMU_CTRL);
+
+ clk_disable(drvdata->clk);
+}
+
+static bool __sysmmu_disable(struct sysmmu_drvdata *drvdata)
+{
+ bool disabled;
+ unsigned long flags;
- if (!set_sysmmu_inactive(data))
- goto finish;
+ spin_lock_irqsave(&drvdata->lock, flags);
- for (i = 0; i < data->nsfrs; i++)
- __raw_writel(CTRL_DISABLE, data->sfrbases[i] + REG_MMU_CTRL);
+ disabled = set_sysmmu_inactive(drvdata);
- if (data->clk[1])
- clk_disable(data->clk[1]);
- if (data->clk[0])
- clk_disable(data->clk[0]);
+ if (disabled) {
+ drvdata->pgtable = 0;
+ drvdata->domain = NULL;
- disabled = true;
- data->pgtable = 0;
- data->domain = NULL;
-finish:
- write_unlock_irqrestore(&data->lock, flags);
+ if (drvdata->runtime_active)
+ __sysmmu_disable_nocount(drvdata);
- if (disabled)
- dev_dbg(data->sysmmu, "(%s) Disabled\n", data->dbgname);
- else
- dev_dbg(data->sysmmu, "(%s) %d times left to be disabled\n",
- data->dbgname, data->activations);
+ dev_dbg(drvdata->sysmmu, "Disabled\n");
+ } else {
+ dev_dbg(drvdata->sysmmu, "%d times left to be disabled\n",
+ drvdata->activations);
+ }
+
+ spin_unlock_irqrestore(&drvdata->lock, flags);
return disabled;
}
+static void __sysmmu_init_prefbuf(struct sysmmu_drvdata *drvdata, int idx,
+ int maj, int min)
+{
+ if (maj == 3) {
+ struct sysmmu_prefbuf pbuf[1] = { {0, ~0} };
+
+ func_set_pbuf[min](drvdata, idx, 1, pbuf);
+ }
+}
+
+static void __sysmmu_enable_nocount(struct sysmmu_drvdata *drvdata)
+{
+ int i;
+
+ clk_enable(drvdata->clk);
+
+ for (i = 0; i < drvdata->nsfrs; i++) {
+ int maj, min;
+ unsigned long cfg = CFG_LRU | CFG_QOS(15);
+
+ __sysmmu_set_ptbase(drvdata->sfrbases[i], drvdata->pgtable);
+
+ /* Initialization of REG_MMU_CFG must be prior to
+ call to __sysmmu_init_prefbuf() */
+ maj = __sysmmu_version(drvdata, i, &min);
+ if (maj == 3) {
+ cfg |= CFG_SHAREABLE;
+ if (min == 2)
+ cfg |= CFG_FLPDCACHE | CFG_SYSSEL;
+ }
+ __raw_writel(cfg, drvdata->sfrbases[i] + REG_MMU_CFG);
+
+ __sysmmu_init_prefbuf(drvdata, i, maj, min);
+
+ __raw_writel(CTRL_ENABLE, drvdata->sfrbases[i] + REG_MMU_CTRL);
+ }
+}
+
+static int __sysmmu_enable(struct sysmmu_drvdata *drvdata,
+ unsigned long pgtable, struct iommu_domain *domain)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&drvdata->lock, flags);
+ if (set_sysmmu_active(drvdata)) {
+ drvdata->pgtable = pgtable;
+ drvdata->domain = domain;
+
+ if (drvdata->runtime_active)
+ __sysmmu_enable_nocount(drvdata);
+
+ dev_dbg(drvdata->sysmmu, "Enabled\n");
+ } else {
+ ret = (pgtable == drvdata->pgtable) ? 1 : -EBUSY;
+
+ dev_dbg(drvdata->sysmmu, "Already enabled\n");
+ }
+
+ if (WARN_ON(ret < 0))
+ set_sysmmu_inactive(drvdata); /* decrement count */
+
+ spin_unlock_irqrestore(&drvdata->lock, flags);
+
+ return ret;
+}
+
/* __exynos_sysmmu_enable: Enables System MMU
*
* returns -error if an error occurred and System MMU is not enabled,
* 0 if the System MMU has been just enabled and 1 if System MMU was already
* enabled before.
*/
-static int __exynos_sysmmu_enable(struct sysmmu_drvdata *data,
- unsigned long pgtable, struct iommu_domain *domain)
+static int __exynos_sysmmu_enable(struct device *dev, unsigned long pgtable,
+ struct iommu_domain *domain)
{
- int i, ret = 0;
+ int ret = 0;
unsigned long flags;
+ struct exynos_iommu_owner *owner = dev->archdata.iommu;
+ struct device *sysmmu;
- write_lock_irqsave(&data->lock, flags);
-
- if (!set_sysmmu_active(data)) {
- if (WARN_ON(pgtable != data->pgtable)) {
- ret = -EBUSY;
- set_sysmmu_inactive(data);
- } else {
- ret = 1;
- }
-
- dev_dbg(data->sysmmu, "(%s) Already enabled\n", data->dbgname);
- goto finish;
- }
-
- if (data->clk[0])
- clk_enable(data->clk[0]);
- if (data->clk[1])
- clk_enable(data->clk[1]);
+ BUG_ON(!has_sysmmu(dev));
- data->pgtable = pgtable;
+ spin_lock_irqsave(&owner->lock, flags);
- for (i = 0; i < data->nsfrs; i++) {
- __sysmmu_set_ptbase(data->sfrbases[i], pgtable);
-
- if ((readl(data->sfrbases[i] + REG_MMU_VERSION) >> 28) == 3) {
- /* System MMU version is 3.x */
- __raw_writel((1 << 12) | (2 << 28),
- data->sfrbases[i] + REG_MMU_CFG);
- __sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 0);
- __sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 1);
+ for_each_sysmmu(dev, sysmmu) {
+ struct sysmmu_drvdata *drvdata = dev_get_drvdata(sysmmu);
+ ret = __sysmmu_enable(drvdata, pgtable, domain);
+ if (ret < 0) {
+ struct device *iter;
+ for_each_sysmmu_until(dev, iter, sysmmu) {
+ drvdata = dev_get_drvdata(iter);
+ __sysmmu_disable(drvdata);
+ }
+ } else {
+ drvdata->master = dev;
}
-
- __raw_writel(CTRL_ENABLE, data->sfrbases[i] + REG_MMU_CTRL);
}
- data->domain = domain;
-
- dev_dbg(data->sysmmu, "(%s) Enabled\n", data->dbgname);
-finish:
- write_unlock_irqrestore(&data->lock, flags);
+ spin_unlock_irqrestore(&owner->lock, flags);
return ret;
}
int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable)
{
- struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
int ret;
BUG_ON(!memblock_is_memory(pgtable));
- ret = pm_runtime_get_sync(data->sysmmu);
- if (ret < 0) {
- dev_dbg(data->sysmmu, "(%s) Failed to enable\n", data->dbgname);
- return ret;
- }
-
- ret = __exynos_sysmmu_enable(data, pgtable, NULL);
- if (WARN_ON(ret < 0)) {
- pm_runtime_put(data->sysmmu);
- dev_err(data->sysmmu,
- "(%s) Already enabled with page table %#lx\n",
- data->dbgname, data->pgtable);
- } else {
- data->dev = dev;
- }
+ ret = __exynos_sysmmu_enable(dev, pgtable, NULL);
return ret;
}
bool exynos_sysmmu_disable(struct device *dev)
{
- struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
- bool disabled;
+ unsigned long flags;
+ bool disabled = true;
+ struct exynos_iommu_owner *owner = dev->archdata.iommu;
+ struct device *sysmmu;
+
+ BUG_ON(!has_sysmmu(dev));
- disabled = __exynos_sysmmu_disable(data);
- pm_runtime_put(data->sysmmu);
+ spin_lock_irqsave(&owner->lock, flags);
+
+ /* Every call to __sysmmu_disable() must return same result */
+ for_each_sysmmu(dev, sysmmu) {
+ struct sysmmu_drvdata *drvdata = dev_get_drvdata(sysmmu);
+ disabled = __sysmmu_disable(drvdata);
+ if (disabled)
+ drvdata->master = NULL;
+ }
+
+ spin_unlock_irqrestore(&owner->lock, flags);
return disabled;
}
-static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova)
+void exynos_sysmmu_tlb_invalidate(struct device *dev)
{
- unsigned long flags;
- struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
-
- read_lock_irqsave(&data->lock, flags);
-
- if (is_sysmmu_active(data)) {
- int i;
- for (i = 0; i < data->nsfrs; i++) {
- if (sysmmu_block(data->sfrbases[i])) {
- __sysmmu_tlb_invalidate_entry(
- data->sfrbases[i], iova);
- sysmmu_unblock(data->sfrbases[i]);
+ struct device *sysmmu;
+
+ for_each_sysmmu(dev, sysmmu) {
+ unsigned long flags;
+ struct sysmmu_drvdata *drvdata;
+
+ drvdata = dev_get_drvdata(sysmmu);
+
+ spin_lock_irqsave(&drvdata->lock, flags);
+ if (is_sysmmu_active(drvdata) &&
+ drvdata->runtime_active) {
+ int i;
+ for (i = 0; i < drvdata->nsfrs; i++) {
+ if (sysmmu_block(drvdata->sfrbases[i])) {
+ __sysmmu_tlb_invalidate(
+ drvdata->sfrbases[i]);
+ sysmmu_unblock(drvdata->sfrbases[i]);
+ }
}
+ } else {
+ dev_dbg(dev, "Disabled. Skipping TLB invalidation\n");
}
- } else {
- dev_dbg(data->sysmmu,
- "(%s) Disabled. Skipping invalidating TLB.\n",
- data->dbgname);
+ spin_unlock_irqrestore(&drvdata->lock, flags);
}
+}
- read_unlock_irqrestore(&data->lock, flags);
+#ifdef CONFIG_EXYNOS_IOMMU_TLBINV_BY_ENTRY
+static void _sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova)
+{
+ struct device *sysmmu;
+
+ for_each_sysmmu(dev, sysmmu) {
+ unsigned long flags;
+ struct sysmmu_drvdata *drvdata;
+
+ drvdata = dev_get_drvdata(sysmmu);
+
+ spin_lock_irqsave(&drvdata->lock, flags);
+ if (is_sysmmu_active(drvdata) &&
+ drvdata->runtime_active) {
+ int i;
+ for (i = 0; i < drvdata->nsfrs; i++) {
+ if (sysmmu_block(drvdata->sfrbases[i])) {
+ __raw_writel((iova & SPAGE_MASK) | 1,
+ drvdata->sfrbases[i] +
+ REG_MMU_FLUSH_ENTRY);
+ sysmmu_unblock(drvdata->sfrbases[i]);
+ } else {
+ dev_err(dev,
+ "%s failed due to blocking timeout\n",
+ __func__);
+ }
+ }
+ } else {
+ dev_dbg(dev,
+ "Disabled. Skipping TLB invalidation for %#lx\n", iova);
+ }
+ spin_unlock_irqrestore(&drvdata->lock, flags);
+ }
}
+#endif
-void exynos_sysmmu_tlb_invalidate(struct device *dev)
+static int __init __sysmmu_init_clock(struct device *sysmmu,
+ struct sysmmu_drvdata *drvdata,
+ struct device *master)
{
- unsigned long flags;
- struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+ char *conid;
+ struct clk *parent_clk;
+ int ret;
+
+ drvdata->clk = clk_get(sysmmu, "sysmmu");
+ if (IS_ERR(drvdata->clk)) {
+ dev_dbg(sysmmu, "No gating clock found.\n");
+ drvdata->clk = NULL;
+ return 0;
+ }
- read_lock_irqsave(&data->lock, flags);
+ if (!master)
+ return 0;
- if (is_sysmmu_active(data)) {
- int i;
- for (i = 0; i < data->nsfrs; i++) {
- if (sysmmu_block(data->sfrbases[i])) {
- __sysmmu_tlb_invalidate(data->sfrbases[i]);
- sysmmu_unblock(data->sfrbases[i]);
- }
+ conid = dev_get_platdata(sysmmu);
+ if (!conid) {
+ dev_dbg(sysmmu, "No parent clock specified.\n");
+ return 0;
+ }
+
+ parent_clk = clk_get(master, conid);
+ if (IS_ERR(parent_clk)) {
+ parent_clk = clk_get(NULL, conid);
+ if (IS_ERR(parent_clk)) {
+ clk_put(drvdata->clk);
+ dev_err(sysmmu, "No parent clock '%s,%s' found\n",
+ dev_name(master), conid);
+ return PTR_ERR(parent_clk);
}
- } else {
- dev_dbg(data->sysmmu,
- "(%s) Disabled. Skipping invalidating TLB.\n",
- data->dbgname);
}
- read_unlock_irqrestore(&data->lock, flags);
+ ret = clk_set_parent(drvdata->clk, parent_clk);
+ if (ret) {
+ clk_put(drvdata->clk);
+ dev_err(sysmmu, "Failed to set parent clock '%s,%s'\n",
+ dev_name(master), conid);
+ }
+
+ clk_put(parent_clk);
+
+ return ret;
}
-static int exynos_sysmmu_probe(struct platform_device *pdev)
+static int __init __sysmmu_setup(struct device *sysmmu,
+ struct sysmmu_drvdata *drvdata)
{
- int i, ret;
- struct device *dev;
- struct sysmmu_drvdata *data;
+ struct exynos_iommu_owner *owner;
+ struct device_node *master_node;
+ struct device *child;
+ const char *compat;
+ struct platform_device *pmaster = NULL;
+ u32 master_inst_no = -1;
+ u32 ver[2];
+ int ret;
- dev = &pdev->dev;
+ if (!of_property_read_u32_array(sysmmu->of_node, "version", ver, 2)) {
+ drvdata->ver.major = (unsigned char)ver[0];
+ drvdata->ver.minor = (unsigned char)ver[1];
+ dev_dbg(sysmmu, "Found version %d.%d\n", ver[0], ver[1]);
+ }
- data = kzalloc(sizeof(*data), GFP_KERNEL);
- if (!data) {
- dev_dbg(dev, "Not enough memory\n");
+ master_node = of_parse_phandle(sysmmu->of_node, "mmu-master", 0);
+ if (!master_node && !of_property_read_string(
+ sysmmu->of_node, "mmu-master-compat", &compat)) {
+ of_property_read_u32_array(sysmmu->of_node,
+ "mmu-master-no", &master_inst_no, 1);
+ for_each_compatible_node(master_node, NULL, compat) {
+ pmaster = of_find_device_by_node(master_node);
+ if (pmaster && (pmaster->id == master_inst_no))
+ break;
+ of_dev_put(pmaster);
+ pmaster = NULL;
+ }
+ } else if (master_node) {
+ pmaster = of_find_device_by_node(master_node);
+ }
+
+ if (!pmaster) {
+ dev_dbg(sysmmu, "No master device is specified.\n");
+ return __sysmmu_init_clock(sysmmu, drvdata, NULL);
+ }
+
+ child = &pmaster->dev;
+
+ while (child->parent && is_sysmmu(child->parent))
+ child = child->parent;
+
+ owner = devm_kzalloc(sysmmu, sizeof(*owner), GFP_KERNEL);
+ if (!owner) {
ret = -ENOMEM;
- goto err_alloc;
+ dev_err(sysmmu, "Failed to allocate iommu data\n");
+ goto err_dev_put;
}
- ret = dev_set_drvdata(dev, data);
+ INIT_LIST_HEAD(&owner->client);
+ owner->dev = &pmaster->dev;
+ spin_lock_init(&owner->lock);
+
+ ret = device_move(child, sysmmu, DPM_ORDER_PARENT_BEFORE_DEV);
if (ret) {
- dev_dbg(dev, "Unabled to initialize driver data\n");
- goto err_init;
+ dev_err(sysmmu, "Failed to set parent of %s\n",
+ dev_name(child));
+ goto err_dev_put;
}
- data->nsfrs = pdev->num_resources / 2;
- data->sfrbases = kmalloc(sizeof(*data->sfrbases) * data->nsfrs,
- GFP_KERNEL);
- if (data->sfrbases == NULL) {
- dev_dbg(dev, "Not enough memory\n");
- ret = -ENOMEM;
- goto err_init;
+ pmaster->dev.archdata.iommu = owner;
+
+ ret = __sysmmu_init_clock(sysmmu, drvdata, owner->dev);
+ if (ret)
+ dev_err(sysmmu, "Failed to initialize gating clocks\n");
+ else
+ dev_dbg(sysmmu, "Assigned master device %s\n",
+ dev_name(owner->dev));
+err_dev_put:
+ of_dev_put(pmaster);
+
+ return ret;
+}
+
+static void __init __sysmmu_init_mmuname(struct device *sysmmu,
+ struct sysmmu_drvdata *drvdata)
+{
+ int i;
+
+ if (of_property_count_strings(sysmmu->of_node, "mmuname") !=
+ drvdata->nsfrs)
+ return;
+
+ drvdata->mmuname = (void *)drvdata + sizeof(*drvdata) +
+ sizeof(*drvdata->sfrbases) * drvdata->nsfrs;
+
+ for (i = 0; i < drvdata->nsfrs; i++) {
+ if (of_property_read_string_index(sysmmu->of_node,
+ "mmuname", i, &drvdata->mmuname[i])) {
+ dev_err(sysmmu, "Failed read mmuname[%d]\n", i);
+ drvdata->mmuname[i] = "noname";
+ }
+ }
+}
+
+static void __create_debugfs_entry(struct sysmmu_drvdata *drvdata);
+
+static int __init exynos_sysmmu_probe(struct platform_device *pdev)
+{
+ int i, ret;
+ struct device *dev = &pdev->dev;
+ struct sysmmu_drvdata *data;
+
+ if (pdev->num_resources == 0) {
+ dev_err(dev, "No System MMU resource defined\n");
+ return -ENODEV;
+ }
+
+ ret = of_property_count_strings(pdev->dev.of_node, "mmuname");
+ if (ret != (int)pdev->num_resources)
+ ret = 0;
+
+ data = devm_kzalloc(dev,
+ sizeof(*data)
+ + sizeof(*data->sfrbases) * (pdev->num_resources / 2)
+ + sizeof(*data->mmuname) * ret,
+ GFP_KERNEL);
+ if (!data) {
+ dev_err(dev, "Not enough memory\n");
+ return -ENOMEM;
}
+ data->nsfrs = pdev->num_resources / 2;
+
for (i = 0; i < data->nsfrs; i++) {
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
if (!res) {
- dev_dbg(dev, "Unable to find IOMEM region\n");
- ret = -ENOENT;
- goto err_res;
+ dev_err(dev, "Unable to find IOMEM region\n");
+ return -ENOENT;
}
- data->sfrbases[i] = ioremap(res->start, resource_size(res));
+ data->sfrbases[i] = devm_request_and_ioremap(dev, res);
if (!data->sfrbases[i]) {
- dev_dbg(dev, "Unable to map IOMEM @ PA:%#x\n",
+ dev_err(dev, "Unable to map IOMEM @ PA:%#x\n",
res->start);
- ret = -ENOENT;
- goto err_res;
+ return -EBUSY;
}
}
for (i = 0; i < data->nsfrs; i++) {
ret = platform_get_irq(pdev, i);
if (ret <= 0) {
- dev_dbg(dev, "Unable to find IRQ resource\n");
- goto err_irq;
+ dev_err(dev, "Unable to find IRQ resource\n");
+ return ret;
}
- ret = request_irq(ret, exynos_sysmmu_irq, 0,
+ ret = devm_request_irq(dev, ret, exynos_sysmmu_irq, 0,
dev_name(dev), data);
if (ret) {
- dev_dbg(dev, "Unabled to register interrupt handler\n");
- goto err_irq;
+ dev_err(dev, "Unabled to register interrupt handler\n");
+ return ret;
}
}
- if (dev_get_platdata(dev)) {
- char *deli, *beg;
- struct sysmmu_platform_data *platdata = dev_get_platdata(dev);
+ pm_runtime_enable(dev);
- beg = platdata->clockname;
+ ret = __sysmmu_setup(dev, data);
+ if (!ret) {
+ __sysmmu_init_mmuname(dev, data);
- for (deli = beg; (*deli != '\0') && (*deli != ','); deli++)
- /* NOTHING */;
+ data->runtime_active = !pm_runtime_enabled(dev);
+ data->sysmmu = dev;
+ spin_lock_init(&data->lock);
- if (*deli == '\0')
- deli = NULL;
- else
- *deli = '\0';
+ __set_fault_handler(data, &default_fault_handler);
- data->clk[0] = clk_get(dev, beg);
- if (IS_ERR(data->clk[0])) {
- data->clk[0] = NULL;
- dev_dbg(dev, "No clock descriptor registered\n");
- }
+ __create_debugfs_entry(data);
- if (data->clk[0] && deli) {
- *deli = ',';
- data->clk[1] = clk_get(dev, deli + 1);
- if (IS_ERR(data->clk[1]))
- data->clk[1] = NULL;
- }
+ platform_set_drvdata(pdev, data);
- data->dbgname = platdata->dbgname;
+ dev->archdata.iommu = &sysmmu_placeholder;
+ dev_dbg(dev, "Initialized successfully!\n");
}
- data->sysmmu = dev;
- rwlock_init(&data->lock);
- INIT_LIST_HEAD(&data->node);
+ return ret;
+}
- __set_fault_handler(data, &default_fault_handler);
+#ifdef CONFIG_PM_SLEEP
+static int sysmmu_suspend(struct device *dev)
+{
+ struct sysmmu_drvdata *drvdata = dev_get_drvdata(dev);
+ unsigned long flags;
+ spin_lock_irqsave(&drvdata->lock, flags);
+ if (is_sysmmu_active(drvdata) &&
+ (!pm_runtime_enabled(dev) || drvdata->runtime_active))
+ __sysmmu_disable_nocount(drvdata);
+ spin_unlock_irqrestore(&drvdata->lock, flags);
+ return 0;
+}
- if (dev->parent)
- pm_runtime_enable(dev);
+static int sysmmu_resume(struct device *dev)
+{
+ struct sysmmu_drvdata *drvdata = dev_get_drvdata(dev);
+ unsigned long flags;
+ spin_lock_irqsave(&drvdata->lock, flags);
+ if (is_sysmmu_active(drvdata) &&
+ (!pm_runtime_enabled(dev) || drvdata->runtime_active)) {
+ __sysmmu_enable_nocount(drvdata);
+ __sysmmu_restore_state(drvdata);
+ }
+ spin_unlock_irqrestore(&drvdata->lock, flags);
+ return 0;
+}
+#endif
- dev_dbg(dev, "(%s) Initialized\n", data->dbgname);
+#ifdef CONFIG_PM_RUNTIME
+static int sysmmu_runtime_suspend(struct device *dev)
+{
+ struct sysmmu_drvdata *drvdata = dev_get_drvdata(dev);
+ unsigned long flags;
+ spin_lock_irqsave(&drvdata->lock, flags);
+ if (is_sysmmu_active(drvdata))
+ __sysmmu_disable_nocount(drvdata);
+ drvdata->runtime_active = false;
+ spin_unlock_irqrestore(&drvdata->lock, flags);
return 0;
-err_irq:
- while (i-- > 0) {
- int irq;
+}
- irq = platform_get_irq(pdev, i);
- free_irq(irq, data);
- }
-err_res:
- while (data->nsfrs-- > 0)
- iounmap(data->sfrbases[data->nsfrs]);
- kfree(data->sfrbases);
-err_init:
- kfree(data);
-err_alloc:
- dev_err(dev, "Failed to initialize\n");
- return ret;
+static int sysmmu_runtime_resume(struct device *dev)
+{
+ struct sysmmu_drvdata *drvdata = dev_get_drvdata(dev);
+ unsigned long flags;
+ spin_lock_irqsave(&drvdata->lock, flags);
+ drvdata->runtime_active = true;
+ if (is_sysmmu_active(drvdata))
+ __sysmmu_enable_nocount(drvdata);
+ spin_unlock_irqrestore(&drvdata->lock, flags);
+ return 0;
}
+#endif
+
+static const struct dev_pm_ops __pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(sysmmu_suspend, sysmmu_resume)
+ SET_RUNTIME_PM_OPS(sysmmu_runtime_resume, sysmmu_runtime_suspend, NULL)
+};
+
+/*
+ * Descriptions of Device Tree node for System MMU
+ *
+ * A System MMU should be described by a single tree node.
+ *
+ * A System MMU node should have the following properties:
+ * - reg: tuples of the base address and the size of the IO region of System MMU
+ * - compatible: it must be "samsung,exynos-sysmmu".
+ * - interrupt-parent = specify if the interrupt of System MMU is generated by
+ * interrupt combiner or interrupt controller.
+ * - interrupts: tuples of interrupt numbers. a tuple has 2 elements if
+ * @interrupt-parent is '<&combiner>', 3 elements otherwise.
+ *
+ * 'mmuname', 'reg' and 'interrupts' properties can be an array if the System
+ * MMU driver controls several number of System MMUs at the same time. Note that
+ * the number of elements in those three properties must be the same.
+ *
+ * The following properties are optional:
+ * - mmuname: name of the System MMU for debugging purpose
+ * - mmu-master: reference to the node of the master device.
+ * - mmu-master-compat: 'compatible' proberty of the node of the master device
+ * of System MMU. This is ignored if @mmu-master is currectly specified.
+ * - mmu-master-no: instance number of the master device of System MMU. This is
+ * ignored if @mmu-master is correctly specified. This is '0' by default.
+ */
+#ifdef CONFIG_OF
+static struct of_device_id sysmmu_of_match[] __initconst = {
+ { .compatible = "samsung,exynos-sysmmu", },
+ { },
+};
+#endif
-static struct platform_driver exynos_sysmmu_driver = {
+static struct platform_driver exynos_sysmmu_driver __refdata = {
.probe = exynos_sysmmu_probe,
.driver = {
.owner = THIS_MODULE,
- .name = "exynos-sysmmu",
+ .name = MODULE_NAME,
+ .pm = &__pm_ops,
+ .of_match_table = of_match_ptr(sysmmu_of_match),
}
};
@@ -732,10 +1235,6 @@ static int exynos_iommu_domain_init(struct iommu_domain *domain)
spin_lock_init(&priv->pgtablelock);
INIT_LIST_HEAD(&priv->clients);
- domain->geometry.aperture_start = 0;
- domain->geometry.aperture_end = ~0UL;
- domain->geometry.force_aperture = true;
-
domain->priv = priv;
return 0;
@@ -749,7 +1248,7 @@ err_pgtable:
static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
{
struct exynos_iommu_domain *priv = domain->priv;
- struct sysmmu_drvdata *data;
+ struct exynos_iommu_owner *owner, *n;
unsigned long flags;
int i;
@@ -757,16 +1256,18 @@ static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
spin_lock_irqsave(&priv->lock, flags);
- list_for_each_entry(data, &priv->clients, node) {
- while (!exynos_sysmmu_disable(data->dev))
+ list_for_each_entry_safe(owner, n, &priv->clients, client) {
+ while (!exynos_sysmmu_disable(owner->dev))
; /* until System MMU is actually disabled */
+ list_del_init(&owner->client);
}
spin_unlock_irqrestore(&priv->lock, flags);
for (i = 0; i < NUM_LV1ENTRIES; i++)
if (lv1ent_page(priv->pgtable + i))
- kfree(__va(lv2table_base(priv->pgtable + i)));
+ kmem_cache_free(lv2table_kmem_cache,
+ __va(lv2table_base(priv->pgtable + i)));
free_pages((unsigned long)priv->pgtable, 2);
free_pages((unsigned long)priv->lv2entcnt, 1);
@@ -777,41 +1278,54 @@ static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
static int exynos_iommu_attach_device(struct iommu_domain *domain,
struct device *dev)
{
- struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+ struct exynos_iommu_owner *owner = dev->archdata.iommu;
struct exynos_iommu_domain *priv = domain->priv;
unsigned long flags;
int ret;
- ret = pm_runtime_get_sync(data->sysmmu);
- if (ret < 0)
- return ret;
+ if (WARN_ON(!list_empty(&owner->client))) {
+ bool found = false;
+ struct exynos_iommu_owner *tmpowner;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ list_for_each_entry(tmpowner, &priv->clients, client) {
+ if (tmpowner == owner) {
+ found = true;
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&priv->lock, flags);
- ret = 0;
+ if (!found) {
+ dev_err(dev, "%s: Already attached to another domain\n",
+ __func__);
+ return -EBUSY;
+ }
+
+ dev_dbg(dev, "%s: Already attached to this domain\n", __func__);
+ return 0;
+ }
spin_lock_irqsave(&priv->lock, flags);
- ret = __exynos_sysmmu_enable(data, __pa(priv->pgtable), domain);
+ ret = __exynos_sysmmu_enable(dev, __pa(priv->pgtable), domain);
- if (ret == 0) {
- /* 'data->node' must not be appeared in priv->clients */
- BUG_ON(!list_empty(&data->node));
- data->dev = dev;
- list_add_tail(&data->node, &priv->clients);
- }
+ /*
+ * __exynos_sysmmu_enable() returns 1
+ * if the System MMU of dev is already enabled
+ */
+ BUG_ON(ret > 0);
+
+ list_add_tail(&owner->client, &priv->clients);
spin_unlock_irqrestore(&priv->lock, flags);
- if (ret < 0) {
+ if (ret < 0)
dev_err(dev, "%s: Failed to attach IOMMU with pgtable %#lx\n",
__func__, __pa(priv->pgtable));
- pm_runtime_put(data->sysmmu);
- } else if (ret > 0) {
- dev_dbg(dev, "%s: IOMMU with pgtable 0x%lx already attached\n",
- __func__, __pa(priv->pgtable));
- } else {
+ else
dev_dbg(dev, "%s: Attached new IOMMU with pgtable 0x%lx\n",
__func__, __pa(priv->pgtable));
- }
return ret;
}
@@ -819,39 +1333,29 @@ static int exynos_iommu_attach_device(struct iommu_domain *domain,
static void exynos_iommu_detach_device(struct iommu_domain *domain,
struct device *dev)
{
- struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+ struct exynos_iommu_owner *owner, *n;
struct exynos_iommu_domain *priv = domain->priv;
- struct list_head *pos;
unsigned long flags;
- bool found = false;
spin_lock_irqsave(&priv->lock, flags);
- list_for_each(pos, &priv->clients) {
- if (list_entry(pos, struct sysmmu_drvdata, node) == data) {
- found = true;
+ list_for_each_entry_safe(owner, n, &priv->clients, client) {
+ if (owner == dev->archdata.iommu) {
+ if (exynos_sysmmu_disable(dev))
+ list_del_init(&owner->client);
+ else
+ BUG();
break;
}
}
- if (!found)
- goto finish;
+ spin_unlock_irqrestore(&priv->lock, flags);
- if (__exynos_sysmmu_disable(data)) {
+ if (owner == dev->archdata.iommu)
dev_dbg(dev, "%s: Detached IOMMU with pgtable %#lx\n",
__func__, __pa(priv->pgtable));
- list_del_init(&data->node);
-
- } else {
- dev_dbg(dev, "%s: Detaching IOMMU with pgtable %#lx delayed",
- __func__, __pa(priv->pgtable));
- }
-
-finish:
- spin_unlock_irqrestore(&priv->lock, flags);
-
- if (found)
- pm_runtime_put(data->sysmmu);
+ else
+ dev_dbg(dev, "%s: No IOMMU is attached\n", __func__);
}
static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,
@@ -860,7 +1364,7 @@ static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,
if (lv1ent_fault(sent)) {
unsigned long *pent;
- pent = kzalloc(LV2TABLE_SIZE, GFP_ATOMIC);
+ pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
if (!pent)
return NULL;
@@ -883,7 +1387,7 @@ static int lv1set_section(unsigned long *sent, phys_addr_t paddr, short *pgcnt)
if (*pgcnt != NUM_LV2ENTRIES)
return -EADDRINUSE;
- kfree(page_entry(sent, 0));
+ kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
*pgcnt = 0;
}
@@ -966,7 +1470,6 @@ static size_t exynos_iommu_unmap(struct iommu_domain *domain,
unsigned long iova, size_t size)
{
struct exynos_iommu_domain *priv = domain->priv;
- struct sysmmu_drvdata *data;
unsigned long flags;
unsigned long *ent;
@@ -1017,11 +1520,15 @@ static size_t exynos_iommu_unmap(struct iommu_domain *domain,
done:
spin_unlock_irqrestore(&priv->pgtablelock, flags);
+#ifdef CONFIG_EXYNOS_IOMMU_TLBINV_BY_ENTRY
spin_lock_irqsave(&priv->lock, flags);
- list_for_each_entry(data, &priv->clients, node)
- sysmmu_tlb_invalidate_entry(data->dev, iova);
+ {
+ struct exynos_iommu_owner *owner;
+ list_for_each_entry(owner, &priv->clients, client)
+ _sysmmu_tlb_invalidate_entry(owner->dev, iova);
+ }
spin_unlock_irqrestore(&priv->lock, flags);
-
+#endif
return size;
}
@@ -1065,15 +1572,210 @@ static struct iommu_ops exynos_iommu_ops = {
.pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
};
+static struct dentry *sysmmu_debugfs_root; /* /sys/kernel/debug/sysmmu */
+
static int __init exynos_iommu_init(void)
{
int ret;
- ret = platform_driver_register(&exynos_sysmmu_driver);
+ lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
+ LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
+ if (!lv2table_kmem_cache) {
+ pr_err("%s: failed to create kmem cache\n", __func__);
+ return -ENOMEM;
+ }
+
+ ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
+ if (ret) {
+ kmem_cache_destroy(lv2table_kmem_cache);
+ pr_err("%s: Failed to register IOMMU ops\n", __func__);
+ return -EFAULT;
+ }
+
+ sysmmu_debugfs_root = debugfs_create_dir("sysmmu", NULL);
+ if (!sysmmu_debugfs_root)
+ pr_err("%s: Failed to create debugfs entry, 'sysmmu'\n",
+ __func__);
+ if (IS_ERR(sysmmu_debugfs_root))
+ sysmmu_debugfs_root = NULL;
- if (ret == 0)
- bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
+ ret = platform_driver_register(&exynos_sysmmu_driver);
+ if (ret) {
+ kmem_cache_destroy(lv2table_kmem_cache);
+ pr_err("%s: Failed to register System MMU driver\n", __func__);
+ }
return ret;
}
subsys_initcall(exynos_iommu_init);
+
+static int debug_string_show(struct seq_file *s, void *unused)
+{
+ char *str = s->private;
+
+ seq_printf(s, "%s\n", str);
+
+ return 0;
+}
+
+static int debug_sysmmu_list_show(struct seq_file *s, void *unused)
+{
+ struct sysmmu_drvdata *drvdata = s->private;
+ struct platform_device *pdev = to_platform_device(drvdata->sysmmu);
+ int idx, maj, min, ret;
+
+ seq_printf(s, "SysMMU Name | Ver | SFR Base\n");
+
+ if (pm_runtime_enabled(drvdata->sysmmu)) {
+ ret = pm_runtime_get_sync(drvdata->sysmmu);
+ if (ret < 0)
+ return ret;
+ }
+
+ for (idx = 0; idx < drvdata->nsfrs; idx++) {
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, idx);
+ if (!res)
+ break;
+
+ maj = __sysmmu_version(drvdata, idx, &min);
+
+ if (drvdata->mmuname) {
+ if (maj == 0)
+ seq_printf(s, "%11.s | N/A | 0x%08x\n",
+ drvdata->mmuname[idx], res->start);
+ else
+ seq_printf(s, "%11.s | %d.%d | 0x%08x\n",
+ drvdata->mmuname[idx], maj, min, res->start);
+ } else {
+ if (maj == 0)
+ seq_printf(s, "N/A | 0x%08x\n", res->start);
+ else
+ seq_printf(s, "%d.%d | 0x%08x\n",
+ maj, min, res->start);
+ }
+ }
+
+ if (pm_runtime_enabled(drvdata->sysmmu))
+ pm_runtime_put(drvdata->sysmmu);
+
+ return 0;
+}
+
+static int debug_next_sibling_show(struct seq_file *s, void *unused)
+{
+ struct device *dev = s->private;
+
+ if (dev->parent &&
+ !strncmp(dev_name(dev->parent),
+ MODULE_NAME, strlen(MODULE_NAME)))
+ seq_printf(s, "%s\n", dev_name(dev->parent));
+ return 0;
+}
+
+static int __show_master(struct device *dev, void *data)
+{
+ struct seq_file *s = data;
+
+ if (strncmp(dev_name(dev), MODULE_NAME, strlen(MODULE_NAME)))
+ seq_printf(s, "%s\n", dev_name(dev));
+ return 0;
+}
+
+static int debug_master_show(struct seq_file *s, void *unused)
+{
+ struct device *dev = s->private;
+
+ device_for_each_child(dev, s, __show_master);
+ return 0;
+}
+
+static int debug_string_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, debug_string_show, inode->i_private);
+}
+
+static int debug_sysmmu_list_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, debug_sysmmu_list_show, inode->i_private);
+}
+
+static int debug_next_sibling_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, debug_next_sibling_show, inode->i_private);
+}
+
+static int debug_master_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, debug_master_show, inode->i_private);
+}
+
+static const struct file_operations debug_string_fops = {
+ .open = debug_string_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static const struct file_operations debug_sysmmu_list_fops = {
+ .open = debug_sysmmu_list_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static const struct file_operations debug_next_sibling_fops = {
+ .open = debug_next_sibling_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static const struct file_operations debug_master_fops = {
+ .open = debug_master_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static void __init __create_debugfs_entry(struct sysmmu_drvdata *drvdata)
+{
+ if (!sysmmu_debugfs_root)
+ return;
+
+ drvdata->debugfs_root = debugfs_create_dir(dev_name(drvdata->sysmmu),
+ sysmmu_debugfs_root);
+ if (!drvdata->debugfs_root)
+ dev_err(drvdata->sysmmu, "Failed to create debugfs dentry\n");
+ if (IS_ERR(drvdata->debugfs_root))
+ drvdata->debugfs_root = NULL;
+
+ if (!drvdata->debugfs_root)
+ return;
+
+ if (!debugfs_create_u32("enable", 0664, drvdata->debugfs_root,
+ &drvdata->activations))
+ dev_err(drvdata->sysmmu,
+ "Failed to create debugfs file 'enable'\n");
+
+ if (!debugfs_create_x32("pagetable", 0664, drvdata->debugfs_root,
+ (u32 *)&drvdata->pgtable))
+ dev_err(drvdata->sysmmu,
+ "Failed to create debugfs file 'pagetable'\n");
+
+ if (!debugfs_create_file("sysmmu_list", 0444, drvdata->debugfs_root,
+ drvdata, &debug_sysmmu_list_fops))
+ dev_err(drvdata->sysmmu,
+ "Failed to create debugfs file 'sysmmu_list'\n");
+
+ if (!debugfs_create_file("next_sibling", 0x444, drvdata->debugfs_root,
+ drvdata->sysmmu, &debug_next_sibling_fops))
+ dev_err(drvdata->sysmmu,
+ "Failed to create debugfs file 'next_siblings'\n");
+
+ if (!debugfs_create_file("master", 0x444, drvdata->debugfs_root,
+ drvdata->sysmmu, &debug_master_fops))
+ dev_err(drvdata->sysmmu,
+ "Failed to create debugfs file 'next_siblings'\n");
+}
--
1.8.0
^ permalink raw reply related
* [PATCH v2] i2c: i2c-gpio: fix name issue when i2c gpio node GT 1
From: Wolfram Sang @ 2012-11-14 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350287477-30936-1-git-send-email-voice.shen@atmel.com>
On Mon, Oct 15, 2012 at 03:51:17PM +0800, Bo Shen wrote:
> When i2c-gpio node number is greater than 1, the name for each is same
> So add the patch to fix it.
>
> The adap->name printing information is add by myself
>
> without this patch the log information is as following
> ---<8---
> adap->name = i2c-gpio-1
> i2c-gpio i2c.2: using pins 30 (SDA) and 31 (SCL)
> adap->name = i2c-gpio-1
> i2c-gpio i2c.3: using pins 64 (SDA) and 65 (SCL)
> --->8---
>
> with this patch, the log information is as following
> ---<8---
> adap->name = i2c.2
> i2c-gpio i2c.2: using pins 30 (SDA) and 31 (SCL)
> adap->name = i2c.3
> i2c-gpio i2c.3: using pins 64 (SDA) and 65 (SCL)
> --->8---
>
> Signed-off-by: Bo Shen <voice.shen@atmel.com>
Applied to for-next, thanks.
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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* [PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ
From: Etienne CARRIERE ST @ 2012-11-14 9:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121113170711.GI28327@n2100.arm.linux.org.uk>
> From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> Sent: Tuesday, November 13, 2012 6:07 PM
>
> Right, so, what this tells me is that the implementation of the spinlock
> in the secure software is potentially the same as the kernel's spinlock.
> The kernel's spinlock implementation is GPL'd. If the secure side spinlock
> implementation is a copy of the kernel's spinlock implementation, then
> that implementation is also GPL'd (...).
>
> I think someone has some explaining to do.
It does.
The TZ implementation of the shared mutex is the ARM native mutex instructions set LDREX/STREX, protected by a native ARM IRQ disabling.
I believe this is native ARMv7 natural handling and not subject to GPLization.
This is why the mutex added for TZ shared of L2 cache maintenance is a "arch_spinlock". It assumes linux handles the spinlock as a native ARM native mutex DDR cell, handled from the ARMv7-A LDREX/STREX.
I think this is the weakest part of the driver since they is no insurance that linux pristine arch_spinlock will not evolve into something else (i.e features in raw_spinclock).
etienne
-----Original Message-----
To: Etienne CARRIERE
Cc: linux-arm-kernel at lists.infradead.org; Will Deacon; Marc Zyngier; Catalin Marinas; Linus Walleij (linus.walleij at linaro.org); Rabin VINCENT; Srinidhi KASAGAR
Subject: Re: [PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ
On Tue, Nov 13, 2012 at 05:08:14PM +0100, Etienne CARRIERE wrote:
> From: Etienne Carriere <etienne.carriere@stericsson.com>
>
> Secure code in TrustZone space may need to perform L2 cache
> maintenance operations. A shared mutex is required to synchronize
> linux l2cc maintenance and TZ l2cc maintenance.
>
> The TZ mutex is an "arch_spinlock": a 32bit DDR cell (ARMv7-A mutex).
> Linux L2 cache driver must lock TZ mutex if enabled.
>...
> +#define l2x0_spin_lock_irqsave(flags) \
> + do { \
> + raw_spin_lock_irqsave(&l2x0_lock, flags); \
> + if (l2x0_tz_mutex) \
> + arch_spin_lock(l2x0_tz_mutex); \
> + } while (0)
^ permalink raw reply
* [PATCH v2] i2c: at91: add dma support
From: Wolfram Sang @ 2012-11-14 9:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352470068-7678-1-git-send-email-ludovic.desroches@atmel.com>
On Fri, Nov 09, 2012 at 03:07:48PM +0100, ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches@atmel.com>
>
> Add dma support for Atmel TWI which is available on sam9x5 and later.
>
> When using dma for reception, you have to read only n-2 bytes. The last
> two bytes are read manually. Don't doing this should cause to send the
> STOP command too late and then to get extra data in the receive
> register.
>
> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Some minor comments. But please let sparse run over your build. It has
some hints for you.
> ---
>
> Changes:
> - v2 (based on Russell feedback):
> - replace DMA_TO_DEVICE/DMA_FROM_DEVICE by DMA_MEM_TO_DEV/DMA_DEV_TO_MEM
> - don't check for tx_submit errors
> - atmel dma header location has changed
>
> drivers/i2c/busses/i2c-at91.c | 316 ++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 305 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
> index aa59a25..f6fba9c 100644
> --- a/drivers/i2c/busses/i2c-at91.c
> +++ b/drivers/i2c/busses/i2c-at91.c
> @@ -19,6 +19,8 @@
>
> #include <linux/clk.h>
> #include <linux/completion.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/dmaengine.h>
> #include <linux/err.h>
> #include <linux/i2c.h>
> #include <linux/interrupt.h>
> @@ -30,6 +32,8 @@
> #include <linux/platform_device.h>
> #include <linux/slab.h>
>
Unneeded empty line.
> +#include <linux/platform_data/dma-atmel.h>
> +
> #define TWI_CLK_HZ 100000 /* max 400 Kbits/s */
> #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
>
> @@ -65,9 +69,21 @@
> #define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
>
> struct at91_twi_pdata {
> - unsigned clk_max_div;
> - unsigned clk_offset;
> - bool has_unre_flag;
> + unsigned clk_max_div;
> + unsigned clk_offset;
> + bool has_unre_flag;
> + bool has_dma_support;
> + struct at_dma_slave dma_slave;
> +};
This is a good example why indenting struct members to tabs is causing
trouble later. My recommendation is to use a single space even if this
means no alignment.
...
> @@ -224,12 +389,36 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
> if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN))
> start_flags |= AT91_TWI_STOP;
> at91_twi_write(dev, AT91_TWI_CR, start_flags);
> - at91_twi_write(dev, AT91_TWI_IER,
> + /*
> + * When using dma, the last byte has to be read manually in
> + * order to not send the stop command too late and then
> + * to receive extra data. In practice, there are some issues
> + * if you use the dma to read n-1 bytes because of latency.
> + * Reading n-2 bytes with dma and the two last ones manually
> + * seems to be the best solution.
> + */
> + if (dev->use_dma && (dev->buf_len > 2)) {
Setting up DMA can cause quite some overhead, so it might be more
efficient to to start using DMA only for transfers bigger than x byte
instead of 2.
...
BTW on a glimpse, are you really using the cookies you set up?
Regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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* OMAP* Latest build failures
From: Russell King - ARM Linux @ 2012-11-14 9:26 UTC (permalink / raw)
To: linux-arm-kernel
OMAP* allnoconfig fails:
arch/arm/mach-omap2/built-in.o: In function `omap_dss_set_min_bus_tput':
twl-common.c:(.text+0x1e08): undefined reference to `omap_pm_set_min_bus_tput'
arch/arm/mach-omap2/built-in.o: In function `omap_hwmod_init_postsetup':
twl-common.c:(.init.text+0x8f8): undefined reference to `omap_pm_if_early_init'
arch/arm/mach-omap2/built-in.o: In function `omap_serial_init_port':
twl-common.c:(.init.text+0x1284): undefined reference to `omap_pm_get_dev_context_loss_count'
arch/arm/mach-omap2/built-in.o: In function `omap_timer_init':
twl-common.c:(.init.text+0x1544): undefined reference to `omap_pm_get_dev_context_loss_count'
arch/arm/mach-omap2/built-in.o: In function `omap2_common_pm_init':
twl-common.c:(.init.text+0x1af0): undefined reference to `omap_pm_if_init'
arch/arm/mach-omap2/built-in.o: In function `omap2_gpio_dev_init':
twl-common.c:(.init.text+0x2168): undefined reference to `omap_pm_get_dev_context_loss_count'
arch/arm/mach-omap2/built-in.o: In function `omap_display_init':
twl-common.c:(.init.text+0x25cc): undefined reference to `omap_pm_get_dev_context_loss_count'
OMAP4 randconfig fails:
arch/arm/mach-omap2/cm_common.c: In function 'cm_register':
arch/arm/mach-omap2/cm_common.c:42:11: error: 'EINVAL' undeclared (first use in this function)
arch/arm/mach-omap2/cm_common.c:45:11: error: 'EEXIST' undeclared (first use in this function)
arch/arm/mach-omap2/cm_common.c: In function 'cm_unregister':
arch/arm/mach-omap2/cm_common.c:66:11: error: 'EINVAL' undeclared (first use in this function)
You know where to find the build information and results...
^ permalink raw reply
* [PATCH v2] i2c: at91: fix SMBus quick command
From: Wolfram Sang @ 2012-11-14 9:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352821401-1944-1-git-send-email-ludovic.desroches@atmel.com>
On Tue, Nov 13, 2012 at 04:43:21PM +0100, ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches@atmel.com>
>
> The driver claims to support SMBus quick command but it was not the case.
> This patch fixes this issue.
>
> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
> ---
>
> Hi Wolfram,
>
> Thanks to Jean explanation about i2cdetect and eeprom behavior, I realized
> that the first version of the patch was incorrect. This time all the i2c
> devices are detected with i2cdetect -q.
>
> I hope this fix could go into 3.7 since the driver claims SMBus quick
> capability but it doesn't support it. Moreover without it i2cdetect find
> imaginary devices, and with some IP versions, trying to send 0 byte can cause
> issue when writing data to an EEPROM.
Updated the commit message with the latter paragraph and added to
for-current, thanks!
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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* [PATCH 1/1] regulator: gpio-regulator: fix crash when no states property in dt
From: Lee Jones @ 2012-11-14 9:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352450076-22682-1-git-send-email-Frank.Li@freescale.com>
On Fri, 09 Nov 2012, Frank Li wrote:
> Unable to handle kernel NULL pointer dereference at virtual address 00000004
> pgd = 80004000
> [00000004] *pgd=00000000
> Internal error: Oops: 5 [#1] SMP ARM
> Modules linked in:
> CPU: 0 Not tainted (3.5.7+ #11)
> PC is at of_get_gpio_regulator_config+0x1b0/0x2e0
> LR is at of_find_property+0x4c/0x9c
> pc : [<8022498c>] lr : [<80322d44>] psr: 60000013
> sp : bf859de8 ip : bf859dc8 fp : bf859e14
> r10: 805d1180 r9 : 8053e208 r8 : 00000001
> r7 : 811056ec r6 : 00000000 r5 : bf8e0208 r4 : bf8f2b50
> r3 : 805a7e00 r2 : 000000d0 r1 : 00000000 r0 : 00000000
> Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
> Control: 10c53c7d Table: 1000404a DAC: 00000017
> Process swapper/0 (pid: 1, stack limit = 0xbf8582f0)
> Stack: (0xbf859de8 to 0xbf85a000)
> 9de0: bf859e34 bf859df8 8010a040 00000000 bf8e0200 811056ec
> 9e00: 00000000 805b4d9c bf859e54 bf859e18 80404a14 802247e8 00000000 00000000
> 9e20: 00000000 00000000 00000000 00000000 00000000 00000000 8061f05c 805b4d9c
> 9e40: bf8e0208 00000000 bf859e64 bf859e58 8024bc0c 804049e0 bf859e8c bf859e68
> 9e60: 8024a7d8 8024bbf8 00000000 bf8e0208 805b4d9c bf8e023c 00000000 0000008d
> 9e80: bf859eac bf859e90 8024a9dc 8024a76c 8024a948 805b4d9c 8024a948 00000000
> 9ea0: bf859ed4 bf859eb0 80248f10 8024a954 bf83b458 bf8dd934 801f13e0 805b4d9c
> 9ec0: 805b8af8 bf8e9f00 bf859ee4 bf859ed8 8024a358 80248ec4 bf859f14 bf859ee8
> 9ee0: 80249f94 8024a344 804eb244 805d1180 805b4d9c 00000004 00000000 805d1180
> 9f00: 0000008d 805d1180 bf859f3c bf859f18 8024aefc 80249e1c 00000000 bf858000
> 9f20: 00000004 00000000 805d1180 0000008d bf859f4c bf859f40 8024bedc 8024ae88
> 9f40: bf859f5c bf859f50 805600b4 8024be9c bf859fb4 bf859f60 800086e4 805600ac
> 9f60: bf859fb4 bf859f70 805600a0 00000000 00000000 00000004 00000004 8053cb20
> 9f80: 00000000 804c9788 bf859fb4 805770a0 00000004 80577080 805d1180 0000008d
> 9fa0: 8053e208 805827a4 bf859ff4 bf859fb8 8053e974 800086b0 00000004 00000004
> 9fc0: 8053e208 8053e870 80026750 00000000 8053e870 80026750 00000013 00000000
> 9fe0: 00000000 00000000 00000000 bf859ff8 80026750 8053e87c 9773f7a7 ed28dffe
> Backtrace:
> [<802247dc>] (of_get_gpio_regulator_config+0x0/0x2e0) from [<80404a14>] (gpio_regulator_probe+0x40/0x2f0)
> r8:805b4d9c r7:00000000 r6:811056ec r5:bf8e0200 r4:00000000
> [<804049d4>] (gpio_regulator_probe+0x0/0x2f0) from [<8024bc0c>] (platform_drv_probe+0x20/0x24)
> r7:00000000 r6:bf8e0208 r5:805b4d9c r4:8061f05c
> [<8024bbec>] (platform_drv_probe+0x0/0x24) from [<8024a7d8>] (driver_probe_device+0x78/0x1e8)
> [<8024a760>] (driver_probe_device+0x0/0x1e8) from [<8024a9dc>] (__driver_attach+0x94/0x98)
> r8:0000008d r7:00000000 r6:bf8e023c r5:805b4d9c r4:bf8e0208
> r3:00000000
> [<8024a948>] (__driver_attach+0x0/0x98) from [<80248f10>] (bus_for_each_dev+0x58/0x84)
> r6:00000000 r5:8024a948 r4:805b4d9c r3:8024a948
> [<80248eb8>] (bus_for_each_dev+0x0/0x84) from [<8024a358>] (driver_attach+0x20/0x28)
> r6:bf8e9f00 r5:805b8af8 r4:805b4d9c
> [<8024a338>] (driver_attach+0x0/0x28) from [<80249f94>] (bus_add_driver+0x184/0x250)
> [<80249e10>] (bus_add_driver+0x0/0x250) from [<8024aefc>] (driver_register+0x80/0x134)
> [<8024ae7c>] (driver_register+0x0/0x134) from [<8024bedc>] (platform_driver_register+0x4c/0x60)
> r8:0000008d r7:805d1180 r6:00000000 r5:00000004 r4:bf858000
> r3:00000000
> [<8024be90>] (platform_driver_register+0x0/0x60) from [<805600b4>] (gpio_regulator_init+0x14/0x1c)
> [<805600a0>] (gpio_regulator_init+0x0/0x1c) from [<800086e4>] (do_one_initcall+0x40/0x184)
> [<800086a4>] (do_one_initcall+0x0/0x184) from [<8053e974>] (kernel_init+0x104/0x1c8)
> [<8053e870>] (kernel_init+0x0/0x1c8) from [<80026750>] (do_exit+0x0/0x7fc)
> Code: e3a02000 e1a00007 eb03f8db e3a020d0 (e5903004)
>
> Signed-off-by: Frank Li <Frank.Li@freescale.com>
> ---
> drivers/regulator/gpio-regulator.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/regulator/gpio-regulator.c b/drivers/regulator/gpio-regulator.c
> index e467d0a..b51e757 100644
> --- a/drivers/regulator/gpio-regulator.c
> +++ b/drivers/regulator/gpio-regulator.c
> @@ -183,7 +183,7 @@ of_get_gpio_regulator_config(struct device *dev, struct device_node *np)
>
> /* Fetch states. */
> prop = of_find_property(np, "states", NULL);
> - proplen = prop->length / sizeof(int);
> + proplen = prop ? prop->length / sizeof(int) : 0;
>
> config->states = devm_kzalloc(dev,
> sizeof(struct gpio_regulator_state)
I agree that this should fail more gracfully, but a state should
be compulsary. If you can't change the value of either state you
should be using a fixed regulator.
I'll submit a patch.
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH V2 2/5] arm: mvebu: Added initial support for power managmement service unit
From: Will Deacon @ 2012-11-14 9:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121114000736.GE3290@n2100.arm.linux.org.uk>
On Wed, Nov 14, 2012 at 12:07:36AM +0000, Russell King - ARM Linux wrote:
> On Mon, Nov 05, 2012 at 02:05:58PM +0000, Will Deacon wrote:
> > On Mon, Oct 29, 2012 at 09:11:45PM +0000, Gregory CLEMENT wrote:
> > > + /* Make sure value hits memory before reset */
> > > + dsb();
> >
> > writel has barrier semantics -- you shouldn't need this dsb.
>
> writel has a barrier before the write (to ensure that DMA agents see data
> that was written to memory when they are enabled by the write). There
> isn't a barrier after the write.
Indeed, but there's a following write to actually do the reset, so the dsb
should come from there.
Will
^ permalink raw reply
* [PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ
From: Will Deacon @ 2012-11-14 9:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0154077FE026E54BB093CA7EB3FD1AE32B57AF1E29@SAFEX1MAIL3.st.com>
On Wed, Nov 14, 2012 at 09:18:31AM +0000, Etienne CARRIERE ST wrote:
> This is why the mutex added for TZ shared of L2 cache maintenance is a "arch_spinlock". It assumes linux handles the spinlock as a native ARM native mutex DDR cell, handled from the ARMv7-A LDREX/STREX.
> I think this is the weakest part of the driver since they is no insurance that linux pristine arch_spinlock will not evolve into something else (i.e features in raw_spinclock).
How does this work with our ticket lock approach? Can you swizzle your
locking implementation by inspecting the kernel version of the code running
on the non-secure side? (I sincerely hope not...)
Will
^ permalink raw reply
* [PATCH v4 2/2] ARM: OMAP3/4: iommu: adapt to runtime pm
From: Ohad Ben-Cohen @ 2012-11-14 9:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352860489-19960-3-git-send-email-omar.luna@linaro.org>
Hi Omar,
On Wed, Nov 14, 2012 at 4:34 AM, Omar Ramirez Luna <omar.luna@linaro.org> wrote:
> Use runtime PM functionality interfaced with hwmod enable/idle
> functions, to replace direct clock operations and sysconfig
> handling.
>
> Dues to reset sequence, pm_runtime_put_sync must be used, to avoid
> possible operations with the module under reset.
There are some changes here that might not be trivial to understand in
hindsight; any chance you can add more explanations (even only in the
commit log) regarding:
> @@ -160,11 +160,10 @@ static int iommu_enable(struct omap_iommu *obj)
...
> - clk_enable(obj->clk);
> + pm_runtime_get_sync(obj->dev);
>
> err = arch_iommu->enable(obj);
>
> - clk_disable(obj->clk);
> return err;
> }
Why do we remove clk_disable here (instead of replacing it with a _put
variant) ?
> @@ -306,7 +303,7 @@ static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
> if (!obj || !obj->nr_tlb_entries || !e)
> return -EINVAL;
>
> - clk_enable(obj->clk);
> + pm_runtime_get_sync(obj->dev);
If iommu_enable no longer disables obj->clk before returning, do we
really need to call ->get here (and in all the other similar
instances) ?
> @@ -816,9 +813,7 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
> if (!obj->refcount)
> return IRQ_NONE;
>
> - clk_enable(obj->clk);
> errs = iommu_report_fault(obj, &da);
> - clk_disable(obj->clk);
Why do we remove the clk_ invocations here (instead of replacing them
with get/put variants) ?
Most of the above questions imply this patch not only converts the
iommu to runtime PM, but may carry additional changes that may imply
previous implementation is sub-optimal. I hope we can clearly document
the motivation behind these changes too (maybe even consider
extracting them to a different patch ?).
> @@ -990,6 +981,9 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev)
> goto err_irq;
> platform_set_drvdata(pdev, obj);
>
> + pm_runtime_irq_safe(obj->dev);
Let's also document why _irq_safe is needed here ?
Thanks,
Ohad.
^ permalink raw reply
* OMAP* Latest build failures
From: Peter Ujfalusi @ 2012-11-14 10:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121114092643.GG3290@n2100.arm.linux.org.uk>
Hi Russell,
On 11/14/2012 10:26 AM, Russell King - ARM Linux wrote:
> OMAP* allnoconfig fails:
>
> arch/arm/mach-omap2/built-in.o: In function `omap_dss_set_min_bus_tput':
> twl-common.c:(.text+0x1e08): undefined reference to `omap_pm_set_min_bus_tput'
> arch/arm/mach-omap2/built-in.o: In function `omap_hwmod_init_postsetup':
> twl-common.c:(.init.text+0x8f8): undefined reference to `omap_pm_if_early_init'
> arch/arm/mach-omap2/built-in.o: In function `omap_serial_init_port':
> twl-common.c:(.init.text+0x1284): undefined reference to `omap_pm_get_dev_context_loss_count'
> arch/arm/mach-omap2/built-in.o: In function `omap_timer_init':
> twl-common.c:(.init.text+0x1544): undefined reference to `omap_pm_get_dev_context_loss_count'
> arch/arm/mach-omap2/built-in.o: In function `omap2_common_pm_init':
> twl-common.c:(.init.text+0x1af0): undefined reference to `omap_pm_if_init'
> arch/arm/mach-omap2/built-in.o: In function `omap2_gpio_dev_init':
> twl-common.c:(.init.text+0x2168): undefined reference to `omap_pm_get_dev_context_loss_count'
> arch/arm/mach-omap2/built-in.o: In function `omap_display_init':
> twl-common.c:(.init.text+0x25cc): undefined reference to `omap_pm_get_dev_context_loss_count'
Not sure what is going on here but neither of these are referenced within
twl-common.c directly.
> OMAP4 randconfig fails:
>
> arch/arm/mach-omap2/cm_common.c: In function 'cm_register':
> arch/arm/mach-omap2/cm_common.c:42:11: error: 'EINVAL' undeclared (first use in this function)
> arch/arm/mach-omap2/cm_common.c:45:11: error: 'EEXIST' undeclared (first use in this function)
> arch/arm/mach-omap2/cm_common.c: In function 'cm_unregister':
> arch/arm/mach-omap2/cm_common.c:66:11: error: 'EINVAL' undeclared (first use in this function)
I have already sent a patch to fix this:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-November/131341.html
> You know where to find the build information and results...
It seams I can not find the link in my mail archives. Could you point me to
the correct place?
--
P?ter
^ permalink raw reply
* [PATCH 1/4] mfd: tps65217: Set PMIC to shutdowm on PWR_EN toggle
From: Benoit Cousson @ 2012-11-14 10:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121114070046.GE7407@opensource.wolfsonmicro.com>
Hi Mark,
On 11/14/2012 08:00 AM, Mark Brown wrote:
> On Wed, Nov 14, 2012 at 06:49:58AM +0000, AnilKumar, Chimata wrote:
>
>> Earlier you have a comment on this thread, I am adding my comments
>> on top of it. Sorry if I am in wrong direction.
>
> Ah, I see. I was just commenting because Benoit was asking if this
> should be supported with a standard framework feature - I'm not
> convinced that it should right now as there's not any clear patterns in
> hardware behaviour. I've no specific interest in this system.
I was wondering that, because exposing a pin to control the whole PMIC
low power mode seems to be something that should be generic enough to be
handled by the regulator framework.
In the current situation we do have a pwr_en pin that can be controlled
by a GPIO or whatever signal from the SoC.
That's very similar, at PMIC level, to the fixedregulator that allow a
GPIO binding to enable it.
Don't you think that should deserve a support in the fmwk?
Regards,
Benoit
^ permalink raw reply
* [Patch v6 0/4] ASoC: atmel-ssc: Add pinctrl support and change register method
From: Bo Shen @ 2012-11-14 10:09 UTC (permalink / raw)
To: linux-arm-kernel
This patch set is based on linux next master branch
The detail information as following:
Git: git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
Branch: master
Commit ID: 75e0ebabd87048b91e4189b90d4af8ef565115db
Detail information about implement as following:
- atmel ssc: add pinctrl support
- atmel ssc dai: register dai and pcm directly
- at91sam9g20ek wm8731: match new method of dai and pcm register
- at91sam9g20ek wm8731: convert to dt support
Bo Shen (4):
ARM: at91: atmel-ssc: add pinctrl support
ASoC: atmel-ssc-dai: register dai and pcm directly
ASoC: atmel-ssc-dai: match new method of dai and pcm register
ASoC: at91sam9g20ek-wm8731: convert to dt support
.../sound/atmel-at91sam9g20ek-wm8731-audio.txt | 26 ++++
arch/arm/boot/dts/at91sam9260.dtsi | 18 +++
arch/arm/boot/dts/at91sam9263.dtsi | 36 +++++
arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 32 +++-
arch/arm/boot/dts/at91sam9g45.dtsi | 36 +++++
arch/arm/boot/dts/at91sam9n12.dtsi | 26 ++++
arch/arm/boot/dts/at91sam9x5.dtsi | 32 +++-
arch/arm/mach-at91/at91sam9260_devices.c | 9 --
arch/arm/mach-at91/board-sam9g20ek.c | 6 -
drivers/misc/atmel-ssc.c | 8 +
sound/soc/atmel/Kconfig | 3 +-
sound/soc/atmel/atmel-pcm.c | 23 +--
sound/soc/atmel/atmel-pcm.h | 3 +
sound/soc/atmel/atmel_ssc_dai.c | 157 +++++---------------
sound/soc/atmel/atmel_ssc_dai.h | 3 +-
sound/soc/atmel/sam9g20_wm8731.c | 75 +++++++++-
16 files changed, 328 insertions(+), 165 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt
--
1.7.9.5
^ permalink raw reply
* [Patch v6 1/4] ARM: at91: atmel-ssc: add pinctrl support
From: Bo Shen @ 2012-11-14 10:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352887751-21848-1-git-send-email-voice.shen@atmel.com>
Add pinctrl support for atmel ssc peripheral
Signed-off-by: Bo Shen <voice.shen@atmel.com>
---
Change since v5
- correct the pull setting, without pull up
Change since v4
- This is initial version
---
arch/arm/boot/dts/at91sam9260.dtsi | 18 ++++++++++++++++++
arch/arm/boot/dts/at91sam9263.dtsi | 36 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9g45.dtsi | 36 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9n12.dtsi | 26 ++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9x5.dtsi | 32 +++++++++++++++++++++++++-------
drivers/misc/atmel-ssc.c | 8 ++++++++
6 files changed, 149 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 3164dcd..f9dc7db 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -217,6 +217,22 @@
};
};
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <1 16 0x1 0x0 /* PB16 periph A */
+ 1 17 0x1 0x0 /* PB17 periph A */
+ 1 18 0x1 0x0>; /* PB18 periph A */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <1 19 0x1 0x0 /* PB19 periph A */
+ 1 20 0x1 0x0 /* PB20 periph A */
+ 1 21 0x1 0x0>; /* PB21 periph A */
+ };
+ };
+
pioA: gpio at fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
@@ -350,6 +366,8 @@
compatible = "atmel,at91rm9200-ssc";
reg = <0xfffbc000 0x4000>;
interrupts = <14 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
status = "disable";
};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 96e0bc9..6e9a4ff 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -165,6 +165,38 @@
};
};
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <1 0 0x2 0x0 /* PB0 periph B */
+ 1 1 0x2 0x0 /* PB1 periph B */
+ 1 2 0x2 0x0>; /* PB2 periph B */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <1 3 0x2 0x0 /* PB3 periph B */
+ 1 4 0x2 0x0 /* PB4 periph B */
+ 1 5 0x2 0x0>; /* PB5 periph B */
+ };
+ };
+
+ ssc1 {
+ pinctrl_ssc1_tx: ssc1_tx-0 {
+ atmel,pins =
+ <1 6 0x1 0x0 /* PB6 periph A */
+ 1 7 0x1 0x0 /* PB7 periph A */
+ 1 8 0x1 0x0>; /* PB8 periph A */
+ };
+
+ pinctrl_ssc1_rx: ssc1_rx-0 {
+ atmel,pins =
+ <1 9 0x1 0x0 /* PB9 periph A */
+ 1 10 0x1 0x0 /* PB10 periph A */
+ 1 11 0x1 0x0>; /* PB11 periph A */
+ };
+ };
+
pioA: gpio at fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>;
@@ -262,6 +294,8 @@
compatible = "atmel,at91rm9200-ssc";
reg = <0xfff98000 0x4000>;
interrupts = <16 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
status = "disable";
};
@@ -269,6 +303,8 @@
compatible = "atmel,at91rm9200-ssc";
reg = <0xfff9c000 0x4000>;
interrupts = <17 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
status = "disable";
};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index c40c3eb..63cf206 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -198,6 +198,38 @@
};
};
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <3 0 0x1 0x0 /* PD0 periph A */
+ 3 1 0x1 0x0 /* PD1 periph A */
+ 3 2 0x1 0x0>; /* PD2 periph A */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <3 3 0x1 0x0 /* PD3 periph A */
+ 3 4 0x1 0x0 /* PD4 periph A */
+ 3 5 0x1 0x0>; /* PD5 periph A */
+ };
+ };
+
+ ssc1 {
+ pinctrl_ssc1_tx: ssc1_tx-0 {
+ atmel,pins =
+ <3 10 0x1 0x0 /* PD10 periph A */
+ 3 11 0x1 0x0 /* PD11 periph A */
+ 3 12 0x1 0x0>; /* PD12 periph A */
+ };
+
+ pinctrl_ssc1_rx: ssc1_rx-0 {
+ atmel,pins =
+ <3 13 0x1 0x0 /* PD13 periph A */
+ 3 14 0x1 0x0 /* PD14 periph A */
+ 3 15 0x1 0x0>; /* PD15 periph A */
+ };
+ };
+
pioA: gpio at fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>;
@@ -331,6 +363,8 @@
compatible = "atmel,at91sam9g45-ssc";
reg = <0xfff9c000 0x4000>;
interrupts = <16 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
status = "disable";
};
@@ -338,6 +372,8 @@
compatible = "atmel,at91sam9g45-ssc";
reg = <0xfffa0000 0x4000>;
interrupts = <17 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
status = "disable";
};
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 7b644c5..de0cb81 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -28,6 +28,7 @@
tcb1 = &tcb1;
i2c0 = &i2c0;
i2c1 = &i2c1;
+ ssc0 = &ssc0;
};
cpus {
cpu at 0 {
@@ -199,6 +200,22 @@
};
};
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <0 24 0x1 0x0 /* PA24 periph A */
+ 0 25 0x1 0x0 /* PA25 periph A */
+ 0 26 0x1 0x0>; /* PA26 periph A */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <0 27 0x1 0x0 /* PA27 periph A */
+ 0 28 0x1 0x0 /* PA28 periph A */
+ 0 29 0x1 0x0>; /* PA29 periph A */
+ };
+ };
+
pioA: gpio at fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
@@ -249,6 +266,15 @@
status = "disabled";
};
+ ssc0: ssc at f0010000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0xf0010000 0x4000>;
+ interrupts = <28 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ status = "disable";
+ };
+
usart0: serial at f801c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf801c000 0x4000>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1cb26c28..d9014e5 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -88,13 +88,6 @@
interrupts = <1 4 7>;
};
- ssc0: ssc at f0010000 {
- compatible = "atmel,at91sam9g45-ssc";
- reg = <0xf0010000 0x4000>;
- interrupts = <28 4 5>;
- status = "disable";
- };
-
tcb0: timer at f8008000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
@@ -214,6 +207,22 @@
};
};
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <0 24 0x1 0x0 /* PA24 periph A */
+ 0 25 0x1 0x0 /* PA25 periph A */
+ 0 26 0x1 0x0>; /* PA26 periph A */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <0 27 0x1 0x0 /* PA27 periph A */
+ 0 28 0x1 0x0 /* PA28 periph A */
+ 0 29 0x1 0x0>; /* PA29 periph A */
+ };
+ };
+
pioA: gpio at fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
@@ -266,6 +275,15 @@
status = "disabled";
};
+ ssc0: ssc at f0010000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0xf0010000 0x4000>;
+ interrupts = <28 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ status = "disable";
+ };
+
usart0: serial at f801c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf801c000 0x200>;
diff --git a/drivers/misc/atmel-ssc.c b/drivers/misc/atmel-ssc.c
index a769719..3b3d0e0 100644
--- a/drivers/misc/atmel-ssc.c
+++ b/drivers/misc/atmel-ssc.c
@@ -19,6 +19,7 @@
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/pinctrl/consumer.h>
/* Serialize access to ssc_list and user count */
static DEFINE_SPINLOCK(user_lock);
@@ -131,6 +132,13 @@ static int ssc_probe(struct platform_device *pdev)
struct resource *regs;
struct ssc_device *ssc;
const struct atmel_ssc_platform_data *plat_dat;
+ struct pinctrl *pinctrl;
+
+ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+ if (IS_ERR(pinctrl)) {
+ dev_err(&pdev->dev, "Failed to request pinctrl\n");
+ return PTR_ERR(pinctrl);
+ }
ssc = devm_kzalloc(&pdev->dev, sizeof(struct ssc_device), GFP_KERNEL);
if (!ssc) {
--
1.7.9.5
^ permalink raw reply related
* [Patch v6 2/4] ASoC: atmel-ssc-dai: register dai and pcm directly
From: Bo Shen @ 2012-11-14 10:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352887751-21848-1-git-send-email-voice.shen@atmel.com>
change the method for register dai and pcm
- let the atmel-ssc-dai no longer as a standalone platform device
- remap ssc and then register dai directly
- register pcm from dai directly
- modify the code which related with this change
Signed-off-by: Bo Shen <voice.shen@atmel.com>
---
Change since v5
- split the patch, this only include register method change
- fix the backwards
Change since v4 RFC
- no change
Change since v3 RFC
- remap ssc and then register dai and pcm directly
Change since v2
- Register dai and pcm directly according to Mark Brown's suggestion
- using name to distinguish ssc register for audio or library
if for audio, the name with dai subfix
if for library, the name without dai subfix
- fix the issue for sam9g20-wm8731
- when register dai and pcm cause the sam9g20-wm8731 doesn't work,
so fix it
- Add device tree support
- Detail information reference atmel-ssc-dai.txt binding document
Change since v1
No change
---
sound/soc/atmel/atmel-pcm.c | 23 ++----
sound/soc/atmel/atmel-pcm.h | 3 +
sound/soc/atmel/atmel_ssc_dai.c | 157 ++++++++++-----------------------------
sound/soc/atmel/atmel_ssc_dai.h | 3 +-
4 files changed, 50 insertions(+), 136 deletions(-)
diff --git a/sound/soc/atmel/atmel-pcm.c b/sound/soc/atmel/atmel-pcm.c
index 9b84f98..40e17d1 100644
--- a/sound/soc/atmel/atmel-pcm.c
+++ b/sound/soc/atmel/atmel-pcm.c
@@ -473,28 +473,17 @@ static struct snd_soc_platform_driver atmel_soc_platform = {
.resume = atmel_pcm_resume,
};
-static int __devinit atmel_soc_platform_probe(struct platform_device *pdev)
+int atmel_pcm_platform_register(struct device *dev)
{
- return snd_soc_register_platform(&pdev->dev, &atmel_soc_platform);
+ return snd_soc_register_platform(dev, &atmel_soc_platform);
}
+EXPORT_SYMBOL(atmel_pcm_platform_register);
-static int __devexit atmel_soc_platform_remove(struct platform_device *pdev)
+void atmel_pcm_platform_unregister(struct device *dev)
{
- snd_soc_unregister_platform(&pdev->dev);
- return 0;
+ snd_soc_unregister_platform(dev);
}
-
-static struct platform_driver atmel_pcm_driver = {
- .driver = {
- .name = "atmel-pcm-audio",
- .owner = THIS_MODULE,
- },
-
- .probe = atmel_soc_platform_probe,
- .remove = __devexit_p(atmel_soc_platform_remove),
-};
-
-module_platform_driver(atmel_pcm_driver);
+EXPORT_SYMBOL(atmel_pcm_platform_unregister);
MODULE_AUTHOR("Sedji Gaouaou <sedji.gaouaou@atmel.com>");
MODULE_DESCRIPTION("Atmel PCM module");
diff --git a/sound/soc/atmel/atmel-pcm.h b/sound/soc/atmel/atmel-pcm.h
index 5e0a95e..e6d67b3 100644
--- a/sound/soc/atmel/atmel-pcm.h
+++ b/sound/soc/atmel/atmel-pcm.h
@@ -80,4 +80,7 @@ struct atmel_pcm_dma_params {
#define ssc_readx(base, reg) (__raw_readl((base) + (reg)))
#define ssc_writex(base, reg, value) __raw_writel((value), (base) + (reg))
+int atmel_pcm_platform_register(struct device *dev);
+void atmel_pcm_platform_unregister(struct device *dev);
+
#endif /* _ATMEL_PCM_H */
diff --git a/sound/soc/atmel/atmel_ssc_dai.c b/sound/soc/atmel/atmel_ssc_dai.c
index 354341e..7932c05 100644
--- a/sound/soc/atmel/atmel_ssc_dai.c
+++ b/sound/soc/atmel/atmel_ssc_dai.c
@@ -48,11 +48,7 @@
#include "atmel_ssc_dai.h"
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
-#define NUM_SSC_DEVICES 1
-#else
#define NUM_SSC_DEVICES 3
-#endif
/*
* SSC PDC registers required by the PCM DMA engine.
@@ -107,7 +103,6 @@ static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
.pdc = &pdc_rx_reg,
.mask = &ssc_rx_mask,
} },
-#if NUM_SSC_DEVICES == 3
{{
.name = "SSC1 PCM out",
.pdc = &pdc_tx_reg,
@@ -128,7 +123,6 @@ static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
.pdc = &pdc_rx_reg,
.mask = &ssc_rx_mask,
} },
-#endif
};
@@ -139,7 +133,6 @@ static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
.dir_mask = SSC_DIR_MASK_UNUSED,
.initialized = 0,
},
-#if NUM_SSC_DEVICES == 3
{
.name = "ssc1",
.lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
@@ -152,7 +145,6 @@ static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
.dir_mask = SSC_DIR_MASK_UNUSED,
.initialized = 0,
},
-#endif
};
@@ -690,27 +682,9 @@ static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
static int atmel_ssc_probe(struct snd_soc_dai *dai)
{
struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
- int ret = 0;
snd_soc_dai_set_drvdata(dai, ssc_p);
- /*
- * Request SSC device
- */
- ssc_p->ssc = ssc_request(dai->id);
- if (IS_ERR(ssc_p->ssc)) {
- printk(KERN_ERR "ASoC: Failed to request SSC %d\n", dai->id);
- ret = PTR_ERR(ssc_p->ssc);
- }
-
- return ret;
-}
-
-static int atmel_ssc_remove(struct snd_soc_dai *dai)
-{
- struct atmel_ssc_info *ssc_p = snd_soc_dai_get_drvdata(dai);
-
- ssc_free(ssc_p->ssc);
return 0;
}
@@ -728,48 +702,8 @@ static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
.set_clkdiv = atmel_ssc_set_dai_clkdiv,
};
-static struct snd_soc_dai_driver atmel_ssc_dai[NUM_SSC_DEVICES] = {
- {
- .name = "atmel-ssc-dai.0",
- .probe = atmel_ssc_probe,
- .remove = atmel_ssc_remove,
- .suspend = atmel_ssc_suspend,
- .resume = atmel_ssc_resume,
- .playback = {
- .channels_min = 1,
- .channels_max = 2,
- .rates = ATMEL_SSC_RATES,
- .formats = ATMEL_SSC_FORMATS,},
- .capture = {
- .channels_min = 1,
- .channels_max = 2,
- .rates = ATMEL_SSC_RATES,
- .formats = ATMEL_SSC_FORMATS,},
- .ops = &atmel_ssc_dai_ops,
- },
-#if NUM_SSC_DEVICES == 3
- {
- .name = "atmel-ssc-dai.1",
- .probe = atmel_ssc_probe,
- .remove = atmel_ssc_remove,
- .suspend = atmel_ssc_suspend,
- .resume = atmel_ssc_resume,
- .playback = {
- .channels_min = 1,
- .channels_max = 2,
- .rates = ATMEL_SSC_RATES,
- .formats = ATMEL_SSC_FORMATS,},
- .capture = {
- .channels_min = 1,
- .channels_max = 2,
- .rates = ATMEL_SSC_RATES,
- .formats = ATMEL_SSC_FORMATS,},
- .ops = &atmel_ssc_dai_ops,
- },
- {
- .name = "atmel-ssc-dai.2",
+static struct snd_soc_dai_driver atmel_ssc_dai = {
.probe = atmel_ssc_probe,
- .remove = atmel_ssc_remove,
.suspend = atmel_ssc_suspend,
.resume = atmel_ssc_resume,
.playback = {
@@ -783,32 +717,37 @@ static struct snd_soc_dai_driver atmel_ssc_dai[NUM_SSC_DEVICES] = {
.rates = ATMEL_SSC_RATES,
.formats = ATMEL_SSC_FORMATS,},
.ops = &atmel_ssc_dai_ops,
- },
-#endif
};
-static __devinit int asoc_ssc_probe(struct platform_device *pdev)
+static int asoc_ssc_init(struct device *dev)
{
- BUG_ON(pdev->id < 0);
- BUG_ON(pdev->id >= ARRAY_SIZE(atmel_ssc_dai));
- return snd_soc_register_dai(&pdev->dev, &atmel_ssc_dai[pdev->id]);
-}
+ int ret;
+
+ ret = snd_soc_register_dai(dev, &atmel_ssc_dai);
+ if (ret) {
+ dev_err(dev, "Could not register DAI: %d\n", ret);
+ goto err;
+ }
+
+ ret = atmel_pcm_platform_register(dev);
+ if (ret) {
+ dev_err(dev, "Could not register PCM: %d\n", ret);
+ goto err_unregister_dai;
+ };
-static int __devexit asoc_ssc_remove(struct platform_device *pdev)
-{
- snd_soc_unregister_dai(&pdev->dev);
return 0;
-}
-static struct platform_driver asoc_ssc_driver = {
- .driver = {
- .name = "atmel-ssc-dai",
- .owner = THIS_MODULE,
- },
+err_unregister_dai:
+ snd_soc_unregister_dai(dev);
+err:
+ return ret;
+}
- .probe = asoc_ssc_probe,
- .remove = __devexit_p(asoc_ssc_remove),
-};
+static void asoc_ssc_exit(struct device *dev)
+{
+ atmel_pcm_platform_unregister(dev);
+ snd_soc_unregister_dai(dev);
+}
/**
* atmel_ssc_set_audio - Allocate the specified SSC for audio use.
@@ -816,50 +755,32 @@ static struct platform_driver asoc_ssc_driver = {
int atmel_ssc_set_audio(int ssc_id)
{
struct ssc_device *ssc;
- static struct platform_device *dma_pdev;
- struct platform_device *ssc_pdev;
int ret;
- if (ssc_id < 0 || ssc_id >= ARRAY_SIZE(atmel_ssc_dai))
- return -EINVAL;
-
- /* Allocate a dummy device for DMA if we don't have one already */
- if (!dma_pdev) {
- dma_pdev = platform_device_alloc("atmel-pcm-audio", -1);
- if (!dma_pdev)
- return -ENOMEM;
-
- ret = platform_device_add(dma_pdev);
- if (ret < 0) {
- platform_device_put(dma_pdev);
- dma_pdev = NULL;
- return ret;
- }
- }
-
- ssc_pdev = platform_device_alloc("atmel-ssc-dai", ssc_id);
- if (!ssc_pdev)
- return -ENOMEM;
-
/* If we can grab the SSC briefly to parent the DAI device off it */
ssc = ssc_request(ssc_id);
- if (IS_ERR(ssc))
- pr_warn("Unable to parent ASoC SSC DAI on SSC: %ld\n",
+ if (IS_ERR(ssc)) {
+ pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
PTR_ERR(ssc));
- else {
- ssc_pdev->dev.parent = &(ssc->pdev->dev);
- ssc_free(ssc);
+ return PTR_ERR(ssc);
+ } else {
+ ssc_info[ssc_id].ssc = ssc;
}
- ret = platform_device_add(ssc_pdev);
- if (ret < 0)
- platform_device_put(ssc_pdev);
+ ret = asoc_ssc_init(&ssc->pdev->dev);
return ret;
}
EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
-module_platform_driver(asoc_ssc_driver);
+void atmel_ssc_put_audio(int ssc_id)
+{
+ struct ssc_device *ssc = ssc_info[ssc_id].ssc;
+
+ ssc_free(ssc);
+ asoc_ssc_exit(&ssc->pdev->dev);
+}
+EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
/* Module information */
MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou at atmel.com, www.atmel.com");
diff --git a/sound/soc/atmel/atmel_ssc_dai.h b/sound/soc/atmel/atmel_ssc_dai.h
index 5d4f0f9..b1f08d5 100644
--- a/sound/soc/atmel/atmel_ssc_dai.h
+++ b/sound/soc/atmel/atmel_ssc_dai.h
@@ -117,6 +117,7 @@ struct atmel_ssc_info {
struct atmel_ssc_state ssc_state;
};
-int atmel_ssc_set_audio(int ssc);
+int atmel_ssc_set_audio(int ssc_id);
+void atmel_ssc_put_audio(int ssc_id);
#endif /* _AT91_SSC_DAI_H */
--
1.7.9.5
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