* [PATCH v5 0/10] use pinctrl-single in arch mmp
From: Haojian Zhuang @ 2012-11-15 8:36 UTC (permalink / raw)
To: linux-arm-kernel
Changelog:
v5:
1. Move the properties of pinconf into pin group. So those mask
properties could be merged with other pinconf properties.
2. Append lookup pinctrl map method.
3. Append input schmitt disable config parameter.
4. Clean code.
v4:
1. Define gpio range as sub-node, not label. And remove
pinctrl-single,gpio-ranges property.
2. Use new two properties in sub-node, reg &
pinctrl-single,gpio. GPIO number & GPIO function are listed in
the pinctrl-single,gpio property.
3. Reference the names like pinctrl-single,bias.
4. Add compatible name "pinconf-single". If the compatible name is
"pinctrl-single", there's no pinconf. If the compatible name is
"pinconf-single", there's the generic pinconf in pinctrl-single.
5. Update documents.
v3:
1. Add more comments in document.
2. Replace pcs_readl() & pcs_writel() by pcs->read() & pcs->write().
3. Clean code.
v2:
1. Remove "pinctrl-single,gpio-mask". Since GPIO function is one of the
mux function in the pinmux register of both OMAP and PXA/MMP silicons.
Use "pinctrl-single,function-mask" instead.
2. Remove "pinctrl-single,gpio-enable" & "pinctrl-single,gpio-disable".
Use "pinctrl-single,gpio-func" instead. Because GPIO mode is only one
of the mux functions in the pinmux register. Defining "gpio-enable" &
"gpio-disable" are redundant.
3. Define register with __iomem, not u32 type.
4. Remove "pinctrl-single,input-schmit-shift",
"pinctrl-single,power-source-shift", "pinctrl-single,bias-shift". All
these properties could be calculated by mask fields.
5. Return -EPROBE_DEFER if pinmux could be got in device driver. And
the device driver would be probed again deferred.
^ permalink raw reply
* [PATCH v5 01/10] ARM: mmp: select pinctrl driver
From: Haojian Zhuang @ 2012-11-15 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352968600-15345-1-git-send-email-haojian.zhuang@gmail.com>
Pinctrl driver is necessary for MMP DT & MMP2 DT platforms.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-mmp/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 178d4da..ebdda83 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -89,6 +89,8 @@ config MACH_MMP_DT
select CPU_PXA168
select CPU_PXA910
select USE_OF
+ select PINCTRL
+ select PINCTRL_SINGLE
help
Include support for Marvell MMP2 based platforms using
the device tree. Needn't select any other machine while
@@ -99,6 +101,8 @@ config MACH_MMP2_DT
depends on !CPU_MOHAWK
select CPU_MMP2
select USE_OF
+ select PINCTRL
+ select PINCTRL_SINGLE
help
Include support for Marvell MMP2 based platforms using
the device tree.
--
1.7.10.4
^ permalink raw reply related
* [PATCH v5 02/10] pinctrl: single: support gpio request and free
From: Haojian Zhuang @ 2012-11-15 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352968600-15345-1-git-send-email-haojian.zhuang@gmail.com>
Marvell's PXA/MMP silicon also match the behavior of pinctrl-single.
Each pin binds to one register. A lot of pins could be configured
as gpio.
GPIO range is defined as a child node of pinmux in .dtsi file. If those
pins are with the same gpio function configuration in the pinmux
register, they could be defined in the same GPIO range. For this new
child node, two properties are used.
reg = <the start of pinmux register in range, size of range>
pinctrl-single,gpio: <gpio base in range, the gpio function of the range
in the pinmux register>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
drivers/pinctrl/pinctrl-single.c | 80 +++++++++++++++++++++++++++++++++++++-
1 file changed, 78 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 726a729..2476a68 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -30,6 +30,7 @@
#define PCS_MUX_BITS_NAME "pinctrl-single,bits"
#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1)
#define PCS_OFF_DISABLED ~0U
+#define PCS_MAX_GPIO_VALUES 2
/**
* struct pcs_pingroup - pingroups for a function
@@ -77,6 +78,16 @@ struct pcs_function {
};
/**
+ * struct pcs_gpio_range - pinctrl gpio range
+ * @range: subrange of the GPIO number space
+ * @gpio_func: gpio function value in the pinmux register
+ */
+struct pcs_gpio_range {
+ struct pinctrl_gpio_range range;
+ int gpio_func;
+};
+
+/**
* struct pcs_data - wrapper for data needed by pinctrl framework
* @pa: pindesc array
* @cur: index to current element
@@ -403,9 +414,26 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
}
static int pcs_request_gpio(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range, unsigned offset)
+ struct pinctrl_gpio_range *range, unsigned pin)
{
- return -ENOTSUPP;
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ struct pcs_gpio_range *gpio = NULL;
+ int end, mux_bytes;
+ unsigned data;
+
+ gpio = container_of(range, struct pcs_gpio_range, range);
+ end = range->pin_base + range->npins - 1;
+ if (pin < range->pin_base || pin > end) {
+ dev_err(pctldev->dev,
+ "pin %d isn't in the range of %d to %d\n",
+ pin, range->pin_base, end);
+ return -EINVAL;
+ }
+ mux_bytes = pcs->width / BITS_PER_BYTE;
+ data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
+ data |= gpio->gpio_func;
+ pcs->write(data, pcs->base + pin * mux_bytes);
+ return 0;
}
static struct pinmux_ops pcs_pinmux_ops = {
@@ -879,6 +907,50 @@ static void pcs_free_resources(struct pcs_device *pcs)
static struct of_device_id pcs_of_match[];
+static int __devinit pcs_add_gpio_range(struct device_node *node,
+ struct pcs_device *pcs)
+{
+ struct pcs_gpio_range *gpio;
+ struct device_node *child;
+ struct resource r;
+ const char name[] = "pinctrl-single";
+ u32 gpiores[PCS_MAX_GPIO_VALUES];
+ int ret, i = 0, mux_bytes = 0;
+
+ for_each_child_of_node(node, child) {
+ ret = of_address_to_resource(child, 0, &r);
+ if (ret < 0)
+ continue;
+ memset(gpiores, 0, sizeof(u32) * PCS_MAX_GPIO_VALUES);
+ ret = of_property_read_u32_array(child, "pinctrl-single,gpio",
+ gpiores, PCS_MAX_GPIO_VALUES);
+ if (ret < 0)
+ continue;
+ gpio = devm_kzalloc(pcs->dev, sizeof(*gpio), GFP_KERNEL);
+ if (!gpio) {
+ dev_err(pcs->dev, "failed to allocate pcs gpio\n");
+ return -ENOMEM;
+ }
+ gpio->range.name = devm_kzalloc(pcs->dev, sizeof(name),
+ GFP_KERNEL);
+ if (!gpio->range.name) {
+ dev_err(pcs->dev, "failed to allocate range name\n");
+ return -ENOMEM;
+ }
+ memcpy((char *)gpio->range.name, name, sizeof(name));
+
+ gpio->range.id = i++;
+ gpio->range.base = gpiores[0];
+ gpio->gpio_func = gpiores[1];
+ mux_bytes = pcs->width / BITS_PER_BYTE;
+ gpio->range.pin_base = (r.start - pcs->res->start) / mux_bytes;
+ gpio->range.npins = (r.end - r.start) / mux_bytes + 1;
+
+ pinctrl_add_gpio_range(pcs->pctl, &gpio->range);
+ }
+ return 0;
+}
+
static int __devinit pcs_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -975,6 +1047,10 @@ static int __devinit pcs_probe(struct platform_device *pdev)
goto free;
}
+ ret = pcs_add_gpio_range(np, pcs);
+ if (ret < 0)
+ goto free;
+
dev_info(pcs->dev, "%i pins at pa %p size %u\n",
pcs->desc.npins, pcs->base, pcs->size);
--
1.7.10.4
^ permalink raw reply related
* [PATCH v5 03/10] pinctrl: append method of lookup pinctrl map
From: Haojian Zhuang @ 2012-11-15 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352968600-15345-1-git-send-email-haojian.zhuang@gmail.com>
pinctrl driver gets pinctrl map if both group and map type is specified.
In pinctrl-single driver, each pin group is defined in DT file. The pinconf
information is also defined in each pin group.
pinctrl-single driver could store those mask/shift/value information
into pinctrl map. pinconf_get()/pinconf_set() and
pinconf_group_get()/pinconf_group_set() could get those information from
pinctrl map.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
drivers/pinctrl/core.c | 24 ++++++++++++++++++++++++
include/linux/pinctrl/consumer.h | 4 ++++
2 files changed, 28 insertions(+)
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 2e39c04..0d36270 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -839,6 +839,30 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
}
EXPORT_SYMBOL_GPL(pinctrl_select_state);
+const struct pinctrl_map *pinctrl_lookup_map(struct pinctrl *p,
+ const char *name, unsigned type)
+{
+ struct pinctrl_maps *maps_node;
+ struct pinctrl_map const *map;
+ int i;
+
+ for_each_maps(maps_node, i, map) {
+ /* Map must be for this device */
+ if (strcmp(map->ctrl_dev_name, dev_name(p->dev)))
+ continue;
+ if (map->type != type)
+ continue;
+ if (map->type == PIN_MAP_TYPE_MUX_GROUP)
+ if (!strcmp(map->data.mux.group, name))
+ return map;
+ if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP)
+ if (!strcmp(map->data.configs.group_or_pin, name))
+ return map;
+ }
+ return NULL;
+}
+EXPORT_SYMBOL_GPL(pinctrl_lookup_map);
+
static void devm_pinctrl_release(struct device *dev, void *res)
{
pinctrl_put(*(struct pinctrl **)res);
diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h
index 4aad3ce..2687515 100644
--- a/include/linux/pinctrl/consumer.h
+++ b/include/linux/pinctrl/consumer.h
@@ -36,6 +36,10 @@ extern struct pinctrl_state * __must_check pinctrl_lookup_state(
struct pinctrl *p,
const char *name);
extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s);
+extern const struct pinctrl_map * __must_check pinctrl_lookup_map(
+ struct pinctrl *p,
+ const char *name,
+ unsigned type);
extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev);
extern void devm_pinctrl_put(struct pinctrl *p);
--
1.7.10.4
^ permalink raw reply related
* [PATCH v5 04/10] pinctrl: generic: add input schmitt disable parameter
From: Haojian Zhuang @ 2012-11-15 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352968600-15345-1-git-send-email-haojian.zhuang@gmail.com>
In Marvell PXA/MMP silicons, input schmitt disable value is 0x40, not 0.
So append new config parameter -- input schmitt disable.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
drivers/pinctrl/pinconf-generic.c | 1 +
include/linux/pinctrl/pinconf-generic.h | 5 +++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index 33fbaea..833a364 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -41,6 +41,7 @@ struct pin_config_item conf_items[] = {
PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL),
PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL),
PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL),
+ PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_DISABLE, "input schmitt disabled", NULL),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL),
PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "time units"),
PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector"),
diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
index 4f0abb9..47a1bdd 100644
--- a/include/linux/pinctrl/pinconf-generic.h
+++ b/include/linux/pinctrl/pinconf-generic.h
@@ -46,11 +46,11 @@
* @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source
* (open emitter). Sending this config will enabale open drain mode, the
* argument is ignored.
+ * @PIN_CONFIG_INPUT_SCHMITT_DISABLE: disable schmitt-trigger mode on the pin.
* @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in
* schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis,
* the threshold value is given on a custom format as argument when
- * setting pins to this mode. The argument zero turns the schmitt trigger
- * off.
+ * setting pins to this mode.
* @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
* which means it will wait for signals to settle when reading inputs. The
* argument gives the debounce time on a custom format. Setting the
@@ -74,6 +74,7 @@ enum pin_config_param {
PIN_CONFIG_DRIVE_PUSH_PULL,
PIN_CONFIG_DRIVE_OPEN_DRAIN,
PIN_CONFIG_DRIVE_OPEN_SOURCE,
+ PIN_CONFIG_INPUT_SCHMITT_DISABLE,
PIN_CONFIG_INPUT_SCHMITT,
PIN_CONFIG_INPUT_DEBOUNCE,
PIN_CONFIG_POWER_SOURCE,
--
1.7.10.4
^ permalink raw reply related
* [PATCH v5 05/10] pinctrl: single: support pinconf generic
From: Haojian Zhuang @ 2012-11-15 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352968600-15345-1-git-send-email-haojian.zhuang@gmail.com>
Add pinconf generic support with POWER SOURCE, BIAS PULL.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/pinctrl-single.c | 322 +++++++++++++++++++++++++++++++++++---
2 files changed, 305 insertions(+), 18 deletions(-)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 7bf914d..e9f2d2d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -139,6 +139,7 @@ config PINCTRL_SINGLE
depends on OF
select PINMUX
select PINCONF
+ select GENERIC_PINCONF
help
This selects the device tree based generic pinctrl driver.
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 2476a68..be12aca 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -20,6 +20,8 @@
#include <linux/of_device.h>
#include <linux/of_address.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
@@ -33,6 +35,26 @@
#define PCS_MAX_GPIO_VALUES 2
/**
+ * union pcs_pinconf_argument_t -- upper 16-bit in the pinconf data
+ *
+ * The 32-bit pinmux register value could be divided into some different
+ * config arguments. Each config parameter binds to one config argument.
+ * And each config argument can't exceed 5-bit value.
+ * @data: argument of config in pinconf generic
+ * @value: 5-bit value
+ * @mask: 5-bit mask
+ * @shift: shift of value/mask field in pinmux register
+ */
+union pcs_pinconf_argument_t {
+ u16 data;
+ struct {
+ unsigned value:5;
+ unsigned mask:5;
+ unsigned shift:5;
+ } bits;
+};
+
+/**
* struct pcs_pingroup - pingroups for a function
* @np: pingroup device node pointer
* @name: pingroup name
@@ -88,6 +110,16 @@ struct pcs_gpio_range {
};
/**
+ * struct pcs_conf - configuration of pinctrl device
+ * @nconf: number of configuration that is defined for pinconf
+ * @is_generic: for pin controller that want to use the generic interface
+ */
+struct pcs_conf {
+ unsigned nconfs;
+ bool is_generic;
+};
+
+/**
* struct pcs_data - wrapper for data needed by pinctrl framework
* @pa: pindesc array
* @cur: index to current element
@@ -130,6 +162,7 @@ struct pcs_name {
* @fmax: max number of functions in fmask
* @names: array of register names for pins
* @pins: physical pins on the SoC
+ * @conf: value of pinconf
* @pgtree: pingroup index radix tree
* @ftree: function index radix tree
* @pingroups: list of pingroups
@@ -155,6 +188,7 @@ struct pcs_device {
bool bits_per_mux;
struct pcs_name *names;
struct pcs_data pins;
+ struct pcs_conf conf;
struct radix_tree_root pgtree;
struct radix_tree_root ftree;
struct list_head pingroups;
@@ -445,28 +479,168 @@ static struct pinmux_ops pcs_pinmux_ops = {
.gpio_request_enable = pcs_request_gpio,
};
+static void pcs_free_pingroups(struct pcs_device *pcs);
+
+static int pcs_pinconf_get_config(struct pinctrl_dev *pctldev, unsigned pin,
+ enum pin_config_param config_param)
+{
+ const struct pinctrl_map *map;
+ enum pin_config_param param;
+ const unsigned *pins = NULL;
+ const char *name;
+ unsigned long *conf;
+ unsigned count, group, i, npins;
+ int found = 0;
+
+ count = pcs_get_groups_count(pctldev);
+ for (group = 0; group < count; group++) {
+ if (pcs_get_group_pins(pctldev, group, &pins, &npins))
+ return -EINVAL;
+ for (i = 0; i < npins; i++) {
+ if (pins[i] == pin) {
+ found = 1;
+ break;
+ }
+ }
+ if (found)
+ break;
+ }
+ if (!found)
+ return -ENOTSUPP;
+
+ name = pcs_get_group_name(pctldev, group);
+ if (!name)
+ return -EINVAL;
+ map = pinctrl_lookup_map(pctldev->p, name, PIN_MAP_TYPE_CONFIGS_GROUP);
+ if (!map)
+ return -ENOTSUPP;
+
+ conf = map->data.configs.configs;
+ for (i = 0; i < map->data.configs.num_configs; i++) {
+ param = pinconf_to_config_param(conf[i]);
+ if (config_param == param)
+ return conf[i];
+ }
+ return -ENOTSUPP;
+}
+
static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *config)
{
- return -ENOTSUPP;
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param config_param = pinconf_to_config_param(*config);
+ union pcs_pinconf_argument_t arg;
+ u32 offset;
+ unsigned data;
+ int ret;
+
+ if (!pcs->conf.nconfs)
+ return -ENOTSUPP;
+
+ ret = pcs_pinconf_get_config(pctldev, pin, config_param);
+ if (ret < 0)
+ return ret;
+
+ offset = pin * (pcs->width / BITS_PER_BYTE);
+ data = pcs->read(pcs->base + offset);
+
+ arg.data = pinconf_to_config_argument(ret);
+ data = (data >> arg.bits.shift) & arg.bits.mask;
+ arg.bits.value = data;
+ *config = pinconf_to_config_packed(config_param, arg.data);
+ return 0;
}
static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long config)
{
- return -ENOTSUPP;
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param config_param = pinconf_to_config_param(config);
+ union pcs_pinconf_argument_t arg;
+ u32 offset;
+ unsigned data;
+ int ret;
+
+ if (!pcs->conf.nconfs)
+ return -ENOTSUPP;
+
+ ret = pcs_pinconf_get_config(pctldev, pin, config_param);
+ if (ret < 0)
+ return ret;
+
+ offset = pin * (pcs->width / BITS_PER_BYTE);
+ data = pcs->read(pcs->base + offset);
+
+ arg.data = pinconf_to_config_argument(config);
+ data = (data >> arg.bits.shift) & arg.bits.mask;
+ arg.bits.value = data;
+ data = pinconf_to_config_packed(config_param, arg.data);
+ pcs->write(data, pcs->base + offset);
+ return 0;
}
static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned group, unsigned long *config)
{
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ const struct pinctrl_map *map;
+ enum pin_config_param param, config_param;
+ union pcs_pinconf_argument_t arg;
+ const char *name;
+ unsigned long *conf;
+ int i;
+
+ if (!pcs->conf.nconfs)
+ return -ENOTSUPP;
+
+ name = pcs_get_group_name(pctldev, group);
+ if (!name)
+ return -EINVAL;
+ map = pinctrl_lookup_map(pctldev->p, name, PIN_MAP_TYPE_CONFIGS_GROUP);
+ if (!map)
+ return -ENOTSUPP;
+ config_param = pinconf_to_config_param(*config);
+ conf = map->data.configs.configs;
+ for (i = 0; i < map->data.configs.num_configs; i++) {
+ param = pinconf_to_config_param(conf[i]);
+ if (config_param == param) {
+ arg.data = pinconf_to_config_argument(conf[i]);
+ *config = pinconf_to_config_packed(param, arg.data);
+ return 0;
+ }
+ }
return -ENOTSUPP;
}
static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long config)
{
- return -ENOTSUPP;
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ struct pcs_pingroup *pins;
+ union pcs_pinconf_argument_t arg;
+ u32 offset, data;
+ unsigned ret, mask;
+ int i, mux_bytes;
+
+ if (!pcs->conf.nconfs)
+ return -ENOTSUPP;
+
+ pins = radix_tree_lookup(&pcs->pgtree, group);
+ if (!pins) {
+ dev_err(pcs->dev, "%s could not find pingroup%i\n",
+ __func__, group);
+ return -EINVAL;
+ }
+ mux_bytes = pcs->width / BITS_PER_BYTE;
+ arg.data = pinconf_to_config_argument(config);
+ mask = arg.bits.mask << arg.bits.shift;
+ data = arg.bits.value << arg.bits.shift;
+ for (i = 0; i < pins->ngpins; i++) {
+ offset = pins->gpins[i] * mux_bytes;
+ ret = pcs->read(pcs->base + offset) & ~mask;
+ pcs->write(ret | data, pcs->base + offset);
+ }
+ return 0;
}
static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
@@ -676,8 +850,22 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
return index;
}
+static int pcs_config_match(unsigned data, unsigned match)
+{
+ int ret = 0;
+
+ if (!match) {
+ if (!data)
+ ret = 1;
+ } else {
+ if ((data & match) == match)
+ ret = 1;
+ }
+ return ret;
+}
+
/**
- * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
+ * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
* @pcs: pinctrl driver instance
* @np: device node of the mux entry
* @map: map entry
@@ -700,9 +888,13 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
const char **pgnames)
{
struct pcs_func_vals *vals;
+ struct pinctrl_map *m = *map;
const __be32 *mux;
- int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM;
+ int size, params, rows, *pins, i = 0, found = 0, res = -ENOMEM;
struct pcs_function *function;
+ unsigned long *conf;
+ union pcs_pinconf_argument_t arg;
+ u32 value[8], data, nconfs;
if (pcs->bits_per_mux) {
params = 3;
@@ -733,16 +925,16 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
if (!pins)
goto free_vals;
- while (index < size) {
+ while (i < size) {
unsigned offset, val;
int pin;
- offset = be32_to_cpup(mux + index++);
- val = be32_to_cpup(mux + index++);
+ offset = be32_to_cpup(mux + i++);
+ val = be32_to_cpup(mux + i++);
vals[found].reg = pcs->base + offset;
vals[found].val = val;
if (params == 3) {
- val = be32_to_cpup(mux + index++);
+ val = be32_to_cpup(mux + i++);
vals[found].mask = val;
}
@@ -756,6 +948,7 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
pins[found++] = pin;
}
+ nconfs = pcs->conf.nconfs;
pgnames[0] = np->name;
function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
if (!function)
@@ -765,12 +958,82 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
if (res < 0)
goto free_function;
- (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
- (*map)->data.mux.group = np->name;
- (*map)->data.mux.function = np->name;
+ m->type = PIN_MAP_TYPE_MUX_GROUP;
+ m->data.mux.group = np->name;
+ m->data.mux.function = np->name;
+
+ if (!nconfs)
+ return 0;
+
+ conf = devm_kzalloc(pcs->dev, sizeof(*conf) * nconfs, GFP_KERNEL);
+ if (!conf) {
+ res = -ENOMEM;
+ goto free_pingroup;
+ }
+ i = 0;
+ if (!of_property_read_u32_array(np, "pinctrl-single,bias",
+ value, 5)) {
+ /* array: bias value, mask, disable, pull down, pull up */
+ data = value[0] & value[1];
+ arg.bits.shift = ffs(value[1]) - 1;
+ arg.bits.mask = value[1] >> arg.bits.shift;
+ if (pcs_config_match(data, value[2])) {
+ arg.bits.value = value[2] >> arg.bits.shift;
+ conf[i++] = PIN_CONF_PACKED(PIN_CONFIG_BIAS_DISABLE,
+ arg.data);
+ }
+ if (pcs_config_match(data, value[3])) {
+ arg.bits.value = value[3] >> arg.bits.shift;
+ conf[i++] = PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN,
+ arg.data);
+ }
+ if (pcs_config_match(data, value[4])) {
+ arg.bits.value = value[4] >> arg.bits.shift;
+ conf[i++] = PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP,
+ arg.data);
+ }
+ }
+ if (!of_property_read_u32_array(np, "pinctrl-single,power-source",
+ value, 2)) {
+ /* array: power source value, mask */
+ data = value[0] & value[1];
+ arg.bits.shift = ffs(value[1]) - 1;
+ arg.bits.mask = value[1] >> arg.bits.shift;
+ arg.bits.value = data >> arg.bits.shift;
+ conf[i++] = PIN_CONF_PACKED(PIN_CONFIG_POWER_SOURCE, arg.data);
+ }
+ if (!of_property_read_u32_array(np, "pinctrl-single,input-schmitt",
+ value, 3)) {
+ /* array: input schmitt value, mask, disable */
+ data = value[0] & value[1];
+ arg.bits.shift = ffs(value[1]) - 1;
+ arg.bits.mask = value[1] >> arg.bits.shift;
+ if (pcs_config_match(data, value[2])) {
+ arg.bits.value = value[2] >> arg.bits.shift;
+ conf[i++] = PIN_CONF_PACKED(PIN_CONFIG_INPUT_SCHMITT_DISABLE,
+ arg.data);
+ } else {
+ arg.bits.value = data >> arg.bits.shift;
+ conf[i++] = PIN_CONF_PACKED(PIN_CONFIG_INPUT_SCHMITT,
+ arg.data);
+ }
+ }
+ m++;
+ m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
+ m->data.configs.group_or_pin = np->name;
+ m->data.configs.configs = conf;
+ if (i > nconfs) {
+ dev_err(pcs->dev, "pinconf items (%d) more than nconfs (%d)\n",
+ i, nconfs);
+ i = nconfs;
+ }
+ m->data.configs.num_configs = i;
return 0;
+free_pingroup:
+ pcs_free_pingroups(pcs);
+
free_function:
pcs_remove_function(pcs, function);
@@ -782,6 +1045,7 @@ free_vals:
return res;
}
+
/**
* pcs_dt_node_to_map() - allocates and parses pinctrl maps
* @pctldev: pinctrl instance
@@ -797,13 +1061,17 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
const char **pgnames;
int ret;
+
pcs = pinctrl_dev_get_drvdata(pctldev);
- *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL);
- if (!map)
- return -ENOMEM;
+ if (!pcs->conf.nconfs)
+ *num_maps = 1;
+ else
+ *num_maps = 2;
- *num_maps = 0;
+ *map = devm_kzalloc(pcs->dev, sizeof(**map) * (*num_maps), GFP_KERNEL);
+ if (!*map)
+ return -ENOMEM;
pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
if (!pgnames) {
@@ -817,7 +1085,6 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
np_config->name);
goto free_pgnames;
}
- *num_maps = 1;
return 0;
@@ -957,11 +1224,13 @@ static int __devinit pcs_probe(struct platform_device *pdev)
const struct of_device_id *match;
struct resource *res;
struct pcs_device *pcs;
+ const struct pcs_conf *conf;
int ret;
match = of_match_device(pcs_of_match, &pdev->dev);
if (!match)
return -EINVAL;
+ conf = match->data;
pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
if (!pcs) {
@@ -969,6 +1238,7 @@ static int __devinit pcs_probe(struct platform_device *pdev)
return -ENOMEM;
}
pcs->dev = &pdev->dev;
+ memcpy(&pcs->conf, conf, sizeof(*conf));
mutex_init(&pcs->mutex);
INIT_LIST_HEAD(&pcs->pingroups);
INIT_LIST_HEAD(&pcs->functions);
@@ -989,6 +1259,9 @@ static int __devinit pcs_probe(struct platform_device *pdev)
pcs->bits_per_mux = of_property_read_bool(np,
"pinctrl-single,bit-per-mux");
+ if (conf->nconfs)
+ pcs_pinconf_ops.is_generic = true;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(pcs->dev, "could not get resource\n");
@@ -1074,8 +1347,21 @@ static int __devexit pcs_remove(struct platform_device *pdev)
return 0;
}
+/* PINCONF isn't supported */
+static struct pcs_conf pinctrl_conf __devinitdata = {
+ .nconfs = 0,
+ .is_generic = false,
+};
+
+/* Generic PINCONF is supported. */
+static struct pcs_conf pinconf_conf __devinitdata = {
+ .nconfs = 7,
+ .is_generic = true,
+};
+
static struct of_device_id pcs_of_match[] __devinitdata = {
- { .compatible = DRIVER_NAME, },
+ { .compatible = "pinctrl-single", .data = &pinctrl_conf },
+ { .compatible = "pinconf-single", .data = &pinconf_conf },
{ },
};
MODULE_DEVICE_TABLE(of, pcs_of_match);
--
1.7.10.4
^ permalink raw reply related
* [PATCH v5 06/10] ARM: dts: support pinctrl single in pxa910
From: Haojian Zhuang @ 2012-11-15 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352968600-15345-1-git-send-email-haojian.zhuang@gmail.com>
Add pinctrl-single support with device tree in pxa910 dkb platform.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
arch/arm/boot/dts/pxa910-dkb.dts | 204 +++++++++++++++++++++++++++++++++++++-
arch/arm/boot/dts/pxa910.dtsi | 68 +++++++++++++
2 files changed, 271 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
index 595492a..76e9c8d 100644
--- a/arch/arm/boot/dts/pxa910-dkb.dts
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -24,10 +24,212 @@
soc {
apb at d4000000 {
- uart1: uart at d4017000 {
+ pmx: pinmux at d401e000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&board_pins>;
+
+ board_pins: pinmux_board_pins {
+ /* pins not owned by device driver */
+ /* w1 */
+ pinctrl-single,pins = <
+ 0x0cc 0x2 /* CLK_REQ_W1 */
+ >;
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ 0x198 0x6 /* GPIO47_UART1_RXD */
+ 0x19c 0x6 /* GPIO48_UART1_TXD */
+ >;
+ /* power source, mask */
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ /* bias, mask, disable, pull down, pull up */
+ pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>;
+ /* input schmitt, mask, disable */
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ 0x150 0x4 /* GPIO29_UART2_CTS */
+ 0x154 0x4 /* GPIO30_UART2_RTS */
+ 0x158 0x4 /* GPIO31_UART2_TXD */
+ 0x15c 0x4 /* GPIO32_UART2_RXD */
+ >;
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ 0x188 0x7 /* GPIO43_UART3_RXD */
+ 0x18c 0x7 /* GPIO44_UART3_TXD */
+ >;
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ twsi1_pins: pinmux_twsi1_pins {
+ pinctrl-single,pins = <
+ 0x1b0 0x2 /* GPIO53_TWSI_SCL */
+ 0x1b4 0x2 /* GPIO54_TWSI_SDA */
+ >;
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ nand_pins: pinmux_nand_pins {
+ pinctrl-single,pins = <
+ 0x040 0x0 /* ND_IO0 */
+ 0x03c 0x0 /* ND_IO1 */
+ 0x038 0x0 /* ND_IO2 */
+ 0x034 0x0 /* ND_IO3 */
+ 0x030 0x0 /* ND_IO4 */
+ 0x02c 0x0 /* ND_IO5 */
+ 0x028 0x0 /* ND_IO6 */
+ 0x024 0x0 /* ND_IO7 */
+ 0x020 0x0 /* ND_IO8 */
+ 0x01c 0x0 /* ND_IO9 */
+ 0x018 0x0 /* ND_IO10 */
+ 0x014 0x0 /* ND_IO11 */
+ 0x010 0x0 /* ND_IO12 */
+ 0x00c 0x0 /* ND_IO13 */
+ 0x008 0x0 /* ND_IO14 */
+ 0x004 0x0 /* ND_IO15 */
+ 0x044 0x0 /* ND_nCS0 */
+ 0x060 0x1 /* ND_ALE */
+ 0x05c 0x0 /* ND_CLE */
+ 0x054 0x1 /* ND_nWE */
+ 0x058 0x1 /* ND_nRE */
+ 0x068 0x0 /* ND_RDY0 */
+ >;
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ mmc1_ldata_pins: pinmux_mmc1_ldata_pins {
+ pinctrl-single,pins = <
+ 0x0a0 0x0 /* MMC1_DATA0 */
+ 0x09c 0x0 /* MMC1_DATA1 */
+ 0x098 0x0 /* MMC1_DATA2 */
+ 0x094 0x0 /* MMC1_DATA3 */
+ >;
+ pinctrl-single,power-source = <0x1800 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ mmc1_hdata_pins: pinmux_mmc1_hdata_pins {
+ pinctrl-single,pins = <
+ 0x090 0x0 /* MMC1_DATA4 */
+ 0x08c 0x0 /* MMC1_DATA5 */
+ 0x088 0x0 /* MMC1_DATA6 */
+ 0x084 0x0 /* MMC1_DATA7 */
+ >;
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ mmc1_clk_pins: pinmux_mmc1_clk_pins {
+ pinctrl-single,pins = <
+ 0x0a4 0x0 /* MMC1_CMD */
+ 0x0a8 0x0 /* MMC1_CLK */
+ >;
+ pinctrl-single,power-source = <0x1800 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ mmc1_cd_pins: pinmux_mmc1_cd_pins {
+ pinctrl-single,pins = <
+ 0x0ac 0x0 /* MMC1_CD */
+ 0x0b0 0x0 /* MMC1_WP */
+ >;
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ mmc2_pins: pinmux_mmc2_pins {
+ pinctrl-single,pins = <
+ 0x180 0x1 /* MMC2_CMD */
+ 0x184 0x1 /* MMC2_CLK */
+ 0x17c 0x1 /* MMC2_DATA0 */
+ 0x178 0x1 /* MMC2_DATA1 */
+ 0x174 0x1 /* MMC2_DATA2 */
+ 0x170 0x1 /* MMC2_DATA3 */
+ >;
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ ssp1_pins: pinmux_ssp1_pins {
+ pinctrl-single,pins = <
+ 0x130 0x1 /* GPIO21_SSP1_SCLK */
+ 0x134 0x1 /* GPIO22_SSP1_FRM */
+ 0x138 0x1 /* GPIO23_SSP1_TXD */
+ 0x13c 0x1 /* GPIO24_SSP1_RXD */
+ >;
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ keypad_pins: pinmux_keypad_pins {
+ pinctrl-single,pins = <
+ 0x0dc 0x1 /* GPIO0_MKIN0 */
+ 0x0e0 0x1 /* GPIO1_MKOUT0 */
+ 0x0e4 0x1 /* GPIO2_MKIN1 */
+ 0x0e8 0x1 /* GPIO3_MKOUT1 */
+ 0x0ec 0x1 /* GPIO4_MKIN2 */
+ 0x0f0 0x1 /* GPIO5_MKOUT2 */
+ 0x0f4 0x1 /* GPIO6_MKIN3 */
+ 0x0f8 0x1 /* GPIO7_MKOUT3 */
+ 0x0fc 0x1 /* GPIO8_MKIN4 */
+ 0x100 0x1 /* GPIO9_MKOUT4 */
+ 0x10c 0x1 /* GPIO12_MKIN6 */
+ >;
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ nfc_pins: pinmux_nfc_pins {
+ pinctrl-single,pins = <
+ 0x120 0x0 /* GPIO17 */
+ >;
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ wlan_pins: pinmux_wlan_pins {
+ pinctrl-single,pins = <
+ 0x114 0x0 /* GPIO14 */
+ 0x12c 0x0 /* GPIO20 */
+ 0x160 0x0 /* GPIO33 */
+ 0x164 0x0 /* GPIO34 */
+ 0x168 0x0 /* GPIO35 */
+ 0x16c 0x0 /* GPIO36 */
+ >;
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>;
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+ };
+ uart1: uart at d4017000 { /* FFUART */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+ };
+ uart2: uart at d4018000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+ };
+ uart3: uart at d4036000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
status = "okay";
};
twsi1: i2c at d4011000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&twsi1_pins>;
status = "okay";
pmic: 88pm860x at 34 {
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index 825aaca..c2f8b21 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -54,6 +54,74 @@
reg = <0xd4000000 0x00200000>;
ranges;
+ pmx: pinmux at d401e000 {
+ compatible = "pinconf-single";
+ reg = <0xd401e000 0x0330>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+
+ range0: range at d401e0dc {
+ /* GPIO0 ~ GPIO54 */
+ reg = <0xd401e0dc 0xdc>;
+ /* gpio base & gpio func */
+ pinctrl-single,gpio = <0 0>;
+ };
+ range1: range at d401e2f0 {
+ /* GPIO55 ~ GPIO59 */
+ reg = <0xd401e2f0 0x14>;
+ pinctrl-single,gpio = <55 1>;
+ };
+ range2: range at d401e304 {
+ /* GPIO60 ~ GPIO66 */
+ reg = <0xd401e304 0x1c>;
+ pinctrl-single,gpio = <60 0>;
+ };
+ range3: range at d401e1b8 {
+ /* GPIO67 ~ GPIO109 */
+ reg = <0xd401e1b8 0xac>;
+ pinctrl-single,gpio = <67 0>;
+ };
+ range4: range at d401e298 {
+ /* GPIO110 ~ GPIO116 */
+ reg = <0xd401e298 0x1c>;
+ pinctrl-single,gpio = <110 0>;
+ };
+ range5: range at d401e0b4 {
+ /* GPIO117 ~ GPIO120 */
+ reg = <0xd401e0b4 0x10>;
+ pinctrl-single,gpio = <117 1>;
+ };
+ range6: range at d401e32c {
+ /* GPIO121 */
+ reg = <0xd401e32c 0x04>;
+ pinctrl-single,gpio = <121 0>;
+ };
+ range7: range at d401e0c8 {
+ /* GPIO122 ~ GPIO123 */
+ reg = <0xd401e0c8 0x08>;
+ pinctrl-single,gpio = <122 1>;
+ };
+ range8: range at d401e0d0 {
+ /* GPIO124 */
+ reg = <0xd401e0d0 0x04>;
+ pinctrl-single,gpio = <124 0>;
+ };
+ range9: range at d401e0d4 {
+ /* GPIO125 */
+ reg = <0xd401e0d4 0x04>;
+ pinctrl-single,gpio = <125 1>;
+ };
+ range10: range at d401e06c {
+ /* GPIO126 ~ GPIO127 */
+ reg = <0xd401e06c 0x08>;
+ pinctrl-single,gpio = <126 0>;
+ };
+ };
+
timer0: timer at d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
--
1.7.10.4
^ permalink raw reply related
* [PATCH v5 07/10] document: devicetree: bind pinconf with pin single
From: Haojian Zhuang @ 2012-11-15 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352968600-15345-1-git-send-email-haojian.zhuang@gmail.com>
Add comments with pinconf & gpio range in the document of
pinctrl-single.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
.../devicetree/bindings/pinctrl/pinctrl-single.txt | 82 +++++++++++++++++++-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index 2c81e45..8f0c0dd 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -1,7 +1,9 @@
One-register-per-pin type device tree based pinctrl driver
Required properties:
-- compatible : "pinctrl-single"
+- compatible : "pinctrl-single" or "pinconf-single".
+ "pinctrl-single" means that pinconf isn't supported.
+ "pinconf-single" means that generic pinconf is supported.
- reg : offset and length of the register set for the mux registers
@@ -14,9 +16,31 @@ Optional properties:
- pinctrl-single,function-off : function off mode for disabled state if
available and same for all registers; if not specified, disabling of
pin functions is ignored
+
- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
more than one pin
+- pinctrl-single,power-source : array of value that are used to configure
+ power source in the pinmux register. They're value of power source field
+ and power source mask.
+
+ /* power source, mask */
+ pinctrl-single,power-source = <0x1000 0x1800>;
+
+- pinctrl-single,bias : array of value that are used to configure the input
+ bias in the pinmux register. They're value of bias field, bias mask,
+ bias disable value, bias pull down value & bias pull up value.
+
+ /* bias, mask, disable, pull down, pull up */
+ pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>;
+
+- pinctrl-single,input-schmitt : array of value that are used to configure
+ input schmitt in the pinmux register. They're value of input schmitt field,
+ mask, & disable value.
+
+ /* input schmitt value, mask, disable */
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+
This driver assumes that there is only one register for each pin (unless the
pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
specified in the pinctrl-bindings.txt document in this directory.
@@ -42,6 +66,24 @@ Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
be used when applying this change to the register.
+
+Optional sub-node: In case some pins could be configured as GPIO in the pinmux
+register, those pins could be defined as a GPIO range. The sub-node should
+be defined in .dtsi files of those silicons.
+
+Required properties in sub-node:
+- reg : offset and length of the GPIO range sub-node.
+
+- pinctrl-single,gpio : array of GPIO base number in the range and the GPIO
+ function in the pinmux register.
+
+ range0: {
+ /* GPIO0 ~ GPIO54 */
+ reg = <0xd401e0dc 55>;
+ pinctrl-single,gpio = <0 0>;
+ };
+
+
Example:
/* SoC common file */
@@ -76,6 +118,26 @@ control_devconf0: pinmux at 48002274 {
pinctrl-single,function-mask = <0x5F>;
};
+/* third controller instance for pins in gpio domain */
+pmx_gpio: pinmux at d401e000 {
+ compatible = "pinconf-single";
+ reg = <0xd401e000 0x0330>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+
+ range0: range at d401e0dc {
+ /* GPIO0 ~ GPIO54 */
+ reg = <0xd401e0dc 0xdc>;
+ /* gpio base & gpio func */
+ pinctrl-single,gpio = <0 0>;
+ };
+};
+
+
/* board specific .dts file */
&pmx_core {
@@ -96,6 +158,19 @@ control_devconf0: pinmux at 48002274 {
>;
};
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ 0x198 0x6 /* GPIO47_UART1_RXD */
+ 0x19c 0x6 /* GPIO48_UART1_TXD */
+ >;
+ /* power source, mask */
+ pinctrl-single,power-source = <0x1000 0x1800>;
+ /* bias, mask, disable, pull down, pull up */
+ pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>;
+ /* input schmitt, mask, disable */
+ pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
+ };
+
/* map uart2 pins */
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
@@ -122,6 +197,11 @@ control_devconf0: pinmux@48002274 {
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+};
+
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
--
1.7.10.4
^ permalink raw reply related
* [PATCH v5 08/10] tty: pxa: configure pin
From: Haojian Zhuang @ 2012-11-15 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352968600-15345-1-git-send-email-haojian.zhuang@gmail.com>
Configure pins by pinctrl driver.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/tty/serial/pxa.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
index 9033fc6..02dc771 100644
--- a/drivers/tty/serial/pxa.c
+++ b/drivers/tty/serial/pxa.c
@@ -37,6 +37,7 @@
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/of.h>
+#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
@@ -809,6 +810,7 @@ static int serial_pxa_probe_dt(struct platform_device *pdev,
struct uart_pxa_port *sport)
{
struct device_node *np = pdev->dev.of_node;
+ struct pinctrl *pinctrl;
int ret;
if (!np)
@@ -819,6 +821,10 @@ static int serial_pxa_probe_dt(struct platform_device *pdev,
dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
return ret;
}
+ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+ if (IS_ERR(pinctrl))
+ return -EPROBE_DEFER;
+
sport->port.line = ret;
return 0;
}
@@ -857,7 +863,7 @@ static int serial_pxa_probe(struct platform_device *dev)
ret = serial_pxa_probe_dt(dev, sport);
if (ret > 0)
sport->port.line = dev->id;
- else if (ret < 0)
+ if (ret < 0)
goto err_clk;
snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
--
1.7.10.4
^ permalink raw reply related
* [PATCH v5 09/10] i2c: pxa: use devm_kzalloc
From: Haojian Zhuang @ 2012-11-15 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352968600-15345-1-git-send-email-haojian.zhuang@gmail.com>
Use devm_kzalloc & add checking in probe() function.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
---
drivers/i2c/busses/i2c-pxa.c | 26 ++++++++++----------------
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 1034d93..7c8b5d0 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -1078,6 +1078,8 @@ static int i2c_pxa_probe_pdata(struct platform_device *pdev,
struct i2c_pxa_platform_data *plat = pdev->dev.platform_data;
const struct platform_device_id *id = platform_get_device_id(pdev);
+ if (!id)
+ return -EINVAL;
*i2c_types = id->driver_data;
if (plat) {
i2c->use_pio = plat->use_pio;
@@ -1094,29 +1096,23 @@ static int i2c_pxa_probe(struct platform_device *dev)
struct resource *res = NULL;
int ret, irq;
- i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
- if (!i2c) {
- ret = -ENOMEM;
- goto emalloc;
- }
+ i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
+ if (!i2c)
+ return -ENOMEM;
ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
if (ret > 0)
ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
if (ret < 0)
- goto eclk;
+ return ret;
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
irq = platform_get_irq(dev, 0);
- if (res == NULL || irq < 0) {
- ret = -ENODEV;
- goto eclk;
- }
+ if (res == NULL || irq < 0)
+ return -ENODEV;
- if (!request_mem_region(res->start, resource_size(res), res->name)) {
- ret = -ENOMEM;
- goto eclk;
- }
+ if (!request_mem_region(res->start, resource_size(res), res->name))
+ return -ENOMEM;
i2c->adap.owner = THIS_MODULE;
i2c->adap.retries = 5;
@@ -1209,8 +1205,6 @@ ereqirq:
eremap:
clk_put(i2c->clk);
eclk:
- kfree(i2c);
-emalloc:
release_mem_region(res->start, resource_size(res));
return ret;
}
--
1.7.10.4
^ permalink raw reply related
* [PATCH v5 10/10] i2c: pxa: configure pinmux
From: Haojian Zhuang @ 2012-11-15 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352968600-15345-1-git-send-email-haojian.zhuang@gmail.com>
Configure pins by pinctrl driver.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/i2c/busses/i2c-pxa.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 7c8b5d0..11e4a30 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -32,6 +32,7 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_i2c.h>
+#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
@@ -1051,6 +1052,7 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
enum pxa_i2c_types *i2c_types)
{
struct device_node *np = pdev->dev.of_node;
+ struct pinctrl *pinctrl;
const struct of_device_id *of_id =
of_match_device(i2c_pxa_dt_ids, &pdev->dev);
int ret;
@@ -1063,6 +1065,9 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
return ret;
}
pdev->id = ret;
+ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+ if (IS_ERR(pinctrl))
+ return -EPROBE_DEFER;
if (of_get_property(np, "mrvl,i2c-polling", NULL))
i2c->use_pio = 1;
if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
--
1.7.10.4
^ permalink raw reply related
* [PATCH v3 03/11] clk: exynos4: register clocks using common clock framework
From: Thomas Abraham @ 2012-11-15 8:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1838496.eVNjc9n65Z@flatron>
Hi Tomasz,
On 15 November 2012 04:54, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Thomas,
>
> Looks mostly good, but I have some minor comments inline.
>
> On Thursday 15 of November 2012 03:37:25 Thomas Abraham wrote:
>> The Exynos4 clocks are statically listed and registered using the
>> Samsung specific common clock helper functions. Both device tree based
>> clock lookup and clkdev based clock lookups are supported.
>>
>> Cc: Mike Turquette <mturquette@linaro.org>
>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> .../devicetree/bindings/clock/exynos4-clock.txt | 215 +++++++
>> drivers/clk/samsung/Makefile | 1 +
>> drivers/clk/samsung/clk-exynos4.c | 641
>> ++++++++++++++++++++ 3 files changed, 857 insertions(+), 0 deletions(-)
>> create mode 100644
>> Documentation/devicetree/bindings/clock/exynos4-clock.txt create mode
>> 100644 drivers/clk/samsung/clk-exynos4.c
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> b/Documentation/devicetree/bindings/clock/exynos4-clock.txt new file
>> mode 100644
>> index 0000000..e874add
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> @@ -0,0 +1,215 @@
>> +* Samsung Exynos4 Clock Controller
>> +
>> +The Exynos4 clock controller generates and supplies clock to various
>> controllers +within the Exynos4 SoC. The clock binding described here
>> is applicable to all +SoC's in the Exynos4 family.
>> +
>> +Required Properties:
>> +
>> +- comptible: should be one of the following.
>> + - "samsung,exynos4210-clock" - controller compatible with Exynos4210
>> SoC. + - "samsung,exynos4412-clock" - controller compatible with
>> Exynos4412 SoC. +
>> +- reg: physical base address of the controller and length of memory
>> mapped + region.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +The following is the list of clocks generated by the controller. Each
>> clock is +assigned an identifier and client nodes use this identifier
>> to specify the +clock which they consume. Some of the clocks are
>> available only on a particular +Exynos4 SoC and this is specified where
>> applicable.
>> +
>> +
>> + [Core Clocks]
>> +
>> + Clock ID SoC (if specific)
>> + -----------------------------------------------
>> +
>> + xxti 1
>> + xusbxti 2
>> + fin_pll 3
>> + fout_apll 4
>> + fout_mpll 5
>> + fout_epll 6
>> + fout_vpll 7
>> + sclk_apll 8
>> + sclk_mpll 9
>> + sclk_epll 10
>> + sclk_vpll 11
>> + arm_clk 12
>> + aclk200 13
>> + aclk100 14
>> + aclk160 15
>> + aclk133 16
>> +
>> +
>> + [Clock Gate for Special Clocks]
>> +
>> + Clock ID SoC (if specific)
>> + -----------------------------------------------
>> +
>> + sclk_fimc0 128
>> + sclk_fimc1 129
>> + sclk_fimc2 130
>> + sclk_fimc3 131
>> + sclk_cam0 132
>> + sclk_cam1 133
>> + sclk_csis0 134
>> + sclk_csis1 135
>> + sclk_hdmi 136
>> + sclk_mixer 137
>> + sclk_dac 138
>> + sclk_pixel 139
>> + sclk_fimd0 140
>> + sclk_mdnie0 141 Exynos4412
>> + sclk_mdnie_pwm0 12 142 Exynos4412
>> + sclk_mipi0 143
>> + sclk_audio0 144
>> + sclk_mmc0 145
>> + sclk_mmc1 146
>> + sclk_mmc2 147
>> + sclk_mmc3 148
>> + sclk_mmc4 149
>> + sclk_sata 150 Exynos4210
>> + sclk_uart0 151
>> + sclk_uart1 152
>> + sclk_uart2 153
>> + sclk_uart3 154
>> + sclk_uart4 155
>> + sclk_audio1 156
>> + sclk_audio2 157
>> + sclk_spdif 158
>> + sclk_spi0 159
>> + sclk_spi1 160
>> + sclk_spi2 161
>> + sclk_slimbus 162
>> + sclk_fimd1 163 Exynos4210
>> + sclk_mipi1 164 Exynos4210
>> + sclk_pcm1 165
>> + sclk_pcm2 166
>> + sclk_i2s1 167
>> + sclk_i2s2 168
>> + sclk_mipihsi 169 Exynos4412
>> +
>> +
>> + [Peripheral Clock Gates]
>> +
>> + Clock ID SoC (if specific)
>> + -----------------------------------------------
>> +
>> + fimc0 256
>> + fimc1 257
>> + fimc2 258
>> + fimc3 259
>> + csis0 260
>> + csis1 261
>> + jpeg 262
>> + smmu_fimc0 263
>> + smmu_fimc1 264
>> + smmu_fimc2 265
>> + smmu_fimc3 266
>> + smmu_jpeg 267
>> + vp 268
>> + mixer 269
>> + tvenc 270 Exynos4210
>> + hdmi 271
>> + smmu_tv 272
>> + mfc 273
>> + smmu_mfcl 274
>> + smmu_mfcr 275
>> + g3d 276
>> + g2d 277 Exynos4210
>> + rotator 278 Exynos4210
>> + mdma 279 Exynos4210
>> + smmu_g2d 280 Exynos4210
>> + smmu_rotator 281 Exynos4210
>> + smmu_mdma 282 Exynos4210
>> + fimd0 283
>> + mie0 284
>> + mdnie0 285 Exynos4412
>> + dsim0 286
>> + smmu_fimd0 287
>> + fimd1 288 Exynos4210
>> + mie1 289 Exynos4210
>> + dsim1 290 Exynos4210
>> + smmu_fimd1 291 Exynos4210
>> + pdma0 292
>> + pdma1 293
>> + pcie_phy 294
>> + sata_phy 295 Exynos4210
>> + tsi 296
>> + sdmmc0 297
>> + sdmmc1 298
>> + sdmmc2 299
>> + sdmmc3 300
>> + sdmmc4 301
>> + sata 302 Exynos4210
>> + sromc 303
>> + usb_host 304
>> + usb_device 305
>> + pcie 306
>> + onenand 307
>> + nfcon 308
>> + smmu_pcie 309
>> + gps 310
>> + smmu_gps 311
>> + uart0 312
>> + uart1 313
>> + uart2 314
>> + uart3 315
>> + uart4 316
>> + i2c0 317
>> + i2c1 318
>> + i2c2 319
>> + i2c3 320
>> + i2c4 321
>> + i2c5 322
>> + i2c6 323
>> + i2c7 324
>> + i2c_hdmi 325
>> + tsadc 326
>> + spi0 327
>> + spi1 328
>> + spi2 329
>> + i2s1 330
>> + i2s2 331
>> + pcm0 332
>> + i2s0 333
>> + pcm1 334
>> + pcm2 335
>> + pwm 336
>> + slimbus 337
>> + spdif 338
>> + ac97 339
>> + modemif 340
>> + chipid 341
>> + sysreg 342
>> + hdmi_cec 343
>> + mct 344
>> + wdt 345
>> + rtc 346
>> + keyif 347
>> + audss 348
>> + mipi_hsi 349 Exynos4210
>> + mdma2 350 Exynos4210
>
> I wonder what is the state of including the possibility of defining
> constants in dts into dtc. Is it already merged?
>
> If yes, maybe we could define all those constants instead of specifying
> these raw numbers?
I checked while I was working on this patch series, but the
pre-processor patch from Stephen Warren was not yet merged.
>
>> +Example 1: An example of a clock controller node is listed below.
>> +
>> + clock: clock-controller at 0x10030000 {
>> + compatible = "samsung,exynos4210-clock";
>> + reg = <0x10030000 0x20000>;
>> + #clock-cells = <1>;
>> + };
>> +
>> +Example 2: UART controller node that consumes the clock generated by
>> the clock + controller. Refer to the standard clock bindings for
>> information + about 'clocks' and 'clock-names' property.
>> +
>> + serial at 13820000 {
>> + compatible = "samsung,exynos4210-uart";
>> + reg = <0x13820000 0x100>;
>> + interrupts = <0 54 0>;
>> + clocks = <&clock 314>, <&clock 153>;
>> + clock-names = "uart", "clk_uart_baud0";
>> + };
>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>> index a5bf189..5d98904 100644
>> --- a/drivers/clk/samsung/Makefile
>> +++ b/drivers/clk/samsung/Makefile
>> @@ -3,3 +3,4 @@
>> #
>>
>> obj-$(CONFIG_PLAT_SAMSUNG) += clk.o clk-pll.o
>> +obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
>> diff --git a/drivers/clk/samsung/clk-exynos4.c
>> b/drivers/clk/samsung/clk-exynos4.c new file mode 100644
>> index 0000000..6f0b6a7
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-exynos4.c
>> @@ -0,0 +1,641 @@
>> +/*
>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>> + * Copyright (c) 2012 Linaro Ltd.
>> + * Author: Thomas Abraham <thomas.ab@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as +
>> * published by the Free Software Foundation.
>> + *
>> + * Common Clock Framework support for all Exynos4 SoC's.
>> +*/
>> +
>> +#include <linux/clk.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +
>> +#include <plat/cpu.h>
>> +#include "clk.h"
>> +#include "clk-pll.h"
>> +
>> +/* the exynos4 soc type */
>> +enum exynos4_soc {
>> + EXYNOS4210,
>> + EXYNOS4X12,
>> +};
>> +
>> +/*
>> + * Let each supported clock get a unique id. This id is used to lookup
>> the clock + * for device tree based platforms. The clocks are
>> categorized into three + * sections: core, sclk gate and bus interface
>> gate clocks.
>> + *
>> + * When adding a new clock to this list, it is advised to choose a
>> clock + * category and add it to the end of that category. That is
>> because the the + * device tree source file is referring to these ids
>> and any change in the + * sequence number of existing clocks will
>> require corresponding change in the + * device tree files. This
>> limitation would go away when pre-processor support + * for dtc would
>> be available.
>> + */
>> +enum exynos4_clks {
>> + none,
>> +
>> + /* core clocks */
>> + xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
>> + sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200,
> aclk100,
>> + aclk160, aclk133,
>> +
>> + /* gate for special clocks (sclk) */
>> + sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
>> + sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac,
>> + sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0,
>> + sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4,
>> + sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3,
> sclk_uart4,
>> + sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1,
>> sclk_spi2, + sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1,
>> sclk_pcm2, sclk_i2s1, + sclk_i2s2, sclk_mipihsi,
>> +
>> + /* gate clocks */
>> + fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
>> + smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc,
> hdmi,
>> + smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma,
>> smmu_g2d, + smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0,
>> smmu_fimd0, fimd1, + mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy,
>> sata_phy, tsi, sdmmc0, + sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc,
>> usb_host, usb_device, pcie, + onenand, nfcon, smmu_pcie, gps,
> smmu_gps,
>> uart0, uart1, uart2, uart3, + uart4, i2c0, i2c1, i2c2, i2c3, i2c4,
>> i2c5, i2c6, i2c7, i2c_hdmi, tsadc, + spi0, spi1, spi2, i2s1, i2s2,
>> pcm0, i2s0, pcm1, pcm2, pwm, slimbus, + spdif, ac97, modemif,
> chipid,
>> sysreg, hdmi_cec, mct, wdt, rtc, keyif, + audss, mipi_hsi, mdma2,
>> +
>> + nr_clks,
>> +};
>> +/* list of all parent clock list */
>> +PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
>> +PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
>> +PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
>> +PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
>> +PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
>> +PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
>> +PNAME(mout_core_p) = { "mout_apll", "sclk_mpll", };
>> +PNAME(sclk_ampll_p) = { "sclk_mpll", "sclk_apll", };
>> +PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll", };
>> +PNAME(aclk_p4412) = { "mout_mpll_user", "sclk_apll", };
>> +PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
>> +PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
>> +PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
>> +PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
>> +PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
>> +PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
>> +PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
>> +PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
>> +PNAME(group1_p) = { "xxti", "xusbxti", "sclk_hdmi24m",
> "sclk_usbphy0",
>> + "none", "sclk_hdmiphy", "sclk_mpll",
>> + "mout_epll", "mout_vpll", };
>> +PNAME(mout_audio0_p) = { "cdclk0", "none", "sclk_hdmi24m",
>> "sclk_usbphy0", + "xxti", "xusbxti", "sclk_mpll",
> "sclk_epll",
>> + "sclk_vpll" };
>> +PNAME(mout_audio1_p) = { "cdclk1", "none", "sclk_hdmi24m",
>> "sclk_usbphy0", + "xxti", "xusbxti", "sclk_mpll",
> "mout_epll",
>> + "mout_vpll", };
>> +PNAME(mout_audio2_p) = { "cdclk2", "none", "sclk_hdmi24m",
>> "sclk_usbphy0", + "xxti", "xusbxti", "sclk_mpll",
> "mout_epll",
>> + "mout_vpll", };
>> +PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
>> + "spdif_extclk", };
>> +
>> +/* fixed rate clocks generated outside the soc */
>> +struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] = {
>> + FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
>> + FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
>> +};
>> +
>> +/* fixed rate clocks generated inside the soc */
>> +struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] = {
>> + FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
>> + FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
>> + FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
>> +};
>> +
>> +struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] = {
>> + FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
>> +};
>> +
>> +/* list of mux clocks supported in all exynos4 soc's */
>> +struct samsung_mux_clock exynos4_mux_clks[] = {
>> + MUX(none, "mout_apll", mout_apll_p, 0x14200, 0, 1),
>> + MUX(none, "mout_core", mout_core_p, 0x14200, 16, 1),
>> + MUX_A(sclk_epll, "sclk_epll", mout_epll_p, 0xc210, 4, 1,
> "sclk_epll"),
>> + MUX(none, "mout_fimc0", group1_p, 0xc220, 0, 4),
>> + MUX(none, "mout_fimc1", group1_p, 0xc220, 4, 4),
>> + MUX(none, "mout_fimc2", group1_p, 0xc220, 8, 4),
>> + MUX(none, "mout_fimc3", group1_p, 0xc220, 12, 4),
>> + MUX(none, "mout_cam0", group1_p, 0xc220, 16, 4),
>> + MUX(none, "mout_cam1", group1_p, 0xc220, 20, 4),
>> + MUX(none, "mout_csis0", group1_p, 0xc220, 24, 4),
>> + MUX(none, "mout_csis1", group1_p, 0xc220, 28, 4),
>> + MUX(none, "mout_hdmi", mout_hdmi_p, 0xc224, 0, 1),
>> + MUX(none, "mout_mfc0", sclk_ampll_p, 0xc228, 0, 1),
>> + MUX(none, "mout_mfc1", sclk_evpll_p, 0xc228, 4, 1),
>> + MUX(none, "mout_mfc", mout_mfc_p, 0xc228, 8, 1),
>> + MUX(none, "mout_g3d0", sclk_ampll_p, 0xc22c, 0, 1),
>> + MUX(none, "mout_g3d1", sclk_evpll_p, 0xc22c, 4, 1),
>> + MUX(none, "mout_g3d", mout_g3d_p, 0xc22c, 8, 1),
>> + MUX(none, "mout_fimd0", group1_p, 0xc234, 0, 4),
>> + MUX(none, "mout_mipi0", group1_p, 0xc234, 12, 4),
>> + MUX(none, "mout_audio0", mout_audio0_p, 0xc23c, 0, 4),
>> + MUX(none, "mout_mmc0", group1_p, 0xc240, 0, 4),
>> + MUX(none, "mout_mmc1", group1_p, 0xc240, 4, 4),
>> + MUX(none, "mout_mmc2", group1_p, 0xc240, 8, 4),
>> + MUX(none, "mout_mmc3", group1_p, 0xc240, 12, 4),
>> + MUX(none, "mout_mmc4", group1_p, 0xc240, 16, 4),
>> + MUX(none, "mout_uart0", group1_p, 0xc250, 0, 4),
>> + MUX(none, "mout_uart1", group1_p, 0xc250, 4, 4),
>> + MUX(none, "mout_uart2", group1_p, 0xc250, 8, 4),
>> + MUX(none, "mout_uart3", group1_p, 0xc250, 12, 4),
>> + MUX(none, "mout_uart4", group1_p, 0xc250, 16, 4),
>> + MUX(none, "mout_audio1", mout_audio1_p, 0xc254, 0, 4),
>> + MUX(none, "mout_audio2", mout_audio2_p, 0xc254, 4, 4),
>> + MUX(none, "mout_spdif", mout_spdif_p, 0xc254, 8, 2),
>> + MUX(none, "mout_spi0", group1_p, 0xc254, 16, 4),
>> + MUX(none, "mout_spi1", group1_p, 0xc254, 20, 4),
>> + MUX(none, "mout_spi2", group1_p, 0xc254, 24, 4),
>> +};
>> +
>> +/* list of mux clocks supported in exynos4210 soc */
>> +struct samsung_mux_clock exynos4210_mux_clks[] = {
>> + MUX(none, "mout_aclk200", sclk_ampll_p, 0xc210, 12, 1),
>> + MUX(none, "mout_aclk100", sclk_ampll_p, 0xc210, 16, 1),
>> + MUX(none, "mout_aclk160", sclk_ampll_p, 0xc210, 20, 1),
>> + MUX(none, "mout_aclk133", sclk_ampll_p, 0xc210, 24, 1),
>> + MUX(none, "mout_vpllsrc", mout_vpllsrc_p, 0xc214, 0, 1),
>> + MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, 0x14200, 8, 1,
>> "sclk_mpll"), + MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, 0xc210,
>> 8, 1, "sclk_vpll"), + MUX(none, "mout_mixer", mout_mixer_p4210,
> 0xc224,
>> 4, 1),
>> + MUX(none, "mout_dac", mout_dac_p4210, 0xc224, 8, 1),
>> + MUX(none, "mout_g2d0", sclk_ampll_p, 0xc230, 0, 1),
>> + MUX(none, "mout_g2d1", sclk_evpll_p, 0xc230, 4, 1),
>> + MUX(none, "mout_g2d", mout_g2d_p, 0xc230, 8, 1),
>> + MUX(none, "mout_fimd1", group1_p, 0xc238, 0, 4),
>> + MUX(none, "mout_mipi1", group1_p, 0xc238, 12, 4),
>> +};
>> +
>> +/* list of mux clocks supported in exynos4x12 soc */
>> +struct samsung_mux_clock exynos4x12_mux_clks[] = {
>> + MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, 0x10200, 12, 1,
>> "sclk_mpll"), + MUX(none, "mout_mpll_user", mout_mpll_user_p, 0x4200,
>> 4, 1), + MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p, 0xc210, 8, 1,
>> "sclk_vpll"), + MUX(none, "mout_aclk200", aclk_p4412, 0xc210, 12, 1),
>> + MUX(none, "mout_aclk100", aclk_p4412, 0xc210, 16, 1),
>> + MUX(none, "mout_aclk160", aclk_p4412, 0xc210, 20, 1),
>> + MUX(none, "mout_aclk133", aclk_p4412, 0xc210, 24, 1),
>> + MUX(none, "mout_mdnie0", group1_p, 0xc234, 4, 4),
>> + MUX(none, "mout_mdnie_pwm0", group1_p, 0xc234, 8, 4),
>> + MUX(none, "mout_sata", sclk_ampll_p, 0xc240, 24, 1),
>> + MUX(none, "mout_jpeg0", sclk_ampll_p, 0xc258, 0, 1),
>> + MUX(none, "mout_jpeg1", sclk_evpll_p, 0xc258, 4, 1),
>> + MUX(none, "mout_jpeg", mout_jpeg_p, 0xc258, 8, 1),
>> +};
>> +
>> +/* list of divider clocks supported in all exynos4 soc's */
>> +struct samsung_div_clock exynos4_div_clks[] = {
>> + DIV_A(sclk_apll, "sclk_apll", "mout_apll", 0x14500, 24, 3,
>> "sclk_apll"), + DIV(none, "div_core", "mout_core", 0x14500, 0, 3),
>> + DIV(none, "div_core2", "div_core", 0x14500, 28, 3),
>> + DIV_A(arm_clk, "arm_clk", "div_core2", 0x14500, 28, 3, "arm_clk"),
>> + DIV(aclk200, "aclk200", "mout_aclk200", 0xc510, 0, 3),
>> + DIV(aclk100, "aclk100", "mout_aclk100", 0xc510, 4, 4),
>> + DIV(aclk160, "aclk160", "mout_aclk160", 0xc510, 8, 3),
>> + DIV(aclk133, "aclk133", "mout_aclk133", 0xc510, 12, 3),
>> + DIV(none, "div_fimc0", "mout_fimc0", 0xc520, 0, 4),
>> + DIV(none, "div_fimc1", "mout_fimc1", 0xc520, 4, 4),
>> + DIV(none, "div_fimc2", "mout_fimc2", 0xc520, 8, 4),
>> + DIV(none, "div_fimc3", "mout_fimc3", 0xc520, 12, 4),
>> + DIV(none, "div_cam0", "mout_cam0", 0xc520, 16, 4),
>> + DIV(none, "div_cam1", "mout_cam1", 0xc520, 20, 4),
>> + DIV(none, "div_csis0", "mout_csis0", 0xc520, 24, 4),
>> + DIV(none, "div_csis1", "mout_csis1", 0xc520, 28, 4),
>> + DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", 0xc524, 0, 4),
>> + DIV(none, "div_mfc", "mout_mfc", 0xc528, 0, 4),
>> + DIV(none, "div_g3d", "mout_g3d", 0xc52c, 0, 4),
>> + DIV(none, "div_fimd0", "mout_fimd0", 0xc534, 0, 4),
>> + DIV(none, "div_mipi0", "mout_mipi0", 0xc534, 16, 4),
>> + DIV(none, "div_mipi_pre0", "div_mipi0", 0xc534, 20, 4),
>> + DIV(none, "div_audio0", "mout_audio0", 0xc53c, 0, 4),
>> + DIV(none, "div_pcm0", "sclk_audio0", 0xc53c, 4, 8),
>> + DIV(none, "div_mmc0", "mout_mmc0", 0xc544, 0, 4),
>> + DIV(none, "div_mmc_pre0", "div_mmc0", 0xc544, 8, 8),
>> + DIV(none, "div_mmc1", "mout_mmc1", 0xc544, 16, 4),
>> + DIV(none, "div_mmc_pre1", "div_mmc1", 0xc544, 24, 8),
>> + DIV(none, "div_mmc2", "mout_mmc2", 0xc548, 0, 4),
>> + DIV(none, "div_mmc_pre2", "div_mmc2", 0xc548, 8, 8),
>> + DIV(none, "div_mmc3", "mout_mmc3", 0xc548, 16, 4),
>> + DIV(none, "div_mmc_pre3", "div_mmc3", 0xc548, 24, 8),
>> + DIV(none, "div_mmc4", "mout_mmc4", 0xc54c, 0, 4),
>> + DIV(none, "div_mmc_pre4", "div_mmc4", 0xc54c, 8, 8),
>> + DIV(none, "div_uart0", "mout_uart0", 0xc550, 0, 4),
>> + DIV(none, "div_uart1", "mout_uart1", 0xc550, 4, 4),
>> + DIV(none, "div_uart2", "mout_uart2", 0xc550, 8, 4),
>> + DIV(none, "div_uart3", "mout_uart3", 0xc550, 12, 4),
>> + DIV(none, "div_uart4", "mout_uart4", 0xc550, 16, 4),
>> + DIV(none, "div_spi0", "mout_spi0", 0xc554, 0, 4),
>> + DIV(none, "div_spi_pre0", "div_spi0", 0xc554, 8, 8),
>> + DIV(none, "div_spi1", "mout_spi1", 0xc554, 16, 4),
>> + DIV(none, "div_spi_pre1", "div_spi1", 0xc554, 24, 8),
>> + DIV(none, "div_spi2", "mout_spi2", 0xc558, 0, 4),
>> + DIV(none, "div_spi_pre2", "div_spi2", 0xc558, 8, 8),
>> + DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", 0xc55c, 4, 4),
>> + DIV(none, "div_audio1", "mout_audio1", 0xc560, 0, 4),
>> + DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", 0xc560, 4, 8),
>> + DIV(none, "div_audio2", "mout_audio2", 0xc560, 16, 4),
>> + DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", 0xc560, 20, 8),
>> + DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", 0xc564, 0, 6),
>> + DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", 0xc564, 8, 6),
>> +};
>> +
>> +/* list of divider clocks supported in exynos4210 soc */
>> +struct samsung_div_clock exynos4210_div_clks[] = {
>> + DIV(none, "div_g2d", "mout_g2d", 0xc530, 0, 4),
>> + DIV(none, "div_fimd1", "mout_fimd1", 0xc538, 0, 4),
>> + DIV(none, "div_mipi1", "mout_mipi1", 0xc538, 16, 4),
>> + DIV(none, "div_mipi_pre1", "div_mipi1", 0xc538, 20, 4),
>> + DIV(none, "div_sata", "mout_sata", 0xc540, 20, 4),
>> +};
>> +
>> +/* list of divider clocks supported in exynos4x12 soc */
>> +struct samsung_div_clock exynos4x12_div_clks[] = {
>> + DIV(none, "div_mdnie0", "mout_mdnie0", 0xc534, 4, 4),
>> + DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", 0xc534, 8, 4),
>> + DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", 0xc534, 12, 4),
>> + DIV(none, "div_mipihsi", "mout_mipihsi", 0xc540, 20, 4),
>> + DIV(none, "div_jpeg", "mout_jpeg", 0xc568, 0, 4),
>> +};
>> +
>> +/* list of gate clocks supported in all exynos4 soc's */
>> +struct samsung_gate_clock exynos4_gate_clks[] = {
>> + /*
>> + * After all Exynos4 based platforms are migrated to use device
> tree,
>> + * the device name and clock alias names specified below for some
>> + * of the clocks can be removed.
>> + */
>> + GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0",
>> + 0xc320, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
>> + GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1",
>> + 0xc320, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
>> + GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2",
>> + 0xc320, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
>> + GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3",
>> + 0xc320, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
>> + GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0",
>> + 0xc320, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
>> + GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1",
>> + 0xc320, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
>> + GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", 0xc324, 0, 0, 0),
>> + GATE(sclk_mixer, "sclk_mixer", "mout_mixer", 0xc324, 4, 0, 0),
>> + GATE(sclk_dac, "sclk_dac", "mout_dac", 0xc324, 8, 0, 0),
>> + GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0",
>> + 0xc334, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
>> + GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0",
>> + 0xc334, 12, CLK_SET_RATE_PARENT, 0),
>> + GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc-pre0",
>> + 0xc340, 0, CLK_SET_RATE_PARENT, 0, "mmc_busclk.2"),
>> + GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc-pre1",
>> + 0xc340, 4, CLK_SET_RATE_PARENT, 0, "mmc_busclk.2"),
>> + GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc-pre2",
>> + 0xc340, 8, CLK_SET_RATE_PARENT, 0, "mmc_busclk.2"),
>> + GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc-pre3",
>> + 0xc340, 12, CLK_SET_RATE_PARENT, 0, "mmc_busclk.2"),
>> + GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc-pre4",
>> + 0xc340, 16, CLK_SET_RATE_PARENT, 0, "ciu"),
>> + GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0",
>> + 0xc350, 0, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
>> + GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1",
>> + 0xc350, 4, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
>> + GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2",
>> + 0xc350, 8, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
>> + GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3",
>> + 0xc350, 12, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
>> + GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4",
>> + 0xc350, 16, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
>> + GATE(sclk_audio1, "sclk_audio1", "div_audio1", 0xc354, 0,
>> CLK_SET_RATE_PARENT, 0), + GATE(sclk_audio2, "sclk_audio2",
>> "div_audio2", 0xc354, 4, CLK_SET_RATE_PARENT, 0), + GATE(sclk_spdif,
>> "sclk_spdif", "mout_spdif", 0xc354, 8, 0, 0), + GATE_DA(sclk_spi0,
>> "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0", +
> 0xc354, 16,
>> CLK_SET_RATE_PARENT, 0, "spi_busclk0"),
>> + GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1",
>> + 0xc354, 20, CLK_SET_RATE_PARENT, 0, "spi_busclk0"),
>> + GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2",
>> + 0xc354, 24, CLK_SET_RATE_PARENT, 0, "spi_busclk0"),
>> + GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160", 0xc920, 0, 0,
> 0,
>> "fimc"), + GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160",
> 0xc920,
>> 1, 0, 0, "fimc"), + GATE_DA(fimc2, "exynos4-fimc.2", "fimc2",
>> "aclk160", 0xc920, 2, 0, 0, "fimc"), + GATE_DA(fimc3, "exynos4-
> fimc.3",
>> "fimc3", "aclk160", 0xc920, 3, 0, 0, "fimc"), + GATE_DA(csis0,
>> "s5p-mipi-csis.0", "csis0", "aclk160", 0xc920, 4, 0, 0, "fimc"),
>> + GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160", 0xc920, 5, 0,
>> 0, "fimc"), + GATE(jpeg, "jpeg", "aclk160", 0xc920, 6, 0, 0),
>> + GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160",
>> + 0xc920, 7, 0, 0, "sysmmu"),
>> + GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160",
>> + 0xc920, 8, 0, 0, "sysmmu"),
>> + GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160",
>> + 0xc920, 9, 0, 0, "sysmmu"),
>> + GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160",
>> + 0xc920, 10, 0, 0, "sysmmu"),
>> + GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160",
> 0xc920,
>> 11, 0, 0, "sysmmu"), + GATE_D(vp, "s5p-mixer", "vp", "aclk160",
> 0xc924,
>> 0, 0, 0),
>> + GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", 0xc924, 1, 0, 0),
>> + GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", 0xc924, 3, 0, 0),
>> + GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160", 0xc924, 4,
>> 0, 0, "sysmmu"), + GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", 0xc928,
> 0,
>> 0, 0, "mfc"), + GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl",
>> "aclk100", 0xc928, 1, 0, 0, "sysmmu"), + GATE_DA(smmu_mfcr,
>> "exynos-sysmmu.1", "smmu_mfcr", "aclk100", 0xc928, 2, 0, 0, "sysmmu"),
>> + GATE(g3d, "g3d", "aclk200", 0xc92c, 0, 0, 0),
>> + GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160", 0xc934, 0, 0, 0,
>> "fimd"), + GATE(mie0, "mie0", "aclk160", 0xc934, 1, 0, 0),
>> + GATE(dsim0, "dsim0", "aclk160", 0xc934, 3, 0, 0),
>> + GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160",
>> + 0xc934, 4, 0, 0, "sysmmu"),
>> + GATE(fimd1, "fimd1", "aclk160", 0xc938, 0, 0, 0),
>> + GATE(mie1, "mie1", "aclk160", 0xc938, 1, 0, 0),
>> + GATE(dsim1, "dsim1", "aclk160", 0xc938, 3, 0, 0),
>> + GATE(smmu_fimd1, "smmu_fimd1", "aclk160", 0xc938, 4, 0, 0),
>> + GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133", 0xc940, 0, 0, 0,
>> "dma"), + GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133", 0xc940, 1,
>> 0, 0, "dma"), + GATE(tsi, "tsi", "aclk133", 0xc940, 4, 0, 0),
>> + GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133", 0xc940, 5,
> 0,
>> 0, "hsmmc"), + GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133",
>> 0xc940, 6, 0, 0, "hsmmc"), + GATE_DA(sdmmc2, "exynos4-sdhci.2",
>> "sdmmc2", "aclk133", 0xc940, 7, 0, 0, "hsmmc"), + GATE_DA(sdmmc3,
>> "exynos4-sdhci.3", "sdmmc3", "aclk133", 0xc940, 8, 0, 0, "hsmmc"),
>> + GATE_A(sdmmc4, "sdmmc4", "aclk133", 0xc940, 9, 0, 0, "biu"),
>> + GATE(sromc, "sromc", "aclk133", 0xc940, 11, 0, 0),
>> + GATE_A(usb_host, "usb_host", "aclk133", 0xc940, 12, 0, 0,
> "usbhost"),
>> + GATE(usb_device, "usb_device", "aclk133", 0xc940, 13, 0, 0),
>> + GATE(onenand, "onenand", "aclk133", 0xc940, 15, 0, 0),
>> + GATE(nfcon, "nfcon", "aclk133", 0xc940, 16, 0, 0),
>> + GATE(gps, "gps", "aclk133", 0xc94c, 0, 0, 0),
>> + GATE(smmu_gps, "smmu_gps", "aclk133", 0xc94c, 1, 0, 0),
>> + GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100", 0xc950, 0,
> 0,
>> 0, "uart"), + GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100",
>> 0xc950, 1, 0, 0, "uart"), + GATE_DA(uart2, "exynos4210-uart.2",
>> "uart2", "aclk100", 0xc950, 2, 0, 0, "uart"), + GATE_DA(uart3,
>> "exynos4210-uart.3", "uart3", "aclk100", 0xc950, 3, 0, 0, "uart"),
>> + GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100", 0xc950, 4,
> 0,
>> 0, "uart"), + GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100", 0xc950,
>> 6, 0, 0, "i2c"), + GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100",
>> 0xc950, 7, 0, 0, "i2c"), + GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2",
>> "aclk100", 0xc950, 8, 0, 0, "i2c"), + GATE_DA(i2c3, "s3c2440-i2c.3",
>> "i2c3", "aclk100", 0xc950, 9, 0, 0, "i2c"), + GATE_DA(i2c4,
>> "s3c2440-i2c.4", "i2c4", "aclk100", 0xc950, 10, 0, 0, "i2c"),
>> + GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100", 0xc950, 11, 0, 0,
>> "i2c"), + GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100", 0xc950, 12,
>> 0, 0, "i2c"), + GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100",
>> 0xc950, 13, 0, 0, "i2c"), + GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c",
>> "i2c-hdmi", "aclk100", 0xc950, 14, 0, 0, "i2c"), + GATE_DA(spi0,
>> "exynos4210-spi.0", "spi0", "aclk100", 0xc950, 16, 0, 0, "spi"),
>> + GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100", 0xc950, 17, 0,
>> 0, "spi"), + GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100",
>> 0xc950, 18, 0, 0, "spi"), + GATE_DA(i2s1, "samsung-i2s.1", "i2s1",
>> "aclk100", 0xc950, 20, 0, 0, "iis"), + GATE_DA(i2s2, "samsung-
> i2s.2",
>> "i2s2", "aclk100", 0xc950, 21, 0, 0, "iis"), + GATE_DA(pcm1,
>> "samsung-pcm.1", "pcm1", "aclk100", 0xc950, 22, 0, 0, "pcm"),
>> + GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100", 0xc950, 23, 0, 0,
>> "pcm"), + GATE_A(pwm, "pwm", "aclk100", 0xc950, 24, 0, 0, "timers"),
>> + GATE(slimbus, "slimbus", "aclk100", 0xc950, 25, 0, 0),
>> + GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100", 0xc950, 26, 0,
> 0,
>> "spdif"), + GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100", 0xc950,
>> 27, 0, 0, "ac97"), +};
>> +
>> +/* list of gate clocks supported in exynos4210 soc */
>> +struct samsung_gate_clock exynos4210_gate_clks[] = {
>> + GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",
>> + 0xc338, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
>> + GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1", 0xc338, 12,
>> CLK_SET_RATE_PARENT, 0), + GATE(sclk_sata, "sclk_sata", "div_sata",
>> 0xc340, 24, CLK_SET_RATE_PARENT, 0), + GATE(sclk_cam0, "sclk_cam0",
>> "div_cam0", 0xc820, 4, CLK_SET_RATE_PARENT, 0), + GATE(sclk_cam1,
>> "sclk_cam1", "div_cam1", 0xc820, 5, CLK_SET_RATE_PARENT, 0),
>> + GATE(tvenc, "tvenc", "aclk160", 0xc924, 2, 0, 0),
>> + GATE(g2d, "g2d", "aclk200", 0xc930, 0, 0, 0),
>> + GATE(rotator, "rotator", "aclk200", 0xc930, 1, 0, 0),
>> + GATE(mdma, "mdma", "aclk200", 0xc930, 2, 0, 0),
>> + GATE(smmu_g2d, "smmu_g2d", "aclk200", 0xc930, 3, 0, 0),
>> + GATE(smmu_rotator, "smmu_rotator", "aclk200", 0xc930, 4, 0, 0),
>> + GATE(smmu_mdma, "smmu_mdma", "aclk200", 0xc930, 5, 0, 0),
>> + GATE(pcie_phy, "pcie_phy", "aclk133", 0xc940, 2, 0, 0),
>> + GATE(sata_phy, "sata_phy", "aclk133", 0xc940, 3, 0, 0),
>> + GATE(sata, "sata", "aclk133", 0xc940, 10, 0, 0),
>> + GATE(pcie, "pcie", "aclk133", 0xc940, 14, 0, 0),
>> + GATE(smmu_pcie, "smmu_pcie", "aclk133", 0xc940, 18, 0, 0),
>> + GATE_A(tsadc, "tsadc", "aclk100", 0xc950, 15, 0, 0, "adc"),
>> + GATE(modemif, "modemif", "aclk100", 0xc950, 28, 0, 0),
>> + GATE(chipid, "chipid", "aclk100", 0xc960, 0, 0, 0),
>> + GATE(sysreg, "sysreg", "aclk100", 0xc960, 0, 0, 0),
>> + GATE(hdmi_cec, "hdmi_cec", "aclk100", 0xc960, 11, 0, 0),
>> + GATE_A(mct, "mct", "aclk100", 0xc960, 13, 0, 0, "mct"),
>> + GATE_A(wdt, "watchdog", "aclk100", 0xc960, 14, 0, 0, "watchdog"),
>> + GATE_A(rtc, "rtc", "aclk100", 0xc960, 15, 0, 0, "rtc"),
>> + GATE_A(keyif, "keyif", "aclk100", 0xc960, 16, 0, 0, "keypad"),
>> +};
>> +
>> +/* list of gate clocks supported in exynos4x12 soc */
>> +struct samsung_gate_clock exynos4x12_gate_clks[] = {
>> + GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0", 0xc334, 4,
>> CLK_SET_RATE_PARENT, 0), + GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0",
>> "div_mdnie_pwm_pre0", + 0xc334, 8, CLK_SET_RATE_PARENT,
> 0),
>> + GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi", 0xc340, 24,
>> CLK_SET_RATE_PARENT, 0), + GATE(audss, "audss", "sclk_epll", 0xc93c, 0,
>> 0, 0),
>> + GATE(mdnie0, "mdnie0", "aclk160", 0xc934, 2, 0, 0),
>> + GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100", 0xc93c, 2, 0, 0,
>> "pcm"), + GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100", 0xc93c, 3,
>> 0, 0, "iis"), + GATE(mipi_hsi, "mipi_hsi", "aclk133", 0xc940, 10, 0,
>> 0),
>> + GATE(chipid, "chipid", "aclk100", 0x8960, 0, 0, 0),
>> + GATE(sysreg, "sysreg", "aclk100", 0x8960, 1, 0, 0),
>> + GATE(hdmi_cec, "hdmi_cec", "aclk100", 0x8960, 11, 0, 0),
>> + GATE_A(mct, "mct", "aclk100", 0x8960, 13, 0, 0, "mct"),
>> + GATE_A(wdt, "watchdog", "aclk100", 0x8960, 14, 0, 0, "watchdog"),
>> + GATE_A(rtc, "rtc", "aclk100", 0x8960, 15, 0, 0, "rtc"),
>> + GATE_A(keyif, "keyif", "aclk100", 0x8960, 16, 0, 0, "keypad"),
>> + GATE(rotator, "rotator", "aclk200", 0x4930, 1, 0, 0),
>> + GATE(mdma2, "mdma2", "aclk200", 0x4930, 2, 0, 0),
>> + GATE(smmu_rotator, "smmu_rotator", "aclk200", 0x4930, 4, 0, 0),
>> + GATE(smmu_mdma, "smmu_mdma", "aclk200", 0x4930, 5, 0, 0),
>> +};
>> +
>> +static struct of_device_id exynos4_clk_ids[] = {
>> + { .compatible = "samsung,exynos4210-clock",
>> + .data = (void *)EXYNOS4210, },
>> + { .compatible = "samsung,exynos4412-clock",
>> + .data = (void *)EXYNOS4X12, },
>> + { },
>> +};
>
> I wonder if most of these static arrays couldn't be marked as initdata to
> be dropped after initialization.
Yes, that's right. These can be marked as initdata.
>
> Correct me if I'm wrong, but from what I see these data are referenced by
> common clock framework core only when registering these clocks.
Yes, that's correct.
Thanks,
Thomas.
^ permalink raw reply
* [PATCH V3 0/5] SMP support for Armada XP
From: Hui Wang @ 2012-11-15 8:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352931637-3405-1-git-send-email-gregory.clement@free-electrons.com>
Sorry for asking a question. Does it support CPU HOTPLUG? I am just
testing the marvell 2012_Q4.1, and found the CPU HOTPLUG (echo 0|1 >
/sys/devices/system/cpu/cpu1/online) doesn't work on the XP_GP board,
does your BSP have the same problem?
Regards,
Hui.
Gregory CLEMENT wrote:
> Hello,
>
> The purpose of this patch set is to add the SMP support for the Armada
> XP SoCs. Beside the SMP support itself brought by the last 3 patches,
> this patch set also adds the support for the coherency fabric unit and
>
^ permalink raw reply
* Fwd: [PATCH 1/7] I2c-nomadik: Fix the usage of wait_for_completion_timeout
From: Srinidhi Kasagar @ 2012-11-15 8:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdYekQF5111NSNSPeaHdxgS_gpXkCjqT1n-n1_iAdDXbSg@mail.gmail.com>
[...]
> From: Chuansheng Liu <chuansheng.liu@intel.com>
> Date: Tue, Nov 6, 2012 at 6:18 PM
> Subject: [PATCH 1/7] I2c-nomadik: Fix the usage of wait_for_completion_timeout
> To: linus.walleij at linaro.org, w.sang at pengutronix.de
> Cc: linux-arm-kernel at lists.infradead.org,
> linux-kernel at vger.kernel.org, chuansheng.liu at intel.com
>
>
>
> The return value of wait_for_completion_timeout() is always
> >= 0 with unsigned int type.
>
> So the condition "ret < 0" or "ret >= 0" is pointless.
>
> Signed-off-by: liu chuansheng <chuansheng.liu@intel.com>
> ---
> drivers/i2c/busses/i2c-nomadik.c | 14 --------------
> 1 files changed, 0 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
> index 02c3115..8b2ffcf 100644
> --- a/drivers/i2c/busses/i2c-nomadik.c
> +++ b/drivers/i2c/busses/i2c-nomadik.c
> @@ -435,13 +435,6 @@ static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
> timeout = wait_for_completion_timeout(
> &dev->xfer_complete, dev->adap.timeout);
>
> - if (timeout < 0) {
> - dev_err(&dev->adev->dev,
> - "wait_for_completion_timeout "
> - "returned %d waiting for event\n", timeout);
> - status = timeout;
> - }
> -
No, it is wrong. You need to update the status variable in the case of timeout.
It is used further in nmk_i2c_xfer_one. You could perhaps use
if (timeout == 0) {
...and the rest of the code as is
}
regards/srinidhi
^ permalink raw reply
* [PATCHv3] i2c: omap: Move the remove constraint
From: Shubhrajyoti D @ 2012-11-15 8:49 UTC (permalink / raw)
To: linux-arm-kernel
Currently we just queue the transfer and release the
qos constraints, however we do not wait for the transfer
to complete to release the constraint. Move the remove
constraint after the bus busy as we are sure that the
transfers are completed by then.
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
---
v2: rebase to the for-next branch
v3: Fix a typo
drivers/i2c/busses/i2c-omap.c | 7 ++++---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 482c63d..fabcbe1 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -654,13 +654,14 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
break;
}
- if (dev->set_mpu_wkup_lat != NULL)
- dev->set_mpu_wkup_lat(dev->dev, -1);
-
if (r == 0)
r = num;
omap_i2c_wait_for_bb(dev);
+
+ if (dev->set_mpu_wkup_lat != NULL)
+ dev->set_mpu_wkup_lat(dev->dev, -1);
+
out:
pm_runtime_mark_last_busy(dev->dev);
pm_runtime_put_autosuspend(dev->dev);
--
1.7.5.4
^ permalink raw reply related
* [PATCH 1/3] OF: Add helper for matching against linux, stdout-path
From: Sascha Hauer @ 2012-11-15 8:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACxGe6uW+XN6RDnP+8QFXaCYqqPZO4dZM_aynR6AVMYZT=KuMg@mail.gmail.com>
On Wed, Nov 14, 2012 at 08:49:54PM +0000, Grant Likely wrote:
> On Fri, Nov 2, 2012 at 9:48 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > devicetrees may have a linux,stdout-path property in the chosen
> > node describing the console device. This adds a helper function
> > to match a device against this property so a driver can call
> > add_preferred_console for a matching device.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > drivers/of/Kconfig | 3 +++
> > drivers/of/Makefile | 1 +
> > drivers/of/of_stdout.c | 27 +++++++++++++++++++++++++++
> > include/linux/of_stdout.h | 24 ++++++++++++++++++++++++
> > 4 files changed, 55 insertions(+)
> > create mode 100644 drivers/of/of_stdout.c
> > create mode 100644 include/linux/of_stdout.h
> >
> > diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
> > index dfba3e6..8574ebb 100644
> > --- a/drivers/of/Kconfig
> > +++ b/drivers/of/Kconfig
> > @@ -67,6 +67,9 @@ config OF_MDIO
> > help
> > OpenFirmware MDIO bus (Ethernet PHY) accessors
> >
> > +config OF_STDOUT
> > + def_bool y
> > +
> > config OF_PCI
> > def_tristate PCI
> > depends on PCI
> > diff --git a/drivers/of/Makefile b/drivers/of/Makefile
> > index e027f44..c9f3f2f 100644
> > --- a/drivers/of/Makefile
> > +++ b/drivers/of/Makefile
> > @@ -8,6 +8,7 @@ obj-$(CONFIG_OF_I2C) += of_i2c.o
> > obj-$(CONFIG_OF_NET) += of_net.o
> > obj-$(CONFIG_OF_SELFTEST) += selftest.o
> > obj-$(CONFIG_OF_MDIO) += of_mdio.o
> > +obj-$(CONFIG_OF_STDOUT) += of_stdout.o
> > obj-$(CONFIG_OF_PCI) += of_pci.o
> > obj-$(CONFIG_OF_PCI_IRQ) += of_pci_irq.o
> > obj-$(CONFIG_OF_MTD) += of_mtd.o
> > diff --git a/drivers/of/of_stdout.c b/drivers/of/of_stdout.c
> > new file mode 100644
> > index 0000000..c9e370e
> > --- /dev/null
> > +++ b/drivers/of/of_stdout.c
> > @@ -0,0 +1,27 @@
> > +/*
> > + * OF helper for linux,stdoutpath property.
> > + *
> > + * This file is released under the GPLv2
> > + */
> > +#include <linux/of_stdout.h>
> > +
> > +/**
> > + * of_device_is_stdout_path - check if a device node matches the
> > + * linux,stdout-path property
> > + *
> > + * Check if this device node matches the linux,stdout-path property
> > + * in the chosen node. return true if yes, false otherwise.
> > + */
> > +int of_device_is_stdout_path(struct device_node *dn)
> > +{
> > + const char *name;
> > +
> > + name = of_get_property(of_chosen, "linux,stdout-path", NULL);
> > + if (name == NULL)
> > + return 0;
> > +
> > + if (dn == of_find_node_by_path(name))
>
> need to of_node_put() the return value of of_find_node_by_path()
>
> > + return 1;
> > +
> > + return 0;
> > +}
>
> Hi Sascha,
>
> I'm fine with the helper, but there really is no need for a completely
> separate .c file. Just put it in drivers/of/base.c.
I guess the same applies to include/linux/of_stdout.h.
Should I drop the CONFIG_OF_STDOUT aswell?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH V3 0/5] SMP support for Armada XP
From: Gregory CLEMENT @ 2012-11-15 8:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A4ABD1.3070902@gmail.com>
Hello Hui,
On 11/15/2012 09:46 AM, Hui Wang wrote:
> Sorry for asking a question. Does it support CPU HOTPLUG? I am just
> testing the marvell 2012_Q4.1, and found the CPU HOTPLUG (echo 0|1 >
> /sys/devices/system/cpu/cpu1/online) doesn't work on the XP_GP board,
> does your BSP have the same problem?
>
Indeed, we don't support it yet, but we plan to add this feature once
this "basic" support will be included in the 3.8.
> Regards,
> Hui.
>
> Gregory CLEMENT wrote:
>> Hello,
>>
>> The purpose of this patch set is to add the SMP support for the Armada
>> XP SoCs. Beside the SMP support itself brought by the last 3 patches,
>> this patch set also adds the support for the coherency fabric unit and
>>
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCHv2] i2c: omap: Move the remove constraint
From: Shubhrajyoti Datta @ 2012-11-15 8:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAORVsuVuOLKpcx085VWiPRaD4syS-5F4+s+eKXGN8PPRRiTg2g@mail.gmail.com>
On Thu, Nov 15, 2012 at 1:46 PM, Jean Pihet <jean.pihet@newoldbits.com> wrote:
> Hi Shubhrajyoti,
>
> On Thu, Nov 15, 2012 at 8:34 AM, Shubhrajyoti D <shubhrajyoti@ti.com> wrote:
>> Currently we just queue the transfer and release the
>> qos constraints, however we donot wait for the transfer
> Typo: donot
Just fixed and resent.
>
>> to complete to release the constraint. Move the remove
>> constraint after the bus busy as we are sure that the
>> transfers are completed by then.
>>
>> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
> Looks good!
> Acked-by: Jean Pihet <j-pihet@ti.com>
Thanks for review.
>
> Regards,
> Jean
>
^ permalink raw reply
* [PATCHv2] i2c: omap: Move the remove constraint
From: Jean Pihet @ 2012-11-15 8:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAM=Q2cvE2=c_L5YhkeXscx=2EfZp5MGtdnp6KowhwUQx_j1Muw@mail.gmail.com>
On Thu, Nov 15, 2012 at 9:51 AM, Shubhrajyoti Datta
<omaplinuxkernel@gmail.com> wrote:
> On Thu, Nov 15, 2012 at 1:46 PM, Jean Pihet <jean.pihet@newoldbits.com> wrote:
>> Hi Shubhrajyoti,
>>
>> On Thu, Nov 15, 2012 at 8:34 AM, Shubhrajyoti D <shubhrajyoti@ti.com> wrote:
>>> Currently we just queue the transfer and release the
>>> qos constraints, however we donot wait for the transfer
>> Typo: donot
> Just fixed and resent.
>
>>
>>> to complete to release the constraint. Move the remove
>>> constraint after the bus busy as we are sure that the
>>> transfers are completed by then.
>>>
>>> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
>> Looks good!
>> Acked-by: Jean Pihet <j-pihet@ti.com>
>
> Thanks for review.
Thanks!
Regards,
Jean
>
>>
>> Regards,
>> Jean
>>
^ permalink raw reply
* [PATCH V3 0/5] SMP support for Armada XP
From: Hui Wang @ 2012-11-15 8:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A4ACC5.4040209@free-electrons.com>
Gregory CLEMENT wrote:
> Hello Hui,
>
> On 11/15/2012 09:46 AM, Hui Wang wrote:
>
>> Sorry for asking a question. Does it support CPU HOTPLUG? I am just
>> testing the marvell 2012_Q4.1, and found the CPU HOTPLUG (echo 0|1 >
>> /sys/devices/system/cpu/cpu1/online) doesn't work on the XP_GP board,
>> does your BSP have the same problem?
>>
>>
>
> Indeed, we don't support it yet, but we plan to add this feature once
> this "basic" support will be included in the 3.8.
>
>
Got it, thanks.
>> Regards,
>> Hui.
>>
>> Gregory CLEMENT wrote:
>>
>>> Hello,
>>>
>>> The purpose of this patch set is to add the SMP support for the Armada
>>> XP SoCs. Beside the SMP support itself brought by the last 3 patches,
>>> this patch set also adds the support for the coherency fabric unit and
>>>
>>>
>
>
>
^ permalink raw reply
* [PATCH v3 05/11] ARM: dts: add exynos4 clock controller nodes
From: Thomas Abraham @ 2012-11-15 8:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4979279.mb3rWrdaG3@flatron>
On 15 November 2012 04:57, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> On Thursday 15 of November 2012 03:37:27 Thomas Abraham wrote:
>> Add clock controller nodes for Exynos4210 and Exynos4x12 SoC's.
>>
>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> arch/arm/boot/dts/exynos4210.dtsi | 6 ++++++
>> arch/arm/boot/dts/exynos4x12.dtsi | 6 ++++++
>> 2 files changed, 12 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos4210.dtsi
>> b/arch/arm/boot/dts/exynos4210.dtsi index d6fc306..f7daa09 100644
>> --- a/arch/arm/boot/dts/exynos4210.dtsi
>> +++ b/arch/arm/boot/dts/exynos4210.dtsi
>> @@ -50,6 +50,12 @@
>> samsung,mct-nr-local-irqs = <4>;
>> };
>>
>> + clock: clock-controller at 0x10030000 {
>> + compatible = "samsung,exynos4210-clock";
>> + reg = <0x10030000 0x20000>;
>> + #clock-cells = <1>;
>> + };
>> +
>> pinctrl_0: pinctrl at 11400000 {
>> compatible = "samsung,pinctrl-exynos4210";
>> reg = <0x11400000 0x1000>;
>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
>> b/arch/arm/boot/dts/exynos4x12.dtsi index 7cbbd19..bcfdaac 100644
>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>> @@ -35,6 +35,12 @@
>> <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
>> };
>>
>> + clock: clock-controller at 0x10030000 {
>> + compatible = "samsung,exynos4412-clock";
>
> nitpick: I forgot to mention about it in my comments for patch 3, but
> wouldn't it be better to call it "samsung,exynos4x12-clock"?
I prefer to use a specific version for compatible strings. I remember
that there have been discussion in the past on this, but I belong to
the camp which favors using fixed compatible values over wildcards in
compatible values. It is easier to track and less problematic in case
a new Exynos4x12 SoC comes up with altogether a different clock
architecture. We have used this method for wdt, rtc, i2c and many
other drivers and it has proven to be suit well. For instance, for
i2c, we have two variants - s3c2410 and s3c2440 and we can use this
most of all the Samsung SoCs.
>
>> + reg = <0x10030000 0x20000>;
>> + #clock-cells = <1>;
>> + };
>> +
>> pinctrl_0: pinctrl at 11400000 {
>> compatible = "samsung,pinctrl-exynos4x12";
>> reg = <0x11400000 0x1000>;
>
> Otherwise looks fine.
Thanks,
Thomas.
^ permalink raw reply
* [PATCH] ARM: pxa: remove pxa95x support
From: Haojian Zhuang @ 2012-11-15 9:06 UTC (permalink / raw)
To: linux-arm-kernel
PXA95x isn't widely used. And it adds the effort on supporting
multiple platform. So remove it.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-pxa/Kconfig | 34 ----
arch/arm/mach-pxa/Makefile | 3 -
arch/arm/mach-pxa/clock.h | 2 +-
arch/arm/mach-pxa/devices.c | 8 +-
arch/arm/mach-pxa/include/mach/hardware.h | 28 ---
arch/arm/mach-pxa/include/mach/irqs.h | 1 -
arch/arm/mach-pxa/include/mach/pxa3xx.h | 1 -
arch/arm/mach-pxa/include/mach/pxa95x.h | 7 -
arch/arm/mach-pxa/pxa95x.c | 295 -----------------------------
arch/arm/mach-pxa/saarb.c | 115 -----------
arch/arm/mach-pxa/tavorevb3.c | 136 -------------
arch/arm/plat-pxa/Makefile | 1 -
arch/arm/plat-pxa/include/plat/mfp.h | 4 +-
drivers/gpio/gpio-pxa.c | 2 +-
15 files changed, 9 insertions(+), 630 deletions(-)
delete mode 100644 arch/arm/mach-pxa/include/mach/pxa95x.h
delete mode 100644 arch/arm/mach-pxa/pxa95x.c
delete mode 100644 arch/arm/mach-pxa/saarb.c
delete mode 100644 arch/arm/mach-pxa/tavorevb3.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ade7e92..5c7e94f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1168,7 +1168,7 @@ config ARM_NR_BANKS
config IWMMXT
bool "Enable iWMMXt support"
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
- default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
+ default y if PXA27x || PXA3xx || ARCH_MMP
help
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 11aa739..86eec41 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -2,27 +2,6 @@ if ARCH_PXA
menu "Intel PXA2xx/PXA3xx Implementations"
-config ARCH_PXA_V7
- bool "ARMv7 (PXA95x) based systems"
-
-if ARCH_PXA_V7
-comment "Marvell Dev Platforms (sorted by hardware release time)"
-config MACH_TAVOREVB3
- bool "PXA95x Development Platform (aka TavorEVB III)"
- select CPU_PXA955
-
-config MACH_SAARB
- bool "PXA955 Handheld Platform (aka SAARB)"
- select CPU_PXA955
-endif
-
-config PXA_V7_MACH_AUTO
- def_bool y
- depends on ARCH_PXA_V7
- depends on !MACH_SAARB
- select MACH_TAVOREVB3
-
-if !ARCH_PXA_V7
comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
config MACH_PXA3XX_DT
@@ -630,7 +609,6 @@ config MACH_ZIPIT2
bool "Zipit Z2 Handheld"
select HAVE_PWM
select PXA27x
-endif
endmenu
config PXA25x
@@ -688,18 +666,6 @@ config CPU_PXA935
help
PXA935 (codename Tavor-P65)
-config PXA95x
- bool
- select CPU_PJ4
- help
- Select code specific to PXA95x variants
-
-config CPU_PXA955
- bool
- select PXA95x
- help
- PXA950 (codename MG1)
-
config PXA_SHARP_C7xx
bool
select SHARPSL_PM
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index ee88d6e..12c5005 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -19,7 +19,6 @@ endif
obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o
obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o
obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
-obj-$(CONFIG_PXA95x) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o pxa95x.o smemc.o
obj-$(CONFIG_CPU_PXA300) += pxa300.o
obj-$(CONFIG_CPU_PXA320) += pxa320.o
obj-$(CONFIG_CPU_PXA930) += pxa930.o
@@ -36,9 +35,7 @@ obj-$(CONFIG_MACH_ZYLONITE300) += zylonite.o zylonite_pxa300.o
obj-$(CONFIG_MACH_ZYLONITE320) += zylonite.o zylonite_pxa320.o
obj-$(CONFIG_MACH_LITTLETON) += littleton.o
obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
-obj-$(CONFIG_MACH_TAVOREVB3) += tavorevb3.o
obj-$(CONFIG_MACH_SAAR) += saar.o
-obj-$(CONFIG_MACH_SAARB) += saarb.o
# 3rd Party Dev Platforms
obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 3a258b1..1f65d32 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -57,7 +57,7 @@ void clk_pxa2xx_cken_disable(struct clk *clk);
extern struct syscore_ops pxa2xx_clock_syscore_ops;
-#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
+#if defined(CONFIG_PXA3xx)
#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \
struct clk clk_##_name = { \
.ops = &clk_pxa3xx_cken_ops, \
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index ddaa04d..daa86d3 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -703,7 +703,7 @@ void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
}
#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
static struct resource pxa27x_resource_keypad[] = {
[0] = {
.start = 0x41500000,
@@ -872,7 +872,7 @@ struct platform_device pxa27x_device_pwm1 = {
.resource = pxa27x_resource_pwm1,
.num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
};
-#endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
+#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
#ifdef CONFIG_PXA3xx
static struct resource pxa3xx_resources_mci2[] = {
@@ -981,7 +981,7 @@ struct platform_device pxa3xx_device_gcu = {
#endif /* CONFIG_PXA3xx */
-#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
+#if defined(CONFIG_PXA3xx)
static struct resource pxa3xx_resources_i2c_power[] = {
{
.start = 0x40f500c0,
@@ -1082,7 +1082,7 @@ struct platform_device pxa3xx_device_ssp4 = {
.resource = pxa3xx_resource_ssp4,
.num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
};
-#endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
+#endif /* CONFIG_PXA3xx */
struct resource pxa_resource_gpio[] = {
{
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 56d92e5..ccb06e4 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -194,17 +194,6 @@
#define __cpu_is_pxa935(id) (0)
#endif
-#ifdef CONFIG_CPU_PXA955
-#define __cpu_is_pxa955(id) \
- ({ \
- unsigned int _id = (id) >> 4 & 0xfff; \
- _id == 0x581 || _id == 0xc08 \
- || _id == 0xb76; \
- })
-#else
-#define __cpu_is_pxa955(id) (0)
-#endif
-
#define cpu_is_pxa210() \
({ \
__cpu_is_pxa210(read_cpuid_id()); \
@@ -255,10 +244,6 @@
__cpu_is_pxa935(read_cpuid_id()); \
})
-#define cpu_is_pxa955() \
- ({ \
- __cpu_is_pxa955(read_cpuid_id()); \
- })
/*
@@ -297,15 +282,6 @@
#define __cpu_is_pxa93x(id) (0)
#endif
-#ifdef CONFIG_PXA95x
-#define __cpu_is_pxa95x(id) \
- ({ \
- __cpu_is_pxa955(id); \
- })
-#else
-#define __cpu_is_pxa95x(id) (0)
-#endif
-
#define cpu_is_pxa2xx() \
({ \
__cpu_is_pxa2xx(read_cpuid_id()); \
@@ -321,10 +297,6 @@
__cpu_is_pxa93x(read_cpuid_id()); \
})
-#define cpu_is_pxa95x() \
- ({ \
- __cpu_is_pxa95x(read_cpuid_id()); \
- })
/*
* return current memory and LCD clock frequency in units of 10kHz
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index 8765782..48c2fd8 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -84,7 +84,6 @@
#define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */
#define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */
#define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */
-#define IRQ_PXA955_MMC3 PXA_IRQ(75) /* MMC3 Controller (PXA955) */
#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */
#define PXA_GPIO_IRQ_BASE PXA_IRQ(96)
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx.h b/arch/arm/mach-pxa/include/mach/pxa3xx.h
index cd3e57f..6dd7fa1 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx.h
@@ -7,7 +7,6 @@
extern void __init pxa3xx_map_io(void);
extern void __init pxa3xx_init_irq(void);
-extern void __init pxa95x_init_irq(void);
#define pxa3xx_handle_irq ichp_handle_irq
diff --git a/arch/arm/mach-pxa/include/mach/pxa95x.h b/arch/arm/mach-pxa/include/mach/pxa95x.h
deleted file mode 100644
index cbb097c..0000000
--- a/arch/arm/mach-pxa/include/mach/pxa95x.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_PXA95X_H
-#define __MACH_PXA95X_H
-
-#include <mach/pxa3xx.h>
-#include <mach/mfp-pxa930.h>
-
-#endif /* __MACH_PXA95X_H */
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
deleted file mode 100644
index 47601f8..0000000
--- a/arch/arm/mach-pxa/pxa95x.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/pxa95x.c
- *
- * code specific to PXA95x aka MGx
- *
- * Copyright (C) 2009-2010 Marvell International Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pm.h>
-#include <linux/platform_device.h>
-#include <linux/i2c/pxa-i2c.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
-#include <mach/pxa930.h>
-#include <mach/reset.h>
-#include <mach/pm.h>
-#include <mach/dma.h>
-
-#include "generic.h"
-#include "devices.h"
-#include "clock.h"
-
-static struct mfp_addr_map pxa95x_mfp_addr_map[] __initdata = {
-
- MFP_ADDR(GPIO0, 0x02e0),
- MFP_ADDR(GPIO1, 0x02dc),
- MFP_ADDR(GPIO2, 0x02e8),
- MFP_ADDR(GPIO3, 0x02d8),
- MFP_ADDR(GPIO4, 0x02e4),
- MFP_ADDR(GPIO5, 0x02ec),
- MFP_ADDR(GPIO6, 0x02f8),
- MFP_ADDR(GPIO7, 0x02fc),
- MFP_ADDR(GPIO8, 0x0300),
- MFP_ADDR(GPIO9, 0x02d4),
- MFP_ADDR(GPIO10, 0x02f4),
- MFP_ADDR(GPIO11, 0x02f0),
- MFP_ADDR(GPIO12, 0x0304),
- MFP_ADDR(GPIO13, 0x0310),
- MFP_ADDR(GPIO14, 0x0308),
- MFP_ADDR(GPIO15, 0x030c),
- MFP_ADDR(GPIO16, 0x04e8),
- MFP_ADDR(GPIO17, 0x04f4),
- MFP_ADDR(GPIO18, 0x04f8),
- MFP_ADDR(GPIO19, 0x04fc),
- MFP_ADDR(GPIO20, 0x0518),
- MFP_ADDR(GPIO21, 0x051c),
- MFP_ADDR(GPIO22, 0x04ec),
- MFP_ADDR(GPIO23, 0x0500),
- MFP_ADDR(GPIO24, 0x04f0),
- MFP_ADDR(GPIO25, 0x0504),
- MFP_ADDR(GPIO26, 0x0510),
- MFP_ADDR(GPIO27, 0x0514),
- MFP_ADDR(GPIO28, 0x0520),
- MFP_ADDR(GPIO29, 0x0600),
- MFP_ADDR(GPIO30, 0x0618),
- MFP_ADDR(GPIO31, 0x0610),
- MFP_ADDR(GPIO32, 0x060c),
- MFP_ADDR(GPIO33, 0x061c),
- MFP_ADDR(GPIO34, 0x0620),
- MFP_ADDR(GPIO35, 0x0628),
- MFP_ADDR(GPIO36, 0x062c),
- MFP_ADDR(GPIO37, 0x0630),
- MFP_ADDR(GPIO38, 0x0634),
- MFP_ADDR(GPIO39, 0x0638),
- MFP_ADDR(GPIO40, 0x063c),
- MFP_ADDR(GPIO41, 0x0614),
- MFP_ADDR(GPIO42, 0x0624),
- MFP_ADDR(GPIO43, 0x0608),
- MFP_ADDR(GPIO44, 0x0604),
- MFP_ADDR(GPIO45, 0x050c),
- MFP_ADDR(GPIO46, 0x0508),
- MFP_ADDR(GPIO47, 0x02bc),
- MFP_ADDR(GPIO48, 0x02b4),
- MFP_ADDR(GPIO49, 0x02b8),
- MFP_ADDR(GPIO50, 0x02c8),
- MFP_ADDR(GPIO51, 0x02c0),
- MFP_ADDR(GPIO52, 0x02c4),
- MFP_ADDR(GPIO53, 0x02d0),
- MFP_ADDR(GPIO54, 0x02cc),
- MFP_ADDR(GPIO55, 0x029c),
- MFP_ADDR(GPIO56, 0x02a0),
- MFP_ADDR(GPIO57, 0x0294),
- MFP_ADDR(GPIO58, 0x0298),
- MFP_ADDR(GPIO59, 0x02a4),
- MFP_ADDR(GPIO60, 0x02a8),
- MFP_ADDR(GPIO61, 0x02b0),
- MFP_ADDR(GPIO62, 0x02ac),
- MFP_ADDR(GPIO63, 0x0640),
- MFP_ADDR(GPIO64, 0x065c),
- MFP_ADDR(GPIO65, 0x0648),
- MFP_ADDR(GPIO66, 0x0644),
- MFP_ADDR(GPIO67, 0x0674),
- MFP_ADDR(GPIO68, 0x0658),
- MFP_ADDR(GPIO69, 0x0654),
- MFP_ADDR(GPIO70, 0x0660),
- MFP_ADDR(GPIO71, 0x0668),
- MFP_ADDR(GPIO72, 0x0664),
- MFP_ADDR(GPIO73, 0x0650),
- MFP_ADDR(GPIO74, 0x066c),
- MFP_ADDR(GPIO75, 0x064c),
- MFP_ADDR(GPIO76, 0x0670),
- MFP_ADDR(GPIO77, 0x0678),
- MFP_ADDR(GPIO78, 0x067c),
- MFP_ADDR(GPIO79, 0x0694),
- MFP_ADDR(GPIO80, 0x069c),
- MFP_ADDR(GPIO81, 0x06a0),
- MFP_ADDR(GPIO82, 0x06a4),
- MFP_ADDR(GPIO83, 0x0698),
- MFP_ADDR(GPIO84, 0x06bc),
- MFP_ADDR(GPIO85, 0x06b4),
- MFP_ADDR(GPIO86, 0x06b0),
- MFP_ADDR(GPIO87, 0x06c0),
- MFP_ADDR(GPIO88, 0x06c4),
- MFP_ADDR(GPIO89, 0x06ac),
- MFP_ADDR(GPIO90, 0x0680),
- MFP_ADDR(GPIO91, 0x0684),
- MFP_ADDR(GPIO92, 0x0688),
- MFP_ADDR(GPIO93, 0x0690),
- MFP_ADDR(GPIO94, 0x068c),
- MFP_ADDR(GPIO95, 0x06a8),
- MFP_ADDR(GPIO96, 0x06b8),
- MFP_ADDR(GPIO97, 0x0410),
- MFP_ADDR(GPIO98, 0x0418),
- MFP_ADDR(GPIO99, 0x041c),
- MFP_ADDR(GPIO100, 0x0414),
- MFP_ADDR(GPIO101, 0x0408),
- MFP_ADDR(GPIO102, 0x0324),
- MFP_ADDR(GPIO103, 0x040c),
- MFP_ADDR(GPIO104, 0x0400),
- MFP_ADDR(GPIO105, 0x0328),
- MFP_ADDR(GPIO106, 0x0404),
-
- MFP_ADDR(GPIO159, 0x0524),
- MFP_ADDR(GPIO163, 0x0534),
- MFP_ADDR(GPIO167, 0x0544),
- MFP_ADDR(GPIO168, 0x0548),
- MFP_ADDR(GPIO169, 0x054c),
- MFP_ADDR(GPIO170, 0x0550),
- MFP_ADDR(GPIO171, 0x0554),
- MFP_ADDR(GPIO172, 0x0558),
- MFP_ADDR(GPIO173, 0x055c),
-
- MFP_ADDR(nXCVREN, 0x0204),
- MFP_ADDR(DF_CLE_nOE, 0x020c),
- MFP_ADDR(DF_nADV1_ALE, 0x0218),
- MFP_ADDR(DF_SCLK_E, 0x0214),
- MFP_ADDR(DF_SCLK_S, 0x0210),
- MFP_ADDR(nBE0, 0x021c),
- MFP_ADDR(nBE1, 0x0220),
- MFP_ADDR(DF_nADV2_ALE, 0x0224),
- MFP_ADDR(DF_INT_RnB, 0x0228),
- MFP_ADDR(DF_nCS0, 0x022c),
- MFP_ADDR(DF_nCS1, 0x0230),
- MFP_ADDR(nLUA, 0x0254),
- MFP_ADDR(nLLA, 0x0258),
- MFP_ADDR(DF_nWE, 0x0234),
- MFP_ADDR(DF_nRE_nOE, 0x0238),
- MFP_ADDR(DF_ADDR0, 0x024c),
- MFP_ADDR(DF_ADDR1, 0x0250),
- MFP_ADDR(DF_ADDR2, 0x025c),
- MFP_ADDR(DF_ADDR3, 0x0260),
- MFP_ADDR(DF_IO0, 0x023c),
- MFP_ADDR(DF_IO1, 0x0240),
- MFP_ADDR(DF_IO2, 0x0244),
- MFP_ADDR(DF_IO3, 0x0248),
- MFP_ADDR(DF_IO4, 0x0264),
- MFP_ADDR(DF_IO5, 0x0268),
- MFP_ADDR(DF_IO6, 0x026c),
- MFP_ADDR(DF_IO7, 0x0270),
- MFP_ADDR(DF_IO8, 0x0274),
- MFP_ADDR(DF_IO9, 0x0278),
- MFP_ADDR(DF_IO10, 0x027c),
- MFP_ADDR(DF_IO11, 0x0280),
- MFP_ADDR(DF_IO12, 0x0284),
- MFP_ADDR(DF_IO13, 0x0288),
- MFP_ADDR(DF_IO14, 0x028c),
- MFP_ADDR(DF_IO15, 0x0290),
-
- MFP_ADDR(GSIM_UIO, 0x0314),
- MFP_ADDR(GSIM_UCLK, 0x0318),
- MFP_ADDR(GSIM_UDET, 0x031c),
- MFP_ADDR(GSIM_nURST, 0x0320),
-
- MFP_ADDR(PMIC_INT, 0x06c8),
-
- MFP_ADDR(RDY, 0x0200),
-
- MFP_ADDR_END,
-};
-
-static DEFINE_CK(pxa95x_lcd, LCD, &clk_pxa3xx_hsio_ops);
-static DEFINE_CLK(pxa95x_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
-static DEFINE_PXA3_CKEN(pxa95x_ffuart, FFUART, 14857000, 1);
-static DEFINE_PXA3_CKEN(pxa95x_btuart, BTUART, 14857000, 1);
-static DEFINE_PXA3_CKEN(pxa95x_stuart, STUART, 14857000, 1);
-static DEFINE_PXA3_CKEN(pxa95x_i2c, I2C, 32842000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_keypad, KEYPAD, 32768, 0);
-static DEFINE_PXA3_CKEN(pxa95x_ssp1, SSP1, 13000000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_ssp2, SSP2, 13000000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_ssp3, SSP3, 13000000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_ssp4, SSP4, 13000000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_pwm0, PWM0, 13000000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_gpio, GPIO, 13000000, 0);
-
-static struct clk_lookup pxa95x_clkregs[] = {
- INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"),
- /* Power I2C clock is always on */
- INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
- INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL),
- INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL),
- INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL),
- INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-uart.2", NULL),
- INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-ir", "UARTCLK"),
- INIT_CLKREG(&clk_pxa95x_i2c, "pxa2xx-i2c.0", NULL),
- INIT_CLKREG(&clk_pxa95x_keypad, "pxa27x-keypad", NULL),
- INIT_CLKREG(&clk_pxa95x_ssp1, "pxa27x-ssp.0", NULL),
- INIT_CLKREG(&clk_pxa95x_ssp2, "pxa27x-ssp.1", NULL),
- INIT_CLKREG(&clk_pxa95x_ssp3, "pxa27x-ssp.2", NULL),
- INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL),
- INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL),
- INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL),
- INIT_CLKREG(&clk_pxa95x_gpio, "pxa-gpio", NULL),
- INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
-};
-
-void __init pxa95x_init_irq(void)
-{
- pxa_init_irq(96, NULL);
-}
-
-/*
- * device registration specific to PXA93x.
- */
-
-void __init pxa95x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
-{
- pxa_register_device(&pxa3xx_device_i2c_power, info);
-}
-
-static struct platform_device *devices[] __initdata = {
- &pxa_device_gpio,
- &sa1100_device_rtc,
- &pxa_device_rtc,
- &pxa27x_device_ssp1,
- &pxa27x_device_ssp2,
- &pxa27x_device_ssp3,
- &pxa3xx_device_ssp4,
- &pxa27x_device_pwm0,
- &pxa27x_device_pwm1,
-};
-
-static int __init pxa95x_init(void)
-{
- int ret = 0, i;
-
- if (cpu_is_pxa95x()) {
- mfp_init_base(io_p2v(MFPR_BASE));
- mfp_init_addr(pxa95x_mfp_addr_map);
-
- reset_status = ARSR;
-
- /*
- * clear RDH bit every time after reset
- *
- * Note: the last 3 bits DxS are write-1-to-clear so carefully
- * preserve them here in case they will be referenced later
- */
- ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
-
- clkdev_add_table(pxa95x_clkregs, ARRAY_SIZE(pxa95x_clkregs));
-
- if ((ret = pxa_init_dma(IRQ_DMA, 32)))
- return ret;
-
- register_syscore_ops(&pxa_irq_syscore_ops);
- register_syscore_ops(&pxa3xx_clock_syscore_ops);
-
- ret = platform_add_devices(devices, ARRAY_SIZE(devices));
- }
-
- return ret;
-}
-
-postcore_initcall(pxa95x_init);
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
deleted file mode 100644
index 5aded5e..0000000
--- a/arch/arm/mach-pxa/saarb.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/saarb.c
- *
- * Support for the Marvell Handheld Platform (aka SAARB)
- *
- * Copyright (C) 2007-2010 Marvell International Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/i2c.h>
-#include <linux/i2c/pxa-i2c.h>
-#include <linux/mfd/88pm860x.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/mfp.h>
-#include <mach/mfp-pxa930.h>
-#include <mach/pxa95x.h>
-
-#include "generic.h"
-
-#define SAARB_NR_IRQS (IRQ_BOARD_START + 40)
-
-static struct pm860x_touch_pdata saarb_touch = {
- .gpadc_prebias = 1,
- .slot_cycle = 1,
- .tsi_prebias = 6,
- .pen_prebias = 16,
- .pen_prechg = 2,
- .res_x = 300,
-};
-
-static struct pm860x_backlight_pdata saarb_backlight[] = {
- {
- .id = PM8606_ID_BACKLIGHT,
- .iset = PM8606_WLED_CURRENT(24),
- .flags = PM8606_BACKLIGHT1,
- },
- {},
-};
-
-static struct pm860x_led_pdata saarb_led[] = {
- {
- .id = PM8606_ID_LED,
- .iset = PM8606_LED_CURRENT(12),
- .flags = PM8606_LED1_RED,
- }, {
- .id = PM8606_ID_LED,
- .iset = PM8606_LED_CURRENT(12),
- .flags = PM8606_LED1_GREEN,
- }, {
- .id = PM8606_ID_LED,
- .iset = PM8606_LED_CURRENT(12),
- .flags = PM8606_LED1_BLUE,
- }, {
- .id = PM8606_ID_LED,
- .iset = PM8606_LED_CURRENT(12),
- .flags = PM8606_LED2_RED,
- }, {
- .id = PM8606_ID_LED,
- .iset = PM8606_LED_CURRENT(12),
- .flags = PM8606_LED2_GREEN,
- }, {
- .id = PM8606_ID_LED,
- .iset = PM8606_LED_CURRENT(12),
- .flags = PM8606_LED2_BLUE,
- },
-};
-
-static struct pm860x_platform_data saarb_pm8607_info = {
- .touch = &saarb_touch,
- .backlight = &saarb_backlight[0],
- .led = &saarb_led[0],
- .companion_addr = 0x10,
- .irq_mode = 0,
- .irq_base = IRQ_BOARD_START,
-
- .i2c_port = GI2C_PORT,
-};
-
-static struct i2c_board_info saarb_i2c_info[] = {
- {
- .type = "88PM860x",
- .addr = 0x34,
- .platform_data = &saarb_pm8607_info,
- .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
- },
-};
-
-static void __init saarb_init(void)
-{
- pxa_set_ffuart_info(NULL);
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(saarb_i2c_info));
-}
-
-MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)")
- .atag_offset = 0x100,
- .map_io = pxa3xx_map_io,
- .nr_irqs = SAARB_NR_IRQS,
- .init_irq = pxa95x_init_irq,
- .handle_irq = pxa3xx_handle_irq,
- .timer = &pxa_timer,
- .init_machine = saarb_init,
- .restart = pxa_restart,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
deleted file mode 100644
index f7d9305..0000000
--- a/arch/arm/mach-pxa/tavorevb3.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/tavorevb3.c
- *
- * Support for the Marvell EVB3 Development Platform.
- *
- * Copyright: (C) Copyright 2008-2010 Marvell International Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/i2c/pxa-i2c.h>
-#include <linux/gpio.h>
-#include <linux/mfd/88pm860x.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/pxa930.h>
-
-#include "devices.h"
-#include "generic.h"
-
-#define TAVOREVB3_NR_IRQS (IRQ_BOARD_START + 24)
-
-static mfp_cfg_t evb3_mfp_cfg[] __initdata = {
- /* UART */
- GPIO53_UART1_TXD,
- GPIO54_UART1_RXD,
-
- /* PMIC */
- PMIC_INT_GPIO83,
-};
-
-#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
-static struct pm860x_touch_pdata evb3_touch = {
- .gpadc_prebias = 1,
- .slot_cycle = 1,
- .tsi_prebias = 6,
- .pen_prebias = 16,
- .pen_prechg = 2,
- .res_x = 300,
-};
-
-static struct pm860x_backlight_pdata evb3_backlight[] = {
- {
- .id = PM8606_ID_BACKLIGHT,
- .iset = PM8606_WLED_CURRENT(24),
- .flags = PM8606_BACKLIGHT1,
- },
- {},
-};
-
-static struct pm860x_led_pdata evb3_led[] = {
- {
- .id = PM8606_ID_LED,
- .iset = PM8606_LED_CURRENT(12),
- .flags = PM8606_LED1_RED,
- }, {
- .id = PM8606_ID_LED,
- .iset = PM8606_LED_CURRENT(12),
- .flags = PM8606_LED1_GREEN,
- }, {
- .id = PM8606_ID_LED,
- .iset = PM8606_LED_CURRENT(12),
- .flags = PM8606_LED1_BLUE,
- }, {
- .id = PM8606_ID_LED,
- .iset = PM8606_LED_CURRENT(12),
- .flags = PM8606_LED2_RED,
- }, {
- .id = PM8606_ID_LED,
- .iset = PM8606_LED_CURRENT(12),
- .flags = PM8606_LED2_GREEN,
- }, {
- .id = PM8606_ID_LED,
- .iset = PM8606_LED_CURRENT(12),
- .flags = PM8606_LED2_BLUE,
- },
-};
-
-static struct pm860x_platform_data evb3_pm8607_info = {
- .touch = &evb3_touch,
- .backlight = &evb3_backlight[0],
- .led = &evb3_led[0],
- .companion_addr = 0x10,
- .irq_mode = 0,
- .irq_base = IRQ_BOARD_START,
-
- .i2c_port = GI2C_PORT,
-};
-
-static struct i2c_board_info evb3_i2c_info[] = {
- {
- .type = "88PM860x",
- .addr = 0x34,
- .platform_data = &evb3_pm8607_info,
- .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
- },
-};
-
-static void __init evb3_init_i2c(void)
-{
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(evb3_i2c_info));
-}
-#else
-static inline void evb3_init_i2c(void) {}
-#endif
-
-static void __init evb3_init(void)
-{
- /* initialize MFP configurations */
- pxa3xx_mfp_config(ARRAY_AND_SIZE(evb3_mfp_cfg));
-
- pxa_set_ffuart_info(NULL);
-
- evb3_init_i2c();
-}
-
-MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
- .atag_offset = 0x100,
- .map_io = pxa3xx_map_io,
- .nr_irqs = TAVOREVB3_NR_IRQS,
- .init_irq = pxa3xx_init_irq,
- .handle_irq = pxa3xx_handle_irq,
- .timer = &pxa_timer,
- .init_machine = evb3_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index af8e484..1fc9419 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -5,7 +5,6 @@
obj-y := dma.o
obj-$(CONFIG_PXA3xx) += mfp.o
-obj-$(CONFIG_PXA95x) += mfp.o
obj-$(CONFIG_ARCH_MMP) += mfp.o
obj-$(CONFIG_PXA_SSP) += ssp.o
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
index 5c79c29..10bc4f3 100644
--- a/arch/arm/plat-pxa/include/plat/mfp.h
+++ b/arch/arm/plat-pxa/include/plat/mfp.h
@@ -423,7 +423,7 @@ typedef unsigned long mfp_cfg_t;
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
-#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) || defined(CONFIG_ARCH_MMP)
+#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP)
/*
* each MFP pin will have a MFPR register, since the offset of the
* register varies between processors, the processor specific code
@@ -470,6 +470,6 @@ void mfp_write(int mfp, unsigned long mfpr_val);
void mfp_config(unsigned long *mfp_cfgs, int num);
void mfp_config_run(void);
void mfp_config_lpm(void);
-#endif /* CONFIG_PXA3xx || CONFIG_PXA95x || CONFIG_ARCH_MMP */
+#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */
#endif /* __ASM_PLAT_MFP_H */
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 98d52cb..6ab8afb 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -448,7 +448,7 @@ static int pxa_gpio_nums(void)
} else if (cpu_is_pxa27x()) {
count = 120;
gpio_type = PXA27X_GPIO;
- } else if (cpu_is_pxa93x() || cpu_is_pxa95x()) {
+ } else if (cpu_is_pxa93x()) {
count = 191;
gpio_type = PXA93X_GPIO;
} else if (cpu_is_pxa3xx()) {
--
1.7.10.4
^ permalink raw reply related
* [PATCH 1/3] OF: Add helper for matching against linux, stdout-path
From: Grant Likely @ 2012-11-15 9:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121115084945.GZ10369@pengutronix.de>
On Thu, Nov 15, 2012 at 8:49 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Wed, Nov 14, 2012 at 08:49:54PM +0000, Grant Likely wrote:
>> On Fri, Nov 2, 2012 at 9:48 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>> > devicetrees may have a linux,stdout-path property in the chosen
>> > node describing the console device. This adds a helper function
>> > to match a device against this property so a driver can call
>> > add_preferred_console for a matching device.
>> >
>> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>> > ---
>> > drivers/of/Kconfig | 3 +++
>> > drivers/of/Makefile | 1 +
>> > drivers/of/of_stdout.c | 27 +++++++++++++++++++++++++++
>> > include/linux/of_stdout.h | 24 ++++++++++++++++++++++++
>> > 4 files changed, 55 insertions(+)
>> > create mode 100644 drivers/of/of_stdout.c
>> > create mode 100644 include/linux/of_stdout.h
>> >
>> > diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
>> > index dfba3e6..8574ebb 100644
>> > --- a/drivers/of/Kconfig
>> > +++ b/drivers/of/Kconfig
>> > @@ -67,6 +67,9 @@ config OF_MDIO
>> > help
>> > OpenFirmware MDIO bus (Ethernet PHY) accessors
>> >
>> > +config OF_STDOUT
>> > + def_bool y
>> > +
>> > config OF_PCI
>> > def_tristate PCI
>> > depends on PCI
>> > diff --git a/drivers/of/Makefile b/drivers/of/Makefile
>> > index e027f44..c9f3f2f 100644
>> > --- a/drivers/of/Makefile
>> > +++ b/drivers/of/Makefile
>> > @@ -8,6 +8,7 @@ obj-$(CONFIG_OF_I2C) += of_i2c.o
>> > obj-$(CONFIG_OF_NET) += of_net.o
>> > obj-$(CONFIG_OF_SELFTEST) += selftest.o
>> > obj-$(CONFIG_OF_MDIO) += of_mdio.o
>> > +obj-$(CONFIG_OF_STDOUT) += of_stdout.o
>> > obj-$(CONFIG_OF_PCI) += of_pci.o
>> > obj-$(CONFIG_OF_PCI_IRQ) += of_pci_irq.o
>> > obj-$(CONFIG_OF_MTD) += of_mtd.o
>> > diff --git a/drivers/of/of_stdout.c b/drivers/of/of_stdout.c
>> > new file mode 100644
>> > index 0000000..c9e370e
>> > --- /dev/null
>> > +++ b/drivers/of/of_stdout.c
>> > @@ -0,0 +1,27 @@
>> > +/*
>> > + * OF helper for linux,stdoutpath property.
>> > + *
>> > + * This file is released under the GPLv2
>> > + */
>> > +#include <linux/of_stdout.h>
>> > +
>> > +/**
>> > + * of_device_is_stdout_path - check if a device node matches the
>> > + * linux,stdout-path property
>> > + *
>> > + * Check if this device node matches the linux,stdout-path property
>> > + * in the chosen node. return true if yes, false otherwise.
>> > + */
>> > +int of_device_is_stdout_path(struct device_node *dn)
>> > +{
>> > + const char *name;
>> > +
>> > + name = of_get_property(of_chosen, "linux,stdout-path", NULL);
>> > + if (name == NULL)
>> > + return 0;
>> > +
>> > + if (dn == of_find_node_by_path(name))
>>
>> need to of_node_put() the return value of of_find_node_by_path()
>>
>> > + return 1;
>> > +
>> > + return 0;
>> > +}
>>
>> Hi Sascha,
>>
>> I'm fine with the helper, but there really is no need for a completely
>> separate .c file. Just put it in drivers/of/base.c.
>
> I guess the same applies to include/linux/of_stdout.h.
>
> Should I drop the CONFIG_OF_STDOUT aswell?
Yup.
g.
^ permalink raw reply
* [PATCH v2 2/3] serial: mxs-auart: add the DMA support for mx28
From: Huang Shijie @ 2012-11-15 9:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A4983F.8080407@bluegiga.com>
? 2012?11?15? 15:22, Lauri Hintsala ??:
> Hi,
>
> On 11/15/2012 05:20 AM, Huang Shijie wrote:
>> ? 2012?11?13? 17:42, Lauri Hintsala ??:
>>> Hi Huang,
>>>
>>> DMA support doesn't work with latest stable v3.6.5 or development
>>> 3.7-rc5 kernels. I get following error message when I open the serial
>>> port /dev/ttyAPP0:
>>>
>>> [ 48.730000] mxs-auart 8006a000.serial: step 1 error
>>> [ 48.750000] mxs-auart 8006a000.serial: We can not start up the DMA.
>>>
>> I tested this patch set in imx28-evk board Rev C with
>> linux-next-20121114.
>> it works fine.
>>
>> Maybe you can try the linux-next code.
>
> I tested linux-next-20121114 on apx4devkit (imx28 based device) and I
> got the same error message:
>
> # stty -F /dev/ttyAPP0 crtscts; microcom /dev/ttyAPP0 -s 115200
> [ 133.710000] mxs-auart 8006a000.serial: step 1 error
> [ 133.720000] mxs-auart 8006a000.serial: We can not start up the DMA.
Could you test this patch?
thanks
Huang Shijie
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^ permalink raw reply
* [PATCH v3 04/11] ARM: Exynos4: Migrate clock support to common clock framework
From: Thomas Abraham @ 2012-11-15 9:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1496911.LC6ynRgIgc@flatron>
On 15 November 2012 05:01, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> On Thursday 15 of November 2012 03:37:26 Thomas Abraham wrote:
>> Remove Samsung specific clock support in Exynos4 and migrate to use
>> common clock framework.
>>
>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> arch/arm/mach-exynos/Kconfig | 1 +
>> arch/arm/mach-exynos/Makefile | 3 -
>> arch/arm/mach-exynos/clock-exynos4.c | 1602
>> ---------------------------- arch/arm/mach-exynos/clock-exynos4.h
>> | 35 -
>> arch/arm/mach-exynos/clock-exynos4210.c | 188 ----
>> arch/arm/mach-exynos/clock-exynos4212.c | 192 ----
>> arch/arm/mach-exynos/common.c | 22 +-
>> arch/arm/mach-exynos/common.h | 3 +
>> arch/arm/mach-exynos/mach-armlex4210.c | 1 -
>> arch/arm/mach-exynos/mach-exynos4-dt.c | 1 -
>> arch/arm/mach-exynos/mach-nuri.c | 1 -
>> arch/arm/mach-exynos/mach-origen.c | 1 -
>> arch/arm/mach-exynos/mach-smdk4x12.c | 1 -
>> arch/arm/mach-exynos/mach-smdkv310.c | 1 -
>> arch/arm/mach-exynos/mach-universal_c210.c | 1 -
>> arch/arm/mach-exynos/mct.c | 19 +
>> arch/arm/plat-samsung/Kconfig | 4 +-
>> 17 files changed, 27 insertions(+), 2049 deletions(-)
>> delete mode 100644 arch/arm/mach-exynos/clock-exynos4.c
>> delete mode 100644 arch/arm/mach-exynos/clock-exynos4.h
>> delete mode 100644 arch/arm/mach-exynos/clock-exynos4210.c
>> delete mode 100644 arch/arm/mach-exynos/clock-exynos4212.c
>>
> [snip]
>> diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
>> index f7792b8..c2e806c 100644
>> --- a/arch/arm/mach-exynos/mct.c
>> +++ b/arch/arm/mach-exynos/mct.c
>> @@ -31,6 +31,7 @@
>> #include <mach/map.h>
>> #include <mach/irqs.h>
>> #include <asm/mach/time.h>
>> +#include "common.h"
>>
>> #define EXYNOS4_MCTREG(x) (x)
>> #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
>> @@ -517,6 +518,24 @@ static void __init exynos4_timer_init(void)
>> struct device_node *np;
>> u32 nr_irqs, i;
>>
>> +#ifdef CONFIG_COMMON_CLK
>> + /*
>> + * Clock lookup should be functional now since the MCT controller
>> driver + * looks up clocks. So the clock initialization is initiated
>> here. + */
>> + if (of_have_populated_dt()) {
>> + if (of_machine_is_compatible("samsung,exynos4210") ||
>> + of_machine_is_compatible("samsung,exynos4212") ||
>> + of_machine_is_compatible("samsung,exynos4412"))
>> + exynos4_clk_init();
>> + } else {
>> + if (soc_is_exynos4210() || soc_is_exynos4212() ||
>> + soc_is_exynos4412()) {
>> + exynos4_clk_init();
>> + }
>> + }
>> +#endif
>> +
>
> I don't like the idea of initializing the clocks from timer
> initialization. What about some platforms where MCT isn't used? It is also
> far from being elegant.
Very true, I did also prefer not do this. But, clock lookup should be
functional atleast by the time mct initialization begins. So I tried
few options such as adding .early_init_call callback in MACHINE_DESC
which then can call exynos4_clk_init, but that did not help since
mem_init isn't complete by then and memory allocation failed during
clock registration. Other methods also did not help much. If you know
of a solution to get around this, could you please let me know.
Thanks,
Thomas.
^ permalink raw reply
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