* [PATCH V6 2/2] dmaengine: add helper function to request a slave DMA channel
From: Vinod Koul @ 2012-11-16 1:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509D6108.1060304@ti.com>
On Fri, 2012-11-09 at 14:01 -0600, Jon Hunter wrote:
> Hi Vinod,
>
> A few people have been asking me if getting device-tree support for DMA
> engine is plan for record for v3.8. I know that you were working through
> implementing a common interface and so I wanted to check how that is
> going. Do you have any insight to when device-tree support may get added?
>
I have not been able to do much work on this for last couple of weeks. I
hope to do it in by this weekend. If not I will merge yours and then
uppdate.
Anyway, DT would be there in 3.8 with or without my changes.
--
~Vinod
^ permalink raw reply
* [Patch v6 4/4] ASoC: at91sam9g20ek-wm8731: convert to dt support
From: Mark Brown @ 2012-11-16 1:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352887751-21848-5-git-send-email-voice.shen@atmel.com>
On Wed, Nov 14, 2012 at 06:09:11PM +0800, Bo Shen wrote:
> convert at91sam9g20ek with wm8731 to device tree support
Applied, thanks. Now I have a board with full DT enablement I can run
(I think...)!
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121116/941f9f50/attachment.sig>
^ permalink raw reply
* [Patch v6 3/4] ASoC: atmel-ssc-dai: match new method of dai and pcm register
From: Mark Brown @ 2012-11-16 1:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352887751-21848-4-git-send-email-voice.shen@atmel.com>
On Wed, Nov 14, 2012 at 06:09:10PM +0800, Bo Shen wrote:
> Remove unneeded code with the new method of dai and pcm register
Applied, thanks.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121116/244ae253/attachment.sig>
^ permalink raw reply
* [Patch v6 2/4] ASoC: atmel-ssc-dai: register dai and pcm directly
From: Mark Brown @ 2012-11-16 1:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352887751-21848-3-git-send-email-voice.shen@atmel.com>
On Wed, Nov 14, 2012 at 06:09:09PM +0800, Bo Shen wrote:
> change the method for register dai and pcm
> - let the atmel-ssc-dai no longer as a standalone platform device
> - remap ssc and then register dai directly
> - register pcm from dai directly
> - modify the code which related with this change
Applied, thanks.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121116/c19ed5dd/attachment.sig>
^ permalink raw reply
* [Patch v6 1/4] ARM: at91: atmel-ssc: add pinctrl support
From: Mark Brown @ 2012-11-16 1:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352887751-21848-2-git-send-email-voice.shen@atmel.com>
On Wed, Nov 14, 2012 at 06:09:08PM +0800, Bo Shen wrote:
> Add pinctrl support for atmel ssc peripheral
>
> Signed-off-by: Bo Shen <voice.shen@atmel.com>
This generates lots of conflicts in the pinctrl stuff in the DTS - looks
like it was generated against -next. Can you please regenerate against
my atmel branch with just the changes to add the pinmux information on
the SSC nodes? Or possbily this can just be applied direct to the
pinctrl branch (we'll get an add/add conflict with the SSC nodes though
that should be simple to resolve, a cross merge might be helpful).
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121116/c118b45c/attachment.sig>
^ permalink raw reply
* [PATCH 00/10] serial: sh-sci fixes - console PM, SCIFB, SMP lockup, etc.
From: Greg KH @ 2012-11-16 1:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509A0B4E.1030801@renesas.com>
On Wed, Nov 07, 2012 at 04:18:38PM +0900, Shinya Kuribayashi wrote:
> On 11/7/2012 3:57 PM, Shinya Kuribayashi wrote:
> > Hi Paul and serial forks,
> [...]
> > Takashi YOSHII (4):
> > serial: sh-sci: fix condition test to set SCBRR
> > serial: sh-sci: support lower baud rate
> > serial: sh-sci: mask SCTFDR/RFDR according to fifosize
> > serial: sh-sci: fix common SCIFB regmap definition
> >
> > Teppei Kamijou (1):
> > serial: sh-sci: console runtime PM support (revisit)
> >
> > drivers/tty/serial/sh-sci.c | 140 ++++++++++++++++++--------------------------
> > 1 file changed, 56 insertions(+), 84 deletions(-)
>
> Oops, I forgot to append proper From: author lines in five commits
> (patch 04/10 to 09/10). Didn't mean to supersede your authoship.
>
> I'd respin the patchset later, waiting for some feedback.
Can you please resend this with this fixed up if you want to get this
into 3.8?
thanks,
greg k-h
^ permalink raw reply
* ttySAC0 or ttyS0 in 3.6.x ARM Linux?
From: Woody Wu @ 2012-11-16 0:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121115171615.GP3290@n2100.arm.linux.org.uk>
On 2012-11-15, Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:
> On Thu, Nov 15, 2012 at 03:07:24PM +0800, woody wrote:
>> In the 3.6.6 ARM kernel, should I use ttySAC0 or ttyS0 to specify the
>> 'console' kernel command line?
>
> That depends on what type of UART you're using. ttyS is for 8250 ports.
> ttySAC ended up being used for various SoC based ports which aren't
> 8250 based.
Thanks. I think I understood.
The only strange thing is that, however, on my here this is a 2.6.16.4
kernel, that was using ttyS instead of ttySAC for the same physical port
on the same board.
--
-woody
I can't go back to yesterday - because I was a different person then.
^ permalink raw reply
* [PATCH] Documentation: correct argument list for of_platform_populate correction to match of_platform.h prototype
From: Chaiken, Alison @ 2012-11-15 23:32 UTC (permalink / raw)
To: linux-arm-kernel
>From fd4450ac6bdcf62a84b0d029b36506e7fd567688 Mon Sep 17 00:00:00 2001
From: Alison Chaiken <alchaiken@gmail.com>
Date: Thu, 1 Nov 2012 01:12:38 -0700
Subject: [PATCH] Argument list for of_platform_populate correction to match of_platform.h prototype
Signed-off-by: Alison Chaiken <alison_chaiken@mentor.com>
---
Documentation/devicetree/usage-model.txt | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/usage-model.txt b/Documentation/devicetree/usage-model.txt
index c5a8009..daa56a2 100644
--- a/Documentation/devicetree/usage-model.txt
+++ b/Documentation/devicetree/usage-model.txt
@@ -347,7 +347,7 @@ later), which will happily live at the base of the Linux /sys/devices
tree. Therefore, if a DT node is at the root of the tree, then it
really probably is best registered as a platform_device.
-Linux board support code calls of_platform_populate(NULL, NULL, NULL)
+Linux board support code calls of_platform_populate(NULL, NULL, NULL, NULL)
to kick off discovery of devices at the root of the tree. The
parameters are all NULL because when starting from the root of the
tree, there is no need to provide a starting node (the first NULL), a
--
1.7.1
^ permalink raw reply related
* [PATCH 2/2] ARM: tegra: trimslice: enable HDMI port
From: Stephen Warren @ 2012-11-15 23:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1353021614-29200-1-git-send-email-swarren@wwwdotorg.org>
From: Thierry Reding <thierry.reding@avionic-design.de>
Enable host1x, and the HDMI output. Harmony also has a DVI port with an
HDMI form-factor connector, driven by Tegra's LVDS output. This isn't
enabled yet, due to potential issues with having multiple outputs enabled.
Correct DDC I2C frequency to 100KHz.
Add dummy/fixed regulators to satisfy the HDMI driver.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
[swarren: add commit description, remove enable of DVI port]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/boot/dts/tegra20-trimslice.dts | 44 ++++++++++++++++++++++++++++---
1 file changed, 40 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index f4e0428..b70b4cb 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -10,6 +10,18 @@
reg = <0x00000000 0x40000000>;
};
+ host1x {
+ hdmi {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ };
+ };
+
pinmux {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
@@ -249,9 +261,9 @@
clock-frequency = <216000000>;
};
- i2c at 7000c000 {
+ dvi_ddc: i2c at 7000c000 {
status = "okay";
- clock-frequency = <400000>;
+ clock-frequency = <100000>;
};
spi at 7000c380 {
@@ -264,9 +276,9 @@
};
};
- i2c at 7000c400 {
+ hdmi_ddc: i2c at 7000c400 {
status = "okay";
- clock-frequency = <400000>;
+ clock-frequency = <100000>;
};
i2c at 7000c500 {
@@ -310,6 +322,30 @@
bus-width = <4>;
};
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_vdd_reg: regulator at 0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ hdmi_pll_reg: regulator at 1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ };
+
sound {
compatible = "nvidia,tegra-audio-trimslice";
nvidia,i2s-controller = <&tegra_i2s1>;
--
1.7.10.4
^ permalink raw reply related
* [PATCH 1/2] ARM: tegra: harmony: enable HDMI port
From: Stephen Warren @ 2012-11-15 23:20 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
Enable host1x, and the HDMI output. Harmony also has an optional LCD,
and a VGA output. The former isn't enabled due to potential issues with
having multiple outputs enabled. The latter isn't enabled since the
driver doesn't support VGA yet anyway.
Correct DDC I2C frequency to 100KHz.
Based on work by Thierry Reding for TrimSlice.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/boot/dts/tegra20-harmony.dts | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index a3f2f38..43eb72a 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -10,6 +10,18 @@
reg = <0x00000000 0x40000000>;
};
+ host1x {
+ hdmi {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ };
+ };
+
pinmux {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
@@ -262,9 +274,9 @@
};
};
- i2c at 7000c400 {
+ hdmi_ddc: i2c at 7000c400 {
status = "okay";
- clock-frequency = <400000>;
+ clock-frequency = <100000>;
};
i2c at 7000c500 {
@@ -369,13 +381,13 @@
regulator-max-microvolt = <1800000>;
};
- ldo7 {
+ hdmi_vdd_reg: ldo7 {
regulator-name = "vdd_ldo7,avdd_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- ldo8 {
+ hdmi_pll_reg: ldo8 {
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
--
1.7.10.4
^ permalink raw reply related
* [PATCH 6/6] ARM: sunxi: Add entry to MAINTAINERS
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1353019586-21043-1-git-send-email-maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 59203e7..7dbfcb7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -685,6 +685,12 @@ M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
+ARM/Allwinner A1X SoC support
+M: Maxime Ripard <maxime.ripard@free-electrons.com>
+L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: arch/arm/mach-sunxi/
+
ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
M: Andrew Victor <linux@maxim.org.za>
M: Nicolas Ferre <nicolas.ferre@atmel.com>
--
1.7.9.5
^ permalink raw reply related
* [PATCH 5/6] ARM: sunxi: Add device tree for the A13 and the Olinuxino board
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1353019586-21043-1-git-send-email-maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun5i-olinuxino.dts | 30 +++++++++++++++++
arch/arm/boot/dts/sun5i.dtsi | 58 +++++++++++++++++++++++++++++++++
3 files changed, 89 insertions(+)
create mode 100644 arch/arm/boot/dts/sun5i-olinuxino.dts
create mode 100644 arch/arm/boot/dts/sun5i.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f37cf9f..9b2d3f0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear310-evb.dtb \
spear320-evb.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun5i-olinuxino.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
diff --git a/arch/arm/boot/dts/sun5i-olinuxino.dts b/arch/arm/boot/dts/sun5i-olinuxino.dts
new file mode 100644
index 0000000..add1e60
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-olinuxino.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun5i.dtsi"
+
+/ {
+ model = "Olimex A13-Olinuxino";
+ compatible = "olimex,a13-olinuxino", "allwinner,sun5i";
+
+ memory {
+ reg = <0x40000000 0x40000000>;
+ };
+
+ soc {
+ duart: uart at 01c28400 {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
new file mode 100644
index 0000000..5797323
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&intc>;
+
+ cpus {
+ cpu at 0 {
+ compatible = "arm,cortex-a8";
+ };
+ };
+
+ chosen {
+ bootargs = "earlyprintk console=ttyS0,115200";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x01c20000 0x300000>;
+ ranges;
+
+ timer at 01c20c00 {
+ compatible = "allwinner,sunxi-timer";
+ reg = <0x01c20c00 0x400>;
+ interrupts = <22>;
+ };
+
+ intc: interrupt-controller at 01c20400 {
+ compatible = "allwinner,sunxi-ic";
+ reg = <0x01c20400 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart1: uart at 01c28400 {
+ compatible = "ns8250";
+ reg = <0x01c28400 0x400>;
+ interrupts = <2>;
+ reg-shift = <2>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 4/6] ARM: sunxi: Add earlyprintk support
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1353019586-21043-1-git-send-email-maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/Kconfig.debug | 8 ++++++++
arch/arm/include/debug/sunxi.S | 22 ++++++++++++++++++++++
2 files changed, 30 insertions(+)
create mode 100644 arch/arm/include/debug/sunxi.S
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b0f3857..6672b02 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -345,6 +345,13 @@ choice
Say Y here if you want kernel low-level debugging support
on SOCFPGA based platforms.
+ config DEBUG_SUNXI_UART
+ bool "Kernel low-level debugging messages via sunXi UART"
+ depends on ARCH_SUNXI
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Allwinner A1X based platforms.
+
config DEBUG_VEXPRESS_UART0_DETECT
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -416,6 +423,7 @@ config DEBUG_LL_INCLUDE
default "debug/mvebu.S" if DEBUG_MVEBU_UART
default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
+ default "debug/sunxi.S" if DEBUG_SUNXI_UART
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
default "mach/debug-macro.S"
diff --git a/arch/arm/include/debug/sunxi.S b/arch/arm/include/debug/sunxi.S
new file mode 100644
index 0000000..ffd101f
--- /dev/null
+++ b/arch/arm/include/debug/sunxi.S
@@ -0,0 +1,22 @@
+/*
+ * Early serial output macro for Allwinner A1X SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define SUNXI_UART1_PHYS_BASE 0x01c28400
+#define SUNXI_UART1_VIRT_BASE 0xf1c28400
+
+ .macro addruart, rp, rv, tmp
+ ldr \rp, =SUNXI_UART1_PHYS_BASE
+ ldr \rv, =SUNXI_UART1_VIRT_BASE
+ .endm
+
+#define UART_SHIFT 2
+#include <asm/hardware/debug-8250.S>
--
1.7.9.5
^ permalink raw reply related
* [PATCH 3/6] ARM: sunxi: Add basic support for Allwinner A1x SoCs
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1353019586-21043-1-git-send-email-maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/Kconfig | 2 ++
arch/arm/Makefile | 1 +
arch/arm/mach-sunxi/Kconfig | 9 ++++++
arch/arm/mach-sunxi/Makefile | 1 +
arch/arm/mach-sunxi/Makefile.boot | 1 +
arch/arm/mach-sunxi/sunxi.c | 60 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-sunxi/sunxi.h | 20 +++++++++++++
7 files changed, 94 insertions(+)
create mode 100644 arch/arm/mach-sunxi/Kconfig
create mode 100644 arch/arm/mach-sunxi/Makefile
create mode 100644 arch/arm/mach-sunxi/Makefile.boot
create mode 100644 arch/arm/mach-sunxi/sunxi.c
create mode 100644 arch/arm/mach-sunxi/sunxi.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ade7e92..1abb573 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1113,6 +1113,8 @@ source "arch/arm/mach-exynos/Kconfig"
source "arch/arm/mach-shmobile/Kconfig"
+source "arch/arm/mach-sunxi/Kconfig"
+
source "arch/arm/mach-prima2/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5f914fc..363320a 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -193,6 +193,7 @@ machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx
machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx
machine-$(CONFIG_MACH_SPEAR600) += spear6xx
machine-$(CONFIG_ARCH_ZYNQ) += zynq
+machine-$(CONFIG_ARCH_SUNXI) += sunxi
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
new file mode 100644
index 0000000..3fdd008
--- /dev/null
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -0,0 +1,9 @@
+config ARCH_SUNXI
+ bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
+ select CLKSRC_MMIO
+ select COMMON_CLK
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_IRQ_CHIP
+ select PINCTRL
+ select SPARSE_IRQ
+ select SUNXI_TIMER
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
new file mode 100644
index 0000000..93bebfc
--- /dev/null
+++ b/arch/arm/mach-sunxi/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
diff --git a/arch/arm/mach-sunxi/Makefile.boot b/arch/arm/mach-sunxi/Makefile.boot
new file mode 100644
index 0000000..46d4cf0
--- /dev/null
+++ b/arch/arm/mach-sunxi/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-$(CONFIG_ARCH_SUNXI) += 0x40008000
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
new file mode 100644
index 0000000..8f42df8
--- /dev/null
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -0,0 +1,60 @@
+/*
+ * Device Tree support for Allwinner A1X SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/sunxi_timer.h>
+
+#include <linux/irqchip/sunxi.h>
+
+#include <asm/hardware/vic.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "sunxi.h"
+
+static struct map_desc sunxi_io_desc[] __initdata = {
+ {
+ .virtual = (unsigned long) SUNXI_REGS_VIRT_BASE,
+ .pfn = __phys_to_pfn(SUNXI_REGS_PHYS_BASE),
+ .length = SUNXI_REGS_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+
+void __init sunxi_map_io(void)
+{
+ iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
+}
+
+static void __init sunxi_dt_init(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const sunxi_board_dt_compat[] = {
+ "allwinner,sun5i",
+ NULL,
+};
+
+DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
+ .init_machine = sunxi_dt_init,
+ .map_io = sunxi_map_io,
+ .init_irq = sunxi_init_irq,
+ .handle_irq = sunxi_handle_irq,
+ .timer = &sunxi_timer,
+ .dt_compat = sunxi_board_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-sunxi/sunxi.h b/arch/arm/mach-sunxi/sunxi.h
new file mode 100644
index 0000000..33b5871
--- /dev/null
+++ b/arch/arm/mach-sunxi/sunxi.h
@@ -0,0 +1,20 @@
+/*
+ * Generic definitions for Allwinner SunXi SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SUNXI_H
+#define __MACH_SUNXI_H
+
+#define SUNXI_REGS_PHYS_BASE 0x01c00000
+#define SUNXI_REGS_VIRT_BASE IOMEM(0xf1c00000)
+#define SUNXI_REGS_SIZE (SZ_2M + SZ_1M)
+
+#endif /* __MACH_SUNXI_H */
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/6] irqchip: sunxi: Add irq controller driver
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1353019586-21043-1-git-send-email-maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
CC: Thomas Gleixner <tglx@linutronix.de>
---
.../interrupt-controller/allwinner,sunxi-ic.txt | 104 ++++++++++++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-sunxi.c | 173 ++++++++++++++++++++
include/linux/irqchip/sunxi.h | 27 +++
4 files changed, 305 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
create mode 100644 drivers/irqchip/irq-sunxi.c
create mode 100644 include/linux/irqchip/sunxi.h
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
new file mode 100644
index 0000000..7f9fb85
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
@@ -0,0 +1,104 @@
+Allwinner Sunxi Interrupt Controller
+
+Required properties:
+
+- compatible : should be "allwinner,sunxi-ic"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+The interrupt sources are as follows:
+
+0: ENMI
+1: UART0
+2: UART1
+3: UART2
+4: UART3
+5: IR0
+6: IR1
+7: I2C0
+8: I2C1
+9: I2C2
+10: SPI0
+11: SPI1
+12: SPI2
+13: SPDIF
+14: AC97
+15: TS
+16: I2S
+17: UART4
+18: UART5
+19: UART6
+20: UART7
+21: KEYPAD
+22: TIMER0
+23: TIMER1
+24: TIMER2
+25: TIMER3
+26: CAN
+27: DMA
+28: PIO
+29: TOUCH_PANEL
+30: AUDIO_CODEC
+31: LRADC
+32: SDMC0
+33: SDMC1
+34: SDMC2
+35: SDMC3
+36: MEMSTICK
+37: NAND
+38: USB0
+39: USB1
+40: USB2
+41: SCR
+42: CSI0
+43: CSI1
+44: LCDCTRL0
+45: LCDCTRL1
+46: MP
+47: DEFEBE0
+48: DEFEBE1
+49: PMU
+50: SPI3
+51: TZASC
+52: PATA
+53: VE
+54: SS
+55: EMAC
+56: SATA
+57: GPS
+58: HDMI
+59: TVE
+60: ACE
+61: TVD
+62: PS2_0
+63: PS2_1
+64: USB3
+65: USB4
+66: PLE_PFM
+67: TIMER4
+68: TIMER5
+69: GPU_GP
+70: GPU_GPMMU
+71: GPU_PP0
+72: GPU_PPMMU0
+73: GPU_PMU
+74: GPU_RSV0
+75: GPU_RSV1
+76: GPU_RSV2
+77: GPU_RSV3
+78: GPU_RSV4
+79: GPU_RSV5
+80: GPU_RSV6
+82: SYNC_TIMER0
+83: SYNC_TIMER1
+
+Example:
+
+intc: interrupt-controller {
+ compatible = "allwinner,sunxi-ic";
+ reg = <0x01c20400 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 054321d..2444d07 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
+obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
diff --git a/drivers/irqchip/irq-sunxi.c b/drivers/irqchip/irq-sunxi.c
new file mode 100644
index 0000000..9dcb323
--- /dev/null
+++ b/drivers/irqchip/irq-sunxi.c
@@ -0,0 +1,173 @@
+/*
+ * Allwinner A1X SoCs IRQ chip driver.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Benn Huang <benn@allwinnertech.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <linux/irqchip/sunxi.h>
+
+#define SUNXI_IRQ_PROTECTION_REG 0x08
+#define SUNXI_IRQ_NMI_CTRL_REG 0x0c
+#define SUNXI_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
+#define SUNXI_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
+#define SUNXI_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
+#define SUNXI_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
+
+static void __iomem *sunxi_irq_base;
+static struct irq_domain *sunxi_irq_domain;
+
+void sunxi_irq_ack(struct irq_data *irqd)
+{
+ unsigned int irq = irqd_to_hwirq(irqd);
+ unsigned int irq_off = irq % 32;
+ int reg = irq / 32;
+ u32 val;
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+ writel(val & ~(1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+ writel(val | (1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
+ writel(val | (1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
+}
+
+static void sunxi_irq_mask(struct irq_data *irqd)
+{
+ unsigned int irq = irqd_to_hwirq(irqd);
+ unsigned int irq_off = irq % 32;
+ int reg = irq / 32;
+ u32 val;
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+ writel(val & ~(1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+ writel(val | (1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+}
+
+static void sunxi_irq_unmask(struct irq_data *irqd)
+{
+ unsigned int irq = irqd_to_hwirq(irqd);
+ unsigned int irq_off = irq % 32;
+ int reg = irq / 32;
+ u32 val;
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+ writel(val | (1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+
+ val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+ writel(val & ~(1 << irq_off),
+ sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+
+ /* Must clear pending bit when enabled */
+ if (irq == 0)
+ writel(1, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
+}
+
+static struct irq_chip sunxi_irq_chip = {
+ .name = "sunxi_irq",
+ .irq_ack = sunxi_irq_ack,
+ .irq_mask = sunxi_irq_mask,
+ .irq_unmask = sunxi_irq_unmask,
+};
+
+static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ irq_set_chip(virq, &sunxi_irq_chip);
+ irq_set_handler(virq, handle_level_irq);
+ set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+ return 0;
+}
+
+static struct irq_domain_ops sunxi_irq_ops = {
+ .map = sunxi_irq_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init sunxi_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ sunxi_irq_base = of_iomap(node, 0);
+ if (!sunxi_irq_base)
+ panic("%s: unable to map IC registers\n",
+ node->full_name);
+
+ /* Disable all interrupts */
+ writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
+ writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
+ writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
+
+ /* Mask all the interrupts */
+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));
+
+ /* Clear all the pending interrupts */
+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
+
+ /* Enable protection mode */
+ writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
+
+ /* Configure the external interrupt source type */
+ writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
+
+ sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
+ &sunxi_irq_ops, NULL);
+ if (!sunxi_irq_domain)
+ panic("%s: unable to create IRQ domain\n", node->full_name);
+
+ return 0;
+}
+
+static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
+ { .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init }
+};
+
+void __init sunxi_init_irq(void)
+{
+ of_irq_init(sunxi_irq_dt_ids);
+}
+
+asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
+{
+ u32 irq, reg;
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ reg = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(i));
+ if (reg == 0)
+ continue;
+ irq = ilog2(reg);
+ break;
+ }
+ irq = irq_find_mapping(sunxi_irq_domain, irq);
+ handle_IRQ(irq, regs);
+}
diff --git a/include/linux/irqchip/sunxi.h b/include/linux/irqchip/sunxi.h
new file mode 100644
index 0000000..1fe2c22
--- /dev/null
+++ b/include/linux/irqchip/sunxi.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_IRQCHIP_SUNXI_H
+#define __LINUX_IRQCHIP_SUNXI_H
+
+#include <asm/exception.h>
+
+extern void sunxi_init_irq(void);
+
+extern asmlinkage void __exception_irq_entry sunxi_handle_irq(
+ struct pt_regs *regs);
+
+#endif
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/6] clocksource: sunxi: Add Allwinner A1X Timer Driver
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1353019586-21043-1-git-send-email-maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: John Stultz <johnstul@us.ibm.com>
---
.../bindings/timer/allwinner,sunxi-timer.txt | 15 ++
drivers/clocksource/Kconfig | 3 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/sunxi_timer.c | 160 ++++++++++++++++++++
include/linux/sunxi_timer.h | 24 +++
5 files changed, 203 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
create mode 100644 drivers/clocksource/sunxi_timer.c
create mode 100644 include/linux/sunxi_timer.h
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
new file mode 100644
index 0000000..c6041ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
@@ -0,0 +1,15 @@
+Allwinner A1X SoCs Timer Controller
+
+Required properties:
+
+- compatible : should be "allwinner,sunxi-timer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt of the first timer
+
+Example:
+
+timer {
+ compatible = "allwinner,sunxi-timer";
+ reg = <0x01c20c00 0x400>;
+ interrupts = <22>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 6a78073..a098573 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -22,6 +22,9 @@ config DW_APB_TIMER_OF
config ARMADA_370_XP_TIMER
bool
+config SUNXI_TIMER
+ bool
+
config CLKSRC_DBX500_PRCMU
bool "Clocksource PRCMU Timer"
depends on UX500_SOC_DB8500
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 603be36..36f06de 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -14,5 +14,6 @@ obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
+obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o
obj-$(CONFIG_CLKSRC_ARM_GENERIC) += arm_generic.o
diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sunxi_timer.c
new file mode 100644
index 0000000..5dd5b48
--- /dev/null
+++ b/drivers/clocksource/sunxi_timer.c
@@ -0,0 +1,160 @@
+/*
+ * Allwinner A1X SoCs timer handling.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Benn Huang <benn@allwinnertech.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sunxi_timer.h>
+
+#define TIMER_CTL_REG 0x00
+#define TIMER_CTL_ENABLE (1 << 0)
+#define TIMER_IRQ_ST_REG 0x04
+#define TIMER0_CTL_REG 0x10
+#define TIMER0_CTL_ENABLE (1 << 0)
+#define TIMER0_CTL_AUTORELOAD (1 << 1)
+#define TIMER0_CTL_ONESHOT (1 << 7)
+#define TIMER0_INTVAL_REG 0x14
+#define TIMER0_CNTVAL_REG 0x18
+
+#define TIMER_CLKSRC 24000000
+#define TIMER_SCAL 16
+#define TIMER_INTERVAL (TIMER_CLKSRC / (TIMER_SCAL * HZ))
+
+static void __iomem *timer_base;
+
+static void sunxi_clkevt_mode(enum clock_event_mode mode,
+ struct clock_event_device *clk)
+{
+ u32 u = readl(timer_base + TIMER0_CTL_REG);
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ writel(TIMER_INTERVAL, timer_base + TIMER0_INTVAL_REG);
+ u &= ~(TIMER0_CTL_ONESHOT);
+ writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG);
+ break;
+
+ case CLOCK_EVT_MODE_ONESHOT:
+ writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG);
+ break;
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ default:
+ writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG);
+ break;
+ }
+}
+
+static int sunxi_clkevt_next_event(unsigned long evt,
+ struct clock_event_device *unused)
+{
+ u32 u = readl(timer_base + TIMER0_CTL_REG);
+ writel(evt, timer_base + TIMER0_CNTVAL_REG);
+ writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD,
+ timer_base + TIMER0_CTL_REG);
+
+ return 0;
+}
+
+static struct clock_event_device sunxi_clockevent = {
+ .name = "sunxi_tick",
+ .shift = 32,
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .set_mode = sunxi_clkevt_mode,
+ .set_next_event = sunxi_clkevt_next_event,
+};
+
+
+static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+
+ writel(0x1, timer_base + TIMER_IRQ_ST_REG);
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction sunxi_timer_irq = {
+ .name = "sunxi_timer0",
+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+ .handler = sunxi_timer_interrupt,
+ .dev_id = &sunxi_clockevent,
+};
+
+static struct of_device_id sunxi_timer_dt_ids[] = {
+ { .compatible = "allwinner,sunxi-timer" },
+};
+
+static void __init sunxi_timer_init(void)
+{
+ struct device_node *node;
+ int ret, irq;
+ u32 val;
+
+ node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
+ if (!node)
+ panic("No sunxi timer node");
+
+ timer_base = of_iomap(node, 0);
+ if (!timer_base)
+ panic("Can't map registers");
+
+ irq = irq_of_parse_and_map(node, 0);
+ if (irq <= 0)
+ panic("Can't parse IRQ");
+
+ writel(TIMER_INTERVAL, timer_base + TIMER0_INTVAL_REG);
+
+ /* set clock source to HOSC, 16 pre-division */
+ val = readl(timer_base + TIMER0_CTL_REG);
+ val &= ~(0x07 << 4);
+ val &= ~(0x03 << 2);
+ val |= (4 << 4) | (1 << 2);
+ writel(val, timer_base + TIMER0_CTL_REG);
+
+ /* set mode to auto reload */
+ val = readl(timer_base + TIMER0_CTL_REG);
+ writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
+
+ ret = setup_irq(irq, &sunxi_timer_irq);
+ if (ret)
+ pr_warn("failed to setup irq %d\n", irq);
+
+ /* Enable timer0 interrupt */
+ val = readl(timer_base + TIMER_CTL_REG);
+ writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
+
+ sunxi_clockevent.mult = div_sc(TIMER_CLKSRC / TIMER_SCAL,
+ NSEC_PER_SEC,
+ sunxi_clockevent.shift);
+ sunxi_clockevent.max_delta_ns = clockevent_delta2ns(0xff,
+ &sunxi_clockevent);
+ sunxi_clockevent.min_delta_ns = clockevent_delta2ns(0x1,
+ &sunxi_clockevent);
+ sunxi_clockevent.cpumask = cpumask_of(0);
+
+ clockevents_register_device(&sunxi_clockevent);
+}
+
+struct sys_timer sunxi_timer = {
+ .init = sunxi_timer_init,
+};
diff --git a/include/linux/sunxi_timer.h b/include/linux/sunxi_timer.h
new file mode 100644
index 0000000..b9165bb
--- /dev/null
+++ b/include/linux/sunxi_timer.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SUNXI_TIMER_H
+#define __SUNXI_TIMER_H
+
+#include <asm/mach/time.h>
+
+extern struct sys_timer sunxi_timer;
+
+#endif
--
1.7.9.5
^ permalink raw reply related
* [PATCH 0/6] Add basic support for Allwinner A1X SoCs
From: Maxime Ripard @ 2012-11-15 22:46 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
You'll find in this patchset the initial support for Allwinner A10 and A13 SoCs
from Allwinner. Since the internal name of these SoCs are sun4i and sun5i, the
mach- directory is named sunxi.
You can find these SoCs in the Cubieboard, the A13-olinuxino or the Melee
A1000.
Both SoCs should work fine, as the A13 is a trimmed down version of the A10,
but it has only been tested on a A13-OlinuXino from Olimex.
Support is quite minimal for now, since it only includes timer and IRQ
controller drivers, so we can only boot to userspace through initramfs. Support
for the other peripherals on these SoCs will come eventually.
Thanks,
Maxime
Maxime Ripard (6):
clocksource: sunxi: Add Allwinner A1X Timer Driver
irqchip: sunxi: Add irq controller driver
ARM: sunxi: Add basic support for Allwinner A1x SoCs
ARM: sunxi: Add earlyprintk support
ARM: sunxi: Add device tree for the A13 and the Olinuxino board
ARM: sunxi: Add entry to MAINTAINERS
.../interrupt-controller/allwinner,sunxi-ic.txt | 104 ++++++++++++
.../bindings/timer/allwinner,sunxi-timer.txt | 15 ++
MAINTAINERS | 6 +
arch/arm/Kconfig | 2 +
arch/arm/Kconfig.debug | 8 +
arch/arm/Makefile | 1 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun5i-olinuxino.dts | 30 ++++
arch/arm/boot/dts/sun5i.dtsi | 58 +++++++
arch/arm/include/debug/sunxi.S | 22 +++
arch/arm/mach-sunxi/Kconfig | 9 +
arch/arm/mach-sunxi/Makefile | 1 +
arch/arm/mach-sunxi/Makefile.boot | 1 +
arch/arm/mach-sunxi/sunxi.c | 60 +++++++
arch/arm/mach-sunxi/sunxi.h | 20 +++
drivers/clocksource/Kconfig | 3 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/sunxi_timer.c | 160 ++++++++++++++++++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-sunxi.c | 173 ++++++++++++++++++++
include/linux/irqchip/sunxi.h | 27 +++
include/linux/sunxi_timer.h | 24 +++
22 files changed, 727 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
create mode 100644 arch/arm/boot/dts/sun5i-olinuxino.dts
create mode 100644 arch/arm/boot/dts/sun5i.dtsi
create mode 100644 arch/arm/include/debug/sunxi.S
create mode 100644 arch/arm/mach-sunxi/Kconfig
create mode 100644 arch/arm/mach-sunxi/Makefile
create mode 100644 arch/arm/mach-sunxi/Makefile.boot
create mode 100644 arch/arm/mach-sunxi/sunxi.c
create mode 100644 arch/arm/mach-sunxi/sunxi.h
create mode 100644 drivers/clocksource/sunxi_timer.c
create mode 100644 drivers/irqchip/irq-sunxi.c
create mode 100644 include/linux/irqchip/sunxi.h
create mode 100644 include/linux/sunxi_timer.h
--
1.7.9.5
^ permalink raw reply
* [PATCH 7/8] ARM: OMAP: Remove unnecessary inclusion of dmtimer.h
From: Greg Kroah-Hartman @ 2012-11-15 22:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CALLhW=5wiTd9u0PorwDH_68K7XRS8_ajDSDOLB7x8F2qvtJvaA@mail.gmail.com>
On Thu, Nov 15, 2012 at 02:42:13PM -0600, Omar Ramirez Luna wrote:
> Hi Jon,
>
> On 14 November 2012 09:53, Jon Hunter <jon-hunter@ti.com> wrote:
> >> diff --git a/drivers/staging/tidspbridge/core/ue_deh.c b/drivers/staging/tidspbridge/core/ue_deh.c
> >> index 3d28b23..6aea6f1 100644
> >> --- a/drivers/staging/tidspbridge/core/ue_deh.c
> >> +++ b/drivers/staging/tidspbridge/core/ue_deh.c
> >> @@ -19,7 +19,6 @@
> >>
> >> #include <linux/kernel.h>
> >> #include <linux/interrupt.h>
> >> -#include <plat/dmtimer.h>
> >>
> >> #include <dspbridge/dbdefs.h>
> >> #include <dspbridge/dspdeh.h>
> >
> > Hi Omar, I should have had you in copy on this one. Are you ok with the
> > removal of the above dmtimer.h include? It does not appear that this
> > file needs to include dmtimer.h.
>
> Indeed, we don't use it here.
>
> > Is it ok for this to go through Tony's tree? If so, care to ACK?
>
> Looks fine to me, but I believe you will want to let Greg know if this
> patch will bypass staging tree.
That's fine with me for such trivial stuff.
greg k-h
^ permalink raw reply
* [PATCH] arm/crypto: Make asm SHA-1 and AES code Thumb-2 compatible
From: Nicolas Pitre @ 2012-11-15 22:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352119337-22619-1-git-send-email-dave.martin@linaro.org>
On Mon, 5 Nov 2012, Dave Martin wrote:
> This patch fixes aes-armv4.S and sha1-armv4-large.S to work
> natively in Thumb. This allows ARM/Thumb interworking workarounds
> to be removed.
>
> I also take the opportunity to convert some explicit assembler
> directives for exported functions to the standard
> ENTRY()/ENDPROC().
>
> For the code itself:
>
> * In sha1_block_data_order, use of TEQ with sp is deprecated in
> ARMv7 and not supported in Thumb. For the branches back to
> .L_00_15 and .L_40_59, the TEQ is converted to a CMP, under the
> assumption that clobbering the C flag here will not cause
> incorrect behaviour.
>
> For the first branch back to .L_20_39_or_60_79 the C flag is
> important, so sp is moved temporarily into another register so
> that TEQ can be used for the comparison.
>
> * In the AES code, most forms of register-indexed addressing with
> shifts and rotates are not permitted for loads and stores in
> Thumb, so the address calculation is done using a separate
> instruction for the Thumb case.
>
> The resulting code is unlikely to be optimally scheduled, but
> it should not have a large impact given the overall size of the
> code. I haven't run any benchmarks.
>
> Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
I didn't test it either, only reviewed the patch. Looks obvious enough.
And if something is wrong, then it is very unlikely to be unnoticed in
practice.
> ---
>
> For now, I have built the code but not tested it. I'll consider the
> patch an RFC until someone gives me a Tested-by (or failing that, when I
> get around to testing it myself...)
>
> Cheers
> ---Dave
>
> arch/arm/crypto/aes-armv4.S | 64 +++++++++++------------------------
> arch/arm/crypto/sha1-armv4-large.S | 24 +++++--------
> 2 files changed, 29 insertions(+), 59 deletions(-)
>
> diff --git a/arch/arm/crypto/aes-armv4.S b/arch/arm/crypto/aes-armv4.S
> index e59b1d5..19d6cd6 100644
> --- a/arch/arm/crypto/aes-armv4.S
> +++ b/arch/arm/crypto/aes-armv4.S
> @@ -34,8 +34,9 @@
> @ A little glue here to select the correct code below for the ARM CPU
> @ that is being targetted.
>
> +#include <linux/linkage.h>
> +
> .text
> -.code 32
>
> .type AES_Te,%object
> .align 5
> @@ -145,10 +146,8 @@ AES_Te:
>
> @ void AES_encrypt(const unsigned char *in, unsigned char *out,
> @ const AES_KEY *key) {
> -.global AES_encrypt
> -.type AES_encrypt,%function
> .align 5
> -AES_encrypt:
> +ENTRY(AES_encrypt)
> sub r3,pc,#8 @ AES_encrypt
> stmdb sp!,{r1,r4-r12,lr}
> mov r12,r0 @ inp
> @@ -239,15 +238,8 @@ AES_encrypt:
> strb r6,[r12,#14]
> strb r3,[r12,#15]
> #endif
> -#if __ARM_ARCH__>=5
> ldmia sp!,{r4-r12,pc}
> -#else
> - ldmia sp!,{r4-r12,lr}
> - tst lr,#1
> - moveq pc,lr @ be binary compatible with V4, yet
> - .word 0xe12fff1e @ interoperable with Thumb ISA:-)
> -#endif
> -.size AES_encrypt,.-AES_encrypt
> +ENDPROC(AES_encrypt)
>
> .type _armv4_AES_encrypt,%function
> .align 2
> @@ -386,10 +378,8 @@ _armv4_AES_encrypt:
> ldr pc,[sp],#4 @ pop and return
> .size _armv4_AES_encrypt,.-_armv4_AES_encrypt
>
> -.global private_AES_set_encrypt_key
> -.type private_AES_set_encrypt_key,%function
> .align 5
> -private_AES_set_encrypt_key:
> +ENTRY(private_AES_set_encrypt_key)
> _armv4_AES_set_encrypt_key:
> sub r3,pc,#8 @ AES_set_encrypt_key
> teq r0,#0
> @@ -658,15 +648,11 @@ _armv4_AES_set_encrypt_key:
>
> .Ldone: mov r0,#0
> ldmia sp!,{r4-r12,lr}
> -.Labrt: tst lr,#1
> - moveq pc,lr @ be binary compatible with V4, yet
> - .word 0xe12fff1e @ interoperable with Thumb ISA:-)
> -.size private_AES_set_encrypt_key,.-private_AES_set_encrypt_key
> +.Labrt: mov pc,lr
> +ENDPROC(private_AES_set_encrypt_key)
>
> -.global private_AES_set_decrypt_key
> -.type private_AES_set_decrypt_key,%function
> .align 5
> -private_AES_set_decrypt_key:
> +ENTRY(private_AES_set_decrypt_key)
> str lr,[sp,#-4]! @ push lr
> #if 0
> @ kernel does both of these in setkey so optimise this bit out by
> @@ -748,15 +734,8 @@ private_AES_set_decrypt_key:
> bne .Lmix
>
> mov r0,#0
> -#if __ARM_ARCH__>=5
> ldmia sp!,{r4-r12,pc}
> -#else
> - ldmia sp!,{r4-r12,lr}
> - tst lr,#1
> - moveq pc,lr @ be binary compatible with V4, yet
> - .word 0xe12fff1e @ interoperable with Thumb ISA:-)
> -#endif
> -.size private_AES_set_decrypt_key,.-private_AES_set_decrypt_key
> +ENDPROC(private_AES_set_decrypt_key)
>
> .type AES_Td,%object
> .align 5
> @@ -862,10 +841,8 @@ AES_Td:
>
> @ void AES_decrypt(const unsigned char *in, unsigned char *out,
> @ const AES_KEY *key) {
> -.global AES_decrypt
> -.type AES_decrypt,%function
> .align 5
> -AES_decrypt:
> +ENTRY(AES_decrypt)
> sub r3,pc,#8 @ AES_decrypt
> stmdb sp!,{r1,r4-r12,lr}
> mov r12,r0 @ inp
> @@ -956,15 +933,8 @@ AES_decrypt:
> strb r6,[r12,#14]
> strb r3,[r12,#15]
> #endif
> -#if __ARM_ARCH__>=5
> ldmia sp!,{r4-r12,pc}
> -#else
> - ldmia sp!,{r4-r12,lr}
> - tst lr,#1
> - moveq pc,lr @ be binary compatible with V4, yet
> - .word 0xe12fff1e @ interoperable with Thumb ISA:-)
> -#endif
> -.size AES_decrypt,.-AES_decrypt
> +ENDPROC(AES_decrypt)
>
> .type _armv4_AES_decrypt,%function
> .align 2
> @@ -1064,7 +1034,9 @@ _armv4_AES_decrypt:
> and r9,lr,r1,lsr#8
>
> ldrb r7,[r10,r7] @ Td4[s1>>0]
> - ldrb r1,[r10,r1,lsr#24] @ Td4[s1>>24]
> + ARM( ldrb r1,[r10,r1,lsr#24] ) @ Td4[s1>>24]
> + THUMB( add r1,r10,r1,lsr#24 ) @ Td4[s1>>24]
> + THUMB( ldrb r1,[r1] )
> ldrb r8,[r10,r8] @ Td4[s1>>16]
> eor r0,r7,r0,lsl#24
> ldrb r9,[r10,r9] @ Td4[s1>>8]
> @@ -1077,7 +1049,9 @@ _armv4_AES_decrypt:
> ldrb r8,[r10,r8] @ Td4[s2>>0]
> and r9,lr,r2,lsr#16
>
> - ldrb r2,[r10,r2,lsr#24] @ Td4[s2>>24]
> + ARM( ldrb r2,[r10,r2,lsr#24] ) @ Td4[s2>>24]
> + THUMB( add r2,r10,r2,lsr#24 ) @ Td4[s2>>24]
> + THUMB( ldrb r2,[r2] )
> eor r0,r0,r7,lsl#8
> ldrb r9,[r10,r9] @ Td4[s2>>16]
> eor r1,r8,r1,lsl#16
> @@ -1090,7 +1064,9 @@ _armv4_AES_decrypt:
> and r9,lr,r3 @ i2
>
> ldrb r9,[r10,r9] @ Td4[s3>>0]
> - ldrb r3,[r10,r3,lsr#24] @ Td4[s3>>24]
> + ARM( ldrb r3,[r10,r3,lsr#24] ) @ Td4[s3>>24]
> + THUMB( add r3,r10,r3,lsr#24 ) @ Td4[s3>>24]
> + THUMB( ldrb r3,[r3] )
> eor r0,r0,r7,lsl#16
> ldr r7,[r11,#0]
> eor r1,r1,r8,lsl#8
> diff --git a/arch/arm/crypto/sha1-armv4-large.S b/arch/arm/crypto/sha1-armv4-large.S
> index 7050ab1..92c6eed 100644
> --- a/arch/arm/crypto/sha1-armv4-large.S
> +++ b/arch/arm/crypto/sha1-armv4-large.S
> @@ -51,13 +51,12 @@
> @ Profiler-assisted and platform-specific optimization resulted in 10%
> @ improvement on Cortex A8 core and 12.2 cycles per byte.
>
> -.text
> +#include <linux/linkage.h>
>
> -.global sha1_block_data_order
> -.type sha1_block_data_order,%function
> +.text
>
> .align 2
> -sha1_block_data_order:
> +ENTRY(sha1_block_data_order)
> stmdb sp!,{r4-r12,lr}
> add r2,r1,r2,lsl#6 @ r2 to point at the end of r1
> ldmia r0,{r3,r4,r5,r6,r7}
> @@ -194,7 +193,7 @@ sha1_block_data_order:
> eor r10,r10,r7,ror#2 @ F_00_19(B,C,D)
> str r9,[r14,#-4]!
> add r3,r3,r10 @ E+=F_00_19(B,C,D)
> - teq r14,sp
> + cmp r14,sp
> bne .L_00_15 @ [((11+4)*5+2)*3]
> #if __ARM_ARCH__<7
> ldrb r10,[r1,#2]
> @@ -374,7 +373,9 @@ sha1_block_data_order:
> @ F_xx_xx
> add r3,r3,r9 @ E+=X[i]
> add r3,r3,r10 @ E+=F_20_39(B,C,D)
> - teq r14,sp @ preserve carry
> + ARM( teq r14,sp ) @ preserve carry
> + THUMB( mov r11,sp )
> + THUMB( teq r14,r11 ) @ preserve carry
> bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4]
> bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes
>
> @@ -466,7 +467,7 @@ sha1_block_data_order:
> add r3,r3,r9 @ E+=X[i]
> add r3,r3,r10 @ E+=F_40_59(B,C,D)
> add r3,r3,r11,ror#2
> - teq r14,sp
> + cmp r14,sp
> bne .L_40_59 @ [+((12+5)*5+2)*4]
>
> ldr r8,.LK_60_79
> @@ -485,19 +486,12 @@ sha1_block_data_order:
> teq r1,r2
> bne .Lloop @ [+18], total 1307
>
> -#if __ARM_ARCH__>=5
> ldmia sp!,{r4-r12,pc}
> -#else
> - ldmia sp!,{r4-r12,lr}
> - tst lr,#1
> - moveq pc,lr @ be binary compatible with V4, yet
> - .word 0xe12fff1e @ interoperable with Thumb ISA:-)
> -#endif
> .align 2
> .LK_00_19: .word 0x5a827999
> .LK_20_39: .word 0x6ed9eba1
> .LK_40_59: .word 0x8f1bbcdc
> .LK_60_79: .word 0xca62c1d6
> -.size sha1_block_data_order,.-sha1_block_data_order
> +ENDPROC(sha1_block_data_order)
> .asciz "SHA1 block transform for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
> .align 2
> --
> 1.7.4.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply
* [PATCH] ARM: add get_user() support for 8 byte types
From: Nicolas Pitre @ 2012-11-15 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1353016879-15007-1-git-send-email-rob.clark@linaro.org>
On Thu, 15 Nov 2012, Rob Clark wrote:
> From: Rob Clark <rob@ti.com>
>
> A new atomic modeset/pageflip ioctl being developed in DRM requires
> get_user() to work for 64bit types (in addition to just put_user()).
>
> v1: original
> v2: pass correct size to check_uaccess, and better handling of narrowing
> double word read with __get_user_xb() (Russell King's suggestion)
> v3: explain in comment about why this works for narrowing fetch to 1,
> 2, or 4 byte type on ARM.
>
> Signed-off-by: Rob Clark <rob@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
> ---
> arch/arm/include/asm/uaccess.h | 22 +++++++++++++++++++++-
> arch/arm/lib/getuser.S | 17 ++++++++++++++++-
> 2 files changed, 37 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
> index 7e1f760..4cfa793 100644
> --- a/arch/arm/include/asm/uaccess.h
> +++ b/arch/arm/include/asm/uaccess.h
> @@ -100,6 +100,7 @@ static inline void set_fs(mm_segment_t fs)
> extern int __get_user_1(void *);
> extern int __get_user_2(void *);
> extern int __get_user_4(void *);
> +extern int __get_user_8(void *);
>
> #define __GUP_CLOBBER_1 "lr", "cc"
> #ifdef CONFIG_CPU_USE_DOMAINS
> @@ -108,6 +109,7 @@ extern int __get_user_4(void *);
> #define __GUP_CLOBBER_2 "lr", "cc"
> #endif
> #define __GUP_CLOBBER_4 "lr", "cc"
> +#define __GUP_CLOBBER_8 "lr", "cc"
>
> #define __get_user_x(__r2,__p,__e,__l,__s) \
> __asm__ __volatile__ ( \
> @@ -118,11 +120,23 @@ extern int __get_user_4(void *);
> : "0" (__p), "r" (__l) \
> : __GUP_CLOBBER_##__s)
>
> +/*
> + * Narrowing a double-word get into a single 32bit word register, which works
> + * for 1, 2, or 4 byte types on ARM because there are no integer registers
> + * smaller than 32bit
> + */
> +#ifdef BIG_ENDIAN
> +#define __get_user_xb(__r2,__p,__e,__l,__s) \
> + __get_user_x(__r2,(uintptr_t)__p + 4,__e,__l,__s)
> +#else
> +#define __get_user_xb __get_user_x
> +#endif
> +
> #define __get_user_check(x,p) \
> ({ \
> unsigned long __limit = current_thread_info()->addr_limit - 1; \
> register const typeof(*(p)) __user *__p asm("r0") = (p);\
> - register unsigned long __r2 asm("r2"); \
> + register typeof(x) __r2 asm("r2"); \
> register unsigned long __l asm("r1") = __limit; \
> register int __e asm("r0"); \
> switch (sizeof(*(__p))) { \
> @@ -135,6 +149,12 @@ extern int __get_user_4(void *);
> case 4: \
> __get_user_x(__r2, __p, __e, __l, 4); \
> break; \
> + case 8: \
> + if (sizeof((x)) < 8) \
> + __get_user_xb(__r2, __p, __e, __l, 4); \
> + else \
> + __get_user_x(__r2, __p, __e, __l, 8); \
> + break; \
> default: __e = __get_user_bad(); break; \
> } \
> x = (typeof(*(p))) __r2; \
> diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
> index 9b06bb4..ed98707 100644
> --- a/arch/arm/lib/getuser.S
> +++ b/arch/arm/lib/getuser.S
> @@ -18,7 +18,7 @@
> * Inputs: r0 contains the address
> * r1 contains the address limit, which must be preserved
> * Outputs: r0 is the error code
> - * r2 contains the zero-extended value
> + * r2, r3 contains the zero-extended value
> * lr corrupted
> *
> * No other registers must be altered. (see <asm/uaccess.h>
> @@ -66,6 +66,19 @@ ENTRY(__get_user_4)
> mov pc, lr
> ENDPROC(__get_user_4)
>
> +ENTRY(__get_user_8)
> + check_uaccess r0, 8, r1, r2, __get_user_bad
> +#ifdef CONFIG_THUMB2_KERNEL
> +5: TUSER(ldr) r2, [r0]
> +6: TUSER(ldr) r3, [r0, #4]
> +#else
> +5: TUSER(ldr) r2, [r0], #4
> +6: TUSER(ldr) r3, [r0]
> +#endif
> + mov r0, #0
> + mov pc, lr
> +ENDPROC(__get_user_8)
> +
> __get_user_bad:
> mov r2, #0
> mov r0, #-EFAULT
> @@ -77,4 +90,6 @@ ENDPROC(__get_user_bad)
> .long 2b, __get_user_bad
> .long 3b, __get_user_bad
> .long 4b, __get_user_bad
> + .long 5b, __get_user_bad
> + .long 6b, __get_user_bad
> .popsection
> --
> 1.8.0
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
>
^ permalink raw reply
* [PATCH] ARM: add get_user() support for 8 byte types
From: Rob Clark @ 2012-11-15 22:01 UTC (permalink / raw)
To: linux-arm-kernel
From: Rob Clark <rob@ti.com>
A new atomic modeset/pageflip ioctl being developed in DRM requires
get_user() to work for 64bit types (in addition to just put_user()).
v1: original
v2: pass correct size to check_uaccess, and better handling of narrowing
double word read with __get_user_xb() (Russell King's suggestion)
v3: explain in comment about why this works for narrowing fetch to 1,
2, or 4 byte type on ARM.
Signed-off-by: Rob Clark <rob@ti.com>
---
arch/arm/include/asm/uaccess.h | 22 +++++++++++++++++++++-
arch/arm/lib/getuser.S | 17 ++++++++++++++++-
2 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 7e1f760..4cfa793 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -100,6 +100,7 @@ static inline void set_fs(mm_segment_t fs)
extern int __get_user_1(void *);
extern int __get_user_2(void *);
extern int __get_user_4(void *);
+extern int __get_user_8(void *);
#define __GUP_CLOBBER_1 "lr", "cc"
#ifdef CONFIG_CPU_USE_DOMAINS
@@ -108,6 +109,7 @@ extern int __get_user_4(void *);
#define __GUP_CLOBBER_2 "lr", "cc"
#endif
#define __GUP_CLOBBER_4 "lr", "cc"
+#define __GUP_CLOBBER_8 "lr", "cc"
#define __get_user_x(__r2,__p,__e,__l,__s) \
__asm__ __volatile__ ( \
@@ -118,11 +120,23 @@ extern int __get_user_4(void *);
: "0" (__p), "r" (__l) \
: __GUP_CLOBBER_##__s)
+/*
+ * Narrowing a double-word get into a single 32bit word register, which works
+ * for 1, 2, or 4 byte types on ARM because there are no integer registers
+ * smaller than 32bit
+ */
+#ifdef BIG_ENDIAN
+#define __get_user_xb(__r2,__p,__e,__l,__s) \
+ __get_user_x(__r2,(uintptr_t)__p + 4,__e,__l,__s)
+#else
+#define __get_user_xb __get_user_x
+#endif
+
#define __get_user_check(x,p) \
({ \
unsigned long __limit = current_thread_info()->addr_limit - 1; \
register const typeof(*(p)) __user *__p asm("r0") = (p);\
- register unsigned long __r2 asm("r2"); \
+ register typeof(x) __r2 asm("r2"); \
register unsigned long __l asm("r1") = __limit; \
register int __e asm("r0"); \
switch (sizeof(*(__p))) { \
@@ -135,6 +149,12 @@ extern int __get_user_4(void *);
case 4: \
__get_user_x(__r2, __p, __e, __l, 4); \
break; \
+ case 8: \
+ if (sizeof((x)) < 8) \
+ __get_user_xb(__r2, __p, __e, __l, 4); \
+ else \
+ __get_user_x(__r2, __p, __e, __l, 8); \
+ break; \
default: __e = __get_user_bad(); break; \
} \
x = (typeof(*(p))) __r2; \
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index 9b06bb4..ed98707 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -18,7 +18,7 @@
* Inputs: r0 contains the address
* r1 contains the address limit, which must be preserved
* Outputs: r0 is the error code
- * r2 contains the zero-extended value
+ * r2, r3 contains the zero-extended value
* lr corrupted
*
* No other registers must be altered. (see <asm/uaccess.h>
@@ -66,6 +66,19 @@ ENTRY(__get_user_4)
mov pc, lr
ENDPROC(__get_user_4)
+ENTRY(__get_user_8)
+ check_uaccess r0, 8, r1, r2, __get_user_bad
+#ifdef CONFIG_THUMB2_KERNEL
+5: TUSER(ldr) r2, [r0]
+6: TUSER(ldr) r3, [r0, #4]
+#else
+5: TUSER(ldr) r2, [r0], #4
+6: TUSER(ldr) r3, [r0]
+#endif
+ mov r0, #0
+ mov pc, lr
+ENDPROC(__get_user_8)
+
__get_user_bad:
mov r2, #0
mov r0, #-EFAULT
@@ -77,4 +90,6 @@ ENDPROC(__get_user_bad)
.long 2b, __get_user_bad
.long 3b, __get_user_bad
.long 4b, __get_user_bad
+ .long 5b, __get_user_bad
+ .long 6b, __get_user_bad
.popsection
--
1.8.0
^ permalink raw reply related
* [PATCH 0/7] core, cpu and gated clocks for mvebu
From: Thomas Petazzoni @ 2012-11-15 21:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1353014906-31566-1-git-send-email-andrew@lunn.ch>
Dear Andrew Lunn,
On Thu, 15 Nov 2012 22:28:19 +0100, Andrew Lunn wrote:
> This patchset combines code from Gregory Clement, Sebastian
> Hesselbarth and myself to implement core clks, cpu clock and gated
> clocks on Marvel MVEBU SoCs.
>
> The Armada 370/XP core clock code is a refactored version of the
> already submitted and ACKed code from Gregory. It has been made to fit
> inside a framework developed by Sebastian which can handle all MVEBU
> SoCs. The Armarda 370/XP SoCs have more core clocks than the older SoCs, and
> the framework needs to handle this. Rather than specify the clock
> frequencies in DT, a Sample At Reset register is used, which describes
> each core clock frequency.
>
> Armarda XP is an SMP processor, with each CPU having its own
> clock. Gregories code for this has been taken as is.
>
> The Armarda 370/XP clock source has been converted to the common clock
> framework.
>
> Dove, Kirkword, and probably Armarda 370/XP have the ability to gate
> clocks to various blocks. A clk-gate clock is created for each of the
> gateable clocks on Dove and Kirkwood. Armarda 370/XP clock gates are
> currently unimplemented. Dove and Kirkwood board-dt.c and DT
> descriptions are then modified to make use of these clk gates.
I had a quick look and made a few comments, but overall, it looks
really great. I really hope we can get this in 3.8.
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 6/7] ARM: dove: switch to DT clock providers
From: Thomas Petazzoni @ 2012-11-15 21:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1353014906-31566-7-git-send-email-andrew@lunn.ch>
Dear Andrew Lunn,
On Thu, 15 Nov 2012 22:28:25 +0100, Andrew Lunn wrote:
> + core_clk: core-clocks at d0214 {
> + compatible = "marvell,dove-core-clocks";
> + reg = <0xd0214 0x4>;
> + #clock-cells = <1>;
> + };
> +
> + clk_gate: clock-gating-control at d0038 {
> + compatible = "marvell,dove-clock-gating";
> + reg = <0xd0038 0x4>;
> + clocks = <&core_clk 0>;
> + #clock-cells = <1>;
> + };
I'm nitpicking maybe, but names lack a bit of coherency here:
core_clk vs. clk_gate
marvell,dove-core-clocks vs. marvell,dove-clock-gating
Maybe:
core_clk / gate_clk
marvell,dove-core-clocks / marvell,dove-gating-clocks
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 4/7] clocksource: time-armada-370-xp converted to clk framework
From: Thomas Petazzoni @ 2012-11-15 21:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1353014906-31566-5-git-send-email-andrew@lunn.ch>
Dear Andrew Lunn,
Title should be "clocksource: convert time-armada-370-xp to the clk
framework".
On Thu, 15 Nov 2012 22:28:23 +0100, Andrew Lunn wrote:
> diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
> index 4674f94..a4605fd 100644
> --- a/drivers/clocksource/time-armada-370-xp.c
> +++ b/drivers/clocksource/time-armada-370-xp.c
> @@ -18,6 +18,7 @@
> #include <linux/init.h>
> #include <linux/platform_device.h>
> #include <linux/kernel.h>
> +#include <linux/clk.h>
> #include <linux/timer.h>
> #include <linux/clockchips.h>
> #include <linux/interrupt.h>
> @@ -167,7 +168,6 @@ void __init armada_370_xp_timer_init(void)
> u32 u;
> struct device_node *np;
> unsigned int timer_clk;
> - int ret;
> np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer");
> timer_base = of_iomap(np, 0);
> WARN_ON(!timer_base);
> @@ -179,13 +179,14 @@ void __init armada_370_xp_timer_init(void)
> timer_base + TIMER_CTRL_OFF);
> timer_clk = 25000000;
> } else {
> - u32 clk = 0;
> - ret = of_property_read_u32(np, "clock-frequency", &clk);
> - WARN_ON(!clk || ret < 0);
> + unsigned long rate = 0;
> + struct clk *clk = of_clk_get(np, 0);
> + WARN_ON(IS_ERR(clk));
> + rate = clk_get_rate(clk);
> u = readl(timer_base + TIMER_CTRL_OFF);
> writel(u & ~(TIMER0_25MHZ | TIMER1_25MHZ),
> timer_base + TIMER_CTRL_OFF);
> - timer_clk = clk / TIMER_DIVIDER;
> + timer_clk = rate / TIMER_DIVIDER;
> }
>
> /* We use timer 0 as clocksource, and timer 1 for
This change requires an update to
Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt. The
previous clock-frequency property was not documented, but maybe the new
clocks property should.
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 3/7] clk: armada-370-xp: add support for clock framework
From: Thomas Petazzoni @ 2012-11-15 21:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1353014906-31566-4-git-send-email-andrew@lunn.ch>
Dear Andrew Lunn,
On Thu, 15 Nov 2012 22:28:22 +0100, Andrew Lunn wrote:
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index 416d46e..e5f0ae2 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -9,11 +9,17 @@ config ARCH_MVEBU
> select PINCTRL
> select PLAT_ORION
> select SPARSE_IRQ
> + select CLKDEV_LOOKUP
> + select MVEBU_CLK_CORE
> + select MVEBU_CLK_CPU
>
> if ARCH_MVEBU
>
> menu "Marvell SOC with device tree"
>
> +config MVEBU_CLK_CPU
> + bool
> +
This config option is added to drivers/clk/mvebu/Kconfig in patch 2/7,
so I think it shouldn't be added here in patch 3/7.
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox