* [shawnguo:cleanup/clockevents 2/2] ERROR: "clockevents_config_and_register" [drivers/clocksource/cs5535-clockevt.ko] undefined!
From: Fengguang Wu @ 2013-01-11 12:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50efde33.imTwOnb1rtCKWsgz%yuanhan.liu@linux.intel.com>
Hi Shawn,
FYI, kernel build failed on
tree: git://git.linaro.org/people/shawnguo/linux-2.6.git cleanup/clockevents
head: ab8e73c98749a58c242b187c9799db70cd903157
commit: ab8e73c98749a58c242b187c9799db70cd903157 [2/2] clocksource: use clockevents_config_and_register() where possible
config: i386-randconfig-b030 (attached as .config)
All error/warnings:
>> ERROR: "clockevents_config_and_register" [drivers/clocksource/cs5535-clockevt.ko] undefined!
---
0-DAY kernel build testing backend Open Source Technology Center
Fengguang Wu, Yuanhan Liu Intel Corporation
-------------- next part --------------
#
# Automatically generated file; DO NOT EDIT.
# Linux/i386 3.8.0-rc1 Kernel Configuration
#
# CONFIG_64BIT is not set
CONFIG_X86_32=y
CONFIG_X86=y
CONFIG_INSTRUCTION_DECODER=y
CONFIG_OUTPUT_FORMAT="elf32-i386"
CONFIG_ARCH_DEFCONFIG="arch/x86/configs/i386_defconfig"
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_MMU=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_GPIO=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_HAS_CPU_RELAX=y
CONFIG_ARCH_HAS_DEFAULT_IDLE=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CPU_AUTOPROBE=y
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# CONFIG_ZONE_DMA32 is not set
# CONFIG_AUDIT_ARCH is not set
CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_X86_32_LAZY_GS=y
CONFIG_ARCH_HWEIGHT_CFLAGS="-fcall-saved-ecx -fcall-saved-edx"
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
CONFIG_HAVE_IRQ_WORK=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y
#
# General setup
#
# CONFIG_EXPERIMENTAL is not set
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE=""
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
# CONFIG_SYSVIPC is not set
CONFIG_FHANDLE=y
# CONFIG_AUDIT is not set
CONFIG_HAVE_GENERIC_HARDIRQS=y
#
# IRQ subsystem
#
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_IRQ_DOMAIN=y
# CONFIG_IRQ_DOMAIN_DEBUG is not set
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
CONFIG_CLOCKSOURCE_WATCHDOG=y
CONFIG_KTIME_SCALAR=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
CONFIG_GENERIC_CMOS_UPDATE=y
#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_IRQ_TIME_ACCOUNTING is not set
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
# CONFIG_TASK_IO_ACCOUNTING is not set
#
# RCU Subsystem
#
CONFIG_TINY_RCU=y
# CONFIG_PREEMPT_RCU is not set
# CONFIG_TREE_RCU_TRACE is not set
CONFIG_IKCONFIG=y
CONFIG_LOG_BUF_SHIFT=17
CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_ARCH_WANTS_PROT_NUMA_PROT_NONE=y
# CONFIG_CGROUPS is not set
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_NET_NS=y
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
CONFIG_RD_XZ=y
# CONFIG_RD_LZO is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_ANON_INODES=y
CONFIG_EXPERT=y
CONFIG_HAVE_UID16=y
CONFIG_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_PCSPKR_PLATFORM=y
CONFIG_HAVE_PCSPKR_PLATFORM=y
# CONFIG_BASE_FULL is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
# CONFIG_SIGNALFD is not set
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SHMEM is not set
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y
#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
CONFIG_DEBUG_PERF_USE_VMALLOC=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_PCI_QUIRKS=y
CONFIG_COMPAT_BRK=y
# CONFIG_SLAB is not set
# CONFIG_SLUB is not set
CONFIG_SLOB=y
CONFIG_PROFILING=y
# CONFIG_OPROFILE is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_OPROFILE_NMI_TIMER=y
# CONFIG_KPROBES is not set
CONFIG_JUMP_LABEL=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
CONFIG_HAVE_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP_FILTER=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_GENERIC_SIGALTSTACK=y
CONFIG_CLONE_BACKWARDS=y
#
# GCOV-based kernel profiling
#
CONFIG_GCOV_KERNEL=y
CONFIG_GCOV_PROFILE_ALL=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=1
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_BLOCK=y
# CONFIG_LBDAF is not set
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
# CONFIG_BLK_DEV_INTEGRITY is not set
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
CONFIG_ACORN_PARTITION=y
CONFIG_ACORN_PARTITION_CUMANA=y
CONFIG_ACORN_PARTITION_EESOX=y
# CONFIG_ACORN_PARTITION_ICS is not set
# CONFIG_ACORN_PARTITION_ADFS is not set
# CONFIG_ACORN_PARTITION_POWERTEC is not set
CONFIG_ACORN_PARTITION_RISCIX=y
# CONFIG_OSF_PARTITION is not set
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
# CONFIG_MAC_PARTITION is not set
# CONFIG_MSDOS_PARTITION is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
CONFIG_ULTRIX_PARTITION=y
CONFIG_SUN_PARTITION=y
CONFIG_KARMA_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_SYSV68_PARTITION=y
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_DEADLINE=m
CONFIG_IOSCHED_CFQ=m
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_FREEZER=y
#
# Processor type and features
#
CONFIG_ZONE_DMA=y
# CONFIG_SMP is not set
CONFIG_X86_MPPARSE=y
# CONFIG_X86_EXTENDED_PLATFORM is not set
CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_X86_32_IRIS is not set
# CONFIG_SCHED_OMIT_FRAME_POINTER is not set
CONFIG_PARAVIRT_GUEST=y
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_XEN_PRIVILEGED_GUEST is not set
CONFIG_KVM_GUEST=y
# CONFIG_LGUEST_GUEST is not set
CONFIG_PARAVIRT=y
CONFIG_PARAVIRT_CLOCK=y
# CONFIG_PARAVIRT_DEBUG is not set
CONFIG_NO_BOOTMEM=y
# CONFIG_MEMTEST is not set
# CONFIG_M486 is not set
# CONFIG_M586 is not set
# CONFIG_M586TSC is not set
# CONFIG_M586MMX is not set
CONFIG_M686=y
# CONFIG_MPENTIUMII is not set
# CONFIG_MPENTIUMIII is not set
# CONFIG_MPENTIUMM is not set
# CONFIG_MPENTIUM4 is not set
# CONFIG_MK6 is not set
# CONFIG_MK7 is not set
# CONFIG_MK8 is not set
# CONFIG_MCRUSOE is not set
# CONFIG_MEFFICEON is not set
# CONFIG_MWINCHIPC6 is not set
# CONFIG_MWINCHIP3D is not set
# CONFIG_MELAN is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
# CONFIG_MCYRIXIII is not set
# CONFIG_MVIAC3_2 is not set
# CONFIG_MVIAC7 is not set
# CONFIG_MCORE2 is not set
# CONFIG_MATOM is not set
CONFIG_X86_GENERIC=y
CONFIG_X86_INTERNODE_CACHE_SHIFT=6
CONFIG_X86_L1_CACHE_SHIFT=6
CONFIG_X86_PPRO_FENCE=y
CONFIG_X86_INTEL_USERCOPY=y
CONFIG_X86_USE_PPRO_CHECKSUM=y
CONFIG_X86_TSC=y
CONFIG_X86_CMPXCHG64=y
CONFIG_X86_CMOV=y
CONFIG_X86_MINIMUM_CPU_FAMILY=5
CONFIG_X86_DEBUGCTLMSR=y
CONFIG_PROCESSOR_SELECT=y
CONFIG_CPU_SUP_INTEL=y
CONFIG_CPU_SUP_CYRIX_32=y
# CONFIG_CPU_SUP_AMD is not set
# CONFIG_CPU_SUP_CENTAUR is not set
# CONFIG_CPU_SUP_TRANSMETA_32 is not set
# CONFIG_CPU_SUP_UMC_32 is not set
CONFIG_HPET_TIMER=y
CONFIG_DMI=y
CONFIG_NR_CPUS=1
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_PREEMPT_COUNT=y
CONFIG_X86_UP_APIC=y
CONFIG_X86_UP_IOAPIC=y
CONFIG_X86_LOCAL_APIC=y
CONFIG_X86_IO_APIC=y
# CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set
CONFIG_X86_MCE=y
CONFIG_X86_MCE_INTEL=y
# CONFIG_X86_MCE_AMD is not set
CONFIG_X86_ANCIENT_MCE=y
CONFIG_X86_MCE_THRESHOLD=y
CONFIG_X86_MCE_INJECT=m
CONFIG_X86_THERMAL_VECTOR=y
# CONFIG_VM86 is not set
CONFIG_TOSHIBA=m
CONFIG_I8K=m
CONFIG_X86_REBOOTFIXUPS=y
# CONFIG_MICROCODE is not set
# CONFIG_X86_MSR is not set
CONFIG_X86_CPUID=m
# CONFIG_NOHIGHMEM is not set
CONFIG_HIGHMEM4G=y
# CONFIG_HIGHMEM64G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_HIGHMEM=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ILLEGAL_POINTER_VALUE=0
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=999999
# CONFIG_COMPACTION is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_MMU_NOTIFIER=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
CONFIG_MEMORY_FAILURE=y
# CONFIG_TRANSPARENT_HUGEPAGE is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NEED_PER_CPU_KM=y
CONFIG_CLEANCACHE=y
# CONFIG_FRONTSWAP is not set
# CONFIG_HIGHPTE is not set
CONFIG_X86_CHECK_BIOS_CORRUPTION=y
CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
CONFIG_X86_RESERVE_LOW=64
CONFIG_MATH_EMULATION=y
# CONFIG_MTRR is not set
# CONFIG_ARCH_RANDOM is not set
# CONFIG_X86_SMAP is not set
# CONFIG_EFI is not set
CONFIG_SECCOMP=y
# CONFIG_CC_STACKPROTECTOR is not set
CONFIG_HZ_100=y
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
# CONFIG_KEXEC is not set
CONFIG_CRASH_DUMP=y
CONFIG_PHYSICAL_START=0x1000000
# CONFIG_RELOCATABLE is not set
CONFIG_PHYSICAL_ALIGN=0x1000000
# CONFIG_COMPAT_VDSO is not set
# CONFIG_CMDLINE_BOOL is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
#
# Power management and ACPI options
#
# CONFIG_SUSPEND is not set
CONFIG_HIBERNATE_CALLBACKS=y
CONFIG_HIBERNATION=y
CONFIG_PM_STD_PARTITION=""
CONFIG_PM_SLEEP=y
# CONFIG_PM_AUTOSLEEP is not set
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=100
CONFIG_PM_WAKELOCKS_GC=y
# CONFIG_PM_RUNTIME is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
# CONFIG_PM_ADVANCED_DEBUG is not set
CONFIG_PM_SLEEP_DEBUG=y
CONFIG_PM_TRACE=y
CONFIG_PM_TRACE_RTC=y
CONFIG_ACPI=y
CONFIG_ACPI_SLEEP=y
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=m
CONFIG_ACPI_FAN=y
CONFIG_ACPI_I2C=m
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_THERMAL=y
CONFIG_ACPI_CUSTOM_DSDT_FILE=""
# CONFIG_ACPI_CUSTOM_DSDT is not set
# CONFIG_ACPI_INITRD_TABLE_OVERRIDE is not set
CONFIG_ACPI_BLACKLIST_YEAR=0
# CONFIG_ACPI_DEBUG is not set
# CONFIG_ACPI_PCI_SLOT is not set
CONFIG_X86_PM_TIMER=y
# CONFIG_ACPI_SBS is not set
# CONFIG_ACPI_HED is not set
# CONFIG_ACPI_CUSTOM_METHOD is not set
# CONFIG_ACPI_APEI is not set
CONFIG_SFI=y
# CONFIG_APM is not set
#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_TABLE=m
CONFIG_CPU_FREQ_STAT=m
# CONFIG_CPU_FREQ_STAT_DETAILS is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=m
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
#
# x86 CPU frequency scaling drivers
#
# CONFIG_X86_PCC_CPUFREQ is not set
# CONFIG_X86_ACPI_CPUFREQ is not set
# CONFIG_X86_POWERNOW_K6 is not set
CONFIG_X86_POWERNOW_K7=m
CONFIG_X86_POWERNOW_K7_ACPI=y
# CONFIG_X86_POWERNOW_K8 is not set
# CONFIG_X86_GX_SUSPMOD is not set
CONFIG_X86_SPEEDSTEP_CENTRINO=m
CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE=y
# CONFIG_X86_SPEEDSTEP_ICH is not set
CONFIG_X86_P4_CLOCKMOD=m
# CONFIG_X86_LONGRUN is not set
# CONFIG_X86_LONGHAUL is not set
#
# shared options
#
CONFIG_X86_SPEEDSTEP_LIB=m
CONFIG_CPU_IDLE=y
# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set
CONFIG_CPU_IDLE_GOV_LADDER=y
# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
# CONFIG_INTEL_IDLE is not set
#
# Bus options (PCI etc.)
#
CONFIG_PCI=y
# CONFIG_PCI_GOBIOS is not set
# CONFIG_PCI_GOMMCONFIG is not set
# CONFIG_PCI_GODIRECT is not set
CONFIG_PCI_GOANY=y
CONFIG_PCI_BIOS=y
CONFIG_PCI_DIRECT=y
CONFIG_PCI_MMCONFIG=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PCIEPORTBUS is not set
CONFIG_ARCH_SUPPORTS_MSI=y
CONFIG_PCI_MSI=y
CONFIG_PCI_DEBUG=y
CONFIG_PCI_REALLOC_ENABLE_AUTO=y
# CONFIG_PCI_STUB is not set
# CONFIG_HT_IRQ is not set
CONFIG_PCI_ATS=y
CONFIG_PCI_IOV=y
# CONFIG_PCI_PRI is not set
CONFIG_PCI_PASID=y
# CONFIG_PCI_IOAPIC is not set
CONFIG_PCI_LABEL=y
CONFIG_ISA_DMA_API=y
# CONFIG_ISA is not set
CONFIG_SCx200=m
CONFIG_SCx200HR_TIMER=m
# CONFIG_OLPC is not set
# CONFIG_ALIX is not set
# CONFIG_NET5501 is not set
CONFIG_GEOS=y
# CONFIG_PCCARD is not set
CONFIG_HOTPLUG_PCI=m
# CONFIG_HOTPLUG_PCI_COMPAQ is not set
CONFIG_HOTPLUG_PCI_IBM=m
# CONFIG_HOTPLUG_PCI_ACPI is not set
CONFIG_HOTPLUG_PCI_CPCI=y
# CONFIG_HOTPLUG_PCI_CPCI_ZT5550 is not set
CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m
CONFIG_HOTPLUG_PCI_SHPC=m
CONFIG_RAPIDIO=y
CONFIG_RAPIDIO_DISC_TIMEOUT=30
# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set
CONFIG_RAPIDIO_DMA_ENGINE=y
CONFIG_RAPIDIO_DEBUG=y
# CONFIG_RAPIDIO_TSI57X is not set
CONFIG_RAPIDIO_CPS_XX=y
CONFIG_RAPIDIO_TSI568=y
CONFIG_RAPIDIO_CPS_GEN2=y
CONFIG_RAPIDIO_TSI500=y
#
# Executable file formats / Emulations
#
CONFIG_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_HAVE_AOUT=y
CONFIG_BINFMT_AOUT=m
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
CONFIG_HAVE_ATOMIC_IOMAP=y
CONFIG_HAVE_TEXT_POKE_SMP=y
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=m
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
# CONFIG_UNIX_DIAG is not set
CONFIG_XFRM=y
CONFIG_XFRM_ALGO=m
CONFIG_NET_KEY=m
# CONFIG_INET is not set
CONFIG_NETWORK_SECMARK=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_DEBUG=y
# CONFIG_NETFILTER_ADVANCED is not set
# CONFIG_BRIDGE_NF_EBTABLES is not set
CONFIG_ATM=m
# CONFIG_ATM_LANE is not set
CONFIG_STP=m
CONFIG_GARP=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
# CONFIG_DECNET is not set
CONFIG_LLC=m
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_PHONET is not set
# CONFIG_NET_SCHED is not set
CONFIG_DCB=y
CONFIG_BATMAN_ADV=m
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_OPENVSWITCH is not set
CONFIG_BQL=y
#
# Network testing
#
# CONFIG_HAMRADIO is not set
CONFIG_CAN=m
CONFIG_CAN_RAW=m
# CONFIG_CAN_BCM is not set
# CONFIG_CAN_GW is not set
#
# CAN Device Drivers
#
CONFIG_CAN_VCAN=m
# CONFIG_CAN_SLCAN is not set
# CONFIG_CAN_DEV is not set
CONFIG_CAN_DEBUG_DEVICES=y
# CONFIG_IRDA is not set
CONFIG_BT=m
CONFIG_BT_RFCOMM=m
# CONFIG_BT_RFCOMM_TTY is not set
# CONFIG_BT_BNEP is not set
# CONFIG_BT_HIDP is not set
#
# Bluetooth device drivers
#
# CONFIG_BT_HCIBTUSB is not set
# CONFIG_BT_HCIBTSDIO is not set
# CONFIG_BT_HCIUART is not set
# CONFIG_BT_HCIBCM203X is not set
# CONFIG_BT_HCIBPA10X is not set
# CONFIG_BT_HCIBFUSB is not set
CONFIG_BT_HCIVHCI=m
# CONFIG_BT_MRVL is not set
# CONFIG_WIRELESS is not set
# CONFIG_WIMAX is not set
CONFIG_RFKILL=m
# CONFIG_RFKILL_INPUT is not set
CONFIG_RFKILL_REGULATOR=m
CONFIG_NET_9P=m
CONFIG_NET_9P_DEBUG=y
# CONFIG_CAIF is not set
# CONFIG_NFC is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_FW_LOADER=m
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_GENERIC_CPU_DEVICES is not set
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=m
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=m
CONFIG_REGMAP_IRQ=y
# CONFIG_DMA_SHARED_BUFFER is not set
# CONFIG_CMA is not set
#
# Bus devices
#
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y
#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_FD is not set
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
# CONFIG_BLK_CPQ_DA is not set
CONFIG_BLK_CPQ_CISS_DA=m
CONFIG_BLK_DEV_DAC960=m
CONFIG_BLK_DEV_UMEM=m
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS or INET not selected
#
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_NVME=m
CONFIG_BLK_DEV_SX8=m
CONFIG_BLK_DEV_RAM=m
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_XIP=y
CONFIG_CDROM_PKTCDVD=m
CONFIG_CDROM_PKTCDVD_BUFFERS=8
CONFIG_CDROM_PKTCDVD_WCACHE=y
CONFIG_ATA_OVER_ETH=m
CONFIG_BLK_DEV_HD=y
#
# Misc devices
#
# CONFIG_SENSORS_LIS3LV02D is not set
# CONFIG_AD525X_DPOT is not set
# CONFIG_IBM_ASM is not set
# CONFIG_PHANTOM is not set
# CONFIG_INTEL_MID_PTI is not set
CONFIG_SGI_IOC4=m
# CONFIG_TIFM_CORE is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
CONFIG_CS5535_MFGPT=m
CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7
CONFIG_CS5535_CLOCK_EVENT_SRC=m
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
CONFIG_ISL29003=m
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1780 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
CONFIG_TI_DAC7512=m
# CONFIG_VMWARE_BALLOON is not set
CONFIG_BMP085=y
CONFIG_BMP085_I2C=m
# CONFIG_BMP085_SPI is not set
CONFIG_PCH_PHUB=m
# CONFIG_USB_SWITCH_FSA9480 is not set
# CONFIG_C2PORT is not set
#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_CB710_CORE is not set
#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# CONFIG_SENSORS_LIS3_I2C is not set
#
# Altera FPGA firmware download module
#
# CONFIG_ALTERA_STAPL is not set
CONFIG_INTEL_MEI=m
CONFIG_HAVE_IDE=y
CONFIG_IDE=m
#
# Please see Documentation/ide/ide.txt for help/info on IDE drives
#
CONFIG_IDE_XFER_MODE=y
CONFIG_IDE_TIMINGS=y
CONFIG_IDE_ATAPI=y
CONFIG_BLK_DEV_IDE_SATA=y
CONFIG_IDE_GD=m
CONFIG_IDE_GD_ATA=y
CONFIG_IDE_GD_ATAPI=y
# CONFIG_BLK_DEV_IDECD is not set
# CONFIG_BLK_DEV_IDETAPE is not set
# CONFIG_BLK_DEV_IDEACPI is not set
CONFIG_IDE_TASK_IOCTL=y
#
# IDE chipset support/bugfixes
#
# CONFIG_IDE_GENERIC is not set
# CONFIG_BLK_DEV_PLATFORM is not set
CONFIG_BLK_DEV_CMD640=m
CONFIG_BLK_DEV_CMD640_ENHANCED=y
# CONFIG_BLK_DEV_IDEPNP is not set
CONFIG_BLK_DEV_IDEDMA_SFF=y
#
# PCI IDE chipsets support
#
CONFIG_BLK_DEV_IDEPCI=y
# CONFIG_BLK_DEV_OFFBOARD is not set
CONFIG_BLK_DEV_GENERIC=m
CONFIG_BLK_DEV_RZ1000=m
CONFIG_BLK_DEV_IDEDMA_PCI=y
CONFIG_BLK_DEV_AEC62XX=m
# CONFIG_BLK_DEV_ALI15X3 is not set
CONFIG_BLK_DEV_AMD74XX=m
CONFIG_BLK_DEV_ATIIXP=m
CONFIG_BLK_DEV_CMD64X=m
# CONFIG_BLK_DEV_TRIFLEX is not set
# CONFIG_BLK_DEV_CS5530 is not set
CONFIG_BLK_DEV_CS5535=m
CONFIG_BLK_DEV_CS5536=m
CONFIG_BLK_DEV_HPT366=m
# CONFIG_BLK_DEV_JMICRON is not set
CONFIG_BLK_DEV_SC1200=m
CONFIG_BLK_DEV_PIIX=m
CONFIG_BLK_DEV_IT8172=m
CONFIG_BLK_DEV_IT8213=m
# CONFIG_BLK_DEV_IT821X is not set
CONFIG_BLK_DEV_NS87415=m
CONFIG_BLK_DEV_PDC202XX_OLD=m
# CONFIG_BLK_DEV_PDC202XX_NEW is not set
CONFIG_BLK_DEV_SVWKS=m
CONFIG_BLK_DEV_SIIMAGE=m
# CONFIG_BLK_DEV_SIS5513 is not set
# CONFIG_BLK_DEV_SLC90E66 is not set
CONFIG_BLK_DEV_TRM290=m
# CONFIG_BLK_DEV_VIA82CXXX is not set
# CONFIG_BLK_DEV_TC86C001 is not set
CONFIG_BLK_DEV_IDEDMA=y
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=m
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
# CONFIG_MD_RAID0 is not set
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
# CONFIG_MD_RAID456 is not set
# CONFIG_MD_MULTIPATH is not set
# CONFIG_MD_FAULTY is not set
# CONFIG_BLK_DEV_DM is not set
CONFIG_FUSION=y
CONFIG_FUSION_MAX_SGE=128
CONFIG_FUSION_LOGGING=y
#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
CONFIG_FIREWIRE_NOSY=m
CONFIG_I2O=m
# CONFIG_I2O_LCT_NOTIFY_ON_CHANGES is not set
# CONFIG_I2O_EXT_ADAPTEC is not set
# CONFIG_I2O_CONFIG is not set
# CONFIG_I2O_BUS is not set
# CONFIG_I2O_BLOCK is not set
CONFIG_I2O_PROC=m
# CONFIG_MACINTOSH_DRIVERS is not set
# CONFIG_NETDEVICES is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_MATRIXKMAP is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_STMPE is not set
# CONFIG_KEYBOARD_XTKBD is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_GPIO is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_MOUSE_SYNAPTICS_USB is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
CONFIG_GAMEPORT=m
# CONFIG_GAMEPORT_NS558 is not set
CONFIG_GAMEPORT_L4=m
CONFIG_GAMEPORT_EMU10K1=m
CONFIG_GAMEPORT_FM801=m
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_UNIX98_PTYS is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_SERIAL_NONSTANDARD is not set
CONFIG_NOZOMI=m
CONFIG_N_GSM=m
# CONFIG_TRACE_SINK is not set
# CONFIG_DEVKMEM is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_PNP=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_SERIAL_8250_PCI=m
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
CONFIG_SERIAL_MFD_HSU=m
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
CONFIG_SERIAL_SCCNXP=m
CONFIG_SERIAL_TIMBERDALE=m
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
CONFIG_SERIAL_IFX6X60=m
CONFIG_SERIAL_PCH_UART=m
# CONFIG_SERIAL_ARC is not set
# CONFIG_TTY_PRINTK is not set
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=m
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
CONFIG_HW_RANDOM_INTEL=m
# CONFIG_HW_RANDOM_AMD is not set
# CONFIG_HW_RANDOM_GEODE is not set
CONFIG_HW_RANDOM_VIA=m
CONFIG_HW_RANDOM_TPM=m
CONFIG_NVRAM=m
CONFIG_R3964=m
CONFIG_APPLICOM=m
# CONFIG_SONYPI is not set
# CONFIG_MWAVE is not set
# CONFIG_SCx200_GPIO is not set
# CONFIG_PC8736x_GPIO is not set
# CONFIG_NSC_GPIO is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HPET is not set
CONFIG_HANGCHECK_TIMER=m
CONFIG_TCG_TPM=m
# CONFIG_TCG_TIS is not set
# CONFIG_TCG_TIS_I2C_INFINEON is not set
# CONFIG_TCG_NSC is not set
# CONFIG_TCG_ATMEL is not set
# CONFIG_TCG_INFINEON is not set
# CONFIG_TELCLOCK is not set
CONFIG_DEVPORT=y
CONFIG_I2C=m
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=m
# CONFIG_I2C_MUX is not set
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=m
CONFIG_I2C_ALGOBIT=m
CONFIG_I2C_ALGOPCA=m
#
# I2C Hardware Bus support
#
#
# PC SMBus host controller drivers
#
CONFIG_I2C_ALI1535=m
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
CONFIG_I2C_AMD8111=m
# CONFIG_I2C_I801 is not set
CONFIG_I2C_ISCH=m
# CONFIG_I2C_PIIX4 is not set
CONFIG_I2C_NFORCE2=m
CONFIG_I2C_SIS5595=m
CONFIG_I2C_SIS630=m
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIAPRO is not set
#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=m
CONFIG_I2C_DESIGNWARE_PCI=m
CONFIG_I2C_EG20T=m
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_INTEL_MID is not set
CONFIG_I2C_PCA_PLATFORM=m
# CONFIG_I2C_PXA_PCI is not set
CONFIG_I2C_SIMTEC=m
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
CONFIG_I2C_PARPORT_LIGHT=m
# CONFIG_I2C_TINY_USB is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_SCx200_ACB is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
CONFIG_I2C_DEBUG_BUS=y
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
#
# SPI Master Controller Drivers
#
CONFIG_SPI_ALTERA=m
CONFIG_SPI_BITBANG=m
# CONFIG_SPI_GPIO is not set
CONFIG_SPI_OC_TINY=m
# CONFIG_SPI_PXA2XX_PCI is not set
CONFIG_SPI_SC18IS602=m
# CONFIG_SPI_TOPCLIFF_PCH is not set
CONFIG_SPI_XCOMM=m
# CONFIG_SPI_DESIGNWARE is not set
#
# SPI Protocol Masters
#
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_HSI is not set
#
# PPS support
#
CONFIG_PPS=m
# CONFIG_PPS_DEBUG is not set
# CONFIG_NTP_PPS is not set
#
# PPS clients support
#
CONFIG_PPS_CLIENT_KTIMER=m
# CONFIG_PPS_CLIENT_LDISC is not set
# CONFIG_PPS_CLIENT_GPIO is not set
#
# PPS generators support
#
#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=m
#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
CONFIG_PTP_1588_CLOCK_PCH=m
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_ACPI=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_GENERIC=m
CONFIG_GPIO_DA9052=m
CONFIG_GPIO_MAX730X=m
#
# Memory mapped GPIO drivers:
#
CONFIG_GPIO_GENERIC_PLATFORM=m
# CONFIG_GPIO_IT8761E is not set
# CONFIG_GPIO_TS5500 is not set
CONFIG_GPIO_SCH=m
CONFIG_GPIO_ICH=m
CONFIG_GPIO_VX855=m
#
# I2C GPIO expanders:
#
CONFIG_GPIO_ARIZONA=m
# CONFIG_GPIO_MAX7300 is not set
CONFIG_GPIO_MAX732X=m
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_STMPE is not set
CONFIG_GPIO_TPS65912=m
CONFIG_GPIO_ADP5588=m
#
# PCI GPIO expanders:
#
# CONFIG_GPIO_CS5535 is not set
CONFIG_GPIO_BT8XX=m
# CONFIG_GPIO_AMD8111 is not set
# CONFIG_GPIO_LANGWELL is not set
# CONFIG_GPIO_PCH is not set
# CONFIG_GPIO_ML_IOH is not set
# CONFIG_GPIO_TIMBERDALE is not set
CONFIG_GPIO_RDC321X=m
#
# SPI GPIO expanders:
#
CONFIG_GPIO_MAX7301=m
CONFIG_GPIO_MCP23S08=m
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_74X164 is not set
#
# AC97 GPIO expanders:
#
#
# MODULbus GPIO expanders:
#
#
# USB GPIO expanders:
#
CONFIG_W1=m
#
# 1-wire Bus Masters
#
# CONFIG_W1_MASTER_MATROX is not set
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
# CONFIG_W1_MASTER_DS1WM is not set
# CONFIG_W1_MASTER_GPIO is not set
#
# 1-wire Slaves
#
# CONFIG_W1_SLAVE_THERM is not set
# CONFIG_W1_SLAVE_SMEM is not set
CONFIG_W1_SLAVE_DS2408=m
# CONFIG_W1_SLAVE_DS2423 is not set
CONFIG_W1_SLAVE_DS2431=m
# CONFIG_W1_SLAVE_DS2433 is not set
CONFIG_W1_SLAVE_DS2760=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
# CONFIG_W1_SLAVE_DS28E04 is not set
# CONFIG_W1_SLAVE_BQ27000 is not set
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_DEBUG=y
# CONFIG_PDA_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_BATTERY_BQ27x00 is not set
CONFIG_BATTERY_DA9052=m
CONFIG_BATTERY_MAX17040=m
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
CONFIG_CHARGER_GPIO=m
CONFIG_CHARGER_MANAGER=y
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_POWER_RESET is not set
CONFIG_POWER_AVS=y
CONFIG_HWMON=m
CONFIG_HWMON_VID=m
# CONFIG_HWMON_DEBUG_CHIP is not set
#
# Native drivers
#
# CONFIG_SENSORS_ABITUGURU is not set
CONFIG_SENSORS_ABITUGURU3=m
CONFIG_SENSORS_AD7314=m
CONFIG_SENSORS_AD7414=m
CONFIG_SENSORS_AD7418=m
CONFIG_SENSORS_ADCXX=m
CONFIG_SENSORS_ADM1021=m
# CONFIG_SENSORS_ADM1025 is not set
CONFIG_SENSORS_ADM1026=m
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
CONFIG_SENSORS_ADT7410=m
CONFIG_SENSORS_ADT7411=m
CONFIG_SENSORS_ADT7462=m
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
CONFIG_SENSORS_ASC7621=m
CONFIG_SENSORS_K8TEMP=m
# CONFIG_SENSORS_K10TEMP is not set
# CONFIG_SENSORS_FAM15H_POWER is not set
CONFIG_SENSORS_ASB100=m
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS620 is not set
CONFIG_SENSORS_DS1621=m
# CONFIG_SENSORS_DA9052_ADC is not set
CONFIG_SENSORS_I5K_AMB=m
# CONFIG_SENSORS_F71805F is not set
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_F75375S=m
# CONFIG_SENSORS_FSCHMD is not set
CONFIG_SENSORS_G760A=m
CONFIG_SENSORS_GL518SM=m
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_GPIO_FAN=m
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_CORETEMP is not set
CONFIG_SENSORS_IT87=m
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
CONFIG_SENSORS_LM73=m
# CONFIG_SENSORS_LM75 is not set
CONFIG_SENSORS_LM77=m
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4245 is not set
CONFIG_SENSORS_LTC4261=m
CONFIG_SENSORS_LM95241=m
CONFIG_SENSORS_LM95245=m
CONFIG_SENSORS_MAX1111=m
# CONFIG_SENSORS_MAX16065 is not set
CONFIG_SENSORS_MAX1619=m
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX6639 is not set
CONFIG_SENSORS_MAX6642=m
CONFIG_SENSORS_MAX6650=m
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
CONFIG_SENSORS_PC87360=m
CONFIG_SENSORS_PC87427=m
CONFIG_SENSORS_PCF8591=m
CONFIG_PMBUS=m
CONFIG_SENSORS_PMBUS=m
# CONFIG_SENSORS_ADM1275 is not set
CONFIG_SENSORS_LM25066=m
CONFIG_SENSORS_LTC2978=m
# CONFIG_SENSORS_MAX16064 is not set
# CONFIG_SENSORS_MAX34440 is not set
CONFIG_SENSORS_MAX8688=m
CONFIG_SENSORS_UCD9000=m
CONFIG_SENSORS_UCD9200=m
# CONFIG_SENSORS_ZL6100 is not set
CONFIG_SENSORS_SHT15=m
CONFIG_SENSORS_SHT21=m
CONFIG_SENSORS_SIS5595=m
CONFIG_SENSORS_SMM665=m
CONFIG_SENSORS_DME1737=m
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
CONFIG_SENSORS_SMSC47M192=m
CONFIG_SENSORS_SMSC47B397=m
# CONFIG_SENSORS_SCH56XX_COMMON is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_ADS1015 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_THMC50 is not set
CONFIG_SENSORS_TMP102=m
# CONFIG_SENSORS_TMP401 is not set
CONFIG_SENSORS_TMP421=m
CONFIG_SENSORS_VIA_CPUTEMP=m
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
CONFIG_SENSORS_VT8231=m
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
CONFIG_SENSORS_W83627EHF=m
# CONFIG_SENSORS_APPLESMC is not set
CONFIG_SENSORS_MC13783_ADC=m
#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
# CONFIG_SENSORS_ATK0110 is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_FAIR_SHARE is not set
CONFIG_STEP_WISE=y
# CONFIG_USER_SPACE is not set
# CONFIG_CPU_THERMAL is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_NOWAYOUT=y
#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
# CONFIG_DA9052_WATCHDOG is not set
CONFIG_ACQUIRE_WDT=m
CONFIG_ADVANTECH_WDT=m
CONFIG_ALIM1535_WDT=m
CONFIG_ALIM7101_WDT=m
CONFIG_F71808E_WDT=m
CONFIG_SP5100_TCO=m
CONFIG_GEODE_WDT=m
# CONFIG_SC520_WDT is not set
# CONFIG_SBC_FITPC2_WATCHDOG is not set
# CONFIG_EUROTECH_WDT is not set
# CONFIG_IB700_WDT is not set
# CONFIG_IBMASR is not set
CONFIG_WAFER_WDT=m
CONFIG_I6300ESB_WDT=m
CONFIG_IE6XX_WDT=m
# CONFIG_ITCO_WDT is not set
# CONFIG_IT8712F_WDT is not set
# CONFIG_IT87_WDT is not set
CONFIG_HP_WATCHDOG=m
# CONFIG_HPWDT_NMI_DECODING is not set
CONFIG_SC1200_WDT=m
CONFIG_SCx200_WDT=m
# CONFIG_PC87413_WDT is not set
CONFIG_NV_TCO=m
# CONFIG_60XX_WDT is not set
CONFIG_SBC8360_WDT=m
# CONFIG_SBC7240_WDT is not set
# CONFIG_CPU5_WDT is not set
# CONFIG_SMSC_SCH311X_WDT is not set
# CONFIG_SMSC37B787_WDT is not set
# CONFIG_VIA_WDT is not set
# CONFIG_W83627HF_WDT is not set
# CONFIG_W83697HF_WDT is not set
CONFIG_W83697UG_WDT=m
CONFIG_W83877F_WDT=m
CONFIG_W83977F_WDT=m
CONFIG_MACHZ_WDT=m
CONFIG_SBC_EPX_C3_WATCHDOG=m
#
# PCI-based Watchdog Cards
#
CONFIG_PCIPCWATCHDOG=m
CONFIG_WDTPCI=m
#
# USB-based Watchdog Cards
#
CONFIG_USBPCWATCHDOG=m
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
CONFIG_SSB=m
CONFIG_SSB_SPROM=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
# CONFIG_SSB_B43_PCI_BRIDGE is not set
CONFIG_SSB_SDIOHOST_POSSIBLE=y
# CONFIG_SSB_SDIOHOST is not set
CONFIG_SSB_SILENT=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE=y
# CONFIG_SSB_DRIVER_GPIO is not set
CONFIG_BCMA_POSSIBLE=y
#
# Broadcom specific AMBA
#
# CONFIG_BCMA is not set
#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_RTSX_PCI is not set
CONFIG_MFD_TI_AM335X_TSCADC=m
CONFIG_HTC_PASIC3=m
# CONFIG_MFD_LM3533 is not set
CONFIG_TPS6105X=m
# CONFIG_TPS65010 is not set
CONFIG_TPS6507X=m
CONFIG_MFD_TPS65217=m
CONFIG_MFD_TPS65912=y
CONFIG_MFD_TPS65912_SPI=y
CONFIG_MFD_STMPE=y
#
# STMPE Interface Drivers
#
# CONFIG_STMPE_SPI is not set
# CONFIG_MFD_TMIO is not set
CONFIG_PMIC_DA9052=y
CONFIG_MFD_DA9052_SPI=y
CONFIG_MFD_ARIZONA=y
CONFIG_MFD_ARIZONA_I2C=m
CONFIG_MFD_ARIZONA_SPI=m
# CONFIG_MFD_WM5102 is not set
# CONFIG_MFD_WM5110 is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_PCF50633 is not set
CONFIG_MFD_MC13783=m
CONFIG_MFD_MC13XXX=m
CONFIG_MFD_MC13XXX_SPI=m
CONFIG_MFD_MC13XXX_I2C=m
# CONFIG_ABX500_CORE is not set
CONFIG_EZX_PCAP=y
CONFIG_MFD_CS5535=m
CONFIG_MFD_TIMBERDALE=m
CONFIG_LPC_SCH=m
CONFIG_LPC_ICH=m
CONFIG_MFD_RDC321X=m
# CONFIG_MFD_JANZ_CMODIO is not set
CONFIG_MFD_VX855=m
CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_RETU is not set
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
# CONFIG_REGULATOR_DUMMY is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=m
CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_GPIO is not set
# CONFIG_REGULATOR_AD5398 is not set
# CONFIG_REGULATOR_ARIZONA is not set
CONFIG_REGULATOR_DA9052=m
# CONFIG_REGULATOR_FAN53555 is not set
# CONFIG_REGULATOR_MC13783 is not set
# CONFIG_REGULATOR_MC13892 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8952 is not set
CONFIG_REGULATOR_MAX8973=m
CONFIG_REGULATOR_PCAP=m
# CONFIG_REGULATOR_LP3971 is not set
CONFIG_REGULATOR_LP3972=m
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS6105X is not set
CONFIG_REGULATOR_TPS62360=m
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS65217 is not set
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_REGULATOR_TPS65912 is not set
# CONFIG_MEDIA_SUPPORT is not set
#
# Graphics support
#
CONFIG_AGP=m
CONFIG_AGP_ALI=m
# CONFIG_AGP_ATI is not set
# CONFIG_AGP_AMD is not set
CONFIG_AGP_INTEL=m
# CONFIG_AGP_NVIDIA is not set
# CONFIG_AGP_SIS is not set
# CONFIG_AGP_SWORKS is not set
# CONFIG_AGP_VIA is not set
CONFIG_AGP_EFFICEON=m
# CONFIG_VGA_ARB is not set
# CONFIG_VGA_SWITCHEROO is not set
# CONFIG_DRM is not set
CONFIG_STUB_POULSBO=m
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
# CONFIG_FB is not set
# CONFIG_EXYNOS_VIDEO is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=m
CONFIG_BACKLIGHT_GENERIC=m
# CONFIG_BACKLIGHT_PWM is not set
# CONFIG_BACKLIGHT_DA9052 is not set
# CONFIG_BACKLIGHT_APPLE is not set
CONFIG_BACKLIGHT_SAHARA=m
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3630 is not set
CONFIG_BACKLIGHT_LM3639=m
# CONFIG_BACKLIGHT_LP855X is not set
# CONFIG_BACKLIGHT_TPS65217 is not set
# CONFIG_SOUND is not set
#
# HID support
#
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HIDRAW is not set
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y
#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_ACRUX is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_AUREAL is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_CHICONY is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_TWINHAN is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LENOVO_TPKBD is not set
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_SAITEK is not set
# CONFIG_HID_SAMSUNG is not set
# CONFIG_HID_SONY is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set
#
# USB HID support
#
CONFIG_USB_HID=m
# CONFIG_HID_PID is not set
# CONFIG_USB_HIDDEV is not set
#
# USB HID Boot Protocol drivers
#
# CONFIG_USB_KBD is not set
# CONFIG_USB_MOUSE is not set
#
# I2C HID support
#
# CONFIG_I2C_HID is not set
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
CONFIG_USB_ARCH_HAS_XHCI=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=m
# CONFIG_USB_DEBUG is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
#
# Miscellaneous USB options
#
CONFIG_USB_DYNAMIC_MINORS=y
CONFIG_USB_OTG_WHITELIST=y
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_MON is not set
CONFIG_USB_WUSB=m
# CONFIG_USB_WUSB_CBAF is not set
#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=m
CONFIG_USB_XHCI_HCD=m
# CONFIG_USB_XHCI_HCD_DEBUGGING is not set
# CONFIG_USB_EHCI_HCD is not set
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
# CONFIG_USB_ISP1760_HCD is not set
CONFIG_USB_ISP1362_HCD=m
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_UHCI_HCD is not set
CONFIG_USB_SL811_HCD=m
CONFIG_USB_SL811_HCD_ISO=y
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_WHCI_HCD is not set
CONFIG_USB_HWA_HCD=m
CONFIG_USB_HCD_SSB=m
# CONFIG_USB_CHIPIDEA is not set
#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
# CONFIG_USB_PRINTER is not set
CONFIG_USB_WDM=m
CONFIG_USB_TMC=m
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
#
# also be needed; see USB_STORAGE Help for more info
#
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set
#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
# CONFIG_USB_EMI26 is not set
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_RIO500=m
# CONFIG_USB_LEGOTOWER is not set
CONFIG_USB_LCD=m
CONFIG_USB_LED=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
CONFIG_USB_APPLEDISPLAY=m
# CONFIG_USB_LD is not set
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_YUREX is not set
# CONFIG_USB_EZUSB_FX2 is not set
#
# USB Physical Layer drivers
#
# CONFIG_USB_ISP1301 is not set
CONFIG_USB_RCAR_PHY=m
# CONFIG_USB_ATM is not set
# CONFIG_USB_GADGET is not set
#
# OTG and related infrastructure
#
CONFIG_USB_OTG_UTILS=y
CONFIG_USB_GPIO_VBUS=m
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_UWB=m
CONFIG_UWB_HWA=m
# CONFIG_UWB_WHCI is not set
# CONFIG_UWB_I1480U is not set
CONFIG_MMC=m
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_UNSAFE_RESUME=y
#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=m
CONFIG_MMC_BLOCK_MINORS=8
CONFIG_MMC_BLOCK_BOUNCE=y
CONFIG_SDIO_UART=m
# CONFIG_MMC_TEST is not set
#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_SDHCI is not set
CONFIG_MMC_WBSD=m
# CONFIG_MMC_CB710 is not set
# CONFIG_MMC_VIA_SDMMC is not set
CONFIG_MMC_VUB300=m
# CONFIG_MMC_USHC is not set
CONFIG_MEMSTICK=m
CONFIG_MEMSTICK_DEBUG=y
#
# MemoryStick drivers
#
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
CONFIG_MSPRO_BLOCK=m
#
# MemoryStick Host Controller Drivers
#
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
#
# LED drivers
#
CONFIG_LEDS_LM3530=m
CONFIG_LEDS_LM3642=m
CONFIG_LEDS_GPIO=m
# CONFIG_LEDS_LP3944 is not set
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
# CONFIG_LEDS_CLEVO_MAIL is not set
CONFIG_LEDS_PCA955X=m
# CONFIG_LEDS_PCA9633 is not set
# CONFIG_LEDS_DA9052 is not set
# CONFIG_LEDS_DAC124S085 is not set
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_INTEL_SS4200 is not set
CONFIG_LEDS_LT3593=m
# CONFIG_LEDS_MC13783 is not set
# CONFIG_LEDS_TCA6507 is not set
# CONFIG_LEDS_LM355x is not set
CONFIG_LEDS_OT200=m
CONFIG_LEDS_BLINKM=m
# CONFIG_LEDS_TRIGGERS is not set
#
# LED Triggers
#
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
# CONFIG_EDAC is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
CONFIG_RTC_DEBUG=y
#
# RTC interfaces
#
# CONFIG_RTC_INTF_SYSFS is not set
# CONFIG_RTC_INTF_DEV is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_DS1374=m
CONFIG_RTC_DRV_DS1672=m
CONFIG_RTC_DRV_DS3232=m
# CONFIG_RTC_DRV_MAX6900 is not set
CONFIG_RTC_DRV_RS5C372=m
CONFIG_RTC_DRV_ISL1208=m
CONFIG_RTC_DRV_ISL12022=m
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
CONFIG_RTC_DRV_PCF8583=m
# CONFIG_RTC_DRV_M41T80 is not set
CONFIG_RTC_DRV_BQ32K=m
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RX8025=m
CONFIG_RTC_DRV_EM3027=m
# CONFIG_RTC_DRV_RV3029C2 is not set
#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
CONFIG_RTC_DRV_M41T94=m
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1390 is not set
CONFIG_RTC_DRV_MAX6902=m
# CONFIG_RTC_DRV_R9701 is not set
CONFIG_RTC_DRV_RS5C348=m
CONFIG_RTC_DRV_DS3234=m
CONFIG_RTC_DRV_PCF2123=m
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
CONFIG_RTC_DRV_DS1286=m
# CONFIG_RTC_DRV_DS1511 is not set
CONFIG_RTC_DRV_DS1553=m
# CONFIG_RTC_DRV_DS1742 is not set
CONFIG_RTC_DRV_DA9052=m
# CONFIG_RTC_DRV_STK17TA8 is not set
CONFIG_RTC_DRV_M48T86=m
# CONFIG_RTC_DRV_M48T35 is not set
CONFIG_RTC_DRV_M48T59=m
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
CONFIG_RTC_DRV_RP5C01=m
CONFIG_RTC_DRV_V3020=m
# CONFIG_RTC_DRV_DS2404 is not set
#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_PCAP is not set
# CONFIG_RTC_DRV_MC13XXX is not set
CONFIG_DMADEVICES=y
CONFIG_DMADEVICES_DEBUG=y
CONFIG_DMADEVICES_VDEBUG=y
#
# DMA Devices
#
# CONFIG_INTEL_MID_DMAC is not set
# CONFIG_INTEL_IOATDMA is not set
CONFIG_TIMB_DMA=m
# CONFIG_PCH_DMA is not set
CONFIG_DMA_ENGINE=y
#
# DMA Clients
#
CONFIG_NET_DMA=y
# CONFIG_ASYNC_TX_DMA is not set
CONFIG_DMATEST=m
# CONFIG_AUXDISPLAY is not set
CONFIG_UIO=m
# CONFIG_UIO_CIF is not set
CONFIG_UIO_PDRV=m
# CONFIG_UIO_PDRV_GENIRQ is not set
CONFIG_UIO_DMEM_GENIRQ=m
CONFIG_UIO_AEC=m
CONFIG_UIO_SERCOS3=m
CONFIG_UIO_PCI_GENERIC=m
CONFIG_UIO_NETX=m
#
# Virtio drivers
#
#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# CONFIG_STAGING is not set
# CONFIG_X86_PLATFORM_DEVICES is not set
#
# Hardware Spinlock drivers
#
CONFIG_CLKSRC_I8253=y
CONFIG_CLKEVT_I8253=y
CONFIG_I8253_LOCK=y
CONFIG_CLKBLD_I8253=y
# CONFIG_IOMMU_SUPPORT is not set
#
# Remoteproc drivers (EXPERIMENTAL)
#
#
# Rpmsg drivers (EXPERIMENTAL)
#
CONFIG_VIRT_DRIVERS=y
# CONFIG_PM_DEVFREQ is not set
CONFIG_EXTCON=y
#
# Extcon Device Drivers
#
CONFIG_EXTCON_GPIO=m
# CONFIG_EXTCON_ARIZONA is not set
# CONFIG_MEMORY is not set
# CONFIG_IIO is not set
CONFIG_VME_BUS=m
#
# VME Bridge Drivers
#
CONFIG_VME_CA91CX42=m
# CONFIG_VME_TSI148 is not set
#
# VME Board Drivers
#
CONFIG_VMIVME_7805=m
#
# VME Device Drivers
#
CONFIG_PWM=y
# CONFIG_IPACK_BUS is not set
#
# Firmware Drivers
#
# CONFIG_EDD is not set
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DELL_RBU=m
# CONFIG_DCDBAS is not set
# CONFIG_DMIID is not set
# CONFIG_DMI_SYSFS is not set
# CONFIG_ISCSI_IBFT_FIND is not set
# CONFIG_GOOGLE_FIRMWARE is not set
#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_EXT2_FS=m
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=m
CONFIG_EXT4_USE_FOR_EXT23=y
CONFIG_EXT4_FS_POSIX_ACL=y
# CONFIG_EXT4_FS_SECURITY is not set
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=m
CONFIG_JBD2_DEBUG=y
CONFIG_FS_MBCACHE=m
# CONFIG_REISERFS_FS is not set
CONFIG_JFS_FS=m
# CONFIG_JFS_POSIX_ACL is not set
# CONFIG_JFS_SECURITY is not set
CONFIG_JFS_DEBUG=y
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=m
CONFIG_XFS_QUOTA=y
# CONFIG_XFS_POSIX_ACL is not set
CONFIG_XFS_RT=y
CONFIG_OCFS2_FS=m
# CONFIG_OCFS2_FS_O2CB is not set
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
CONFIG_OCFS2_DEBUG_FS=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
# CONFIG_FILE_LOCKING is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
CONFIG_QUOTA=y
# CONFIG_QUOTA_NETLINK_INTERFACE is not set
# CONFIG_PRINT_QUOTA_WARNING is not set
CONFIG_QUOTA_DEBUG=y
CONFIG_QUOTA_TREE=m
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=m
CONFIG_QUOTACTL=y
CONFIG_AUTOFS4_FS=m
# CONFIG_FUSE_FS is not set
#
# Caches
#
CONFIG_FSCACHE=m
CONFIG_FSCACHE_DEBUG=y
CONFIG_CACHEFILES=m
CONFIG_CACHEFILES_DEBUG=y
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
CONFIG_UDF_FS=m
CONFIG_UDF_NLS=y
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
# CONFIG_PROC_FS is not set
CONFIG_SYSFS=y
# CONFIG_HUGETLBFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_CONFIGFS_FS=m
CONFIG_MISC_FILESYSTEMS=y
CONFIG_HFSPLUS_FS=m
CONFIG_CRAMFS=m
CONFIG_SQUASHFS=m
CONFIG_SQUASHFS_XATTR=y
# CONFIG_SQUASHFS_ZLIB is not set
# CONFIG_SQUASHFS_LZO is not set
CONFIG_SQUASHFS_XZ=y
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
CONFIG_QNX4FS_FS=m
CONFIG_QNX6FS_FS=m
# CONFIG_QNX6FS_DEBUG is not set
CONFIG_ROMFS_FS=m
CONFIG_ROMFS_BACKED_BY_BLOCK=y
CONFIG_ROMFS_ON_BLOCK=y
# CONFIG_PSTORE is not set
CONFIG_SYSV_FS=m
# CONFIG_UFS_FS is not set
# CONFIG_F2FS_FS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
# CONFIG_NLS_CODEPAGE_775 is not set
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
CONFIG_NLS_CODEPAGE_864=m
# CONFIG_NLS_CODEPAGE_865 is not set
CONFIG_NLS_CODEPAGE_866=m
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
CONFIG_NLS_CODEPAGE_950=m
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
CONFIG_NLS_CODEPAGE_874=m
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
# CONFIG_NLS_ISO8859_1 is not set
CONFIG_NLS_ISO8859_2=m
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
CONFIG_NLS_ISO8859_5=m
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
CONFIG_NLS_ISO8859_13=m
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
# CONFIG_NLS_MAC_ROMAN is not set
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
CONFIG_NLS_MAC_GREEK=m
# CONFIG_NLS_MAC_ICELAND is not set
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=m
#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_PRINTK_TIME=y
CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
CONFIG_ENABLE_WARN_DEPRECATED=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_READABLE_ASM is not set
CONFIG_UNUSED_SYMBOLS=y
CONFIG_DEBUG_FS=y
CONFIG_HEADERS_CHECK=y
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_HARDLOCKUP_DETECTOR=y
# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_DEBUG_OBJECTS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_PI_LIST=y
# CONFIG_RT_MUTEX_TESTER is not set
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_PROVE_LOCKING=y
# CONFIG_PROVE_RCU is not set
# CONFIG_SPARSE_RCU_POINTER is not set
CONFIG_LOCKDEP=y
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_LOCKDEP is not set
CONFIG_TRACE_IRQFLAGS=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
CONFIG_DEBUG_LOCKING_API_SELFTESTS=y
CONFIG_STACKTRACE=y
CONFIG_DEBUG_STACK_USAGE=y
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_HIGHMEM=y
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_INFO is not set
CONFIG_DEBUG_VM=y
# CONFIG_DEBUG_VM_RB is not set
# CONFIG_DEBUG_VIRTUAL is not set
CONFIG_DEBUG_WRITECOUNT=y
# CONFIG_DEBUG_MEMORY_INIT is not set
CONFIG_DEBUG_LIST=y
CONFIG_TEST_LIST_SORT=y
CONFIG_DEBUG_SG=y
# CONFIG_DEBUG_NOTIFIERS is not set
CONFIG_DEBUG_CREDENTIALS=y
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_BOOT_PRINTK_DELAY is not set
CONFIG_RCU_TORTURE_TEST=m
CONFIG_RCU_TRACE=y
# CONFIG_BACKTRACE_SELF_TEST is not set
CONFIG_DEBUG_BLOCK_EXT_DEVT=y
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
CONFIG_FAULT_INJECTION=y
# CONFIG_FAIL_PAGE_ALLOC is not set
CONFIG_FAIL_MAKE_REQUEST=y
CONFIG_FAIL_IO_TIMEOUT=y
# CONFIG_FAIL_MMC_REQUEST is not set
CONFIG_FAULT_INJECTION_DEBUG_FS=y
# CONFIG_FAULT_INJECTION_STACKTRACE_FILTER is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
CONFIG_RBTREE_TEST=m
CONFIG_INTERVAL_TREE_TEST=m
CONFIG_PROVIDE_OHCI1394_DMA_INIT=y
CONFIG_BUILD_DOCSRC=y
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_DMA_API_DEBUG is not set
CONFIG_ATOMIC64_SELFTEST=y
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_KMEMCHECK=y
# CONFIG_TEST_KSTRTOX is not set
CONFIG_STRICT_DEVMEM=y
CONFIG_X86_VERBOSE_BOOTUP=y
# CONFIG_EARLY_PRINTK is not set
# CONFIG_DEBUG_STACKOVERFLOW is not set
# CONFIG_X86_PTDUMP is not set
CONFIG_DEBUG_RODATA=y
# CONFIG_DEBUG_RODATA_TEST is not set
# CONFIG_DEBUG_SET_MODULE_RONX is not set
CONFIG_DEBUG_NX_TEST=m
CONFIG_DOUBLEFAULT=y
CONFIG_IOMMU_STRESS=y
CONFIG_HAVE_MMIOTRACE_SUPPORT=y
CONFIG_IO_DELAY_TYPE_0X80=0
CONFIG_IO_DELAY_TYPE_0XED=1
CONFIG_IO_DELAY_TYPE_UDELAY=2
CONFIG_IO_DELAY_TYPE_NONE=3
# CONFIG_IO_DELAY_0X80 is not set
# CONFIG_IO_DELAY_0XED is not set
# CONFIG_IO_DELAY_UDELAY is not set
CONFIG_IO_DELAY_NONE=y
CONFIG_DEFAULT_IO_DELAY_TYPE=3
CONFIG_DEBUG_BOOT_PARAMS=y
# CONFIG_CPA_DEBUG is not set
# CONFIG_OPTIMIZE_INLINING is not set
# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set
CONFIG_DEBUG_NMI_SELFTEST=y
#
# Security options
#
# CONFIG_KEYS is not set
CONFIG_SECURITY_DMESG_RESTRICT=y
# CONFIG_SECURITY is not set
CONFIG_SECURITYFS=y
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=m
#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=m
CONFIG_CRYPTO_ALGAPI2=m
CONFIG_CRYPTO_AEAD=m
CONFIG_CRYPTO_AEAD2=m
CONFIG_CRYPTO_BLKCIPHER=m
CONFIG_CRYPTO_BLKCIPHER2=m
CONFIG_CRYPTO_HASH=m
CONFIG_CRYPTO_HASH2=m
CONFIG_CRYPTO_RNG=m
CONFIG_CRYPTO_RNG2=m
CONFIG_CRYPTO_PCOMP=m
CONFIG_CRYPTO_PCOMP2=m
CONFIG_CRYPTO_MANAGER=m
CONFIG_CRYPTO_MANAGER2=m
# CONFIG_CRYPTO_USER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=m
# CONFIG_CRYPTO_NULL is not set
CONFIG_CRYPTO_WORKQUEUE=m
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_ABLK_HELPER_X86=m
#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=m
CONFIG_CRYPTO_SEQIV=m
#
# Block modes
#
CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_CTR=m
CONFIG_CRYPTO_CTS=m
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=m
#
# Hash modes
#
CONFIG_CRYPTO_HMAC=m
#
# Digest
#
CONFIG_CRYPTO_CRC32C=m
CONFIG_CRYPTO_CRC32C_INTEL=m
CONFIG_CRYPTO_GHASH=m
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
CONFIG_CRYPTO_MICHAEL_MIC=m
# CONFIG_CRYPTO_RMD128 is not set
CONFIG_CRYPTO_RMD160=m
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
CONFIG_CRYPTO_SHA1=m
CONFIG_CRYPTO_SHA256=m
CONFIG_CRYPTO_SHA512=m
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set
#
# Ciphers
#
CONFIG_CRYPTO_AES=m
CONFIG_CRYPTO_AES_586=m
CONFIG_CRYPTO_AES_NI_INTEL=m
# CONFIG_CRYPTO_ANUBIS is not set
CONFIG_CRYPTO_ARC4=m
# CONFIG_CRYPTO_BLOWFISH is not set
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
# CONFIG_CRYPTO_CAST6 is not set
CONFIG_CRYPTO_DES=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
# CONFIG_CRYPTO_SEED is not set
CONFIG_CRYPTO_SERPENT=m
# CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_COMMON=m
CONFIG_CRYPTO_TWOFISH_586=m
#
# Compression
#
# CONFIG_CRYPTO_DEFLATE is not set
CONFIG_CRYPTO_ZLIB=m
CONFIG_CRYPTO_LZO=m
#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_USER_API=m
CONFIG_CRYPTO_USER_API_HASH=m
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_PADLOCK is not set
# CONFIG_CRYPTO_DEV_GEODE is not set
CONFIG_CRYPTO_DEV_HIFN_795X=m
CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_APIC_ARCHITECTURE=y
CONFIG_KVM_MMIO=y
CONFIG_KVM_ASYNC_PF=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
# CONFIG_KVM_INTEL is not set
CONFIG_KVM_AMD=m
# CONFIG_BINARY_PRINTF is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IO=y
CONFIG_PERCPU_RWSEM=y
CONFIG_CRC_CCITT=m
CONFIG_CRC16=m
# CONFIG_CRC_T10DIF is not set
CONFIG_CRC_ITU_T=m
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
# CONFIG_CRC7 is not set
CONFIG_LIBCRC32C=m
# CONFIG_CRC8 is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_ARM=y
# CONFIG_XZ_DEC_ARMTHUMB is not set
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_CHECK_SIGNATURE=y
CONFIG_DQL=y
CONFIG_NLATTR=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
# CONFIG_AVERAGE is not set
# CONFIG_CORDIC is not set
CONFIG_DDR=y
^ permalink raw reply
* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
From: Lorenzo Pieralisi @ 2013-01-11 12:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357888829.2034.39.camel@jlo-ubuntu-64.nvidia.com>
On Fri, Jan 11, 2013 at 07:20:29AM +0000, Joseph Lo wrote:
> Hi Lorenzo,
>
> On Wed, 2012-12-05 at 18:50 +0800, Lorenzo Pieralisi wrote:
> > On Wed, Dec 05, 2012 at 10:01:49AM +0000, Joseph Lo wrote:
> > > The powered-down state of Tegra20 requires power gating both CPU cores.
> > > When the secondary CPU requests to enter powered-down state, it saves
> > > its own contexts and then enters WFI. The Tegra20 had a limition to
> > > power down both CPU cores. The secondary CPU must waits for CPU0 in
> > > powered-down state too. If the secondary CPU be woken up before CPU0
> > > entering powered-down state, then it needs to restore its CPU states
> > > and waits for next chance.
> > >
> > > Be aware of that, you may see the legacy power state "LP2" in the code
> > > which is exactly the same meaning of "CPU power down".
> > >
> > > Based on the work by:
> > > Colin Cross <ccross@android.com>
> > > Gary King <gking@nvidia.com>
> > >
> > > Signed-off-by: Joseph Lo <josephl@nvidia.com>
> > > +
> > > +#ifdef CONFIG_PM_SLEEP
> > > +/*
> > > + * tegra_pen_lock
> > > + *
> > > + * spinlock implementation with no atomic test-and-set and no coherence
> > > + * using Peterson's algorithm on strongly-ordered registers
> > > + * used to synchronize a cpu waking up from wfi with entering lp2 on idle
> > > + *
> > > + * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
> > > + * on cpu 0:
> > > + * SCRATCH38 = r2 = flag[0]
> > > + * SCRATCH39 = r3 = flag[1]
> > > + * on cpu1:
> > > + * SCRATCH39 = r2 = flag[1]
> > > + * SCRATCH38 = r3 = flag[0]
> > > + *
> > > + * must be called with MMU on
> > > + * corrupts r0-r3, r12
> > > + */
> > > +ENTRY(tegra_pen_lock)
> > > + mov32 r3, TEGRA_PMC_VIRT
> > > + cpu_id r0
> > > + add r1, r3, #PMC_SCRATCH37
> > > + cmp r0, #0
> > > + addeq r2, r3, #PMC_SCRATCH38
> > > + addeq r3, r3, #PMC_SCRATCH39
> > > + addne r2, r3, #PMC_SCRATCH39
> > > + addne r3, r3, #PMC_SCRATCH38
> > > +
> > > + mov r12, #1
> > > + str r12, [r2] @ flag[cpu] = 1
> > > + dsb
> > > + str r12, [r1] @ !turn = cpu
> > > +1: dsb
> > > + ldr r12, [r3]
> > > + cmp r12, #1 @ flag[!cpu] == 1?
> > > + ldreq r12, [r1]
> > > + cmpeq r12, r0 @ !turn == cpu?
> > > + beq 1b @ while !turn == cpu && flag[!cpu] == 1
> > > +
> > > + mov pc, lr @ locked
> > > +ENDPROC(tegra_pen_lock)
> > > +
> > > +ENTRY(tegra_pen_unlock)
> > > + dsb
> > > + mov32 r3, TEGRA_PMC_VIRT
> > > + cpu_id r0
> > > + cmp r0, #0
> > > + addeq r2, r3, #PMC_SCRATCH38
> > > + addne r2, r3, #PMC_SCRATCH39
> > > + mov r12, #0
> > > + str r12, [r2]
> > > + mov pc, lr
> > > +ENDPROC(tegra_pen_unlock)
> >
> > There is an ongoing work to make this locking scheme for MMU/coherency off
> > paths ARM generic, and we do not want to merge yet another platform specific
> > locking mechanism. I will point you to the patchset when it hits LAK.
> >
>
> You did mention there is an ARM generic locking scheme for MMU/coherency
> off case before. Do you mean the patch below?
>
> https://patchwork.kernel.org/patch/1957911/
> https://patchwork.kernel.org/patch/1957901/
Those are used for first-man election when multiple CPUs come out of
idle at once.
You should have a look at the entire series and in particular:
https://patchwork.kernel.org/patch/1957891/
https://patchwork.kernel.org/patch/1957951/
> I gave it a review today. Looks it can't fit our usage for CPU idle
> powered-down mode on Tegra20.
>
> The generic mechanism only can be used when CPUs in non coherent world.
> But our usage needs the mechanism could be used in both coherent and non
> coherent case. OK. The case is we need to sync the status about the CPU1
> was ready to power down. In this case, the CPU0 is still in coherent
> world but the CPU1 isn't. So we need the locking scheme could be still
> safe in this situation.
I know, I implemented something of that sort for an A9 based development
platform, that's why I pointed you to this new patchset.
Have a look at the series, it should do what you want.
> And the proposed scheme looks only for b.L system?
No it works also for single cluster systems. Please have a look and let
me know if you have any questions or comment on the thread so that
authors can help you understand the code.
Lorenzo
^ permalink raw reply
* [PATCH 01/16] ARM: b.L: secondary kernel entry code
From: Dave Martin @ 2013-01-11 12:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111114552.GB12560@localhost.cambridge.arm.com>
On Fri, Jan 11, 2013 at 11:45:53AM +0000, Catalin Marinas wrote:
> On Thu, Jan 10, 2013 at 04:47:09PM +0000, Nicolas Pitre wrote:
> > On Thu, 10 Jan 2013, Catalin Marinas wrote:
> > > On 10 January 2013 00:20, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> > > > --- /dev/null
> > > > +++ b/arch/arm/common/bL_entry.c
> > > ...
> > > > +extern volatile unsigned long bL_entry_vectors[BL_NR_CLUSTERS][BL_CPUS_PER_CLUSTER];
> > >
> > > IMHO, we should keep this array linear and ignore the cluster grouping
> > > at this stage. This information could be added to latter patches that
> > > actually need to know about the b.L topology.
> >
> > That's virtually all of them. Everything b.L related is always
> > expressed in terms of a cpu,cluster tuple at the low level.
> >
> > > This would also imply that we treat the MPIDR just as an ID without
> > > digging into its bit layout.
> >
> > That makes for too large an index space. We always end up needing to
> > break the MPIDR into a cpu,cluster thing as the MPIDR bits are too
> > sparse.
>
> You could find a way to compress this with some mask and shifts. We can
> look at this later if we are to generalise this to non-b.L systems.
The b.L cluster handling code has multiple instances of this issue.
We should either try to fix them all, or defer them all as being
overkill for the foreseeable future.
For current platforms, the space saved in unlikely to be larger than
the amount of code required to implement the optimisation.
I do think we need a good, generic way to map sparesely-populated,
multidimensional topological node IDs to/from a linear space, but
we should avoid reinventing that too many times.
I think Lorenzo was already potentially looking at this issue in
relation to managing cpu_logical_map.
Cheers
---Dave
^ permalink raw reply
* [PATCH v4 7/9] clk: tegra: add clock support for tegra30
From: Hiroshi Doyu @ 2013-01-11 12:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357890387-23245-8-git-send-email-pgaikwad@nvidia.com>
On Fri, 11 Jan 2013 08:46:25 +0100
Prashant Gaikwad <pgaikwad@nvidia.com> wrote:
> Add tegra30 clock support based on common clock framework.
>
> Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
.......
> +static void __init tegra30_pll_init(void)
> +{
> + struct clk *clk;
> +
> + /* PLLC */
> + clk = tegra_clk_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
> + 0, &pll_c_params,
> + TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
> + pll_c_freq_table, NULL);
> + clk_register_clkdev(clk, "pll_c", NULL);
> + clks[pll_c] = clk;
Just I noticed that there are quite many same itegration of:
clk_register_clkdev(clk, <ID name>, ?);
clks[<ID>] = clk;
ID == <ID name>
Can any macro/func do the above at once?
^ permalink raw reply
* [PATCH 01/16] ARM: b.L: secondary kernel entry code
From: Lorenzo Pieralisi @ 2013-01-11 12:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111114552.GB12560@localhost.cambridge.arm.com>
On Fri, Jan 11, 2013 at 11:45:53AM +0000, Catalin Marinas wrote:
> On Thu, Jan 10, 2013 at 04:47:09PM +0000, Nicolas Pitre wrote:
> > On Thu, 10 Jan 2013, Catalin Marinas wrote:
> > > On 10 January 2013 00:20, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> > > > --- /dev/null
> > > > +++ b/arch/arm/common/bL_entry.c
> > > ...
> > > > +extern volatile unsigned long bL_entry_vectors[BL_NR_CLUSTERS][BL_CPUS_PER_CLUSTER];
> > >
> > > IMHO, we should keep this array linear and ignore the cluster grouping
> > > at this stage. This information could be added to latter patches that
> > > actually need to know about the b.L topology.
> >
> > That's virtually all of them. Everything b.L related is always
> > expressed in terms of a cpu,cluster tuple at the low level.
> >
> > > This would also imply that we treat the MPIDR just as an ID without
> > > digging into its bit layout.
> >
> > That makes for too large an index space. We always end up needing to
> > break the MPIDR into a cpu,cluster thing as the MPIDR bits are too
> > sparse.
>
> You could find a way to compress this with some mask and shifts. We can
> look at this later if we are to generalise this to non-b.L systems.
The MPIDR linearization (a simple hash to convert it to a linear index) is
planned anyway since code paths like cpu_{suspend/resume} do not work for
multi-cluster systems as things stand.
Lorenzo
^ permalink raw reply
* [PATCH 2/3] ARM: Orion: Bind the orion bridge interrupt controller through DT
From: Jason Cooper @ 2013-01-11 11:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111091349.55ee0e77@skate>
On Fri, Jan 11, 2013 at 09:13:49AM +0100, Thomas Petazzoni wrote:
> Dear Jason Gunthorpe,
>
> On Thu, 10 Jan 2013 21:02:19 -0700, Jason Gunthorpe wrote:
>
> > I've attached the main mv dt patch as a MIME, sorry for the
> > awkwardness, I am travelling and won't be available... Please feel
> > free to re-post/alter as necessary. As I said before, I'm not happy
> > with it because it doesn't follow the standard convention for MDIO
> > phys.
>
> The MDIO registers for the mv643xx_eth hardware are the same as the
> ones for the mvneta hardware. Therefore, I've splitted this into the
> mvmdio driver (available in mainline since 3.8,
> drivers/net/ethernet/marvell). This allows to have a nicely separated
> driver for the MDIO interface.
>
> My plan was ultimately to modify the mv643xx_eth driver to use the
> mvmdio driver, and then do a nice DT binding on top of that.
>
> Does this sounds like a good plan?
I like it. If you haven't already, please review the thread at
http://www.spinics.net/lists/arm-kernel/msg186742.html
to see some of the concerns already raised.
thx,
Jason.
^ permalink raw reply
* [v2 3/9] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU
From: Hiroshi Doyu @ 2013-01-11 11:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111101134.GC30538@e102568-lin.cambridge.arm.com>
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote @ Fri, 11 Jan 2013 11:11:34 +0100:
> On Thu, Jan 10, 2013 at 04:54:13PM +0000, Stephen Warren wrote:
> > On 01/10/2013 05:58 AM, Hiroshi Doyu wrote:
> > > Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote @ Wed, 9 Jan 2013 16:17:00 +0100:
> > ...
> > > With your "[PATCH] ARM: kernel: DT cpu map validity check helper
> > > function", my original patch gets as below. I think that the following
> > > "smp_detect_ncores()" function may be so generic that it could be
> > > moved in some common place than platform?
> > >
> > > From f5f2a43952ce75fe061b3808b994c3ceb07f1af1 Mon Sep 17 00:00:00 2001
> > > From: Hiroshi Doyu <hdoyu@nvidia.com>
> > > Date: Mon, 26 Nov 2012 12:25:14 +0200
> > > Subject: [PATCH 1/1] ARM: tegra: # of CPU cores detection w/ & w/o
> > > HAVE_ARM_SCU
> > >
> > > The method to detect the number of CPU cores on Cortex-A9 MPCore and
> > > Cortex-A15 MPCore is different. On Cortex-A9 MPCore we can get this
> > > information from the Snoop Control Unit(SCU). On Cortex-A15 MPCore we
> > > have to read it from the system coprocessor(CP15), because the SCU on
> > > Cortex-A15 MPCore does not have software readable registers. This
> > > patch selects the correct method at runtime based on the CPU ID.
> >
> > > diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
> >
> > > +static int __init smp_detect_ncores(void)
> > > +{
> > > + unsigned int ncores, mpidr;
> > > + u32 l2ctlr;
> > > + phys_addr_t pa;
> > > +
> > > + mpidr = read_cpuid_mpidr();
> > > + switch (mpidr) {
> > > + case ARM_CPU_PART_CORTEX_A15:
> > > + asm("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
> > > + ncores = ((l2ctlr >> 24) & 3) + 1;
> > > + break;
> > > + case ARM_CPU_PART_CORTEX_A9:
> > > + /* Get SCU physical base */
> > > + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa));
> > > + scu_base = IO_ADDRESS(pa);
> > > + ncores = scu_get_core_count(scu_base);
> > > + break;
> > > + default:
> > > + pr_warn("Unsupported mpidr\n");
> > > + ncores = 1;
> > > + break;
> > > + }
> > > +
> > > + return ncores;
> > > +}
> >
> > Why not just remove that function...
> >
> > > /*
> > > * Initialise the CPU possible map early - this describes the CPUs
> > > * which may be present or become present in the system.
> > > */
> > > static void __init tegra_smp_init_cpus(void)
> > > {
> > > - unsigned int i, ncores = scu_get_core_count(scu_base);
> > > -
> > > - if (ncores > nr_cpu_ids) {
> > > - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
> > > - ncores, nr_cpu_ids);
> > > - ncores = nr_cpu_ids;
> > > + if (!arm_dt_cpu_map_valid()) {
> > > + unsigned int i, ncores;
> > > +
> > > + ncores = smp_detect_ncores();
> >
> > And just say "ncores = 1" here?
> >
> > For Tegra, it's trivial to simply put the patch adding the required DT
> > nodes before this patch, and then there's no need for any
> > backwards-compatibility, since the nodes are guaranteed to be there.
>
> If you are willing to accept that your code proposal is perfectly fine by me.
That's simple. I'll send ones to add cpu nodes, and then this without detection.
^ permalink raw reply
* Question:add Iirq mask method in irq disable call.
From: steve.zhan @ 2013-01-11 11:52 UTC (permalink / raw)
To: linux-arm-kernel
Resend Email because MUTT email send error.
2013/1/11 Steve zhan <zhanzhenbo@gmail.com>:
> All:
> I have find that arm gic driver have not register irq_disable
> method, as below:
> static struct irq_chip gic_chip = {
> .name = "GIC",
> .irq_mask = gic_mask_irq,
> .irq_unmask = gic_unmask_irq,
> .irq_eoi = gic_eoi_irq,
> .irq_set_type = gic_set_type,
> .irq_retrigger = gic_retrigger,
> #ifdef CONFIG_SMP
> .irq_set_affinity = gic_set_affinity,
> #endif
> .irq_set_wake = gic_set_wake,
> };
>
> Question is:
> When some drivers want to disable irq, maybe it will call
> linux standard inerface: irq_disable() that defined in include\
> linux\interrupt.h, this function will call
> void irq_disable(struct irq_desc *desc)
> {
> irq_state_set_disabled(desc);
> if (desc->irq_data.chip->irq_disable) {
> desc->irq_data.chip->irq_disable(&desc->irq_data);
> irq_state_set_masked(desc);
> }
> }
>
> Because gic have not register irq_diable method, so the interrupt can
> not disable immediately, it is enable until the interrupt come next time,
> then disalbed by mask because irq_state_set_disable(desc);
>
> I have checked irq_enable method:
> void irq_enable(struct irq_desc *desc)
> {
> irq_state_clr_disabled(desc);
> if (desc->irq_data.chip->irq_enable)
> desc->irq_data.chip->irq_enable(&desc->irq_data);
> else
> desc->irq_data.chip->irq_unmask(&desc->irq_data);
> irq_state_clr_masked(desc);
> }
> This method have do unmask when irq_enable method is not exist.
>
> Is it a good idea to add irq_mask call in irq_disable()?
>
>
> Regards,
> Steve
>
--
Steve Zhan
^ permalink raw reply
* [PATCH v4 2/9] clk: tegra: Add tegra specific clocks
From: Hiroshi Doyu @ 2013-01-11 11:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357890387-23245-3-git-send-email-pgaikwad@nvidia.com>
Hi Prahant,
Some nit-pick/cosmetic comments inlined...
Prashant Gaikwad <pgaikwad@nvidia.com> wrote @ Fri, 11 Jan 2013 08:46:20 +0100:
> Add tegra specific clocks, pll, pll_out, peripheral,
> frac_divider, super.
>
> Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
> ---
> drivers/clk/Makefile | 1 +
> drivers/clk/tegra/Makefile | 8 +
> drivers/clk/tegra/clk-audio-sync.c | 89 +++++
> drivers/clk/tegra/clk-divider.c | 188 ++++++++++
> drivers/clk/tegra/clk-periph-gate.c | 182 ++++++++++
> drivers/clk/tegra/clk-periph.c | 190 ++++++++++
> drivers/clk/tegra/clk-pll-out.c | 124 +++++++
> drivers/clk/tegra/clk-pll.c | 676 +++++++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk-super.c | 154 ++++++++
> drivers/clk/tegra/clk.c | 69 ++++
> drivers/clk/tegra/clk.h | 476 ++++++++++++++++++++++++
> 11 files changed, 2157 insertions(+), 0 deletions(-)
> create mode 100644 drivers/clk/tegra/Makefile
> create mode 100644 drivers/clk/tegra/clk-audio-sync.c
> create mode 100644 drivers/clk/tegra/clk-divider.c
> create mode 100644 drivers/clk/tegra/clk-periph-gate.c
> create mode 100644 drivers/clk/tegra/clk-periph.c
> create mode 100644 drivers/clk/tegra/clk-pll-out.c
> create mode 100644 drivers/clk/tegra/clk-pll.c
> create mode 100644 drivers/clk/tegra/clk-super.c
> create mode 100644 drivers/clk/tegra/clk.c
> create mode 100644 drivers/clk/tegra/clk.h
>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index ee90e87..f0b269a 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_U8500) += ux500/
> obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
> obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o
> obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
> +obj-$(CONFIG_ARCH_TEGRA) += tegra/
>
> # Chip specific
> obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
> diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
> new file mode 100644
> index 0000000..68bd353
> --- /dev/null
> +++ b/drivers/clk/tegra/Makefile
> @@ -0,0 +1,8 @@
> +obj-y += clk.o
> +obj-y += clk-audio-sync.o
> +obj-y += clk-divider.o
> +obj-y += clk-periph.o
> +obj-y += clk-periph-gate.o
> +obj-y += clk-pll.o
> +obj-y += clk-pll-out.o
> +obj-y += clk-super.o
> diff --git a/drivers/clk/tegra/clk-audio-sync.c b/drivers/clk/tegra/clk-audio-sync.c
> new file mode 100644
> index 0000000..bb2fe43
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-audio-sync.c
> @@ -0,0 +1,89 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +
> +#include "clk.h"
> +
> +#define to_clk_sync_source(_hw) \
> + container_of(_hw, struct tegra_clk_sync_source, hw)
> +
> +static unsigned long clk_sync_source_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
> +
> + return sync->rate;
> +}
> +
> +static long clk_sync_source_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> + struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
> +
> + if (rate > sync->max_rate)
> + return -EINVAL;
> + else
> + return rate;
> +}
> +
> +static int clk_sync_source_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
> +
> + sync->rate = rate;
> + return 0;
> +}
> +
> +const struct clk_ops tegra_clk_sync_source_ops = {
> + .round_rate = clk_sync_source_round_rate,
> + .set_rate = clk_sync_source_set_rate,
> + .recalc_rate = clk_sync_source_recalc_rate,
> +};
> +
> +struct clk *tegra_clk_sync_source(const char *name, unsigned long rate,
> + unsigned long max_rate)
> +{
> + struct tegra_clk_sync_source *sync;
> + struct clk_init_data init;
> + struct clk *clk;
> +
> + sync = kzalloc(sizeof(struct tegra_clk_sync_source), GFP_KERNEL);
> + if (!sync) {
> + pr_err("%s: could not allocate sync source clk\n", __func__);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + sync->rate = rate;
> + sync->max_rate = max_rate;
> +
> + init.ops = &tegra_clk_sync_source_ops;
> + init.name = name;
> + init.flags = CLK_IS_ROOT;
> + init.parent_names = NULL;
> + init.num_parents = 0;
> +
> + sync->hw.init = &init;
> +
> + clk = clk_register(NULL, &sync->hw);
The above usage of "init" from stack may be a bit
unfamilier. I can guess that its content is copied in clk_register()
but it's originally defined in stack. So I just prefer to writing this
as below. It may be somewhat explict that we know init is from stack.
struct clk *tegra_clk_sync_source(const char *name, unsigned long rate,
unsigned long max_rate)
{
struct tegra_clk_sync_source *sync;
struct clk_init_data init = {
.ops = &tegra_clk_sync_source_ops;
.name = name;
.flags = CLK_IS_ROOT;
.parent_names = NULL;
.num_parents = 0;
};
struct clk *clk;
sync = kzalloc(sizeof(*sync), GFP_KERNEL);
if (!sync) {
pr_err("%s: could not allocate sync source clk\n", __func__);
return ERR_PTR(-ENOMEM);
}
sync->rate = rate;
sync->max_rate = max_rate;
sync->hw.init = &init;
clk = clk_register(NULL, &sync->hw);
Maybe other init as well?
> + if (IS_ERR(clk))
> + kfree(sync);
> +
> + return clk;
> +}
> diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
> new file mode 100644
> index 0000000..fcd0123
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-divider.c
> @@ -0,0 +1,188 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/slab.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +
> +#include "clk.h"
> +
> +#define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
> +
> +#define pll_out_override(p) (BIT((p->shift - 6)))
> +#define div_mask(d) ((1 << (d->width)) - 1)
> +#define get_mul(d) (1 << d->frac_width)
> +#define get_max_div(d) div_mask(d)
> +
> +#define PERIPH_CLK_UART_DIV_ENB BIT(24)
> +
> +static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + s64 divider_ux1 = parent_rate;
> + u8 flags = divider->flags;
> + int mul;
> +
> + if (!rate)
> + return 0;
> +
> + mul = get_mul(divider);
> +
> + if (!(flags & TEGRA_DIVIDER_INT))
> + divider_ux1 *= mul;
> +
> + if (flags & TEGRA_DIVIDER_ROUND_UP)
> + divider_ux1 += rate - 1;
> +
> + do_div(divider_ux1, rate);
> +
> + if (flags & TEGRA_DIVIDER_INT)
> + divider_ux1 *= mul;
> +
> + divider_ux1 -= mul;
> +
> + if (divider_ux1 < 0)
> + return 0;
> +
> + if (divider_ux1 > get_max_div(divider))
> + return -EINVAL;
> +
> + return divider_ux1;
> +}
> +
> +static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
> + u32 reg;
> + int div, mul;
> + u64 rate = parent_rate;
> +
> + reg = readl_relaxed(divider->reg) >> divider->shift;
> + div = reg & div_mask(divider);
> +
> + mul = get_mul(divider);
> + div += mul;
> +
> + rate *= mul;
> + rate += div - 1;
> + do_div(rate, div);
> +
> + return rate;
> +}
> +
> +static long clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> + struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
> + int div, mul;
> + unsigned long output_rate = *prate;
> +
> + if (!rate)
> + return output_rate;
> +
> + div = get_div(divider, rate, output_rate);
> + if (div < 0)
> + return *prate;
> +
> + mul = get_mul(divider);
> +
> + return DIV_ROUND_UP(output_rate * mul, div + mul);
> +}
> +
> +static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
> + int div;
> + unsigned long flags = 0;
> + u32 val;
> +
> + div = get_div(divider, rate, parent_rate);
> + if (div < 0)
> + return div;
> +
> + if (divider->lock)
> + spin_lock_irqsave(divider->lock, flags);
> +
> + val = readl_relaxed(divider->reg);
> + val &= ~(div_mask(divider) << divider->shift);
> + val |= div << divider->shift;
> +
> + if (divider->flags & TEGRA_DIVIDER_UART) {
> + if (div)
> + val |= PERIPH_CLK_UART_DIV_ENB;
> + else
> + val &= ~PERIPH_CLK_UART_DIV_ENB;
> + }
> +
> + if (divider->flags & TEGRA_DIVIDER_FIXED)
> + val |= pll_out_override(divider);
> +
> + writel_relaxed(val, divider->reg);
> +
> + if (divider->lock)
> + spin_unlock_irqrestore(divider->lock, flags);
> +
> + return 0;
> +}
> +
> +const struct clk_ops tegra_clk_frac_div_ops = {
> + .recalc_rate = clk_frac_div_recalc_rate,
> + .set_rate = clk_frac_div_set_rate,
> + .round_rate = clk_frac_div_round_rate,
> +};
> +
> +struct clk *tegra_clk_divider(const char *name, const char *parent_name,
> + void __iomem *reg, unsigned long flags,
> + u8 clk_divider_flags, u8 shift, u8 width,
> + u8 frac_width, spinlock_t *lock)
> +{
> + struct tegra_clk_frac_div *divider;
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + divider = kzalloc(sizeof(struct tegra_clk_frac_div), GFP_KERNEL);
divider = kzalloc(sizeof(*divider), GFP_KERNEL);
Maybe other *alloc() as well?
> + if (!divider) {
> + pr_err("%s: could not allocate fractional divider clk\n",
> + __func__);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + init.name = name;
> + init.ops = &tegra_clk_frac_div_ops;
> + init.flags = flags;
> + init.parent_names = parent_name ? &parent_name : NULL;
> + init.num_parents = parent_name ? 1 : 0;
> +
> + divider->reg = reg;
> + divider->shift = shift;
> + divider->width = width;
> + divider->frac_width = frac_width;
> + divider->lock = lock;
> + divider->flags = clk_divider_flags;
> +
> + divider->hw.init = &init;
> +
> + clk = clk_register(NULL, ÷r->hw);
> + if (IS_ERR(clk))
> + kfree(divider);
> +
> + return clk;
> +}
> diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
> new file mode 100644
> index 0000000..5f0919d
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-periph-gate.c
> @@ -0,0 +1,182 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/tegra-soc.h>
> +
> +#include "clk.h"
> +
> +static DEFINE_SPINLOCK(periph_ref_lock);
> +
> +#define to_clk_periph_gate(_hw) \
> + container_of(_hw, struct tegra_clk_periph_gate, hw)
> +
> +/* Macros to assist peripheral gate clock */
> +#define read_enb(gate) \
> + readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
> +#define write_enb_set(val, gate) \
> + writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
> +#define write_enb_clr(val, gate) \
> + writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
> +
> +#define read_rst(gate) \
> + readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
> +#define write_rst_set(val, gate) \
> + writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
> +#define write_rst_clr(val, gate) \
> + writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
> +
> +#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
> +
> +/* Peripheral gate clock ops */
> +static int clk_periph_is_enabled(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
> + int state = 1;
> +
> + if (!(read_enb(gate) & periph_clk_to_bit(gate)))
> + state = 0;
> +
> + if (!(gate->flags & TEGRA_PERIPH_NO_RESET))
> + if (read_rst(gate) & periph_clk_to_bit(gate))
> + state = 0;
> +
> + return state;
> +}
> +
> +static int clk_periph_enable(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
> + unsigned long flags = 0;
> +
> + spin_lock_irqsave(&periph_ref_lock, flags);
> +
> + gate->enable_refcnt[gate->clk_num]++;
> + if (gate->enable_refcnt[gate->clk_num] > 1) {
> + spin_unlock_irqrestore(&periph_ref_lock, flags);
> + return 0;
> + }
> +
> + write_enb_set(periph_clk_to_bit(gate), gate);
> + udelay(2);
> +
> + if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
> + !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
> + if (read_rst(gate) & periph_clk_to_bit(gate)) {
> + udelay(5); /* reset propogation delay */
> + write_rst_clr(periph_clk_to_bit(gate), gate);
> + }
> + }
> +
> + spin_unlock_irqrestore(&periph_ref_lock, flags);
> +
> + return 0;
> +}
> +
> +static void clk_periph_disable(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
> + unsigned long flags = 0;
> +
> + spin_lock_irqsave(&periph_ref_lock, flags);
> +
> + gate->enable_refcnt[gate->clk_num]--;
> + if (gate->enable_refcnt[gate->clk_num] > 0) {
> + spin_unlock_irqrestore(&periph_ref_lock, flags);
> + return;
> + }
> +
> + /*
> + * If peripheral is in the APB bus then read the APB bus to
> + * flush the write operation in apb bus. This will avoid the
> + * peripheral access after disabling clock
> + */
> + if (gate->flags & TEGRA_PERIPH_ON_APB)
> + tegra_read_chipid();
> +
> + write_enb_clr(periph_clk_to_bit(gate), gate);
> +
> + spin_unlock_irqrestore(&periph_ref_lock, flags);
> +}
> +
> +void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert)
> +{
> + if (gate->flags & TEGRA_PERIPH_NO_RESET)
> + return;
> +
> + if (assert) {
> + /*
> + * If peripheral is in the APB bus then read the APB bus to
> + * flush the write operation in apb bus. This will avoid the
> + * peripheral access after disabling clock
> + */
> + if (gate->flags & TEGRA_PERIPH_ON_APB)
> + tegra_read_chipid();
> +
> + write_rst_set(periph_clk_to_bit(gate), gate);
> + } else {
> + write_rst_clr(periph_clk_to_bit(gate), gate);
> + }
> +}
> +
> +const struct clk_ops tegra_clk_periph_gate_ops = {
> + .is_enabled = clk_periph_is_enabled,
> + .enable = clk_periph_enable,
> + .disable = clk_periph_disable,
> +};
> +
> +struct clk *tegra_clk_periph_gate(const char *name, const char *parent_name,
> + u8 gate_flags, void __iomem *clk_base,
> + unsigned long flags, int clk_num,
> + struct tegra_clk_periph_regs *pregs,
> + int *enable_refcnt)
> +{
> + struct tegra_clk_periph_gate *gate;
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + gate = kzalloc(sizeof(struct tegra_clk_periph_gate), GFP_KERNEL);
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> + if (!gate) {
> + pr_err("%s: could not allocate periph gate clk\n", __func__);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + init.name = name;
> + init.flags = flags;
> + init.parent_names = parent_name ? &parent_name : NULL;
> + init.num_parents = parent_name ? 1 : 0;
> + init.ops = &tegra_clk_periph_gate_ops;
> +
> + gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;
> + gate->clk_base = clk_base;
> + gate->clk_num = clk_num;
> + gate->flags = gate_flags;
> + gate->enable_refcnt = enable_refcnt;
> + gate->regs = pregs;
> +
> + gate->hw.init = &init;
> +
> + clk = clk_register(NULL, &gate->hw);
> + if (IS_ERR(clk))
> + kfree(gate);
> +
> + return clk;
> +}
> diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
> new file mode 100644
> index 0000000..ed0ded2
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-periph.c
> @@ -0,0 +1,190 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +
> +#include "clk.h"
> +
> +#define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
> +
> +static u8 clk_periph_get_parent(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph *periph = to_clk_periph(hw);
> + const struct clk_ops *mux_ops = periph->mux_ops;
> + struct clk_hw *mux_hw = &periph->mux.hw;
> +
> + mux_hw->clk = hw->clk;
> +
> + return mux_ops->get_parent(mux_hw);
> +}
> +
> +static int clk_periph_set_parent(struct clk_hw *hw, u8 index)
> +{
> + struct tegra_clk_periph *periph = to_clk_periph(hw);
> + const struct clk_ops *mux_ops = periph->mux_ops;
> + struct clk_hw *mux_hw = &periph->mux.hw;
> +
> + mux_hw->clk = hw->clk;
> +
> + return mux_ops->set_parent(mux_hw, index);
> +}
> +
> +static unsigned long clk_periph_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct tegra_clk_periph *periph = to_clk_periph(hw);
> + const struct clk_ops *div_ops = periph->div_ops;
> + struct clk_hw *div_hw = &periph->divider.hw;
> +
> + div_hw->clk = hw->clk;
> +
> + return div_ops->recalc_rate(div_hw, parent_rate);
> +}
> +
> +static long clk_periph_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> + struct tegra_clk_periph *periph = to_clk_periph(hw);
> + const struct clk_ops *div_ops = periph->div_ops;
> + struct clk_hw *div_hw = &periph->divider.hw;
> +
> + div_hw->clk = hw->clk;
> +
> + return div_ops->round_rate(div_hw, rate, prate);
> +}
> +
> +static int clk_periph_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct tegra_clk_periph *periph = to_clk_periph(hw);
> + const struct clk_ops *div_ops = periph->div_ops;
> + struct clk_hw *div_hw = &periph->divider.hw;
> +
> + div_hw->clk = hw->clk;
> +
> + return div_ops->set_rate(div_hw, rate, parent_rate);
> +}
> +
> +static int clk_periph_is_enabled(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph *periph = to_clk_periph(hw);
> + const struct clk_ops *gate_ops = periph->gate_ops;
> + struct clk_hw *gate_hw = &periph->gate.hw;
> +
> + gate_hw->clk = hw->clk;
> +
> + return gate_ops->is_enabled(gate_hw);
> +}
> +
> +static int clk_periph_enable(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph *periph = to_clk_periph(hw);
> + const struct clk_ops *gate_ops = periph->gate_ops;
> + struct clk_hw *gate_hw = &periph->gate.hw;
> +
> + gate_hw->clk = hw->clk;
> +
> + return gate_ops->enable(gate_hw);
> +}
> +
> +static void clk_periph_disable(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph *periph = to_clk_periph(hw);
> + const struct clk_ops *gate_ops = periph->gate_ops;
> + struct clk_hw *gate_hw = &periph->gate.hw;
> +
> + gate_ops->disable(gate_hw);
> +}
> +
> +const struct clk_ops tegra_clk_periph_ops = {
> + .get_parent = clk_periph_get_parent,
> + .set_parent = clk_periph_set_parent,
> + .recalc_rate = clk_periph_recalc_rate,
> + .round_rate = clk_periph_round_rate,
> + .set_rate = clk_periph_set_rate,
> + .is_enabled = clk_periph_is_enabled,
> + .enable = clk_periph_enable,
> + .disable = clk_periph_disable,
> +};
> +
> +const struct clk_ops tegra_clk_periph_nodiv_ops = {
> + .get_parent = clk_periph_get_parent,
> + .set_parent = clk_periph_set_parent,
> + .is_enabled = clk_periph_is_enabled,
> + .enable = clk_periph_enable,
> + .disable = clk_periph_disable,
> +};
> +
> +struct clk *tegra_clk_periph(const char *name, const char **parent_names,
> + int num_parents, struct tegra_clk_periph *periph,
> + void __iomem *clk_base, u32 offset)
> +{
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + init.name = name;
> + init.ops = &tegra_clk_periph_ops;
> + init.flags = 0;
> + init.parent_names = parent_names;
> + init.num_parents = num_parents;
> +
> + periph->hw.init = &init;
> + periph->magic = TEGRA_CLK_PERIPH_MAGIC;
> + periph->mux.reg = clk_base + offset;
> + periph->divider.reg = clk_base + offset;
> + periph->gate.clk_base = clk_base;
> +
> + clk = clk_register(NULL, &periph->hw);
> + if (IS_ERR(clk))
> + return clk;
> +
> + periph->mux.hw.clk = clk;
> + periph->divider.hw.clk = clk;
> + periph->gate.hw.clk = clk;
> +
> + return clk;
> +}
> +
> +struct clk *tegra_clk_periph_nodiv(const char *name, const char **parent_names,
> + int num_parents, struct tegra_clk_periph *periph,
> + void __iomem *clk_base, u32 offset)
> +{
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + init.name = name;
> + init.ops = &tegra_clk_periph_nodiv_ops;
> + init.flags = CLK_SET_RATE_PARENT;
> + init.parent_names = parent_names;
> + init.num_parents = num_parents;
> +
> + periph->hw.init = &init;
> + periph->magic = TEGRA_CLK_PERIPH_MAGIC;
> + periph->mux.reg = clk_base + offset;
> + periph->gate.clk_base = clk_base;
> +
> + clk = clk_register(NULL, &periph->hw);
> + if (IS_ERR(clk))
> + return clk;
> +
> + periph->mux.hw.clk = clk;
> + periph->gate.hw.clk = clk;
> +
> + return clk;
> +}
> diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c
> new file mode 100644
> index 0000000..60a117b
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-pll-out.c
> @@ -0,0 +1,124 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/delay.h>
> +#include <linux/slab.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +
> +#include "clk.h"
> +
> +#define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
> +
> +#define pll_out_enb(p) (BIT(p->enb_bit_idx))
> +#define pll_out_rst(p) (BIT(p->rst_bit_idx))
> +
> +static int clk_pll_out_is_enabled(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
> + u32 val = readl_relaxed(pll_out->reg);
> + int state;
> +
> + state = (val & pll_out_enb(pll_out)) ? 1 : 0;
> + if (!(val & (pll_out_rst(pll_out))))
> + state = 0;
> + return state;
> +}
> +
> +static int clk_pll_out_enable(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
> + unsigned long flags = 0;
> + u32 val;
> +
> + if (pll_out->lock)
> + spin_lock_irqsave(pll_out->lock, flags);
> +
> + val = readl_relaxed(pll_out->reg);
> +
> + val |= (pll_out_enb(pll_out) | pll_out_rst(pll_out));
> +
> + writel_relaxed(val, pll_out->reg);
> + udelay(2);
> +
> + if (pll_out->lock)
> + spin_unlock_irqrestore(pll_out->lock, flags);
> +
> + return 0;
> +}
> +
> +static void clk_pll_out_disable(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
> + unsigned long flags = 0;
> + u32 val;
> +
> + if (pll_out->lock)
> + spin_lock_irqsave(pll_out->lock, flags);
> +
> + val = readl_relaxed(pll_out->reg);
> +
> + val &= ~(pll_out_enb(pll_out) | pll_out_rst(pll_out));
> +
> + writel_relaxed(val, pll_out->reg);
> + udelay(2);
> +
> + if (pll_out->lock)
> + spin_unlock_irqrestore(pll_out->lock, flags);
> +}
> +
> +const struct clk_ops tegra_clk_pll_out_ops = {
> + .is_enabled = clk_pll_out_is_enabled,
> + .enable = clk_pll_out_enable,
> + .disable = clk_pll_out_disable,
> +};
> +
> +struct clk *tegra_clk_pll_out(const char *name, const char *parent_name,
> + void __iomem *reg, u8 enb_bit_idx, u8 rst_bit_idx,
> + unsigned long flags, u8 pll_out_flags,
> + spinlock_t *lock)
> +{
> + struct tegra_clk_pll_out *pll_out;
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + pll_out = kzalloc(sizeof(struct tegra_clk_pll_out), GFP_KERNEL);
> + if (!pll_out)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = name;
> + init.ops = &tegra_clk_pll_out_ops;
> + init.parent_names = (parent_name ? &parent_name : NULL);
> + init.num_parents = (parent_name ? 1 : 0);
> + init.flags = flags;
> +
> + pll_out->reg = reg;
> + pll_out->enb_bit_idx = enb_bit_idx;
> + pll_out->rst_bit_idx = rst_bit_idx;
> + pll_out->flags = pll_out_flags;
> + pll_out->lock = lock;
> +
> + pll_out->hw.init = &init;
> +
> + clk = clk_register(NULL, &pll_out->hw);
> + if (IS_ERR(clk))
> + kfree(pll_out);
> +
> + return clk;
> +}
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> new file mode 100644
> index 0000000..f8dc7c0
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -0,0 +1,676 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +
> +#include "clk.h"
> +
> +#define PLL_BASE_BYPASS BIT(31)
> +#define PLL_BASE_ENABLE BIT(30)
> +#define PLL_BASE_REF_ENABLE BIT(29)
> +#define PLL_BASE_OVERRIDE BIT(28)
> +
> +#define PLL_BASE_DIVP_SHIFT 20
> +#define PLL_BASE_DIVP_WIDTH 3
> +#define PLL_BASE_DIVN_SHIFT 8
> +#define PLL_BASE_DIVN_WIDTH 10
> +#define PLL_BASE_DIVM_SHIFT 0
> +#define PLL_BASE_DIVM_WIDTH 5
> +#define PLLU_POST_DIVP_MASK 0x1
> +
> +#define PLL_MISC_DCCON_SHIFT 20
> +#define PLL_MISC_CPCON_SHIFT 8
> +#define PLL_MISC_CPCON_WIDTH 4
> +#define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
> +#define PLL_MISC_LFCON_SHIFT 4
> +#define PLL_MISC_LFCON_WIDTH 4
> +#define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
> +#define PLL_MISC_VCOCON_SHIFT 0
> +#define PLL_MISC_VCOCON_WIDTH 4
> +#define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
> +
> +#define OUT_OF_TABLE_CPCON 8
> +
> +#define PMC_PLLP_WB0_OVERRIDE 0xf8
> +#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
> +#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
> +
> +#define PLL_POST_LOCK_DELAY 50
> +
> +#define PLLDU_LFCON_SET_DIVN 600
> +
> +#define PLLE_BASE_DIVCML_SHIFT 24
> +#define PLLE_BASE_DIVCML_WIDTH 4
> +#define PLLE_BASE_DIVP_SHIFT 16
> +#define PLLE_BASE_DIVP_WIDTH 7
> +#define PLLE_BASE_DIVN_SHIFT 8
> +#define PLLE_BASE_DIVN_WIDTH 8
> +#define PLLE_BASE_DIVM_SHIFT 0
> +#define PLLE_BASE_DIVM_WIDTH 8
> +
> +#define PLLE_MISC_SETUP_BASE_SHIFT 16
> +#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
> +#define PLLE_MISC_LOCK_ENABLE BIT(9)
> +#define PLLE_MISC_READY BIT(15)
> +#define PLLE_MISC_SETUP_EX_SHIFT 2
> +#define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
> +#define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
> + PLLE_MISC_SETUP_EX_MASK)
> +#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
> +
> +#define PLLE_SS_CTRL 0x68
> +#define PLLE_SS_DISABLE (7 << 10)
> +
> +#define PMC_SATA_PWRGT 0x1ac
> +#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
> +#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
> +
> +#define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
> +
> +#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
> +#define pll_readl_base(p) pll_readl(p->params->base_reg, p)
> +#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
> +
> +#define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
> +#define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
> +#define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
> +
> +#define mask(w) ((1 << (w)) - 1)
> +#define divm_mask(p) mask(p->divm_width)
> +#define divn_mask(p) mask(p->divn_width)
> +#define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK : \
> + mask(p->divp_width))
> +
> +#define divm_max(p) (divm_mask(p))
> +#define divn_max(p) (divn_mask(p))
> +#define divp_max(p) (1 << (divp_mask(p)))
> +
> +static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
> +{
> + u32 val;
> +
> + if (!(pll->flags & TEGRA_PLL_USE_LOCK))
> + return;
> +
> + val = pll_readl_misc(pll);
> + val |= BIT(pll->params->lock_enable_bit_idx);
> + pll_writel_misc(val, pll);
> +}
> +
> +static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
> + void __iomem *lock_addr, u32 lock_bit_idx)
> +{
> + int i;
> + u32 val;
> +
> + if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
> + udelay(pll->params->lock_delay);
> + return 0;
> + }
> +
> + for (i = 0; i < pll->params->lock_delay; i++) {
> + val = readl_relaxed(lock_addr);
> + if (val & BIT(lock_bit_idx)) {
> + udelay(PLL_POST_LOCK_DELAY);
> + return 0;
> + }
> + udelay(2); /* timeout = 2 * lock time */
> + }
> +
> + pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
> + __clk_get_name(pll->hw.clk));
> +
> + return -1;
> +}
> +
> +static int clk_pll_is_enabled(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + u32 val;
> +
> + if (pll->flags & TEGRA_PLLM) {
> + val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
> + if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
> + return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
> + }
> +
> + val = pll_readl_base(pll);
> +
> + return val & PLL_BASE_ENABLE ? 1 : 0;
> +}
> +
> +static int _clk_pll_enable(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + u32 val;
> +
> + clk_pll_enable_lock(pll);
> +
> + val = pll_readl_base(pll);
> + val &= ~PLL_BASE_BYPASS;
> + val |= PLL_BASE_ENABLE;
> + pll_writel_base(val, pll);
> +
> + if (pll->flags & TEGRA_PLLM) {
> + val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
> + val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
> + writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
> + }
> +
> + clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->base_reg,
> + pll->params->lock_bit_idx);
> +
> + return 0;
> +}
> +
> +static void _clk_pll_disable(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + u32 val;
> +
> + val = pll_readl_base(pll);
> + val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
> + pll_writel_base(val, pll);
> +
> + if (pll->flags & TEGRA_PLLM) {
> + val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
> + val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
> + writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
> + }
> +}
> +
> +static int clk_pll_enable(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + unsigned long flags = 0;
> + int ret;
> +
> + if (pll->lock)
> + spin_lock_irqsave(pll->lock, flags);
> +
> + ret = _clk_pll_enable(hw);
> +
> + if (pll->lock)
> + spin_unlock_irqrestore(pll->lock, flags);
> +
> + return ret;
> +}
> +
> +static void clk_pll_disable(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + unsigned long flags = 0;
> +
> + if (pll->lock)
> + spin_lock_irqsave(pll->lock, flags);
> +
> + _clk_pll_disable(hw);
> +
> + if (pll->lock)
> + spin_unlock_irqrestore(pll->lock, flags);
> +}
> +
> +static int _get_table_rate(struct clk_hw *hw,
> + struct tegra_clk_pll_freq_table *cfg,
> + unsigned long rate, unsigned long parent_rate)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + struct tegra_clk_pll_freq_table *sel;
> +
> + for (sel = pll->freq_table; sel->input_rate != 0; sel++)
> + if (sel->input_rate == parent_rate &&
> + sel->output_rate == rate)
> + break;
> +
> + if (sel->input_rate == 0)
> + return -EINVAL;
> +
> + BUG_ON(sel->p < 1);
> +
> + cfg->input_rate = sel->input_rate;
> + cfg->output_rate = sel->output_rate;
> + cfg->m = sel->m;
> + cfg->n = sel->n;
> + cfg->p = sel->p;
> + cfg->cpcon = sel->cpcon;
> +
> + return 0;
> +}
> +
> +static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
> + unsigned long rate, unsigned long parent_rate)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + unsigned long cfreq;
> + u32 p_div = 0;
> +
> + switch (parent_rate) {
> + case 12000000:
> + case 26000000:
> + cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
> + break;
> + case 13000000:
> + cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
> + break;
> + case 16800000:
> + case 19200000:
> + cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
> + break;
> + case 9600000:
> + case 28800000:
> + /*
> + * PLL_P_OUT1 rate is not listed in PLLA table
> + */
> + cfreq = parent_rate/(parent_rate/1000000);
> + break;
> + default:
> + pr_err("%s Unexpected reference rate %lu\n",
> + __func__, parent_rate);
> + BUG();
> + }
> +
> + /* Raise VCO to guarantee 0.5% accuracy */
> + for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
> + cfg->output_rate <<= 1)
> + p_div++;
> +
> + cfg->p = 1 << p_div;
> + cfg->m = parent_rate / cfreq;
> + cfg->n = cfg->output_rate / cfreq;
> + cfg->cpcon = OUT_OF_TABLE_CPCON;
> +
> + if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
> + cfg->p > divp_max(pll) || cfg->output_rate > pll->params->vco_max) {
> + pr_err("%s: Failed to set %s rate %lu\n",
> + __func__, __clk_get_name(hw->clk), rate);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
> + unsigned long rate)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + unsigned long flags = 0;
> + u32 divp, val, old_base;
> + int state;
> +
> + divp = __ffs(cfg->p);
> +
> + if (pll->flags & TEGRA_PLLU)
> + divp ^= 1;
> +
> + if (pll->lock)
> + spin_lock_irqsave(pll->lock, flags);
> +
> + old_base = val = pll_readl_base(pll);
> + val &= ~((divm_mask(pll) << pll->divm_shift) |
> + (divn_mask(pll) << pll->divn_shift) |
> + (divp_mask(pll) << pll->divp_shift));
> + val |= ((cfg->m << pll->divm_shift) |
> + (cfg->n << pll->divn_shift) |
> + (divp << pll->divp_shift));
> + if (val == old_base) {
> + if (pll->lock)
> + spin_unlock_irqrestore(pll->lock, flags);
> + return 0;
> + }
> +
> + state = clk_pll_is_enabled(hw);
> +
> + if (state) {
> + if (pll->lock)
> + spin_unlock_irqrestore(pll->lock, flags);
> +
> + clk_pll_disable(hw);
> + val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
> +
> + if (pll->lock)
> + spin_lock_irqsave(pll->lock, flags);
> + }
> + pll_writel_base(val, pll);
> +
> + if (pll->flags & TEGRA_PLL_HAS_CPCON) {
> + val = pll_readl_misc(pll);
> + val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
> + val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
> + if (pll->flags & TEGRA_PLL_SET_LFCON) {
> + val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
> + if (cfg->n >= PLLDU_LFCON_SET_DIVN)
> + val |= 0x1 << PLL_MISC_LFCON_SHIFT;
> + } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
> + val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
> + if (rate >= (pll->params->vco_max >> 1))
> + val |= 0x1 << PLL_MISC_DCCON_SHIFT;
> + }
> + pll_writel_misc(val, pll);
> + }
> +
> + if (pll->lock)
> + spin_unlock_irqrestore(pll->lock, flags);
> +
> + if (state)
> + clk_pll_enable(hw);
> +
> + return 0;
> +}
> +
> +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + struct tegra_clk_pll_freq_table cfg;
> +
> + if (pll->flags & TEGRA_PLL_FIXED) {
> + if (rate != pll->fixed_rate) {
> + pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
> + __func__, __clk_get_name(hw->clk),
> + pll->fixed_rate, rate);
> + return -EINVAL;
> + }
> + return 0;
> + }
> +
> + if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
> + _calc_rate(hw, &cfg, rate, parent_rate))
> + return -EINVAL;
> +
> + return _program_pll(hw, &cfg, rate);
> +}
> +
> +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + struct tegra_clk_pll_freq_table cfg;
> + u64 output_rate = *prate;
> +
> + if (pll->flags & TEGRA_PLL_FIXED)
> + return pll->fixed_rate;
> +
> + /* PLLM is used for memory; we do not change rate */
> + if (pll->flags & TEGRA_PLLM)
> + return __clk_get_rate(hw->clk);
> +
> + if (_get_table_rate(hw, &cfg, rate, *prate) &&
> + _calc_rate(hw, &cfg, rate, *prate))
> + return -EINVAL;
> +
> + output_rate *= cfg.n;
> + do_div(output_rate, cfg.m * cfg.p);
> +
> + return output_rate;
> +}
> +
> +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + u32 val = pll_readl_base(pll);
> + u32 divn = 0, divm = 0, divp = 0;
> + u64 rate = parent_rate;
> +
> + if (val & PLL_BASE_BYPASS)
> + return parent_rate;
> +
> + if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
> + struct tegra_clk_pll_freq_table sel;
> + if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) {
> + pr_err("Clock %s has unknown fixed frequency\n",
> + __clk_get_name(hw->clk));
> + BUG();
> + }
> + return pll->fixed_rate;
> + }
> +
> + divp = (val >> pll->divp_shift) & (divp_mask(pll));
> + if (pll->flags & TEGRA_PLLU)
> + divp ^= 1;
> +
> + divn = (val >> pll->divn_shift) & (divn_mask(pll));
> + divm = (val >> pll->divm_shift) & (divm_mask(pll));
> + divm *= (1 << divp);
> +
> + rate *= divn;
> + do_div(rate, divm);
> + return rate;
> +}
> +
> +static int clk_plle_training(struct tegra_clk_pll *pll)
> +{
> + u32 val;
> + int timeout;
> +
> + if (!pll->pmc)
> + return -ENOSYS;
> +
> + /*
> + * PLLE is already disabled, and setup cleared;
> + * create falling edge on PLLE IDDQ input.
> + */
> + val = readl(pll->pmc + PMC_SATA_PWRGT);
> + val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
> + writel(val, pll->pmc + PMC_SATA_PWRGT);
> +
> + val = readl(pll->pmc + PMC_SATA_PWRGT);
> + val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
> + writel(val, pll->pmc + PMC_SATA_PWRGT);
> +
> + val = readl(pll->pmc + PMC_SATA_PWRGT);
> + val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
> + writel(val, pll->pmc + PMC_SATA_PWRGT);
> +
> + val = pll_readl_misc(pll);
> +
> + timeout = 300;
> + while (!(val & PLLE_MISC_READY)) {
> + val = pll_readl_misc(pll);
> + udelay(300);
> + if (--timeout == 0) {
> + pr_err("%s: timeout waiting for PLLE\n", __func__);
> + return -EBUSY;
> + }
> + }
Can the above be written as below?
timeout = jiffies + msecs_to_jiffies(100);
while (1) {
val = pll_readl_misc(pll);
if (val & PLLE_MISC_READY)
break;
if (time_after(jiffies, timeout)) {
pr_err("%s: timeout waiting for PLLE\n", __func__);
return -EBUSY;
}
udelay(300);
}
^ permalink raw reply
* [PATCH 01/16] ARM: b.L: secondary kernel entry code
From: Catalin Marinas @ 2013-01-11 11:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1301101132080.6300@xanadu.home>
On Thu, Jan 10, 2013 at 04:47:09PM +0000, Nicolas Pitre wrote:
> On Thu, 10 Jan 2013, Catalin Marinas wrote:
> > On 10 January 2013 00:20, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> > > --- /dev/null
> > > +++ b/arch/arm/common/bL_entry.c
> > ...
> > > +extern volatile unsigned long bL_entry_vectors[BL_NR_CLUSTERS][BL_CPUS_PER_CLUSTER];
> >
> > IMHO, we should keep this array linear and ignore the cluster grouping
> > at this stage. This information could be added to latter patches that
> > actually need to know about the b.L topology.
>
> That's virtually all of them. Everything b.L related is always
> expressed in terms of a cpu,cluster tuple at the low level.
>
> > This would also imply that we treat the MPIDR just as an ID without
> > digging into its bit layout.
>
> That makes for too large an index space. We always end up needing to
> break the MPIDR into a cpu,cluster thing as the MPIDR bits are too
> sparse.
You could find a way to compress this with some mask and shifts. We can
look at this later if we are to generalise this to non-b.L systems.
--
Catalin
^ permalink raw reply
* [PATCH v4 00/14] DMA Engine support for AM33XX
From: Arnd Bergmann @ 2013-01-11 11:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357883330-5364-1-git-send-email-mporter@ti.com>
On Friday 11 January 2013, Matt Porter wrote:
> The approach taken is similar to how OMAP DMA is being converted to
> DMA Engine support. With the functional EDMA private API already
> existing in mach-davinci/dma.c, we first move that to an ARM common
> area so it can be shared. Adding DT and runtime PM support to the
> private EDMA API implementation allows it to run on AM33xx. AM33xx
> only boots using DT so we leverage Jon's generic DT DMA helpers to
> register EDMA DMAC with the of_dma framework and then add support
> for calling the dma_request_slave_channel() API to both the mmc
> and spi drivers.
I think this looks very good. What I wonder is whether we should
make the non-DT parts of the dmaengine driver compile-time
conditional on CONFIG_ATAGS though, so the slave drivers don't
have a link-time dependency on the dmaengine driver's
omap_dma_filter_fn symbol when building without ATAGS support.
Arnd
^ permalink raw reply
* [PATCH] ARM: let CPUs not being able to run in ARM mode enter in THUMB mode
From: Uwe Kleine-König @ 2013-01-11 11:39 UTC (permalink / raw)
To: linux-arm-kernel
Some ARM cores are not capable to run in ARM mode (e.g. Cortex-M3). So
obviously these cannot enter the kernel in ARM mode. Make an exception
for them and let them enter in THUMB mode.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/kernel/head-nommu.S | 8 +++++++-
arch/arm/kernel/head.S | 8 +++++++-
arch/arm/mm/Kconfig | 6 ++++++
3 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 3782320..ae7ed46 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -32,15 +32,21 @@
* numbers for r1.
*
*/
- .arm
__HEAD
+
+#ifdef CONFIG_THUMBONLY_CPU
+ .thumb
+ENTRY(stext)
+#else
+ .arm
ENTRY(stext)
THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
THUMB( .thumb ) @ switch to Thumb now.
THUMB(1: )
+#endif
setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
@ and irqs disabled
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 4eee351..0af2749 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -73,15 +73,21 @@
* crap here - that's what the boot loader (or in extreme, well justified
* circumstances, zImage) is for.
*/
- .arm
__HEAD
+
+#ifdef CONFIG_THUMBONLY_CPU
+ .thumb
+ENTRY(stext)
+#else
+ .arm
ENTRY(stext)
THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
THUMB( .thumb ) @ switch to Thumb now.
THUMB(1: )
+#endif
#ifdef CONFIG_ARM_VIRT_EXT
bl __hyp_stub_install
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 3fd629d..bc3150c 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -1,5 +1,11 @@
comment "Processor Type"
+# Select this if your CPU doesn't support the 32 bit ARM instructions.
+config THUMBONLY_CPU
+ bool
+ select THUMB2_KERNEL
+ select ARM_THUMB
+
# Select CPU types depending on the architecture selected. This selects
# which CPUs we support in the kernel image, and the compiler instruction
# optimiser behaviour.
--
1.7.10.4
^ permalink raw reply related
* [PATCH 14/16] ARM: TC2: ensure powerdown-time data is flushed from cache
From: Dave Martin @ 2013-01-11 11:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1301101410540.6300@xanadu.home>
On Thu, Jan 10, 2013 at 02:13:09PM -0500, Nicolas Pitre wrote:
> On Thu, 10 Jan 2013, Dave Martin wrote:
>
> > On Wed, Jan 09, 2013 at 07:20:49PM -0500, Nicolas Pitre wrote:
> > > From: Dave Martin <dave.martin@linaro.org>
> >
> > To avoid confusion, the prefix in the subject line should be "CCI", not
> > "TC2".
>
> Absolutely. This is my mistake as I removed the TC2 changes from your
> original patch to only keep the CCI ones, but forgot to update the patch
> title.
Oh right. I was quite happy to believe it was my mistake :)
It makes sense to have two separate patches anyway, though.
Cheers
---Dave
^ permalink raw reply
* [PATCH] ARM: OMAP: Fix the use of uninitialized dma_lch_count
From: Santosh Shilimkar @ 2013-01-11 11:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50EFA586.5010508@asianux.com>
On Friday 11 January 2013 11:09 AM, Chen Gang wrote:
>
> 'omap_dma_reserve_channels' when used is suppose to be from command.
> so, it alreay has value before 1st call of omap_system_dma_probe.
> and it will never be changed again during running (not from ioctl).
>
> but 'dma_lch_count' is zero before 1st call of omap_system_dma_probe.
> so it will be failed for omap_dma_reserve_channels, when 1st call.
>
> so, need use 'd->lch_count' instead of 'dma_lch_count' for judging.
>
> Signed-off-by: Chen Gang <gang.chen@asianux.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
Looks fine to me.
Tony,
If you are ok with the patch, can you pick this fix in your
non-critical fixes branch ?
^ permalink raw reply
* [PATCH 1/1] usb: fsl-mxc-udc: fix build error due to mach/hardware.h
From: Shawn Guo @ 2013-01-11 11:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111105651.GF11085@arwen.pp.htv.fi>
On Fri, Jan 11, 2013 at 12:56:51PM +0200, Felipe Balbi wrote:
> Hi,
>
> On Fri, Jan 11, 2013 at 05:56:28PM +0800, Peter Chen wrote:
> > It changes the driver to use platform_device_id rather than cpu_is_xxx
> > to determine the SoC type, and updates the platform code accordingly.
> >
> > Compile ok at imx_v6_v7_defconfig with CONFIG_USB_FSL_USB2 enable.
> > Tested at mx51 bbg board, it works ok after enable phy clock
> > (Need another patch to fix this problem)
> >
> > Signed-off-by: Peter Chen <peter.chen@freescale.com>
>
> this is too big for -rc, can you break it down into smaller pieces ?
>
This is a patch missed from my series that enables multiplatform
support for IMX (because the driver is not enabled in defconfig,
sorry). To me, it's logically one patch to convert the driver over
to use platform_device_id. It does not make much sense to split it.
Shawn
^ permalink raw reply
* [PATCH 01/16] ARM: b.L: secondary kernel entry code
From: Dave Martin @ 2013-01-11 11:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111105525.GC12977@mudshark.cambridge.arm.com>
On Fri, Jan 11, 2013 at 10:55:26AM +0000, Will Deacon wrote:
> On Fri, Jan 11, 2013 at 01:26:21AM +0000, Nicolas Pitre wrote:
> > On Thu, 10 Jan 2013, Will Deacon wrote:
> > > On Thu, Jan 10, 2013 at 12:20:36AM +0000, Nicolas Pitre wrote:
> > > > +
> > > > +extern volatile unsigned long bL_entry_vectors[BL_NR_CLUSTERS][BL_CPUS_PER_CLUSTER];
> > >
> > > Does this actually need to be volatile? I'd have thought a compiler
> > > barrier in place of the smp_wmb below would be enough (following on from
> > > Catalin's comments).
> >
> > Actually, I did the reverse i.e. I removed the smp_wmb() entirely. A
> > compiler barrier forces the whole world to memory while here we only
> > want this particular assignment to be pushed out.
> >
> > Furthermore, I like the volatile as it flags that this is a special
> > variable which in this case is also accessed from CPUs with no cache.
>
> Ok, fair enough. Given that the smp_wmb isn't needed that sounds better.
>
> > > > + /* We didn't expect this CPU. Try to make it quiet. */
> > > > +1: wfi
> > > > + wfe
> > > > + b 1b
> > >
> > > I realise this CPU is stuck at this point, but you should have a dsb
> > > before a wfi instruction. This could be problematic with the CCI this
> > > early, so maybe just a comment saying that it doesn't matter because we
> > > don't care about this core?
> >
> > Why a dsb? No data was even touched at this point. And since this is
> > meant to be a better "b ." kind of loop, I'd rather not try to make it
> > more sophisticated than it already is. And of course it is meant to
> > never be executed in practice.
>
> Sure, that's why I think just mentioning that we don't ever plan to boot
> this CPU is a good idea (so people don't add code here later on).
I agree with the conclusions here.
> > > > diff --git a/arch/arm/include/asm/bL_entry.h b/arch/arm/include/asm/bL_entry.h
> > > > new file mode 100644
> > > > index 0000000000..ff623333a1
> > > > --- /dev/null
> > > > +++ b/arch/arm/include/asm/bL_entry.h
> > > > @@ -0,0 +1,35 @@
> > > > +/*
> > > > + * arch/arm/include/asm/bL_entry.h
> > > > + *
> > > > + * Created by: Nicolas Pitre, April 2012
> > > > + * Copyright: (C) 2012 Linaro Limited
> > > > + *
> > > > + * This program is free software; you can redistribute it and/or modify
> > > > + * it under the terms of the GNU General Public License version 2 as
> > > > + * published by the Free Software Foundation.
> > > > + */
> > > > +
> > > > +#ifndef BL_ENTRY_H
> > > > +#define BL_ENTRY_H
> > > > +
> > > > +#define BL_CPUS_PER_CLUSTER 4
> > > > +#define BL_NR_CLUSTERS 2
> > >
> > > Hmm, I see these have to be constant so you can allocate your space in
> > > the assembly file. In which case, I think it's worth changing their
> > > names to have MAX or LIMIT in them...
> >
> > Yes, good point. I'll change them.
>
> Thanks.
>
> > > maybe they could even be CONFIG options?
> >
> > Nah. I prefer not adding new config options unless this is really
> > necessary or useful. For the forseeable future, we'll see systems with
> > at most 2 clusters and at most 4 CPUs per cluster. That could easily be
> > revisited later if that becomes unsuitable for some new systems.
>
> The current GIC is limited to 8 CPUs, so 4x2 is also a realistic possibility.
>
> > Initially I wanted all those things to be runtime sized in relation with
> > the TODO item in the commit log. That too can come later.
>
> Out of interest: how would you achieve that? I also thought about getting
> this information from the device tree, but I can't see how to plug that in
> with static storage.
I think you would just have to bite the bullet and go dynamic in this
case. But it's not a lot of data in total with the current limits, so
this feels like overkill.
If we eventually need to go many-CPU with this code, it will need
addressing, but there are no current plans for that that I know of.
Cheers
---Dave
^ permalink raw reply
* [PATCH 03/16] ARM: b.L: introduce helpers for platform coherency exit/setup
From: Dave Martin @ 2013-01-11 11:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1301101400060.6300@xanadu.home>
On Thu, Jan 10, 2013 at 02:04:02PM -0500, Nicolas Pitre wrote:
> On Thu, 10 Jan 2013, Dave Martin wrote:
>
> > > +int __init bL_cluster_sync_init(void (*power_up_setup)(void))
> >
> > The addition of the affinity level parameter for power_up_setup means
> > that this prototype is not correct.
>
> Indeed.
>
> > This is not a functional change, since that function is only called from
> > assembler anyway, but it will help avoid confusion.
>
> Fixed now, as well as the DCSCB usage.
>
>
> Nicolas
OK, thanks
---Dave
^ permalink raw reply
* [PATCH 02/16] ARM: b.L: introduce the CPU/cluster power API
From: Dave Martin @ 2013-01-11 11:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1301102055320.6300@xanadu.home>
On Thu, Jan 10, 2013 at 09:30:06PM -0500, Nicolas Pitre wrote:
> On Thu, 10 Jan 2013, Will Deacon wrote:
>
> > On Thu, Jan 10, 2013 at 12:20:37AM +0000, Nicolas Pitre wrote:
> > > This is the basic API used to handle the powering up/down of individual
> > > CPUs in a big.LITTLE system. The platform specific backend implementation
> > > has the responsibility to also handle the cluster level power as well when
> > > the first/last CPU in a cluster is brought up/down.
> > >
> > > Signed-off-by: Nicolas Pitre <nico@linaro.org>
> > > ---
> > > arch/arm/common/bL_entry.c | 88 +++++++++++++++++++++++++++++++++++++++
> > > arch/arm/include/asm/bL_entry.h | 92 +++++++++++++++++++++++++++++++++++++++++
> > > 2 files changed, 180 insertions(+)
> > >
> > > diff --git a/arch/arm/common/bL_entry.c b/arch/arm/common/bL_entry.c
> > > index 80fff49417..41de0622de 100644
> > > --- a/arch/arm/common/bL_entry.c
> > > +++ b/arch/arm/common/bL_entry.c
> > > @@ -11,11 +11,13 @@
> > >
> > > #include <linux/kernel.h>
> > > #include <linux/init.h>
> > > +#include <linux/irqflags.h>
> > >
> > > #include <asm/bL_entry.h>
> > > #include <asm/barrier.h>
> > > #include <asm/proc-fns.h>
> > > #include <asm/cacheflush.h>
> > > +#include <asm/idmap.h>
> > >
> > > extern volatile unsigned long bL_entry_vectors[BL_NR_CLUSTERS][BL_CPUS_PER_CLUSTER];
> > >
> > > @@ -28,3 +30,89 @@ void bL_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr)
> > > outer_clean_range(__pa(&bL_entry_vectors[cluster][cpu]),
> > > __pa(&bL_entry_vectors[cluster][cpu + 1]));
> > > }
> > > +
> > > +static const struct bL_platform_power_ops *platform_ops;
> > > +
> > > +int __init bL_platform_power_register(const struct bL_platform_power_ops *ops)
> > > +{
> > > + if (platform_ops)
> > > + return -EBUSY;
> > > + platform_ops = ops;
> > > + return 0;
> > > +}
> > > +
> > > +int bL_cpu_power_up(unsigned int cpu, unsigned int cluster)
> > > +{
> > > + if (!platform_ops)
> > > + return -EUNATCH;
> >
> > Is this the right error code?
>
> It is as good as any other, with some meaning to be distinguished from
> the traditional ones like -ENOMEM or -EINVAL that the platform backends
> could return.
>
> Would you prefer another one?
>
> > > + might_sleep();
> > > + return platform_ops->power_up(cpu, cluster);
> > > +}
> > > +
> > > +typedef void (*phys_reset_t)(unsigned long);
> >
> > Maybe it's worth putting this typedef in a header file somewhere. It's
> > also used by the soft reboot code.
>
> Agreed. Maybe separately from this series though.
>
> > > +
> > > +void bL_cpu_power_down(void)
> > > +{
> > > + phys_reset_t phys_reset;
> > > +
> > > + BUG_ON(!platform_ops);
> >
> > Seems a bit overkill, or are we unrecoverable by this point?
>
> We are. The upper layer expects this CPU to be dead and there is no
> easy recovery possible. This is a "should never happen" condition, and
> the kernel is badly configured otherwise.
bL_cpu_power_down() is unconditional and does not fail. This means
that calling this function means that:
a) a subsequent call to bL_cpu_power_up() on this CPU will cause it
to jump to bL_entry_point, in something resembling reset state;
b) for all, part (or, rarely, none) of the intervening period, the
CPU may really be turned off.
Without this BUG_ON() we would need to implement a dummy mechanism
to send the CPU to bL_entry_point at the right time. If this happens
instantaneously (without waiting for bL_cpu_power_up()), then this
will likely lead to a spin of some sort unless it only happens
occasionally. Also, the whole purpose of this function is to power off
the CPU, permitting power savings, so if no means has been registered too
do that, a call to bL_power_off() is certainly buggy misuse.
>
> >
> > > + BUG_ON(!irqs_disabled());
> > > +
> > > + /*
> > > + * Do this before calling into the power_down method,
> > > + * as it might not always be safe to do afterwards.
> > > + */
> > > + setup_mm_for_reboot();
> > > +
> > > + platform_ops->power_down();
> > > +
> > > + /*
> > > + * It is possible for a power_up request to happen concurrently
> > > + * with a power_down request for the same CPU. In this case the
> > > + * power_down method might not be able to actually enter a
> > > + * powered down state with the WFI instruction if the power_up
> > > + * method has removed the required reset condition. The
> > > + * power_down method is then allowed to return. We must perform
> > > + * a re-entry in the kernel as if the power_up method just had
> > > + * deasserted reset on the CPU.
> > > + *
> > > + * To simplify race issues, the platform specific implementation
> > > + * must accommodate for the possibility of unordered calls to
> > > + * power_down and power_up with a usage count. Therefore, if a
> > > + * call to power_up is issued for a CPU that is not down, then
> > > + * the next call to power_down must not attempt a full shutdown
> > > + * but only do the minimum (normally disabling L1 cache and CPU
> > > + * coherency) and return just as if a concurrent power_up request
> > > + * had happened as described above.
> > > + */
> > > +
> > > + phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
> > > + phys_reset(virt_to_phys(bL_entry_point));
> > > +
> > > + /* should never get here */
> > > + BUG();
> > > +}
> > > +
> > > +void bL_cpu_suspend(u64 expected_residency)
> > > +{
> > > + phys_reset_t phys_reset;
> > > +
> > > + BUG_ON(!platform_ops);
> > > + BUG_ON(!irqs_disabled());
> > > +
> > > + /* Very similar to bL_cpu_power_down() */
> > > + setup_mm_for_reboot();
> > > + platform_ops->suspend(expected_residency);
> > > + phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
> > > + phys_reset(virt_to_phys(bL_entry_point));
> > > + BUG();
> > > +}
> > > +
> > > +int bL_cpu_powered_up(void)
> > > +{
> > > + if (!platform_ops)
> > > + return -EUNATCH;
> > > + if (platform_ops->powered_up)
> > > + platform_ops->powered_up();
> > > + return 0;
> > > +}
> > > diff --git a/arch/arm/include/asm/bL_entry.h b/arch/arm/include/asm/bL_entry.h
> > > index ff623333a1..942d7f9f19 100644
> > > --- a/arch/arm/include/asm/bL_entry.h
> > > +++ b/arch/arm/include/asm/bL_entry.h
> > > @@ -31,5 +31,97 @@ extern void bL_entry_point(void);
> > > */
> > > void bL_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr);
> > >
> > > +/*
> > > + * CPU/cluster power operations API for higher subsystems to use.
> > > + */
> > > +
> > > +/**
> > > + * bL_cpu_power_up - make given CPU in given cluster runable
> > > + *
> > > + * @cpu: CPU number within given cluster
> > > + * @cluster: cluster number for the CPU
> > > + *
> > > + * The identified CPU is brought out of reset. If the cluster was powered
> > > + * down then it is brought up as well, taking care not to let the other CPUs
> > > + * in the cluster run, and ensuring appropriate cluster setup.
> > > + *
> > > + * Caller must ensure the appropriate entry vector is initialized with
> > > + * bL_set_entry_vector() prior to calling this.
> > > + *
> > > + * This must be called in a sleepable context. However, the implementation
> > > + * is strongly encouraged to return early and let the operation happen
> > > + * asynchronously, especially when significant delays are expected.
> > > + *
> > > + * If the operation cannot be performed then an error code is returned.
> > > + */
> > > +int bL_cpu_power_up(unsigned int cpu, unsigned int cluster);
> > > +
> > > +/**
> > > + * bL_cpu_power_down - power the calling CPU down
> > > + *
> > > + * The calling CPU is powered down.
> > > + *
> > > + * If this CPU is found to be the "last man standing" in the cluster
> > > + * then the cluster is prepared for power-down too.
> > > + *
> > > + * This must be called with interrupts disabled.
> > > + *
> > > + * This does not return. Re-entry in the kernel is expected via
> > > + * bL_entry_point.
> > > + */
> > > +void bL_cpu_power_down(void);
> > > +
> > > +/**
> > > + * bL_cpu_suspend - bring the calling CPU in a suspended state
> > > + *
> > > + * @expected_residency: duration in microseconds the CPU is expected
> > > + * to remain suspended, or 0 if unknown/infinity.
> > > + *
> > > + * The calling CPU is suspended. The expected residency argument is used
> > > + * as a hint by the platform specific backend to implement the appropriate
> > > + * sleep state level according to the knowledge it has on wake-up latency
> > > + * for the given hardware.
> > > + *
> > > + * If this CPU is found to be the "last man standing" in the cluster
> > > + * then the cluster may be prepared for power-down too, if the expected
> > > + * residency makes it worthwhile.
> > > + *
> > > + * This must be called with interrupts disabled.
> > > + *
> > > + * This does not return. Re-entry in the kernel is expected via
> > > + * bL_entry_point.
> > > + */
> > > +void bL_cpu_suspend(u64 expected_residency);
> > > +
> > > +/**
> > > + * bL_cpu_powered_up - housekeeping workafter a CPU has been powered up
> > > + *
> > > + * This lets the platform specific backend code perform needed housekeeping
> > > + * work. This must be called by the newly activated CPU as soon as it is
> > > + * fully operational in kernel space, before it enables interrupts.
> > > + *
> > > + * If the operation cannot be performed then an error code is returned.
> > > + */
> > > +int bL_cpu_powered_up(void);
> > > +
> > > +/*
> > > + * Platform specific methods used in the implementation of the above API.
> > > + */
> > > +struct bL_platform_power_ops {
> > > + int (*power_up)(unsigned int cpu, unsigned int cluster);
> > > + void (*power_down)(void);
> > > + void (*suspend)(u64);
> > > + void (*powered_up)(void);
> > > +};
> >
> > It would be good if these prototypes matched the PSCI code, then platforms
> > could just glue them together directly.
>
> No.
>
> I discussed this at length with Charles (the PSCI spec author) already.
> Even in the PSCI case, a minimum PSCI backend is necessary to do some
> impedance matching between what the PSCI calls expect as arguments and
> what this kernel specific API needs to express. For example, the UP
> method needs to always be provided with the address for bL_entry,
> irrespective of where the user of this kernel API wants execution to be
> resumed. There might be some cases where the backend might decide to
> override the desired power saving state because of other kernel induced
> constraints (ongoing DMA operation for example) that PSCI doesn't (and
> should not) know about. And the best place to arbitrate between those
> platform specific constraints is in this platform specific shim or
> backend.
>
> Because of that, and because one feature of Linux is to not have stable
> APIs in the kernel so to be free to adapt them to future needs, I think
> it is best not to even try matching the PSCI interface here.
The kernel may need to do stuff in these functions, even if the
underlying backend is PSCI, so they wouldn't just be a pass-through ...
or does the mach-virt experience convince us that there would be nothing
to do? I feel unsure about that, but I've not looked at the mach-virt
code yet.
mach-virt lacks most of the hardware nasties which we can't ignore at
the host kernel / firmware interface.
Cheers
---Dave
^ permalink raw reply
* [PATCH v7 3/3] Cortex-M3: Add support for exception handling
From: Uwe Kleine-König @ 2013-01-11 11:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111111456.GH14860@pengutronix.de>
Hello Russell,
On Fri, Jan 11, 2013 at 12:14:56PM +0100, Uwe Kleine-K?nig wrote:
> On Fri, Jan 11, 2013 at 11:09:26AM +0000, Russell King - ARM Linux wrote:
> > On Fri, Jan 11, 2013 at 12:05:44PM +0100, Uwe Kleine-K?nig wrote:
> > > Hello,
> > >
> > > On Wed, Oct 17, 2012 at 10:34:32AM +0200, Uwe Kleine-K?nig wrote:
> > > > +/*
> > > > + * Register switch for ARMv7-M processors.
> > > > + * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
> > > > + * previous and next are guaranteed not to be the same.
> > > > + */
> > > > +ENTRY(__switch_to)
> > > > + .fnstart
> > > > + .cantunwind
> > > > + add ip, r1, #TI_CPU_SAVE
> > > > + stmia ip!, {r4 - r11} @ Store most regs on stack
> > > > + str sp, [ip], #4
> > > > + str lr, [ip], #4
> > > > + mov r5, r0
> > > > + add r4, r2, #TI_CPU_SAVE
> > > > + ldr r0, =thread_notify_head
> > > > + mov r1, #THREAD_NOTIFY_SWITCH
> > > > + bl atomic_notifier_call_chain
> > > > + mov ip, r4
> > > > + mov r0, r5
> > > > + ldmia ip!, {r4 - r11} @ Load all regs saved previously
> > > > + ldr sp, [ip], #4
> > > > + ldr pc, [ip]
> > > > + .fnend
> > > > +ENDPROC(__switch_to)
> > > this code triggers a warning
> > >
> > > This instruction may be unpredictable if executed on M-profile
> > > cores with interrupts enabled.
> > >
> > > with newer toolchains (seen with gcc 4.7.2) because of errata 752419
> > > (Interrupted loads to SP can cause erroneous behaviour) which badly
> > > affects the following instructions:
> > >
> > > ldr sp,[Rn],#imm
> > > ldr sp,[Rn,#imm]!
> >
> > Wonder if that means we need to fix it in entry-armv.S too, as it uses
> > the same sequence for Thumb:
> >
> > THUMB( ldr sp, [ip], #4 )
> > THUMB( ldr pc, [ip] )
> >
> > and, of course, M-profile stuff is also Thumb.
> entry-armv.S is not affected as this code snipplet is for switching from
> ARM to THUMB mode on kernel entry. The M-profile CPUs don't have a ARM
> mode, so this code isn't active for them anyhow. (I have a patch in my
> queue to allow entry in Thumb mode for thumb-only CPUs.)
This is wrong, it's not in initial switching to Thumb mode but in
__switch_to. Still this code isn't used for Cortex-M3 CPUs.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH] arch/arm/plat-omap: initializing dma_lch_count, before judging omap_dma_reserve_channels
From: Chen Gang @ 2013-01-11 11:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50EFBEB3.4080207@ti.com>
? 2013?01?11? 15:26, Santosh Shilimkar ??:
> On Friday 11 January 2013 10:33 AM, Chen Gang wrote:
>> ?? 2013??01??10?? 18:48, Santosh Shilimkar ???:
>>> 'omap_dma_reserve_channels' when used is suppose to be from command
>>> line. Hence the proposed fix in the review is the right one.
>>
>> ok, thank you for your suggestion.
>>
>> I will send patch v2, also mark you as Signed-of-by.
>>
> Acked-by: is just fine.
>
>
>
thanks, I have send patch v2 for it, since it is a new subject, so
still use [PATCH] instead of [PATCH v2].
the subject of the new patch (which has sent) is:
[PATCH] ARM: OMAP: Fix the use of uninitialized dma_lch_count
please check, thanks.
--
Chen Gang
Asianux Corporation
^ permalink raw reply
* [PATCH v7 3/3] Cortex-M3: Add support for exception handling
From: Uwe Kleine-König @ 2013-01-11 11:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111110926.GD30875@n2100.arm.linux.org.uk>
Hello Russell,
On Fri, Jan 11, 2013 at 11:09:26AM +0000, Russell King - ARM Linux wrote:
> On Fri, Jan 11, 2013 at 12:05:44PM +0100, Uwe Kleine-K?nig wrote:
> > Hello,
> >
> > On Wed, Oct 17, 2012 at 10:34:32AM +0200, Uwe Kleine-K?nig wrote:
> > > +/*
> > > + * Register switch for ARMv7-M processors.
> > > + * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
> > > + * previous and next are guaranteed not to be the same.
> > > + */
> > > +ENTRY(__switch_to)
> > > + .fnstart
> > > + .cantunwind
> > > + add ip, r1, #TI_CPU_SAVE
> > > + stmia ip!, {r4 - r11} @ Store most regs on stack
> > > + str sp, [ip], #4
> > > + str lr, [ip], #4
> > > + mov r5, r0
> > > + add r4, r2, #TI_CPU_SAVE
> > > + ldr r0, =thread_notify_head
> > > + mov r1, #THREAD_NOTIFY_SWITCH
> > > + bl atomic_notifier_call_chain
> > > + mov ip, r4
> > > + mov r0, r5
> > > + ldmia ip!, {r4 - r11} @ Load all regs saved previously
> > > + ldr sp, [ip], #4
> > > + ldr pc, [ip]
> > > + .fnend
> > > +ENDPROC(__switch_to)
> > this code triggers a warning
> >
> > This instruction may be unpredictable if executed on M-profile
> > cores with interrupts enabled.
> >
> > with newer toolchains (seen with gcc 4.7.2) because of errata 752419
> > (Interrupted loads to SP can cause erroneous behaviour) which badly
> > affects the following instructions:
> >
> > ldr sp,[Rn],#imm
> > ldr sp,[Rn,#imm]!
>
> Wonder if that means we need to fix it in entry-armv.S too, as it uses
> the same sequence for Thumb:
>
> THUMB( ldr sp, [ip], #4 )
> THUMB( ldr pc, [ip] )
>
> and, of course, M-profile stuff is also Thumb.
entry-armv.S is not affected as this code snipplet is for switching from
ARM to THUMB mode on kernel entry. The M-profile CPUs don't have a ARM
mode, so this code isn't active for them anyhow. (I have a patch in my
queue to allow entry in Thumb mode for thumb-only CPUs.)
Best regards and thanks for your heedfulness,
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH] mmc: mvsdio: Replace IS_ERR_NULL() is with IS_ERR()
From: Russell King - ARM Linux @ 2013-01-11 11:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111120909.2cee1b8e@skate>
On Fri, Jan 11, 2013 at 12:09:09PM +0100, Thomas Petazzoni wrote:
> Dear Russell King - ARM Linux,
>
> On Fri, 11 Jan 2013 11:02:10 +0000, Russell King - ARM Linux wrote:
>
> > What remains? The assumption that GPIO0 means "no GPIO" rather than
> > testing with gpio_valid() and the IRQ stuff.
>
> Patches that I have written have been merged by Jason Cooper and while
> adding the DT binding for this driver, it also converts it to use the
> MMC GPIO helpers from drivers/mmc/core/slot-gpio.c, which makes this
> whole GPIO initialization/cleanup a lot simpler.
Please also fix the whole raft of other crap in this driver too, as
I've highlighted previously and in these patches.
^ permalink raw reply
* [PATCH 03/16] ARM: b.L: introduce helpers for platform coherency exit/setup
From: Dave Martin @ 2013-01-11 11:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1301102028510.6300@xanadu.home>
On Thu, Jan 10, 2013 at 08:50:59PM -0500, Nicolas Pitre wrote:
> On Thu, 10 Jan 2013, Will Deacon wrote:
>
> > On Thu, Jan 10, 2013 at 12:20:38AM +0000, Nicolas Pitre wrote:
> > > From: Dave Martin <dave.martin@linaro.org>
> > >
> > > This provides helper methods to coordinate between CPUs coming down
> > > and CPUs going up, as well as documentation on the used algorithms,
> > > so that cluster teardown and setup
> > > operations are not done for a cluster simultaneously.
> >
> > [...]
> >
> > > +int __init bL_cluster_sync_init(void (*power_up_setup)(void))
> > > +{
> > > + unsigned int i, j, mpidr, this_cluster;
> > > +
> > > + BUILD_BUG_ON(BL_SYNC_CLUSTER_SIZE * BL_NR_CLUSTERS != sizeof bL_sync);
> > > + BUG_ON((unsigned long)&bL_sync & (__CACHE_WRITEBACK_GRANULE - 1));
> > > +
> > > + /*
> > > + * Set initial CPU and cluster states.
> > > + * Only one cluster is assumed to be active at this point.
> > > + */
> > > + for (i = 0; i < BL_NR_CLUSTERS; i++) {
> > > + bL_sync.clusters[i].cluster = CLUSTER_DOWN;
> > > + bL_sync.clusters[i].inbound = INBOUND_NOT_COMING_UP;
> > > + for (j = 0; j < BL_CPUS_PER_CLUSTER; j++)
> > > + bL_sync.clusters[i].cpus[j].cpu = CPU_DOWN;
> > > + }
> > > + asm ("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> >
> > We have a helper for this...
Agreed, we would ideally use a single definition for that.
> >
> > > + this_cluster = (mpidr >> 8) & 0xf;
> >
> > ... and also this, thanks to Lorenzo's recent patches.
>
> Indeed, I'll have a closer look at them.
>
> > > + for_each_online_cpu(i)
> > > + bL_sync.clusters[this_cluster].cpus[i].cpu = CPU_UP;
> > > + bL_sync.clusters[this_cluster].cluster = CLUSTER_UP;
> > > + sync_mem(&bL_sync);
> > > +
> > > + if (power_up_setup) {
> > > + bL_power_up_setup_phys = virt_to_phys(power_up_setup);
> > > + sync_mem(&bL_power_up_setup_phys);
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > diff --git a/arch/arm/common/bL_head.S b/arch/arm/common/bL_head.S
> > > index 9d351f2b4c..f7a64ac127 100644
> > > --- a/arch/arm/common/bL_head.S
> > > +++ b/arch/arm/common/bL_head.S
> > > @@ -7,11 +7,19 @@
> > > * This program is free software; you can redistribute it and/or modify
> > > * it under the terms of the GNU General Public License version 2 as
> > > * published by the Free Software Foundation.
> > > + *
> > > + *
> > > + * Refer to Documentation/arm/big.LITTLE/cluster-pm-race-avoidance.txt
> > > + * for details of the synchronisation algorithms used here.
> > > */
> > >
> > > #include <linux/linkage.h>
> > > #include <asm/bL_entry.h>
> > >
> > > +.if BL_SYNC_CLUSTER_CPUS
> > > +.error "cpus must be the first member of struct bL_cluster_sync_struct"
> > > +.endif
> > > +
> > > .macro pr_dbg cpu, string
> > > #if defined(CONFIG_DEBUG_LL) && defined(DEBUG)
> > > b 1901f
> > > @@ -52,12 +60,82 @@ ENTRY(bL_entry_point)
> > > 2: pr_dbg r4, "kernel bL_entry_point\n"
> > >
> > > /*
> > > - * MMU is off so we need to get to bL_entry_vectors in a
> > > + * MMU is off so we need to get to various variables in a
> > > * position independent way.
> > > */
> > > adr r5, 3f
> > > - ldr r6, [r5]
> > > + ldmia r5, {r6, r7, r8}
> > > add r6, r5, r6 @ r6 = bL_entry_vectors
> > > + ldr r7, [r5, r7] @ r7 = bL_power_up_setup_phys
> > > + add r8, r5, r8 @ r8 = bL_sync
> > > +
> > > + mov r0, #BL_SYNC_CLUSTER_SIZE
> > > + mla r8, r0, r10, r8 @ r8 = bL_sync cluster base
> > > +
> > > + @ Signal that this CPU is coming UP:
> > > + mov r0, #CPU_COMING_UP
> > > + mov r5, #BL_SYNC_CPU_SIZE
> > > + mla r5, r9, r5, r8 @ r5 = bL_sync cpu address
> > > + strb r0, [r5]
> > > +
> > > + dsb
> >
> > Why is a dmb not enough here? In fact, the same goes for most of these
> > other than the one preceeding the sev. Is there an interaction with the
> > different mappings for the cluster data that I've missed?
>
> Probably Dave could comment more on this as this is his code, or Achin
> who also reviewed it. I don't know the level of discussion that
> happened inside ARM around those barriers.
>
> When the TC2 firmware didn't properly handle the ACP snoops, the dsb's
> couldn't be used at this point. The replacement for a dsb was a read
> back followed by a dmb in that case, and then the general sentiment was
> that this was an A15 specific workaround which wasn't architecturally
> guaranteed on all ARMv7 compliant implementations, or something along
> those lines.
>
> Given that the TC2 firmware properly handles the snoops now, and that
> the dsb apparently doesn't require a readback, we just decided to revert
> to having simple dsb's.
I'll take another look at the code and think about this again. This code
was initially a bit conservative. Because we are S-O at this point,
most of your potential dmbs should actually require no barrier at all
(as in the vlock code). I was cautious about that, but we've now seen
the principle work successfully with the vlock code (which postdates
the cluster state handling code here).
The one exception is before SEV. Also, before WFE (opinions differ, but
since we are about to wait anyway the extra time cost of the dsb is not
really a concern here).
>
> > > +
> > > + @ At this point, the cluster cannot unexpectedly enter the GOING_DOWN
> > > + @ state, because there is at least one active CPU (this CPU).
> > > +
> > > + @ Check if the cluster has been set up yet:
> > > + ldrb r0, [r8, #BL_SYNC_CLUSTER_CLUSTER]
> > > + cmp r0, #CLUSTER_UP
> > > + beq cluster_already_up
> > > +
> > > + @ Signal that the cluster is being brought up:
> > > + mov r0, #INBOUND_COMING_UP
> > > + strb r0, [r8, #BL_SYNC_CLUSTER_INBOUND]
> > > +
> > > + dsb
> > > +
> > > + @ Any CPU trying to take the cluster into CLUSTER_GOING_DOWN from this
> > > + @ point onwards will observe INBOUND_COMING_UP and abort.
> > > +
> > > + @ Wait for any previously-pending cluster teardown operations to abort
> > > + @ or complete:
> > > +cluster_teardown_wait:
> > > + ldrb r0, [r8, #BL_SYNC_CLUSTER_CLUSTER]
> > > + cmp r0, #CLUSTER_GOING_DOWN
> > > + wfeeq
> > > + beq cluster_teardown_wait
> > > +
> > > + @ power_up_setup is responsible for setting up the cluster:
> > > +
> > > + cmp r7, #0
> > > + mov r0, #1 @ second (cluster) affinity level
> > > + blxne r7 @ Call power_up_setup if defined
> > > +
> > > + @ Leave the cluster setup critical section:
> > > +
> > > + dsb
> > > + mov r0, #INBOUND_NOT_COMING_UP
> > > + strb r0, [r8, #BL_SYNC_CLUSTER_INBOUND]
> > > + mov r0, #CLUSTER_UP
> > > + strb r0, [r8, #BL_SYNC_CLUSTER_CLUSTER]
> > > + dsb
> > > + sev
> > > +
> > > +cluster_already_up:
> > > + @ If a platform-specific CPU setup hook is needed, it is
> > > + @ called from here.
> > > +
> > > + cmp r7, #0
> > > + mov r0, #0 @ first (CPU) affinity level
> > > + blxne r7 @ Call power_up_setup if defined
> > > +
> > > + @ Mark the CPU as up:
> > > +
> > > + dsb
> > > + mov r0, #CPU_UP
> > > + strb r0, [r5]
> > > + dsb
> > > + sev
> > >
> > > bL_entry_gated:
> > > ldr r5, [r6, r4, lsl #2] @ r5 = CPU entry vector
> > > @@ -70,6 +148,8 @@ bL_entry_gated:
> > > .align 2
> > >
> > > 3: .word bL_entry_vectors - .
> > > + .word bL_power_up_setup_phys - 3b
> > > + .word bL_sync - 3b
> > >
> > > ENDPROC(bL_entry_point)
> > >
> > > @@ -79,3 +159,7 @@ ENDPROC(bL_entry_point)
> > > .type bL_entry_vectors, #object
> > > ENTRY(bL_entry_vectors)
> > > .space 4 * BL_NR_CLUSTERS * BL_CPUS_PER_CLUSTER
> > > +
> > > + .type bL_power_up_setup_phys, #object
> > > +ENTRY(bL_power_up_setup_phys)
> > > + .space 4 @ set by bL_cluster_sync_init()
> > > diff --git a/arch/arm/include/asm/bL_entry.h b/arch/arm/include/asm/bL_entry.h
> > > index 942d7f9f19..167394d9a0 100644
> > > --- a/arch/arm/include/asm/bL_entry.h
> > > +++ b/arch/arm/include/asm/bL_entry.h
> > > @@ -15,8 +15,37 @@
> > > #define BL_CPUS_PER_CLUSTER 4
> > > #define BL_NR_CLUSTERS 2
> > >
> > > +/* Definitions for bL_cluster_sync_struct */
> > > +#define CPU_DOWN 0x11
> > > +#define CPU_COMING_UP 0x12
> > > +#define CPU_UP 0x13
> > > +#define CPU_GOING_DOWN 0x14
> > > +
> > > +#define CLUSTER_DOWN 0x21
> > > +#define CLUSTER_UP 0x22
> > > +#define CLUSTER_GOING_DOWN 0x23
> > > +
> > > +#define INBOUND_NOT_COMING_UP 0x31
> > > +#define INBOUND_COMING_UP 0x32
> >
> > Do these numbers signify anything? Why not 0, 1, 2 etc?
>
> Initially that's what they were. But durring debugging (as we faced a
> few cache coherency issues here) it was more useful to use numbers with
> an easily distinguishable signature. For example, a 0 may come from
> anywhere and could mean anything so that is about the worst choice.
> Other than that, those numbers have no particular significance.
>
> > > +
> > > +/* This is a complete guess. */
> > > +#define __CACHE_WRITEBACK_ORDER 6
> >
> > Is this CONFIG_ARM_L1_CACHE_SHIFT?
>
> No. That has to cover L2 as well.
Of course, I seem to remember that there are assumptions elsewhere in
the kernel that 1 << CONFIG_ARM_L1_CACHE_SHIFT is (at least) the cache
writeback granule.
I prefer not to use a macro with a wholly misleading name, but I would
like a "proper" way to get this value, if there is one ... ?
One reason for adding a #define here was to document the fact that the
value used really is a guess and that we have no correct way to discover
it.
>
> > > +#define __CACHE_WRITEBACK_GRANULE (1 << __CACHE_WRITEBACK_ORDER)
> > > +
> > > +/* Offsets for the bL_cluster_sync_struct members, for use in asm: */
> > > +#define BL_SYNC_CLUSTER_CPUS 0
> >
> > Why not use asm-offsets.h for this?
>
> That's how that was done initially. But that ended up cluttering
> asm-offsets.h for stuff that actually is really a local implementation
> detail which doesn't need kernel wide scope. In other words, the end
> result looked worse.
>
> One could argue that they are still exposed too much as the only files
> that need to know about those defines are bL_head.S and bL_entry.c.
>
> > > +#define BL_SYNC_CPU_SIZE __CACHE_WRITEBACK_GRANULE
> > > +#define BL_SYNC_CLUSTER_CLUSTER \
> > > + (BL_SYNC_CLUSTER_CPUS + BL_SYNC_CPU_SIZE * BL_CPUS_PER_CLUSTER)
> > > +#define BL_SYNC_CLUSTER_INBOUND \
> > > + (BL_SYNC_CLUSTER_CLUSTER + __CACHE_WRITEBACK_GRANULE)
> > > +#define BL_SYNC_CLUSTER_SIZE \
> > > + (BL_SYNC_CLUSTER_INBOUND + __CACHE_WRITEBACK_GRANULE)
> > > +
> >
> > Hmm, this looks pretty fragile to me but again, you need this stuff at
> > compile time.
>
> There are compile time and run time assertions in bL_entry.c to ensure
> those offsets and the corresponding C structure don't get out of sync.
>
> > Is there an architected maximum value for the writeback
> > granule? Failing that, we may as well just use things like
There is an architectural maximum, bit it is 2K (which although "safe"
feels a bit excessive for our purposes. A 2+3 CPU system would require
at least 22K for the synchronisation data with this assumption, rising to
28K for 4+4. Not the end of the world for .bss data on modern hardware
with GB of DRAM, but it still feels wasteful.
Does anyone have a view on how much we care?
If there is no outer cache, the actual granule size can be determined
via CP15 at run-time; if there is an outer cache, we would also need
to find out its granule somehow.
> > __cacheline_aligned if we're only using the L1 alignment anyway.
>
> See above -- we need L2 alignment.
This partly depends on whether __cacheline_aligned is supposed to
guarantee cache writeback granule alignment. Is it? At best I was highly
uncertain about this.
Cheers
---Dave
^ permalink raw reply
* [PATCH v7 3/3] Cortex-M3: Add support for exception handling
From: Russell King - ARM Linux @ 2013-01-11 11:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111110544.GG14860@pengutronix.de>
On Fri, Jan 11, 2013 at 12:05:44PM +0100, Uwe Kleine-K?nig wrote:
> Hello,
>
> On Wed, Oct 17, 2012 at 10:34:32AM +0200, Uwe Kleine-K?nig wrote:
> > +/*
> > + * Register switch for ARMv7-M processors.
> > + * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
> > + * previous and next are guaranteed not to be the same.
> > + */
> > +ENTRY(__switch_to)
> > + .fnstart
> > + .cantunwind
> > + add ip, r1, #TI_CPU_SAVE
> > + stmia ip!, {r4 - r11} @ Store most regs on stack
> > + str sp, [ip], #4
> > + str lr, [ip], #4
> > + mov r5, r0
> > + add r4, r2, #TI_CPU_SAVE
> > + ldr r0, =thread_notify_head
> > + mov r1, #THREAD_NOTIFY_SWITCH
> > + bl atomic_notifier_call_chain
> > + mov ip, r4
> > + mov r0, r5
> > + ldmia ip!, {r4 - r11} @ Load all regs saved previously
> > + ldr sp, [ip], #4
> > + ldr pc, [ip]
> > + .fnend
> > +ENDPROC(__switch_to)
> this code triggers a warning
>
> This instruction may be unpredictable if executed on M-profile
> cores with interrupts enabled.
>
> with newer toolchains (seen with gcc 4.7.2) because of errata 752419
> (Interrupted loads to SP can cause erroneous behaviour) which badly
> affects the following instructions:
>
> ldr sp,[Rn],#imm
> ldr sp,[Rn,#imm]!
Wonder if that means we need to fix it in entry-armv.S too, as it uses
the same sequence for Thumb:
THUMB( ldr sp, [ip], #4 )
THUMB( ldr pc, [ip] )
and, of course, M-profile stuff is also Thumb.
^ permalink raw reply
* [PATCH] mmc: mvsdio: Replace IS_ERR_NULL() is with IS_ERR()
From: Thomas Petazzoni @ 2013-01-11 11:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111110210.GC30875@n2100.arm.linux.org.uk>
Dear Russell King - ARM Linux,
On Fri, 11 Jan 2013 11:02:10 +0000, Russell King - ARM Linux wrote:
> What remains? The assumption that GPIO0 means "no GPIO" rather than
> testing with gpio_valid() and the IRQ stuff.
Patches that I have written have been merged by Jason Cooper and while
adding the DT binding for this driver, it also converts it to use the
MMC GPIO helpers from drivers/mmc/core/slot-gpio.c, which makes this
whole GPIO initialization/cleanup a lot simpler.
See:
http://git.infradead.org/users/jcooper/linux.git/commitdiff/c3833fbb117bb1a547d29b27a0de4418fa2d5a5a
http://git.infradead.org/users/jcooper/linux.git/commitdiff/e60a21ed4edb7f33010ab21cefcb20666a9bc7d7
Also, note that Andrew Lunn has sent a v2 of his patch:
Subject: [PATCH v2] mmc: mvsdio: Replace IS_ERR_OR_NULL() with IS_ERR()
Date: Fri, 11 Jan 2013 08:27:52 +0100
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
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