* shmobile and struct sys_timer removal conflicts
From: Stephen Warren @ 2013-01-14 17:52 UTC (permalink / raw)
To: linux-arm-kernel
Simon,
I notice that the following shmobile-related commits in next-20130114
add new ARM machine descriptors, but set the .timer field rather than
the new .init_time field. I believe the code in these commits won't
build in linux-next or Linux 3.9 once it's released:
a625586 ARM: mach-shmobile: kzm9g: Reference DT implementation
ac0876f ARM: shmobile: armadillo800eva: Reference DT implementation
be1fc65 ARM: shmobile: add a reference DT implementation for mackerel
66f1162 ARM: mach-shmobile: sh73a0: Minimal setup using DT
In order to solve this problem, you'll need to adjust those changes
according to:
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git timer/cleanup
(where "adjust" is probably "rebase on top of")
^ permalink raw reply
* [PATCH v5 3/4] ARM: KVM: arch_timers: Add timer world switch
From: Marc Zyngier @ 2013-01-14 17:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130114152101.GD18935@mudshark.cambridge.arm.com>
On 14/01/13 15:21, Will Deacon wrote:
> On Tue, Jan 08, 2013 at 06:43:27PM +0000, Christoffer Dall wrote:
>> From: Marc Zyngier <marc.zyngier@arm.com>
>>
>> Do the necessary save/restore dance for the timers in the world
>> switch code. In the process, allow the guest to read the physical
>> counter, which is useful for its own clock_event_device.
>
> [...]
>
>> @@ -476,6 +513,7 @@ vcpu .req r0 @ vcpu pointer always in r0
>> * for the host.
>> *
>> * Assumes vcpu pointer in vcpu reg
>> + * Clobbers r2-r4
>> */
>> .macro restore_timer_state
>> @ Disallow physical timer access for the guest
>> @@ -484,6 +522,30 @@ vcpu .req r0 @ vcpu pointer always in r0
>> orr r2, r2, #CNTHCTL_PL1PCTEN
>> bic r2, r2, #CNTHCTL_PL1PCEN
>> mcr p15, 4, r2, c14, c1, 0 @ CNTHCTL
>> +
>> +#ifdef CONFIG_KVM_ARM_TIMER
>> + ldr r4, [vcpu, #VCPU_KVM]
>> + ldr r2, [r4, #KVM_TIMER_ENABLED]
>> + cmp r2, #0
>> + beq 1f
>> +
>> + ldr r2, [r4, #KVM_TIMER_CNTVOFF]
>> + ldr r3, [r4, #(KVM_TIMER_CNTVOFF + 4)]
>> + mcrr p15, 4, r2, r3, c14 @ CNTVOFF
>> + isb
>> +
>> + ldr r4, =VCPU_TIMER_CNTV_CVAL
>> + add vcpu, vcpu, r4
>> + ldrd r2, r3, [vcpu]
>> + sub vcpu, vcpu, r4
>> + mcrr p15, 3, r2, r3, c14 @ CNTV_CVAL
>> +
>> + ldr r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
>> + and r2, r2, #3
>> + mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL
>> + isb
>
> How many of these isbs are actually needed, given that we're going to make
> an exception return to the guest? The last one certainly looks redundant and
> I can't see the need for ordering CNTVOFF vs CNTV_CVAL. I can see an
> argument to putting one *before* CNTV_CTL, but you don't have one there!
CNTVOFF directly influences whether or not CNTV_CVAL will trigger or
not. Maybe I'm just being paranoid and moving the isb after CNTV_CVAL is
enough.
The last one is definitively superfluous.
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH] arm: mach-s3c24xx/common.c: fix uninitialized variable warning
From: Cong Ding @ 2013-01-14 17:51 UTC (permalink / raw)
To: linux-arm-kernel
the use of variable tmp is uninitialized, so we fix it.
Signed-off-by: Cong Ding <dinggnu@gmail.com>
---
arch/arm/mach-s3c24xx/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 0c9e9a7..6bcf87f 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -197,7 +197,7 @@ static unsigned long s3c24xx_read_idcode_v4(void)
static void s3c24xx_default_idle(void)
{
- unsigned long tmp;
+ unsigned long tmp = 0;
int i;
/* idle the system by using the idle mode which will wait for an
--
1.7.9.5
^ permalink raw reply related
* [PATCH] ARM: at91: fix board-rm9200-dt after sys_timer conversion
From: Stephen Warren @ 2013-01-14 17:42 UTC (permalink / raw)
To: linux-arm-kernel
From: Joachim Eastwood <manabian@gmail.com>
After "ARM: delete struct sys_timer" board-rm9200-dt
fails compilation with the following error:
CC arch/arm/mach-at91/board-rm9200-dt.o
arch/arm/mach-at91/board-rm9200-dt.c:50:2: error: unknown field 'timer' specified in initializer
arch/arm/mach-at91/board-rm9200-dt.c:50:13: error: 'at91rm9200_timer' undeclared here (not in a function)
make[1]: *** [arch/arm/mach-at91/board-rm9200-dt.o] Error 1
make: *** [arch/arm/mach-at91] Error 2
This is a fall out from the timer conversion. Fix it by
converting board-rm9200-dt to use new timer init
function as well.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
Olof, Arnd, another fix for the timer-cleanup branch in arm-soc.
arch/arm/mach-at91/board-rm9200-dt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-at91/board-rm9200-dt.c b/arch/arm/mach-at91/board-rm9200-dt.c
index 5f9ce3d..3fcb662 100644
--- a/arch/arm/mach-at91/board-rm9200-dt.c
+++ b/arch/arm/mach-at91/board-rm9200-dt.c
@@ -47,7 +47,7 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
};
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
- .timer = &at91rm9200_timer,
+ .init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = at91rm9200_dt_initialize,
--
1.7.10.4
^ permalink raw reply related
* [PATCH v2] arm: kernel/perf_event_cpu.c: remove unnecessary null pointer dereference check
From: Cong Ding @ 2013-01-14 17:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358183933-29160-1-git-send-email-dinggnu@gmail.com>
The NULL pointer check is not necessary. cpu_pmu_init() is called
after cpu_pmu has already been dereferenced by its caller:
cpu_pmu = pmu;
cpu_pmu->plat_device = pdev;
cpu_pmu_init(cpu_pmu);
Signed-off-by: Cong Ding <dinggnu@gmail.com>
---
arch/arm/kernel/perf_event_cpu.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index efa5295..43496f6 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -147,7 +147,7 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
cpu_pmu->free_irq = cpu_pmu_free_irq;
/* Ensure the PMU has sane values out of reset. */
- if (cpu_pmu && cpu_pmu->reset)
+ if (cpu_pmu->reset)
on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
}
--
1.7.4.5
^ permalink raw reply related
* [PATCH v3 1/3] usb: fsl-mxc-udc: replace cpu_is_xxx() with platform_device_id
From: Felipe Balbi @ 2013-01-14 17:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130114125632.GA30157@nchen-desktop>
Hi,
On Mon, Jan 14, 2013 at 08:56:33PM +0800, Peter Chen wrote:
<snip>
> > > Usually there isn't any Changelog between IP cores used in the different
> > > fsl processors (at least available outside of fsl), that makes it quite
> > > difficult to say if something found on one imx is really the same as on
> > > the other one. And they (usually) don't provide any versioning
> > > information in a register or the documentation.
> > >
> > > just my 2?
> >
> > $SUBJECT is trying to differentiate a single feature (or maybe two) to
> > replace cpu_is_xxx(), then expose that on driver_data without creating
> > one enum value for each release from fsl.
>
> Felipe, every one or two SoCs may have their special operations for
> integrate PHY interface, clk operation, or workaround for IC
> limitation.
the particular PHY and clk used should be hidden by phy layer and clk
API respectively. Workarounds, fair enough, we need to handle them; but
ideally those should be based on runtime revision detection, not some
hackery using driver_data.
> Maybe, it will add more future or SoCs (maybe not for this driver) in
> the future, using enum is easier than string comparison for expanding
> something.
a) I never told you to *not* use enum. I said that creating DEVICE_A,
DEVICE_B, DEVICE_C, DEVICE_D and DEVICE_E values when DEVICE_B,
DEVICE_C and DEVICE_E behave exactly the same is unnecessary.
b) you can't be expecting to add future SoCs support to fsl udc, I have
already said and will repeat for the last time: move to chipidea ASAP.
New SoCs cannot be added to fsl udc, you *must* use chipidea for
anything new and move the legacy to chipidea eventually. I will wait for
a full year for you to do that, but after that I will have to start
deleting drivers for the sake of avoid duplication of effort.
cheers
--
balbi
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^ permalink raw reply
* [PATCH] arm: kernel/perf_event_cpu.c: fix error null pointer dereference check
From: Will Deacon @ 2013-01-14 17:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130114173826.GA917@gmail.com>
On Mon, Jan 14, 2013 at 05:38:26PM +0000, Cong Ding wrote:
> On Mon, Jan 14, 2013 at 05:23:46PM +0000, Russell King - ARM Linux wrote:
> > On Mon, Jan 14, 2013 at 05:18:53PM +0000, Cong Ding wrote:
> > > the pointer cpu_pmu is used without null pointer dereference check, and is
> > > checked after the using of it, so we move the null pointer check to before the
> > > first use.
> >
> > The NULL pointer check is not necessary. cpu_pmu_init() is called
> > after cpu_pmu has already been dereferenced by its caller:
> >
> > cpu_pmu = pmu;
> > cpu_pmu->plat_device = pdev;
> > cpu_pmu_init(cpu_pmu);
> >
> > So...
> >
> > > - /* Ensure the PMU has sane values out of reset. */
> > > - if (cpu_pmu && cpu_pmu->reset)
> >
> > Just replace this with:
> > if (cpu_pmu->reset)
> Thanks Russell, I will send version 2.
No need, I've taken this into my perf/updates branch.
Thanks,
Will
^ permalink raw reply
* [PATCH] arm: kernel/perf_event_cpu.c: fix error null pointer dereference check
From: Cong Ding @ 2013-01-14 17:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130114172346.GK23505@n2100.arm.linux.org.uk>
On Mon, Jan 14, 2013 at 05:23:46PM +0000, Russell King - ARM Linux wrote:
> On Mon, Jan 14, 2013 at 05:18:53PM +0000, Cong Ding wrote:
> > the pointer cpu_pmu is used without null pointer dereference check, and is
> > checked after the using of it, so we move the null pointer check to before the
> > first use.
>
> The NULL pointer check is not necessary. cpu_pmu_init() is called
> after cpu_pmu has already been dereferenced by its caller:
>
> cpu_pmu = pmu;
> cpu_pmu->plat_device = pdev;
> cpu_pmu_init(cpu_pmu);
>
> So...
>
> > - /* Ensure the PMU has sane values out of reset. */
> > - if (cpu_pmu && cpu_pmu->reset)
>
> Just replace this with:
> if (cpu_pmu->reset)
Thanks Russell, I will send version 2.
- cong
^ permalink raw reply
* [PATCH v5 08/14] KVM: ARM: Emulation framework and CP15 emulation
From: Christoffer Dall @ 2013-01-14 17:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130114163636.GG23505@n2100.arm.linux.org.uk>
On Mon, Jan 14, 2013 at 11:36 AM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Tue, Jan 08, 2013 at 01:39:31PM -0500, Christoffer Dall wrote:
>> + /*
>> + * Check whether this vcpu requires the cache to be flushed on
>> + * this physical CPU. This is a consequence of doing dcache
>> + * operations by set/way on this vcpu. We do it here to be in
>> + * a non-preemptible section.
>> + */
>> + if (cpumask_test_cpu(cpu, &vcpu->arch.require_dcache_flush)) {
>> + cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
>
> There is cpumask_test_and_clear_cpu() which may be better for this.
nice:
commit d31686fadb74ad564f6a5acabdebe411de86d77d
Author: Christoffer Dall <c.dall@virtualopensystems.com>
Date: Mon Jan 14 12:36:53 2013 -0500
KVM: ARM: Use cpumask_test_and_clear_cpu
Nicer shorter cleaner code. Ahhhh.
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index b5c6ab1..fdd4a7c 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -352,10 +352,8 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
* operations by set/way on this vcpu. We do it here to be in
* a non-preemptible section.
*/
- if (cpumask_test_cpu(cpu, &vcpu->arch.require_dcache_flush)) {
- cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
+ if (cpumask_test_and_clear_cpu(cpu, &vcpu->arch.require_dcache_flush))
flush_cache_all(); /* We'd really want v7_flush_dcache_all() */
- }
kvm_arm_set_running_vcpu(vcpu);
}
--
Thanks,
-Christoffer
^ permalink raw reply related
* [PATCH v5 03/14] KVM: ARM: Initial skeleton to compile KVM support
From: Christoffer Dall @ 2013-01-14 17:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130114162415.GF23505@n2100.arm.linux.org.uk>
On Mon, Jan 14, 2013 at 11:24 AM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Tue, Jan 08, 2013 at 01:38:55PM -0500, Christoffer Dall wrote:
>> + /* -ENOENT for unknown features, -EINVAL for invalid combinations. */
>> + for (i = 0; i < sizeof(init->features)*8; i++) {
>> + if (init->features[i / 32] & (1 << (i % 32))) {
>
> Isn't this an open-coded version of test_bit() ?
indeed, nicely spotted:
commit 608588674144e403ad0ea3c93066f3175bd5cf88
Author: Christoffer Dall <c.dall@virtualopensystems.com>
Date: Mon Jan 14 12:30:07 2013 -0500
KVM: ARM: Use test-bit instead of open-coded version
Makes the code more readable, also adds spaces around the asterisk.
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c
index 65ae563..2339d96 100644
--- a/arch/arm/kvm/guest.c
+++ b/arch/arm/kvm/guest.c
@@ -193,8 +193,8 @@ int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
bitmap_zero(vcpu->arch.features, KVM_VCPU_MAX_FEATURES);
/* -ENOENT for unknown features, -EINVAL for invalid combinations. */
- for (i = 0; i < sizeof(init->features)*8; i++) {
- if (init->features[i / 32] & (1 << (i % 32))) {
+ for (i = 0; i < sizeof(init->features) * 8; i++) {
+ if (test_bit(i, (void *)init->features)) {
if (i >= KVM_VCPU_MAX_FEATURES)
return -ENOENT;
set_bit(i, vcpu->arch.features);
--
Thanks,
-Christoffer
^ permalink raw reply related
* [PATCH 08/16] ARM: bL_platsmp.c: make sure the GIC interface of a dying CPU is disabled
From: Will Deacon @ 2013-01-14 17:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1301141216020.6300@xanadu.home>
On Mon, Jan 14, 2013 at 05:18:24PM +0000, Nicolas Pitre wrote:
> On Mon, 14 Jan 2013, Will Deacon wrote:
> > Sorry! This case is more interesting though, because you also want to order
> > the cpu_if_down GIC write so that it completes before we do the power_off.
>
> In this case I'm leaning toward removing that gic_cpu_if_down()
> entirely. I'm not convinced it is necessary, and if it is then we
> probably have a bug somewhere else.
Or that :)
Will
^ permalink raw reply
* [PATCH] arm: kernel/perf_event_cpu.c: fix error null pointer dereference check
From: Russell King - ARM Linux @ 2013-01-14 17:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358183933-29160-1-git-send-email-dinggnu@gmail.com>
On Mon, Jan 14, 2013 at 05:18:53PM +0000, Cong Ding wrote:
> the pointer cpu_pmu is used without null pointer dereference check, and is
> checked after the using of it, so we move the null pointer check to before the
> first use.
The NULL pointer check is not necessary. cpu_pmu_init() is called
after cpu_pmu has already been dereferenced by its caller:
cpu_pmu = pmu;
cpu_pmu->plat_device = pdev;
cpu_pmu_init(cpu_pmu);
So...
> - /* Ensure the PMU has sane values out of reset. */
> - if (cpu_pmu && cpu_pmu->reset)
Just replace this with:
if (cpu_pmu->reset)
^ permalink raw reply
* [PATCH 07/16] ARM: bL_platsmp.c: close the kernel entry gate before hot-unplugging a CPU
From: Will Deacon @ 2013-01-14 17:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1301141207360.6300@xanadu.home>
On Mon, Jan 14, 2013 at 05:15:07PM +0000, Nicolas Pitre wrote:
> On Mon, 14 Jan 2013, Will Deacon wrote:
> > On Mon, Jan 14, 2013 at 04:53:41PM +0000, Nicolas Pitre wrote:
> > > The bL_set_entry_vector() includes a cache flush which itself has a DSB.
> > > Hence my previous interrogation.
> >
> > For L1, sure, we always have the dsb for v7. However, for the outer-cache we
> > only have a dsb by virtue of a spin_unlock in l2x0.c... it seems a bit risky
> > to rely on that for ordering your entry_vector write with the power_on.
> >
> > I think the best bet is to put a barrier in power_on, before invoking the
> > platform_ops function and similarly for power_off.
> >
> > What do you reckon?
>
> I much prefer adding barriers inside the API when they are needed for
> proper execution of the API intent. So if I call bL_set_entry_vector(),
> I trust that by the time it returns the vector is indeed set and ready
> for use by other processors.
>
> The same could be said about the outer cache ops. If a DSB is needed
> for their intent to be valid, then why isn't this DSB always implied by
> the corresponding cache op calls? And as you say, there is already one
> implied by the spinlock used there, so that is not if things would
> change much in practice.
Ok, so we can fix the outer_cache functions as suggested by Catalin. That
still leaves the GIC CPU interface problem in the later patch, which uses a
writel_relaxed to disable the CPU interface, so I suppose we can just put
a dsb at the end of gic_cpu_if_down().
Will
^ permalink raw reply
* linux-next: manual merge of the arm-soc tree with the crypto tree
From: Tony Lindgren @ 2013-01-14 17:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130114134908.094003722be0612c20574338@canb.auug.org.au>
* Stephen Rothwell <sfr@canb.auug.org.au> [130113 18:52]:
> Hi all,
>
> Today's linux-next merge of the arm-soc tree got a conflict in
> drivers/crypto/omap-sham.c between commit dfd061d5a8f5 ("crypto:
> omap-sham - Add code to use dmaengine API") from the crypto tree and
> commit a62a6e98c370 ("ARM: OMAP2+: Disable code that currently does not
> work with multiplaform") from the arm-soc tree.
>
> I fixed it up (the former removed the include that the latter protected)
> and can carry the fix as necessary (no action is required).
Thanks, yes the crypto tree changes fixed up things so the changes
coming from arm-soc tree are not needed any longer.
Regards,
Tony
^ permalink raw reply
* [PATCH] ARM: tegra: swap cache-/interrupt-ctrlr nodes in DT
From: Stephen Warren @ 2013-01-14 17:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
This ensures nodes are sorted in order of reg address. This makes it
easier to compare against e.g. the U-Boot device trees, and is simply
consistent and clean.
While we're at it, remove the unit address from the cache-controller
node name, since it's unique without it.
Reported-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
I intend to apply this immediately since it's trivial.
arch/arm/boot/dts/tegra20.dtsi | 18 +++++++++---------
arch/arm/boot/dts/tegra30.dtsi | 18 +++++++++---------
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 1ddbefd..dcd220c 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -105,15 +105,6 @@
interrupts = <1 13 0x304>;
};
- cache-controller at 50043000 {
- compatible = "arm,pl310-cache";
- reg = <0x50043000 0x1000>;
- arm,data-latency = <5 5 2>;
- arm,tag-latency = <4 4 2>;
- cache-unified;
- cache-level = <2>;
- };
-
intc: interrupt-controller {
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000
@@ -122,6 +113,15 @@
#interrupt-cells = <3>;
};
+ cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0x50043000 0x1000>;
+ arm,data-latency = <5 5 2>;
+ arm,tag-latency = <4 4 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
timer at 60005000 {
compatible = "nvidia,tegra20-timer";
reg = <0x60005000 0x60>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index dc6dc51..63a0d9b 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -105,15 +105,6 @@
interrupts = <1 13 0xf04>;
};
- cache-controller at 50043000 {
- compatible = "arm,pl310-cache";
- reg = <0x50043000 0x1000>;
- arm,data-latency = <6 6 2>;
- arm,tag-latency = <5 5 2>;
- cache-unified;
- cache-level = <2>;
- };
-
intc: interrupt-controller {
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000
@@ -122,6 +113,15 @@
#interrupt-cells = <3>;
};
+ cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0x50043000 0x1000>;
+ arm,data-latency = <6 6 2>;
+ arm,tag-latency = <5 5 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
timer at 60005000 {
compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
--
1.7.10.4
^ permalink raw reply related
* [PATCH] arm: kernel/perf_event_cpu.c: fix error null pointer dereference check
From: Cong Ding @ 2013-01-14 17:18 UTC (permalink / raw)
To: linux-arm-kernel
the pointer cpu_pmu is used without null pointer dereference check, and is
checked after the using of it, so we move the null pointer check to before the
first use.
Signed-off-by: Cong Ding <dinggnu@gmail.com>
---
arch/arm/kernel/perf_event_cpu.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index efa5295..16aa979 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -142,13 +142,15 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
raw_spin_lock_init(&events->pmu_lock);
}
- cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
- cpu_pmu->request_irq = cpu_pmu_request_irq;
- cpu_pmu->free_irq = cpu_pmu_free_irq;
+ if (cpu_pmu) {
+ cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
+ cpu_pmu->request_irq = cpu_pmu_request_irq;
+ cpu_pmu->free_irq = cpu_pmu_free_irq;
- /* Ensure the PMU has sane values out of reset. */
- if (cpu_pmu && cpu_pmu->reset)
- on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
+ /* Ensure the PMU has sane values out of reset. */
+ if (cpu_pmu->reset)
+ on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
+ }
}
/*
--
1.7.9.5
^ permalink raw reply related
* [PATCH 08/16] ARM: bL_platsmp.c: make sure the GIC interface of a dying CPU is disabled
From: Nicolas Pitre @ 2013-01-14 17:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130114170210.GE31341@mudshark.cambridge.arm.com>
On Mon, 14 Jan 2013, Will Deacon wrote:
> On Mon, Jan 14, 2013 at 04:54:52PM +0000, Nicolas Pitre wrote:
> > On Mon, 14 Jan 2013, Will Deacon wrote:
> >
> > > On Thu, Jan 10, 2013 at 12:20:43AM +0000, Nicolas Pitre wrote:
> > > > Otherwise there might be some interrupts or IPIs becoming pending and the
> > > > CPU will not enter low power mode when doing a WFI. The effect of this
> > > > is a CPU that loops back into the kernel, go through the first man
> > > > election, signals itself as alive, and prevent the cluster from being
> > > > shut down.
> > > >
> > > > This could benefit from a better solution.
> > > >
> > > > Signed-off-by: Nicolas Pitre <nico@linaro.org>
> > > > ---
> > > > arch/arm/common/bL_platsmp.c | 1 +
> > > > arch/arm/common/gic.c | 6 ++++++
> > > > arch/arm/include/asm/hardware/gic.h | 2 ++
> > > > 3 files changed, 9 insertions(+)
> > > >
> > > > diff --git a/arch/arm/common/bL_platsmp.c b/arch/arm/common/bL_platsmp.c
> > > > index 0ae44123bf..6a3b251b97 100644
> > > > --- a/arch/arm/common/bL_platsmp.c
> > > > +++ b/arch/arm/common/bL_platsmp.c
> > > > @@ -68,6 +68,7 @@ static void __ref bL_cpu_die(unsigned int cpu)
> > > > pcpu = mpidr & 0xff;
> > > > pcluster = (mpidr >> 8) & 0xff;
> > > > bL_set_entry_vector(pcpu, pcluster, NULL);
> > > > + gic_cpu_if_down();
> > >
> > > I'm starting to sound like a stuck record (and not a very tuneful one at
> > > that) but... I think you need a barrier here.
> >
> > And I'm getting puzzled at the repetition. ;-)
>
> Sorry! This case is more interesting though, because you also want to order
> the cpu_if_down GIC write so that it completes before we do the power_off.
In this case I'm leaning toward removing that gic_cpu_if_down()
entirely. I'm not convinced it is necessary, and if it is then we
probably have a bug somewhere else.
Nicolas
^ permalink raw reply
* [PATCH 01/14] mfd: omap-usb-host: Consolidate OMAP USB-HS platform data
From: Tony Lindgren @ 2013-01-14 17:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F3EBEF.8040809@ti.com>
* Roger Quadros <rogerq@ti.com> [130114 03:31]:
> On 01/11/2013 08:13 PM, Tony Lindgren wrote:
> > * Roger Quadros <rogerq@ti.com> [130111 01:43]:
> >> Tony,
> >>
> >> On 01/11/2013 01:45 AM, Tony Lindgren wrote:
> >>> * Roger Quadros <rogerq@ti.com> [130110 08:54]:
> >>>> Let's have a single platform data structure for the OMAP's High-Speed
> >>>> USB host subsystem instead of having 3 separate ones i.e. one for
> >>>> board data, one for USB Host (UHH) module and one for USB-TLL module.
> >>>>
> >>>> This makes the code much simpler and avoids creating multiple copies of
> >>>> platform data.
> >>>
> >>> I can apply just this patch alone into an immutable branch that
> >>> we all can merge in as needed as long as we have acks for the USB
> >>> and MFD parts.
> >>>
> >>> Or does this one need to be changed based on Alan's comments
> >>> on the EHCI lib related changes?
> >>>
> >>
> >> This does not depend on EHCI lib based changes but it depends on the
> >> OMAP USB Host cleanup series posted earlier.
> >
> > Can we first apply just the minimal platform_data + board file + clock
> > changes?
> >
> We could, but I'll then have to make changes to the patches in the first
> series and re-post them. Do you want me to do that?
Yes please. Otherwise we'll unnecessarily complicate the dependencies between
arch/arm/*omap* code and the drivers. And we've certainly had enough of
self-inflicted merge conflicts with the omap usb code already :)
> > That way I can apply those to some immutable tree for everybody to use,
> > and we cut off the dependency to the driver changes for the rest of the
> > patches. And then I'm off the hook for the rest of the patches :)
> >
>
> Or you could just ack this patch ;). The platform data is specific to
> USB host only :)
Well it's not just this patch. It's the clock related patches in your
earlier seriers that will conflict with any attempts to move the clock
data to live under drivers/clk/omap where it needs to go. And the three
patches at the end of this series to add platform data (which look fine),
but will likely conflict with something else. Let's try do do these changes
in a way where the dependencies are cut to minimum where possible.
Regards,
Tony
^ permalink raw reply
* [PATCH 04/18] power: ab8500_fg: Replace msleep() with usleep_range() for greater accuracy
From: Joe Perches @ 2013-01-14 17:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357909986-9262-5-git-send-email-lee.jones@linaro.org>
On Fri, 2013-01-11 at 13:12 +0000, Lee Jones wrote:
> Doing so provides a greater degree of accuracy when dealing with
> time-frames between 1us and 20ms. msleep() is only accurate for
> wake-ups greater than 20ms.
[]
> diff --git a/drivers/power/ab8500_fg.c b/drivers/power/ab8500_fg.c
[]
> @@ -956,7 +956,7 @@ static int ab8500_fg_load_comp_volt_to_capacity(struct ab8500_fg *di)
> do {
> vbat += ab8500_fg_bat_voltage(di);
> i++;
> - msleep(5);
> + usleep_range(5000, 5001);
If you're going to give a range that small
you might as well use usleep instead.
Otherwise, add some tolerance to allow any
other coalesced wakeup to occur.
^ permalink raw reply
* [PATCH V3] Add apf51 basic support
From: Laurent Cans @ 2013-01-14 17:16 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Laurent Cans <laurent.cans@gmail.com>
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
---
Differences between v2 and v3
- remove nand device
Differences between v1 and v2
- change board name according project convention
- remove useless compatible properties
- add project copyright
- use device name instead of soc structure for description
- add an entry for the board on documentation
Documentation/devicetree/bindings/arm/fsl.txt | 4 ++
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/imx51-apf51.dts | 55 +++++++++++++++++++++++++
arch/arm/boot/dts/imx51.dtsi | 30 ++++++++++++++
4 files changed, 91 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/imx51-apf51.dts
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index f798187..2549252 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -13,6 +13,10 @@ i.MX51 Babbage Board
Required root node properties:
- compatible = "fsl,imx51-babbage", "fsl,imx51";
+i.MX51 APF51 Board
+Required root node properties:
+ - compatible = "fsl,imx51-apf51", "fsl,imx51";
+
i.MX53 Automotive Reference Design Board
Required root node properties:
- compatible = "fsl,imx53-ard", "fsl,imx53";
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e44da40..1acf809 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -79,7 +79,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
armada-370-mirabox.dtb \
armada-xp-db.dtb \
armada-xp-openblocks-ax3-4.dtb
-dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
+dtb-$(CONFIG_ARCH_MXC) += imx51-apf51.dtb \
+ imx51-babbage.dtb \
imx53-ard.dtb \
imx53-evk.dtb \
imx53-qsb.dtb \
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
new file mode 100644
index 0000000..9239e07
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2012 Armadeus Systems - <support@armadeus.com>
+ * Copyright 2012 Laurent Cans <laurent.cans@gmail.com>
+ *
+ * Based on mx51-babbage.dts
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx51.dtsi"
+
+/ {
+ model = "Armadeus Systems APF51 module";
+ compatible = "fsl,imx51-apf51", "fsl,imx51";
+
+ memory {
+ reg = <0x90000000 0x20000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ckih1 {
+ clock-frequency = <0>;
+ };
+
+ osc {
+ clock-frequency = <33554432>;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_2>;
+ phy-mode = "mii";
+ phy-reset-gpios = <&gpio3 0 0>;
+ phy-reset-duration = <1>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_2>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 1f5d45e..8427279 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -273,6 +273,29 @@
260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
>;
};
+
+ pinctrl_fec_2: fecgrp-2 {
+ fsl,pins = <
+ 589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */
+ 592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */
+ 594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */
+ 596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */
+ 598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
+ 602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */
+ 604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
+ 609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
+ 618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
+ 623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
+ 628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
+ 634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
+ 639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */
+ 644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
+ 649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
+ 653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
+ 657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
+ 662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
+ >;
+ };
};
ecspi1 {
@@ -409,6 +432,13 @@
49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
>;
};
+
+ pinctrl_uart3_2: uart3grp-2 {
+ fsl,pins = <
+ 434 0x1c5 /* MX51_PAD_UART3_RXD__UART3_RXD */
+ 430 0x1c5 /* MX51_PAD_UART3_TXD__UART3_TXD */
+ >;
+ };
};
};
--
1.7.10.4
^ permalink raw reply related
* [PATCH 03/16] ARM: b.L: introduce helpers for platform coherency exit/setup
From: Catalin Marinas @ 2013-01-14 17:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130114170851.GA1967@linaro.org>
On Mon, Jan 14, 2013 at 05:08:51PM +0000, Dave Martin wrote:
> From b64f305c90e7ea585992df2d710f62ec6a7b5395 Mon Sep 17 00:00:00 2001
> From: Dave Martin <dave.martin@linaro.org>
> Date: Mon, 14 Jan 2013 16:25:47 +0000
> Subject: [PATCH] ARM: b.L: Fix outer cache handling for coherency setup/exit helpers
>
> This patch addresses the following issues:
>
> * When invalidating stale data from the cache before a read,
> outer caches must be invalidated _before_ inner caches, not
> after, otherwise stale data may be re-filled from outer to
> inner after the inner cache is flushed.
>
> We still retain an inner clean before touching the outer cache,
> to avoid stale data being rewritten from there into the outer
> cache after the outer cache is flushed.
>
> * All the sync_mem() calls synchronise either reads or writes,
> but not both. This patch splits sync_mem() into separate
> functions for reads and writes, to avoid excessive inner
> flushes in the write case.
>
> The two functions are different from the original sync_mem(),
> to fix the above issues.
>
> Signed-off-by: Dave Martin <dave.martin@linaro.org>
> ---
> NOTE: This patch is build-tested only.
>
> arch/arm/common/bL_entry.c | 57 ++++++++++++++++++++++++++++++++++----------
> 1 files changed, 44 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/common/bL_entry.c b/arch/arm/common/bL_entry.c
> index 1ea4ec9..3e1a404 100644
> --- a/arch/arm/common/bL_entry.c
> +++ b/arch/arm/common/bL_entry.c
> @@ -119,16 +119,47 @@ int bL_cpu_powered_up(void)
>
> struct bL_sync_struct bL_sync;
>
> -static void __sync_range(volatile void *p, size_t size)
> +/*
> + * Ensure preceding writes to *p by this CPU are visible to
> + * subsequent reads by other CPUs:
> + */
> +static void __sync_range_w(volatile void *p, size_t size)
> {
> char *_p = (char *)p;
>
> __cpuc_flush_dcache_area(_p, size);
> - outer_flush_range(__pa(_p), __pa(_p + size));
> + outer_clean_range(__pa(_p), __pa(_p + size));
> outer_sync();
It's not part of your patch but I thought about commenting here. The
outer_clean_range() already has a cache_sync() operation, so no need for
the additional outer_sync().
> }
>
> -#define sync_mem(ptr) __sync_range(ptr, sizeof *(ptr))
> +/*
> + * Ensure preceding writes to *p by other CPUs are visible to
> + * subsequent reads by this CPU:
> + */
> +static void __sync_range_r(volatile void *p, size_t size)
> +{
> + char *_p = (char *)p;
> +
> +#ifdef CONFIG_OUTER_CACHE
> + if (outer_cache.flush_range) {
> + /*
> + * Ensure ditry data migrated from other CPUs into our cache
> + * are cleaned out safely before the outer cache is cleaned:
> + */
> + __cpuc_flush_dcache_area(_p, size);
> +
> + /* Clean and invalidate stale data for *p from outer ... */
> + outer_flush_range(__pa(_p), __pa(_p + size));
> + outer_sync();
Same here.
--
Catalin
^ permalink raw reply
* [PATCH 07/16] ARM: bL_platsmp.c: close the kernel entry gate before hot-unplugging a CPU
From: Nicolas Pitre @ 2013-01-14 17:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130114170028.GD31341@mudshark.cambridge.arm.com>
On Mon, 14 Jan 2013, Will Deacon wrote:
> On Mon, Jan 14, 2013 at 04:53:41PM +0000, Nicolas Pitre wrote:
> > On Mon, 14 Jan 2013, Will Deacon wrote:
> >
> > > On Thu, Jan 10, 2013 at 12:20:42AM +0000, Nicolas Pitre wrote:
> > > > If for whatever reason a CPU is unexpectedly awaken, it shouldn't
> > > > re-enter the kernel by using whatever entry vector that might have
> > > > been set by a previous operation.
> > > >
> > > > Signed-off-by: Nicolas Pitre <nico@linaro.org>
> > > > ---
> > > > arch/arm/common/bL_platsmp.c | 5 +++++
> > > > 1 file changed, 5 insertions(+)
> > > >
> > > > diff --git a/arch/arm/common/bL_platsmp.c b/arch/arm/common/bL_platsmp.c
> > > > index 0acb9f4685..0ae44123bf 100644
> > > > --- a/arch/arm/common/bL_platsmp.c
> > > > +++ b/arch/arm/common/bL_platsmp.c
> > > > @@ -63,6 +63,11 @@ static int bL_cpu_disable(unsigned int cpu)
> > > >
> > > > static void __ref bL_cpu_die(unsigned int cpu)
> > > > {
> > > > + unsigned int mpidr, pcpu, pcluster;
> > > > + asm ("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> > > > + pcpu = mpidr & 0xff;
> > > > + pcluster = (mpidr >> 8) & 0xff;
> > >
> > > Usual comment about helper functions :)
> > >
> > > > + bL_set_entry_vector(pcpu, pcluster, NULL);
> > >
> > > Similar to the power_on story, you need a barrier here (unless you change
> > > your platform_ops API to require barriers).
> >
> > The bL_set_entry_vector() includes a cache flush which itself has a DSB.
> > Hence my previous interrogation.
>
> For L1, sure, we always have the dsb for v7. However, for the outer-cache we
> only have a dsb by virtue of a spin_unlock in l2x0.c... it seems a bit risky
> to rely on that for ordering your entry_vector write with the power_on.
>
> I think the best bet is to put a barrier in power_on, before invoking the
> platform_ops function and similarly for power_off.
>
> What do you reckon?
I much prefer adding barriers inside the API when they are needed for
proper execution of the API intent. So if I call bL_set_entry_vector(),
I trust that by the time it returns the vector is indeed set and ready
for use by other processors.
The same could be said about the outer cache ops. If a DSB is needed
for their intent to be valid, then why isn't this DSB always implied by
the corresponding cache op calls? And as you say, there is already one
implied by the spinlock used there, so that is not if things would
change much in practice.
Nicolas
^ permalink raw reply
* [PATCH 07/16] ARM: bL_platsmp.c: close the kernel entry gate before hot-unplugging a CPU
From: Catalin Marinas @ 2013-01-14 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130114170028.GD31341@mudshark.cambridge.arm.com>
On Mon, Jan 14, 2013 at 05:00:28PM +0000, Will Deacon wrote:
> On Mon, Jan 14, 2013 at 04:53:41PM +0000, Nicolas Pitre wrote:
> > On Mon, 14 Jan 2013, Will Deacon wrote:
> >
> > > On Thu, Jan 10, 2013 at 12:20:42AM +0000, Nicolas Pitre wrote:
> > > > If for whatever reason a CPU is unexpectedly awaken, it shouldn't
> > > > re-enter the kernel by using whatever entry vector that might have
> > > > been set by a previous operation.
> > > >
> > > > Signed-off-by: Nicolas Pitre <nico@linaro.org>
> > > > ---
> > > > arch/arm/common/bL_platsmp.c | 5 +++++
> > > > 1 file changed, 5 insertions(+)
> > > >
> > > > diff --git a/arch/arm/common/bL_platsmp.c b/arch/arm/common/bL_platsmp.c
> > > > index 0acb9f4685..0ae44123bf 100644
> > > > --- a/arch/arm/common/bL_platsmp.c
> > > > +++ b/arch/arm/common/bL_platsmp.c
> > > > @@ -63,6 +63,11 @@ static int bL_cpu_disable(unsigned int cpu)
> > > >
> > > > static void __ref bL_cpu_die(unsigned int cpu)
> > > > {
> > > > + unsigned int mpidr, pcpu, pcluster;
> > > > + asm ("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> > > > + pcpu = mpidr & 0xff;
> > > > + pcluster = (mpidr >> 8) & 0xff;
> > >
> > > Usual comment about helper functions :)
> > >
> > > > + bL_set_entry_vector(pcpu, pcluster, NULL);
> > >
> > > Similar to the power_on story, you need a barrier here (unless you change
> > > your platform_ops API to require barriers).
> >
> > The bL_set_entry_vector() includes a cache flush which itself has a DSB.
> > Hence my previous interrogation.
>
> For L1, sure, we always have the dsb for v7. However, for the outer-cache we
> only have a dsb by virtue of a spin_unlock in l2x0.c... it seems a bit risky
> to rely on that for ordering your entry_vector write with the power_on.
I was discussing this with Dave earlier, I think we need to fix the
outer-cache functions even for the UP case to include a barrier (for
PL310 actually we may need to read a register as the cache_wait is a
no-op). We assume that cache functions (both inner and outer) fully
complete the operation before returning and there is no additional need
for barriers.
--
Catalin
^ permalink raw reply
* [PATCH v5 02/14] ARM: Section based HYP idmap
From: Christoffer Dall @ 2013-01-14 17:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130114161337.GE23505@n2100.arm.linux.org.uk>
On Mon, Jan 14, 2013 at 11:13 AM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Tue, Jan 08, 2013 at 01:38:48PM -0500, Christoffer Dall wrote:
>> + pr_info("Setting up static %sidentity map for 0x%llx - 0x%llx\n",
>> + prot ? "HYP " : "",
>> + (long long)addr, (long long)end);
>
> There's no point using 0x%llx and casting to 64-bit longs if the arguments
> are always going to be 32-bit.
true, that's silly. This should improve the code, suggested by Will:
commit 1baa03f3d70f082e4522fd32db09e4f5542ff48d
Author: Christoffer Dall <c.dall@virtualopensystems.com>
Date: Mon Jan 14 12:06:26 2013 -0500
ARM: idmap: cleanup pr_info
It's cleaner to simply print the info messages in the callers and
there's no reason to convert 32-bit values to 64-bit values.
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index d9213a5..b9ae344 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -71,9 +71,6 @@ static void identity_mapping_add(pgd_t *pgd, const
char *text_start,
addr = virt_to_phys(text_start);
end = virt_to_phys(text_end);
- pr_info("Setting up static %sidentity map for 0x%llx - 0x%llx\n",
- prot ? "HYP " : "",
- (long long)addr, (long long)end);
prot |= PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF;
if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
@@ -97,6 +94,8 @@ static int __init init_static_idmap_hyp(void)
if (!hyp_pgd)
return -ENOMEM;
+ pr_info("Setting up static HYP identity map for 0x%p - 0x%p\n",
+ __hyp_idmap_text_start, __hyp_idmap_text_end);
identity_mapping_add(hyp_pgd, __hyp_idmap_text_start,
__hyp_idmap_text_end, PMD_SECT_AP1);
@@ -119,6 +118,8 @@ static int __init init_static_idmap(void)
if (!idmap_pgd)
return -ENOMEM;
+ pr_info("Setting up static identity map for 0x%p - 0x%p\n",
+ __idmap_text_start, __idmap_text_end);
identity_mapping_add(idmap_pgd, __idmap_text_start,
__idmap_text_end, 0);
--
-Christoffer
^ permalink raw reply related
* [PATCH 03/16] ARM: b.L: introduce helpers for platform coherency exit/setup
From: Dave Martin @ 2013-01-14 17:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357777251-13541-4-git-send-email-nicolas.pitre@linaro.org>
On Wed, Jan 09, 2013 at 07:20:38PM -0500, Nicolas Pitre wrote:
> From: Dave Martin <dave.martin@linaro.org>
>
> This provides helper methods to coordinate between CPUs coming down
> and CPUs going up, as well as documentation on the used algorithms,
> so that cluster teardown and setup
> operations are not done for a cluster simultaneously.
[...]
In response to the incorrectness of the outer cache handling,
here's a supplementary patch:
>From b64f305c90e7ea585992df2d710f62ec6a7b5395 Mon Sep 17 00:00:00 2001
From: Dave Martin <dave.martin@linaro.org>
Date: Mon, 14 Jan 2013 16:25:47 +0000
Subject: [PATCH] ARM: b.L: Fix outer cache handling for coherency setup/exit helpers
This patch addresses the following issues:
* When invalidating stale data from the cache before a read,
outer caches must be invalidated _before_ inner caches, not
after, otherwise stale data may be re-filled from outer to
inner after the inner cache is flushed.
We still retain an inner clean before touching the outer cache,
to avoid stale data being rewritten from there into the outer
cache after the outer cache is flushed.
* All the sync_mem() calls synchronise either reads or writes,
but not both. This patch splits sync_mem() into separate
functions for reads and writes, to avoid excessive inner
flushes in the write case.
The two functions are different from the original sync_mem(),
to fix the above issues.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
NOTE: This patch is build-tested only.
arch/arm/common/bL_entry.c | 57 ++++++++++++++++++++++++++++++++++----------
1 files changed, 44 insertions(+), 13 deletions(-)
diff --git a/arch/arm/common/bL_entry.c b/arch/arm/common/bL_entry.c
index 1ea4ec9..3e1a404 100644
--- a/arch/arm/common/bL_entry.c
+++ b/arch/arm/common/bL_entry.c
@@ -119,16 +119,47 @@ int bL_cpu_powered_up(void)
struct bL_sync_struct bL_sync;
-static void __sync_range(volatile void *p, size_t size)
+/*
+ * Ensure preceding writes to *p by this CPU are visible to
+ * subsequent reads by other CPUs:
+ */
+static void __sync_range_w(volatile void *p, size_t size)
{
char *_p = (char *)p;
__cpuc_flush_dcache_area(_p, size);
- outer_flush_range(__pa(_p), __pa(_p + size));
+ outer_clean_range(__pa(_p), __pa(_p + size));
outer_sync();
}
-#define sync_mem(ptr) __sync_range(ptr, sizeof *(ptr))
+/*
+ * Ensure preceding writes to *p by other CPUs are visible to
+ * subsequent reads by this CPU:
+ */
+static void __sync_range_r(volatile void *p, size_t size)
+{
+ char *_p = (char *)p;
+
+#ifdef CONFIG_OUTER_CACHE
+ if (outer_cache.flush_range) {
+ /*
+ * Ensure ditry data migrated from other CPUs into our cache
+ * are cleaned out safely before the outer cache is cleaned:
+ */
+ __cpuc_flush_dcache_area(_p, size);
+
+ /* Clean and invalidate stale data for *p from outer ... */
+ outer_flush_range(__pa(_p), __pa(_p + size));
+ outer_sync();
+ }
+#endif
+
+ /* ... and inner cache: */
+ __cpuc_flush_dcache_area(_p, size);
+}
+
+#define sync_w(ptr) __sync_range_w(ptr, sizeof *(ptr))
+#define sync_r(ptr) __sync_range_r(ptr, sizeof *(ptr))
/*
* __bL_cpu_going_down: Indicates that the cpu is being torn down.
@@ -138,7 +169,7 @@ static void __sync_range(volatile void *p, size_t size)
void __bL_cpu_going_down(unsigned int cpu, unsigned int cluster)
{
bL_sync.clusters[cluster].cpus[cpu].cpu = CPU_GOING_DOWN;
- sync_mem(&bL_sync.clusters[cluster].cpus[cpu].cpu);
+ sync_w(&bL_sync.clusters[cluster].cpus[cpu].cpu);
}
/*
@@ -151,7 +182,7 @@ void __bL_cpu_down(unsigned int cpu, unsigned int cluster)
{
dsb();
bL_sync.clusters[cluster].cpus[cpu].cpu = CPU_DOWN;
- sync_mem(&bL_sync.clusters[cluster].cpus[cpu].cpu);
+ sync_w(&bL_sync.clusters[cluster].cpus[cpu].cpu);
sev();
}
@@ -167,7 +198,7 @@ void __bL_outbound_leave_critical(unsigned int cluster, int state)
{
dsb();
bL_sync.clusters[cluster].cluster = state;
- sync_mem(&bL_sync.clusters[cluster].cluster);
+ sync_w(&bL_sync.clusters[cluster].cluster);
sev();
}
@@ -189,10 +220,10 @@ bool __bL_outbound_enter_critical(unsigned int cpu, unsigned int cluster)
/* Warn inbound CPUs that the cluster is being torn down: */
c->cluster = CLUSTER_GOING_DOWN;
- sync_mem(&c->cluster);
+ sync_w(&c->cluster);
/* Back out if the inbound cluster is already in the critical region: */
- sync_mem(&c->inbound);
+ sync_r(&c->inbound);
if (c->inbound == INBOUND_COMING_UP)
goto abort;
@@ -203,7 +234,7 @@ bool __bL_outbound_enter_critical(unsigned int cpu, unsigned int cluster)
* If any CPU has been woken up again from the DOWN state, then we
* shouldn't be taking the cluster down at all: abort in that case.
*/
- sync_mem(&c->cpus);
+ sync_r(&c->cpus);
for (i = 0; i < BL_CPUS_PER_CLUSTER; i++) {
int cpustate;
@@ -216,7 +247,7 @@ bool __bL_outbound_enter_critical(unsigned int cpu, unsigned int cluster)
break;
wfe();
- sync_mem(&c->cpus[i].cpu);
+ sync_r(&c->cpus[i].cpu);
}
switch (cpustate) {
@@ -239,7 +270,7 @@ abort:
int __bL_cluster_state(unsigned int cluster)
{
- sync_mem(&bL_sync.clusters[cluster].cluster);
+ sync_r(&bL_sync.clusters[cluster].cluster);
return bL_sync.clusters[cluster].cluster;
}
@@ -267,11 +298,11 @@ int __init bL_cluster_sync_init(void (*power_up_setup)(void))
for_each_online_cpu(i)
bL_sync.clusters[this_cluster].cpus[i].cpu = CPU_UP;
bL_sync.clusters[this_cluster].cluster = CLUSTER_UP;
- sync_mem(&bL_sync);
+ sync_w(&bL_sync);
if (power_up_setup) {
bL_power_up_setup_phys = virt_to_phys(power_up_setup);
- sync_mem(&bL_power_up_setup_phys);
+ sync_w(&bL_power_up_setup_phys);
}
return 0;
--
1.7.4.1
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