* [GIT PULL v3] Renesas ARM-based SoC defconfig for v3.9
From: Simon Horman @ 2013-01-16 6:02 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Arnd,
please consider the following defconfig enhancements for 3.9.
----------------------------------------------------------------
The following changes since commit a49f0d1ea3ec94fc7cf33a7c36a16343b74bd565:
Linux 3.8-rc1 (2012-12-21 17:19:00 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git defconfig
for you to fetch changes up to 8098df15c26b2bf16924df5a134d1a649692ab62:
ARM: mach-shmobile: kzm9d: update defconfig (2013-01-15 08:57:09 +0900)
----------------------------------------------------------------
Simon Horman (5):
ARM: mach-shmobile: mackerel: update defconfig
ARM: mach-shmobile: fix memory size for kota2_defconfig
ARM: mach-shmobile: kzm9g: defconfig update
ARM: mach-shmobile: armadillo: update defconfig
ARM: mach-shmobile: kzm9d: update defconfig
arch/arm/boot/dts/emev2-kzm9d.dts | 2 +-
arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 4 ++++
arch/arm/boot/dts/sh7372-mackerel.dts | 4 ++++
arch/arm/boot/dts/sh73a0-kzm9g.dts | 4 ++++
arch/arm/configs/armadillo800eva_defconfig | 5 ++---
arch/arm/configs/kota2_defconfig | 2 +-
arch/arm/configs/kzm9d_defconfig | 4 +---
arch/arm/configs/kzm9g_defconfig | 4 +++-
arch/arm/configs/mackerel_defconfig | 2 +-
9 files changed, 21 insertions(+), 10 deletions(-)
^ permalink raw reply
* [RFC PATCH 0/7] usb: musb: add driver for control module
From: kishon @ 2013-01-16 6:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6C6B28D4DC342643927BEAFCE8707BF63EA5ACAB@DBDE01.ent.ti.com>
Hi Ravi,
On Tuesday 15 January 2013 09:36 PM, B, Ravi wrote:
>> Hi,
>>
>> On Tue, Jan 15, 2013 at 08:09:22PM +0530, kishon wrote:
>>> Hi Arnd,
>>>
>>> On Tuesday 15 January 2013 07:11 PM, Arnd Bergmann wrote:
>>>> On Tuesday 15 January 2013, Kishon Vijay Abraham I wrote:
>>>>> Added a new driver for the usb part of control module.
>> This has an
>>>>> API to power on the USB2 phy and an API to write to the mailbox
>>>>> depending on whether MUSB has to act in host mode or in
>> device mode.
>>>>>
>>>>> Writing to control module registers for doing the above
>> task which
>>>>> was previously done in omap glue and in omap-usb2 phy is removed.
>>>>>
>>>>> Also added the dt data to get MUSB working in OMAP platforms.
>>>>> This series has patches for both drivers and ARCH
>> folders, so If it
>>>>> has to be split I'll do it.
>>>>>
>>>>
>>>> The series looks good to me, I just had a minor comment on
>> one patch.
>>>>
>>>> One a somewhat related topic, I wonder whether there are
>> any plans on
>>>> your side to change this driver to support multiple bus
>> glues to be
>>>> built for one kernel image. With a multiplatform kernel,
>> we may need
>>>> all of TUSB6010/OMAP2PLUS/DSPS/UX500 for instance.
>>>
>>> We don't have plans as of now. I actually don't expect any
>> changes in
>>> the driver other than the Kconfig changes. Anyways the
>> probe of glue's
>>> other than the platform it's running won't get called. right Felipe?
>
> If understand correctly the control module driver used to configure the respective usb phy of SoC to respective usb modes using the common set of control module APIs.
What if, if control module interface (register defintions) varies b/w
different revision or spin of same type of SoCs, if usbphy type is changed.
Well in that case, we can write to the registers based on the IP
revision check (I think thats the common practice to do).
In this case whether the single instance of control module driver is
good enough to cater of all cpu types of same SoC series ?
Of course. I don't see why we can't have the same driver to handle
different versions of the same IP.
The only reason where we might need multiple instance is if the SoC have
multiple control module which Arnd already pointed out.
> Whether cpu_is_xxx() can be used to differentiate b/w different cpu types in CM driver?
Not needed at all IMHO. We can use revision register to differentiate.
Btw I think Felipe looped you for a different reason ;-)
Thanks
Kishon
^ permalink raw reply
* [PATCH v2 9/9] ARM: PRIMA2: provide two DEBUG_LL ports for prima2 and marco
From: Barry Song @ 2013-01-16 5:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358315784-25104-1-git-send-email-Barry.Song@csr.com>
From: Barry Song <Baohua.Song@csr.com>
prima2 and marco has different memory base, the old code will
fail if we enable DEBUG_LL in marco.
this patch adds two debuf port, while debugging, we select one
of PRIMA2 and MARCO debug ports, in the products, we disable
DEBUG_LL.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
---
arch/arm/Kconfig.debug | 14 ++++++++++++++
arch/arm/mach-prima2/include/mach/uart.h | 6 ++++++
arch/arm/mach-prima2/include/mach/uncompress.h | 3 +++
3 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 661030d..00ad1f8 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -386,6 +386,20 @@ choice
Say Y here if you want kernel low-level debugging support
on Tegra based platforms.
+ config DEBUG_SIRFPRIMA2_UART1
+ bool "Kernel low-level debugging messages via SiRFprimaII UART1"
+ depends on ARCH_PRIMA2
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the uart1 port on SiRFprimaII devices.
+
+ config DEBUG_SIRFMARCO_UART1
+ bool "Kernel low-level debugging messages via SiRFmarco UART1"
+ depends on ARCH_MARCO
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the uart1 port on SiRFmarco devices.
+
config DEBUG_VEXPRESS_UART0_DETECT
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
depends on ARCH_VEXPRESS && CPU_CP15_MMU
diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/mach-prima2/include/mach/uart.h
index c98b4d5..c10510d 100644
--- a/arch/arm/mach-prima2/include/mach/uart.h
+++ b/arch/arm/mach-prima2/include/mach/uart.h
@@ -10,7 +10,13 @@
#define __MACH_PRIMA2_SIRFSOC_UART_H
/* UART-1: used as serial debug port */
+#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
#define SIRFSOC_UART1_PA_BASE 0xb0060000
+#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
+#define SIRFSOC_UART1_PA_BASE 0xcc060000
+#else
+#define SIRFSOC_UART1_PA_BASE 0
+#endif
#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000)
#define SIRFSOC_UART1_SIZE SZ_4K
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
index 0c898fc..15f3edc 100644
--- a/arch/arm/mach-prima2/include/mach/uncompress.h
+++ b/arch/arm/mach-prima2/include/mach/uncompress.h
@@ -25,6 +25,9 @@ static __inline__ void putc(char c)
* during kernel decompression, all mappings are flat:
* virt_addr == phys_addr
*/
+ if (!SIRFSOC_UART1_PA_BASE)
+ return;
+
while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
& SIRFSOC_UART1_TXFIFO_FULL)
barrier();
--
1.7.5.4
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
^ permalink raw reply related
* [PATCH v2 8/9] ARM: PRIMA2: add new SiRFmarco SMP SoC infrastructures
From: Barry Song @ 2013-01-16 5:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358315784-25104-1-git-send-email-Barry.Song@csr.com>
From: Barry Song <Baohua.Song@csr.com>
this patch adds tick timer, smp entries and generic DT machine
for SiRFmarco dual-core SMP chips.
with the added marco, we change the defconfig, using the same
defconfig, we get a zImage which can work on both prima2 and
marco.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/configs/prima2_defconfig | 3 +
arch/arm/mach-prima2/Kconfig | 10 +
arch/arm/mach-prima2/Makefile | 3 +
arch/arm/mach-prima2/common.c | 40 ++++-
arch/arm/mach-prima2/common.h | 11 +
arch/arm/mach-prima2/headsmp.S | 79 ++++++++
arch/arm/mach-prima2/hotplug.c | 41 ++++
arch/arm/mach-prima2/platsmp.c | 170 +++++++++++++++++
arch/arm/mach-prima2/timer-marco.c | 355 ++++++++++++++++++++++++++++++++++++
10 files changed, 712 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-prima2/headsmp.S
create mode 100644 arch/arm/mach-prima2/hotplug.c
create mode 100644 arch/arm/mach-prima2/platsmp.c
create mode 100644 arch/arm/mach-prima2/timer-marco.c
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e44da40..6af9901 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
kirkwood-ts219-6281.dtb \
kirkwood-ts219-6282.dtb \
kirkwood-openblocks_a6.dtb
+dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
msm8960-cdp.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
index 6a936c7..002a1ce 100644
--- a/arch/arm/configs/prima2_defconfig
+++ b/arch/arm/configs/prima2_defconfig
@@ -11,6 +11,9 @@ CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_ARCH_SIRF=y
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SMP=y
+CONFIG_SCHED_MC=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_KEXEC=y
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 558ccfb..4f7379f 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -11,6 +11,16 @@ config ARCH_PRIMA2
help
Support for CSR SiRFSoC ARM Cortex A9 Platform
+config ARCH_MARCO
+ bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
+ default y
+ select ARM_GIC
+ select CPU_V7
+ select HAVE_SMP
+ select SMP_ON_UP
+ help
+ Support for CSR SiRFSoC ARM Cortex A9 Platform
+
endmenu
config SIRF_IRQ
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 0007a6e..bfe360c 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -5,4 +5,7 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
obj-$(CONFIG_CACHE_L2X0) += l2x0.o
obj-$(CONFIG_SUSPEND) += pm.o sleep.o
obj-$(CONFIG_SIRF_IRQ) += irq.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
+obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 99f9c7e..00a6564 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -8,9 +8,11 @@
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/of_irq.h>
#include <asm/sizes.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include "common.h"
@@ -30,6 +32,12 @@ void __init sirfsoc_init_late(void)
sirfsoc_pm_init();
}
+static __init void sirfsoc_map_io(void)
+{
+ sirfsoc_map_lluart();
+ sirfsoc_map_scu();
+}
+
#ifdef CONFIG_ARCH_PRIMA2
static const char *prima2_dt_match[] __initdata = {
"sirf,prima2",
@@ -38,7 +46,7 @@ static const char *prima2_dt_match[] __initdata = {
DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
- .map_io = sirfsoc_map_lluart,
+ .map_io = sirfsoc_map_io,
.init_irq = sirfsoc_of_irq_init,
.init_time = sirfsoc_prima2_timer_init,
#ifdef CONFIG_MULTI_IRQ_HANDLER
@@ -51,3 +59,33 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
.restart = sirfsoc_restart,
MACHINE_END
#endif
+
+#ifdef CONFIG_ARCH_MARCO
+static const struct of_device_id marco_irq_match[] __initconst = {
+ { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+ { /* sentinel */ }
+};
+
+static void __init marco_init_irq(void)
+{
+ of_irq_init(marco_irq_match);
+}
+
+static const char *marco_dt_match[] __initdata = {
+ "sirf,marco",
+ NULL
+};
+
+DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
+ /* Maintainer: Barry Song <baohua.song@csr.com> */
+ .smp = smp_ops(sirfsoc_smp_ops),
+ .map_io = sirfsoc_map_io,
+ .init_irq = marco_init_irq,
+ .init_time = sirfsoc_marco_timer_init,
+ .handle_irq = gic_handle_irq,
+ .init_machine = sirfsoc_mach_init,
+ .init_late = sirfsoc_init_late,
+ .dt_compat = marco_dt_match,
+ .restart = sirfsoc_restart,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index a4f91a6..b7c26b6 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -14,6 +14,11 @@
#include <asm/exception.h>
extern void sirfsoc_prima2_timer_init(void);
+extern void sirfsoc_marco_timer_init(void);
+
+extern struct smp_operations sirfsoc_smp_ops;
+extern void sirfsoc_secondary_startup(void);
+extern void sirfsoc_cpu_die(unsigned int cpu);
extern void __init sirfsoc_of_irq_init(void);
extern void __init sirfsoc_of_clk_init(void);
@@ -26,6 +31,12 @@ static inline void sirfsoc_map_lluart(void) {}
extern void __init sirfsoc_map_lluart(void);
#endif
+#ifndef CONFIG_SMP
+static inline void sirfsoc_map_scu(void) {}
+#else
+extern void sirfsoc_map_scu(void);
+#endif
+
#ifdef CONFIG_SUSPEND
extern int sirfsoc_pm_init(void);
#else
diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
new file mode 100644
index 0000000..6ec19d5
--- /dev/null
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -0,0 +1,79 @@
+/*
+ * Entry of the second core for CSR Marco dual-core SMP SoCs
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ __INIT
+/*
+ * Cold boot and hardware reset show different behaviour,
+ * system will be always panic if we warm-reset the board
+ * Here we invalidate L1 of CPU1 to make sure there isn't
+ * uninitialized data written into memory later
+ */
+ENTRY(v7_invalidate_l1)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mcr p15, 2, r0, c0, c0, 0
+ mrc p15, 1, r0, c0, c0, 0
+
+ ldr r1, =0x7fff
+ and r2, r1, r0, lsr #13
+
+ ldr r1, =0x3ff
+
+ and r3, r1, r0, lsr #3 @ NumWays - 1
+ add r2, r2, #1 @ NumSets
+
+ and r0, r0, #0x7
+ add r0, r0, #4 @ SetShift
+
+ clz r1, r3 @ WayShift
+ add r4, r3, #1 @ NumWays
+1: sub r2, r2, #1 @ NumSets--
+ mov r3, r4 @ Temp = NumWays
+2: subs r3, r3, #1 @ Temp--
+ mov r5, r3, lsl r1
+ mov r6, r2, lsl r0
+ orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+ mcr p15, 0, r5, c7, c6, 2
+ bgt 2b
+ cmp r2, #0
+ bgt 1b
+ dsb
+ isb
+ mov pc, lr
+ENDPROC(v7_invalidate_l1)
+
+/*
+ * SIRFSOC specific entry point for secondary CPUs. This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(sirfsoc_secondary_startup)
+ bl v7_invalidate_l1
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #15
+ adr r4, 1f
+ ldmia r4, {r5, r6}
+ sub r4, r4, r5
+ add r6, r6, r4
+pen: ldr r7, [r6]
+ cmp r7, r0
+ bne pen
+
+ /*
+ * we've been released from the holding pen: secondary_stack
+ * should now contain the SVC stack for this core
+ */
+ b secondary_startup
+ENDPROC(sirfsoc_secondary_startup)
+
+ .align
+1: .long .
+ .long pen_release
diff --git a/arch/arm/mach-prima2/hotplug.c b/arch/arm/mach-prima2/hotplug.c
new file mode 100644
index 0000000..97c1ee5
--- /dev/null
+++ b/arch/arm/mach-prima2/hotplug.c
@@ -0,0 +1,41 @@
+/*
+ * CPU hotplug support for CSR Marco dual-core SMP SoCs
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+
+static inline void platform_do_lowpower(unsigned int cpu)
+{
+ flush_cache_all();
+
+ /* we put the platform to just WFI */
+ for (;;) {
+ __asm__ __volatile__("dsb\n\t" "wfi\n\t"
+ : : : "memory");
+ if (pen_release == cpu_logical_map(cpu)) {
+ /*
+ * OK, proper wakeup, we're done
+ */
+ break;
+ }
+ }
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void sirfsoc_cpu_die(unsigned int cpu)
+{
+ platform_do_lowpower(cpu);
+}
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
new file mode 100644
index 0000000..b939e9b4
--- /dev/null
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -0,0 +1,170 @@
+/*
+ * plat smp support for CSR Marco dual-core SMP SoCs
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/hardware/gic.h>
+#include <mach/map.h>
+
+#include "common.h"
+
+static void __iomem *scu_base;
+static void __iomem *rsc_base;
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static struct map_desc scu_io_desc __initdata = {
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+};
+
+void __init sirfsoc_map_scu(void)
+{
+ unsigned long base;
+
+ /* Get SCU base */
+ asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+ scu_io_desc.virtual = SIRFSOC_VA(base);
+ scu_io_desc.pfn = __phys_to_pfn(base);
+ iotable_init(&scu_io_desc, 1);
+
+ scu_base = (void __iomem *)SIRFSOC_VA(base);
+}
+
+static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
+{
+ /*
+ * if any interrupts are already enabled for the primary
+ * core (e.g. timer irq), then they will not have been enabled
+ * for us: do so
+ */
+ gic_secondary_init(0);
+
+ /*
+ * let the primary processor know we're out of the
+ * pen, then head off into the C entry point
+ */
+ pen_release = -1;
+ smp_wmb();
+
+ /*
+ * Synchronise with the boot thread.
+ */
+ spin_lock(&boot_lock);
+ spin_unlock(&boot_lock);
+}
+
+static struct of_device_id rsc_ids[] = {
+ { .compatible = "sirf,marco-rsc" },
+ {},
+};
+
+static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ unsigned long timeout;
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, rsc_ids);
+ if (!np)
+ return -ENODEV;
+
+ rsc_base = of_iomap(np, 0);
+ if (!rsc_base)
+ return -ENOMEM;
+
+ /*
+ * write the address of secondary startup into the sram register
+ * at offset 0x2C, then write the magic number 0x3CAF5D62 to the
+ * RSC register at offset 0x28, which is what boot rom code is
+ * waiting for. This would wake up the secondary core from WFE
+ */
+#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C
+ __raw_writel(virt_to_phys(sirfsoc_secondary_startup),
+ rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
+
+#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28
+ __raw_writel(0x3CAF5D62,
+ rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
+
+ /* make sure write buffer is drained */
+ mb();
+
+ spin_lock(&boot_lock);
+
+ /*
+ * The secondary processor is waiting to be released from
+ * the holding pen - release it, then wait for it to flag
+ * that it has been released by resetting pen_release.
+ *
+ * Note that "pen_release" is the hardware CPU ID, whereas
+ * "cpu" is Linux's internal ID.
+ */
+ pen_release = cpu_logical_map(cpu);
+ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+
+ /*
+ * Send the secondary CPU SEV, thereby causing the boot monitor to read
+ * the JUMPADDR and WAKEMAGIC, and branch to the address found there.
+ */
+ dsb_sev();
+
+ timeout = jiffies + (1 * HZ);
+ while (time_before(jiffies, timeout)) {
+ smp_rmb();
+ if (pen_release == -1)
+ break;
+
+ udelay(10);
+ }
+
+ /*
+ * now the secondary core is starting up let it run its
+ * calibrations, then wait for it to finish
+ */
+ spin_unlock(&boot_lock);
+
+ return pen_release != -1 ? -ENOSYS : 0;
+}
+
+static void __init sirfsoc_smp_init_cpus(void)
+{
+ int i, ncores;
+
+ ncores = scu_get_core_count(scu_base);
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
+}
+
+static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus)
+{
+ scu_enable(scu_base);
+}
+
+struct smp_operations sirfsoc_smp_ops __initdata = {
+ .smp_init_cpus = sirfsoc_smp_init_cpus,
+ .smp_prepare_cpus = sirfsoc_smp_prepare_cpus,
+ .smp_secondary_init = sirfsoc_secondary_init,
+ .smp_boot_secondary = sirfsoc_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = sirfsoc_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-prima2/timer-marco.c b/arch/arm/mach-prima2/timer-marco.c
new file mode 100644
index 0000000..07b3a6b
--- /dev/null
+++ b/arch/arm/mach-prima2/timer-marco.c
@@ -0,0 +1,355 @@
+/*
+ * System timer for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/bitops.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <asm/sched_clock.h>
+#include <asm/localtimer.h>
+#include <asm/mach/time.h>
+
+#include "common.h"
+
+#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000
+#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004
+#define SIRFSOC_TIMER_MATCH_0 0x0018
+#define SIRFSOC_TIMER_MATCH_1 0x001c
+#define SIRFSOC_TIMER_COUNTER_0 0x0048
+#define SIRFSOC_TIMER_COUNTER_1 0x004c
+#define SIRFSOC_TIMER_INTR_STATUS 0x0060
+#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064
+#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068
+#define SIRFSOC_TIMER_64COUNTER_LO 0x006c
+#define SIRFSOC_TIMER_64COUNTER_HI 0x0070
+#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074
+#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078
+#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c
+#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080
+
+#define SIRFSOC_TIMER_REG_CNT 6
+
+static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
+ SIRFSOC_TIMER_WATCHDOG_EN,
+ SIRFSOC_TIMER_32COUNTER_0_CTRL,
+ SIRFSOC_TIMER_32COUNTER_1_CTRL,
+ SIRFSOC_TIMER_64COUNTER_CTRL,
+ SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
+ SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
+};
+
+static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
+
+static void __iomem *sirfsoc_timer_base;
+static void __init sirfsoc_of_timer_map(void);
+
+/* disable count and interrupt */
+static inline void sirfsoc_timer_count_disable(int idx)
+{
+ writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
+ sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
+}
+
+/* enable count and interrupt */
+static inline void sirfsoc_timer_count_enable(int idx)
+{
+ writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
+ sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
+}
+
+/* timer0 interrupt handler */
+static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *ce = dev_id;
+
+ /* clear timer0 interrupt */
+ writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
+
+ if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
+ sirfsoc_timer_count_disable(0);
+
+ ce->event_handler(ce);
+
+ return IRQ_HANDLED;
+}
+
+/* read 64-bit timer counter */
+static cycle_t sirfsoc_timer_read(struct clocksource *cs)
+{
+ u64 cycles;
+
+ writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
+ BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+
+ cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
+ cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
+
+ return cycles;
+}
+
+static int sirfsoc_timer_set_next_event(unsigned long delta,
+ struct clock_event_device *ce)
+{
+
+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
+ writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
+
+ /* enable the tick */
+ sirfsoc_timer_count_enable(0);
+
+ return 0;
+}
+
+static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *ce)
+{
+ switch (mode) {
+ case CLOCK_EVT_MODE_ONESHOT:
+ /* enable in set_next_event */
+ break;
+ default:
+ break;
+ }
+
+ sirfsoc_timer_count_disable(0);
+}
+
+static void sirfsoc_clocksource_suspend(struct clocksource *cs)
+{
+ int i;
+
+ for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
+ sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
+}
+
+static void sirfsoc_clocksource_resume(struct clocksource *cs)
+{
+ int i;
+
+ for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
+ writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
+
+ writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
+ sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
+ writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
+ sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
+
+ writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
+ BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+}
+
+static struct clock_event_device sirfsoc_clockevent = {
+ .name = "sirfsoc_clockevent",
+ .rating = 200,
+ .features = CLOCK_EVT_FEAT_ONESHOT,
+ .set_mode = sirfsoc_timer_set_mode,
+ .set_next_event = sirfsoc_timer_set_next_event,
+};
+
+static struct clocksource sirfsoc_clocksource = {
+ .name = "sirfsoc_clocksource",
+ .rating = 200,
+ .mask = CLOCKSOURCE_MASK(64),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+ .read = sirfsoc_timer_read,
+ .suspend = sirfsoc_clocksource_suspend,
+ .resume = sirfsoc_clocksource_resume,
+};
+
+static struct irqaction sirfsoc_timer_irq = {
+ .name = "sirfsoc_timer0",
+ .flags = IRQF_TIMER | IRQF_NOBALANCING,
+ .handler = sirfsoc_timer_interrupt,
+ .dev_id = &sirfsoc_clockevent,
+};
+
+#ifdef CONFIG_LOCAL_TIMERS
+
+/* timer1 interrupt handler */
+static irqreturn_t sirfsoc_timer1_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *ce = dev_id;
+
+ /* clear timer1 interrupt */
+ writel_relaxed(BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
+
+ if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
+ sirfsoc_timer_count_disable(1);
+
+ ce->event_handler(ce);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction sirfsoc_timer1_irq = {
+ .name = "sirfsoc_timer1",
+ .flags = IRQF_TIMER | IRQF_NOBALANCING,
+ .handler = sirfsoc_timer1_interrupt,
+};
+
+static int sirfsoc_timer1_set_next_event(unsigned long delta,
+ struct clock_event_device *ce)
+{
+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
+ writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_1);
+
+ /* enable the tick */
+ sirfsoc_timer_count_enable(1);
+
+ return 0;
+}
+
+static void sirfsoc_timer1_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *ce)
+{
+ switch (mode) {
+ case CLOCK_EVT_MODE_ONESHOT:
+ /* enable in set_next_event */
+ break;
+ default:
+ break;
+ }
+
+ sirfsoc_timer_count_disable(1);
+}
+
+static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce)
+{
+ /* Use existing clock_event for cpu 0 */
+ if (!smp_processor_id())
+ return 0;
+
+ ce->irq = sirfsoc_timer1_irq.irq;
+ ce->name = "local_timer";
+ ce->features = sirfsoc_clockevent.features;
+ ce->rating = sirfsoc_clockevent.rating;
+ ce->cpumask = cpumask_of(1);
+ ce->set_mode = sirfsoc_timer1_set_mode;
+ ce->set_next_event = sirfsoc_timer1_set_next_event;
+ ce->shift = sirfsoc_clockevent.shift;
+ ce->mult = sirfsoc_clockevent.mult;
+ ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns;
+ ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns;
+
+ sirfsoc_timer1_irq.dev_id = ce;
+ BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq));
+ irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1));
+
+ clockevents_register_device(ce);
+ return 0;
+}
+
+static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
+{
+ sirfsoc_timer_count_disable(1);
+
+ remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
+}
+
+static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = {
+ .setup = sirfsoc_local_timer_setup,
+ .stop = sirfsoc_local_timer_stop,
+};
+#endif /* CONFIG_LOCAL_TIMERS */
+
+static void __init sirfsoc_clockevent_init(void)
+{
+ clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
+
+ sirfsoc_clockevent.max_delta_ns =
+ clockevent_delta2ns(-2, &sirfsoc_clockevent);
+ sirfsoc_clockevent.min_delta_ns =
+ clockevent_delta2ns(2, &sirfsoc_clockevent);
+
+ sirfsoc_clockevent.cpumask = cpumask_of(0);
+ clockevents_register_device(&sirfsoc_clockevent);
+#ifdef CONFIG_LOCAL_TIMERS
+ local_timer_register(&sirfsoc_local_timer_ops);
+#endif
+}
+
+/* initialize the kernel jiffy timer source */
+void __init sirfsoc_marco_timer_init(void)
+{
+ unsigned long rate;
+ u32 timer_div;
+ struct clk *clk;
+
+ /* initialize clocking early, we want to set the OS timer */
+ sirfsoc_of_clk_init();
+
+ /* timer's input clock is io clock */
+ clk = clk_get_sys("io", NULL);
+
+ BUG_ON(IS_ERR(clk));
+ rate = clk_get_rate(clk);
+
+ BUG_ON(rate < CLOCK_TICK_RATE);
+ BUG_ON(rate % CLOCK_TICK_RATE);
+
+ sirfsoc_of_timer_map();
+
+ /* Initialize the timer dividers */
+ timer_div = rate / CLOCK_TICK_RATE / 2 - 1;
+ writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+ writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
+ writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
+
+ /* Initialize timer counters to 0 */
+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
+ writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
+ BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
+
+ /* Clear all interrupts */
+ writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
+
+ BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
+
+ BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
+
+ sirfsoc_clockevent_init();
+}
+
+static struct of_device_id timer_ids[] = {
+ { .compatible = "sirf,marco-tick" },
+ {},
+};
+
+static void __init sirfsoc_of_timer_map(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, timer_ids);
+ if (!np)
+ return;
+ sirfsoc_timer_base = of_iomap(np, 0);
+ if (!sirfsoc_timer_base)
+ panic("unable to map timer cpu registers\n");
+
+ sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
+ if (!sirfsoc_timer_irq.irq)
+ panic("No irq passed for timer0 via DT\n");
+
+#ifdef CONFIG_LOCAL_TIMERS
+ sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
+ if (!sirfsoc_timer1_irq.irq)
+ panic("No irq passed for timer1 via DT\n");
+#endif
+
+ of_node_put(np);
+}
--
1.7.5.4
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog@www.csr.com/blog
^ permalink raw reply related
* [PATCH v2 7/9] ARM: PRIMA2: irq: make prima2 irq can work even we enable GIC for Marco
From: Barry Song @ 2013-01-16 5:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358315784-25104-1-git-send-email-Barry.Song@csr.com>
From: Barry Song <Baohua.Song@csr.com>
in Marco, we will use GIC. this patch prepares the handle_irq for prima2
to avoid the compiling errors since we want only one defconfig and zImage
for both prima2 and marco that means we will need handle_irq for both.
Signed-off-by: Baohua Song <Baohua.Song@csr.com>
---
arch/arm/mach-prima2/common.c | 3 +++
arch/arm/mach-prima2/common.h | 2 ++
arch/arm/mach-prima2/include/mach/irqs.h | 4 ++--
arch/arm/mach-prima2/irq.c | 16 ++++++++++++++--
4 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 8e6f668..99f9c7e 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -41,6 +41,9 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
.map_io = sirfsoc_map_lluart,
.init_irq = sirfsoc_of_irq_init,
.init_time = sirfsoc_prima2_timer_init,
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+ .handle_irq = sirfsoc_handle_irq,
+#endif
.dma_zone_size = SZ_256M,
.init_machine = sirfsoc_mach_init,
.init_late = sirfsoc_init_late,
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index d6890b6..a4f91a6 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -11,12 +11,14 @@
#include <linux/init.h>
#include <asm/mach/time.h>
+#include <asm/exception.h>
extern void sirfsoc_prima2_timer_init(void);
extern void __init sirfsoc_of_irq_init(void);
extern void __init sirfsoc_of_clk_init(void);
extern void sirfsoc_restart(char, const char *);
+extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
#ifndef CONFIG_DEBUG_LL
static inline void sirfsoc_map_lluart(void) {}
diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h
index f6014a0..b778a0f 100644
--- a/arch/arm/mach-prima2/include/mach/irqs.h
+++ b/arch/arm/mach-prima2/include/mach/irqs.h
@@ -10,8 +10,8 @@
#define __ASM_ARCH_IRQS_H
#define SIRFSOC_INTENAL_IRQ_START 0
-#define SIRFSOC_INTENAL_IRQ_END 59
+#define SIRFSOC_INTENAL_IRQ_END 127
#define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1)
-#define NR_IRQS 220
+#define NR_IRQS 288
#endif
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
index 7dee917..6c0f3e9 100644
--- a/arch/arm/mach-prima2/irq.c
+++ b/arch/arm/mach-prima2/irq.c
@@ -9,17 +9,19 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
-#include <mach/hardware.h>
-#include <asm/mach/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/irqdomain.h>
#include <linux/syscore_ops.h>
+#include <asm/mach/irq.h>
+#include <asm/exception.h>
+#include <mach/hardware.h>
#define SIRFSOC_INT_RISC_MASK0 0x0018
#define SIRFSOC_INT_RISC_MASK1 0x001C
#define SIRFSOC_INT_RISC_LEVEL0 0x0020
#define SIRFSOC_INT_RISC_LEVEL1 0x0024
+#define SIRFSOC_INIT_IRQ_ID 0x0038
void __iomem *sirfsoc_intc_base;
@@ -52,6 +54,16 @@ static __init void sirfsoc_irq_init(void)
writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
}
+asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
+{
+ u32 irqstat, irqnr;
+
+ irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);
+ irqnr = irqstat & 0xff;
+
+ handle_IRQ(irqnr, regs);
+}
+
static struct of_device_id intc_ids[] = {
{ .compatible = "sirf,prima2-intc" },
{},
--
1.7.5.4
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
^ permalink raw reply related
* [PATCH v2 6/9] ARM: PRIMA2: rtciobg: it is also compatible with marco
From: Barry Song @ 2013-01-16 5:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358315784-25104-1-git-send-email-Barry.Song@csr.com>
From: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
---
arch/arm/mach-prima2/rtciobrg.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-prima2/rtciobrg.c
index 9d80f1e..fc6c4ab 100644
--- a/arch/arm/mach-prima2/rtciobrg.c
+++ b/arch/arm/mach-prima2/rtciobrg.c
@@ -104,6 +104,7 @@ EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);
static const struct of_device_id rtciobrg_ids[] = {
{ .compatible = "sirf,prima2-rtciobg" },
+ { .compatible = "sirf,marco-rtciobg" },
{}
};
--
1.7.5.4
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
^ permalink raw reply related
* [PATCH v2 5/9] ARM: PRIMA2: rstc: enable the support for Marco
From: Barry Song @ 2013-01-16 5:56 UTC (permalink / raw)
To: linux-arm-kernel
From: Barry Song <Baohua.Song@csr.com>
marco has SET/CLEAR registers pair for rstc to avoid read-modify-write,
this patch detects the mach typer and access registers based on SoC.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
---
arch/arm/mach-prima2/rstc.c | 45 ++++++++++++++++++++++++++----------------
1 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 762adb7..435019c 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -19,6 +19,7 @@ static DEFINE_MUTEX(rstc_lock);
static struct of_device_id rstc_ids[] = {
{ .compatible = "sirf,prima2-rstc" },
+ { .compatible = "sirf,marco-rstc" },
{},
};
@@ -42,27 +43,37 @@ early_initcall(sirfsoc_of_rstc_init);
int sirfsoc_reset_device(struct device *dev)
{
- const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL);
- unsigned int reset_bit;
+ u32 reset_bit;
- if (!prop)
- return -ENODEV;
-
- reset_bit = be32_to_cpup(prop);
+ if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit))
+ return -EINVAL;
mutex_lock(&rstc_lock);
- /*
- * Writing 1 to this bit resets corresponding block. Writing 0 to this
- * bit de-asserts reset signal of the corresponding block.
- * datasheet doesn't require explicit delay between the set and clear
- * of reset bit. it could be shorter if tests pass.
- */
- writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
- sirfsoc_rstc_base + (reset_bit / 32) * 4);
- msleep(10);
- writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
- sirfsoc_rstc_base + (reset_bit / 32) * 4);
+ if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) {
+ /*
+ * Writing 1 to this bit resets corresponding block. Writing 0 to this
+ * bit de-asserts reset signal of the corresponding block.
+ * datasheet doesn't require explicit delay between the set and clear
+ * of reset bit. it could be shorter if tests pass.
+ */
+ writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
+ sirfsoc_rstc_base + (reset_bit / 32) * 4);
+ msleep(10);
+ writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
+ sirfsoc_rstc_base + (reset_bit / 32) * 4);
+ } else {
+ /*
+ * For MARCO and POLO
+ * Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
+ * register de-asserts reset signal of the corresponding block.
+ * datasheet doesn't require explicit delay between the set and clear
+ * of reset bit. it could be shorter if tests pass.
+ */
+ writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
+ msleep(10);
+ writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
+ }
mutex_unlock(&rstc_lock);
--
1.7.5.4
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
^ permalink raw reply related
* [PATCH v2 4/9] ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marco
From: Barry Song @ 2013-01-16 5:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358315610-25001-1-git-send-email-Barry.Song@csr.com>
From: Barry Song <Baohua.Song@csr.com>
Marco timer has different timer IP with prima2, so rename the current timer
to timer-prima2 so that we can add timer-marco.
at the same time, if we don't find prima2 timer node in dt, don't panic the
system as we will make prima2 and marco use same kernel image.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
---
arch/arm/mach-prima2/Makefile | 2 +-
arch/arm/mach-prima2/common.c | 2 +-
arch/arm/mach-prima2/common.h | 2 +-
arch/arm/mach-prima2/{timer.c => timer-prima2.c} | 6 +++---
4 files changed, 6 insertions(+), 6 deletions(-)
rename arch/arm/mach-prima2/{timer.c => timer-prima2.c} (98%)
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index fc9ce22..0007a6e 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,4 +1,3 @@
-obj-y := timer.o
obj-y += rstc.o
obj-y += common.o
obj-y += rtciobrg.o
@@ -6,3 +5,4 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
obj-$(CONFIG_CACHE_L2X0) += l2x0.o
obj-$(CONFIG_SUSPEND) += pm.o sleep.o
obj-$(CONFIG_SIRF_IRQ) += irq.o
+obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index ed3570e..8e6f668 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -40,7 +40,7 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.map_io = sirfsoc_map_lluart,
.init_irq = sirfsoc_of_irq_init,
- .init_time = sirfsoc_timer_init,
+ .init_time = sirfsoc_prima2_timer_init,
.dma_zone_size = SZ_256M,
.init_machine = sirfsoc_mach_init,
.init_late = sirfsoc_init_late,
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 9c75f12..d6890b6 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -12,7 +12,7 @@
#include <linux/init.h>
#include <asm/mach/time.h>
-extern void sirfsoc_timer_init(void);
+extern void sirfsoc_prima2_timer_init(void);
extern void __init sirfsoc_of_irq_init(void);
extern void __init sirfsoc_of_clk_init(void);
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer-prima2.c
similarity index 98%
rename from arch/arm/mach-prima2/timer.c
rename to arch/arm/mach-prima2/timer-prima2.c
index 8c732a5..309e724 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer-prima2.c
@@ -187,7 +187,7 @@ static void __init sirfsoc_clockevent_init(void)
}
/* initialize the kernel jiffy timer source */
-void __init sirfsoc_timer_init(void)
+void __init sirfsoc_prima2_timer_init(void)
{
unsigned long rate;
struct clk *clk;
@@ -226,14 +226,14 @@ static struct of_device_id timer_ids[] = {
{},
};
-void __init sirfsoc_of_timer_map(void)
+static void __init sirfsoc_of_timer_map(void)
{
struct device_node *np;
const unsigned int *intspec;
np = of_find_matching_node(NULL, timer_ids);
if (!np)
- panic("unable to find compatible timer node in dtb\n");
+ return;
sirfsoc_timer_base = of_iomap(np, 0);
if (!sirfsoc_timer_base)
panic("unable to map timer cpu registers\n");
--
1.7.5.4
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
^ permalink raw reply related
* [PATCH v2 3/9] ARM: PRIMA2: initialize l2x0 according to mach from DT
From: Barry Song @ 2013-01-16 5:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358315610-25001-1-git-send-email-Barry.Song@csr.com>
From: Barry Song <Baohua.Song@csr.com>
prima2 and marco have diffetent l2 cache configuration, so
we initialize l2x0 cache based on dtb given to kernel.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Cc: Mark Rutland <mark.rutland@arm.com>
---
arch/arm/mach-prima2/l2x0.c | 29 ++++++++++++++++++++++++-----
1 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c
index c998377..e41ecd2 100644
--- a/arch/arm/mach-prima2/l2x0.c
+++ b/arch/arm/mach-prima2/l2x0.c
@@ -11,19 +11,38 @@
#include <linux/of.h>
#include <asm/hardware/cache-l2x0.h>
-static struct of_device_id prima2_l2x0_ids[] = {
- { .compatible = "sirf,prima2-pl310-cache" },
+struct l2x0_aux
+{
+ u32 val;
+ u32 mask;
+};
+
+static struct l2x0_aux prima2_l2x0_aux __initconst = {
+ 0x40000,
+ 0,
+};
+
+static struct l2x0_aux marco_l2x0_aux __initconst = {
+ (2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
+ (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT),
+ L2X0_AUX_CTRL_MASK,
+};
+
+static struct of_device_id sirf_l2x0_ids[] __initconst = {
+ { .compatible = "sirf,prima2-pl310-cache", .data = &prima2_l2x0_aux, },
+ { .compatible = "sirf,marco-pl310-cache", .data = &marco_l2x0_aux, },
{},
};
static int __init sirfsoc_l2x0_init(void)
{
struct device_node *np;
+ const struct l2x0_aux *aux;
- np = of_find_matching_node(NULL, prima2_l2x0_ids);
+ np = of_find_matching_node(NULL, sirf_l2x0_ids);
if (np) {
- pr_info("Initializing prima2 L2 cache\n");
- return l2x0_of_init(0x40000, 0);
+ aux = of_match_node(sirf_l2x0_ids, np)->data;
+ return l2x0_of_init(aux->val, aux->mask);
}
return 0;
--
1.7.5.4
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
^ permalink raw reply related
* [PATCH v2 2/9] ARM: PRIMA2: enable AUTO_ZRELADDR for SIRF in Kconfig
From: Barry Song @ 2013-01-16 5:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358315610-25001-1-git-send-email-Barry.Song@csr.com>
From: Barry Song <Baohua.Song@csr.com>
prima2 and marco have different memory base address. prima2
begins from 0 and marco begins from
Signed-off-by: Barry Song <Baohua.Song@csr.com>
---
arch/arm/Kconfig | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f95ba14..13f89a2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -394,6 +394,7 @@ config ARCH_GEMINI
config ARCH_SIRF
bool "CSR SiRF"
select ARCH_REQUIRE_GPIOLIB
+ select AUTO_ZRELADDR
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
--
1.7.5.4
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
^ permalink raw reply related
* [PATCH v2 1/9] ARM: PRIMA2: add CSR SiRFmarco device tree .dts
From: Barry Song @ 2013-01-16 5:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Barry Song <Baohua.Song@csr.com>
SiRFmarco is a dual-core cortex-a9 SMP SoC from CSR. this patch
adds the .dtsi and a basic evb board .dts for it.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Cc: Mark Rutland <mark.rutland@arm.com>
---
arch/arm/boot/dts/marco-evb.dts | 51 +++
arch/arm/boot/dts/marco.dtsi | 756 +++++++++++++++++++++++++++++++++++++++
2 files changed, 807 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/marco-evb.dts
create mode 100644 arch/arm/boot/dts/marco.dtsi
diff --git a/arch/arm/boot/dts/marco-evb.dts b/arch/arm/boot/dts/marco-evb.dts
new file mode 100644
index 0000000..4e68d3c
--- /dev/null
+++ b/arch/arm/boot/dts/marco-evb.dts
@@ -0,0 +1,51 @@
+/*
+ * DTS file for CSR SiRFmarco Evaluation Board
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "marco.dtsi"
+
+/ {
+ model = "CSR SiRFmarco Evaluation Board";
+ compatible = "sirf,marco", "sirf,marco-cb";
+
+ memory {
+ reg = <0x40000000 0x60000000>;
+ };
+
+ axi {
+ peri-iobg {
+ uart1: uart at cc060000 {
+ status = "okay";
+ };
+ i2c0: i2c at cc0e0000 {
+ status = "okay";
+ fpga-cpld at 4d {
+ compatible = "sirf,fpga-cpld";
+ reg = <0x4d>;
+ };
+ };
+ spi1: spi at cc170000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins_a>;
+ spi at 0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+ pci-iobg {
+ sd0: sdhci at cd000000 {
+ bus-width = <8>;
+ status = "okay";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi
new file mode 100644
index 0000000..d6bad50
--- /dev/null
+++ b/arch/arm/boot/dts/marco.dtsi
@@ -0,0 +1,756 @@
+/*
+ * DTS file for CSR SiRFmarco SoC
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+/ {
+ compatible = "sirf,marco";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ axi {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x40000000 0x40000000 0xa0000000>;
+
+ l2-cache-controller at c0030000 {
+ compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";
+ reg = <0xc0030000 0x1000>;
+ interrupts = <0 59 0>;
+ arm,tag-latency = <1 1 1>;
+ arm,data-latency = <1 1 1>;
+ arm,filter-ranges = <0x40000000 0x80000000>;
+ };
+
+ gic: interrupt-controller at c0011000 {
+ compatible = "arm,cortex-a9-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0xc0011000 0x1000>,
+ <0xc0010100 0x0100>;
+ };
+
+ rstc-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xc2000000 0xc2000000 0x1000000>;
+
+ reset-controller at c2000000 {
+ compatible = "sirf,marco-rstc";
+ reg = <0xc2000000 0x10000>;
+ };
+ };
+
+ sys-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xc3000000 0xc3000000 0x1000000>;
+
+ clock-controller at c3000000 {
+ compatible = "sirf,marco-clkc";
+ reg = <0xc3000000 0x1000>;
+ interrupts = <0 3 0>;
+ };
+
+ rsc-controller at c3010000 {
+ compatible = "sirf,marco-rsc";
+ reg = <0xc3010000 0x1000>;
+ };
+ };
+
+ mem-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xc4000000 0xc4000000 0x1000000>;
+
+ memory-controller at c4000000 {
+ compatible = "sirf,marco-memc";
+ reg = <0xc4000000 0x10000>;
+ interrupts = <0 27 0>;
+ };
+ };
+
+ disp-iobg0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xc5000000 0xc5000000 0x1000000>;
+
+ display0 at c5000000 {
+ compatible = "sirf,marco-lcd";
+ reg = <0xc5000000 0x10000>;
+ interrupts = <0 30 0>;
+ };
+
+ vpp0 at c5010000 {
+ compatible = "sirf,marco-vpp";
+ reg = <0xc5010000 0x10000>;
+ interrupts = <0 31 0>;
+ };
+ };
+
+ disp-iobg1 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xc6000000 0xc6000000 0x1000000>;
+
+ display1 at c6000000 {
+ compatible = "sirf,marco-lcd";
+ reg = <0xc6000000 0x10000>;
+ interrupts = <0 62 0>;
+ };
+
+ vpp1 at c6010000 {
+ compatible = "sirf,marco-vpp";
+ reg = <0xc6010000 0x10000>;
+ interrupts = <0 63 0>;
+ };
+ };
+
+ graphics-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xc8000000 0xc8000000 0x1000000>;
+
+ graphics at c8000000 {
+ compatible = "powervr,sgx540";
+ reg = <0xc8000000 0x1000000>;
+ interrupts = <0 6 0>;
+ };
+ };
+
+ multimedia-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xc9000000 0xc9000000 0x1000000>;
+
+ multimedia at a0000000 {
+ compatible = "sirf,marco-video-codec";
+ reg = <0xc9000000 0x1000000>;
+ interrupts = <0 5 0>;
+ };
+ };
+
+ dsp-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xca000000 0xca000000 0x2000000>;
+
+ dspif at ca000000 {
+ compatible = "sirf,marco-dspif";
+ reg = <0xca000000 0x10000>;
+ interrupts = <0 9 0>;
+ };
+
+ gps at ca010000 {
+ compatible = "sirf,marco-gps";
+ reg = <0xca010000 0x10000>;
+ interrupts = <0 7 0>;
+ };
+
+ dsp at cb000000 {
+ compatible = "sirf,marco-dsp";
+ reg = <0xcb000000 0x1000000>;
+ interrupts = <0 8 0>;
+ };
+ };
+
+ peri-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xcc000000 0xcc000000 0x2000000>;
+
+ timer at cc020000 {
+ compatible = "sirf,marco-tick";
+ reg = <0xcc020000 0x1000>;
+ interrupts = <0 0 0>,
+ <0 1 0>,
+ <0 2 0>,
+ <0 49 0>,
+ <0 50 0>,
+ <0 51 0>;
+ };
+
+ nand at cc030000 {
+ compatible = "sirf,marco-nand";
+ reg = <0xcc030000 0x10000>;
+ interrupts = <0 41 0>;
+ };
+
+ audio at cc040000 {
+ compatible = "sirf,marco-audio";
+ reg = <0xcc040000 0x10000>;
+ interrupts = <0 35 0>;
+ };
+
+ uart0: uart at cc050000 {
+ cell-index = <0>;
+ compatible = "sirf,marco-uart";
+ reg = <0xcc050000 0x1000>;
+ interrupts = <0 17 0>;
+ fifosize = <128>;
+ status = "disabled";
+ };
+
+ uart1: uart at cc060000 {
+ cell-index = <1>;
+ compatible = "sirf,marco-uart";
+ reg = <0xcc060000 0x1000>;
+ interrupts = <0 18 0>;
+ fifosize = <32>;
+ status = "disabled";
+ };
+
+ uart2: uart at cc070000 {
+ cell-index = <2>;
+ compatible = "sirf,marco-uart";
+ reg = <0xcc070000 0x1000>;
+ interrupts = <0 19 0>;
+ fifosize = <128>;
+ status = "disabled";
+ };
+
+ uart3: uart at cc190000 {
+ cell-index = <3>;
+ compatible = "sirf,marco-uart";
+ reg = <0xcc190000 0x1000>;
+ interrupts = <0 66 0>;
+ fifosize = <128>;
+ status = "disabled";
+ };
+
+ uart4: uart at cc1a0000 {
+ cell-index = <4>;
+ compatible = "sirf,marco-uart";
+ reg = <0xcc1a0000 0x1000>;
+ interrupts = <0 69 0>;
+ fifosize = <128>;
+ status = "disabled";
+ };
+
+ usp0: usp at cc080000 {
+ cell-index = <0>;
+ compatible = "sirf,marco-usp";
+ reg = <0xcc080000 0x10000>;
+ interrupts = <0 20 0>;
+ status = "disabled";
+ };
+
+ usp1: usp at cc090000 {
+ cell-index = <1>;
+ compatible = "sirf,marco-usp";
+ reg = <0xcc090000 0x10000>;
+ interrupts = <0 21 0>;
+ status = "disabled";
+ };
+
+ usp2: usp at cc0a0000 {
+ cell-index = <2>;
+ compatible = "sirf,marco-usp";
+ reg = <0xcc0a0000 0x10000>;
+ interrupts = <0 22 0>;
+ status = "disabled";
+ };
+
+ dmac0: dma-controller at cc0b0000 {
+ cell-index = <0>;
+ compatible = "sirf,marco-dmac";
+ reg = <0xcc0b0000 0x10000>;
+ interrupts = <0 12 0>;
+ };
+
+ dmac1: dma-controller at cc160000 {
+ cell-index = <1>;
+ compatible = "sirf,marco-dmac";
+ reg = <0xcc160000 0x10000>;
+ interrupts = <0 13 0>;
+ };
+
+ vip at cc0c0000 {
+ compatible = "sirf,marco-vip";
+ reg = <0xcc0c0000 0x10000>;
+ };
+
+ spi0: spi at cc0d0000 {
+ cell-index = <0>;
+ compatible = "sirf,marco-spi";
+ reg = <0xcc0d0000 0x10000>;
+ interrupts = <0 15 0>;
+ sirf,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio 0 0>;
+ sirf,spi-dma-rx-channel = <25>;
+ sirf,spi-dma-tx-channel = <20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi at cc170000 {
+ cell-index = <1>;
+ compatible = "sirf,marco-spi";
+ reg = <0xcc170000 0x10000>;
+ interrupts = <0 16 0>;
+ sirf,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio 0 0>;
+ sirf,spi-dma-rx-channel = <12>;
+ sirf,spi-dma-tx-channel = <13>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c at cc0e0000 {
+ cell-index = <0>;
+ compatible = "sirf,marco-i2c";
+ reg = <0xcc0e0000 0x10000>;
+ interrupts = <0 24 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at cc0f0000 {
+ cell-index = <1>;
+ compatible = "sirf,marco-i2c";
+ reg = <0xcc0f0000 0x10000>;
+ interrupts = <0 25 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ tsc at cc110000 {
+ compatible = "sirf,marco-tsc";
+ reg = <0xcc110000 0x10000>;
+ interrupts = <0 33 0>;
+ };
+
+ gpio: pinctrl at cc120000 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "sirf,marco-pinctrl";
+ reg = <0xcc120000 0x10000>;
+ interrupts = <0 43 0>,
+ <0 44 0>,
+ <0 45 0>,
+ <0 46 0>,
+ <0 47 0>;
+ gpio-controller;
+ interrupt-controller;
+
+ lcd_16pins_a: lcd0 at 0 {
+ lcd {
+ sirf,pins = "lcd_16bitsgrp";
+ sirf,function = "lcd_16bits";
+ };
+ };
+ lcd_18pins_a: lcd0 at 1 {
+ lcd {
+ sirf,pins = "lcd_18bitsgrp";
+ sirf,function = "lcd_18bits";
+ };
+ };
+ lcd_24pins_a: lcd0 at 2 {
+ lcd {
+ sirf,pins = "lcd_24bitsgrp";
+ sirf,function = "lcd_24bits";
+ };
+ };
+ lcdrom_pins_a: lcdrom0 at 0 {
+ lcd {
+ sirf,pins = "lcdromgrp";
+ sirf,function = "lcdrom";
+ };
+ };
+ uart0_pins_a: uart0 at 0 {
+ uart {
+ sirf,pins = "uart0grp";
+ sirf,function = "uart0";
+ };
+ };
+ uart1_pins_a: uart1 at 0 {
+ uart {
+ sirf,pins = "uart1grp";
+ sirf,function = "uart1";
+ };
+ };
+ uart2_pins_a: uart2 at 0 {
+ uart {
+ sirf,pins = "uart2grp";
+ sirf,function = "uart2";
+ };
+ };
+ uart2_noflow_pins_a: uart2 at 1 {
+ uart {
+ sirf,pins = "uart2_nostreamctrlgrp";
+ sirf,function = "uart2_nostreamctrl";
+ };
+ };
+ spi0_pins_a: spi0 at 0 {
+ spi {
+ sirf,pins = "spi0grp";
+ sirf,function = "spi0";
+ };
+ };
+ spi1_pins_a: spi1 at 0 {
+ spi {
+ sirf,pins = "spi1grp";
+ sirf,function = "spi1";
+ };
+ };
+ i2c0_pins_a: i2c0 at 0 {
+ i2c {
+ sirf,pins = "i2c0grp";
+ sirf,function = "i2c0";
+ };
+ };
+ i2c1_pins_a: i2c1 at 0 {
+ i2c {
+ sirf,pins = "i2c1grp";
+ sirf,function = "i2c1";
+ };
+ };
+ pwm0_pins_a: pwm0 at 0 {
+ pwm {
+ sirf,pins = "pwm0grp";
+ sirf,function = "pwm0";
+ };
+ };
+ pwm1_pins_a: pwm1 at 0 {
+ pwm {
+ sirf,pins = "pwm1grp";
+ sirf,function = "pwm1";
+ };
+ };
+ pwm2_pins_a: pwm2 at 0 {
+ pwm {
+ sirf,pins = "pwm2grp";
+ sirf,function = "pwm2";
+ };
+ };
+ pwm3_pins_a: pwm3 at 0 {
+ pwm {
+ sirf,pins = "pwm3grp";
+ sirf,function = "pwm3";
+ };
+ };
+ gps_pins_a: gps at 0 {
+ gps {
+ sirf,pins = "gpsgrp";
+ sirf,function = "gps";
+ };
+ };
+ vip_pins_a: vip at 0 {
+ vip {
+ sirf,pins = "vipgrp";
+ sirf,function = "vip";
+ };
+ };
+ sdmmc0_pins_a: sdmmc0 at 0 {
+ sdmmc0 {
+ sirf,pins = "sdmmc0grp";
+ sirf,function = "sdmmc0";
+ };
+ };
+ sdmmc1_pins_a: sdmmc1 at 0 {
+ sdmmc1 {
+ sirf,pins = "sdmmc1grp";
+ sirf,function = "sdmmc1";
+ };
+ };
+ sdmmc2_pins_a: sdmmc2 at 0 {
+ sdmmc2 {
+ sirf,pins = "sdmmc2grp";
+ sirf,function = "sdmmc2";
+ };
+ };
+ sdmmc3_pins_a: sdmmc3 at 0 {
+ sdmmc3 {
+ sirf,pins = "sdmmc3grp";
+ sirf,function = "sdmmc3";
+ };
+ };
+ sdmmc4_pins_a: sdmmc4 at 0 {
+ sdmmc4 {
+ sirf,pins = "sdmmc4grp";
+ sirf,function = "sdmmc4";
+ };
+ };
+ sdmmc5_pins_a: sdmmc5 at 0 {
+ sdmmc5 {
+ sirf,pins = "sdmmc5grp";
+ sirf,function = "sdmmc5";
+ };
+ };
+ i2s_pins_a: i2s at 0 {
+ i2s {
+ sirf,pins = "i2sgrp";
+ sirf,function = "i2s";
+ };
+ };
+ ac97_pins_a: ac97 at 0 {
+ ac97 {
+ sirf,pins = "ac97grp";
+ sirf,function = "ac97";
+ };
+ };
+ nand_pins_a: nand at 0 {
+ nand {
+ sirf,pins = "nandgrp";
+ sirf,function = "nand";
+ };
+ };
+ usp0_pins_a: usp0 at 0 {
+ usp0 {
+ sirf,pins = "usp0grp";
+ sirf,function = "usp0";
+ };
+ };
+ usp1_pins_a: usp1 at 0 {
+ usp1 {
+ sirf,pins = "usp1grp";
+ sirf,function = "usp1";
+ };
+ };
+ usp2_pins_a: usp2 at 0 {
+ usp2 {
+ sirf,pins = "usp2grp";
+ sirf,function = "usp2";
+ };
+ };
+ usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus at 0 {
+ usb0_utmi_drvbus {
+ sirf,pins = "usb0_utmi_drvbusgrp";
+ sirf,function = "usb0_utmi_drvbus";
+ };
+ };
+ usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus at 0 {
+ usb1_utmi_drvbus {
+ sirf,pins = "usb1_utmi_drvbusgrp";
+ sirf,function = "usb1_utmi_drvbus";
+ };
+ };
+ warm_rst_pins_a: warm_rst at 0 {
+ warm_rst {
+ sirf,pins = "warm_rstgrp";
+ sirf,function = "warm_rst";
+ };
+ };
+ pulse_count_pins_a: pulse_count at 0 {
+ pulse_count {
+ sirf,pins = "pulse_countgrp";
+ sirf,function = "pulse_count";
+ };
+ };
+ cko0_rst_pins_a: cko0_rst at 0 {
+ cko0_rst {
+ sirf,pins = "cko0_rstgrp";
+ sirf,function = "cko0_rst";
+ };
+ };
+ cko1_rst_pins_a: cko1_rst at 0 {
+ cko1_rst {
+ sirf,pins = "cko1_rstgrp";
+ sirf,function = "cko1_rst";
+ };
+ };
+ };
+
+ pwm at cc130000 {
+ compatible = "sirf,marco-pwm";
+ reg = <0xcc130000 0x10000>;
+ };
+
+ efusesys at cc140000 {
+ compatible = "sirf,marco-efuse";
+ reg = <0xcc140000 0x10000>;
+ };
+
+ pulsec at cc150000 {
+ compatible = "sirf,marco-pulsec";
+ reg = <0xcc150000 0x10000>;
+ interrupts = <0 48 0>;
+ };
+
+ pci-iobg {
+ compatible = "sirf,marco-pciiobg", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xcd000000 0xcd000000 0x1000000>;
+
+ sd0: sdhci at cd000000 {
+ cell-index = <0>;
+ compatible = "sirf,marco-sdhc";
+ reg = <0xcd000000 0x100000>;
+ interrupts = <0 38 0>;
+ status = "disabled";
+ };
+
+ sd1: sdhci at cd100000 {
+ cell-index = <1>;
+ compatible = "sirf,marco-sdhc";
+ reg = <0xcd100000 0x100000>;
+ interrupts = <0 38 0>;
+ status = "disabled";
+ };
+
+ sd2: sdhci at cd200000 {
+ cell-index = <2>;
+ compatible = "sirf,marco-sdhc";
+ reg = <0xcd200000 0x100000>;
+ interrupts = <0 23 0>;
+ status = "disabled";
+ };
+
+ sd3: sdhci at cd300000 {
+ cell-index = <3>;
+ compatible = "sirf,marco-sdhc";
+ reg = <0xcd300000 0x100000>;
+ interrupts = <0 23 0>;
+ status = "disabled";
+ };
+
+ sd4: sdhci at cd400000 {
+ cell-index = <4>;
+ compatible = "sirf,marco-sdhc";
+ reg = <0xcd400000 0x100000>;
+ interrupts = <0 39 0>;
+ status = "disabled";
+ };
+
+ sd5: sdhci at cd500000 {
+ cell-index = <5>;
+ compatible = "sirf,marco-sdhc";
+ reg = <0xcd500000 0x100000>;
+ interrupts = <0 39 0>;
+ status = "disabled";
+ };
+
+ pci-copy at cd900000 {
+ compatible = "sirf,marco-pcicp";
+ reg = <0xcd900000 0x100000>;
+ interrupts = <0 40 0>;
+ };
+
+ rom-interface at cda00000 {
+ compatible = "sirf,marco-romif";
+ reg = <0xcda00000 0x100000>;
+ };
+ };
+ };
+
+ rtc-iobg {
+ compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xc1000000 0x10000>;
+
+ gpsrtc at 1000 {
+ compatible = "sirf,marco-gpsrtc";
+ reg = <0x1000 0x1000>;
+ interrupts = <0 55 0>,
+ <0 56 0>,
+ <0 57 0>;
+ };
+
+ sysrtc at 2000 {
+ compatible = "sirf,marco-sysrtc";
+ reg = <0x2000 0x1000>;
+ interrupts = <0 52 0>,
+ <0 53 0>,
+ <0 54 0>;
+ };
+
+ pwrc at 3000 {
+ compatible = "sirf,marco-pwrc";
+ reg = <0x3000 0x1000>;
+ interrupts = <0 32 0>;
+ };
+ };
+
+ uus-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xce000000 0xce000000 0x1000000>;
+
+ usb0: usb at ce000000 {
+ compatible = "chipidea,ci13611a-marco";
+ reg = <0xce000000 0x10000>;
+ interrupts = <0 10 0>;
+ };
+
+ usb1: usb at ce010000 {
+ compatible = "chipidea,ci13611a-marco";
+ reg = <0xce010000 0x10000>;
+ interrupts = <0 11 0>;
+ };
+
+ security at ce020000 {
+ compatible = "sirf,marco-security";
+ reg = <0xce020000 0x10000>;
+ interrupts = <0 42 0>;
+ };
+ };
+
+ can-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xd0000000 0xd0000000 0x1000000>;
+
+ can0: can at d0000000 {
+ compatible = "sirf,marco-can";
+ reg = <0xd0000000 0x10000>;
+ };
+
+ can1: can at d0010000 {
+ compatible = "sirf,marco-can";
+ reg = <0xd0010000 0x10000>;
+ };
+ };
+
+ lvds-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xd1000000 0xd1000000 0x1000000>;
+
+ lvds at d1000000 {
+ compatible = "sirf,marco-lvds";
+ reg = <0xd1000000 0x10000>;
+ interrupts = <0 64 0>;
+ };
+ };
+ };
+};
--
1.7.5.4
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
^ permalink raw reply related
* [PATCH v2 0/9] ARM: PRIMA2: bringup new CSR SiRFmarco SMP SoC
From: Barry Song @ 2013-01-16 5:49 UTC (permalink / raw)
To: linux-arm-kernel
this patch series enables the new CSR SiRFmarco SMP SoC.
change list:
-v2:
1. cleanup marco.dtsi according to Mark Rutland's feedback
2. use of_device_id::data to handle the difference of l2x0 aux setting
according to Mark Rutland's feedback
3. rebase to the newest timer/cleanup branch, removing sys_timer
-v1:
1. Marco has different OS timer hardware with Prima2, so add a new timer-marco
2. add platsmp.c, headsmp.S and hotplug.c for MPcore support
3. some hardwares have changed, like rstc, so use of_compatible to branch Prima2
and Marco
4. add initial .dtsi for Marco SoC and initial .dts for the EVB
5. use GIC for Marco instead of Prima2's IRQ controller
6. add DEBUG_LL uart ports for Prima2 and Marco debug ports
Barry Song (9):
ARM: PRIMA2: add CSR SiRFmarco device tree .dts
ARM: PRIMA2: enable AUTO_ZRELADDR for SIRF in Kconfig
ARM: PRIMA2: initialize l2x0 according to mach from DT
ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marco
ARM: PRIMA2: rstc: enable the support for Marco
ARM: PRIMA2: rtciobg: it is also compatible with marco
ARM: PRIMA2: irq: make prima2 irq can work even we enable GIC for
Marco
ARM: PRIMA2: add new SiRFmarco SMP SoC infrastructures
ARM: PRIMA2: provide two DEBUG_LL ports for prima2 and marco
arch/arm/Kconfig | 1 +
arch/arm/Kconfig.debug | 14 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/marco-evb.dts | 51 ++
arch/arm/boot/dts/marco.dtsi | 756 ++++++++++++++++++++++
arch/arm/configs/prima2_defconfig | 3 +
arch/arm/mach-prima2/Kconfig | 10 +
arch/arm/mach-prima2/Makefile | 5 +-
arch/arm/mach-prima2/common.c | 45 ++-
arch/arm/mach-prima2/common.h | 15 +-
arch/arm/mach-prima2/headsmp.S | 79 +++
arch/arm/mach-prima2/hotplug.c | 41 ++
arch/arm/mach-prima2/include/mach/irqs.h | 4 +-
arch/arm/mach-prima2/include/mach/uart.h | 6 +
arch/arm/mach-prima2/include/mach/uncompress.h | 3 +
arch/arm/mach-prima2/irq.c | 16 +-
arch/arm/mach-prima2/l2x0.c | 29 +-
arch/arm/mach-prima2/platsmp.c | 170 +++++
arch/arm/mach-prima2/rstc.c | 45 +-
arch/arm/mach-prima2/rtciobrg.c | 1 +
arch/arm/mach-prima2/timer-marco.c | 355 ++++++++++
arch/arm/mach-prima2/{timer.c => timer-prima2.c} | 6 +-
22 files changed, 1623 insertions(+), 33 deletions(-)
create mode 100644 arch/arm/boot/dts/marco-evb.dts
create mode 100644 arch/arm/boot/dts/marco.dtsi
create mode 100644 arch/arm/mach-prima2/headsmp.S
create mode 100644 arch/arm/mach-prima2/hotplug.c
create mode 100644 arch/arm/mach-prima2/platsmp.c
create mode 100644 arch/arm/mach-prima2/timer-marco.c
rename arch/arm/mach-prima2/{timer.c => timer-prima2.c} (98%)
--
1.7.5.4
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
^ permalink raw reply
* [v3 PATCH 7/9] watchdog/at91sam9_wdt: Use module_platform_driver()
From: Yang, Wenyou @ 2013-01-16 5:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHkwnC8CTFxrJ8F=u=MqKW=cZ88SeoT+rA_hzW38jL8ffT9D2Q@mail.gmail.com>
Hi Fabio Porcedda,
> -----Original Message-----
> From: Fabio Porcedda [mailto:fabio.porcedda at gmail.com]
> Sent: 2013?1?8? 18:18
> To: Yang, Wenyou
> Cc: linux-arm-kernel at lists.infradead.org; Ferre, Nicolas; Jean-Christophe
> PLAGNIOL-VILLARD; Lin, JM; Wim Van Sebroeck;
> linux-watchdog at vger.kernel.org; linux-kernel at vger.kernel.org; Geert
> Uytterhoeven
> Subject: Re: [v3 PATCH 7/9] watchdog/at91sam9_wdt: Use
> module_platform_driver()
>
> On Sat, Jan 5, 2013 at 3:38 AM, Wenyou Yang <wenyou.yang@atmel.com>
> wrote:
> > Using module_platform_driver() replaces module_init() and module_exit()
> > and makes the code simpler.
> >
> > Remove '__init' annotation from the function 'at91wdt_probe'
> > since the driver becomes hot-plug aware now.
> >
> > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> > Cc: wim at iguana.be
> > Cc: linux-watchdog at vger.kernel.org
> > Cc: linux-kernel at vger.kernel.org
> > ---
> > drivers/watchdog/at91sam9_wdt.c | 16 +++-------------
> > 1 file changed, 3 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/watchdog/at91sam9_wdt.c
> b/drivers/watchdog/at91sam9_wdt.c
> > index 94be9d6..7c13dda 100644
> > --- a/drivers/watchdog/at91sam9_wdt.c
> > +++ b/drivers/watchdog/at91sam9_wdt.c
> > @@ -204,7 +204,7 @@ static struct watchdog_device at91wdt_wdd = {
> > .ops = &at91wdt_ops,
> > };
> >
> > -static int __init at91wdt_probe(struct platform_device *pdev)
> > +static int at91wdt_probe(struct platform_device *pdev)
> > {
> > struct at91wdt_drvdata *driver_data;
> > struct resource *r;
> > @@ -273,6 +273,7 @@ MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids);
> > #endif
> >
> > static struct platform_driver at91wdt_driver = {
> > + .probe = at91wdt_probe,
> > .remove = __exit_p(at91wdt_remove),
> > .driver = {
> > .name = "at91_wdt",
> > @@ -281,18 +282,7 @@ static struct platform_driver at91wdt_driver = {
> > },
> > };
> >
> > -static int __init at91sam_wdt_init(void)
> > -{
> > - return platform_driver_probe(&at91wdt_driver, at91wdt_probe);
> > -}
> > -
> > -static void __exit at91sam_wdt_exit(void)
> > -{
> > - platform_driver_unregister(&at91wdt_driver);
> > -}
> > -
> > -module_init(at91sam_wdt_init);
> > -module_exit(at91sam_wdt_exit);
> > +module_platform_driver(at91wdt_driver);
> >
> > MODULE_AUTHOR("Renaud CERRATO <r.cerrato@til-technologies.fr>");
> > MODULE_DESCRIPTION("Watchdog driver for Atmel AT91SAM9x
> processors");
> > --
> > 1.7.9.5
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
>
> The module_platform_driver isn't a substitute of platform_driver_probe,
> because module_platform_driver use platform_driver_register/unregister.
> Using that macro we lose the advantage of platform_driver_probe,
> as stated in:
>
> https://lkml.org/lkml/2012/1/10/335
I just referred to the commit 6b761b2902c56b468370e0ee1691c37e0dae042a.
Didn't think more about it.
I will remove this patch in the next version.
> On Tue, Jan 10, 2012 at 21:47, Geert Uytterhoeven <geert@linux-m68k.org>
> wrote:
> > [...]
> >Still, setting up platform_driver.probe and removing __init from all probe
> >functions is not the right thing to do, as this make (non-__init) kernel code
> >size bigger, while none of these devices are hotpluggable and thus cannot
> >appear after bootup. That's why we have platform_driver_probe() in the
> >first place. So I think all of this should be reverted for non-hotpluggable
> >drivers.
> > [...]
You said is reasonable, watchdog is not hotpluggable.
>
> Best regards
>
> --
> Fabio Porcedda
Best Regards,
Wenyou Yang
^ permalink raw reply
* [PATCH v5 6/9] ARM: davinci: Remoteproc driver support for OMAP-L138 DSP
From: Sekhar Nori @ 2013-01-16 5:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK=WgbYwM2WPWrTp9U+nk_96RY3YYumzo0KxFpV0fDwU6dR+aA@mail.gmail.com>
On 1/15/2013 6:19 PM, Ohad Ben-Cohen wrote:
> On Tue, Jan 15, 2013 at 2:29 PM, Sekhar Nori <nsekhar@ti.com> wrote:
>> May be rproc_alloc() could auto-assign the firmware name to something
>> like 'rproc%d-fw' if firmware name passed to it is NULL?
>
> I prefer we use name-based filenames instead to make it easier for
> users (and us developers).
>
> We can probably do something like "rproc-%s-fw" with pdata->name
> assuming we/you do maintain a meaningful name in the latter.
Are you thinking of passing name of the remote processor (like m3, dsp0,
dsp1 etc) in pdata->name? That sounds OK since the processor name is
actually tied to the platform. BTW, the current driver seems to be
written for OMAP-L138 rather tightly so you could as well hardcode the
firmware name to 'rproc-dsp-fw'.
Thanks,
Sekhar
^ permalink raw reply
* [v3 6/9] ARM: dt: tegra114: Add new SoC base, Tegra 114 SoC
From: Hiroshi Doyu @ 2013-01-16 5:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130115172733.GS4118@tbergstrom-lnx.Nvidia.com>
Peter De Schrijver <pdeschrijver@nvidia.com> wrote @ Tue, 15 Jan 2013 18:27:33 +0100:
> On Tue, Jan 15, 2013 at 05:55:47PM +0100, Stephen Warren wrote:
> > On 01/15/2013 01:13 AM, Hiroshi Doyu wrote:
> > > Initial support for Tegra 114 SoC. This is expected to be included in
> > > the board DTS files, Tegra 114 SoC based evaluation board family.
> >
> > This series looks fine to me. Assuming no other comments, I'll apply
> > once CCF is applied and you've done the rebase you mentioned for patch 2.
> >
> > Note that I'll apply most patches to Tegra's for-3.9/soc branch (the
> > code) but the 3 device tree patches to Tegra's for-3.9/dt branch, since
> > it's fine for the DT files to appear later than the code supporting the
> > SoC, since this is all new features.
> >
> > One question: The .dts files don't include any clocks properties. I
> > assume Peter will add these when he posts the Tegra114 CCF code?
>
> Yes. I will add those as part of the Tegra114 CCF series.
Once Tegra114 CCF comes, the 2nd one can be dropped.
^ permalink raw reply
* linux-next: manual merge of the tegra tree with the arm-soc tree
From: Tony Prisk @ 2013-01-16 4:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F62D69.8080100@nvidia.com>
On Tue, 2013-01-15 at 21:32 -0700, Stephen Warren wrote:
> On 01/15/2013 08:49 PM, Tony Prisk wrote:
> > On Wed, 2013-01-16 at 14:14 +1100, Stephen Rothwell wrote:
> >> Hi all,
> >>
> >> Today's linux-next merge of the tegra tree got a conflict in
> >> drivers/clocksource/Makefile between commit ff7ec345f0ec ("timer: vt8500:
> >> Move timer code to drivers/clocksource") from the arm-soc tree and commit
> >> ac0fd9eca3ba ("ARM: tegra: move timer.c to drivers/clocksource/") from
> >> the tegra tree.
> >>
> >> I fixed it up (see below) and can carry the fix as necessary (no action
> >> is required).
> >>
> >
> > I don't know about everyone else, but I feel the preference should be to
> > keep things alphabetized where possible to help avoid with merge
> > conflicts later on. This is always a problem when we start tacking
> > things on the end of lists.
> >
> > I realise this Kconfig is not alphabetized anyway, but it's never too
> > early to start on the 'right' path.
>
> Sounds like a good idea, but the issue is: When to do the initial sort
> so it doesn't conflict with all the adds in a kernel cycle... Post and
> immediately commit a new patch near the end of the merge window?
Given that the maintainer can quite safely do the patch (sorry
maintainers), I don't see any reason why it couldn't be done at the
point where they stop accepting patches for the merge-window. Once the
patches are stopped, sort the list in one last patch.
It makes sense to get it done in this window if possible as the Kconfig
will only get bigger as time goes on, making sorting it more time
consuming.
Regards
Tony P
^ permalink raw reply
* linux-next: manual merge of the tegra tree with the arm-soc tree
From: Stephen Warren @ 2013-01-16 4:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358308153.32106.8.camel@gitbox>
On 01/15/2013 08:49 PM, Tony Prisk wrote:
> On Wed, 2013-01-16 at 14:14 +1100, Stephen Rothwell wrote:
>> Hi all,
>>
>> Today's linux-next merge of the tegra tree got a conflict in
>> drivers/clocksource/Makefile between commit ff7ec345f0ec ("timer: vt8500:
>> Move timer code to drivers/clocksource") from the arm-soc tree and commit
>> ac0fd9eca3ba ("ARM: tegra: move timer.c to drivers/clocksource/") from
>> the tegra tree.
>>
>> I fixed it up (see below) and can carry the fix as necessary (no action
>> is required).
>>
>
> I don't know about everyone else, but I feel the preference should be to
> keep things alphabetized where possible to help avoid with merge
> conflicts later on. This is always a problem when we start tacking
> things on the end of lists.
>
> I realise this Kconfig is not alphabetized anyway, but it's never too
> early to start on the 'right' path.
Sounds like a good idea, but the issue is: When to do the initial sort
so it doesn't conflict with all the adds in a kernel cycle... Post and
immediately commit a new patch near the end of the merge window?
^ permalink raw reply
* [PATCH v5 07/14] KVM: ARM: World-switch implementation
From: Christoffer Dall @ 2013-01-16 4:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANM98q+qScaXniyYjrd9QEZzWKzj3PkCE0YNFUp2ijnCfS_v4w@mail.gmail.com>
On Tue, Jan 15, 2013 at 9:08 PM, Christoffer Dall
<c.dall@virtualopensystems.com> wrote:
> On Tue, Jan 15, 2013 at 4:43 AM, Gleb Natapov <gleb@redhat.com> wrote:
>> On Tue, Jan 08, 2013 at 01:39:24PM -0500, Christoffer Dall wrote:
>>> Provides complete world-switch implementation to switch to other guests
>>> running in non-secure modes. Includes Hyp exception handlers that
>>> capture necessary exception information and stores the information on
>>> the VCPU and KVM structures.
>>>
>>> The following Hyp-ABI is also documented in the code:
>>>
>>> Hyp-ABI: Calling HYP-mode functions from host (in SVC mode):
>>> Switching to Hyp mode is done through a simple HVC #0 instruction. The
>>> exception vector code will check that the HVC comes from VMID==0 and if
>>> so will push the necessary state (SPSR, lr_usr) on the Hyp stack.
>>> - r0 contains a pointer to a HYP function
>>> - r1, r2, and r3 contain arguments to the above function.
>>> - The HYP function will be called with its arguments in r0, r1 and r2.
>>> On HYP function return, we return directly to SVC.
>>>
>>> A call to a function executing in Hyp mode is performed like the following:
>>>
>>> <svc code>
>>> ldr r0, =BSYM(my_hyp_fn)
>>> ldr r1, =my_param
>>> hvc #0 ; Call my_hyp_fn(my_param) from HYP mode
>>> <svc code>
>>>
>>> Otherwise, the world-switch is pretty straight-forward. All state that
>>> can be modified by the guest is first backed up on the Hyp stack and the
>>> VCPU values is loaded onto the hardware. State, which is not loaded, but
>>> theoretically modifiable by the guest is protected through the
>>> virtualiation features to generate a trap and cause software emulation.
>>> Upon guest returns, all state is restored from hardware onto the VCPU
>>> struct and the original state is restored from the Hyp-stack onto the
>>> hardware.
>>>
>>> SMP support using the VMPIDR calculated on the basis of the host MPIDR
>>> and overriding the low bits with KVM vcpu_id contributed by Marc Zyngier.
>>>
>>> Reuse of VMIDs has been implemented by Antonios Motakis and adapated from
>>> a separate patch into the appropriate patches introducing the
>>> functionality. Note that the VMIDs are stored per VM as required by the ARM
>>> architecture reference manual.
>>>
>>> To support VFP/NEON we trap those instructions using the HPCTR. When
>>> we trap, we switch the FPU. After a guest exit, the VFP state is
>>> returned to the host. When disabling access to floating point
>>> instructions, we also mask FPEXC_EN in order to avoid the guest
>>> receiving Undefined instruction exceptions before we have a chance to
>>> switch back the floating point state. We are reusing vfp_hard_struct,
>>> so we depend on VFPv3 being enabled in the host kernel, if not, we still
>>> trap cp10 and cp11 in order to inject an undefined instruction exception
>>> whenever the guest tries to use VFP/NEON. VFP/NEON developed by
>>> Antionios Motakis and Rusty Russell.
>>>
>>> Aborts that are permission faults, and not stage-1 page table walk, do
>>> not report the faulting address in the HPFAR. We have to resolve the
>>> IPA, and store it just like the HPFAR register on the VCPU struct. If
>>> the IPA cannot be resolved, it means another CPU is playing with the
>>> page tables, and we simply restart the guest. This quirk was fixed by
>>> Marc Zyngier.
>>>
>>> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
>>> Signed-off-by: Rusty Russell <rusty.russell@linaro.org>
>>> Signed-off-by: Antonios Motakis <a.motakis@virtualopensystems.com>
>>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>>> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
>>> ---
>>> arch/arm/include/asm/kvm_arm.h | 51 ++++
>>> arch/arm/include/asm/kvm_host.h | 10 +
>>> arch/arm/kernel/asm-offsets.c | 25 ++
>>> arch/arm/kvm/arm.c | 187 ++++++++++++++++
>>> arch/arm/kvm/interrupts.S | 396 +++++++++++++++++++++++++++++++++++
>>> arch/arm/kvm/interrupts_head.S | 443 +++++++++++++++++++++++++++++++++++++++
>>> 6 files changed, 1108 insertions(+), 4 deletions(-)
>>> create mode 100644 arch/arm/kvm/interrupts_head.S
>>>
>>> diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
>>> index fb22ee8..a3262a2 100644
>>> --- a/arch/arm/include/asm/kvm_arm.h
>>> +++ b/arch/arm/include/asm/kvm_arm.h
>>> @@ -98,6 +98,18 @@
>>> #define TTBCR_T0SZ 3
>>> #define HTCR_MASK (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0)
>>>
>>> +/* Hyp System Trap Register */
>>> +#define HSTR_T(x) (1 << x)
>>> +#define HSTR_TTEE (1 << 16)
>>> +#define HSTR_TJDBX (1 << 17)
>>> +
>>> +/* Hyp Coprocessor Trap Register */
>>> +#define HCPTR_TCP(x) (1 << x)
>>> +#define HCPTR_TCP_MASK (0x3fff)
>>> +#define HCPTR_TASE (1 << 15)
>>> +#define HCPTR_TTA (1 << 20)
>>> +#define HCPTR_TCPAC (1 << 31)
>>> +
>>> /* Hyp Debug Configuration Register bits */
>>> #define HDCR_TDRA (1 << 11)
>>> #define HDCR_TDOSA (1 << 10)
>>> @@ -144,6 +156,45 @@
>>> #else
>>> #define VTTBR_X (5 - KVM_T0SZ)
>>> #endif
>>> +#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
>>> +#define VTTBR_BADDR_MASK (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
>>> +#define VTTBR_VMID_SHIFT (48LLU)
>>> +#define VTTBR_VMID_MASK (0xffLLU << VTTBR_VMID_SHIFT)
>>> +
>>> +/* Hyp Syndrome Register (HSR) bits */
>>> +#define HSR_EC_SHIFT (26)
>>> +#define HSR_EC (0x3fU << HSR_EC_SHIFT)
>>> +#define HSR_IL (1U << 25)
>>> +#define HSR_ISS (HSR_IL - 1)
>>> +#define HSR_ISV_SHIFT (24)
>>> +#define HSR_ISV (1U << HSR_ISV_SHIFT)
>>> +#define HSR_FSC (0x3f)
>>> +#define HSR_FSC_TYPE (0x3c)
>>> +#define HSR_WNR (1 << 6)
>>> +
>>> +#define FSC_FAULT (0x04)
>>> +#define FSC_PERM (0x0c)
>>> +
>>> +/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
>>> +#define HPFAR_MASK (~0xf)
>>>
>>> +#define HSR_EC_UNKNOWN (0x00)
>>> +#define HSR_EC_WFI (0x01)
>>> +#define HSR_EC_CP15_32 (0x03)
>>> +#define HSR_EC_CP15_64 (0x04)
>>> +#define HSR_EC_CP14_MR (0x05)
>>> +#define HSR_EC_CP14_LS (0x06)
>>> +#define HSR_EC_CP_0_13 (0x07)
>>> +#define HSR_EC_CP10_ID (0x08)
>>> +#define HSR_EC_JAZELLE (0x09)
>>> +#define HSR_EC_BXJ (0x0A)
>>> +#define HSR_EC_CP14_64 (0x0C)
>>> +#define HSR_EC_SVC_HYP (0x11)
>>> +#define HSR_EC_HVC (0x12)
>>> +#define HSR_EC_SMC (0x13)
>>> +#define HSR_EC_IABT (0x20)
>>> +#define HSR_EC_IABT_HYP (0x21)
>>> +#define HSR_EC_DABT (0x24)
>>> +#define HSR_EC_DABT_HYP (0x25)
>>>
>>> #endif /* __ARM_KVM_ARM_H__ */
>>> diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
>>> index 1de6f0d..ddb09da 100644
>>> --- a/arch/arm/include/asm/kvm_host.h
>>> +++ b/arch/arm/include/asm/kvm_host.h
>>> @@ -21,6 +21,7 @@
>>>
>>> #include <asm/kvm.h>
>>> #include <asm/kvm_asm.h>
>>> +#include <asm/fpstate.h>
>>>
>>> #define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
>>> #define KVM_USER_MEM_SLOTS 32
>>> @@ -85,6 +86,14 @@ struct kvm_vcpu_arch {
>>> u32 hxfar; /* Hyp Data/Inst Fault Address Register */
>>> u32 hpfar; /* Hyp IPA Fault Address Register */
>>>
>>> + /* Floating point registers (VFP and Advanced SIMD/NEON) */
>>> + struct vfp_hard_struct vfp_guest;
>>> + struct vfp_hard_struct *vfp_host;
>>> +
>>> + /*
>>> + * Anything that is not used directly from assembly code goes
>>> + * here.
>>> + */
>>> /* Interrupt related fields */
>>> u32 irq_lines; /* IRQ and FIQ levels */
>>>
>>> @@ -112,6 +121,7 @@ struct kvm_one_reg;
>>> int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
>>> int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
>>> u64 kvm_call_hyp(void *hypfn, ...);
>>> +void force_vm_exit(const cpumask_t *mask);
>>>
>>> #define KVM_ARCH_WANT_MMU_NOTIFIER
>>> struct kvm;
>>> diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
>>> index c985b48..c8b3272 100644
>>> --- a/arch/arm/kernel/asm-offsets.c
>>> +++ b/arch/arm/kernel/asm-offsets.c
>>> @@ -13,6 +13,9 @@
>>> #include <linux/sched.h>
>>> #include <linux/mm.h>
>>> #include <linux/dma-mapping.h>
>>> +#ifdef CONFIG_KVM_ARM_HOST
>>> +#include <linux/kvm_host.h>
>>> +#endif
>>> #include <asm/cacheflush.h>
>>> #include <asm/glue-df.h>
>>> #include <asm/glue-pf.h>
>>> @@ -146,5 +149,27 @@ int main(void)
>>> DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
>>> DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
>>> DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
>>> +#ifdef CONFIG_KVM_ARM_HOST
>>> + DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
>>> + DEFINE(VCPU_MIDR, offsetof(struct kvm_vcpu, arch.midr));
>>> + DEFINE(VCPU_CP15, offsetof(struct kvm_vcpu, arch.cp15));
>>> + DEFINE(VCPU_VFP_GUEST, offsetof(struct kvm_vcpu, arch.vfp_guest));
>>> + DEFINE(VCPU_VFP_HOST, offsetof(struct kvm_vcpu, arch.vfp_host));
>>> + DEFINE(VCPU_REGS, offsetof(struct kvm_vcpu, arch.regs));
>>> + DEFINE(VCPU_USR_REGS, offsetof(struct kvm_vcpu, arch.regs.usr_regs));
>>> + DEFINE(VCPU_SVC_REGS, offsetof(struct kvm_vcpu, arch.regs.svc_regs));
>>> + DEFINE(VCPU_ABT_REGS, offsetof(struct kvm_vcpu, arch.regs.abt_regs));
>>> + DEFINE(VCPU_UND_REGS, offsetof(struct kvm_vcpu, arch.regs.und_regs));
>>> + DEFINE(VCPU_IRQ_REGS, offsetof(struct kvm_vcpu, arch.regs.irq_regs));
>>> + DEFINE(VCPU_FIQ_REGS, offsetof(struct kvm_vcpu, arch.regs.fiq_regs));
>>> + DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc));
>>> + DEFINE(VCPU_CPSR, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr));
>>> + DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines));
>>> + DEFINE(VCPU_HSR, offsetof(struct kvm_vcpu, arch.hsr));
>>> + DEFINE(VCPU_HxFAR, offsetof(struct kvm_vcpu, arch.hxfar));
>>> + DEFINE(VCPU_HPFAR, offsetof(struct kvm_vcpu, arch.hpfar));
>>> + DEFINE(VCPU_HYP_PC, offsetof(struct kvm_vcpu, arch.hyp_pc));
>>> + DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr));
>>> +#endif
>>> return 0;
>>> }
>>> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
>>> index 9b4566e..c94d278 100644
>>> --- a/arch/arm/kvm/arm.c
>>> +++ b/arch/arm/kvm/arm.c
>>> @@ -40,6 +40,7 @@
>>> #include <asm/kvm_arm.h>
>>> #include <asm/kvm_asm.h>
>>> #include <asm/kvm_mmu.h>
>>> +#include <asm/kvm_emulate.h>
>>>
>>> #ifdef REQUIRES_VIRT
>>> __asm__(".arch_extension virt");
>>> @@ -49,6 +50,10 @@ static DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_page);
>>> static struct vfp_hard_struct __percpu *kvm_host_vfp_state;
>>> static unsigned long hyp_default_vectors;
>>>
>>> +/* The VMID used in the VTTBR */
>>> +static atomic64_t kvm_vmid_gen = ATOMIC64_INIT(1);
>>> +static u8 kvm_next_vmid;
>>> +static DEFINE_SPINLOCK(kvm_vmid_lock);
>>>
>>> int kvm_arch_hardware_enable(void *garbage)
>>> {
>>> @@ -276,6 +281,8 @@ int __attribute_const__ kvm_target_cpu(void)
>>>
>>> int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
>>> {
>>> + /* Force users to call KVM_ARM_VCPU_INIT */
>>> + vcpu->arch.target = -1;
>>> return 0;
>>> }
>>>
>>> @@ -286,6 +293,7 @@ void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
>>> void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
>>> {
>>> vcpu->cpu = cpu;
>>> + vcpu->arch.vfp_host = this_cpu_ptr(kvm_host_vfp_state);
>>> }
>>>
>>> void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
>>> @@ -318,12 +326,189 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
>>>
>>> int kvm_arch_vcpu_in_guest_mode(struct kvm_vcpu *v)
>> As far as I see the function is unused.
>>
>>> {
>>> + return v->mode == IN_GUEST_MODE;
>>> +}
>>> +
>>> +/* Just ensure a guest exit from a particular CPU */
>>> +static void exit_vm_noop(void *info)
>>> +{
>>> +}
>>> +
>>> +void force_vm_exit(const cpumask_t *mask)
>>> +{
>>> + smp_call_function_many(mask, exit_vm_noop, NULL, true);
>>> +}
>> There is make_all_cpus_request() for that. It actually sends IPIs only
>> to cpus that are running vcpus.
>>
>>> +
>>> +/**
>>> + * need_new_vmid_gen - check that the VMID is still valid
>>> + * @kvm: The VM's VMID to checkt
>>> + *
>>> + * return true if there is a new generation of VMIDs being used
>>> + *
>>> + * The hardware supports only 256 values with the value zero reserved for the
>>> + * host, so we check if an assigned value belongs to a previous generation,
>>> + * which which requires us to assign a new value. If we're the first to use a
>>> + * VMID for the new generation, we must flush necessary caches and TLBs on all
>>> + * CPUs.
>>> + */
>>> +static bool need_new_vmid_gen(struct kvm *kvm)
>>> +{
>>> + return unlikely(kvm->arch.vmid_gen != atomic64_read(&kvm_vmid_gen));
>>> +}
>>> +
>>> +/**
>>> + * update_vttbr - Update the VTTBR with a valid VMID before the guest runs
>>> + * @kvm The guest that we are about to run
>>> + *
>>> + * Called from kvm_arch_vcpu_ioctl_run before entering the guest to ensure the
>>> + * VM has a valid VMID, otherwise assigns a new one and flushes corresponding
>>> + * caches and TLBs.
>>> + */
>>> +static void update_vttbr(struct kvm *kvm)
>>> +{
>>> + phys_addr_t pgd_phys;
>>> + u64 vmid;
>>> +
>>> + if (!need_new_vmid_gen(kvm))
>>> + return;
>>> +
>>> + spin_lock(&kvm_vmid_lock);
>>> +
>>> + /*
>>> + * We need to re-check the vmid_gen here to ensure that if another vcpu
>>> + * already allocated a valid vmid for this vm, then this vcpu should
>>> + * use the same vmid.
>>> + */
>>> + if (!need_new_vmid_gen(kvm)) {
>>> + spin_unlock(&kvm_vmid_lock);
>>> + return;
>>> + }
>>> +
>>> + /* First user of a new VMID generation? */
>>> + if (unlikely(kvm_next_vmid == 0)) {
>>> + atomic64_inc(&kvm_vmid_gen);
>>> + kvm_next_vmid = 1;
>>> +
>>> + /*
>>> + * On SMP we know no other CPUs can use this CPU's or each
>>> + * other's VMID after force_vm_exit returns since the
>>> + * kvm_vmid_lock blocks them from reentry to the guest.
>>> + */
>>> + force_vm_exit(cpu_all_mask);
>>> + /*
>>> + * Now broadcast TLB + ICACHE invalidation over the inner
>>> + * shareable domain to make sure all data structures are
>>> + * clean.
>>> + */
>>> + kvm_call_hyp(__kvm_flush_vm_context);
>>> + }
>>> +
>>> + kvm->arch.vmid_gen = atomic64_read(&kvm_vmid_gen);
>>> + kvm->arch.vmid = kvm_next_vmid;
>>> + kvm_next_vmid++;
>>> +
>>> + /* update vttbr to be used with the new vmid */
>>> + pgd_phys = virt_to_phys(kvm->arch.pgd);
>>> + vmid = ((u64)(kvm->arch.vmid) << VTTBR_VMID_SHIFT) & VTTBR_VMID_MASK;
>>> + kvm->arch.vttbr = pgd_phys & VTTBR_BADDR_MASK;
>>> + kvm->arch.vttbr |= vmid;
>>> +
>>> + spin_unlock(&kvm_vmid_lock);
>>> +}
>>> +
>>> +/*
>>> + * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
>>> + * proper exit to QEMU.
>>> + */
>>> +static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
>>> + int exception_index)
>>> +{
>>> + run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
>>> return 0;
>>> }
>>>
>>> +/**
>>> + * kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code
>>> + * @vcpu: The VCPU pointer
>>> + * @run: The kvm_run structure pointer used for userspace state exchange
>>> + *
>>> + * This function is called through the VCPU_RUN ioctl called from user space. It
>>> + * will execute VM code in a loop until the time slice for the process is used
>>> + * or some emulation is needed from user space in which case the function will
>>> + * return with return value 0 and with the kvm_run structure filled in with the
>>> + * required data for the requested emulation.
>>> + */
>>> int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
>>> {
>>> - return -EINVAL;
>>> + int ret;
>>> + sigset_t sigsaved;
>>> +
>>> + /* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
>>> + if (unlikely(vcpu->arch.target < 0))
>>> + return -ENOEXEC;
>>> +
>>> + if (vcpu->sigset_active)
>>> + sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
>>> +
>>> + ret = 1;
>>> + run->exit_reason = KVM_EXIT_UNKNOWN;
>>> + while (ret > 0) {
>>> + /*
>>> + * Check conditions before entering the guest
>>> + */
>>> + cond_resched();
>>> +
>>> + update_vttbr(vcpu->kvm);
>>> +
>>> + local_irq_disable();
>>> +
>>> + /*
>>> + * Re-check atomic conditions
>>> + */
>>> + if (signal_pending(current)) {
>>> + ret = -EINTR;
>>> + run->exit_reason = KVM_EXIT_INTR;
>>> + }
>>> +
>>> + if (ret <= 0 || need_new_vmid_gen(vcpu->kvm)) {
>>> + local_irq_enable();
>>> + continue;
>>> + }
>>> +
>>> + /**************************************************************
>>> + * Enter the guest
>>> + */
>>> + trace_kvm_entry(*vcpu_pc(vcpu));
>>> + kvm_guest_enter();
>>> + vcpu->mode = IN_GUEST_MODE;
>> You need to set mode to IN_GUEST_MODE before disabling interrupt and
>> check that mode != EXITING_GUEST_MODE after disabling interrupt but
>> before entering the guest. This way you will catch kicks that were sent
>> between setting of the mode and disabling the interrupts. Also you need
>> to check vcpu->requests and exit if it is not empty. I see that you do
>> not use vcpu->requests at all, but you should since common kvm code
>> assumes that it is used. make_all_cpus_request() uses it for instance.
>>
>
> I don't quite agree, but almost:
>
> Why would you set IN_GUEST_MODE before disabling interrupts? The only
> reason I can see for to be a requirement is to leverage an implicit
> memory barrier. Receiving the IPI in this little window does nothing
> (the smp_cross_call is a noop).
>
> Checking that mode != EXITING_GUEST_MODE is equally useless in my
> opinion, as I read the requests code the only reason for this mode is
> to avoid sending an IPI twice.
>
> Kicks sent between setting the mode and disabling the interrupts is
> not the point, the point is to check the requests field (which we
> don't use at all on ARM, and generic code also doesn't use on ARM)
> after disabling interrupts, and after setting IN_GUEST_MODE.
>
> The patch below fixes your issues, and while I would push back on
> anything else than direct bug fixes at this point, the current code is
> semantically incorrect wrt. KVM vcpu requests, so it's worth a fix,
> and the patch itself is trivial.
>
[...]
Actually, I take that back, the kvm_vcpu_block function does make a
request, which we don't need to handle, so adding code that checks for
features we don't support is useless at this point. Please ignore the
patch I sent earlier.
Later on we can change some of the code to use the vcpu->features map
if there's a real benefit, but right now the priority is to merge this
code, so anything that's not a bugfix should not go in.
The srcu lock is a real bug though, and should be fixed.
-Christoffer
^ permalink raw reply
* [GIT PULL v2] Renesas ARM-based SoC defconfig for v3.9
From: Simon Horman @ 2013-01-16 4:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358210975-26970-1-git-send-email-horms+renesas@verge.net.au>
On Tue, Jan 15, 2013 at 09:49:30AM +0900, Simon Horman wrote:
> Hi Olof, Hi Arnd,
>
> please consider the following defconfig enhancements for 3.9.
Please ignore this, I will send an updated pull request.
> ----------------------------------------------------------------
> The following changes since commit a49f0d1ea3ec94fc7cf33a7c36a16343b74bd565:
>
> Linux 3.8-rc1 (2012-12-21 17:19:00 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git
>
> for you to fetch changes up to 8098df15c26b2bf16924df5a134d1a649692ab62:
>
> ARM: mach-shmobile: kzm9d: update defconfig (2013-01-15 08:57:09 +0900)
>
> ----------------------------------------------------------------
> Simon Horman (5):
> ARM: mach-shmobile: mackerel: update defconfig
> ARM: mach-shmobile: fix memory size for kota2_defconfig
> ARM: mach-shmobile: kzm9g: defconfig update
> ARM: mach-shmobile: armadillo: update defconfig
> ARM: mach-shmobile: kzm9d: update defconfig
>
> arch/arm/boot/dts/emev2-kzm9d.dts | 2 +-
> arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 4 ++++
> arch/arm/boot/dts/sh7372-mackerel.dts | 4 ++++
> arch/arm/boot/dts/sh73a0-kzm9g.dts | 4 ++++
> arch/arm/configs/armadillo800eva_defconfig | 5 ++---
> arch/arm/configs/kota2_defconfig | 2 +-
> arch/arm/configs/kzm9d_defconfig | 4 +---
> arch/arm/configs/kzm9g_defconfig | 4 +++-
> arch/arm/configs/mackerel_defconfig | 2 +-
> 9 files changed, 21 insertions(+), 10 deletions(-)
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* linux-next: manual merge of the tegra tree with the arm-soc tree
From: Tony Prisk @ 2013-01-16 3:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130116141411.8fadedee54ed35dc0eddd288@canb.auug.org.au>
On Wed, 2013-01-16 at 14:14 +1100, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the tegra tree got a conflict in
> drivers/clocksource/Makefile between commit ff7ec345f0ec ("timer: vt8500:
> Move timer code to drivers/clocksource") from the arm-soc tree and commit
> ac0fd9eca3ba ("ARM: tegra: move timer.c to drivers/clocksource/") from
> the tegra tree.
>
> I fixed it up (see below) and can carry the fix as necessary (no action
> is required).
>
I don't know about everyone else, but I feel the preference should be to
keep things alphabetized where possible to help avoid with merge
conflicts later on. This is always a problem when we start tacking
things on the end of lists.
I realise this Kconfig is not alphabetized anyway, but it's never too
early to start on the 'right' path.
Regards
Tony P
^ permalink raw reply
* [PATCH V4 3/3] ARM: davinci: da850: add NAND driver DT entries
From: Kumar, Anil @ 2013-01-16 3:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358308102-8169-1-git-send-email-anilkumar.v@ti.com>
Add NAND driver DT node and related pinctrl DT data to export NAND
functionality on da850 evm.
Signed-off-by: Kumar, Anil <anilkumar.v@ti.com>
---
:100644 100644 c7609d0... 433027f... M arch/arm/boot/dts/da850-evm.dts
:100644 100644 e9c6e82... 59e6ea4... M arch/arm/boot/dts/da850.dtsi
arch/arm/boot/dts/da850-evm.dts | 5 +++++
arch/arm/boot/dts/da850.dtsi | 30 ++++++++++++++++++++++++++++++
2 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index c7609d0..433027f 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -28,4 +28,9 @@
status = "okay";
};
};
+ nand_cs3 at 62000000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_cs3_pins>;
+ };
};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index e9c6e82..59e6ea4 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -38,6 +38,23 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
status = "disabled";
+
+ nand_cs3_pins: pinmux_nand_pins {
+ pinctrl-single,bits = <
+ /* EMA_OE, EMA_WE */
+ 0x1c 0x00110000 0x00ff0000
+ /* EMA_CS[4],EMA_CS[3]*/
+ 0x1c 0x00000110 0x00000ff0
+ /*
+ * EMA_D[0], EMA_D[1], EMA_D[2],
+ * EMA_D[3], EMA_D[4], EMA_D[5],
+ * EMA_D[6], EMA_D[7]
+ */
+ 0x24 0x11111111 0xffffffff
+ /* EMA_A[1], EMA_A[2] */
+ 0x30 0x01100000 0x0ff00000
+ >;
+ };
};
serial0: serial at 1c42000 {
compatible = "ns16550a";
@@ -67,4 +84,17 @@
status = "disabled";
};
};
+ nand_cs3 at 62000000 {
+ compatible = "ti,davinci-nand";
+ reg = <0x62000000 0x807ff
+ 0x68000000 0x8000>;
+ ti,davinci-chipselect = <1>;
+ ti,davinci-mask-ale = <0>;
+ ti,davinci-mask-cle = <0>;
+ ti,davinci-mask-chipsel = <0>;
+ ti,davinci-ecc-mode = "hw";
+ ti,davinci-ecc-bits = <4>;
+ ti,davinci-nand-use-bbt;
+ status = "disabled";
+ };
};
--
1.7.4.1
^ permalink raw reply related
* [PATCH V4 2/3] ARM: davinci: da8xx defconfig: enable pinctrl config option
From: Kumar, Anil @ 2013-01-16 3:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358308102-8169-1-git-send-email-anilkumar.v@ti.com>
Enable pinctrl related config option in da8xx_omapl_defconfig
Signed-off-by: Kumar, Anil <anilkumar.v@ti.com>
---
:100644 100644 f292239... 0892db4... M arch/arm/configs/da8xx_omapl_defconfig
arch/arm/configs/da8xx_omapl_defconfig | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig
index f292239..0892db4 100644
--- a/arch/arm/configs/da8xx_omapl_defconfig
+++ b/arch/arm/configs/da8xx_omapl_defconfig
@@ -81,6 +81,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DAVINCI=y
+CONFIG_PINCTRL_SINGLE=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_REGULATOR=y
--
1.7.4.1
^ permalink raw reply related
* [PATCH V4 1/3] ARM: davinci: da850: add pinctrl driver DT entries
From: Kumar, Anil @ 2013-01-16 3:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358308102-8169-1-git-send-email-anilkumar.v@ti.com>
For DT, DaVinci platform can use pinctrl-single driver for handling
padconf registers.
Enable PINCTRL Kconfig for MACH_DA8XX_DT platform. Add required
pinctrl DT entries in da850 dts file.
Test procedure
1)Populate DT file with NAND node information.
2)Populate board DT file with pinmux information for NAND.
3)Boot and confirm NAND is detected by the kernel.
4)cat /proc/mtd to show partitions.
Signed-off-by: Kumar, Anil <anilkumar.v@ti.com>
---
:100644 100644 37dc5a3... c7609d0... M arch/arm/boot/dts/da850-evm.dts
:100644 100644 fbada87... e9c6e82... M arch/arm/boot/dts/da850.dtsi
:100644 100644 0153950... a075b3e... M arch/arm/mach-davinci/Kconfig
arch/arm/boot/dts/da850-evm.dts | 3 +++
arch/arm/boot/dts/da850.dtsi | 10 ++++++++++
arch/arm/mach-davinci/Kconfig | 1 +
3 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 37dc5a3..c7609d0 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -15,6 +15,9 @@
model = "DA850/AM1808/OMAP-L138 EVM";
soc {
+ pmx_core:pinmux at 1c14120 {
+ status = "okay";
+ };
serial0: serial at 1c42000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index fbada87..e9c6e82 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -29,6 +29,16 @@
#size-cells = <1>;
ranges = <0x0 0x01c00000 0x400000>;
+ pmx_core:pinmux at 1c14120 {
+ compatible = "pinctrl-single";
+ reg = <0x14120 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,bit-per-mux;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ status = "disabled";
+ };
serial0: serial at 1c42000 {
compatible = "ns16550a";
reg = <0x42000 0x100>;
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0153950..a075b3e 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -62,6 +62,7 @@ config MACH_DA8XX_DT
bool "Support DA8XX platforms using device tree"
default y
depends on ARCH_DAVINCI_DA8XX
+ select PINCTRL
help
Say y here to include support for TI DaVinci DA850 based using
Flattened Device Tree. More information at Documentation/devicetree
--
1.7.4.1
^ permalink raw reply related
* [PATCH V4 0/3] ARM: davinci: da850: add pinctrl support
From: Kumar, Anil @ 2013-01-16 3:48 UTC (permalink / raw)
To: linux-arm-kernel
This set of patches adds:
* Add pinctrl-single for handling Padconf registers.
* Add NAND node to export NAND functionality on da850 EVM.
* Add NAND pinctrl node to do pin mux according to pinctrl-single driver.
This series applies on top of tag next-20130107 git tree
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
and the following patch
-drivers/pinctrl: grab default handles from device core
https://patchwork.kernel.org/patch/1862231/
This series is tested on da850 EVM.
Changes since V3:
-Move NAND related pinctrl DT data into the da850.dtsi file so it can
be reused.
Changes since V2:
-Move NAND pins configuration into the nand_cs3 DT node to avoid pins
configuration if it is not probed.
Changes since V1:
-Remove the binding documentation as already documented as part of
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
-Enable PINCTRL Kconfig for MACH_DA8XX_DT platform only.
-Fix the pinctrl driver node unit-address.
-Make separate patch for da8xx_omapl_defconfig changes.
Kumar, Anil (3):
ARM: davinci: da850: add pinctrl driver DT entries
ARM: davinci: da8xx defconfig: enable pinctrl config option
ARM: davinci: da850: add NAND driver DT entries
arch/arm/boot/dts/da850-evm.dts | 8 ++++++
arch/arm/boot/dts/da850.dtsi | 40 ++++++++++++++++++++++++++++++++
arch/arm/configs/da8xx_omapl_defconfig | 1 +
arch/arm/mach-davinci/Kconfig | 1 +
4 files changed, 50 insertions(+), 0 deletions(-)
--
1.7.4.1
^ permalink raw reply
* [PATCH v2] mm: dmapool: use provided gfp flags for all dma_alloc_coherent() calls
From: Soeren Moch @ 2013-01-16 3:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130116024014.GH25500@titan.lakedaemon.net>
On 16.01.2013 03:40, Jason Cooper wrote:
> Soeren,
>
> On Wed, Jan 16, 2013 at 01:17:59AM +0100, Soeren Moch wrote:
>> On 15.01.2013 22:56, Jason Cooper wrote:
>>> On Tue, Jan 15, 2013 at 03:16:17PM -0500, Jason Cooper wrote:
>>>> If my understanding is correct, one of the drivers (most likely one)
>>>> either asks for too small of a dma buffer, or is not properly
>>>> deallocating blocks from the per-device pool. Either case leads to
>>>> exhaustion, and falling back to the atomic pool. Which subsequently
>>>> gets wiped out as well.
>>>
>>> If my hunch is right, could you please try each of the three dvb drivers
>>> in turn and see which one (or more than one) causes the error?
>>
>> In fact I use only 2 types of DVB sticks: em28xx usb bridge plus drxk
>> demodulator, and dib0700 usb bridge plus dib7000p demod.
>>
>> I would bet for em28xx causing the error, but this is not thoroughly
>> tested. Unfortunately testing with removed sticks is not easy, because
>> this is a production system and disabling some services for the long
>> time we need to trigger this error will certainly result in unhappy
>> users.
>
> Just out of curiosity, what board is it?
The kirkwood board? A modified Guruplug Server Plus.
>
>> I will see what I can do here. Is there an easy way to track the buffer
>> usage without having to wait for complete exhaustion?
>
> DMA_API_DEBUG
OK, maybe I can try this.
>
>> In linux-3.5.x there is no such problem. Can we use all available memory
>> for dma buffers here on armv5 architectures, in contrast to newer
>> kernels?
>
> Were the loads exactly the same when you tested 3.5.x?
Exactly the same, yes.
>I looked at the
> changes from v3.5 to v3.7.1 for all four drivers you mentioned as well
> as sata_mv.
>
> The biggest thing I see is that all of the media drivers got shuffled
> around into their own subdirectories after v3.5. 'git show -M 0c0d06c'
> shows it was a clean copy of all the files.
>
> What would be most helpful is if you could do a git bisect between
> v3.5.x (working) and the oldest version where you know it started
> failing (v3.7.1 or earlier if you know it).
>
I did not bisect it, but Marek mentioned earlier that commit
e9da6e9905e639b0f842a244bc770b48ad0523e9 in Linux v3.6-rc1 introduced
new code for dma allocations. This is probably the root cause for the
new (mis-)behavior (due to my tests 3.6.0 is not working anymore).
I'm not very familiar with arm mm code, and from the patch itself I
cannot understand what's different. Maybe CONFIG_CMA is default
also for armv5 (not only v6) now? But I might be totally wrong here,
maybe someone of the mm experts can explain the difference?
Regards,
Soeren
^ permalink raw reply
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