* [PATCH v5 07/14] KVM: ARM: World-switch implementation
From: Christoffer Dall @ 2013-01-16 15:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130116121238.GS11529@redhat.com>
[...]
>
>> read side RCU protects against is the memslots data structure as far
>> as I can see, so the second patch pasted below fixes this for the code
>> that actually accesses this data structure.
> Many memory related functions that you call access memslots under the
> hood and assume that locking is done by the caller. From the quick look
> I found those that you've missed:
> kvm_is_visible_gfn()
> kvm_read_guest()
> gfn_to_hva()
> gfn_to_pfn_prot()
> kvm_memslots()
>
> May be there are more. Can you enable RCU debugging in your kernel config
> and check? This does not guaranty that it will catch all of the places,
> but better than nothing.
>
yeah, I missed the call to is_visible_gfn and friends, this fixes it:
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index c806080..f30e131 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -591,7 +591,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu,
struct kvm_run *run)
struct kvm_memory_slot *memslot;
bool is_iabt;
gfn_t gfn;
- int ret;
+ int ret, idx;
hsr_ec = vcpu->arch.hsr >> HSR_EC_SHIFT;
is_iabt = (hsr_ec == HSR_EC_IABT);
@@ -608,33 +608,43 @@ int kvm_handle_guest_abort(struct kvm_vcpu
*vcpu, struct kvm_run *run)
return -EFAULT;
}
+ idx = srcu_read_lock(&vcpu->kvm->srcu);
+
gfn = fault_ipa >> PAGE_SHIFT;
if (!kvm_is_visible_gfn(vcpu->kvm, gfn)) {
if (is_iabt) {
/* Prefetch Abort on I/O address */
kvm_inject_pabt(vcpu, vcpu->arch.hxfar);
- return 1;
+ ret = 1;
+ goto out_unlock;
}
if (fault_status != FSC_FAULT) {
kvm_err("Unsupported fault status on io memory: %#lx\n",
fault_status);
- return -EFAULT;
+ ret = -EFAULT;
+ goto out_unlock;
}
/* Adjust page offset */
fault_ipa |= vcpu->arch.hxfar & ~PAGE_MASK;
- return io_mem_abort(vcpu, run, fault_ipa);
+ ret = io_mem_abort(vcpu, run, fault_ipa);
+ goto out_unlock;
}
memslot = gfn_to_memslot(vcpu->kvm, gfn);
if (!memslot->user_alloc) {
kvm_err("non user-alloc memslots not supported\n");
- return -EINVAL;
+ ret = -EINVAL;
+ goto out_unlock;
}
ret = user_mem_abort(vcpu, fault_ipa, gfn, memslot, fault_status);
- return ret ? ret : 1;
+ if (ret == 0)
+ ret = 1;
+out_unlock:
+ srcu_read_unlock(&vcpu->kvm->srcu, idx);
+ return ret;
}
static void handle_hva_to_gpa(struct kvm *kvm,
--
Thanks,
-Christoffer
^ permalink raw reply related
* [PATCH v5 07/14] KVM: ARM: World-switch implementation
From: Christoffer Dall @ 2013-01-16 15:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130116125712.GT11529@redhat.com>
[...]
>>
>
> Agree. Lets merge it and change later. The vcpu run loop is simple
> enough at this point. The question of using vcpu->requests is not
> the question of "real benefit" though, of course you can introduce your
> own mechanism to pass requests to vcpus instead of using whatever kvm
> provides you. But from maintenance and code share point of view this
> is wrong thing to do. Looks at this code for instance:
>
> /* Kick out any which are still running. */
> kvm_for_each_vcpu(i, v, vcpu->kvm) {
> /* Guest could exit now, making cpu wrong. That's OK. */
> if (kvm_vcpu_exiting_guest_mode(v) == IN_GUEST_MODE) {
> force_vm_exit(get_cpu_mask(v->cpu));
> }
> }
>
> Why not make_all_cpus_request(vcpu->kvm, KVM_REQ_PAUSE)?
well for one, make_all_cpus_request is a static function in kvm_main.c
and the semantics of that one is really tricky with respect to locking
and requires (imho) a much clearer explanation with commenting (see
separate e-mail to kvm list). And now is not the time to do this.
>
> And I am not sure KVM_REQ_UNHALT is so useless to you in the first
> place. kvm_vcpu_block() can return even when vcpu is not runnable (if
> signal is pending). KVM_REQ_UNHALT is the way to check for that. Hmm
> this is actually looks like a BUG in the current code.
>
there's no guarantee that you won't be woken up from a WFI instruction
for spurious interrupts on ARM, so we don't care about this, we simply
return to the guest, and it must go back to sleep if that's what it
wants to do.
-Christoffer
^ permalink raw reply
* [PATCH v2 8/9] ARM: PRIMA2: add new SiRFmarco SMP SoC infrastructures
From: Mark Rutland @ 2013-01-16 15:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358315784-25104-4-git-send-email-Barry.Song@csr.com>
Hello,
On Wed, Jan 16, 2013 at 05:56:23AM +0000, Barry Song wrote:
> From: Barry Song <Baohua.Song@csr.com>
>
> this patch adds tick timer, smp entries and generic DT machine
> for SiRFmarco dual-core SMP chips.
>
> with the added marco, we change the defconfig, using the same
> defconfig, we get a zImage which can work on both prima2 and
> marco.
>
> Signed-off-by: Barry Song <Baohua.Song@csr.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/configs/prima2_defconfig | 3 +
> arch/arm/mach-prima2/Kconfig | 10 +
> arch/arm/mach-prima2/Makefile | 3 +
> arch/arm/mach-prima2/common.c | 40 ++++-
> arch/arm/mach-prima2/common.h | 11 +
> arch/arm/mach-prima2/headsmp.S | 79 ++++++++
> arch/arm/mach-prima2/hotplug.c | 41 ++++
> arch/arm/mach-prima2/platsmp.c | 170 +++++++++++++++++
> arch/arm/mach-prima2/timer-marco.c | 355 ++++++++++++++++++++++++++++++++++++
> 10 files changed, 712 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/mach-prima2/headsmp.S
> create mode 100644 arch/arm/mach-prima2/hotplug.c
> create mode 100644 arch/arm/mach-prima2/platsmp.c
> create mode 100644 arch/arm/mach-prima2/timer-marco.c
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index e44da40..6af9901 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
> kirkwood-ts219-6281.dtb \
> kirkwood-ts219-6282.dtb \
> kirkwood-openblocks_a6.dtb
> +dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
> dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
> msm8960-cdp.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
> diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
> index 6a936c7..002a1ce 100644
> --- a/arch/arm/configs/prima2_defconfig
> +++ b/arch/arm/configs/prima2_defconfig
> @@ -11,6 +11,9 @@ CONFIG_PARTITION_ADVANCED=y
> CONFIG_BSD_DISKLABEL=y
> CONFIG_SOLARIS_X86_PARTITION=y
> CONFIG_ARCH_SIRF=y
> +# CONFIG_SWP_EMULATE is not set
> +CONFIG_SMP=y
> +CONFIG_SCHED_MC=y
> CONFIG_PREEMPT=y
> CONFIG_AEABI=y
> CONFIG_KEXEC=y
> diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
> index 558ccfb..4f7379f 100644
> --- a/arch/arm/mach-prima2/Kconfig
> +++ b/arch/arm/mach-prima2/Kconfig
> @@ -11,6 +11,16 @@ config ARCH_PRIMA2
> help
> Support for CSR SiRFSoC ARM Cortex A9 Platform
>
> +config ARCH_MARCO
> + bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
> + default y
> + select ARM_GIC
> + select CPU_V7
> + select HAVE_SMP
> + select SMP_ON_UP
> + help
> + Support for CSR SiRFSoC ARM Cortex A9 Platform
> +
> endmenu
>
> config SIRF_IRQ
> diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
> index 0007a6e..bfe360c 100644
> --- a/arch/arm/mach-prima2/Makefile
> +++ b/arch/arm/mach-prima2/Makefile
> @@ -5,4 +5,7 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
> obj-$(CONFIG_CACHE_L2X0) += l2x0.o
> obj-$(CONFIG_SUSPEND) += pm.o sleep.o
> obj-$(CONFIG_SIRF_IRQ) += irq.o
> +obj-$(CONFIG_SMP) += platsmp.o headsmp.o
> +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
> obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
> +obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
> diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
> index 99f9c7e..00a6564 100644
> --- a/arch/arm/mach-prima2/common.c
> +++ b/arch/arm/mach-prima2/common.c
> @@ -8,9 +8,11 @@
>
> #include <linux/init.h>
> #include <linux/kernel.h>
> +#include <linux/of_irq.h>
> #include <asm/sizes.h>
> #include <asm/mach-types.h>
> #include <asm/mach/arch.h>
> +#include <asm/hardware/gic.h>
> #include <linux/of.h>
> #include <linux/of_platform.h>
> #include "common.h"
> @@ -30,6 +32,12 @@ void __init sirfsoc_init_late(void)
> sirfsoc_pm_init();
> }
>
> +static __init void sirfsoc_map_io(void)
> +{
> + sirfsoc_map_lluart();
> + sirfsoc_map_scu();
> +}
> +
> #ifdef CONFIG_ARCH_PRIMA2
> static const char *prima2_dt_match[] __initdata = {
> "sirf,prima2",
> @@ -38,7 +46,7 @@ static const char *prima2_dt_match[] __initdata = {
>
> DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
> /* Maintainer: Barry Song <baohua.song@csr.com> */
> - .map_io = sirfsoc_map_lluart,
> + .map_io = sirfsoc_map_io,
> .init_irq = sirfsoc_of_irq_init,
> .init_time = sirfsoc_prima2_timer_init,
> #ifdef CONFIG_MULTI_IRQ_HANDLER
> @@ -51,3 +59,33 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
> .restart = sirfsoc_restart,
> MACHINE_END
> #endif
> +
> +#ifdef CONFIG_ARCH_MARCO
> +static const struct of_device_id marco_irq_match[] __initconst = {
> + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
> + { /* sentinel */ }
> +};
> +
> +static void __init marco_init_irq(void)
> +{
> + of_irq_init(marco_irq_match);
> +}
> +
> +static const char *marco_dt_match[] __initdata = {
> + "sirf,marco",
> + NULL
> +};
> +
> +DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
> + /* Maintainer: Barry Song <baohua.song@csr.com> */
> + .smp = smp_ops(sirfsoc_smp_ops),
> + .map_io = sirfsoc_map_io,
> + .init_irq = marco_init_irq,
> + .init_time = sirfsoc_marco_timer_init,
> + .handle_irq = gic_handle_irq,
> + .init_machine = sirfsoc_mach_init,
> + .init_late = sirfsoc_init_late,
> + .dt_compat = marco_dt_match,
> + .restart = sirfsoc_restart,
> +MACHINE_END
> +#endif
> diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
> index a4f91a6..b7c26b6 100644
> --- a/arch/arm/mach-prima2/common.h
> +++ b/arch/arm/mach-prima2/common.h
> @@ -14,6 +14,11 @@
> #include <asm/exception.h>
>
> extern void sirfsoc_prima2_timer_init(void);
> +extern void sirfsoc_marco_timer_init(void);
> +
> +extern struct smp_operations sirfsoc_smp_ops;
> +extern void sirfsoc_secondary_startup(void);
> +extern void sirfsoc_cpu_die(unsigned int cpu);
>
> extern void __init sirfsoc_of_irq_init(void);
> extern void __init sirfsoc_of_clk_init(void);
> @@ -26,6 +31,12 @@ static inline void sirfsoc_map_lluart(void) {}
> extern void __init sirfsoc_map_lluart(void);
> #endif
>
> +#ifndef CONFIG_SMP
> +static inline void sirfsoc_map_scu(void) {}
> +#else
> +extern void sirfsoc_map_scu(void);
> +#endif
> +
> #ifdef CONFIG_SUSPEND
> extern int sirfsoc_pm_init(void);
> #else
> diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
> new file mode 100644
> index 0000000..6ec19d5
> --- /dev/null
> +++ b/arch/arm/mach-prima2/headsmp.S
> @@ -0,0 +1,79 @@
> +/*
> + * Entry of the second core for CSR Marco dual-core SMP SoCs
> + *
> + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
> + *
> + * Licensed under GPLv2 or later.
> + */
> +
> +#include <linux/linkage.h>
> +#include <linux/init.h>
> +
> + __INIT
> +/*
> + * Cold boot and hardware reset show different behaviour,
> + * system will be always panic if we warm-reset the board
> + * Here we invalidate L1 of CPU1 to make sure there isn't
> + * uninitialized data written into memory later
> + */
> +ENTRY(v7_invalidate_l1)
> + mov r0, #0
> + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
> + mcr p15, 2, r0, c0, c0, 0
> + mrc p15, 1, r0, c0, c0, 0
> +
> + ldr r1, =0x7fff
> + and r2, r1, r0, lsr #13
> +
> + ldr r1, =0x3ff
> +
> + and r3, r1, r0, lsr #3 @ NumWays - 1
> + add r2, r2, #1 @ NumSets
> +
> + and r0, r0, #0x7
> + add r0, r0, #4 @ SetShift
> +
> + clz r1, r3 @ WayShift
> + add r4, r3, #1 @ NumWays
> +1: sub r2, r2, #1 @ NumSets--
> + mov r3, r4 @ Temp = NumWays
> +2: subs r3, r3, #1 @ Temp--
> + mov r5, r3, lsl r1
> + mov r6, r2, lsl r0
> + orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
> + mcr p15, 0, r5, c7, c6, 2
> + bgt 2b
> + cmp r2, #0
> + bgt 1b
> + dsb
> + isb
> + mov pc, lr
> +ENDPROC(v7_invalidate_l1)
> +
> +/*
> + * SIRFSOC specific entry point for secondary CPUs. This provides
> + * a "holding pen" into which all secondary cores are held until we're
> + * ready for them to initialise.
> + */
> +ENTRY(sirfsoc_secondary_startup)
> + bl v7_invalidate_l1
> + mrc p15, 0, r0, c0, c0, 5
> + and r0, r0, #15
> + adr r4, 1f
> + ldmia r4, {r5, r6}
> + sub r4, r4, r5
> + add r6, r6, r4
> +pen: ldr r7, [r6]
> + cmp r7, r0
> + bne pen
> +
> + /*
> + * we've been released from the holding pen: secondary_stack
> + * should now contain the SVC stack for this core
> + */
> + b secondary_startup
> +ENDPROC(sirfsoc_secondary_startup)
> +
> + .align
> +1: .long .
> + .long pen_release
> diff --git a/arch/arm/mach-prima2/hotplug.c b/arch/arm/mach-prima2/hotplug.c
> new file mode 100644
> index 0000000..97c1ee5
> --- /dev/null
> +++ b/arch/arm/mach-prima2/hotplug.c
> @@ -0,0 +1,41 @@
> +/*
> + * CPU hotplug support for CSR Marco dual-core SMP SoCs
> + *
> + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
> + *
> + * Licensed under GPLv2 or later.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/errno.h>
> +#include <linux/smp.h>
> +
> +#include <asm/cacheflush.h>
> +#include <asm/smp_plat.h>
> +
> +static inline void platform_do_lowpower(unsigned int cpu)
> +{
> + flush_cache_all();
> +
> + /* we put the platform to just WFI */
> + for (;;) {
> + __asm__ __volatile__("dsb\n\t" "wfi\n\t"
> + : : : "memory");
> + if (pen_release == cpu_logical_map(cpu)) {
> + /*
> + * OK, proper wakeup, we're done
> + */
> + break;
> + }
> + }
> +}
> +
> +/*
> + * platform-specific code to shutdown a CPU
> + *
> + * Called with IRQs disabled
> + */
> +void sirfsoc_cpu_die(unsigned int cpu)
> +{
> + platform_do_lowpower(cpu);
> +}
> diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
> new file mode 100644
> index 0000000..b939e9b4
> --- /dev/null
> +++ b/arch/arm/mach-prima2/platsmp.c
> @@ -0,0 +1,170 @@
> +/*
> + * plat smp support for CSR Marco dual-core SMP SoCs
> + *
> + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
> + *
> + * Licensed under GPLv2 or later.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/smp.h>
> +#include <linux/delay.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <asm/page.h>
> +#include <asm/mach/map.h>
> +#include <asm/smp_plat.h>
> +#include <asm/smp_scu.h>
> +#include <asm/cacheflush.h>
> +#include <asm/cputype.h>
> +#include <asm/hardware/gic.h>
> +#include <mach/map.h>
> +
> +#include "common.h"
> +
> +static void __iomem *scu_base;
> +static void __iomem *rsc_base;
> +
> +static DEFINE_SPINLOCK(boot_lock);
> +
> +static struct map_desc scu_io_desc __initdata = {
> + .length = SZ_4K,
> + .type = MT_DEVICE,
> +};
> +
> +void __init sirfsoc_map_scu(void)
> +{
> + unsigned long base;
> +
> + /* Get SCU base */
> + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
> +
> + scu_io_desc.virtual = SIRFSOC_VA(base);
> + scu_io_desc.pfn = __phys_to_pfn(base);
> + iotable_init(&scu_io_desc, 1);
> +
> + scu_base = (void __iomem *)SIRFSOC_VA(base);
> +}
> +
> +static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
> +{
> + /*
> + * if any interrupts are already enabled for the primary
> + * core (e.g. timer irq), then they will not have been enabled
> + * for us: do so
> + */
> + gic_secondary_init(0);
> +
> + /*
> + * let the primary processor know we're out of the
> + * pen, then head off into the C entry point
> + */
> + pen_release = -1;
> + smp_wmb();
> +
> + /*
> + * Synchronise with the boot thread.
> + */
> + spin_lock(&boot_lock);
> + spin_unlock(&boot_lock);
> +}
> +
> +static struct of_device_id rsc_ids[] = {
> + { .compatible = "sirf,marco-rsc" },
> + {},
> +};
> +
> +static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> + unsigned long timeout;
> + struct device_node *np;
> +
> + np = of_find_matching_node(NULL, rsc_ids);
> + if (!np)
> + return -ENODEV;
> +
> + rsc_base = of_iomap(np, 0);
> + if (!rsc_base)
> + return -ENOMEM;
> +
> + /*
> + * write the address of secondary startup into the sram register
> + * at offset 0x2C, then write the magic number 0x3CAF5D62 to the
> + * RSC register at offset 0x28, which is what boot rom code is
> + * waiting for. This would wake up the secondary core from WFE
> + */
> +#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C
> + __raw_writel(virt_to_phys(sirfsoc_secondary_startup),
> + rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
> +
> +#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28
> + __raw_writel(0x3CAF5D62,
> + rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
> +
> + /* make sure write buffer is drained */
> + mb();
> +
> + spin_lock(&boot_lock);
> +
> + /*
> + * The secondary processor is waiting to be released from
> + * the holding pen - release it, then wait for it to flag
> + * that it has been released by resetting pen_release.
> + *
> + * Note that "pen_release" is the hardware CPU ID, whereas
> + * "cpu" is Linux's internal ID.
> + */
> + pen_release = cpu_logical_map(cpu);
> + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
> + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
> +
> + /*
> + * Send the secondary CPU SEV, thereby causing the boot monitor to read
> + * the JUMPADDR and WAKEMAGIC, and branch to the address found there.
> + */
> + dsb_sev();
> +
> + timeout = jiffies + (1 * HZ);
> + while (time_before(jiffies, timeout)) {
> + smp_rmb();
> + if (pen_release == -1)
> + break;
> +
> + udelay(10);
> + }
> +
> + /*
> + * now the secondary core is starting up let it run its
> + * calibrations, then wait for it to finish
> + */
> + spin_unlock(&boot_lock);
> +
> + return pen_release != -1 ? -ENOSYS : 0;
> +}
> +
> +static void __init sirfsoc_smp_init_cpus(void)
> +{
> + int i, ncores;
> +
> + ncores = scu_get_core_count(scu_base);
> +
> + for (i = 0; i < ncores; i++)
> + set_cpu_possible(i, true);
> +
> + set_smp_cross_call(gic_raise_softirq);
> +}
You don't need to use scu_get_core_count to figure out which cpus to set
possible. It duplicates work already done by arm_dt_init_cpu_maps, and doesn't
initialise the logical map (as arm_dt_init_cpu_maps does).
You're already relying on the arm_dt_init_cpu_maps to set up the logical map
for the holding pen release, so you may as well rely on it to set_cpu_possible
for each of the cpus described in the dt.
Tegra is already on its way to doing this:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-December/138319.html
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-January/140219.html
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-January/141596.html
> +
> +static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus)
> +{
> + scu_enable(scu_base);
> +}
> +
> +struct smp_operations sirfsoc_smp_ops __initdata = {
> + .smp_init_cpus = sirfsoc_smp_init_cpus,
> + .smp_prepare_cpus = sirfsoc_smp_prepare_cpus,
> + .smp_secondary_init = sirfsoc_secondary_init,
> + .smp_boot_secondary = sirfsoc_boot_secondary,
> +#ifdef CONFIG_HOTPLUG_CPU
> + .cpu_die = sirfsoc_cpu_die,
> +#endif
> +};
The timer below is a big chunk of code, it'd be nicer if it had a patch to
itself.
> diff --git a/arch/arm/mach-prima2/timer-marco.c b/arch/arm/mach-prima2/timer-marco.c
> new file mode 100644
> index 0000000..07b3a6b
> --- /dev/null
> +++ b/arch/arm/mach-prima2/timer-marco.c
> @@ -0,0 +1,355 @@
> +/*
> + * System timer for CSR SiRFprimaII
> + *
> + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
> + *
> + * Licensed under GPLv2 or later.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/interrupt.h>
> +#include <linux/clockchips.h>
> +#include <linux/clocksource.h>
> +#include <linux/bitops.h>
> +#include <linux/irq.h>
> +#include <linux/clk.h>
> +#include <linux/slab.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +#include <asm/sched_clock.h>
> +#include <asm/localtimer.h>
> +#include <asm/mach/time.h>
> +
> +#include "common.h"
> +
> +#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000
> +#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004
> +#define SIRFSOC_TIMER_MATCH_0 0x0018
> +#define SIRFSOC_TIMER_MATCH_1 0x001c
> +#define SIRFSOC_TIMER_COUNTER_0 0x0048
> +#define SIRFSOC_TIMER_COUNTER_1 0x004c
> +#define SIRFSOC_TIMER_INTR_STATUS 0x0060
> +#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064
> +#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068
> +#define SIRFSOC_TIMER_64COUNTER_LO 0x006c
> +#define SIRFSOC_TIMER_64COUNTER_HI 0x0070
> +#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074
> +#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078
> +#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c
> +#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080
> +
> +#define SIRFSOC_TIMER_REG_CNT 6
> +
> +static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
> + SIRFSOC_TIMER_WATCHDOG_EN,
> + SIRFSOC_TIMER_32COUNTER_0_CTRL,
> + SIRFSOC_TIMER_32COUNTER_1_CTRL,
> + SIRFSOC_TIMER_64COUNTER_CTRL,
> + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
> + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
> +};
> +
> +static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
> +
> +static void __iomem *sirfsoc_timer_base;
> +static void __init sirfsoc_of_timer_map(void);
> +
> +/* disable count and interrupt */
> +static inline void sirfsoc_timer_count_disable(int idx)
> +{
> + writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
> + sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
> +}
> +
> +/* enable count and interrupt */
> +static inline void sirfsoc_timer_count_enable(int idx)
> +{
> + writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
> + sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
> +}
> +
> +/* timer0 interrupt handler */
> +static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
> +{
> + struct clock_event_device *ce = dev_id;
> +
> + /* clear timer0 interrupt */
> + writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
> +
> + if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
> + sirfsoc_timer_count_disable(0);
> +
> + ce->event_handler(ce);
> +
> + return IRQ_HANDLED;
> +}
> +
> +/* read 64-bit timer counter */
> +static cycle_t sirfsoc_timer_read(struct clocksource *cs)
> +{
> + u64 cycles;
> +
> + writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
> + BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
> +
> + cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
> + cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
> +
> + return cycles;
> +}
> +
> +static int sirfsoc_timer_set_next_event(unsigned long delta,
> + struct clock_event_device *ce)
> +{
> +
> + writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
> + writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
> +
> + /* enable the tick */
> + sirfsoc_timer_count_enable(0);
> +
> + return 0;
> +}
> +
> +static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
> + struct clock_event_device *ce)
> +{
> + switch (mode) {
> + case CLOCK_EVT_MODE_ONESHOT:
> + /* enable in set_next_event */
> + break;
> + default:
> + break;
> + }
> +
> + sirfsoc_timer_count_disable(0);
> +}
> +
> +static void sirfsoc_clocksource_suspend(struct clocksource *cs)
> +{
> + int i;
> +
> + for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
> + sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
> +}
> +
> +static void sirfsoc_clocksource_resume(struct clocksource *cs)
> +{
> + int i;
> +
> + for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
> + writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
> +
> + writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
> + sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
> + writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
> + sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
> +
> + writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
> + BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
> +}
> +
> +static struct clock_event_device sirfsoc_clockevent = {
> + .name = "sirfsoc_clockevent",
> + .rating = 200,
> + .features = CLOCK_EVT_FEAT_ONESHOT,
> + .set_mode = sirfsoc_timer_set_mode,
> + .set_next_event = sirfsoc_timer_set_next_event,
> +};
> +
> +static struct clocksource sirfsoc_clocksource = {
> + .name = "sirfsoc_clocksource",
> + .rating = 200,
> + .mask = CLOCKSOURCE_MASK(64),
> + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> + .read = sirfsoc_timer_read,
> + .suspend = sirfsoc_clocksource_suspend,
> + .resume = sirfsoc_clocksource_resume,
> +};
> +
> +static struct irqaction sirfsoc_timer_irq = {
> + .name = "sirfsoc_timer0",
> + .flags = IRQF_TIMER | IRQF_NOBALANCING,
> + .handler = sirfsoc_timer_interrupt,
> + .dev_id = &sirfsoc_clockevent,
> +};
> +
> +#ifdef CONFIG_LOCAL_TIMERS
> +
> +/* timer1 interrupt handler */
> +static irqreturn_t sirfsoc_timer1_interrupt(int irq, void *dev_id)
> +{
> + struct clock_event_device *ce = dev_id;
> +
> + /* clear timer1 interrupt */
> + writel_relaxed(BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
> +
> + if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
> + sirfsoc_timer_count_disable(1);
> +
> + ce->event_handler(ce);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static struct irqaction sirfsoc_timer1_irq = {
> + .name = "sirfsoc_timer1",
> + .flags = IRQF_TIMER | IRQF_NOBALANCING,
> + .handler = sirfsoc_timer1_interrupt,
> +};
> +
> +static int sirfsoc_timer1_set_next_event(unsigned long delta,
> + struct clock_event_device *ce)
> +{
> + writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
> + writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_1);
> +
> + /* enable the tick */
> + sirfsoc_timer_count_enable(1);
> +
> + return 0;
> +}
> +
> +static void sirfsoc_timer1_set_mode(enum clock_event_mode mode,
> + struct clock_event_device *ce)
> +{
> + switch (mode) {
> + case CLOCK_EVT_MODE_ONESHOT:
> + /* enable in set_next_event */
> + break;
> + default:
> + break;
> + }
> +
> + sirfsoc_timer_count_disable(1);
> +}
> +
> +static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce)
> +{
> + /* Use existing clock_event for cpu 0 */
> + if (!smp_processor_id())
> + return 0;
This seems a little scary. Does the timer only exist for 1 core, or is it not
actually a local timer?
> +
> + ce->irq = sirfsoc_timer1_irq.irq;
> + ce->name = "local_timer";
> + ce->features = sirfsoc_clockevent.features;
> + ce->rating = sirfsoc_clockevent.rating;
> + ce->cpumask = cpumask_of(1);
The local_timer api sets the cpumask, and you've already rejected setups from
cpu0, so this isn't technically necessary.
> + ce->set_mode = sirfsoc_timer1_set_mode;
> + ce->set_next_event = sirfsoc_timer1_set_next_event;
> + ce->shift = sirfsoc_clockevent.shift;
> + ce->mult = sirfsoc_clockevent.mult;
> + ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns;
> + ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns;
> +
> + sirfsoc_timer1_irq.dev_id = ce;
> + BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq));
> + irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1));
> +
> + clockevents_register_device(ce);
> + return 0;
> +}
> +
> +static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
> +{
> + sirfsoc_timer_count_disable(1);
> +
> + remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
> +}
Presumably you need to balance what you've done in sirfsoc_local_timer_setup,
and return early for cpu0.
> +
> +static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = {
> + .setup = sirfsoc_local_timer_setup,
> + .stop = sirfsoc_local_timer_stop,
> +};
> +#endif /* CONFIG_LOCAL_TIMERS */
> +
> +static void __init sirfsoc_clockevent_init(void)
> +{
> + clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
> +
> + sirfsoc_clockevent.max_delta_ns =
> + clockevent_delta2ns(-2, &sirfsoc_clockevent);
I assume this is a typo. For one thing, clockevent_delta2ns takes an unsigned
long.
> + sirfsoc_clockevent.min_delta_ns =
> + clockevent_delta2ns(2, &sirfsoc_clockevent);
> +
> + sirfsoc_clockevent.cpumask = cpumask_of(0);
> + clockevents_register_device(&sirfsoc_clockevent);
> +#ifdef CONFIG_LOCAL_TIMERS
> + local_timer_register(&sirfsoc_local_timer_ops);
> +#endif
> +}
> +
> +/* initialize the kernel jiffy timer source */
> +void __init sirfsoc_marco_timer_init(void)
> +{
> + unsigned long rate;
> + u32 timer_div;
> + struct clk *clk;
> +
> + /* initialize clocking early, we want to set the OS timer */
> + sirfsoc_of_clk_init();
> +
> + /* timer's input clock is io clock */
> + clk = clk_get_sys("io", NULL);
> +
> + BUG_ON(IS_ERR(clk));
> + rate = clk_get_rate(clk);
> +
> + BUG_ON(rate < CLOCK_TICK_RATE);
> + BUG_ON(rate % CLOCK_TICK_RATE);
> +
> + sirfsoc_of_timer_map();
> +
> + /* Initialize the timer dividers */
> + timer_div = rate / CLOCK_TICK_RATE / 2 - 1;
> + writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
> + writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
> + writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
> +
> + /* Initialize timer counters to 0 */
> + writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
> + writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
> + writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
> + BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
> + writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
> + writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
> +
> + /* Clear all interrupts */
> + writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
> +
> + BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
> +
> + BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
> +
> + sirfsoc_clockevent_init();
> +}
> +
> +static struct of_device_id timer_ids[] = {
> + { .compatible = "sirf,marco-tick" },
> + {},
> +};
> +
> +static void __init sirfsoc_of_timer_map(void)
> +{
> + struct device_node *np;
> +
> + np = of_find_matching_node(NULL, timer_ids);
> + if (!np)
> + return;
> + sirfsoc_timer_base = of_iomap(np, 0);
> + if (!sirfsoc_timer_base)
> + panic("unable to map timer cpu registers\n");
> +
> + sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
> + if (!sirfsoc_timer_irq.irq)
> + panic("No irq passed for timer0 via DT\n");
> +
> +#ifdef CONFIG_LOCAL_TIMERS
> + sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
> + if (!sirfsoc_timer1_irq.irq)
> + panic("No irq passed for timer1 via DT\n");
> +#endif
> +
> + of_node_put(np);
> +}
> --
> 1.7.5.4
>
>
>
> Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
> More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
Thanks,
Mark.
^ permalink raw reply
* [RFC PATCH 3/4] ARM: bL_entry: Match memory barriers to architectural requirements
From: Dave Martin @ 2013-01-16 15:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130116150533.GA31318@arm.com>
On Wed, Jan 16, 2013 at 03:05:34PM +0000, Catalin Marinas wrote:
> Santosh,
>
> On Wed, Jan 16, 2013 at 06:50:47AM +0000, Santosh Shilimkar wrote:
> > On Tuesday 15 January 2013 10:18 PM, Dave Martin wrote:
> > > For architectural correctness even Strongly-Ordered memory accesses
> > > require barriers in order to guarantee that multiple CPUs have a
> > > coherent view of the ordering of memory accesses.
> > >
> > > Virtually everything done by this early code is done via explicit
> > > memory access only, so DSBs are seldom required. Existing barriers
> > > are demoted to DMB, except where a DSB is needed to synchronise
> > > non-memory signalling (i.e., before a SEV). If a particular
> > > platform performs cache maintenance in its power_up_setup function,
> > > it should force it to complete explicitly including a DSB, instead
> > > of relying on the bL_head framework code to do it.
> > >
> > > Some additional DMBs are added to ensure all the memory ordering
> > > properties required by the race avoidance algorithm. DMBs are also
> > > moved out of loops, and for clarity some are moved so that most
> > > directly follow the memory operation which needs to be
> > > synchronised.
> > >
> > > The setting of a CPU's bL_entry_vectors[] entry is also required to
> > > act as a synchronisation point, so a DMB is added after checking
> > > that entry to ensure that other CPUs do not observe gated
> > > operations leaking across the opening of the gate.
> > >
> > > Signed-off-by: Dave Martin <dave.martin@linaro.org>
> >
> > Sorry to pick on this again but I am not able to understand why
> > the strongly ordered access needs barriers. At least from the
> > ARM point of view, a strongly ordered write will be more of blocking
> > write and the further interconnect also is suppose to respect that
> > rule. SO read writes are like adding barrier after every load store
> > so adding explicit barriers doesn't make sense. Is this a side
> > effect of some "write early response" kind of optimizations at
> > interconnect level ?
>
> SO or Device memory accesses are *not* like putting a proper barrier
> between each access, though it may behave in some situations like having
> a barrier. The ARM ARM (A3.8.3, fig 3.5) defines how accesses must
> *arrive* at a peripheral or block of memory depending on the memory type
> and in case of Device or SO we don't need additional barriers because
> such accesses would *arrive* in order (given the minimum 1KB range
> restriction). But it does not say anything about *observability* by a
> different *master*. That's because you can't guarantee that your memory
> accesses go to the same slave port.
>
> For observability by a different master, you need an explicit DMB even
> though the memory type is Device or SO. While it may work fine in most
> cases (especially when the accesses by various masters go to the same
> slave port), you can't be sure what the memory controller or whatever
> interconnect do.
>
> As Dave said, it's more about what the ARM ARM doesn't say rather than
> what it explicitly states.
OK, so I talked to one of the ARM architects and he strongly recommends
having the DMBs.
The fact that SO accesses are shareable guarantees a coherent view of
access order only per memory location (i.e., per address), _not_
per slave. This is what was missing from my original assumption.
For different memory locations, even within a single block of memory,
you don't get that guarantee about what other masters see, except for
the precise documented situations where there are address, control,
or data dependencies between instructions which imply a particular
observation order by other masters. (See A3.8.2, Ordering requirements
for memory accesses).
For this locking code, we're concerned about ordering between different
memory locations in almost all instances, so most or all of the
barriers will be needed, for strict correctness.
Cheers
---Dave
^ permalink raw reply
* [PATCH 2/2] ARM: dma-mapping: use himem for DMA buffers for IOMMU-mapped devices
From: Marek Szyprowski @ 2013-01-16 15:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358350284-6972-1-git-send-email-m.szyprowski@samsung.com>
IOMMU can provide access to any memory page, so there is no point in
limiting the allocated pages only to lowmem, once other parts of
dma-mapping subsystem correctly supports himem pages.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
arch/arm/mm/dma-mapping.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 4080c37..9a6c8ce 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1095,12 +1095,17 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
return pages;
}
+ /*
+ * IOMMU can map any pages, so himem can also be used here
+ */
+ gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
+
while (count) {
int j, order = __fls(count);
- pages[i] = alloc_pages(gfp | __GFP_NOWARN, order);
+ pages[i] = alloc_pages(gfp, order);
while (!pages[i] && order)
- pages[i] = alloc_pages(gfp | __GFP_NOWARN, --order);
+ pages[i] = alloc_pages(gfp, --order);
if (!pages[i])
goto error;
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/2] ARM: dma-mapping: add support for CMA regions placed in highmem zone
From: Marek Szyprowski @ 2013-01-16 15:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358350284-6972-1-git-send-email-m.szyprowski@samsung.com>
This patch adds missing pieces to correctly support memory pages served
from CMA regions placed in high memory zones. Please note that the default
global CMA area is still put into lowmem and is limited by optional
architecture specific DMA zone. One can however put device specific CMA
regions in high memory zone to reduce lowmem usage.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
arch/arm/mm/dma-mapping.c | 61 +++++++++++++++++++++++++++++++++------------
1 file changed, 45 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 6b2fb87..4080c37 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -186,16 +186,29 @@ static u64 get_coherent_dma_mask(struct device *dev)
static void __dma_clear_buffer(struct page *page, size_t size)
{
- void *ptr;
/*
* Ensure that the allocated pages are zeroed, and that any data
* lurking in the kernel direct-mapped region is invalidated.
*/
- ptr = page_address(page);
- if (ptr) {
- memset(ptr, 0, size);
- dmac_flush_range(ptr, ptr + size);
- outer_flush_range(__pa(ptr), __pa(ptr) + size);
+ if (!PageHighMem(page)) {
+ void *ptr = page_address(page);
+ if (ptr) {
+ memset(ptr, 0, size);
+ dmac_flush_range(ptr, ptr + size);
+ outer_flush_range(__pa(ptr), __pa(ptr) + size);
+ }
+ } else {
+ phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
+ phys_addr_t end = base + size;
+ while (size > 0) {
+ void *ptr = kmap_atomic(page);
+ memset(ptr, 0, PAGE_SIZE);
+ dmac_flush_range(ptr, ptr + PAGE_SIZE);
+ kunmap_atomic(ptr);
+ page++;
+ size -= PAGE_SIZE;
+ }
+ outer_flush_range(base, end);
}
}
@@ -243,7 +256,8 @@ static void __dma_free_buffer(struct page *page, size_t size)
#endif
static void *__alloc_from_contiguous(struct device *dev, size_t size,
- pgprot_t prot, struct page **ret_page);
+ pgprot_t prot, struct page **ret_page,
+ const void *caller);
static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
pgprot_t prot, struct page **ret_page,
@@ -346,10 +360,11 @@ static int __init atomic_pool_init(void)
goto no_pages;
if (IS_ENABLED(CONFIG_CMA))
- ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page);
+ ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
+ atomic_pool_init);
else
ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot,
- &page, NULL);
+ &page, atomic_pool_init);
if (ptr) {
int i;
@@ -542,27 +557,41 @@ static int __free_from_pool(void *start, size_t size)
}
static void *__alloc_from_contiguous(struct device *dev, size_t size,
- pgprot_t prot, struct page **ret_page)
+ pgprot_t prot, struct page **ret_page,
+ const void *caller)
{
unsigned long order = get_order(size);
size_t count = size >> PAGE_SHIFT;
struct page *page;
+ void *ptr;
page = dma_alloc_from_contiguous(dev, count, order);
if (!page)
return NULL;
__dma_clear_buffer(page, size);
- __dma_remap(page, size, prot);
+ if (!PageHighMem(page)) {
+ __dma_remap(page, size, prot);
+ ptr = page_address(page);
+ } else {
+ ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
+ if (!ptr) {
+ dma_release_from_contiguous(dev, page, count);
+ return NULL;
+ }
+ }
*ret_page = page;
- return page_address(page);
+ return ptr;
}
static void __free_from_contiguous(struct device *dev, struct page *page,
- size_t size)
+ void *cpu_addr, size_t size)
{
- __dma_remap(page, size, pgprot_kernel);
+ if (!PageHighMem(page))
+ __dma_remap(page, size, pgprot_kernel);
+ else
+ __dma_free_remap(cpu_addr, size);
dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
}
@@ -645,7 +674,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
else if (!IS_ENABLED(CONFIG_CMA))
addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
else
- addr = __alloc_from_contiguous(dev, size, prot, &page);
+ addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
if (addr)
*handle = pfn_to_dma(dev, page_to_pfn(page));
@@ -739,7 +768,7 @@ static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
* Non-atomic allocations cannot be freed with IRQs disabled
*/
WARN_ON(irqs_disabled());
- __free_from_contiguous(dev, page, size);
+ __free_from_contiguous(dev, page, cpu_addr, size);
}
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH 0/2] ARM: dma-mapping: add highmem support for coherent allocation
From: Marek Szyprowski @ 2013-01-16 15:31 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
This is the last missing piece to let us efficiently use large DMA
buffers on systems with lots of memory, which have support for himem
enabled. The first patch adds support for CMA regions placed in high
memory zones, the second one also enables allocations of individual
pages from high memory zone for IOMMU-mapped devices. Those two changes
let us to significantly save low memory for other tasks.
Best regards
Marek Szyprowski
Samsung Poland R&D Center
Patch summary:
Marek Szyprowski (2):
ARM: dma-mapping: add support for CMA regions placed in highmem zone
ARM: dma-mapping: use himem for DMA buffers for IOMMU-mapped devices
arch/arm/mm/dma-mapping.c | 70 +++++++++++++++++++++++++++++++++------------
1 file changed, 52 insertions(+), 18 deletions(-)
--
1.7.9.5
^ permalink raw reply
* [PATCH v5 07/12] ARM: KVM: VGIC virtual CPU interface management
From: Christoffer Dall @ 2013-01-16 15:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F536DC.2060702@arm.com>
[...]
>> diff --git a/arch/arm/include/asm/kvm_vgic.h b/arch/arm/include/asm/kvm_vgic.h
>> index 1ace491..f9d1977 100644
>> --- a/arch/arm/include/asm/kvm_vgic.h
>> +++ b/arch/arm/include/asm/kvm_vgic.h
>> @@ -33,6 +33,7 @@
>> #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
>> #define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
>> #define VGIC_MAX_CPUS KVM_MAX_VCPUS
>> +#define VGIC_MAX_LRS 64
>
> Consider this instead (for the reason below)
> #define VGIC_MAX_LRS (1 << 7)
>
so here you mean (1 << 6), right?
>> /* Sanity checks... */
>> #if (VGIC_MAX_CPUS > 8)
>> @@ -120,7 +121,7 @@ struct vgic_cpu {
>> DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
>>
>> /* Bitmap of used/free list registers */
>> - DECLARE_BITMAP( lr_used, 64);
>> + DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
>>
>> /* Number of list registers on this CPU */
>> int nr_lr;
>> @@ -132,7 +133,7 @@ struct vgic_cpu {
>> u32 vgic_eisr[2]; /* Saved only */
>> u32 vgic_elrsr[2]; /* Saved only */
>> u32 vgic_apr;
>> - u32 vgic_lr[64]; /* A15 has only 4... */
>> + u32 vgic_lr[VGIC_MAX_LRS];
>> #endif
>> };
>>
>> diff --git a/arch/arm/kvm/vgic.c b/arch/arm/kvm/vgic.c
>> index a0d283c..90a99fd 100644
>> --- a/arch/arm/kvm/vgic.c
>> +++ b/arch/arm/kvm/vgic.c
>> @@ -1345,6 +1345,8 @@ int kvm_vgic_hyp_init(void)
>>
>> vgic_nr_lr = readl_relaxed(vgic_vctrl_base + GICH_VTR);
>> vgic_nr_lr = (vgic_nr_lr & 0x1f) + 1;
>
> There is a bug here. It should be:
> vgic_nr_lr = (vgic_nr_lr & 0x2f) + 1;
>
and here you mean (vgic_nr_lr & 0x3f) + 1
right?
>> + if (vgic_nr_lr > VGIC_MAX_LRS)
>> + vgic_nr_lr = VGIC_MAX_LRS; /* TODO: Clear remaining LRs */
>
> Why? VGIC_MAX_LRS isn't a configurable value, but a maximum value
> defined by the specification. This is the maximum you can fit in a 6 bit
> field, plus one (1 << 7, exactly).
>
>> ret = create_hyp_io_mappings(vgic_vctrl_base,
>> vgic_vctrl_base + resource_size(&vctrl_res),
>> --
>>
>> Thanks,
>> -Christoffer
>>
>
>
> --
> Jazz is not dead. It just smells funny...
>
^ permalink raw reply
* [PATCH v4 2/9] clk: tegra: Add tegra specific clocks
From: Hiroshi Doyu @ 2013-01-16 15:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357890387-23245-3-git-send-email-pgaikwad@nvidia.com>
Prashant Gaikwad <pgaikwad@nvidia.com> wrote @ Fri, 11 Jan 2013 08:46:20 +0100:
....
> diff --git a/drivers/clk/tegra/clk-audio-sync.c b/drivers/clk/tegra/clk-audio-sync.c
> new file mode 100644
> index 0000000..bb2fe43
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-audio-sync.c
> @@ -0,0 +1,89 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +
> +#include "clk.h"
> +
> +#define to_clk_sync_source(_hw) \
> + container_of(_hw, struct tegra_clk_sync_source, hw)
Can we define "struct tegra_clk_sync_source" here if there's no need
to expose this structure out?
> +
> +static unsigned long clk_sync_source_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
> +
> + return sync->rate;
> +}
> +
> +static long clk_sync_source_round_rate(struct clk_hw *hw, unsigned long rate,
> +
unsigned long *prate)
.....
> diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
> new file mode 100644
> index 0000000..fcd0123
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-divider.c
> @@ -0,0 +1,188 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/slab.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +
> +#include "clk.h"
> +
> +#define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
> +
> +#define pll_out_override(p) (BIT((p->shift - 6)))
> +#define div_mask(d) ((1 << (d->width)) - 1)
> +#define get_mul(d) (1 << d->frac_width)
> +#define get_max_div(d) div_mask(d)
> +
> +#define PERIPH_CLK_UART_DIV_ENB BIT(24)
Can we define "struct tegra_clk_frac_div" here too?
> +
> +static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + s64 divider_ux1 = parent_rate;
> + u8 flags = divider->flags;
> + int mul;
> +
> + if (!rate)
> + return 0;
> +
> + mul = get_mul(divider);
> +
.....
> +static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
> + int div;
> + unsigned long flags = 0;
nit, is "flags" not needed to initialize here?
.......
> diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
> new file mode 100644
> index 0000000..5f0919d
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-periph-gate.c
> @@ -0,0 +1,182 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/tegra-soc.h>
> +
> +#include "clk.h"
> +
> +static DEFINE_SPINLOCK(periph_ref_lock);
> +
> +#define to_clk_periph_gate(_hw) \
> + container_of(_hw, struct tegra_clk_periph_gate, hw)
For consistency, put "to_clk_periph_gate(_hw)" in "clk.h", then this
can be used in clk-periph.c as well.
> +/* Macros to assist peripheral gate clock */
> +#define read_enb(gate) \
> + readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
> +#define write_enb_set(val, gate) \
> + writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
> +#define write_enb_clr(val, gate) \
> + writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
> +
> +#define read_rst(gate) \
> + readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
> +#define write_rst_set(val, gate) \
> + writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
> +#define write_rst_clr(val, gate) \
> + writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
> +
> +#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
> +
> +/* Peripheral gate clock ops */
> +static int clk_periph_is_enabled(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
> + int state = 1;
> +
> + if (!(read_enb(gate) & periph_clk_to_bit(gate)))
> + state = 0;
> +
> + if (!(gate->flags & TEGRA_PERIPH_NO_RESET))
> + if (read_rst(gate) & periph_clk_to_bit(gate))
> + state = 0;
> +
> + return state;
> +}
> +
> +static int clk_periph_enable(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
> + unsigned long flags = 0;
nit, is "flags" not needed to initialize here?
> +
> + spin_lock_irqsave(&periph_ref_lock, flags);
> +
> + gate->enable_refcnt[gate->clk_num]++;
> + if (gate->enable_refcnt[gate->clk_num] > 1) {
> + spin_unlock_irqrestore(&periph_ref_lock, flags);
> + return 0;
> + }
> +
> + write_enb_set(periph_clk_to_bit(gate), gate);
> + udelay(2);
> +
> + if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
> + !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
> + if (read_rst(gate) & periph_clk_to_bit(gate)) {
> + udelay(5); /* reset propogation delay */
> + write_rst_clr(periph_clk_to_bit(gate), gate);
> + }
> + }
> +
> + spin_unlock_irqrestore(&periph_ref_lock, flags);
> +
> + return 0;
> +}
> +
> +static void clk_periph_disable(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
> + unsigned long flags = 0;
nit, is "flags" not needed to initialize here?
> +
> + spin_lock_irqsave(&periph_ref_lock, flags);
> +
> + gate->enable_refcnt[gate->clk_num]--;
> + if (gate->enable_refcnt[gate->clk_num] > 0) {
> + spin_unlock_irqrestore(&periph_ref_lock, flags);
> + return;
> + }
> +
> + /*
> + * If peripheral is in the APB bus then read the APB bus to
> + * flush the write operation in apb bus. This will avoid the
> + * peripheral access after disabling clock
> + */
> + if (gate->flags & TEGRA_PERIPH_ON_APB)
> + tegra_read_chipid();
> +
> + write_enb_clr(periph_clk_to_bit(gate), gate);
> +
> + spin_unlock_irqrestore(&periph_ref_lock, flags);
> +}
> +
> +void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert)
> +{
> + if (gate->flags & TEGRA_PERIPH_NO_RESET)
> + return;
> +
> + if (assert) {
> + /*
> + * If peripheral is in the APB bus then read the APB bus to
> + * flush the write operation in apb bus. This will avoid the
> + * peripheral access after disabling clock
> + */
> + if (gate->flags & TEGRA_PERIPH_ON_APB)
> + tegra_read_chipid();
> +
> + write_rst_set(periph_clk_to_bit(gate), gate);
> + } else {
> + write_rst_clr(periph_clk_to_bit(gate), gate);
> + }
> +}
> +
> +const struct clk_ops tegra_clk_periph_gate_ops = {
> + .is_enabled = clk_periph_is_enabled,
> + .enable = clk_periph_enable,
> + .disable = clk_periph_disable,
> +};
> +
> +struct clk *tegra_clk_periph_gate(const char *name, const char *parent_name,
> + u8 gate_flags, void __iomem *clk_base,
> + unsigned long flags, int clk_num,
> + struct tegra_clk_periph_regs *pregs,
> + int *enable_refcnt)
> +{
> + struct tegra_clk_periph_gate *gate;
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + gate = kzalloc(sizeof(struct tegra_clk_periph_gate), GFP_KERNEL);
gate = kzalloc(sizeof(*gate), GFP_KERNEL) ?
> + if (!gate) {
> + pr_err("%s: could not allocate periph gate clk\n", __func__);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + init.name = name;
> + init.flags = flags;
> + init.parent_names = parent_name ? &parent_name : NULL;
> + init.num_parents = parent_name ? 1 : 0;
> + init.ops = &tegra_clk_periph_gate_ops;
> +
> + gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;
> + gate->clk_base = clk_base;
> + gate->clk_num = clk_num;
> + gate->flags = gate_flags;
> + gate->enable_refcnt = enable_refcnt;
> + gate->regs = pregs;
> +
> + gate->hw.init = &init;
> +
> + clk = clk_register(NULL, &gate->hw);
> + if (IS_ERR(clk))
> + kfree(gate);
> +
> + return clk;
> +}
> diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
> new file mode 100644
> index 0000000..ed0ded2
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-periph.c
> @@ -0,0 +1,190 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +
> +#include "clk.h"
> +
> +#define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
> +
Can't "struct tegra_clk_periph" be defined in this file?
> +static u8 clk_periph_get_parent(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph *periph = to_clk_periph(hw);
> + const struct clk_ops *mux_ops = periph->mux_ops;
> + struct clk_hw *mux_hw = &periph->mux.hw;
> +
> + mux_hw->clk = hw->clk;
> +
> + return mux_ops->get_parent(mux_hw);
> +}
> +
> +static int clk_periph_set_parent(struct clk_hw *hw, u8 index)
> +{
> + struct tegra_clk_periph *periph = to_clk_periph(hw);
> + const struct clk_ops *mux_ops = periph->mux_ops;
> + struct clk_hw *mux_hw = &periph->mux.hw;
> +
> + mux_hw->clk = hw->clk;
> +
> + return mux_ops->set_parent(mux_hw, index);
> +}
> +
....
> +struct clk *tegra_clk_periph(const char *name, const char **parent_names,
> + int num_parents, struct tegra_clk_periph *periph,
> + void __iomem *clk_base, u32 offset)
> +{
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + init.name = name;
> + init.ops = &tegra_clk_periph_ops;
> + init.flags = 0;
struct members in stack are expected to initialize 0.
> + init.parent_names = parent_names;
> + init.num_parents = num_parents;
.....
> diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c
> new file mode 100644
> index 0000000..60a117b
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-pll-out.c
> @@ -0,0 +1,124 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/delay.h>
> +#include <linux/slab.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +
> +#include "clk.h"
> +
> +#define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
Can't "struct tegra_clk_pll_out" be defined in this file?
> +
> +#define pll_out_enb(p) (BIT(p->enb_bit_idx))
> +#define pll_out_rst(p) (BIT(p->rst_bit_idx))
I don't see much benefit from the above macros.
> +
> +static int clk_pll_out_is_enabled(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
> + u32 val = readl_relaxed(pll_out->reg);
> + int state;
> +
> + state = (val & pll_out_enb(pll_out)) ? 1 : 0;
> + if (!(val & (pll_out_rst(pll_out))))
> + state = 0;
> + return state;
> +}
> +
> +static int clk_pll_out_enable(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
> + unsigned long flags = 0;
nit, is "flags" not needed to initialize here? other places as well.
....
> +struct clk *tegra_clk_pll_out(const char *name, const char *parent_name,
> + void __iomem *reg, u8 enb_bit_idx, u8 rst_bit_idx,
> + unsigned long flags, u8 pll_out_flags,
> + spinlock_t *lock)
> +{
> + struct tegra_clk_pll_out *pll_out;
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + pll_out = kzalloc(sizeof(struct tegra_clk_pll_out), GFP_KERNEL);
pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL) ?
> + if (!pll_out)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = name;
> + init.ops = &tegra_clk_pll_out_ops;
> + init.parent_names = (parent_name ? &parent_name : NULL);
> + init.num_parents = (parent_name ? 1 : 0);
> + init.flags = flags;
> +
> + pll_out->reg = reg;
> + pll_out->enb_bit_idx = enb_bit_idx;
> + pll_out->rst_bit_idx = rst_bit_idx;
> + pll_out->flags = pll_out_flags;
> + pll_out->lock = lock;
> +
> + pll_out->hw.init = &init;
> +
> + clk = clk_register(NULL, &pll_out->hw);
> + if (IS_ERR(clk))
> + kfree(pll_out);
> +
> + return clk;
> +}
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> new file mode 100644
> index 0000000..f8dc7c0
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-pll.c
.....
> +
> +#define PMC_SATA_PWRGT 0x1ac
> +#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
> +#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
> +
> +#define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
Should define struct tegra_clk_pll here?
> +
> +#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
> +#define pll_readl_base(p) pll_readl(p->params->base_reg, p)
> +#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
> +
> +#define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
> +#define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
> +#define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
> +
> +#define mask(w) ((1 << (w)) - 1)
> +#define divm_mask(p) mask(p->divm_width)
> +#define divn_mask(p) mask(p->divn_width)
> +#define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK : \
> + mask(p->divp_width))
> +
> +#define divm_max(p) (divm_mask(p))
> +#define divn_max(p) (divn_mask(p))
> +#define divp_max(p) (1 << (divp_mask(p)))
> +
> +static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
> +{
> + u32 val;
> +
> + if (!(pll->flags & TEGRA_PLL_USE_LOCK))
> + return;
> +
> + val = pll_readl_misc(pll);
> + val |= BIT(pll->params->lock_enable_bit_idx);
> + pll_writel_misc(val, pll);
> +}
> +
> +static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
> + void __iomem *lock_addr, u32 lock_bit_idx)
> +{
> + int i;
> + u32 val;
> +
> + if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
> + udelay(pll->params->lock_delay);
> + return 0;
> + }
> +
> + for (i = 0; i < pll->params->lock_delay; i++) {
> + val = readl_relaxed(lock_addr);
> + if (val & BIT(lock_bit_idx)) {
> + udelay(PLL_POST_LOCK_DELAY);
> + return 0;
> + }
> + udelay(2); /* timeout = 2 * lock time */
> + }
> +
> + pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
> + __clk_get_name(pll->hw.clk));
> +
> + return -1;
> +}
> +
> +static int clk_pll_is_enabled(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + u32 val;
> +
> + if (pll->flags & TEGRA_PLLM) {
> + val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
> + if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
> + return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
> + }
> +
> + val = pll_readl_base(pll);
> +
> + return val & PLL_BASE_ENABLE ? 1 : 0;
> +}
> +
> +static int _clk_pll_enable(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + u32 val;
> +
> + clk_pll_enable_lock(pll);
> +
> + val = pll_readl_base(pll);
> + val &= ~PLL_BASE_BYPASS;
> + val |= PLL_BASE_ENABLE;
> + pll_writel_base(val, pll);
> +
> + if (pll->flags & TEGRA_PLLM) {
> + val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
> + val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
> + writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
> + }
> +
> + clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->base_reg,
> + pll->params->lock_bit_idx);
> +
> + return 0;
> +}
> +
> +static void _clk_pll_disable(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + u32 val;
> +
> + val = pll_readl_base(pll);
> + val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
> + pll_writel_base(val, pll);
> +
> + if (pll->flags & TEGRA_PLLM) {
> + val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
> + val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
> + writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
> + }
> +}
> +
> +static int clk_pll_enable(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + unsigned long flags = 0;
nit, is "flags" not needed to initialize here?
> + int ret;
> +
> + if (pll->lock)
> + spin_lock_irqsave(pll->lock, flags);
> +
> + ret = _clk_pll_enable(hw);
> +
> + if (pll->lock)
> + spin_unlock_irqrestore(pll->lock, flags);
> +
> + return ret;
> +}
> +
> +static void clk_pll_disable(struct clk_hw *hw)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + unsigned long flags = 0;
nit, is "flags" not needed to initialize here?
> +
> + if (pll->lock)
> + spin_lock_irqsave(pll->lock, flags);
> +
> + _clk_pll_disable(hw);
> +
> + if (pll->lock)
> + spin_unlock_irqrestore(pll->lock, flags);
> +}
> +
> +static int _get_table_rate(struct clk_hw *hw,
> + struct tegra_clk_pll_freq_table *cfg,
> + unsigned long rate, unsigned long parent_rate)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + struct tegra_clk_pll_freq_table *sel;
> +
> + for (sel = pll->freq_table; sel->input_rate != 0; sel++)
> + if (sel->input_rate == parent_rate &&
> + sel->output_rate == rate)
> + break;
> +
> + if (sel->input_rate == 0)
> + return -EINVAL;
> +
> + BUG_ON(sel->p < 1);
> +
> + cfg->input_rate = sel->input_rate;
> + cfg->output_rate = sel->output_rate;
> + cfg->m = sel->m;
> + cfg->n = sel->n;
> + cfg->p = sel->p;
> + cfg->cpcon = sel->cpcon;
> +
> + return 0;
> +}
> +
> +static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
> + unsigned long rate, unsigned long parent_rate)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + unsigned long cfreq;
> + u32 p_div = 0;
> +
> + switch (parent_rate) {
> + case 12000000:
> + case 26000000:
> + cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
> + break;
> + case 13000000:
> + cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
> + break;
> + case 16800000:
> + case 19200000:
> + cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
> + break;
> + case 9600000:
> + case 28800000:
> + /*
> + * PLL_P_OUT1 rate is not listed in PLLA table
> + */
> + cfreq = parent_rate/(parent_rate/1000000);
> + break;
> + default:
> + pr_err("%s Unexpected reference rate %lu\n",
> + __func__, parent_rate);
> + BUG();
> + }
> +
> + /* Raise VCO to guarantee 0.5% accuracy */
> + for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
> + cfg->output_rate <<= 1)
> + p_div++;
> +
> + cfg->p = 1 << p_div;
> + cfg->m = parent_rate / cfreq;
> + cfg->n = cfg->output_rate / cfreq;
> + cfg->cpcon = OUT_OF_TABLE_CPCON;
> +
> + if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
> + cfg->p > divp_max(pll) || cfg->output_rate > pll->params->vco_max) {
> + pr_err("%s: Failed to set %s rate %lu\n",
> + __func__, __clk_get_name(hw->clk), rate);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
> + unsigned long rate)
> +{
> + struct tegra_clk_pll *pll = to_clk_pll(hw);
> + unsigned long flags = 0;
nit, is "flags" not needed to initialize here?
....
> +
> +struct clk *tegra_clk_pll(const char *name, const char *parent_name,
> + void __iomem *clk_base, void __iomem *pmc,
> + unsigned long flags, unsigned long fixed_rate,
> + struct tegra_clk_pll_params *pll_params, u8 pll_flags,
> + struct tegra_clk_pll_freq_table *freq_table,
> + spinlock_t *lock)
> +{
> + struct tegra_clk_pll *pll;
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + pll = kzalloc(sizeof(struct tegra_clk_pll), GFP_KERNEL);
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> + if (!pll)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = name;
> + init.ops = &tegra_clk_pll_ops;
> + init.flags = flags;
> + init.parent_names = (parent_name ? &parent_name : NULL);
> + init.num_parents = (parent_name ? 1 : 0);
> +
> + pll->clk_base = clk_base;
> + pll->pmc = pmc;
> +
> + pll->freq_table = freq_table;
> + pll->params = pll_params;
> + pll->fixed_rate = fixed_rate;
> + pll->flags = pll_flags;
> + pll->lock = lock;
> +
> + pll->divp_shift = PLL_BASE_DIVP_SHIFT;
> + pll->divp_width = PLL_BASE_DIVP_WIDTH;
> + pll->divn_shift = PLL_BASE_DIVN_SHIFT;
> + pll->divn_width = PLL_BASE_DIVN_WIDTH;
> + pll->divm_shift = PLL_BASE_DIVM_SHIFT;
> + pll->divm_width = PLL_BASE_DIVM_WIDTH;
> +
> + pll->hw.init = &init;
> +
> + clk = clk_register(NULL, &pll->hw);
> + if (IS_ERR(clk))
> + kfree(pll);
> +
> + return clk;
> +}
> +
> +struct clk *tegra_clk_plle(const char *name, const char *parent_name,
> + void __iomem *clk_base, void __iomem *pmc,
> + unsigned long flags, unsigned long fixed_rate,
> + struct tegra_clk_pll_params *pll_params, u8 pll_flags,
> + struct tegra_clk_pll_freq_table *freq_table,
> + spinlock_t *lock)
> +{
> + struct tegra_clk_pll *pll;
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + pll = kzalloc(sizeof(struct tegra_clk_pll), GFP_KERNEL);
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> + if (!pll)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = name;
> + init.ops = &tegra_clk_plle_ops;
> + init.flags = flags;
> + init.parent_names = (parent_name ? &parent_name : NULL);
> + init.num_parents = (parent_name ? 1 : 0);
> +
> + pll->clk_base = clk_base;
> + pll->pmc = pmc;
> +
> + pll->freq_table = freq_table;
> + pll->params = pll_params;
> + pll->fixed_rate = fixed_rate;
> + pll->flags = pll_flags;
> + pll->lock = lock;
> +
> + pll->divp_shift = PLLE_BASE_DIVP_SHIFT;
> + pll->divp_width = PLLE_BASE_DIVP_WIDTH;
> + pll->divn_shift = PLLE_BASE_DIVN_SHIFT;
> + pll->divn_width = PLLE_BASE_DIVN_WIDTH;
> + pll->divm_shift = PLLE_BASE_DIVM_SHIFT;
> + pll->divm_width = PLLE_BASE_DIVM_WIDTH;
> +
> + pll->hw.init = &init;
> +
> + clk = clk_register(NULL, &pll->hw);
> + if (IS_ERR(clk))
> + kfree(pll);
> +
> + return clk;
> +}
Can tegra_clk_pll() and tegra_clk_plle() be static inline from the same func?
struct clk *__tegra_clk_pll(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
struct tegra_clk_pll_params *pll_params, u8 pll_flags,
struct tegra_clk_pll_freq_table *freq_table,
spinlock_t *lock, int e)
{
....
}
clk.h:
static inline struct clk *tegra_clk_pll(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
struct tegra_clk_pll_params *pll_params, u8 pll_flags,
struct tegra_clk_pll_freq_table *freq_table,
spinlock_t *lock, int e)
{
return __tegra_clk_pll(name, parent_name, clk_base, pmc, flags, fixed_rate, pll_params,
pll_flags, freq_table, lock, 0);
}
static inline struct clk *tegra_clk_plle(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags, unsigned long fixed_rate,
struct tegra_clk_pll_params *pll_params, u8 pll_flags,
struct tegra_clk_pll_freq_table *freq_table,
spinlock_t *lock, int e)
{
return __tegra_clk_pll(name, parent_name, clk_base, pmc, flags, fixed_rate, pll_params,
pll_flags, freq_table, lock, 1);
}
> diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
> new file mode 100644
> index 0000000..1604f12
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-super.c
> @@ -0,0 +1,154 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/io.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/slab.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +
> +#include "clk.h"
> +
> +#define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
Can "struct tegra_clk_super_mux" be private in this file?
> +
> +#define SUPER_STATE_IDLE 0
> +#define SUPER_STATE_RUN 1
> +#define SUPER_STATE_IRQ 2
> +#define SUPER_STATE_FIQ 3
> +
> +#define SUPER_STATE_SHIFT 28
> +#define SUPER_STATE_MASK ((BIT(SUPER_STATE_IDLE) | BIT(SUPER_STATE_RUN) | \
> + BIT(SUPER_STATE_IRQ) | BIT(SUPER_STATE_FIQ)) \
> + << SUPER_STATE_SHIFT)
> +
> +#define SUPER_LP_DIV2_BYPASS (1 << 16)
> +
> +#define super_state(s) (BIT(s) << SUPER_STATE_SHIFT)
> +#define super_state_to_src_shift(m, s) ((m->width * s))
> +#define super_state_to_src_mask(m) (((1 << m->width) - 1))
> +
> +static u8 clk_super_get_parent(struct clk_hw *hw)
> +{
> + struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
> + u32 val, state;
> + u8 source, shift;
> +
> + val = readl_relaxed(mux->reg);
> +
> + state = val & SUPER_STATE_MASK;
> +
> + BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
> + (state != super_state(SUPER_STATE_IDLE)));
> + shift = (state == super_state(SUPER_STATE_IDLE)) ?
> + super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
> + super_state_to_src_shift(mux, SUPER_STATE_RUN);
> +
> + source = (val >> shift) & super_state_to_src_mask(mux);
> +
> + /*
> + * If LP_DIV2_BYPASS is not set and PLLX is current parent then
> + * PLLX/2 is the input source to CCLKLP.
> + */
> + if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) &&
> + (source == mux->pllx_index))
> + source = mux->div2_index;
> +
> + return source;
> +}
> +
> +static int clk_super_set_parent(struct clk_hw *hw, u8 index)
> +{
> + struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
> + u32 val, state;
> + u8 parent_index, shift;
> +
> + val = readl_relaxed(mux->reg);
> + state = val & SUPER_STATE_MASK;
> + BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
> + (state != super_state(SUPER_STATE_IDLE)));
> + shift = (state == super_state(SUPER_STATE_IDLE)) ?
> + super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
> + super_state_to_src_shift(mux, SUPER_STATE_RUN);
> +
> + /*
> + * For LP mode super-clock switch between PLLX direct
> + * and divided-by-2 outputs is allowed only when other
> + * than PLLX clock source is current parent.
> + */
> + if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) ||
> + (index == mux->pllx_index))) {
> + parent_index = clk_super_get_parent(hw);
> + if ((parent_index == mux->div2_index) ||
> + (parent_index == mux->pllx_index))
> + return -EINVAL;
> +
> + val ^= SUPER_LP_DIV2_BYPASS;
> + writel_relaxed(val, mux->reg);
> + udelay(2);
> +
> + if (index == mux->div2_index)
> + index = mux->pllx_index;
> + }
> + val &= ~((super_state_to_src_mask(mux)) << shift);
> + val |= (index & (super_state_to_src_mask(mux))) << shift;
> +
> + writel_relaxed(val, mux->reg);
> + udelay(2);
> + return 0;
> +}
> +
> +const struct clk_ops tegra_clk_super_ops = {
> + .get_parent = clk_super_get_parent,
> + .set_parent = clk_super_set_parent,
> +};
> +
> +struct clk *tegra_clk_super_mux(const char *name, const char **parent_names,
> + u8 num_parents, unsigned long flags,
> + void __iomem *reg, u8 clk_super_flags, u8 width,
> + u8 pllx_index, u8 div2_index, spinlock_t *lock)
> +{
> + struct tegra_clk_super_mux *super;
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + super = kzalloc(sizeof(struct tegra_clk_super_mux), GFP_KERNEL);
super = kzalloc(sizeof(*super), GFP_KERNEL);
> + if (!super) {
> + pr_err("%s: could not allocate super clk\n", __func__);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + init.name = name;
> + init.ops = &tegra_clk_super_ops;
> + init.flags = flags;
> + init.parent_names = parent_names;
> + init.num_parents = num_parents;
> +
> + super->reg = reg;
> + super->pllx_index = pllx_index;
> + super->div2_index = div2_index;
> + super->lock = lock;
> + super->width = width;
> + super->flags = clk_super_flags;
> + super->hw.init = &init;
> +
> + clk = clk_register(NULL, &super->hw);
> + if (IS_ERR(clk))
> + kfree(super);
> +
> + return clk;
> +}
> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
> new file mode 100644
> index 0000000..cf023a9
> --- /dev/null
> +++ b/drivers/clk/tegra/clk.c
> @@ -0,0 +1,69 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +
> +#include "clk.h"
> +
> +void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
> + struct clk *clks[], int clk_max)
> +{
> + struct clk *clk;
> +
> + for (; dup_list->clk_id < clk_max; dup_list++) {
> + clk = clks[dup_list->clk_id];
> + dup_list->lookup.clk = clk;
> + clkdev_add(&dup_list->lookup);
> + }
> +}
> +
> +void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
> + struct clk *clks[], int clk_max)
> +{
> + struct clk *clk;
> +
> + for (; tbl->clk_id < clk_max; tbl++) {
> + clk = clks[tbl->clk_id];
> + if (IS_ERR_OR_NULL(clk))
> + return;
> +
> + if (tbl->parent_id < clk_max) {
> + struct clk *parent = clks[tbl->parent_id];
> + if (clk_set_parent(clk, parent)) {
> + pr_err("%s: Failed to set parent %s of %s\n",
> + __func__, __clk_get_name(parent),
> + __clk_get_name(clk));
> + WARN_ON(1);
> + }
> + }
> +
> + if (tbl->rate)
> + if (clk_set_rate(clk, tbl->rate)) {
> + pr_err("%s: Failed to set rate %lu of %s\n",
> + __func__, tbl->rate,
> + __clk_get_name(clk));
> + WARN_ON(1);
> + }
> +
> + if (tbl->state)
> + if (clk_prepare_enable(clk)) {
> + pr_err("%s: Failed to enable %s\n", __func__,
> + __clk_get_name(clk));
> + WARN_ON(1);
> + }
> + }
> +}
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> new file mode 100644
> index 0000000..ed9a510
> --- /dev/null
> +++ b/drivers/clk/tegra/clk.h
> @@ -0,0 +1,476 @@
> +/*
> + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef __TEGRA_CLK_H
> +#define __TEGRA_CLK_H
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +
> +/**
> + * struct tegra_clk_sync_source - external clock source from codec
> + *
> + * @hw: handle between common and hardware-specific interfaces
> + * @rate: input frequency from source
> + * @max_rate: max rate allowed
> + */
> +struct tegra_clk_sync_source {
> + struct clk_hw hw;
> + unsigned long rate;
> + unsigned long max_rate;
> +};
> +
> +extern const struct clk_ops tegra_clk_sync_source_ops;
> +struct clk *tegra_clk_sync_source(const char *name, unsigned long fixed_rate,
> + unsigned long max_rate);
Can the above move to "clk-audio-sync.c"?
> +/**
> + * struct tegra_clk_frac_div - fractional divider clock
> + *
> + * @hw: handle between common and hardware-specific interfaces
> + * @reg: register containing divider
> + * @flags: hardware-specific flags
> + * @shift: shift to the divider bit field
> + * @width: width of the divider bit field
> + * @frac_width: width of the fractional bit field
> + * @lock: register lock
> + *
> + * Flags:
> + * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
> + * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
> + * flag indicates that this divider is for fixed rate PLL.
> + * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
> + * fraction bit is set. This flags indicates to calculate divider for which
> + * fracton bit will be zero.
> + * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
> + * set when divider value is not 0. This flags indicates that the divider
> + * is for UART module.
> + */
> +struct tegra_clk_frac_div {
> + struct clk_hw hw;
> + void __iomem *reg;
> + u8 flags;
> + u8 shift;
> + u8 width;
> + u8 frac_width;
> + spinlock_t *lock;
> +};
.....
> +extern const struct clk_ops tegra_clk_frac_div_ops;
> +struct clk *tegra_clk_divider(const char *name, const char *parent_name,
> + void __iomem *reg, unsigned long flags,
> + u8 clk_divider_flags, u8 shift, u8 width,
> + u8 frac_width, spinlock_t *lock);
Can the above move to "clk-divider.c"?
> +/*
> + * Tegra PLL:
> + *
> + * In general, there are 3 requirements for each PLL
> + * that SW needs to be comply with.
> + * (1) Input frequency range (REF).
> + * (2) Comparison frequency range (CF). CF = REF/DIVM.
> + * (3) VCO frequency range (VCO). VCO = CF * DIVN.
> + *
> + * The final PLL output frequency (FO) = VCO >> DIVP.
> + */
> +
> +/**
> + * struct tegra_clk_pll_freq_table - PLL frequecy table
> + *
> + * @input_rate: input rate from source
> + * @output_rate: output rate from PLL for the input rate
> + * @n: feedback divider
> + * @m: input divider
> + * @p: post divider
> + * @cpcon: charge pump current
> + */
> +struct tegra_clk_pll_freq_table {
> + unsigned long input_rate;
> + unsigned long output_rate;
> + u16 n;
> + u16 m;
> + u8 p;
> + u8 cpcon;
> +};
> +
> +/**
> + * struct clk_pll_params - PLL parameters
> + *
> + * @input_min: Minimum input frequency
> + * @input_max: Maximum input frequency
> + * @cf_min: Minimum comparison frequency
> + * @cf_max: Maximum comparison frequency
> + * @vco_min: Minimum VCO frequency
> + * @vco_max: Maximum VCO frequency
> + * @base_reg: PLL base reg offset
> + * @misc_reg: PLL misc reg offset
> + * @lock_reg: PLL lock reg offset
> + * @lock_bit_idx: Bit index for PLL lock status
> + * @lock_enable_bit_idx: Bit index to enable PLL lock
> + * @lock_delay: Delay in us if PLL lock is not used
> + */
> +struct tegra_clk_pll_params {
> + unsigned long input_min;
> + unsigned long input_max;
> + unsigned long cf_min;
> + unsigned long cf_max;
> + unsigned long vco_min;
> + unsigned long vco_max;
> +
> + u32 base_reg;
> + u32 misc_reg;
> + u32 lock_reg;
> + u32 lock_bit_idx;
> + u32 lock_enable_bit_idx;
> + int lock_delay;
> +};
> +
> +/**
> + * struct tegra_clk_pll - Tegra PLL clock
> + *
> + * @hw: handle between common and hardware-specifix interfaces
> + * @clk_base: address of CAR controller
> + * @pmc: address of PMC, required to read override bits
> + * @freq_table: array of frequencies supported by PLL
> + * @params: PLL parameters
> + * @flags: PLL flags
> + * @fixed_rate: PLL rate if it is fixed
> + * @lock: register lock
> + * @divn_shift: shift to the feedback divider bit field
> + * @divn_width: width of the feedback divider bit field
> + * @divm_shift: shift to the input divider bit field
> + * @divm_width: width of the input divider bit field
> + * @divp_shift: shift to the post divider bit field
> + * @divp_width: width of the post divider bit field
> + *
> + * Flags:
> + * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
> + * PLL locking. If not set it will use lock_delay value to wait.
> + * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
> + * to be programmed to change output frequency of the PLL.
> + * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
> + * to be programmed to change output frequency of the PLL.
> + * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
> + * to be programmed to change output frequency of the PLL.
> + * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
> + * that it is PLLU and invert post divider value.
> + * TEGRA_PLLM - PLLM has additional override settings in PMC. This
> + * flag indicates that it is PLLM and use override settings.
> + * TEGRA_PLL_FIXED - We are not supposed to change output frequency
> + * of some plls.
> + * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
> + */
> +struct tegra_clk_pll {
> + struct clk_hw hw;
> + void __iomem *clk_base;
> + void __iomem *pmc;
> + u8 flags;
> + unsigned long fixed_rate;
> + spinlock_t *lock;
> + u8 divn_shift;
> + u8 divn_width;
> + u8 divm_shift;
> + u8 divm_width;
> + u8 divp_shift;
> + u8 divp_width;
> + struct tegra_clk_pll_freq_table *freq_table;
> + struct tegra_clk_pll_params *params;
> +};
> +
> +#define TEGRA_PLL_USE_LOCK BIT(0)
> +#define TEGRA_PLL_HAS_CPCON BIT(1)
> +#define TEGRA_PLL_SET_LFCON BIT(2)
> +#define TEGRA_PLL_SET_DCCON BIT(3)
> +#define TEGRA_PLLU BIT(4)
> +#define TEGRA_PLLM BIT(5)
> +#define TEGRA_PLL_FIXED BIT(6)
> +#define TEGRA_PLLE_CONFIGURE BIT(7)
> +
> +extern const struct clk_ops tegra_clk_pll_ops;
> +extern const struct clk_ops tegra_clk_plle_ops;
> +struct clk *tegra_clk_pll(const char *name, const char *parent_name,
> + void __iomem *clk_base, void __iomem *pmc,
> + unsigned long flags, unsigned long fixed_rate,
> + struct tegra_clk_pll_params *pll_params, u8 pll_flags,
> + struct tegra_clk_pll_freq_table *freq_table,
> + spinlock_t *lock);
same name as struct tegra_clk_pll. tegra_clk_register_pll()?
> +struct clk *tegra_clk_plle(const char *name, const char *parent_name,
> + void __iomem *clk_base, void __iomem *pmc,
> + unsigned long flags, unsigned long fixed_rate,
> + struct tegra_clk_pll_params *pll_params, u8 pll_flags,
> + struct tegra_clk_pll_freq_table *freq_table,
> + spinlock_t *lock);
> +
> +/**
> + * struct tegra_clk_pll_out - PLL divider down clock
> + *
> + * @hw: handle between common and hardware-specific interfaces
> + * @reg: register containing the PLL divider
> + * @enb_bit_idx: bit to enable/disable PLL divider
> + * @rst_bit_idx: bit to reset PLL divider
> + * @lock: register lock
> + * @flags: hardware-specific flags
> + */
> +struct tegra_clk_pll_out {
> + struct clk_hw hw;
> + void __iomem *reg;
> + u8 enb_bit_idx;
> + u8 rst_bit_idx;
> + spinlock_t *lock;
> + u8 flags;
> +};
In clk-pll-out.c?
> +
> +extern const struct clk_ops tegra_clk_pll_out_ops;
> +struct clk *tegra_clk_pll_out(const char *name, const char *parent_name,
> + void __iomem *reg, u8 enb_bit_idx, u8 rst_bit_idx,
> + unsigned long flags, u8 pll_div_flags,
> + spinlock_t *lock);
same name as struct...
> +
> +/**
> + * struct tegra_clk_periph_regs - Registers controlling peripheral clock
> + *
> + * @enb_reg: read the enable status
> + * @enb_set_reg: write 1 to enable clock
> + * @enb_clr_reg: write 1 to disable clock
> + * @rst_reg: read the reset status
> + * @rst_set_reg: write 1 to assert the reset of peripheral
> + * @rst_clr_reg: write 1 to deassert the reset of peripheral
> + */
> +struct tegra_clk_periph_regs {
> + u32 enb_reg;
> + u32 enb_set_reg;
> + u32 enb_clr_reg;
> + u32 rst_reg;
> + u32 rst_set_reg;
> + u32 rst_clr_reg;
> +};
> +
> +/**
> + * struct tegra_clk_periph_gate - peripheral gate clock
> + *
> + * @magic: magic number to validate type
> + * @hw: handle between common and hardware-specific interfaces
> + * @clk_base: address of CAR controller
> + * @regs: Registers to control the peripheral
> + * @flags: hardware-specific flags
> + * @clk_num: Clock number
> + * @enable_refcnt: array to maintain reference count of the clock
> + *
> + * Flags:
> + * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
> + * for this module.
> + * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module
> + * after clock enable and driver for the module is responsible for
> + * doing reset.
> + * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
> + * bus to flush the write operation in apb bus. This flag indicates
> + * that this peripheral is in apb bus.
> + */
> +struct tegra_clk_periph_gate {
> + u32 magic;
> + struct clk_hw hw;
> + void __iomem *clk_base;
> + u8 flags;
> + int clk_num;
> + int *enable_refcnt;
> + struct tegra_clk_periph_regs *regs;
> +};
> +
> +#define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309
> +
> +#define TEGRA_PERIPH_NO_RESET BIT(0)
> +#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
> +#define TEGRA_PERIPH_ON_APB BIT(2)
> +
> +void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
> +extern const struct clk_ops tegra_clk_periph_gate_ops;
> +struct clk *tegra_clk_periph_gate(const char *name, const char *parent_name,
> + u8 gate_flags, void __iomem *clk_base,
> + unsigned long flags, int clk_num,
> + struct tegra_clk_periph_regs *pregs,
> + int *enable_refcnt);
> +
> +/**
> + * struct clk-periph - peripheral clock
> + *
> + * @magic: magic number to validate type
> + * @hw: handle between common and hardware-specific interfaces
> + * @mux: mux clock
> + * @divider: divider clock
> + * @gate: gate clock
> + * @mux_ops: mux clock ops
> + * @div_ops: divider clock ops
> + * @gate_ops: gate clock ops
> + */
> +struct tegra_clk_periph {
> + u32 magic;
> + struct clk_hw hw;
> + struct clk_mux mux;
> + struct tegra_clk_frac_div divider;
> + struct tegra_clk_periph_gate gate;
> +
> + const struct clk_ops *mux_ops;
> + const struct clk_ops *div_ops;
> + const struct clk_ops *gate_ops;
> +};
Can be defined in clk-periph.c?
> +
> +#define TEGRA_CLK_PERIPH_MAGIC 0x18221223
> +
> +extern const struct clk_ops tegra_clk_periph_ops;
> +struct clk *tegra_clk_periph(const char *name, const char **parent_names,
> + int num_parents, struct tegra_clk_periph *periph,
> + void __iomem *clk_base, u32 offset);
Not so nice to have the same name as struct. Maybe tegra_clk_register_periph()?
> +struct clk *tegra_clk_periph_nodiv(const char *name, const char **parent_names,
> + int num_parents, struct tegra_clk_periph *periph,
> + void __iomem *clk_base, u32 offset);
Can be inlined func, pointed out in another mail?
> +
> +#define TEGRA_CLK_PERIPH(_mux_shift, _mux_width, _mux_flags, \
> + _div_shift, _div_width, _div_frac_width, \
> + _div_flags, _clk_num, _enb_refcnt, _regs, \
> + _gate_flags) \
> + { \
> + .mux = { \
> + .flags = _mux_flags, \
> + .shift = _mux_shift, \
> + .width = _mux_width, \
> + }, \
> + .divider = { \
> + .flags = _div_flags, \
> + .shift = _div_shift, \
> + .width = _div_width, \
> + .frac_width = _div_frac_width, \
> + }, \
> + .gate = { \
> + .flags = _gate_flags, \
> + .clk_num = _clk_num, \
> + .enable_refcnt = _enb_refcnt, \
> + .regs = _regs, \
> + }, \
> + .mux_ops = &clk_mux_ops, \
> + .div_ops = &tegra_clk_frac_div_ops, \
> + .gate_ops = &tegra_clk_periph_gate_ops, \
> + }
> +
.....
> +/**
> + * struct clk_super_mux - super clock
> + *
> + * @hw: handle between common and hardware-specific interfaces
> + * @reg: register controlling multiplexer
> + * @width: width of the multiplexer bit field
> + * @flags: hardware-specific flags
> + * @div2_index: bit controlling divide-by-2
> + * @pllx_index: PLLX index in the parent list
> + * @lock: register lock
> + *
> + * Flags:
> + * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
> + * that this is LP cluster clock.
> + */
> +struct tegra_clk_super_mux {
> + struct clk_hw hw;
> + void __iomem *reg;
> + u8 width;
> + u8 flags;
> + u8 div2_index;
> + u8 pllx_index;
> + spinlock_t *lock;
> +};
> +
> +#define TEGRA_DIVIDER_2 BIT(0)
> +
> +extern const struct clk_ops tegra_clk_super_ops;
Can be defined in clk-super.c?
> +struct clk *tegra_clk_super_mux(const char *name, const char **parent_names,
> + u8 num_parents, unsigned long flags,
> + void __iomem *reg, u8 clk_super_flags,
> + u8 width, u8 pllx_index, u8 div2_index,
> + spinlock_t *lock);
Better to have different name from struct, like "tegra_clk_register_super_mux()"?
^ permalink raw reply
* [PATCH v6 04/22] mfd: omap-usb-tll: Clean up clock handling
From: Roger Quadros @ 2013-01-16 15:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130116145530.GU23505@n2100.arm.linux.org.uk>
On 01/16/2013 04:55 PM, Russell King - ARM Linux wrote:
> On Wed, Jan 16, 2013 at 04:43:35PM +0200, Roger Quadros wrote:
>> + spin_lock_irqsave(&tll->lock, flags);
>> +
>> + for (i = 0; i < tll->nch; i++) {
>> + char clkname[] = "usb_tll_hs_usb_chx_clk";
>> + struct clk *fck;
>> +
>> + snprintf(clkname, sizeof(clkname),
>> + "usb_tll_hs_usb_ch%d_clk", i);
>> + fck = clk_get(dev, clkname);
>
> NAK. Why are you doing this under a spinlock?
>
> clk_get() takes a mutex. You must not be in an atomic region (iow, you
> must not be holding a spinlock, and you must not have IRQs disabled)
> when you call clk_get().
>
Right. Good catch :).
--
cheers,
-roger.
^ permalink raw reply
* [RFC PATCH 3/4] ARM: bL_entry: Match memory barriers to architectural requirements
From: Catalin Marinas @ 2013-01-16 15:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F64DC7.6040707@ti.com>
Santosh,
On Wed, Jan 16, 2013 at 06:50:47AM +0000, Santosh Shilimkar wrote:
> On Tuesday 15 January 2013 10:18 PM, Dave Martin wrote:
> > For architectural correctness even Strongly-Ordered memory accesses
> > require barriers in order to guarantee that multiple CPUs have a
> > coherent view of the ordering of memory accesses.
> >
> > Virtually everything done by this early code is done via explicit
> > memory access only, so DSBs are seldom required. Existing barriers
> > are demoted to DMB, except where a DSB is needed to synchronise
> > non-memory signalling (i.e., before a SEV). If a particular
> > platform performs cache maintenance in its power_up_setup function,
> > it should force it to complete explicitly including a DSB, instead
> > of relying on the bL_head framework code to do it.
> >
> > Some additional DMBs are added to ensure all the memory ordering
> > properties required by the race avoidance algorithm. DMBs are also
> > moved out of loops, and for clarity some are moved so that most
> > directly follow the memory operation which needs to be
> > synchronised.
> >
> > The setting of a CPU's bL_entry_vectors[] entry is also required to
> > act as a synchronisation point, so a DMB is added after checking
> > that entry to ensure that other CPUs do not observe gated
> > operations leaking across the opening of the gate.
> >
> > Signed-off-by: Dave Martin <dave.martin@linaro.org>
>
> Sorry to pick on this again but I am not able to understand why
> the strongly ordered access needs barriers. At least from the
> ARM point of view, a strongly ordered write will be more of blocking
> write and the further interconnect also is suppose to respect that
> rule. SO read writes are like adding barrier after every load store
> so adding explicit barriers doesn't make sense. Is this a side
> effect of some "write early response" kind of optimizations at
> interconnect level ?
SO or Device memory accesses are *not* like putting a proper barrier
between each access, though it may behave in some situations like having
a barrier. The ARM ARM (A3.8.3, fig 3.5) defines how accesses must
*arrive* at a peripheral or block of memory depending on the memory type
and in case of Device or SO we don't need additional barriers because
such accesses would *arrive* in order (given the minimum 1KB range
restriction). But it does not say anything about *observability* by a
different *master*. That's because you can't guarantee that your memory
accesses go to the same slave port.
For observability by a different master, you need an explicit DMB even
though the memory type is Device or SO. While it may work fine in most
cases (especially when the accesses by various masters go to the same
slave port), you can't be sure what the memory controller or whatever
interconnect do.
As Dave said, it's more about what the ARM ARM doesn't say rather than
what it explicitly states.
--
Catalin
^ permalink raw reply
* [RFC PATCH 6/6] USB: MUSB: OMAP: get PHY by phandle for dt boot
From: Kishon Vijay Abraham I @ 2013-01-16 15:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358348462-27693-1-git-send-email-kishon@ti.com>
The OMAP glue has been modified to get PHY by phandle for dt boot.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/usb/musb/omap2430.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 3628a50..08709cf 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -346,7 +346,12 @@ static int omap2430_musb_init(struct musb *musb)
* up through ULPI. TWL4030-family PMICs include one,
* which needs a driver, drivers aren't always needed.
*/
- musb->xceiv = devm_usb_get_phy(dev, 0);
+ if (dev->parent->of_node)
+ musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent,
+ "usb_phy", 0);
+ else
+ musb->xceiv = devm_usb_get_phy(dev, 0);
+
if (IS_ERR_OR_NULL(musb->xceiv)) {
pr_err("HS USB OTG: no transceiver configured\n");
return -ENODEV;
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH 5/6] usb: otg: add device tree support to otg library
From: Kishon Vijay Abraham I @ 2013-01-16 15:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358348462-27693-1-git-send-email-kishon@ti.com>
Added an API devm_usb_get_phy_by_phandle(), to get usb phy by passing a
device node phandle value. This function will return a pointer to
the phy on success, -EPROBE_DEFER if there is a device_node for the phandle,
but the phy has not been added, or a ERR_PTR() otherwise.
Cc: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/usb/otg/otg.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++
include/linux/usb/phy.h | 8 +++++
2 files changed, 85 insertions(+)
diff --git a/drivers/usb/otg/otg.c b/drivers/usb/otg/otg.c
index dbf2043..e9799bb 100644
--- a/drivers/usb/otg/otg.c
+++ b/drivers/usb/otg/otg.c
@@ -13,7 +13,9 @@
#include <linux/export.h>
#include <linux/err.h>
#include <linux/device.h>
+#include <linux/module.h>
#include <linux/slab.h>
+#include <linux/of.h>
#include <linux/usb/otg.h>
@@ -34,6 +36,20 @@ static struct usb_phy *__usb_find_phy(struct device *dev, u8 index)
return ERR_PTR(-ENODEV);
}
+static struct usb_phy *__of_usb_find_phy(struct device_node *node)
+{
+ struct usb_phy *phy;
+
+ list_for_each_entry(phy, &phy_list, head) {
+ if (node != phy->dev->of_node)
+ continue;
+
+ return phy;
+ }
+
+ return ERR_PTR(-ENODEV);
+}
+
static void devm_usb_phy_release(struct device *dev, void *res)
{
struct usb_phy *phy = *(struct usb_phy **)res;
@@ -109,6 +125,67 @@ err0:
}
EXPORT_SYMBOL(usb_get_phy);
+ /**
+ * devm_usb_get_phy_by_phandle - find the USB PHY by phandle
+ * @dev - device that requests this phy
+ * @phandle - name of the property holding the phy phandle value
+ * @index - the index of the phy
+ *
+ * Returns the phy driver associated with the given phandle value,
+ * after getting a refcount to it, -ENODEV if there is no such phy or
+ * -EPROBE_DEFER if there is a phandle to the phy, but the device is
+ * not yet loaded. While at that, it also associates the device with
+ * the phy using devres. On driver detach, release function is invoked
+ * on the devres data, then, devres data is freed.
+ *
+ * For use by USB host and peripheral drivers.
+ */
+struct usb_phy *devm_usb_get_phy_by_phandle(struct device *dev,
+ const char *phandle, u8 index)
+{
+ struct usb_phy *phy = NULL, **ptr;
+ unsigned long flags;
+ struct device_node *node;
+
+ if (!dev->of_node) {
+ dev_dbg(dev, "device does not have a device node entry\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ node = of_parse_phandle(dev->of_node, phandle, index);
+ if (!node) {
+ dev_dbg(dev, "failed to get %s phandle in %s node\n", phandle,
+ dev->of_node->full_name);
+ return ERR_PTR(-ENODEV);
+ }
+
+ ptr = devres_alloc(devm_usb_phy_release, sizeof(*ptr), GFP_KERNEL);
+ if (!ptr) {
+ dev_dbg(dev, "failed to allocate memory for devres\n");
+ return ERR_PTR(-ENOMEM);
+ }
+
+ spin_lock_irqsave(&phy_lock, flags);
+
+ phy = __of_usb_find_phy(node);
+ if (IS_ERR(phy) || !try_module_get(phy->dev->driver->owner)) {
+ phy = ERR_PTR(-EPROBE_DEFER);
+ devres_free(ptr);
+ goto err0;
+ }
+
+ *ptr = phy;
+ devres_add(dev, ptr);
+
+ get_device(phy->dev);
+
+err0:
+ spin_unlock_irqrestore(&phy_lock, flags);
+
+ return phy;
+}
+EXPORT_SYMBOL(devm_usb_get_phy_by_phandle);
+
/**
* devm_usb_put_phy - release the USB PHY
* @dev - device that wants to release this phy
diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h
index d133c8b..5836b6d 100644
--- a/include/linux/usb/phy.h
+++ b/include/linux/usb/phy.h
@@ -163,6 +163,8 @@ usb_phy_shutdown(struct usb_phy *x)
#ifdef CONFIG_USB_OTG_UTILS
extern struct usb_phy *usb_get_phy(struct device *dev, u8 index);
extern struct usb_phy *devm_usb_get_phy(struct device *dev, u8 index);
+extern struct usb_phy *devm_usb_get_phy_by_phandle(struct device *dev,
+ const char *phandle, u8 index);
extern void usb_put_phy(struct usb_phy *);
extern void devm_usb_put_phy(struct device *dev, struct usb_phy *x);
extern struct usb_phy_bind *usb_bind_phy(const char *dev_name, u8 index,
@@ -178,6 +180,12 @@ static inline struct usb_phy *devm_usb_get_phy(struct device *dev, u8 index)
return NULL;
}
+static inline struct usb_phy *devm_usb_get_phy_by_phandle(struct device *dev,
+ const char *phandle, u8 index)
+{
+ return NULL;
+}
+
static inline void usb_put_phy(struct usb_phy *x)
{
}
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH 4/6] ARM: dts: OMAP: Add phandle to bind PHY with USB controller
From: Kishon Vijay Abraham I @ 2013-01-16 15:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358348462-27693-1-git-send-email-kishon@ti.com>
Added a phandle in the dt node for usb_otg to bind the PHY with the USB
controller and also updated the documentation with the binding information.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
I'll add this patch in this series "usb: musb: add driver for control module"
which contains the dt data to get MUSB working in dt boot in OMAP platforms.
Documentation/devicetree/bindings/usb/omap-usb.txt | 2 ++
arch/arm/boot/dts/omap3.dtsi | 1 +
arch/arm/boot/dts/omap4.dtsi | 3 ++-
arch/arm/boot/dts/twl4030.dtsi | 2 +-
4 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt
index 3f0152b..591c4fc 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -18,6 +18,7 @@ OMAP MUSB GLUE
represents PERIPHERAL.
- power : Should be "50". This signifies the controller can supply upto
100mA when operating in host mode.
+ - usb_phy : the phandle for the PHY device
SOC specific device node entry
usb_otg_hs: usb_otg_hs at 4a0ab000 {
@@ -27,6 +28,7 @@ usb_otg_hs: usb_otg_hs at 4a0ab000 {
multipoint = <1>;
num_eps = <16>;
ram_bits = <12>;
+ usb_phy = <&phy>;
};
Board specific device node entry
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 8d03736..ebbf596 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -404,6 +404,7 @@
interrupts = <0 92 0x4>, <0 93 0x4>;
interrupt-names = "mc", "dma";
ti,hwmods = "usb_otg_hs";
+ usb_phy = <&phy>;
multipoint = <1>;
num_eps = <16>;
ram_bits = <12>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 5d770be..531cb2d 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -438,7 +438,7 @@
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp_usb_phy";
- usb2phy at 4a0ad080 {
+ phy: usb2phy at 4a0ad080 {
compatible = "ti,omap-usb2";
reg = <0x4a0ad080 0x58>;
};
@@ -540,6 +540,7 @@
interrupts = <0 92 0x4>, <0 93 0x4>;
interrupt-names = "mc", "dma";
ti,hwmods = "usb_otg_hs";
+ usb_phy = <&phy>;
multipoint = <1>;
num_eps = <16>;
ram_bits = <12>;
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index ed0bc95..80f7c2b 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -67,7 +67,7 @@
#interrupt-cells = <1>;
};
- twl4030-usb {
+ phy: twl4030-usb {
compatible = "ti,twl4030-usb";
interrupts = <10>, <4>;
usb1v5-supply = <&vusb1v5>;
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH 3/6] usb: otg: utils: change the phy lib to support multiple PHYs of same type
From: Kishon Vijay Abraham I @ 2013-01-16 15:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358348462-27693-1-git-send-email-kishon@ti.com>
In order to add support for multipe PHY's of the same type, the API's
for adding PHY and getting PHY has been changed. Now the binding
information of the PHY and controller should be done in platform file
using usb_bind_phy API. And for getting a PHY, the device pointer of the
USB controller and an index should be passed. Based on the binding
information that is added in the platform file, get_phy will return the
approappropriate PHY.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/mach-shmobile/board-marzen.c | 2 +-
drivers/power/ab8500_charger.c | 2 +-
drivers/power/isp1704_charger.c | 2 +-
drivers/power/pda_power.c | 2 +-
drivers/power/twl4030_charger.c | 2 +-
drivers/usb/chipidea/udc.c | 2 +-
drivers/usb/dwc3/core.c | 4 +-
drivers/usb/gadget/fsl_udc_core.c | 2 +-
drivers/usb/gadget/mv_udc_core.c | 2 +-
drivers/usb/gadget/omap_udc.c | 2 +-
drivers/usb/gadget/pxa25x_udc.c | 2 +-
drivers/usb/gadget/pxa27x_udc.c | 2 +-
drivers/usb/gadget/s3c-hsudc.c | 2 +-
drivers/usb/host/ehci-fsl.c | 2 +-
drivers/usb/host/ehci-msm.c | 2 +-
drivers/usb/host/ehci-mv.c | 2 +-
drivers/usb/host/ehci-tegra.c | 2 +-
drivers/usb/host/ohci-omap.c | 2 +-
drivers/usb/musb/am35x.c | 2 +-
drivers/usb/musb/blackfin.c | 2 +-
drivers/usb/musb/da8xx.c | 2 +-
drivers/usb/musb/davinci.c | 2 +-
drivers/usb/musb/musb_dsps.c | 2 +-
drivers/usb/musb/omap2430.c | 2 +-
drivers/usb/musb/tusb6010.c | 2 +-
drivers/usb/musb/ux500.c | 2 +-
drivers/usb/otg/ab8500-usb.c | 3 +-
drivers/usb/otg/fsl_otg.c | 5 ++-
drivers/usb/otg/gpio_vbus.c | 3 +-
drivers/usb/otg/isp1301_omap.c | 3 +-
drivers/usb/otg/msm_otg.c | 3 +-
drivers/usb/otg/mv_otg.c | 3 +-
drivers/usb/otg/nop-usb-xceiv.c | 3 +-
drivers/usb/otg/otg.c | 67 +++++++++++++++------------------
drivers/usb/otg/twl4030-usb.c | 3 +-
drivers/usb/phy/mv_u3d_phy.c | 3 +-
drivers/usb/phy/omap-usb2.c | 11 ++----
drivers/usb/phy/rcar-phy.c | 3 +-
include/linux/usb/phy.h | 12 +++---
39 files changed, 87 insertions(+), 89 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 449f928..abe482d 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -320,7 +320,7 @@ static struct platform_device *marzen_late_devices[] __initdata = {
void __init marzen_init_late(void)
{
/* get usb phy */
- phy = usb_get_phy(USB_PHY_TYPE_USB2);
+ phy = usb_get_phy(&ehci0_device.dev, 0);
shmobile_init_late();
platform_add_devices(marzen_late_devices,
diff --git a/drivers/power/ab8500_charger.c b/drivers/power/ab8500_charger.c
index 3be9c0e..d20561a 100644
--- a/drivers/power/ab8500_charger.c
+++ b/drivers/power/ab8500_charger.c
@@ -2694,7 +2694,7 @@ static int ab8500_charger_probe(struct platform_device *pdev)
goto free_ac;
}
- di->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
+ di->usb_phy = usb_get_phy(di->dev, 0);
if (IS_ERR_OR_NULL(di->usb_phy)) {
dev_err(di->dev, "failed to get usb transceiver\n");
ret = -EINVAL;
diff --git a/drivers/power/isp1704_charger.c b/drivers/power/isp1704_charger.c
index 176ad59..dfbe597 100644
--- a/drivers/power/isp1704_charger.c
+++ b/drivers/power/isp1704_charger.c
@@ -415,7 +415,7 @@ static int isp1704_charger_probe(struct platform_device *pdev)
if (!isp)
return -ENOMEM;
- isp->phy = usb_get_phy(USB_PHY_TYPE_USB2);
+ isp->phy = usb_get_phy(&pdev->dev, 0);
if (IS_ERR_OR_NULL(isp->phy))
goto fail0;
diff --git a/drivers/power/pda_power.c b/drivers/power/pda_power.c
index 7df7c5f..64d79f7 100644
--- a/drivers/power/pda_power.c
+++ b/drivers/power/pda_power.c
@@ -316,7 +316,7 @@ static int pda_power_probe(struct platform_device *pdev)
}
#ifdef CONFIG_USB_OTG_UTILS
- transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+ transceiver = usb_get_phy(&pdev->dev, 0);
if (!IS_ERR_OR_NULL(transceiver)) {
if (!pdata->is_usb_online)
pdata->is_usb_online = otg_is_usb_online;
diff --git a/drivers/power/twl4030_charger.c b/drivers/power/twl4030_charger.c
index a69d0d1..f53b417 100644
--- a/drivers/power/twl4030_charger.c
+++ b/drivers/power/twl4030_charger.c
@@ -552,7 +552,7 @@ static int __init twl4030_bci_probe(struct platform_device *pdev)
INIT_WORK(&bci->work, twl4030_bci_usb_work);
- bci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+ bci->transceiver = usb_get_phy(&pdev->dev, 0);
if (!IS_ERR_OR_NULL(bci->transceiver)) {
bci->usb_nb.notifier_call = twl4030_bci_usb_ncb;
usb_register_notifier(bci->transceiver, &bci->usb_nb);
diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 2f45bba..ea6a109 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -1745,7 +1745,7 @@ static int udc_start(struct ci13xxx *ci)
ci->gadget.ep0 = &ci->ep0in->ep;
if (ci->global_phy)
- ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+ ci->transceiver = usb_get_phy(dev, 0);
if (ci->platdata->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
if (ci->transceiver == NULL) {
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 3a4004a..574d4b7 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -420,13 +420,13 @@ static int dwc3_probe(struct platform_device *pdev)
return -ENOMEM;
}
- dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+ dwc->usb2_phy = devm_usb_get_phy(dev, 0);
if (IS_ERR_OR_NULL(dwc->usb2_phy)) {
dev_err(dev, "no usb2 phy configured\n");
return -EPROBE_DEFER;
}
- dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
+ dwc->usb3_phy = devm_usb_get_phy(dev, 1);
if (IS_ERR_OR_NULL(dwc->usb3_phy)) {
dev_err(dev, "no usb3 phy configured\n");
return -EPROBE_DEFER;
diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c
index c19f7f1..9c1a7a6 100644
--- a/drivers/usb/gadget/fsl_udc_core.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -2456,7 +2456,7 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
#ifdef CONFIG_USB_OTG
if (pdata->operating_mode == FSL_USB2_DR_OTG) {
- udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+ udc_controller->transceiver = usb_get_phy(&pdev->dev, 0);
if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
ERR("Can't find OTG driver!\n");
ret = -ENODEV;
diff --git a/drivers/usb/gadget/mv_udc_core.c b/drivers/usb/gadget/mv_udc_core.c
index 379aac7..9aef556 100644
--- a/drivers/usb/gadget/mv_udc_core.c
+++ b/drivers/usb/gadget/mv_udc_core.c
@@ -2218,7 +2218,7 @@ static int mv_udc_probe(struct platform_device *dev)
#ifdef CONFIG_USB_OTG_UTILS
if (pdata->mode == MV_USB_MODE_OTG)
- udc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+ udc->transceiver = usb_get_phy(&dev->dev, 0);
#endif
udc->clknum = pdata->clknum;
diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c
index 8bfe990..5352ede 100644
--- a/drivers/usb/gadget/omap_udc.c
+++ b/drivers/usb/gadget/omap_udc.c
@@ -2833,7 +2833,7 @@ static int omap_udc_probe(struct platform_device *pdev)
* use it. Except for OTG, we don't _need_ to talk to one;
* but not having one probably means no VBUS detection.
*/
- xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
+ xceiv = usb_get_phy(&pdev->dev, 0);
if (!IS_ERR_OR_NULL(xceiv))
type = xceiv->label;
else if (config->otg) {
diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c
index d4ca9f1..666f2c0c 100644
--- a/drivers/usb/gadget/pxa25x_udc.c
+++ b/drivers/usb/gadget/pxa25x_udc.c
@@ -2157,7 +2157,7 @@ static int __init pxa25x_udc_probe(struct platform_device *pdev)
dev->dev = &pdev->dev;
dev->mach = pdev->dev.platform_data;
- dev->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+ dev->transceiver = usb_get_phy(dev->dev, 0);
if (gpio_is_valid(dev->mach->gpio_pullup)) {
if ((retval = gpio_request(dev->mach->gpio_pullup,
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 2b3b01d..844138c 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -2465,7 +2465,7 @@ static int __init pxa_udc_probe(struct platform_device *pdev)
udc->dev = &pdev->dev;
udc->mach = pdev->dev.platform_data;
- udc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+ udc->transceiver = usb_get_phy(udc->dev, 0);
gpio = udc->mach->gpio_pullup;
if (gpio_is_valid(gpio)) {
diff --git a/drivers/usb/gadget/s3c-hsudc.c b/drivers/usb/gadget/s3c-hsudc.c
index 52379b1..c1ca9f4 100644
--- a/drivers/usb/gadget/s3c-hsudc.c
+++ b/drivers/usb/gadget/s3c-hsudc.c
@@ -1281,7 +1281,7 @@ static int s3c_hsudc_probe(struct platform_device *pdev)
hsudc->dev = dev;
hsudc->pd = pdev->dev.platform_data;
- hsudc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+ hsudc->transceiver = usb_get_phy(hsudc->dev, 0);
for (i = 0; i < ARRAY_SIZE(hsudc->supplies); i++)
hsudc->supplies[i].supply = s3c_hsudc_supply_names[i];
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index fd9b542..517df2e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -143,7 +143,7 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
if (pdata->operating_mode == FSL_USB2_DR_OTG) {
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
- hcd->phy = usb_get_phy(USB_PHY_TYPE_USB2);
+ hcd->phy = usb_get_phy(&pdev->dev, 0);
dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
hcd, ehci, hcd->phy);
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index 88a49c8..39abbdb 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -144,7 +144,7 @@ static int ehci_msm_probe(struct platform_device *pdev)
* powering up VBUS, mapping of registers address space and power
* management.
*/
- phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
+ phy = devm_usb_get_phy(&pdev->dev, 0);
if (IS_ERR_OR_NULL(phy)) {
dev_err(&pdev->dev, "unable to find transceiver\n");
ret = -ENODEV;
diff --git a/drivers/usb/host/ehci-mv.c b/drivers/usb/host/ehci-mv.c
index f7bfc0b..6316950 100644
--- a/drivers/usb/host/ehci-mv.c
+++ b/drivers/usb/host/ehci-mv.c
@@ -241,7 +241,7 @@ static int mv_ehci_probe(struct platform_device *pdev)
ehci_mv->mode = pdata->mode;
if (ehci_mv->mode == MV_USB_MODE_OTG) {
#ifdef CONFIG_USB_OTG_UTILS
- ehci_mv->otg = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
+ ehci_mv->otg = devm_usb_get_phy(&pdev->dev, 0);
if (IS_ERR_OR_NULL(ehci_mv->otg)) {
dev_err(&pdev->dev,
"unable to find transceiver\n");
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index acf1755..7a081df 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -733,7 +733,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
#ifdef CONFIG_USB_OTG_UTILS
if (pdata->operating_mode == TEGRA_USB_OTG) {
tegra->transceiver =
- devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
+ devm_usb_get_phy(&pdev->dev, 0);
if (!IS_ERR_OR_NULL(tegra->transceiver))
otg_set_host(tegra->transceiver->otg, &hcd->self);
}
diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
index b1d32fb..bd823d2 100644
--- a/drivers/usb/host/ohci-omap.c
+++ b/drivers/usb/host/ohci-omap.c
@@ -213,7 +213,7 @@ static int ohci_omap_init(struct usb_hcd *hcd)
#ifdef CONFIG_USB_OTG
if (need_transceiver) {
- hcd->phy = usb_get_phy(USB_PHY_TYPE_USB2);
+ hcd->phy = usb_get_phy(hcd->self.controller, 0);
if (!IS_ERR_OR_NULL(hcd->phy)) {
int status = otg_set_host(hcd->phy->otg,
&ohci_to_hcd(ohci)->self);
diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c
index c107d7c..b7a8c94 100644
--- a/drivers/usb/musb/am35x.c
+++ b/drivers/usb/musb/am35x.c
@@ -363,7 +363,7 @@ static int am35x_musb_init(struct musb *musb)
return -ENODEV;
usb_nop_xceiv_register();
- musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
+ musb->xceiv = usb_get_phy(dev, 0);
if (IS_ERR_OR_NULL(musb->xceiv))
return -ENODEV;
diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
index 14dab9f..596bc5b 100644
--- a/drivers/usb/musb/blackfin.c
+++ b/drivers/usb/musb/blackfin.c
@@ -403,7 +403,7 @@ static int bfin_musb_init(struct musb *musb)
gpio_direction_output(musb->config->gpio_vrsel, 0);
usb_nop_xceiv_register();
- musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
+ musb->xceiv = usb_get_phy(musb->controller, 0);
if (IS_ERR_OR_NULL(musb->xceiv)) {
gpio_free(musb->config->gpio_vrsel);
return -ENODEV;
diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
index 97996af..a01844e 100644
--- a/drivers/usb/musb/da8xx.c
+++ b/drivers/usb/musb/da8xx.c
@@ -419,7 +419,7 @@ static int da8xx_musb_init(struct musb *musb)
goto fail;
usb_nop_xceiv_register();
- musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
+ musb->xceiv = usb_get_phy(musb->controller, 0);
if (IS_ERR_OR_NULL(musb->xceiv))
goto fail;
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index b1c01ca..66aa3f0 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -382,7 +382,7 @@ static int davinci_musb_init(struct musb *musb)
u32 revision;
usb_nop_xceiv_register();
- musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
+ musb->xceiv = usb_get_phy(musb->controller, 0);
if (IS_ERR_OR_NULL(musb->xceiv))
goto unregister;
diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps.c
index e6f2ae8..d71cbf5 100644
--- a/drivers/usb/musb/musb_dsps.c
+++ b/drivers/usb/musb/musb_dsps.c
@@ -412,7 +412,7 @@ static int dsps_musb_init(struct musb *musb)
/* NOP driver needs change if supporting dual instance */
usb_nop_xceiv_register();
- musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
+ musb->xceiv = usb_get_phy(dev, 0);
if (IS_ERR_OR_NULL(musb->xceiv))
return -ENODEV;
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 3e7ceef..3628a50 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -346,7 +346,7 @@ static int omap2430_musb_init(struct musb *musb)
* up through ULPI. TWL4030-family PMICs include one,
* which needs a driver, drivers aren't always needed.
*/
- musb->xceiv = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+ musb->xceiv = devm_usb_get_phy(dev, 0);
if (IS_ERR_OR_NULL(musb->xceiv)) {
pr_err("HS USB OTG: no transceiver configured\n");
return -ENODEV;
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
index 3969813..02338f6 100644
--- a/drivers/usb/musb/tusb6010.c
+++ b/drivers/usb/musb/tusb6010.c
@@ -1067,7 +1067,7 @@ static int tusb_musb_init(struct musb *musb)
int ret;
usb_nop_xceiv_register();
- musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
+ musb->xceiv = usb_get_phy(musb->controller, 0);
if (IS_ERR_OR_NULL(musb->xceiv))
return -ENODEV;
diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c
index a27ca1a..5affcf7 100644
--- a/drivers/usb/musb/ux500.c
+++ b/drivers/usb/musb/ux500.c
@@ -58,7 +58,7 @@ static irqreturn_t ux500_musb_interrupt(int irq, void *__hci)
static int ux500_musb_init(struct musb *musb)
{
- musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
+ musb->xceiv = usb_get_phy(musb->controller, 0);
if (IS_ERR_OR_NULL(musb->xceiv)) {
pr_err("HS USB OTG: no transceiver configured\n");
return -ENODEV;
diff --git a/drivers/usb/otg/ab8500-usb.c b/drivers/usb/otg/ab8500-usb.c
index 2d86f26..07aeb8c 100644
--- a/drivers/usb/otg/ab8500-usb.c
+++ b/drivers/usb/otg/ab8500-usb.c
@@ -502,6 +502,7 @@ static int ab8500_usb_probe(struct platform_device *pdev)
ab->phy.set_suspend = ab8500_usb_set_suspend;
ab->phy.set_power = ab8500_usb_set_power;
ab->phy.state = OTG_STATE_UNDEFINED;
+ ab->phy.type = USB_PHY_TYPE_USB2;
otg->phy = &ab->phy;
otg->set_host = ab8500_usb_set_host;
@@ -529,7 +530,7 @@ static int ab8500_usb_probe(struct platform_device *pdev)
if (err < 0)
goto fail0;
- err = usb_add_phy(&ab->phy, USB_PHY_TYPE_USB2);
+ err = usb_add_phy(&ab->phy);
if (err) {
dev_err(&pdev->dev, "Can't register transceiver\n");
goto fail1;
diff --git a/drivers/usb/otg/fsl_otg.c b/drivers/usb/otg/fsl_otg.c
index d16adb4..ae6d3f5 100644
--- a/drivers/usb/otg/fsl_otg.c
+++ b/drivers/usb/otg/fsl_otg.c
@@ -810,6 +810,7 @@ static int fsl_otg_conf(struct platform_device *pdev)
/* initialize the otg structure */
fsl_otg_tc->phy.label = DRIVER_DESC;
fsl_otg_tc->phy.set_power = fsl_otg_set_power;
+ fsl_otg_tc->phy.type = USB_PHY_TYPE_USB2;
fsl_otg_tc->phy.otg->phy = &fsl_otg_tc->phy;
fsl_otg_tc->phy.otg->set_host = fsl_otg_set_host;
@@ -820,7 +821,7 @@ static int fsl_otg_conf(struct platform_device *pdev)
fsl_otg_dev = fsl_otg_tc;
/* Store the otg transceiver */
- status = usb_add_phy(&fsl_otg_tc->phy, USB_PHY_TYPE_USB2);
+ status = usb_add_phy(&fsl_otg_tc->phy);
if (status) {
pr_warn(FSL_OTG_NAME ": unable to register OTG transceiver.\n");
goto err;
@@ -838,7 +839,7 @@ err:
int usb_otg_start(struct platform_device *pdev)
{
struct fsl_otg *p_otg;
- struct usb_phy *otg_trans = usb_get_phy(USB_PHY_TYPE_USB2);
+ struct usb_phy *otg_trans = usb_get_phy(&pdev->dev, 0);
struct otg_fsm *fsm;
int status;
struct resource *res;
diff --git a/drivers/usb/otg/gpio_vbus.c b/drivers/usb/otg/gpio_vbus.c
index a67ffe2..815e8dc 100644
--- a/drivers/usb/otg/gpio_vbus.c
+++ b/drivers/usb/otg/gpio_vbus.c
@@ -264,6 +264,7 @@ static int __init gpio_vbus_probe(struct platform_device *pdev)
gpio_vbus->phy.set_power = gpio_vbus_set_power;
gpio_vbus->phy.set_suspend = gpio_vbus_set_suspend;
gpio_vbus->phy.state = OTG_STATE_UNDEFINED;
+ gpio_vbus->phy.type = USB_PHY_TYPE_USB2;
gpio_vbus->phy.otg->phy = &gpio_vbus->phy;
gpio_vbus->phy.otg->set_peripheral = gpio_vbus_set_peripheral;
@@ -320,7 +321,7 @@ static int __init gpio_vbus_probe(struct platform_device *pdev)
}
/* only active when a gadget is registered */
- err = usb_add_phy(&gpio_vbus->phy, USB_PHY_TYPE_USB2);
+ err = usb_add_phy(&gpio_vbus->phy);
if (err) {
dev_err(&pdev->dev, "can't register transceiver, err: %d\n",
err);
diff --git a/drivers/usb/otg/isp1301_omap.c b/drivers/usb/otg/isp1301_omap.c
index af9cb11..c85b309 100644
--- a/drivers/usb/otg/isp1301_omap.c
+++ b/drivers/usb/otg/isp1301_omap.c
@@ -1587,6 +1587,7 @@ isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
isp->phy.dev = &i2c->dev;
isp->phy.label = DRIVER_NAME;
isp->phy.set_power = isp1301_set_power,
+ isp->phy.type = USB_PHY_TYPE_USB2,
isp->phy.otg->phy = &isp->phy;
isp->phy.otg->set_host = isp1301_set_host,
@@ -1610,7 +1611,7 @@ isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
dev_dbg(&i2c->dev, "scheduled timer, %d min\n", TIMER_MINUTES);
#endif
- status = usb_add_phy(&isp->phy, USB_PHY_TYPE_USB2);
+ status = usb_add_phy(&isp->phy);
if (status < 0)
dev_err(&i2c->dev, "can't register transceiver, %d\n",
status);
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 3b9f0d9..5376d84 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -1548,6 +1548,7 @@ static int __init msm_otg_probe(struct platform_device *pdev)
phy->init = msm_otg_reset;
phy->set_power = msm_otg_set_power;
+ phy->phy_type = USB_PHY_TYPE_USB2;
phy->io_ops = &msm_otg_io_ops;
@@ -1555,7 +1556,7 @@ static int __init msm_otg_probe(struct platform_device *pdev)
phy->otg->set_host = msm_otg_set_host;
phy->otg->set_peripheral = msm_otg_set_peripheral;
- ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2);
+ ret = usb_add_phy(&motg->phy);
if (ret) {
dev_err(&pdev->dev, "usb_add_phy failed\n");
goto free_irq;
diff --git a/drivers/usb/otg/mv_otg.c b/drivers/usb/otg/mv_otg.c
index 1dd5750..2167e41 100644
--- a/drivers/usb/otg/mv_otg.c
+++ b/drivers/usb/otg/mv_otg.c
@@ -755,6 +755,7 @@ static int mv_otg_probe(struct platform_device *pdev)
mvotg->phy.otg = otg;
mvotg->phy.label = driver_name;
mvotg->phy.state = OTG_STATE_UNDEFINED;
+ mvotg->phy.type = USB_PHY_TYPE_USB2;
otg->phy = &mvotg->phy;
otg->set_host = mv_otg_set_host;
@@ -853,7 +854,7 @@ static int mv_otg_probe(struct platform_device *pdev)
goto err_disable_clk;
}
- retval = usb_add_phy(&mvotg->phy, USB_PHY_TYPE_USB2);
+ retval = usb_add_phy(&mvotg->phy);
if (retval < 0) {
dev_err(&pdev->dev, "can't register transceiver, %d\n",
retval);
diff --git a/drivers/usb/otg/nop-usb-xceiv.c b/drivers/usb/otg/nop-usb-xceiv.c
index a3ce24b..d8d72f6 100644
--- a/drivers/usb/otg/nop-usb-xceiv.c
+++ b/drivers/usb/otg/nop-usb-xceiv.c
@@ -118,12 +118,13 @@ static int nop_usb_xceiv_probe(struct platform_device *pdev)
nop->phy.label = "nop-xceiv";
nop->phy.set_suspend = nop_set_suspend;
nop->phy.state = OTG_STATE_UNDEFINED;
+ nop->phy.type = type;
nop->phy.otg->phy = &nop->phy;
nop->phy.otg->set_host = nop_set_host;
nop->phy.otg->set_peripheral = nop_set_peripheral;
- err = usb_add_phy(&nop->phy, type);
+ err = usb_add_phy(&nop->phy);
if (err) {
dev_err(&pdev->dev, "can't register transceiver, err: %d\n",
err);
diff --git a/drivers/usb/otg/otg.c b/drivers/usb/otg/otg.c
index 492ba2f..dbf2043 100644
--- a/drivers/usb/otg/otg.c
+++ b/drivers/usb/otg/otg.c
@@ -21,16 +21,14 @@ static LIST_HEAD(phy_list);
static LIST_HEAD(phy_bind_list);
static DEFINE_SPINLOCK(phy_lock);
-static struct usb_phy *__usb_find_phy(struct list_head *list,
- enum usb_phy_type type)
+static struct usb_phy *__usb_find_phy(struct device *dev, u8 index)
{
- struct usb_phy *phy = NULL;
+ struct usb_phy_bind *phy_bind = NULL;
- list_for_each_entry(phy, list, head) {
- if (phy->type != type)
- continue;
-
- return phy;
+ list_for_each_entry(phy_bind, &phy_bind_list, list) {
+ if (!(strcmp(phy_bind->dev_name, dev_name(dev))) &&
+ phy_bind->index == index)
+ return phy_bind->phy;
}
return ERR_PTR(-ENODEV);
@@ -51,7 +49,7 @@ static int devm_usb_phy_match(struct device *dev, void *res, void *match_data)
/**
* devm_usb_get_phy - find the USB PHY
* @dev - device that requests this phy
- * @type - the type of the phy the controller requires
+ * @index - the index of the phy
*
* Gets the phy using usb_get_phy(), and associates a device with it using
* devres. On driver detach, release function is invoked on the devres data,
@@ -59,7 +57,7 @@ static int devm_usb_phy_match(struct device *dev, void *res, void *match_data)
*
* For use by USB host and peripheral drivers.
*/
-struct usb_phy *devm_usb_get_phy(struct device *dev, enum usb_phy_type type)
+struct usb_phy *devm_usb_get_phy(struct device *dev, u8 index)
{
struct usb_phy **ptr, *phy;
@@ -67,7 +65,7 @@ struct usb_phy *devm_usb_get_phy(struct device *dev, enum usb_phy_type type)
if (!ptr)
return NULL;
- phy = usb_get_phy(type);
+ phy = usb_get_phy(dev, index);
if (!IS_ERR(phy)) {
*ptr = phy;
devres_add(dev, ptr);
@@ -80,7 +78,8 @@ EXPORT_SYMBOL(devm_usb_get_phy);
/**
* usb_get_phy - find the USB PHY
- * @type - the type of the phy the controller requires
+ * @dev - device that requests this phy
+ * @index - the index of the phy
*
* Returns the phy driver, after getting a refcount to it; or
* -ENODEV if there is no such phy. The caller is responsible for
@@ -88,17 +87,16 @@ EXPORT_SYMBOL(devm_usb_get_phy);
*
* For use by USB host and peripheral drivers.
*/
-struct usb_phy *usb_get_phy(enum usb_phy_type type)
+struct usb_phy *usb_get_phy(struct device *dev, u8 index)
{
struct usb_phy *phy = NULL;
unsigned long flags;
spin_lock_irqsave(&phy_lock, flags);
- phy = __usb_find_phy(&phy_list, type);
+ phy = __usb_find_phy(dev, index);
if (IS_ERR(phy)) {
- pr_err("unable to find transceiver of type %s\n",
- usb_phy_type_string(type));
+ pr_err("unable to find phy\n");
goto err0;
}
@@ -148,40 +146,30 @@ EXPORT_SYMBOL(usb_put_phy);
/**
* usb_add_phy - declare the USB PHY
* @x: the USB phy to be used; or NULL
- * @type - the type of this PHY
*
* This call is exclusively for use by phy drivers, which
* coordinate the activities of drivers for host and peripheral
* controllers, and in some cases for VBUS current regulation.
*/
-int usb_add_phy(struct usb_phy *x, enum usb_phy_type type)
+int usb_add_phy(struct usb_phy *x)
{
- int ret = 0;
- unsigned long flags;
- struct usb_phy *phy;
+ struct usb_phy_bind *phy_bind;
+ unsigned long flags;
- if (x->type != USB_PHY_TYPE_UNDEFINED) {
- dev_err(x->dev, "not accepting initialized PHY %s\n", x->label);
+ if (!x->dev) {
+ dev_err(x->dev, "no device provided for PHY\n");
return -EINVAL;
}
spin_lock_irqsave(&phy_lock, flags);
+ list_for_each_entry(phy_bind, &phy_bind_list, list)
+ if (!(strcmp(phy_bind->phy_dev_name, dev_name(x->dev))))
+ phy_bind->phy = x;
- list_for_each_entry(phy, &phy_list, head) {
- if (phy->type == type) {
- ret = -EBUSY;
- dev_err(x->dev, "transceiver type %s already exists\n",
- usb_phy_type_string(type));
- goto out;
- }
- }
-
- x->type = type;
list_add_tail(&x->head, &phy_list);
-
-out:
spin_unlock_irqrestore(&phy_lock, flags);
- return ret;
+
+ return 0;
}
EXPORT_SYMBOL(usb_add_phy);
@@ -194,10 +182,15 @@ EXPORT_SYMBOL(usb_add_phy);
void usb_remove_phy(struct usb_phy *x)
{
unsigned long flags;
+ struct usb_phy_bind *phy_bind;
spin_lock_irqsave(&phy_lock, flags);
- if (x)
+ if (x) {
+ list_for_each_entry(phy_bind, &phy_bind_list, list)
+ if (phy_bind->phy == x)
+ phy_bind->phy = NULL;
list_del(&x->head);
+ }
spin_unlock_irqrestore(&phy_lock, flags);
}
EXPORT_SYMBOL(usb_remove_phy);
diff --git a/drivers/usb/otg/twl4030-usb.c b/drivers/usb/otg/twl4030-usb.c
index 0a70193..f6bdd75 100644
--- a/drivers/usb/otg/twl4030-usb.c
+++ b/drivers/usb/otg/twl4030-usb.c
@@ -611,6 +611,7 @@ static int twl4030_usb_probe(struct platform_device *pdev)
twl->phy.label = "twl4030";
twl->phy.otg = otg;
twl->phy.set_suspend = twl4030_set_suspend;
+ twl->phy.type = USB_PHY_TYPE_USB2;
otg->phy = &twl->phy;
otg->set_host = twl4030_set_host;
@@ -624,7 +625,7 @@ static int twl4030_usb_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "ldo init failed\n");
return err;
}
- usb_add_phy(&twl->phy, USB_PHY_TYPE_USB2);
+ usb_add_phy(&twl->phy);
platform_set_drvdata(pdev, twl);
if (device_create_file(&pdev->dev, &dev_attr_vbus))
diff --git a/drivers/usb/phy/mv_u3d_phy.c b/drivers/usb/phy/mv_u3d_phy.c
index eaddbe3..31a19a3 100644
--- a/drivers/usb/phy/mv_u3d_phy.c
+++ b/drivers/usb/phy/mv_u3d_phy.c
@@ -298,10 +298,11 @@ static int mv_u3d_phy_probe(struct platform_device *pdev)
mv_u3d_phy->base = phy_base;
mv_u3d_phy->phy.dev = mv_u3d_phy->dev;
mv_u3d_phy->phy.label = "mv-u3d-phy";
+ mv_u3d_phy->phy.type = USB_PHY_TYPE_USB3;
mv_u3d_phy->phy.init = mv_u3d_phy_init;
mv_u3d_phy->phy.shutdown = mv_u3d_phy_shutdown;
- ret = usb_add_phy(&mv_u3d_phy->phy, USB_PHY_TYPE_USB3);
+ ret = usb_add_phy(&mv_u3d_phy->phy);
if (ret)
goto err;
diff --git a/drivers/usb/phy/omap-usb2.c b/drivers/usb/phy/omap-usb2.c
index 2152ce4..0e7636f 100644
--- a/drivers/usb/phy/omap-usb2.c
+++ b/drivers/usb/phy/omap-usb2.c
@@ -29,6 +29,7 @@
#include <linux/delay.h>
#include <linux/usb/omap_control_usb.h>
+static struct omap_usb *phy;
/**
* omap_usb2_set_comparator - links the comparator present in the sytem with
* this phy
@@ -41,13 +42,9 @@
*/
int omap_usb2_set_comparator(struct phy_companion *comparator)
{
- struct omap_usb *phy;
- struct usb_phy *x = usb_get_phy(USB_PHY_TYPE_USB2);
-
- if (IS_ERR(x))
+ if (!phy)
return -ENODEV;
- phy = phy_to_omapusb(x);
phy->comparator = comparator;
return 0;
}
@@ -121,7 +118,6 @@ static int omap_usb2_suspend(struct usb_phy *x, int suspend)
static int omap_usb2_probe(struct platform_device *pdev)
{
- struct omap_usb *phy;
struct usb_otg *otg;
struct resource *res;
@@ -141,6 +137,7 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy->phy.dev = phy->dev;
phy->phy.label = "omap-usb2";
+ phy->phy.type = USB_PHY_TYPE_USB2;
phy->phy.set_suspend = omap_usb2_suspend;
phy->phy.otg = otg;
@@ -168,7 +165,7 @@ static int omap_usb2_probe(struct platform_device *pdev)
}
clk_prepare(phy->wkupclk);
- usb_add_phy(&phy->phy, USB_PHY_TYPE_USB2);
+ usb_add_phy(&phy->phy);
platform_set_drvdata(pdev, phy);
diff --git a/drivers/usb/phy/rcar-phy.c b/drivers/usb/phy/rcar-phy.c
index a35681b..bd00fd9 100644
--- a/drivers/usb/phy/rcar-phy.c
+++ b/drivers/usb/phy/rcar-phy.c
@@ -181,11 +181,12 @@ static int rcar_usb_phy_probe(struct platform_device *pdev)
priv->counter = 0;
priv->phy.dev = dev;
priv->phy.label = dev_name(dev);
+ priv->phy.type = USB_PHY_TYPE_USB2;
priv->phy.init = rcar_usb_phy_init;
priv->phy.shutdown = rcar_usb_phy_shutdown;
spin_lock_init(&priv->lock);
- ret = usb_add_phy(&priv->phy, USB_PHY_TYPE_USB2);
+ ret = usb_add_phy(&priv->phy);
if (ret < 0) {
dev_err(dev, "usb phy addition error\n");
return ret;
diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h
index fbeab1a..d133c8b 100644
--- a/include/linux/usb/phy.h
+++ b/include/linux/usb/phy.h
@@ -123,7 +123,7 @@ struct usb_phy_bind {
};
/* for board-specific init logic */
-extern int usb_add_phy(struct usb_phy *, enum usb_phy_type type);
+extern int usb_add_phy(struct usb_phy *);
extern void usb_remove_phy(struct usb_phy *);
/* helpers for direct access thru low-level io interface */
@@ -161,21 +161,19 @@ usb_phy_shutdown(struct usb_phy *x)
/* for usb host and peripheral controller drivers */
#ifdef CONFIG_USB_OTG_UTILS
-extern struct usb_phy *usb_get_phy(enum usb_phy_type type);
-extern struct usb_phy *devm_usb_get_phy(struct device *dev,
- enum usb_phy_type type);
+extern struct usb_phy *usb_get_phy(struct device *dev, u8 index);
+extern struct usb_phy *devm_usb_get_phy(struct device *dev, u8 index);
extern void usb_put_phy(struct usb_phy *);
extern void devm_usb_put_phy(struct device *dev, struct usb_phy *x);
extern struct usb_phy_bind *usb_bind_phy(const char *dev_name, u8 index,
const char *phy_dev_name);
#else
-static inline struct usb_phy *usb_get_phy(enum usb_phy_type type)
+static inline struct usb_phy *usb_get_phy(struct device *dev, u8 index)
{
return NULL;
}
-static inline struct usb_phy *devm_usb_get_phy(struct device *dev,
- enum usb_phy_type type)
+static inline struct usb_phy *devm_usb_get_phy(struct device *dev, u8 index)
{
return NULL;
}
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH 2/6] ARM: OMAP: USB: Add phy binding information
From: Kishon Vijay Abraham I @ 2013-01-16 15:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358348462-27693-1-git-send-email-kishon@ti.com>
This is in preparation for the changes in PHY library to support adding
and getting multiple PHYs of the same type. In the new design, the
binding information between the PHY and the USB controller should be
specified in the platform specific initialization code. So it's been
done for OMAP platforms here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
This kind-of binding should be done in all the platforms (I've done only
for OMAP platform).
arch/arm/mach-omap2/usb-musb.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 9d27e3f..bbe2fa5 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -24,6 +24,7 @@
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/usb/musb.h>
+#include <linux/usb/phy.h>
#include "omap_device.h"
#include "soc.h"
@@ -85,8 +86,12 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
musb_plat.mode = board_data->mode;
musb_plat.extvbus = board_data->extvbus;
- if (cpu_is_omap44xx())
+ if (cpu_is_omap44xx()) {
musb_plat.has_mailbox = true;
+ usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto");
+ } else if (cpu_is_omap34xx()) {
+ usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
+ }
if (soc_is_am35xx()) {
oh_name = "am35x_otg_hs";
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH 1/6] usb: otg: Add an API to bind the USB controller and PHY
From: Kishon Vijay Abraham I @ 2013-01-16 15:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358348462-27693-1-git-send-email-kishon@ti.com>
New platforms are added which has multiple PHY's (of same type) and
which has multiple USB controllers. The binding information has to be
present in the PHY library (otg.c) in order for it to return the
appropriate PHY whenever the USB controller request for the PHY. So
added a new API to pass the binding information. This API should be
called by platform specific initialization code.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/usb/otg/otg.c | 37 +++++++++++++++++++++++++++++++++++++
include/linux/usb/phy.h | 22 ++++++++++++++++++++++
2 files changed, 59 insertions(+)
diff --git a/drivers/usb/otg/otg.c b/drivers/usb/otg/otg.c
index a30c041..492ba2f 100644
--- a/drivers/usb/otg/otg.c
+++ b/drivers/usb/otg/otg.c
@@ -18,6 +18,7 @@
#include <linux/usb/otg.h>
static LIST_HEAD(phy_list);
+static LIST_HEAD(phy_bind_list);
static DEFINE_SPINLOCK(phy_lock);
static struct usb_phy *__usb_find_phy(struct list_head *list,
@@ -201,6 +202,42 @@ void usb_remove_phy(struct usb_phy *x)
}
EXPORT_SYMBOL(usb_remove_phy);
+/**
+ * usb_bind_phy - bind the phy and the controller that uses the phy
+ * @dev_name: the device name of the device that will bind to the phy
+ * @index: index to specify the port number
+ * @phy_dev_name: the device name of the phy
+ *
+ * Fills the phy_bind structure with the dev_name and phy_dev_name. This will
+ * be used when the phy driver registers the phy and when the controller
+ * requests this phy.
+ *
+ * To be used by platform specific initialization code.
+ */
+struct usb_phy_bind __init *usb_bind_phy(const char *dev_name, u8 index,
+ const char *phy_dev_name)
+{
+ struct usb_phy_bind *phy_bind;
+ unsigned long flags;
+
+ phy_bind = kzalloc(sizeof(*phy_bind), GFP_KERNEL);
+ if (!phy_bind) {
+ pr_err("phy_bind(): No memory for phy_bind");
+ return ERR_PTR(-ENOMEM);
+ }
+
+ phy_bind->dev_name = dev_name;
+ phy_bind->phy_dev_name = phy_dev_name;
+ phy_bind->index = index;
+
+ spin_lock_irqsave(&phy_lock, flags);
+ list_add_tail(&phy_bind->list, &phy_bind_list);
+ spin_unlock_irqrestore(&phy_lock, flags);
+
+ return phy_bind;
+}
+EXPORT_SYMBOL_GPL(usb_bind_phy);
+
const char *otg_state_string(enum usb_otg_state state)
{
switch (state) {
diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h
index a29ae1e..fbeab1a 100644
--- a/include/linux/usb/phy.h
+++ b/include/linux/usb/phy.h
@@ -106,6 +106,21 @@ struct usb_phy {
enum usb_device_speed speed);
};
+/**
+ * struct usb_phy_bind - represent the binding for the phy
+ * @dev_name: the device name of the device that will bind to the phy
+ * @phy_dev_name: the device name of the phy
+ * @index: used if a single controller uses multiple phys
+ * @phy: reference to the phy
+ * @list: to maintain a linked list of the binding information
+ */
+struct usb_phy_bind {
+ const char *dev_name;
+ const char *phy_dev_name;
+ u8 index;
+ struct usb_phy *phy;
+ struct list_head list;
+};
/* for board-specific init logic */
extern int usb_add_phy(struct usb_phy *, enum usb_phy_type type);
@@ -151,6 +166,8 @@ extern struct usb_phy *devm_usb_get_phy(struct device *dev,
enum usb_phy_type type);
extern void usb_put_phy(struct usb_phy *);
extern void devm_usb_put_phy(struct device *dev, struct usb_phy *x);
+extern struct usb_phy_bind *usb_bind_phy(const char *dev_name, u8 index,
+ const char *phy_dev_name);
#else
static inline struct usb_phy *usb_get_phy(enum usb_phy_type type)
{
@@ -171,6 +188,11 @@ static inline void devm_usb_put_phy(struct device *dev, struct usb_phy *x)
{
}
+static inline struct usb_phy_bind *usb_bind_phy(const char *dev_name, u8 index,
+ const char *phy_dev_name)
+{
+ return NULL;
+}
#endif
static inline int
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH 0/6] USB: Add multiple PHYs of same type
From: Kishon Vijay Abraham I @ 2013-01-16 15:00 UTC (permalink / raw)
To: linux-arm-kernel
New platforms are being added which has multiple PHY's (of same type) and
which has multiple USB controllers. The binding information has to be
present in the PHY library (otg.c) in order for it to return the
appropriate PHY whenever the USB controller request for the PHY. So
added a new API to pass the binding information. This API should be
called by platform specific initialization code.
So the binding should be done something like
usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto"); specifying the USB
controller device name, index, and the PHY device name.
I have done this binding for OMAP platforms, but it should be done for
all the platforms.
After this design, the phy can be got by passing the USB controller device
pointer and the index.
Developed this patch series on
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git xceiv
after applying "usb: musb: add driver for control module" patch series.
Did basic enumeration testing in omap4 panda, omap4 sdp and omap3 beagle.
Kishon Vijay Abraham I (6):
usb: otg: Add an API to bind the USB controller and PHY
ARM: OMAP: USB: Add phy binding information
usb: otg: utils: change the phy lib to support multiple PHYs of same
type
ARM: dts: OMAP: Add phandle to bind PHY with USB controller
usb: otg: add device tree support to otg library
USB: MUSB: OMAP: get PHY by phandle for dt boot
Documentation/devicetree/bindings/usb/omap-usb.txt | 2 +
arch/arm/boot/dts/omap3.dtsi | 1 +
arch/arm/boot/dts/omap4.dtsi | 3 +-
arch/arm/boot/dts/twl4030.dtsi | 2 +-
arch/arm/mach-omap2/usb-musb.c | 7 +-
arch/arm/mach-shmobile/board-marzen.c | 2 +-
drivers/power/ab8500_charger.c | 2 +-
drivers/power/isp1704_charger.c | 2 +-
drivers/power/pda_power.c | 2 +-
drivers/power/twl4030_charger.c | 2 +-
drivers/usb/chipidea/udc.c | 2 +-
drivers/usb/dwc3/core.c | 4 +-
drivers/usb/gadget/fsl_udc_core.c | 2 +-
drivers/usb/gadget/mv_udc_core.c | 2 +-
drivers/usb/gadget/omap_udc.c | 2 +-
drivers/usb/gadget/pxa25x_udc.c | 2 +-
drivers/usb/gadget/pxa27x_udc.c | 2 +-
drivers/usb/gadget/s3c-hsudc.c | 2 +-
drivers/usb/host/ehci-fsl.c | 2 +-
drivers/usb/host/ehci-msm.c | 2 +-
drivers/usb/host/ehci-mv.c | 2 +-
drivers/usb/host/ehci-tegra.c | 2 +-
drivers/usb/host/ohci-omap.c | 2 +-
drivers/usb/musb/am35x.c | 2 +-
drivers/usb/musb/blackfin.c | 2 +-
drivers/usb/musb/da8xx.c | 2 +-
drivers/usb/musb/davinci.c | 2 +-
drivers/usb/musb/musb_dsps.c | 2 +-
drivers/usb/musb/omap2430.c | 7 +-
drivers/usb/musb/tusb6010.c | 2 +-
drivers/usb/musb/ux500.c | 2 +-
drivers/usb/otg/ab8500-usb.c | 3 +-
drivers/usb/otg/fsl_otg.c | 5 +-
drivers/usb/otg/gpio_vbus.c | 3 +-
drivers/usb/otg/isp1301_omap.c | 3 +-
drivers/usb/otg/msm_otg.c | 3 +-
drivers/usb/otg/mv_otg.c | 3 +-
drivers/usb/otg/nop-usb-xceiv.c | 3 +-
drivers/usb/otg/otg.c | 175 ++++++++++++++++----
drivers/usb/otg/twl4030-usb.c | 3 +-
drivers/usb/phy/mv_u3d_phy.c | 3 +-
drivers/usb/phy/omap-usb2.c | 11 +-
drivers/usb/phy/rcar-phy.c | 3 +-
include/linux/usb/phy.h | 42 ++++-
44 files changed, 245 insertions(+), 89 deletions(-)
--
1.7.9.5
^ permalink raw reply
* [PATCH V2 5/5] DTS: Add device tree entry for onewire master on i.MX53
From: Martin Fuzzey @ 2013-01-16 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130116145749.24249.678.stgit@localhost>
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
---
arch/arm/boot/dts/imx53.dtsi | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index edc3f1e..00c957c 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -387,6 +387,14 @@
};
};
+ owire {
+ pinctrl_owire_1: owiregrp-1 {
+ fsl,pins = <
+ 1166 0x80000000 /* MX53_PAD_GPIO_18__OWIRE_LINE */
+ >;
+ };
+ };
+
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
@@ -570,6 +578,13 @@
status = "disabled";
};
+ owire: owire@63fa4000 {
+ compatible = "fsl,imx53-owire", "fsl,imx21-owire";
+ reg = <0x63fa4000 0x4000>;
+ clocks = <&clks 159>;
+ status = "disabled";
+ };
+
ecspi2: ecspi at 63fac000 {
#address-cells = <1>;
#size-cells = <0>;
^ permalink raw reply related
* [PATCH V2 4/5] W1: Add pinctrl support to MXC onewire master.
From: Martin Fuzzey @ 2013-01-16 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130116145749.24249.678.stgit@localhost>
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
---
drivers/w1/masters/mxc_w1.c | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c
index 317b2bc..48afc2c 100644
--- a/drivers/w1/masters/mxc_w1.c
+++ b/drivers/w1/masters/mxc_w1.c
@@ -24,6 +24,7 @@
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/pinctrl/consumer.h>
#include "../w1.h"
#include "../w1_int.h"
@@ -107,6 +108,7 @@ static int mxc_w1_probe(struct platform_device *pdev)
{
struct mxc_w1_device *mdev;
struct resource *res;
+ struct pinctrl *pinctrl;
int err = 0;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -117,6 +119,13 @@ static int mxc_w1_probe(struct platform_device *pdev)
if (!mdev)
return -ENOMEM;
+ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+ if (IS_ERR(pinctrl)) {
+ err = PTR_ERR(pinctrl);
+ dev_err(&pdev->dev, "failed to get default pinctrl: %d\n", err);
+ goto failed_pin;
+ }
+
mdev->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(mdev->clk)) {
err = PTR_ERR(mdev->clk);
@@ -152,6 +161,7 @@ failed_add:
failed_req:
failed_clk:
+failed_pin:
kfree(mdev);
return err;
}
^ permalink raw reply related
* [PATCH V2 3/5] W1: Convert MXC onewire master to devm_ functions.
From: Martin Fuzzey @ 2013-01-16 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130116145749.24249.678.stgit@localhost>
While doing this fix missing clk_disable_unprepare in error path.
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
---
drivers/w1/masters/mxc_w1.c | 26 ++++++--------------------
1 files changed, 6 insertions(+), 20 deletions(-)
diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c
index 949e566..317b2bc 100644
--- a/drivers/w1/masters/mxc_w1.c
+++ b/drivers/w1/masters/mxc_w1.c
@@ -117,7 +117,7 @@ static int mxc_w1_probe(struct platform_device *pdev)
if (!mdev)
return -ENOMEM;
- mdev->clk = clk_get(&pdev->dev, NULL);
+ mdev->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(mdev->clk)) {
err = PTR_ERR(mdev->clk);
goto failed_clk;
@@ -125,17 +125,11 @@ static int mxc_w1_probe(struct platform_device *pdev)
mdev->clkdiv = (clk_get_rate(mdev->clk) / 1000000) - 1;
- res = request_mem_region(res->start, resource_size(res),
- "mxc_w1");
- if (!res) {
- err = -EBUSY;
- goto failed_req;
- }
-
- mdev->regs = ioremap(res->start, resource_size(res));
+ mdev->regs = devm_request_and_ioremap(&pdev->dev, res);
if (!mdev->regs) {
dev_err(&pdev->dev, "Cannot map mxc_w1 registers\n");
- goto failed_ioremap;
+ err = -ENXIO;
+ goto failed_req;
}
clk_prepare_enable(mdev->clk);
@@ -154,11 +148,9 @@ static int mxc_w1_probe(struct platform_device *pdev)
return 0;
failed_add:
- iounmap(mdev->regs);
-failed_ioremap:
- release_mem_region(res->start, resource_size(res));
+ clk_disable_unprepare(mdev->clk);
+
failed_req:
- clk_put(mdev->clk);
failed_clk:
kfree(mdev);
return err;
@@ -170,16 +162,10 @@ failed_clk:
static int mxc_w1_remove(struct platform_device *pdev)
{
struct mxc_w1_device *mdev = platform_get_drvdata(pdev);
- struct resource *res;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
w1_remove_master_device(&mdev->bus_master);
- iounmap(mdev->regs);
- release_mem_region(res->start, resource_size(res));
clk_disable_unprepare(mdev->clk);
- clk_put(mdev->clk);
platform_set_drvdata(pdev, NULL);
^ permalink raw reply related
* [PATCH V2 2/5] ARM: i.MX53: Add clocks for i.mx53 onewire master.
From: Martin Fuzzey @ 2013-01-16 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130116145749.24249.678.stgit@localhost>
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
---
.../devicetree/bindings/clock/imx5-clock.txt | 1 +
arch/arm/mach-imx/clk-imx51-imx53.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index 04ad478..2a0c904 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -171,6 +171,7 @@ clocks and IDs.
can_sel 156
can1_serial_gate 157
can1_ipg_gate 158
+ owire_gate 159
Examples (for mx53):
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 579023f..7ff293b 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -83,6 +83,7 @@ enum imx5_clks {
ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
can_sel, can1_serial_gate, can1_ipg_gate,
+ owire_gate,
clk_max
};
@@ -233,12 +234,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
+ clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX5 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
-
+
clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
^ permalink raw reply related
* [PATCH V2 1/5] W1: Add device tree support to MXC onewire master.
From: Martin Fuzzey @ 2013-01-16 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130116145749.24249.678.stgit@localhost>
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
---
drivers/w1/masters/mxc_w1.c | 9 ++++++++-
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c
index 708a25f..949e566 100644
--- a/drivers/w1/masters/mxc_w1.c
+++ b/drivers/w1/masters/mxc_w1.c
@@ -186,9 +186,16 @@ static int mxc_w1_remove(struct platform_device *pdev)
return 0;
}
+static struct of_device_id mxc_w1_dt_ids[] = {
+ { .compatible = "fsl,imx21-owire" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids);
+
static struct platform_driver mxc_w1_driver = {
.driver = {
- .name = "mxc_w1",
+ .name = "mxc_w1",
+ .of_match_table = mxc_w1_dt_ids,
},
.probe = mxc_w1_probe,
.remove = mxc_w1_remove,
^ permalink raw reply related
* [PATCH V2 0/5] W1: Support onewire master on i.MX53
From: Martin Fuzzey @ 2013-01-16 14:57 UTC (permalink / raw)
To: linux-arm-kernel
W1: Support onewire master on i.MX53
* Add device tree and pinctrl support to the MXC master driver
* Convert to use devm_
* Add i.MX53 clocks
* Add i.MX53 device tree entries
Changes since V1
* Applied comments from Sascha Hauer:
* Move patch converting driver to devm_ before the one adding devm_ based pinctrl
* Fix existing unbalanced clk_prepare_enable/clk_disable_unprepare
in probe error path
* Place DT patch last since it includes pinctrls for driver.
^ permalink raw reply
* [PATCH v6 04/22] mfd: omap-usb-tll: Clean up clock handling
From: Russell King - ARM Linux @ 2013-01-16 14:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358347433-329-5-git-send-email-rogerq@ti.com>
On Wed, Jan 16, 2013 at 04:43:35PM +0200, Roger Quadros wrote:
> + spin_lock_irqsave(&tll->lock, flags);
> +
> + for (i = 0; i < tll->nch; i++) {
> + char clkname[] = "usb_tll_hs_usb_chx_clk";
> + struct clk *fck;
> +
> + snprintf(clkname, sizeof(clkname),
> + "usb_tll_hs_usb_ch%d_clk", i);
> + fck = clk_get(dev, clkname);
NAK. Why are you doing this under a spinlock?
clk_get() takes a mutex. You must not be in an atomic region (iow, you
must not be holding a spinlock, and you must not have IRQs disabled)
when you call clk_get().
^ permalink raw reply
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