* linux-next: manual merge of the samsung tree with the arm-soc tree
From: Kukjin Kim @ 2013-01-17 5:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130117145324.3f1f27fb5902b5a03135bf06@canb.auug.org.au>
Kukjin Kim wrote:
>
> Stephen Rothwell wrote:
> >
> > Hi Kukjin,
> >
> Hi,
>
> > On Fri, 11 Jan 2013 15:32:06 +1100 Stephen Rothwell
> <sfr@canb.auug.org.au>
> > wrote:
> > >
> > > Today's linux-next merge of the samsung tree got conflicts in
> > > many files with the arm-soc tree.
> > >
> > > I just dropped the samsung tree for today. Please have a look and try
to
> > > fix this mess up, thanks.
> >
> > Ping?
>
> Oops, I missed above e-mail. Anyway, really?
>
> Let me look at it soon and I will fix.
>
> Thanks for your information.
>
Hmm, updating timer patches in Samsung tree cause the merge conflicts with
arm-soc, so for now I dropped them in my tree just now.
And note that regarding topic branch which are including it will be
re-worked soon :-)
Now to merge Samsung tree for linux-next should be fine.
Thanks again.
- Kukjin
^ permalink raw reply
* [PATCH 3/3] ARM: omap2: use get_auxcr for aux ctrl register read
From: Nicolas Pitre @ 2013-01-17 4:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358391205-23943-3-git-send-email-robherring2@gmail.com>
On Wed, 16 Jan 2013, Rob Herring wrote:
> From: Rob Herring <rob.herring@calxeda.com>
>
> Use get_auxcr instead of inline assembly to read the CP15 aux ctrl
> register.
>
> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
> Cc: Kevin Hilman <khilman@ti.com>
> Cc: Tony Lindgren <tony@atomide.com>
Looks trivial enough.
Acked-by: Nicolas Pitre <nico@linaro.org>
> ---
> arch/arm/mach-omap2/pm34xx.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 7be3622..bef8ef6 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -33,6 +33,7 @@
>
> #include <trace/events/power.h>
>
> +#include <asm/cp15.h>
> #include <asm/fncpy.h>
> #include <asm/suspend.h>
> #include <asm/system_misc.h>
> @@ -216,9 +217,8 @@ static void omap34xx_save_context(u32 *save)
> u32 val;
>
> /* Read Auxiliary Control Register */
> - asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
> *save++ = 1;
> - *save++ = val;
> + *save++ = get_auxcr();
>
> /* Read L2 AUX ctrl register */
> asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
> --
> 1.7.10.4
>
^ permalink raw reply
* [PATCH 2/3] ARM: convert platform hotplug inline assembly to C
From: Nicolas Pitre @ 2013-01-17 4:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358391205-23943-2-git-send-email-robherring2@gmail.com>
On Wed, 16 Jan 2013, Rob Herring wrote:
> From: Rob Herring <rob.herring@calxeda.com>
>
> With the addition of set_auxcr/get_auxcr, all the hotplug inline assembly
> code for exynos, imx, realview, spear13xx and vexpress can be converted to
> C code.
That might not be all safe. Please see
http://article.gmane.org/gmane.linux.ports.arm.kernel/209584
>
> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Shiraz Hashim <shiraz.hashim@st.com>
> ---
> arch/arm/mach-exynos/hotplug.c | 57 ++++++-------------------------------
> arch/arm/mach-imx/hotplug.c | 19 ++++---------
> arch/arm/mach-realview/hotplug.c | 32 +++++----------------
> arch/arm/mach-spear13xx/hotplug.c | 32 +++++----------------
> arch/arm/mach-vexpress/hotplug.c | 33 +++++----------------
> 5 files changed, 35 insertions(+), 138 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
> index c3f825b..5548fa3 100644
> --- a/arch/arm/mach-exynos/hotplug.c
> +++ b/arch/arm/mach-exynos/hotplug.c
> @@ -26,69 +26,30 @@
>
> static inline void cpu_enter_lowpower_a9(void)
> {
> - unsigned int v;
> -
> flush_cache_all();
> - asm volatile(
> - " mcr p15, 0, %1, c7, c5, 0\n"
> - " mcr p15, 0, %1, c7, c10, 4\n"
> + __flush_icache_all();
> + dsb();
> +
> /*
> * Turn off coherency
> */
> - " mrc p15, 0, %0, c1, c0, 1\n"
> - " bic %0, %0, %3\n"
> - " mcr p15, 0, %0, c1, c0, 1\n"
> - " mrc p15, 0, %0, c1, c0, 0\n"
> - " bic %0, %0, %2\n"
> - " mcr p15, 0, %0, c1, c0, 0\n"
> - : "=&r" (v)
> - : "r" (0), "Ir" (CR_C), "Ir" (0x40)
> - : "cc");
> + set_auxcr(get_auxcr() & ~0x40);
> + set_cr(get_cr() & ~CR_C);
> }
>
> static inline void cpu_enter_lowpower_a15(void)
> {
> - unsigned int v;
> -
> - asm volatile(
> - " mrc p15, 0, %0, c1, c0, 0\n"
> - " bic %0, %0, %1\n"
> - " mcr p15, 0, %0, c1, c0, 0\n"
> - : "=&r" (v)
> - : "Ir" (CR_C)
> - : "cc");
> -
> + set_cr(get_cr() & ~CR_C);
> flush_cache_louis();
> + set_auxcr(get_auxcr() & ~0x40);
>
> - asm volatile(
> - /*
> - * Turn off coherency
> - */
> - " mrc p15, 0, %0, c1, c0, 1\n"
> - " bic %0, %0, %1\n"
> - " mcr p15, 0, %0, c1, c0, 1\n"
> - : "=&r" (v)
> - : "Ir" (0x40)
> - : "cc");
> -
> - isb();
> dsb();
> }
>
> static inline void cpu_leave_lowpower(void)
> {
> - unsigned int v;
> -
> - asm volatile(
> - "mrc p15, 0, %0, c1, c0, 0\n"
> - " orr %0, %0, %1\n"
> - " mcr p15, 0, %0, c1, c0, 0\n"
> - " mrc p15, 0, %0, c1, c0, 1\n"
> - " orr %0, %0, %2\n"
> - " mcr p15, 0, %0, c1, c0, 1\n"
> - : "=&r" (v)
> - : "Ir" (CR_C), "Ir" (0x40)
> - : "cc");
> + set_cr(get_cr() | CR_C);
> + set_auxcr(get_auxcr() | 0x40);
> }
>
> static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
> diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
> index 3dec962..1470c75 100644
> --- a/arch/arm/mach-imx/hotplug.c
> +++ b/arch/arm/mach-imx/hotplug.c
> @@ -18,24 +18,15 @@
>
> static inline void cpu_enter_lowpower(void)
> {
> - unsigned int v;
> -
> flush_cache_all();
> - asm volatile(
> - "mcr p15, 0, %1, c7, c5, 0\n"
> - " mcr p15, 0, %1, c7, c10, 4\n"
> + __flush_icache_all();
> + dsb();
> +
> /*
> * Turn off coherency
> */
> - " mrc p15, 0, %0, c1, c0, 1\n"
> - " bic %0, %0, %3\n"
> - " mcr p15, 0, %0, c1, c0, 1\n"
> - " mrc p15, 0, %0, c1, c0, 0\n"
> - " bic %0, %0, %2\n"
> - " mcr p15, 0, %0, c1, c0, 0\n"
> - : "=&r" (v)
> - : "r" (0), "Ir" (CR_C), "Ir" (0x40)
> - : "cc");
> + set_auxcr(get_auxcr() & ~0x40);
> + set_cr(get_cr() & ~CR_C);
> }
>
> /*
> diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
> index 53818e5..c17c8c0 100644
> --- a/arch/arm/mach-realview/hotplug.c
> +++ b/arch/arm/mach-realview/hotplug.c
> @@ -18,39 +18,21 @@
>
> static inline void cpu_enter_lowpower(void)
> {
> - unsigned int v;
> -
> flush_cache_all();
> - asm volatile(
> - " mcr p15, 0, %1, c7, c5, 0\n"
> - " mcr p15, 0, %1, c7, c10, 4\n"
> + __flush_icache_all();
> + dsb();
> +
> /*
> * Turn off coherency
> */
> - " mrc p15, 0, %0, c1, c0, 1\n"
> - " bic %0, %0, #0x20\n"
> - " mcr p15, 0, %0, c1, c0, 1\n"
> - " mrc p15, 0, %0, c1, c0, 0\n"
> - " bic %0, %0, %2\n"
> - " mcr p15, 0, %0, c1, c0, 0\n"
> - : "=&r" (v)
> - : "r" (0), "Ir" (CR_C)
> - : "cc");
> + set_auxcr(get_auxcr() & ~0x40);
> + set_cr(get_cr() & ~CR_C);
> }
>
> static inline void cpu_leave_lowpower(void)
> {
> - unsigned int v;
> -
> - asm volatile( "mrc p15, 0, %0, c1, c0, 0\n"
> - " orr %0, %0, %1\n"
> - " mcr p15, 0, %0, c1, c0, 0\n"
> - " mrc p15, 0, %0, c1, c0, 1\n"
> - " orr %0, %0, #0x20\n"
> - " mcr p15, 0, %0, c1, c0, 1\n"
> - : "=&r" (v)
> - : "Ir" (CR_C)
> - : "cc");
> + set_cr(get_cr() | CR_C);
> + set_auxcr(get_auxcr() | 0x40);
> }
>
> static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
> diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c
> index a7d2dd1..a38a087 100644
> --- a/arch/arm/mach-spear13xx/hotplug.c
> +++ b/arch/arm/mach-spear13xx/hotplug.c
> @@ -19,39 +19,21 @@
>
> static inline void cpu_enter_lowpower(void)
> {
> - unsigned int v;
> -
> flush_cache_all();
> - asm volatile(
> - " mcr p15, 0, %1, c7, c5, 0\n"
> - " dsb\n"
> + __flush_icache_all();
> + dsb();
> +
> /*
> * Turn off coherency
> */
> - " mrc p15, 0, %0, c1, c0, 1\n"
> - " bic %0, %0, #0x20\n"
> - " mcr p15, 0, %0, c1, c0, 1\n"
> - " mrc p15, 0, %0, c1, c0, 0\n"
> - " bic %0, %0, %2\n"
> - " mcr p15, 0, %0, c1, c0, 0\n"
> - : "=&r" (v)
> - : "r" (0), "Ir" (CR_C)
> - : "cc", "memory");
> + set_auxcr(get_auxcr() & ~0x40);
> + set_cr(get_cr() & ~CR_C);
> }
>
> static inline void cpu_leave_lowpower(void)
> {
> - unsigned int v;
> -
> - asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
> - " orr %0, %0, %1\n"
> - " mcr p15, 0, %0, c1, c0, 0\n"
> - " mrc p15, 0, %0, c1, c0, 1\n"
> - " orr %0, %0, #0x20\n"
> - " mcr p15, 0, %0, c1, c0, 1\n"
> - : "=&r" (v)
> - : "Ir" (CR_C)
> - : "cc");
> + set_cr(get_cr() | CR_C);
> + set_auxcr(get_auxcr() | 0x40);
> }
>
> static inline void spear13xx_do_lowpower(unsigned int cpu, int *spurious)
> diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
> index a141b98..74a9eb5 100644
> --- a/arch/arm/mach-vexpress/hotplug.c
> +++ b/arch/arm/mach-vexpress/hotplug.c
> @@ -18,40 +18,21 @@
>
> static inline void cpu_enter_lowpower(void)
> {
> - unsigned int v;
> -
> flush_cache_all();
> - asm volatile(
> - "mcr p15, 0, %1, c7, c5, 0\n"
> - " mcr p15, 0, %1, c7, c10, 4\n"
> + __flush_icache_all();
> + dsb();
> +
> /*
> * Turn off coherency
> */
> - " mrc p15, 0, %0, c1, c0, 1\n"
> - " bic %0, %0, %3\n"
> - " mcr p15, 0, %0, c1, c0, 1\n"
> - " mrc p15, 0, %0, c1, c0, 0\n"
> - " bic %0, %0, %2\n"
> - " mcr p15, 0, %0, c1, c0, 0\n"
> - : "=&r" (v)
> - : "r" (0), "Ir" (CR_C), "Ir" (0x40)
> - : "cc");
> + set_auxcr(get_auxcr() & ~0x40);
> + set_cr(get_cr() & ~CR_C);
> }
>
> static inline void cpu_leave_lowpower(void)
> {
> - unsigned int v;
> -
> - asm volatile(
> - "mrc p15, 0, %0, c1, c0, 0\n"
> - " orr %0, %0, %1\n"
> - " mcr p15, 0, %0, c1, c0, 0\n"
> - " mrc p15, 0, %0, c1, c0, 1\n"
> - " orr %0, %0, %2\n"
> - " mcr p15, 0, %0, c1, c0, 1\n"
> - : "=&r" (v)
> - : "Ir" (CR_C), "Ir" (0x40)
> - : "cc");
> + set_cr(get_cr() | CR_C);
> + set_auxcr(get_auxcr() | 0x40);
> }
>
> static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
> --
> 1.7.10.4
>
^ permalink raw reply
* [PATCH 1/2] ARM: tegra: config: enable SERIAL_TEGRA
From: Laxman Dewangan @ 2013-01-17 4:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F6EA0A.4080904@wwwdotorg.org>
On Wednesday 16 January 2013 11:27 PM, Stephen Warren wrote:
> On 01/16/2013 06:06 AM, Laxman Dewangan wrote:
>> Enable high speed serial driver for tegra platform.
> Thanks, I've applied patch 1 to Tegra's for-3.9/defconfig branch and
> patch 2 to Tegra's for-3.9/dt branch.
>
> Just as an FYI, the dt branch is merged into my for-next branch, and
> sent upstream, before the defconfig branch, so your patch order was
> reversed relative to that, but it's not an issue here.
Thanks for applying it. There is no issue on the reversing the sequence.
> Question: How do I test this; do I just fire up bluez(?) and point it at
> the UARTC serial port, or is there more to it?
I tested this in may pieces, not with the bluez.
I tested this in downstream with linux-next dma, this new serial driver,
some hacks in the board files with bluetooth.
Then I tested this again on linux-next with some hacks in board-dt filew
with invoking the driver from cardhu dts file. In this I tested driver
registration, basic write is wokring or not with some register
dump/interrupt, Not checked data integrity as not connected the serial
sniffer. The idea is that nothing should be crash in linux-next. The
basic driver code is already tested with bluetooth.
^ permalink raw reply
* [PATCH 1/3] ARM: introduce common set_auxcr/get_auxcr functions
From: Nicolas Pitre @ 2013-01-17 4:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358391205-23943-1-git-send-email-robherring2@gmail.com>
On Wed, 16 Jan 2013, Rob Herring wrote:
> From: Rob Herring <rob.herring@calxeda.com>
>
> Move the private set_auxcr/get_auxcr functions from
> drivers/cpuidle/cpuidle-calxeda.c so they can be used across platforms.
>
> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
> Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Nicolas Pitre <nico@linaro.org>
> ---
> arch/arm/include/asm/cp15.h | 14 ++++++++++++++
> drivers/cpuidle/cpuidle-calxeda.c | 14 --------------
> 2 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
> index 5ef4d80..ef0094a 100644
> --- a/arch/arm/include/asm/cp15.h
> +++ b/arch/arm/include/asm/cp15.h
> @@ -59,6 +59,20 @@ static inline void set_cr(unsigned int val)
> isb();
> }
>
> +static inline unsigned int get_auxcr(void)
> +{
> + unsigned int val;
> + asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val) : : "cc");
> + return val;
> +}
> +
> +static inline void set_auxcr(unsigned int val)
> +{
> + asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
> + : : "r" (val) : "cc");
> + isb();
> +}
> +
> #ifndef CONFIG_SMP
> extern void adjust_cr(unsigned long mask, unsigned long set);
> #endif
> diff --git a/drivers/cpuidle/cpuidle-calxeda.c b/drivers/cpuidle/cpuidle-calxeda.c
> index e1aab38..ece83d6 100644
> --- a/drivers/cpuidle/cpuidle-calxeda.c
> +++ b/drivers/cpuidle/cpuidle-calxeda.c
> @@ -37,20 +37,6 @@ extern void *scu_base_addr;
>
> static struct cpuidle_device __percpu *calxeda_idle_cpuidle_devices;
>
> -static inline unsigned int get_auxcr(void)
> -{
> - unsigned int val;
> - asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val) : : "cc");
> - return val;
> -}
> -
> -static inline void set_auxcr(unsigned int val)
> -{
> - asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
> - : : "r" (val) : "cc");
> - isb();
> -}
> -
> static noinline void calxeda_idle_restore(void)
> {
> set_cr(get_cr() | CR_C);
> --
> 1.7.10.4
>
^ permalink raw reply
* linux-next: manual merge of the samsung tree with the arm-soc tree
From: Kukjin Kim @ 2013-01-17 4:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130117145324.3f1f27fb5902b5a03135bf06@canb.auug.org.au>
Stephen Rothwell wrote:
>
> Hi Kukjin,
>
Hi,
> On Fri, 11 Jan 2013 15:32:06 +1100 Stephen Rothwell <sfr@canb.auug.org.au>
> wrote:
> >
> > Today's linux-next merge of the samsung tree got conflicts in
> > many files with the arm-soc tree.
> >
> > I just dropped the samsung tree for today. Please have a look and try
to
> > fix this mess up, thanks.
>
> Ping?
Oops, I missed above e-mail. Anyway, really?
Let me look at it soon and I will fix.
Thanks for your information.
- Kukjin
^ permalink raw reply
* linux-next: manual merge of the samsung tree with the arm-soc tree
From: Kukjin Kim @ 2013-01-17 4:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130117145324.3f1f27fb5902b5a03135bf06@canb.auug.org.au>
Stephen Rothwell wrote:
>
> Hi Kukjin,
>
Hi,
> On Fri, 11 Jan 2013 15:32:06 +1100 Stephen Rothwell <sfr@canb.auug.org.au>
> wrote:
> >
> > Today's linux-next merge of the samsung tree got conflicts in
> > many files with the arm-soc tree.
> >
> > I just dropped the samsung tree for today. Please have a look and try
to
> > fix this mess up, thanks.
>
> Ping?
>
Oops, I missed above e-mail. Anyway, really?
Let me look at soon and I will fix.
Thanks for your information.
- Kukjin
^ permalink raw reply
* linux-next: manual merge of the samsung tree with the arm-soc tree
From: Stephen Rothwell @ 2013-01-17 3:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111153206.e075edb9b1e4a38d90f23ab6@canb.auug.org.au>
Hi Kukjin,
On Fri, 11 Jan 2013 15:32:06 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>
> Today's linux-next merge of the samsung tree got conflicts in
> many files with the arm-soc tree.
>
> I just dropped the samsung tree for today. Please have a look and try to
> fix this mess up, thanks.
Ping?
--
Cheers,
Stephen Rothwell sfr at canb.auug.org.au
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^ permalink raw reply
* [PATCH V5 5/5] ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
From: Joseph Lo @ 2013-01-17 3:33 UTC (permalink / raw)
To: linux-arm-kernel
The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one
core to go into this mode before other core. The coupled cpuidle framework
can help to sync the MPCore to coupled state then go into "powered-down"
idle mode together. The driver can just assume the MPCore come into
"powered-down" mode at the same time. No need to take care if the CPU_0
goes into this mode along and only can put it into safe idle mode (WFI).
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI for waiting CPU0 in the same state.
When the CPU0 requests powered-down state, it attempts to put the secondary
CPU into reset to prevent it from waking up. Then power down both CPUs
together and power off the cpu rail.
Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".
Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Colin Cross <ccross@android.com>
---
V5:
* take care the comments that from Colin in the previous version
V4:
* rename the function to "tegra20_wake_cpu1_from_reset"
* make the coupled cpuidle can be disabled if SMP is disabled
V3:
* sqash last two patch in previous version to support coupled cpuidle
directly
V2:
* refine the cpu control function that dedicate for CPU_1
* rename "tegra_cpu_pllp" to "tegra_switch_cpu_to_pllp"
---
arch/arm/mach-tegra/Kconfig | 1 +
arch/arm/mach-tegra/cpuidle-tegra20.c | 125 +++++++++++++++++++++++++++++++---
arch/arm/mach-tegra/sleep-tegra20.S | 53 ++++++++++++++
arch/arm/mach-tegra/sleep.S | 19 ++++++
arch/arm/mach-tegra/sleep.h | 3 +
5 files changed, 192 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 1ec7f80..abc688f 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -4,6 +4,7 @@ comment "NVIDIA Tegra options"
config ARCH_TEGRA_2x_SOC
bool "Enable support for Tegra20 family"
+ select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
select ARCH_REQUIRE_GPIOLIB
select ARM_ERRATA_720789
select ARM_ERRATA_742230 if SMP
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 50f984d..825ced4 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -24,6 +24,7 @@
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/clockchips.h>
+#include <linux/clk/tegra.h>
#include <asm/cpuidle.h>
#include <asm/proc-fns.h>
@@ -32,22 +33,28 @@
#include "pm.h"
#include "sleep.h"
+#include "iomap.h"
+#include "irq.h"
+#include "flowctrl.h"
#ifdef CONFIG_PM_SLEEP
-static int tegra20_idle_lp2(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index);
+static bool abort_flag;
+static atomic_t abort_barrier;
+static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index);
#endif
static struct cpuidle_state tegra_idle_states[] = {
[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
#ifdef CONFIG_PM_SLEEP
[1] = {
- .enter = tegra20_idle_lp2,
+ .enter = tegra20_idle_lp2_coupled,
.exit_latency = 5000,
.target_residency = 10000,
.power_usage = 0,
- .flags = CPUIDLE_FLAG_TIME_VALID,
+ .flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_COUPLED,
.name = "powered-down",
.desc = "CPU power gated",
},
@@ -64,6 +71,88 @@ static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
#ifdef CONFIG_PM_SLEEP
#ifdef CONFIG_SMP
+static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+
+static int tegra20_reset_sleeping_cpu_1(void)
+{
+ int ret = 0;
+
+ tegra_pen_lock();
+
+ if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
+ tegra20_cpu_shutdown(1);
+ else
+ ret = -EINVAL;
+
+ tegra_pen_unlock();
+
+ return ret;
+}
+
+static void tegra20_wake_cpu1_from_reset(void)
+{
+ tegra_pen_lock();
+
+ tegra20_cpu_clear_resettable();
+
+ /* enable cpu clock on cpu */
+ tegra_enable_cpu_clock(1);
+
+ /* take the CPU out of reset */
+ tegra_cpu_out_of_reset(1);
+
+ /* unhalt the cpu */
+ flowctrl_write_cpu_halt(1, 0);
+
+ tegra_pen_unlock();
+}
+
+static int tegra20_reset_cpu_1(void)
+{
+ if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())
+ return 0;
+
+ tegra20_wake_cpu1_from_reset();
+ return -EBUSY;
+}
+#else
+static inline void tegra20_wake_cpu1_from_reset(void)
+{
+}
+
+static inline int tegra20_reset_cpu_1(void)
+{
+ return 0;
+}
+#endif
+
+static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ struct cpuidle_state *state = &drv->states[index];
+ u32 cpu_on_time = state->exit_latency;
+ u32 cpu_off_time = state->target_residency - state->exit_latency;
+
+ while (tegra20_cpu_is_resettable_soon())
+ cpu_relax();
+
+ if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
+ return false;
+
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+
+ tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+
+ if (cpu_online(1))
+ tegra20_wake_cpu1_from_reset();
+
+ return true;
+}
+
+#ifdef CONFIG_SMP
static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
@@ -87,20 +176,31 @@ static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
}
#endif
-static int tegra20_idle_lp2(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
+static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
{
u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
bool entered_lp2 = false;
+ if (tegra_pending_sgi())
+ ACCESS_ONCE(abort_flag) = true;
+
+ cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
+
+ if (abort_flag) {
+ cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
+ abort_flag = false; /* clean flag for next coming */
+ return -EINTR;
+ }
+
local_fiq_disable();
tegra_set_cpu_in_lp2(cpu);
cpu_pm_enter();
if (cpu == 0)
- cpu_do_idle();
+ entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
else
entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
@@ -122,6 +222,10 @@ int __init tegra20_cpuidle_init(void)
struct cpuidle_device *dev;
struct cpuidle_driver *drv = &tegra_idle_driver;
+#ifdef CONFIG_PM_SLEEP
+ tegra_tear_down_cpu = tegra20_tear_down_cpu;
+#endif
+
drv->state_count = ARRAY_SIZE(tegra_idle_states);
memcpy(drv->states, tegra_idle_states,
drv->state_count * sizeof(drv->states[0]));
@@ -135,6 +239,9 @@ int __init tegra20_cpuidle_init(void)
for_each_possible_cpu(cpu) {
dev = &per_cpu(tegra_idle_device, cpu);
dev->cpu = cpu;
+#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
+ dev->coupled_cpus = *cpu_possible_mask;
+#endif
dev->state_count = drv->state_count;
ret = cpuidle_register_device(dev);
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 1074364..9f6bfaf 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -57,6 +57,9 @@ ENDPROC(tegra20_hotplug_shutdown)
ENTRY(tegra20_cpu_shutdown)
cmp r0, #0
moveq pc, lr @ must not be called for CPU 0
+ mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
+ mov r12, #CPU_RESETTABLE
+ str r12, [r1]
cpu_to_halt_reg r1, r0
ldr r3, =TEGRA_FLOW_CTRL_VIRT
@@ -163,6 +166,21 @@ ENTRY(tegra20_cpu_set_resettable_soon)
ENDPROC(tegra20_cpu_set_resettable_soon)
/*
+ * tegra20_cpu_is_resettable_soon(void)
+ *
+ * Returns true if the "resettable soon" flag in PMC_SCRATCH41 has been
+ * set because it is expected that the secondary CPU will be idle soon.
+ */
+ENTRY(tegra20_cpu_is_resettable_soon)
+ mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
+ ldr r12, [r1]
+ cmp r12, #CPU_RESETTABLE_SOON
+ moveq r0, #1
+ movne r0, #0
+ mov pc, lr
+ENDPROC(tegra20_cpu_is_resettable_soon)
+
+/*
* tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
*
* Enters WFI on secondary CPU by exiting coherency.
@@ -221,4 +239,39 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
ldmfd sp!, {r4 - r11, pc}
ENDPROC(tegra20_sleep_cpu_secondary_finish)
+
+/*
+ * tegra20_tear_down_cpu
+ *
+ * Switches the CPU cluster to PLL-P and enters sleep.
+ */
+ENTRY(tegra20_tear_down_cpu)
+ bl tegra_switch_cpu_to_pllp
+ b tegra20_enter_sleep
+ENDPROC(tegra20_tear_down_cpu)
+
+/*
+ * tegra20_enter_sleep
+ *
+ * uses flow controller to enter sleep state
+ * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
+ * executes from SDRAM with target state is LP2
+ */
+tegra20_enter_sleep:
+ mov32 r6, TEGRA_FLOW_CTRL_BASE
+
+ mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
+ orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
+ cpu_id r1
+ cpu_to_halt_reg r1, r1
+ str r0, [r6, r1]
+ dsb
+ ldr r0, [r6, r1] /* memory barrier */
+
+halted:
+ dsb
+ wfe /* CPU should be power gated here */
+ isb
+ b halted
+
#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index addae35..364d845 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -34,6 +34,9 @@
#include "flowctrl.h"
#include "sleep.h"
+#define CLK_RESET_CCLK_BURST 0x20
+#define CLK_RESET_CCLK_DIVIDER 0x24
+
#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
/*
* tegra_disable_clean_inv_dcache
@@ -110,4 +113,20 @@ ENTRY(tegra_shut_off_mmu)
mov pc, r0
ENDPROC(tegra_shut_off_mmu)
.popsection
+
+/*
+ * tegra_switch_cpu_to_pllp
+ *
+ * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp
+ */
+ENTRY(tegra_switch_cpu_to_pllp)
+ /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */
+ mov32 r5, TEGRA_CLK_RESET_BASE
+ mov r0, #(2 << 28) @ burst policy = run mode
+ orr r0, r0, #(4 << 4) @ use PLLP in run mode burst
+ str r0, [r5, #CLK_RESET_CCLK_BURST]
+ mov r0, #0
+ str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
+ mov pc, lr
+ENDPROC(tegra_switch_cpu_to_pllp)
#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index e39a56b..4ffae54 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -131,6 +131,8 @@ static inline void tegra20_hotplug_init(void) {}
static inline void tegra30_hotplug_init(void) {}
#endif
+void tegra20_cpu_shutdown(int cpu);
+int tegra20_cpu_is_resettable_soon(void);
void tegra20_cpu_clear_resettable(void);
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
void tegra20_cpu_set_resettable_soon(void);
@@ -139,6 +141,7 @@ static inline void tegra20_cpu_set_resettable_soon(void) {}
#endif
int tegra20_sleep_cpu_secondary_finish(unsigned long);
+void tegra20_tear_down_cpu(void);
int tegra30_sleep_cpu_secondary_finish(unsigned long);
void tegra30_tear_down_cpu(void);
--
1.8.0.3
^ permalink raw reply related
* [PATCH v2 3/3] at91: at91sam9n12: add DT parameters to enable PMECC
From: Josh Wu @ 2013-01-17 3:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358393072-14794-1-git-send-email-josh.wu@atmel.com>
Default ecc correctable setting is 2bits in 512 bytes.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
---
change log:
v2: rebase to v3.8-rc3
arch/arm/boot/dts/at91sam9n12.dtsi | 1 +
arch/arm/boot/dts/at91sam9n12ek.dts | 5 ++++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index e9efb34..eb9f12e 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -366,6 +366,7 @@
0xffffe600 0x00000200
0x00100000 0x00100000
>;
+ atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 0376bf4..d400f8d 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -71,7 +71,10 @@
nand0: nand at 40000000 {
nand-bus-width = <8>;
- nand-ecc-mode = "soft";
+ nand-ecc-mode = "hw";
+ atmel,has-pmecc;
+ atmel,pmecc-cap = <2>;
+ atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 2/3] at91: 9x5: add DT parameters to enable PMECC
From: Josh Wu @ 2013-01-17 3:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358393072-14794-1-git-send-email-josh.wu@atmel.com>
Default ecc correctable setting is 2bits in 512 bytes.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
---
change log:
v2: rebase to v3.8-rc3
arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++++
arch/arm/boot/dts/at91sam9x5cm.dtsi | 5 ++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 40ac3a4..eedc191 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -480,7 +480,11 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x10000000
+ 0xffffe000 0x600 /* PMECC Registers */
+ 0xffffe600 0x200 /* PMECC Error Location Registers */
+ 0x00100000 0x100000 /* ROM code */
>;
+ atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 31e7be2..4027ac7 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -26,7 +26,10 @@
ahb {
nand0: nand at 40000000 {
nand-bus-width = <8>;
- nand-ecc-mode = "soft";
+ nand-ecc-mode = "hw";
+ atmel,has-pmecc; /* Enable PMECC */
+ atmel,pmecc-cap = <2>;
+ atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 1/3] MTD: at91: atmel_nand: for PMECC, add code to choose the ecc bits and sector size according to the ONFI parameter ECC requirement.
From: Josh Wu @ 2013-01-17 3:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358393072-14794-1-git-send-email-josh.wu@atmel.com>
This patch will check NAND flash's ecc minimum requirement in ONFI parameter.
If ecc minimum requirement is equal or smaller than pmecc-cap in dtsi, then
use ecc_bits in ONFI. otherwise, return an error since pmecc-cap in dtsi
doesn't meet the ecc minimum reqirement.
This patch also check sector size (codeword) requirement in ONFI. If it is
equal or bigger than sector_size in dtsi, then use the one of ONFI.
otherwise return error.
Currently we don't support to read the ECC parameter in ONFI extended
parameter page. So in that case we just use the value specified in dts.
For non-ONFI support nand flash, we assume the minimum ecc requirement is
2bits in 512 bytes.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
---
change log:
v2: wrap the commit message.
drivers/mtd/nand/atmel_nand.c | 89 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index c516a94..b50283a 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -908,6 +908,84 @@ static void atmel_pmecc_core_init(struct mtd_info *mtd)
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
}
+/*
+ * Get ECC requirement in ONFI parameters, returns -1 if ONFI
+ * parameters is not supported.
+ * return 0 if success to get the ECC requirement.
+ */
+static int get_onfi_ecc_param(struct nand_chip *chip,
+ int *ecc_bits, int *sector_size)
+{
+ *ecc_bits = *sector_size = 0;
+
+ if (chip->onfi_params.ecc_bits == 0xff)
+ /* TODO: the sector_size and ecc_bits need to be find in
+ * extended ecc parameter, currently we don't support it.
+ */
+ return -1;
+
+ *ecc_bits = chip->onfi_params.ecc_bits;
+
+ /* The default sector size (ecc codeword size) is 512 */
+ *sector_size = 512;
+
+ return 0;
+}
+
+/*
+ * Choose ecc cap and sector size in atmel_nand_host according to ONFI
+ * parameters ecc requirement.
+ * return 0 if success. otherwise return error code.
+ */
+static int pmecc_choose_ecc_bits(struct atmel_nand_host *host,
+ struct nand_chip *chip)
+{
+ int ecc_bits, sector_size;
+
+ if (!get_onfi_ecc_param(chip, &ecc_bits, §or_size)) {
+ dev_info(host->dev, "ONFI params, minimum required ECC: %dbits in %d bytes\n",
+ ecc_bits, sector_size);
+
+ if (ecc_bits > host->pmecc_corr_cap) {
+ dev_err(host->dev, "Error: Need to set a bigger pmecc-cap in dts. Current is: %d\n",
+ host->pmecc_corr_cap);
+ return -EINVAL;
+ }
+ if (sector_size < host->pmecc_sector_size) {
+ dev_err(host->dev, "Error: Need to set a smaller pmecc-sector-size in dts. Current is: %d\n",
+ host->pmecc_sector_size);
+ return -EINVAL;
+ }
+
+ /* use the most fitable ecc bits (the near bigger one ) */
+ if (ecc_bits <= 2)
+ host->pmecc_corr_cap = 2;
+ else if (ecc_bits <= 4)
+ host->pmecc_corr_cap = 4;
+ else if (ecc_bits < 8)
+ host->pmecc_corr_cap = 8;
+ else if (ecc_bits < 12)
+ host->pmecc_corr_cap = 12;
+ else if (ecc_bits < 24)
+ host->pmecc_corr_cap = 24;
+ else
+ return -EINVAL;
+
+ /* use the most fitable sector size (the near smaller one ) */
+ if (sector_size >= 1024)
+ host->pmecc_sector_size = 1024;
+ else if (sector_size >= 512)
+ host->pmecc_sector_size = 512;
+ else
+ return -EINVAL;
+ } else {
+ dev_info(host->dev,
+ "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet. So use default setting in dts\n");
+ }
+
+ return 0;
+}
+
static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
struct atmel_nand_host *host)
{
@@ -916,8 +994,19 @@ static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
struct resource *regs, *regs_pmerr, *regs_rom;
int cap, sector_size, err_no;
+ if (nand_chip->onfi_version) {
+ /* Choose ecc cap and sector size base on ONFI parameters */
+ err_no = pmecc_choose_ecc_bits(host, nand_chip);
+ if (err_no)
+ return err_no;
+ } else {
+ dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2");
+ host->pmecc_corr_cap = 2;
+ }
+
cap = host->pmecc_corr_cap;
sector_size = host->pmecc_sector_size;
+
dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
cap, sector_size);
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 0/3] at91: PMECC: enable PMECC in dt for at91sam9x5ek, at91sam9n12ek
From: Josh Wu @ 2013-01-17 3:24 UTC (permalink / raw)
To: linux-arm-kernel
Those patches will enable PMECC in dt parameters for at91sam9x5ek, at91sam9n12ek.
The driver will check minimum required ecc on ONFI parameter from NAND flash.
If pmecc-cap in dts doesn't meet the requirement then driver reports a error.
v2: rebase to v3.8-rc3. And wrapped the commit message.
Josh Wu (3):
MTD: at91: atmel_nand: for PMECC, add code to choose the ecc bits and
sector size according to the ONFI parameter ECC requirement.
at91: 9x5: add DT parameters to enable PMECC
at91: at91sam9n12: add DT parameters to enable PMECC
arch/arm/boot/dts/at91sam9n12.dtsi | 1 +
arch/arm/boot/dts/at91sam9n12ek.dts | 5 +-
arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++
arch/arm/boot/dts/at91sam9x5cm.dtsi | 5 +-
drivers/mtd/nand/atmel_nand.c | 89 +++++++++++++++++++++++++++++++++++
5 files changed, 102 insertions(+), 2 deletions(-)
--
1.7.9.5
^ permalink raw reply
* [PATCH v2 1/1 net-next] net: fec: enable pause frame to improve rx prefomance for 1G network
From: David Miller @ 2013-01-17 3:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHrpEqRV7PonDpqAvGkDf7QqSeUj+mVbnF2rA-Zjb9xfWh-_2g@mail.gmail.com>
From: Frank Li <lznuaa@gmail.com>
Date: Thu, 17 Jan 2013 10:50:36 +0800
> Any feedback about this patch?
Well it's full of stylistic problems.
>> + /* enable pause frame*/
>> + if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
>> + ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
>> + fep->phy_dev && fep->phy_dev->pause)) {
This is mis-idented.
>> +
>> + rcntl |= FEC_ENET_FCE;
That empty line before this assignment is spurious.
>> + pause->rx_pause = pause->tx_pause;
>> +
>> +}
That empty line is unnecessary, remove it.
>> + /* default enable pause frame auto negotiation */
>> + if (pdev->id_entry &&
>> + (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
You can't possibly tell me that this indentation looks right
to you.
You must style things like this:
if (condition1 &&
condition2)
That is, you must line up the first character on the second and
subsequent lines at the first column after the openning parenthesis of
the first line.
^ permalink raw reply
* [PATCH v3 1/1 net-next] net: fec: enable pause frame to improve rx prefomance for 1G network
From: Frank Li @ 2013-01-17 2:55 UTC (permalink / raw)
To: linux-arm-kernel
The limition of imx6 internal bus cause fec can't achieve 1G perfomance.
There will be many packages lost because FIFO over run.
This patch enable pause frame flow control.
Before this patch
iperf -s -i 1
TCP window size: 85.3 KByte (default)
------------------------------------------------------------
[ 4] local 10.192.242.153 port 5001 connected with 10.192.242.94 port 49773
[ ID] Interval Transfer Bandwidth
[ 4] 0.0- 1.0 sec 6.35 MBytes 53.3 Mbits/sec
[ 4] 1.0- 2.0 sec 3.39 MBytes 28.5 Mbits/sec
[ 4] 2.0- 3.0 sec 2.63 MBytes 22.1 Mbits/sec
[ 4] 3.0- 4.0 sec 1.10 MBytes 9.23 Mbits/sec
ifconfig
RX packets:46195 errors:1859 dropped:1 overruns:1859 frame:1859
After this patch
iperf -s -i 1
[ 4] local 10.192.242.153 port 5001 connected with 10.192.242.94 port 49757
[ ID] Interval Transfer Bandwidth
[ 4] 0.0- 1.0 sec 49.8 MBytes 418 Mbits/sec
[ 4] 1.0- 2.0 sec 50.1 MBytes 420 Mbits/sec
[ 4] 2.0- 3.0 sec 47.5 MBytes 399 Mbits/sec
[ 4] 3.0- 4.0 sec 45.9 MBytes 385 Mbits/sec
[ 4] 4.0- 5.0 sec 44.8 MBytes 376 Mbits/sec
ifconfig
RX packets:2348454 errors:0 dropped:16 overruns:0 frame:0
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
---
Change from v2 to v3
* Fix code style problem reviewed by David
Change from V1 to V2
* using pause_setparam to enable/disable pause frame
* default enable pause frame auto negotiation
drivers/net/ethernet/freescale/fec.c | 87 +++++++++++++++++++++++++++++++++-
drivers/net/ethernet/freescale/fec.h | 5 ++
2 files changed, 91 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index 6dc2094..8336157 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -68,6 +68,14 @@
#define DRIVER_NAME "fec"
+/* Pause frame feild and FIFO threshold */
+#define FEC_ENET_FCE (1 << 5)
+#define FEC_ENET_RSEM_V 0x84
+#define FEC_ENET_RSFL_V 16
+#define FEC_ENET_RAEM_V 0x8
+#define FEC_ENET_RAFL_V 0x8
+#define FEC_ENET_OPD_V 0xFFF0
+
/* Controller is ENET-MAC */
#define FEC_QUIRK_ENET_MAC (1 << 0)
/* Controller needs driver to swap frame */
@@ -193,6 +201,9 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
/* Transmitter timeout */
#define TX_TIMEOUT (2 * HZ)
+#define FEC_PAUSE_FLAG_AUTONEG 0x1
+#define FEC_PAUSE_FLAG_ENABLE 0x2
+
static int mii_cnt;
static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
@@ -470,6 +481,25 @@ fec_restart(struct net_device *ndev, int duplex)
}
#endif
}
+
+ /* enable pause frame*/
+ if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
+ ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
+ fep->phy_dev && fep->phy_dev->pause)) {
+ rcntl |= FEC_ENET_FCE;
+
+ /* set FIFO thresh hold parameter to reduce overrun */
+ writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
+ writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
+ writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
+ writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
+
+ /* OPD */
+ writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
+ } else {
+ rcntl &= ~FEC_ENET_FCE;
+ }
+
writel(rcntl, fep->hwp + FEC_R_CNTRL);
if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
@@ -1016,8 +1046,10 @@ static int fec_enet_mii_probe(struct net_device *ndev)
}
/* mask with MAC supported features */
- if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT)
+ if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
phy_dev->supported &= PHY_GBIT_FEATURES;
+ phy_dev->supported |= SUPPORTED_Pause;
+ }
else
phy_dev->supported &= PHY_BASIC_FEATURES;
@@ -1203,7 +1235,55 @@ static int fec_enet_get_ts_info(struct net_device *ndev,
}
}
+static void fec_enet_get_pauseparam(struct net_device *ndev,
+ struct ethtool_pauseparam *pause)
+{
+ struct fec_enet_private *fep = netdev_priv(ndev);
+
+ pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
+ pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
+ pause->rx_pause = pause->tx_pause;
+}
+
+static int fec_enet_set_pauseparam(struct net_device *ndev,
+ struct ethtool_pauseparam *pause)
+{
+ struct fec_enet_private *fep = netdev_priv(ndev);
+
+ if (pause->tx_pause != pause->rx_pause) {
+ netdev_info(ndev,
+ "hardware only support enable/disable both tx and rx");
+ return -EINVAL;
+ }
+
+ fep->pause_flag = 0;
+
+ /* tx pause must be same as rx pause */
+ fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
+ fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
+
+ if (pause->rx_pause || pause->autoneg) {
+ fep->phy_dev->supported |= ADVERTISED_Pause;
+ fep->phy_dev->advertising |= ADVERTISED_Pause;
+ } else {
+ fep->phy_dev->supported &= ~ADVERTISED_Pause;
+ fep->phy_dev->advertising &= ~ADVERTISED_Pause;
+ }
+
+ if (pause->autoneg) {
+ if (netif_running(ndev))
+ fec_stop(ndev);
+ phy_start_aneg(fep->phy_dev);
+ }
+ if (netif_running(ndev))
+ fec_restart(ndev, 0);
+
+ return 0;
+}
+
static const struct ethtool_ops fec_enet_ethtool_ops = {
+ .get_pauseparam = fec_enet_get_pauseparam,
+ .set_pauseparam = fec_enet_set_pauseparam,
.get_settings = fec_enet_get_settings,
.set_settings = fec_enet_set_settings,
.get_drvinfo = fec_enet_get_drvinfo,
@@ -1643,6 +1723,11 @@ fec_probe(struct platform_device *pdev)
/* setup board info structure */
fep = netdev_priv(ndev);
+ /* default enable pause frame auto negotiation */
+ if (pdev->id_entry &&
+ (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
+ fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
+
fep->hwp = ioremap(r->start, resource_size(r));
fep->pdev = pdev;
fep->dev_id = dev_id++;
diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
index 4862394..2ebedaf 100644
--- a/drivers/net/ethernet/freescale/fec.h
+++ b/drivers/net/ethernet/freescale/fec.h
@@ -48,6 +48,10 @@
#define FEC_R_DES_START 0x180 /* Receive descriptor ring */
#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */
#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */
+#define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
+#define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */
+#define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */
+#define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */
#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
#define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
@@ -243,6 +247,7 @@ struct fec_enet_private {
struct completion mdio_done;
int irq[FEC_IRQ_NUM];
int bufdesc_ex;
+ int pause_flag;
struct ptp_clock *ptp_clock;
struct ptp_clock_info ptp_caps;
--
1.7.1
^ permalink raw reply related
* [PATCH 3/3] ARM: omap2: use get_auxcr for aux ctrl register read
From: Rob Herring @ 2013-01-17 2:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358391205-23943-1-git-send-email-robherring2@gmail.com>
From: Rob Herring <rob.herring@calxeda.com>
Use get_auxcr instead of inline assembly to read the CP15 aux ctrl
register.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/pm34xx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7be3622..bef8ef6 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -33,6 +33,7 @@
#include <trace/events/power.h>
+#include <asm/cp15.h>
#include <asm/fncpy.h>
#include <asm/suspend.h>
#include <asm/system_misc.h>
@@ -216,9 +217,8 @@ static void omap34xx_save_context(u32 *save)
u32 val;
/* Read Auxiliary Control Register */
- asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
*save++ = 1;
- *save++ = val;
+ *save++ = get_auxcr();
/* Read L2 AUX ctrl register */
asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
--
1.7.10.4
^ permalink raw reply related
* [PATCH 2/3] ARM: convert platform hotplug inline assembly to C
From: Rob Herring @ 2013-01-17 2:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358391205-23943-1-git-send-email-robherring2@gmail.com>
From: Rob Herring <rob.herring@calxeda.com>
With the addition of set_auxcr/get_auxcr, all the hotplug inline assembly
code for exynos, imx, realview, spear13xx and vexpress can be converted to
C code.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
---
arch/arm/mach-exynos/hotplug.c | 57 ++++++-------------------------------
arch/arm/mach-imx/hotplug.c | 19 ++++---------
arch/arm/mach-realview/hotplug.c | 32 +++++----------------
arch/arm/mach-spear13xx/hotplug.c | 32 +++++----------------
arch/arm/mach-vexpress/hotplug.c | 33 +++++----------------
5 files changed, 35 insertions(+), 138 deletions(-)
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index c3f825b..5548fa3 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -26,69 +26,30 @@
static inline void cpu_enter_lowpower_a9(void)
{
- unsigned int v;
-
flush_cache_all();
- asm volatile(
- " mcr p15, 0, %1, c7, c5, 0\n"
- " mcr p15, 0, %1, c7, c10, 4\n"
+ __flush_icache_all();
+ dsb();
+
/*
* Turn off coherency
*/
- " mrc p15, 0, %0, c1, c0, 1\n"
- " bic %0, %0, %3\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- " mrc p15, 0, %0, c1, c0, 0\n"
- " bic %0, %0, %2\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- : "=&r" (v)
- : "r" (0), "Ir" (CR_C), "Ir" (0x40)
- : "cc");
+ set_auxcr(get_auxcr() & ~0x40);
+ set_cr(get_cr() & ~CR_C);
}
static inline void cpu_enter_lowpower_a15(void)
{
- unsigned int v;
-
- asm volatile(
- " mrc p15, 0, %0, c1, c0, 0\n"
- " bic %0, %0, %1\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- : "=&r" (v)
- : "Ir" (CR_C)
- : "cc");
-
+ set_cr(get_cr() & ~CR_C);
flush_cache_louis();
+ set_auxcr(get_auxcr() & ~0x40);
- asm volatile(
- /*
- * Turn off coherency
- */
- " mrc p15, 0, %0, c1, c0, 1\n"
- " bic %0, %0, %1\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- : "=&r" (v)
- : "Ir" (0x40)
- : "cc");
-
- isb();
dsb();
}
static inline void cpu_leave_lowpower(void)
{
- unsigned int v;
-
- asm volatile(
- "mrc p15, 0, %0, c1, c0, 0\n"
- " orr %0, %0, %1\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- " mrc p15, 0, %0, c1, c0, 1\n"
- " orr %0, %0, %2\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- : "=&r" (v)
- : "Ir" (CR_C), "Ir" (0x40)
- : "cc");
+ set_cr(get_cr() | CR_C);
+ set_auxcr(get_auxcr() | 0x40);
}
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 3dec962..1470c75 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -18,24 +18,15 @@
static inline void cpu_enter_lowpower(void)
{
- unsigned int v;
-
flush_cache_all();
- asm volatile(
- "mcr p15, 0, %1, c7, c5, 0\n"
- " mcr p15, 0, %1, c7, c10, 4\n"
+ __flush_icache_all();
+ dsb();
+
/*
* Turn off coherency
*/
- " mrc p15, 0, %0, c1, c0, 1\n"
- " bic %0, %0, %3\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- " mrc p15, 0, %0, c1, c0, 0\n"
- " bic %0, %0, %2\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- : "=&r" (v)
- : "r" (0), "Ir" (CR_C), "Ir" (0x40)
- : "cc");
+ set_auxcr(get_auxcr() & ~0x40);
+ set_cr(get_cr() & ~CR_C);
}
/*
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index 53818e5..c17c8c0 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -18,39 +18,21 @@
static inline void cpu_enter_lowpower(void)
{
- unsigned int v;
-
flush_cache_all();
- asm volatile(
- " mcr p15, 0, %1, c7, c5, 0\n"
- " mcr p15, 0, %1, c7, c10, 4\n"
+ __flush_icache_all();
+ dsb();
+
/*
* Turn off coherency
*/
- " mrc p15, 0, %0, c1, c0, 1\n"
- " bic %0, %0, #0x20\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- " mrc p15, 0, %0, c1, c0, 0\n"
- " bic %0, %0, %2\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- : "=&r" (v)
- : "r" (0), "Ir" (CR_C)
- : "cc");
+ set_auxcr(get_auxcr() & ~0x40);
+ set_cr(get_cr() & ~CR_C);
}
static inline void cpu_leave_lowpower(void)
{
- unsigned int v;
-
- asm volatile( "mrc p15, 0, %0, c1, c0, 0\n"
- " orr %0, %0, %1\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- " mrc p15, 0, %0, c1, c0, 1\n"
- " orr %0, %0, #0x20\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- : "=&r" (v)
- : "Ir" (CR_C)
- : "cc");
+ set_cr(get_cr() | CR_C);
+ set_auxcr(get_auxcr() | 0x40);
}
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c
index a7d2dd1..a38a087 100644
--- a/arch/arm/mach-spear13xx/hotplug.c
+++ b/arch/arm/mach-spear13xx/hotplug.c
@@ -19,39 +19,21 @@
static inline void cpu_enter_lowpower(void)
{
- unsigned int v;
-
flush_cache_all();
- asm volatile(
- " mcr p15, 0, %1, c7, c5, 0\n"
- " dsb\n"
+ __flush_icache_all();
+ dsb();
+
/*
* Turn off coherency
*/
- " mrc p15, 0, %0, c1, c0, 1\n"
- " bic %0, %0, #0x20\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- " mrc p15, 0, %0, c1, c0, 0\n"
- " bic %0, %0, %2\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- : "=&r" (v)
- : "r" (0), "Ir" (CR_C)
- : "cc", "memory");
+ set_auxcr(get_auxcr() & ~0x40);
+ set_cr(get_cr() & ~CR_C);
}
static inline void cpu_leave_lowpower(void)
{
- unsigned int v;
-
- asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
- " orr %0, %0, %1\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- " mrc p15, 0, %0, c1, c0, 1\n"
- " orr %0, %0, #0x20\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- : "=&r" (v)
- : "Ir" (CR_C)
- : "cc");
+ set_cr(get_cr() | CR_C);
+ set_auxcr(get_auxcr() | 0x40);
}
static inline void spear13xx_do_lowpower(unsigned int cpu, int *spurious)
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
index a141b98..74a9eb5 100644
--- a/arch/arm/mach-vexpress/hotplug.c
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -18,40 +18,21 @@
static inline void cpu_enter_lowpower(void)
{
- unsigned int v;
-
flush_cache_all();
- asm volatile(
- "mcr p15, 0, %1, c7, c5, 0\n"
- " mcr p15, 0, %1, c7, c10, 4\n"
+ __flush_icache_all();
+ dsb();
+
/*
* Turn off coherency
*/
- " mrc p15, 0, %0, c1, c0, 1\n"
- " bic %0, %0, %3\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- " mrc p15, 0, %0, c1, c0, 0\n"
- " bic %0, %0, %2\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- : "=&r" (v)
- : "r" (0), "Ir" (CR_C), "Ir" (0x40)
- : "cc");
+ set_auxcr(get_auxcr() & ~0x40);
+ set_cr(get_cr() & ~CR_C);
}
static inline void cpu_leave_lowpower(void)
{
- unsigned int v;
-
- asm volatile(
- "mrc p15, 0, %0, c1, c0, 0\n"
- " orr %0, %0, %1\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- " mrc p15, 0, %0, c1, c0, 1\n"
- " orr %0, %0, %2\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- : "=&r" (v)
- : "Ir" (CR_C), "Ir" (0x40)
- : "cc");
+ set_cr(get_cr() | CR_C);
+ set_auxcr(get_auxcr() | 0x40);
}
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
--
1.7.10.4
^ permalink raw reply related
* [PATCH 1/3] ARM: introduce common set_auxcr/get_auxcr functions
From: Rob Herring @ 2013-01-17 2:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Rob Herring <rob.herring@calxeda.com>
Move the private set_auxcr/get_auxcr functions from
drivers/cpuidle/cpuidle-calxeda.c so they can be used across platforms.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
---
arch/arm/include/asm/cp15.h | 14 ++++++++++++++
drivers/cpuidle/cpuidle-calxeda.c | 14 --------------
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 5ef4d80..ef0094a 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -59,6 +59,20 @@ static inline void set_cr(unsigned int val)
isb();
}
+static inline unsigned int get_auxcr(void)
+{
+ unsigned int val;
+ asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val) : : "cc");
+ return val;
+}
+
+static inline void set_auxcr(unsigned int val)
+{
+ asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
+ : : "r" (val) : "cc");
+ isb();
+}
+
#ifndef CONFIG_SMP
extern void adjust_cr(unsigned long mask, unsigned long set);
#endif
diff --git a/drivers/cpuidle/cpuidle-calxeda.c b/drivers/cpuidle/cpuidle-calxeda.c
index e1aab38..ece83d6 100644
--- a/drivers/cpuidle/cpuidle-calxeda.c
+++ b/drivers/cpuidle/cpuidle-calxeda.c
@@ -37,20 +37,6 @@ extern void *scu_base_addr;
static struct cpuidle_device __percpu *calxeda_idle_cpuidle_devices;
-static inline unsigned int get_auxcr(void)
-{
- unsigned int val;
- asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val) : : "cc");
- return val;
-}
-
-static inline void set_auxcr(unsigned int val)
-{
- asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
- : : "r" (val) : "cc");
- isb();
-}
-
static noinline void calxeda_idle_restore(void)
{
set_cr(get_cr() | CR_C);
--
1.7.10.4
^ permalink raw reply related
* [PATCH v2 1/1 net-next] net: fec: enable pause frame to improve rx prefomance for 1G network
From: Frank Li @ 2013-01-17 2:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358153387-19275-1-git-send-email-Frank.Li@freescale.com>
Any feedback about this patch?
best regards
Frank Li
2013/1/14 Frank Li <Frank.Li@freescale.com>:
> The limition of imx6 internal bus cause fec can't achieve 1G perfomance.
> There will be many packages lost because FIFO over run.
>
> This patch enable pause frame flow control.
>
> Before this patch
> iperf -s -i 1
> TCP window size: 85.3 KByte (default)
> ------------------------------------------------------------
> [ 4] local 10.192.242.153 port 5001 connected with 10.192.242.94 port 49773
> [ ID] Interval Transfer Bandwidth
> [ 4] 0.0- 1.0 sec 6.35 MBytes 53.3 Mbits/sec
> [ 4] 1.0- 2.0 sec 3.39 MBytes 28.5 Mbits/sec
> [ 4] 2.0- 3.0 sec 2.63 MBytes 22.1 Mbits/sec
> [ 4] 3.0- 4.0 sec 1.10 MBytes 9.23 Mbits/sec
>
> ifconfig
> RX packets:46195 errors:1859 dropped:1 overruns:1859 frame:1859
>
> After this patch
> iperf -s -i 1
>
> [ 4] local 10.192.242.153 port 5001 connected with 10.192.242.94 port 49757
> [ ID] Interval Transfer Bandwidth
> [ 4] 0.0- 1.0 sec 49.8 MBytes 418 Mbits/sec
> [ 4] 1.0- 2.0 sec 50.1 MBytes 420 Mbits/sec
> [ 4] 2.0- 3.0 sec 47.5 MBytes 399 Mbits/sec
> [ 4] 3.0- 4.0 sec 45.9 MBytes 385 Mbits/sec
> [ 4] 4.0- 5.0 sec 44.8 MBytes 376 Mbits/sec
>
> ifconfig
> RX packets:2348454 errors:0 dropped:16 overruns:0 frame:0
>
> Signed-off-by: Frank Li <Frank.Li@freescale.com>
> Signed-off-by: Fugang Duan <B38611@freescale.com>
> ---
>
> Change from V1 to V2
> * using pause_setparam to enable/disable pause frame
> * default enable pause frame auto negotiation
>
> drivers/net/ethernet/freescale/fec.c | 89 +++++++++++++++++++++++++++++++++-
> drivers/net/ethernet/freescale/fec.h | 5 ++
> 2 files changed, 93 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
> index 6dc2094..ea30c26 100644
> --- a/drivers/net/ethernet/freescale/fec.c
> +++ b/drivers/net/ethernet/freescale/fec.c
> @@ -68,6 +68,14 @@
>
> #define DRIVER_NAME "fec"
>
> +/* Pause frame feild and FIFO threshold */
> +#define FEC_ENET_FCE (1 << 5)
> +#define FEC_ENET_RSEM_V 0x84
> +#define FEC_ENET_RSFL_V 16
> +#define FEC_ENET_RAEM_V 0x8
> +#define FEC_ENET_RAFL_V 0x8
> +#define FEC_ENET_OPD_V 0xFFF0
> +
> /* Controller is ENET-MAC */
> #define FEC_QUIRK_ENET_MAC (1 << 0)
> /* Controller needs driver to swap frame */
> @@ -193,6 +201,9 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
> /* Transmitter timeout */
> #define TX_TIMEOUT (2 * HZ)
>
> +#define FEC_PAUSE_FLAG_AUTONEG 0x1
> +#define FEC_PAUSE_FLAG_ENABLE 0x2
> +
> static int mii_cnt;
>
> static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
> @@ -470,6 +481,26 @@ fec_restart(struct net_device *ndev, int duplex)
> }
> #endif
> }
> +
> + /* enable pause frame*/
> + if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
> + ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
> + fep->phy_dev && fep->phy_dev->pause)) {
> +
> + rcntl |= FEC_ENET_FCE;
> +
> + /* set FIFO thresh hold parameter to reduce overrun */
> + writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
> + writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
> + writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
> + writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
> +
> + /* OPD */
> + writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
> + } else {
> + rcntl &= ~FEC_ENET_FCE;
> + }
> +
> writel(rcntl, fep->hwp + FEC_R_CNTRL);
>
> if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
> @@ -1016,8 +1047,10 @@ static int fec_enet_mii_probe(struct net_device *ndev)
> }
>
> /* mask with MAC supported features */
> - if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT)
> + if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
> phy_dev->supported &= PHY_GBIT_FEATURES;
> + phy_dev->supported |= SUPPORTED_Pause;
> + }
> else
> phy_dev->supported &= PHY_BASIC_FEATURES;
>
> @@ -1203,7 +1236,56 @@ static int fec_enet_get_ts_info(struct net_device *ndev,
> }
> }
>
> +static void fec_enet_get_pauseparam(struct net_device *ndev,
> + struct ethtool_pauseparam *pause)
> +{
> + struct fec_enet_private *fep = netdev_priv(ndev);
> +
> + pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
> + pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
> + pause->rx_pause = pause->tx_pause;
> +
> +}
> +
> +static int fec_enet_set_pauseparam(struct net_device *ndev,
> + struct ethtool_pauseparam *pause)
> +{
> + struct fec_enet_private *fep = netdev_priv(ndev);
> +
> + if (pause->tx_pause != pause->rx_pause) {
> + netdev_info(ndev,
> + "hardware only support enable/disable both tx and rx");
> + return -EINVAL;
> + }
> +
> + fep->pause_flag = 0;
> +
> + /* tx pause must be same as rx pause */
> + fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
> + fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
> +
> + if (pause->rx_pause || pause->autoneg) {
> + fep->phy_dev->supported |= ADVERTISED_Pause;
> + fep->phy_dev->advertising |= ADVERTISED_Pause;
> + } else {
> + fep->phy_dev->supported &= ~ADVERTISED_Pause;
> + fep->phy_dev->advertising &= ~ADVERTISED_Pause;
> + }
> +
> + if (pause->autoneg) {
> + if (netif_running(ndev))
> + fec_stop(ndev);
> + phy_start_aneg(fep->phy_dev);
> + }
> + if (netif_running(ndev))
> + fec_restart(ndev, 0);
> +
> + return 0;
> +}
> +
> static const struct ethtool_ops fec_enet_ethtool_ops = {
> + .get_pauseparam = fec_enet_get_pauseparam,
> + .set_pauseparam = fec_enet_set_pauseparam,
> .get_settings = fec_enet_get_settings,
> .set_settings = fec_enet_set_settings,
> .get_drvinfo = fec_enet_get_drvinfo,
> @@ -1643,6 +1725,11 @@ fec_probe(struct platform_device *pdev)
> /* setup board info structure */
> fep = netdev_priv(ndev);
>
> + /* default enable pause frame auto negotiation */
> + if (pdev->id_entry &&
> + (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
> + fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
> +
> fep->hwp = ioremap(r->start, resource_size(r));
> fep->pdev = pdev;
> fep->dev_id = dev_id++;
> diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
> index 4862394..2ebedaf 100644
> --- a/drivers/net/ethernet/freescale/fec.h
> +++ b/drivers/net/ethernet/freescale/fec.h
> @@ -48,6 +48,10 @@
> #define FEC_R_DES_START 0x180 /* Receive descriptor ring */
> #define FEC_X_DES_START 0x184 /* Transmit descriptor ring */
> #define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */
> +#define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
> +#define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */
> +#define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */
> +#define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */
> #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
> #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
>
> @@ -243,6 +247,7 @@ struct fec_enet_private {
> struct completion mdio_done;
> int irq[FEC_IRQ_NUM];
> int bufdesc_ex;
> + int pause_flag;
>
> struct ptp_clock *ptp_clock;
> struct ptp_clock_info ptp_caps;
> --
> 1.7.1
>
>
^ permalink raw reply
* [PATCH V4 5/5] ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
From: Joseph Lo @ 2013-01-17 2:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMbhsRQpEE_bkLTZCKno_kDAHh5ggXm6qBSJ91K+ezqwoCsY5A@mail.gmail.com>
On Thu, 2013-01-17 at 10:32 +0800, Colin Cross wrote:
> On Wed, Jan 16, 2013 at 6:05 PM, Joseph Lo <josephl@nvidia.com> wrote:
> > On Thu, 2013-01-17 at 02:55 +0800, Colin Cross wrote:
> >> On Wed, Jan 16, 2013 at 12:11 AM, Joseph Lo <josephl@nvidia.com> wrote:
> >> > The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one
> >> > core to go into this mode before other core. The coupled cpuidle framework
> >> > can help to sync the MPCore to coupled state then go into "powered-down"
> >> > idle mode together. The driver can just assume the MPCore come into
> >> > "powered-down" mode at the same time. No need to take care if the CPU_0
> >> > goes into this mode along and only can put it into safe idle mode (WFI).
> >> >
> >> > The powered-down state of Tegra20 requires power gating both CPU cores.
> >> > When the secondary CPU requests to enter powered-down state, it saves
> >> > its own contexts and then enters WFI for waiting CPU0 in the same state.
> >> > When the CPU0 requests powered-down state, it attempts to put the secondary
> >> > CPU into reset to prevent it from waking up. Then power down both CPUs
> >> > together and power off the cpu rail.
> >> >
> >> > Be aware of that, you may see the legacy power state "LP2" in the code
> >> > which is exactly the same meaning of "CPU power down".
> >> >
> >> > Based on the work by:
> >> > Colin Cross <ccross@android.com>
> >> > Gary King <gking@nvidia.com>
> >> >
> >> > Signed-off-by: Joseph Lo <josephl@nvidia.com>
> >> > ---
> >> > V4:
> >> > * rename the function to "tegra20_wake_cpu1_from_reset"
> >> > * make the coupled cpuidle can be disabled if SMP is disabled
> >> > V3:
> >> > * sqash last two patch in previous version to support coupled cpuidle
> >> > directly
> >> > V2:
> >> > * refine the cpu control function that dedicate for CPU_1
> >> > * rename "tegra_cpu_pllp" to "tegra_switch_cpu_to_pllp"
> >> > ---
> >>
> >> <snip>
> >>
> >> > diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
> >> > index 50f984d..63ab9c2 100644
> >> > --- a/arch/arm/mach-tegra/cpuidle-tegra20.c
> >> > +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
> >>
> >> <snip>
> >>
> >> > @@ -87,20 +176,31 @@ static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
> >> > }
> >> > #endif
> >> >
> >> > -static int tegra20_idle_lp2(struct cpuidle_device *dev,
> >> > - struct cpuidle_driver *drv,
> >> > - int index)
> >> > +static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
> >> > + struct cpuidle_driver *drv,
> >> > + int index)
> >> > {
> >> > u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
> >> > bool entered_lp2 = false;
> >> >
> >> > + if (tegra_pending_sgi())
> >> > + atomic_inc(&abort_flag);
> >> Minor nit, this doesn't need to be atomic. You could just use
> >> abort_flag = true, or ACCESS_ONCE(abort_flag) = true. Each cpu will
> >> either not touch this variable or write 1 to it, so there is no
> >> read/modify/write race.
> >>
> > Thanks for your remind. There is a reason I don't use a boolean flag
> > here. The SGI register was per CPU register. Different CPU may get
> > different content of the register depend on there is a SGI pending or
> > not. That's why I don't use a boolean flag that may be overwritten by
> > the other CPU here.
> >
> > So I think I can just modify as follows and remove atomic operation.
> >
> > if (tegra_pending_sgi())
> > abort_flag++;
> >
> > if (abort_flag > 0)
> > abort coupled cpuidle;
>
> abort_flag++ is a bad idea, it will do a read-modify-write on the
> variable, and two concurrent read-modify-writes will not result in the
> correct value.
>
> In this case you don't care about counting how many cpus have sgis,
> you just care if any cpu does. ACCESS_ONCE(abort_flag) = true will
> work fine, because cpus that do not have a pending sgi will not set
> the variable to false.
Ah, yes. You are right.
Thanks,
Joseph
^ permalink raw reply
* [PATCH v2] drivers/pinctrl: grab default handles from device core
From: Greg KH @ 2013-01-17 2:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdbnyzppd-iom4PL3N3-YkuK+BRNzR577qVc6cPoTKxhTw@mail.gmail.com>
On Thu, Jan 17, 2013 at 01:59:52AM +0100, Linus Walleij wrote:
> On Wed, Jan 16, 2013 at 6:49 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>
> > Hmm. It's causing a lot of engineers here a lot of trouble, since they
> > all see linux-next won't boot, and haven't been paying enough attention
> > to know which commit to revert:-(. Lots of lost productivity:-(
> >
> > Simon, the offending commit:
> >
> > 6d3ef6b drivers/pinctrl: grab default handles from device core
> >
> > is still in next-20130116. Can you please remove it?
>
> Not that this should be in the SH tree, but I have merged your fix
> to the pinctrl tree and it should be in -next, does it fix the problem?
>
> Mainly asking because once Greg ACKs that patch I want to
> put it into the pinctrl tree...
I want to see the updated one with all of the fixes before I ack
anything.
thanks,
greg k-h
^ permalink raw reply
* [PATCH V4 5/5] ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
From: Colin Cross @ 2013-01-17 2:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358388332.1667.7.camel@jlo-ubuntu-64.nvidia.com>
On Wed, Jan 16, 2013 at 6:05 PM, Joseph Lo <josephl@nvidia.com> wrote:
> On Thu, 2013-01-17 at 02:55 +0800, Colin Cross wrote:
>> On Wed, Jan 16, 2013 at 12:11 AM, Joseph Lo <josephl@nvidia.com> wrote:
>> > The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one
>> > core to go into this mode before other core. The coupled cpuidle framework
>> > can help to sync the MPCore to coupled state then go into "powered-down"
>> > idle mode together. The driver can just assume the MPCore come into
>> > "powered-down" mode at the same time. No need to take care if the CPU_0
>> > goes into this mode along and only can put it into safe idle mode (WFI).
>> >
>> > The powered-down state of Tegra20 requires power gating both CPU cores.
>> > When the secondary CPU requests to enter powered-down state, it saves
>> > its own contexts and then enters WFI for waiting CPU0 in the same state.
>> > When the CPU0 requests powered-down state, it attempts to put the secondary
>> > CPU into reset to prevent it from waking up. Then power down both CPUs
>> > together and power off the cpu rail.
>> >
>> > Be aware of that, you may see the legacy power state "LP2" in the code
>> > which is exactly the same meaning of "CPU power down".
>> >
>> > Based on the work by:
>> > Colin Cross <ccross@android.com>
>> > Gary King <gking@nvidia.com>
>> >
>> > Signed-off-by: Joseph Lo <josephl@nvidia.com>
>> > ---
>> > V4:
>> > * rename the function to "tegra20_wake_cpu1_from_reset"
>> > * make the coupled cpuidle can be disabled if SMP is disabled
>> > V3:
>> > * sqash last two patch in previous version to support coupled cpuidle
>> > directly
>> > V2:
>> > * refine the cpu control function that dedicate for CPU_1
>> > * rename "tegra_cpu_pllp" to "tegra_switch_cpu_to_pllp"
>> > ---
>>
>> <snip>
>>
>> > diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
>> > index 50f984d..63ab9c2 100644
>> > --- a/arch/arm/mach-tegra/cpuidle-tegra20.c
>> > +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
>>
>> <snip>
>>
>> > @@ -87,20 +176,31 @@ static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
>> > }
>> > #endif
>> >
>> > -static int tegra20_idle_lp2(struct cpuidle_device *dev,
>> > - struct cpuidle_driver *drv,
>> > - int index)
>> > +static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
>> > + struct cpuidle_driver *drv,
>> > + int index)
>> > {
>> > u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
>> > bool entered_lp2 = false;
>> >
>> > + if (tegra_pending_sgi())
>> > + atomic_inc(&abort_flag);
>> Minor nit, this doesn't need to be atomic. You could just use
>> abort_flag = true, or ACCESS_ONCE(abort_flag) = true. Each cpu will
>> either not touch this variable or write 1 to it, so there is no
>> read/modify/write race.
>>
> Thanks for your remind. There is a reason I don't use a boolean flag
> here. The SGI register was per CPU register. Different CPU may get
> different content of the register depend on there is a SGI pending or
> not. That's why I don't use a boolean flag that may be overwritten by
> the other CPU here.
>
> So I think I can just modify as follows and remove atomic operation.
>
> if (tegra_pending_sgi())
> abort_flag++;
>
> if (abort_flag > 0)
> abort coupled cpuidle;
abort_flag++ is a bad idea, it will do a read-modify-write on the
variable, and two concurrent read-modify-writes will not result in the
correct value.
In this case you don't care about counting how many cpus have sgis,
you just care if any cpu does. ACCESS_ONCE(abort_flag) = true will
work fine, because cpus that do not have a pending sgi will not set
the variable to false.
^ permalink raw reply
* [PATCH V4 5/5] ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
From: Joseph Lo @ 2013-01-17 2:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F71C21.20904@wwwdotorg.org>
On Thu, 2013-01-17 at 05:31 +0800, Stephen Warren wrote:
> On 01/16/2013 11:55 AM, Colin Cross wrote:
> > On Wed, Jan 16, 2013 at 12:11 AM, Joseph Lo <josephl@nvidia.com> wrote:
> >> The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one
> >> core to go into this mode before other core. The coupled cpuidle framework
> >> can help to sync the MPCore to coupled state then go into "powered-down"
> >> idle mode together. The driver can just assume the MPCore come into
> >> "powered-down" mode at the same time. No need to take care if the CPU_0
> >> goes into this mode along and only can put it into safe idle mode (WFI).
> >>
> >> The powered-down state of Tegra20 requires power gating both CPU cores.
> >> When the secondary CPU requests to enter powered-down state, it saves
> >> its own contexts and then enters WFI for waiting CPU0 in the same state.
> >> When the CPU0 requests powered-down state, it attempts to put the secondary
> >> CPU into reset to prevent it from waking up. Then power down both CPUs
> >> together and power off the cpu rail.
> >>
> >> Be aware of that, you may see the legacy power state "LP2" in the code
>
> Colin, since you only raised a few small issues on this series, does
> that mean you're OK with it once those issues are fixed?
>
> Joseph, we'll be merging Tegra114 in the near future. How will this
> patch series affect Tegra114? Will the cpuidle driver simply fail to
> register on Tegra114 (which would be fine until we explicitly add
> support), or would we need to disable cpuidle in Kconfig to get a
> working Tegra114 kernel. Does this patch series affect the answer to the
> previous question? Thanks.
>
Stephen,
This patch series won't affect Tegra114. I think I need to add a simple
cpuidle driver for Tegra114 to support just WFI state first.
And I am going do some re-works about CPUs and cluster power status sync
functions that be introduced recently[1] for CPU hotplug, idle and
secondary booting in Tegra tree. I hope I can hide all the power related
function behind that and make the CPU idle driver be more generic for
all Tegra series.
Before that re-works, I will still keep upstream the platform suspend
function for Tegra.
(If I am not in the right direction, please pull me back.)
Thanks,
Joseph
[1]: https://patchwork.kernel.org/patch/1957891/
https://patchwork.kernel.org/patch/1957951/
(pretty good job by Nicolas and Dave)
^ permalink raw reply
* [PATCH v4] video: imxfb: Do not crash on reboot
From: Fabio Estevam @ 2013-01-17 2:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130117021708.GE26179@S2101-09.ap.freescale.net>
On Thu, Jan 17, 2013 at 12:17 AM, Shawn Guo <shawn.guo@linaro.org> wrote:
> On Wed, Jan 16, 2013 at 10:58:41AM -0200, Fabio Estevam wrote:
>> Shawn,
>>
>> Since you have taken a patch recently that touches this file and given the fact
>> that we have zero response from the fb maintainer, can you please apply it via
>> imx tree?
>
> Ok, I will queue it as the 3rd batch of fixes to be sent next week.
>
> Is it a material for stable tree?
It could be sent to stable, but this patch does not apply to stable
because stable tree does not have your commit:
commit e69dc9a91eeb0387e08d8e1d0e576c88b28902fc
Author: Shawn Guo <shawn.guo@linaro.org>
Date: Sun Sep 16 19:59:53 2012 +0800
video: imxfb: remove cpu_is_xxx by using platform_device_id
^ permalink raw reply
* [PATCH] ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT
From: Shawn Guo @ 2013-01-17 2:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358386324-23995-1-git-send-email-festevam@gmail.com>
On Wed, Jan 16, 2013 at 11:32:04PM -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> Newer versions of udev (such as 182) requires CONFIG_DEVTMPFS_MOUNT to be
> selected, otherwise we get a stuck console:
>
> Starting udev
> Starting Bootlog daemon: bootlogd: cannot deduce real console device
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Applied, thanks.
^ permalink raw reply
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