* [PATCH v4 0/3] mtd: nand: OMAP: ELM error correction support for BCH ecc
From: Philip, Avinash @ 2013-01-18 3:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358424375.2731.234.camel@sauron.fi.intel.com>
On Thu, Jan 17, 2013 at 17:36:15, Artem Bityutskiy wrote:
> On Wed, 2013-01-16 at 12:22 +0000, Philip, Avinash wrote:
> > > This series is based on linux 3.8-rc2 and tested with [1].
> > > Also this patch series depend on [1] for NAND flash device
> > > tree data and gpmc nand device tree binding documentation updates.
> > >
> > > 1. [PATCH v7 0/5] OMAP GPMC DT bindings
> > > http://www.spinics.net/lists/linux-omap/msg83505.html
> > >
> > > Tested on am335x-evm for BCH 4 and 8 bit error correction.
> >
> > Can you apply this patch series on l2-mtd tree as it will help RBL compatibility
> > ecc layout for NAND flash in am335x-platforms and hardware based BCH error
> > correction.
>
> OK, I've applied them. I dropped the part that updates the
> documentation. Please, handle it separately when Daniel's patches are
> in.
>
> Pushed to l2-mtd.git, thanks!
Thanks for applying this patch series.
I will update gpmc-nand documentation part in a separate patch.
Thanks,
Avinash
>
> --
> Best Regards,
> Artem Bityutskiy
>
^ permalink raw reply
* [PATCH] arm: mach-s3c24xx/common.c: fix uninitialized variable warning
From: Kukjin Kim @ 2013-01-18 3:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358185860-5425-1-git-send-email-dinggnu@gmail.com>
Cong Ding wrote:
>
> the use of variable tmp is uninitialized, so we fix it.
>
> Signed-off-by: Cong Ding <dinggnu@gmail.com>
> ---
> arch/arm/mach-s3c24xx/common.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-
> s3c24xx/common.c
> index 0c9e9a7..6bcf87f 100644
> --- a/arch/arm/mach-s3c24xx/common.c
> +++ b/arch/arm/mach-s3c24xx/common.c
> @@ -197,7 +197,7 @@ static unsigned long s3c24xx_read_idcode_v4(void)
>
> static void s3c24xx_default_idle(void)
> {
> - unsigned long tmp;
> + unsigned long tmp = 0;
> int i;
>
> /* idle the system by using the idle mode which will wait for an
> --
> 1.7.9.5
Yes, correct. Applied.
Thanks.
- Kukjin
^ permalink raw reply
* [PATCH 2/3] ARM: convert platform hotplug inline assembly to C
From: Nicolas Pitre @ 2013-01-18 4:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F8C2D5.4070405@gmail.com>
On Thu, 17 Jan 2013, Rob Herring wrote:
> On 01/17/2013 09:42 AM, Nicolas Pitre wrote:
> > On Thu, 17 Jan 2013, Rob Herring wrote:
> >
> >> On 01/16/2013 10:40 PM, Nicolas Pitre wrote:
> >>> On Wed, 16 Jan 2013, Rob Herring wrote:
> >>>
> >>>> From: Rob Herring <rob.herring@calxeda.com>
> >>>>
> >>>> With the addition of set_auxcr/get_auxcr, all the hotplug inline assembly
> >>>> code for exynos, imx, realview, spear13xx and vexpress can be converted to
> >>>> C code.
> >>>
> >>> That might not be all safe. Please see
> >>> http://article.gmane.org/gmane.linux.ports.arm.kernel/209584
> >>
> >> Other than the OR/AND operations, it's all just inline assembly
> >> functions that are called, so it gets compiled to the same code. Perhaps
> >> I should put noinline on the functions so they stay of limited
> >> complexity. If you don't think doing this in C is okay, then there is
> >> probably no point in having the set_auxcr/get_auxcr functions.
> >
> > I think set_auxcr/get_auxcr is fine.
> >
> > But your patch goes beyond simply converting those. You also converted
> > the cache flush and disable from assembly to C, which on a Cortex A9
> > might be unsafe if the stack is modified in the sequence according to
> > the discussion I referenced.
>
> The referenced discussion is mainly for the A15, not the A9, right?
Yes, however Santosh and Lorenzo were concerned by the fact that some
people could look at the A15 code where accessing the stack is fine and
copy it for some A9 where it apparently it is not. See that message I
directed you to and the responses to it.
> It seems the sequences are a bit different. So this is the code for A9
> (spear13xx):
>
> flush_cache_all();
> __flush_icache_all();
> dsb();
>
> /*
> * Turn off coherency
> */
> set_auxcr(get_auxcr() & ~0x40);
> set_cr(get_cr() & ~CR_C);
>
> which generates this:
>
> c027f36c: ebf648d2 bl c00116bc <v7_flush_kern_cache_all>
> c027f370: e3a03000 mov r3, #0
> c027f374: ee073f11 mcr 15, 0, r3, cr7, cr1, {0}
> c027f378: f57ff04f dsb sy
> c027f37c: ee113f30 mrc 15, 0, r3, cr1, cr0, {1}
> c027f380: e3c33040 bic r3, r3, #64 ; 0x40
> c027f384: ee013f30 mcr 15, 0, r3, cr1, cr0, {1}
> c027f388: f57ff06f isb sy
> c027f38c: ee113f10 mrc 15, 0, r3, cr1, cr0, {0}
> c027f390: e3c33004 bic r3, r3, #4
> c027f394: ee013f10 mcr 15, 0, r3, cr1, cr0, {0}
> c027f398: f57ff06f isb sy
> c027f39c: e320f003 wfi
>
> v7_flush_kern_cache_all will generate stack accesses, but I didn't change that
> fact. The I cache invalidate changed from invalidate all to invalidate
> inner-shareable. I believe that should be equivalent. And the mcr version of
> dsb changed to a dsb instruction. Some isb's are inserted as well.
>
> So I don't follow your concern.
_Their_ concern. I did not stop to think about the alleged implications
myself yet. And that doesn't mean the existing code is correct either.
> You can't guarantee that the compiler wouldn't
> insert a data access in the middle, but then you could not guarantee that here
> either (exynos A15):
>
> asm volatile(
> " mrc p15, 0, %0, c1, c0, 0\n"
> " bic %0, %0, %1\n"
> " mcr p15, 0, %0, c1, c0, 0\n"
> : "=&r" (v)
> : "Ir" (CR_C)
> : "cc");
>
> flush_cache_louis();
Hence Lorenzo's argument that this should be done from assembly in a
single stretch without memory access in the middle.
So, given the uncertainty around the correctness of the cache flush on a
Cortex-A9, I'd suggest you steer clear of the debate and only convert
accesses to the aux ctrl register.
Nicolas
^ permalink raw reply
* [PATCH] ARM: OMAP: gpmc: Add device tree documentation for elm handle
From: Philip Avinash @ 2013-01-18 4:57 UTC (permalink / raw)
To: linux-arm-kernel
In case ELM module available, omap2 NAND driver can opt for hardware
correction method for bit flip errors in NAND flash with BCH. Hence the
detection of ELM module is done through devicetree population of elm_id.
This patch update device tree documentation for gpmc-nand for elm-id
data population.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
---
This patch based [1] and depends on [2]. As Artem suggested, this patch can
go in omap_tree due to the dependency on [3].
Discussion can found at [4]
Tony,
Can you accept this patch.
1. http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap.git;a=shortlog;h=refs/heads/omap-for-v3.9/gpmc
2. mtd: nand: omap2: Support for hardware BCH error correction
http://git.infradead.org/users/dedekind/l2-mtd-2.6.git/commit/576daed18c3f27bb5d0e57e1df11e8f7b493dce8
3. ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap.git;a=commit;h=bc6b1e7b86f5d8e4a6fc1c0189e64bba4077efe0
4. https://lkml.org/lkml/2013/1/17/167
.../devicetree/bindings/mtd/gpmc-nand.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index 9f464f9..e7f8d7e 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -29,6 +29,9 @@ Optional properties:
"bch4" 4-bit BCH ecc code
"bch8" 8-bit BCH ecc code
+ - elm_id: Specifies elm device node. This is required to support BCH
+ error correction using ELM module.
+
For inline partiton table parsing (optional):
- #address-cells: should be set to 1
@@ -46,6 +49,7 @@ Example for an AM33xx board:
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND */
+ elm_id = <&elm>;
nand at 0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3] gpio: vt8500: memory cleanup missing
From: Tony Prisk @ 2013-01-18 4:58 UTC (permalink / raw)
To: linux-arm-kernel
This driver is missing a .remove callback, and the fail path on
probe is incomplete.
If an error occurs in vt8500_add_chips, gpio_base is not unmapped.
The driver is also ignoring the return value from this function so
if a chip fails to register it completes as successful.
Replaced pr_err with dev_err in vt8500_add_chips since the device is
available.
There is also no .remove callback defined so the function is added.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
---
v2:
Remove global vtchip and store pointer in platform_data - As pointed out by
Russell King.
v3:
Following problems pointed out by Grant Likely:
Removed unnecessary whitespace change.
Removed test against pdev->dev.of_node (np). Replaced code with a
devm_request_and_ioremap so np is now unneccessary. This also removes the need
for cleanup in the fail path.
Move struct vt8500_gpio_chip within vt8500_data and store the iobase and
num_banks in vt8500_data.
drivers/gpio/gpio-vt8500.c | 61 +++++++++++++++++++++++++++++++++++---------
1 file changed, 49 insertions(+), 12 deletions(-)
diff --git a/drivers/gpio/gpio-vt8500.c b/drivers/gpio/gpio-vt8500.c
index b53320a..5c8cd7c 100644
--- a/drivers/gpio/gpio-vt8500.c
+++ b/drivers/gpio/gpio-vt8500.c
@@ -127,6 +127,12 @@ struct vt8500_gpio_chip {
void __iomem *base;
};
+struct vt8500_data {
+ struct vt8500_gpio_chip *chip;
+ void __iomem *iobase;
+ int num_banks;
+};
+
#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
@@ -224,19 +230,32 @@ static int vt8500_of_xlate(struct gpio_chip *gc,
static int vt8500_add_chips(struct platform_device *pdev, void __iomem *base,
const struct vt8500_gpio_data *data)
{
+ struct vt8500_data *priv;
struct vt8500_gpio_chip *vtchip;
struct gpio_chip *chip;
int i;
int pin_cnt = 0;
- vtchip = devm_kzalloc(&pdev->dev,
+ priv = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_data), GFP_KERNEL);
+ if (!priv) {
+ dev_err(&pdev->dev, "failed to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ priv->chip = devm_kzalloc(&pdev->dev,
sizeof(struct vt8500_gpio_chip) * data->num_banks,
GFP_KERNEL);
- if (!vtchip) {
- pr_err("%s: failed to allocate chip memory\n", __func__);
+ if (!priv->chip) {
+ dev_err(&pdev->dev, "failed to allocate chip memory\n");
return -ENOMEM;
}
+ priv->iobase = base;
+ priv->num_banks = data->num_banks;
+ platform_set_drvdata(pdev, priv);
+
+ vtchip = priv->chip;
+
for (i = 0; i < data->num_banks; i++) {
vtchip[i].base = base;
vtchip[i].regs = &data->banks[i];
@@ -273,36 +292,54 @@ static struct of_device_id vt8500_gpio_dt_ids[] = {
static int vt8500_gpio_probe(struct platform_device *pdev)
{
+ int ret;
void __iomem *gpio_base;
- struct device_node *np;
+ struct resource *res;
const struct of_device_id *of_id =
of_match_device(vt8500_gpio_dt_ids, &pdev->dev);
if (!of_id) {
- dev_err(&pdev->dev, "Failed to find gpio controller\n");
+ dev_err(&pdev->dev, "No matching driver data\n");
return -ENODEV;
}
- np = pdev->dev.of_node;
- if (!np) {
- dev_err(&pdev->dev, "Missing GPIO description in devicetree\n");
- return -EFAULT;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Unable to get IO resource\n");
+ return -ENODEV;
}
- gpio_base = of_iomap(np, 0);
+ gpio_base = devm_request_and_ioremap(&pdev->dev, res);
if (!gpio_base) {
dev_err(&pdev->dev, "Unable to map GPIO registers\n");
- of_node_put(np);
return -ENOMEM;
}
- vt8500_add_chips(pdev, gpio_base, of_id->data);
+ ret = vt8500_add_chips(pdev, gpio_base, of_id->data);
+
+ return ret;
+}
+
+static int vt8500_gpio_remove(struct platform_device *pdev)
+{
+ int i;
+ int ret;
+ struct vt8500_data *priv = platform_get_drvdata(pdev);
+ struct vt8500_gpio_chip *vtchip = priv->chip;
+
+ for (i = 0; i < priv->num_banks; i++) {
+ ret = gpiochip_remove(&vtchip[i].chip);
+ if (ret)
+ dev_warn(&pdev->dev, "gpiochip_remove returned %d\n",
+ ret);
+ }
return 0;
}
static struct platform_driver vt8500_gpio_driver = {
.probe = vt8500_gpio_probe,
+ .remove = vt8500_gpio_remove,
.driver = {
.name = "vt8500-gpio",
.owner = THIS_MODULE,
--
1.7.9.5
^ permalink raw reply related
* [PATCH] ARM: shmobile: armadillo800eva: set clock rates before timer init
From: Hideki EIRAKU @ 2013-01-18 5:02 UTC (permalink / raw)
To: linux-arm-kernel
Previously clock rates were set after initialization of timer.
Therefore the timer used the default extal1 clock rate (25MHz)
instead of the correct rate for this board (24MHz).
Signed-off-by: Hideki EIRAKU <hdk@igel.co.jp>
---
arch/arm/mach-shmobile/board-armadillo800eva.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 5353adf..1e79cfb 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1175,8 +1175,6 @@ static void __init eva_init(void)
platform_add_devices(eva_devices,
ARRAY_SIZE(eva_devices));
- eva_clock_init();
-
rmobile_add_device_to_domain("A4LC", &lcdc0_device);
rmobile_add_device_to_domain("A4LC", &hdmi_lcdc_device);
if (usb)
@@ -1187,6 +1185,9 @@ static void __init eva_earlytimer_init(void)
{
r8a7740_clock_init(MD_CK0 | MD_CK2);
shmobile_earlytimer_init();
+
+ /* the rate of extal1 clock must be set before late_time_init */
+ eva_clock_init();
}
static void __init eva_add_early_devices(void)
--
1.8.0
^ permalink raw reply related
* [RFC v2 12/18] ARM: OMAP2+: timer: Add suspend-resume callbacks for clockevent device
From: Santosh Shilimkar @ 2013-01-18 5:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F846D7.8060509@ti.com>
On Friday 18 January 2013 12:15 AM, Jon Hunter wrote:
>
> On 01/10/2013 10:37 PM, Bedia, Vaibhav wrote:
>> On Tue, Jan 08, 2013 at 20:45:10, Shilimkar, Santosh wrote:
>>> On Monday 31 December 2012 06:37 PM, Vaibhav Bedia wrote:
>>>> The current OMAP timer code registers two timers -
>>>> one as clocksource and one as clockevent.
>>>> AM33XX has only one usable timer in the WKUP domain
>>>> so one of the timers needs suspend-resume support
>>>> to restore the configuration to pre-suspend state.
>>>>
>>>> commit adc78e6 (timekeeping: Add suspend and resume
>>>> of clock event devices) introduced .suspend and .resume
>>>> callbacks for clock event devices. Leverages these
>>>> callbacks to have AM33XX clockevent timer which is
>>>> in not in WKUP domain to behave properly across system
>>>> suspend.
>>>>
>>>> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
>>>> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> Cc: Benoit Cousson <b-cousson@ti.com>
>>>> Cc: Paul Walmsley <paul@pwsan.com>
>>>> Cc: Kevin Hilman <khilman@deeprootsystems.com>
>>>> Cc: Vaibhav Hiremath <hvaibhav@ti.com>
>>>> Cc: Jon Hunter <jon-hunter@ti.com>
>>>> ---
>>>> v1->v2:
>>>> Get rid of harcoded timer id.
>>>> Note: since a platform device is not created for these timer
>>>> instances and because there's very minimal change needed for
>>>> restarting the timer a full blown context save and restore
>>>> has been skipped.
>>>>
>>>> arch/arm/mach-omap2/timer.c | 33 +++++++++++++++++++++++++++++++++
>>>> 1 files changed, 33 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
>>>> index 691aa67..38f9cbc 100644
>>>> --- a/arch/arm/mach-omap2/timer.c
>>>> +++ b/arch/arm/mach-omap2/timer.c
>>>> @@ -128,6 +128,36 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
>>>> }
>>>> }
>>>>
>>>> +static void omap_clkevt_suspend(struct clock_event_device *unused)
>>>> +{
>>>> + char name[10];
>>>> + struct omap_hwmod *oh;
>>>> +
>>>> + sprintf(name, "timer%d", clkev.id);
>>>> + oh = omap_hwmod_lookup(name);
>>>> + if (!oh)
>>>> + return;
>>>> +
>>>> + __omap_dm_timer_stop(&clkev, 1, clkev.rate);
>>>> + omap_hwmod_idle(oh);
>>>> +}
>>>> +
>>>> +static void omap_clkevt_resume(struct clock_event_device *unused)
>>>> +{
>>>> + char name[10];
>>>> + struct omap_hwmod *oh;
>>>> +
>>>> + sprintf(name, "timer%d", clkev.id);
>>>> + oh = omap_hwmod_lookup(name);
>>>> + if (!oh)
>>>> + return;
>>>> +
>>>> + omap_hwmod_enable(oh);
>>>> + __omap_dm_timer_load_start(&clkev,
>>>> + OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
>>>> + __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
>>>> +}
>>>> +
>>> Am still bit uncomfortable with direct hwmod usage in the suspend/resmue
>>> hooks.
>>>
>>> Jon, Any alternatives you can think of ?
>>>
>>
>> Jon,
>>
>> Any suggestions here?
>
> Sorry completed this missed this!
>
> Unfortunately, I don't have any good suggestions here. However, I am
> wondering if the suspend/resume handlers can just be calls to
> omap_hwmod_idle/enable and we can remove these __omap_dm_timer_xxxx
> calls (I don't think they are needed). Furthermore, my understanding is
> this is only needed for AM335x (per the changelog), and so we should not
> add suspend/resume handlers for all OMAP2+ based devices.
>
I agree with the direction.
Regards,
Santosh
^ permalink raw reply
* [RFC PATCH 3/6] usb: otg: utils: change the phy lib to support multiple PHYs of same type
From: kishon @ 2013-01-18 5:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F821DD.1040609@ti.com>
Hi,
On Thursday 17 January 2013 09:37 PM, Roger Quadros wrote:
> On 01/16/2013 05:00 PM, Kishon Vijay Abraham I wrote:
>> In order to add support for multipe PHY's of the same type, the API's
>> for adding PHY and getting PHY has been changed. Now the binding
>> information of the PHY and controller should be done in platform file
>> using usb_bind_phy API. And for getting a PHY, the device pointer of the
>> USB controller and an index should be passed. Based on the binding
>> information that is added in the platform file, get_phy will return the
>> approappropriate PHY.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> arch/arm/mach-shmobile/board-marzen.c | 2 +-
>> drivers/power/ab8500_charger.c | 2 +-
>> drivers/power/isp1704_charger.c | 2 +-
>> drivers/power/pda_power.c | 2 +-
>> drivers/power/twl4030_charger.c | 2 +-
>> drivers/usb/chipidea/udc.c | 2 +-
>> drivers/usb/dwc3/core.c | 4 +-
>> drivers/usb/gadget/fsl_udc_core.c | 2 +-
>> drivers/usb/gadget/mv_udc_core.c | 2 +-
>> drivers/usb/gadget/omap_udc.c | 2 +-
>> drivers/usb/gadget/pxa25x_udc.c | 2 +-
>> drivers/usb/gadget/pxa27x_udc.c | 2 +-
>> drivers/usb/gadget/s3c-hsudc.c | 2 +-
>> drivers/usb/host/ehci-fsl.c | 2 +-
>> drivers/usb/host/ehci-msm.c | 2 +-
>> drivers/usb/host/ehci-mv.c | 2 +-
>> drivers/usb/host/ehci-tegra.c | 2 +-
>> drivers/usb/host/ohci-omap.c | 2 +-
>> drivers/usb/musb/am35x.c | 2 +-
>> drivers/usb/musb/blackfin.c | 2 +-
>> drivers/usb/musb/da8xx.c | 2 +-
>> drivers/usb/musb/davinci.c | 2 +-
>> drivers/usb/musb/musb_dsps.c | 2 +-
>> drivers/usb/musb/omap2430.c | 2 +-
>> drivers/usb/musb/tusb6010.c | 2 +-
>> drivers/usb/musb/ux500.c | 2 +-
>> drivers/usb/otg/ab8500-usb.c | 3 +-
>> drivers/usb/otg/fsl_otg.c | 5 ++-
>> drivers/usb/otg/gpio_vbus.c | 3 +-
>> drivers/usb/otg/isp1301_omap.c | 3 +-
>> drivers/usb/otg/msm_otg.c | 3 +-
>> drivers/usb/otg/mv_otg.c | 3 +-
>> drivers/usb/otg/nop-usb-xceiv.c | 3 +-
>> drivers/usb/otg/otg.c | 67 +++++++++++++++------------------
>> drivers/usb/otg/twl4030-usb.c | 3 +-
>> drivers/usb/phy/mv_u3d_phy.c | 3 +-
>> drivers/usb/phy/omap-usb2.c | 11 ++----
>> drivers/usb/phy/rcar-phy.c | 3 +-
>> include/linux/usb/phy.h | 12 +++---
>> 39 files changed, 87 insertions(+), 89 deletions(-)
>
> I think it better to leave the existing add/get APIs as they are add add
> new APIs that support multiple PHYs. You could probably mark the old
> ones as deprecated.
>
> That way you don't need to wait till all users are converted and tested.
Makes sense. Will do that :-)
Thanks
Kishon
^ permalink raw reply
* [PATCH] ARM: tegra: DTS: whistler: enable keyboard
From: Laxman Dewangan @ 2013-01-18 5:58 UTC (permalink / raw)
To: linux-arm-kernel
Enable tegra based keyboard controller and populate the key mapping
for whistler.
With this patch, HOME, BACK, POWER and MENU keys will work.
Still other keys which are in ROW3 and ROW4 will not work as it
conflicts with KBC pins on SDIO2 pinmux.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Stephen,
Not tested the change but I reviewed all possible configuration like pinmux and
the parameter as per the downstream.
Request you to give a try.
arch/arm/boot/dts/tegra20-whistler.dts | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 5836ad6..b8e0ee1 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -520,6 +520,18 @@
bus-width = <8>;
};
+ kbc {
+ status = "okay";
+ nvidia,debounce-delay-ms = <20>;
+ nvidia,repeat-delay-ms = <160>;
+ nvidia,kbc-row-pins = <0 1 2>;
+ nvidia,kbc-col-pins = <16 17>;
+ linux,keymap = <0x00000074 /* KEY_POWER */
+ 0x01000066 /* KEY_HOME */
+ 0x0101009E /* KEY_BACK */
+ 0x0201008B>; /* KEY_MENU */
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
--
1.7.1.1
^ permalink raw reply related
* [PATCH] ARM: shmobile: armadillo800eva: set clock rates before timer init
From: Kuninori Morimoto @ 2013-01-18 6:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358485325-19673-1-git-send-email-hdk@igel.co.jp>
> Previously clock rates were set after initialization of timer.
> Therefore the timer used the default extal1 clock rate (25MHz)
> instead of the correct rate for this board (24MHz).
>
> Signed-off-by: Hideki EIRAKU <hdk@igel.co.jp>
> ---
> arch/arm/mach-shmobile/board-armadillo800eva.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Best regards
---
Kuninori Morimoto
^ permalink raw reply
* [PATCH v7] usb: phy: samsung: Add support to set pmu isolation
From: Vivek Gautam @ 2013-01-18 6:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <003001cdf519$6d21c690$476553b0$@samsung.com>
HI Kukjin,
On Fri, Jan 18, 2013 at 6:46 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Vivek Gautam wrote:
>>
>> Adding support to parse device node data in order to get
>> required properties to set pmu isolation for usb-phy.
>>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
>> Reviewed-by: Doug Anderson <dianders@chromium.org>
>
> This looks good to me,
> Acked-by: Kukjin Kim <kgene.kim@samsung.com>
>
Thanks
> Vivek, could you please re-send following in one series?
> - [PATCH v9 1/2] usb: phy: samsung: Introducing usb phy driver for hsotg
> - [PATCH v8 2/2] usb: s3c-hsotg: Adding phy driver support
>
Praveen will re-send this patch-series asap.
> As I know, this should be applied on top of above patches.
>
--
Thanks & Regards
Vivek
^ permalink raw reply
* [PATCH] ARM: shmobile: ipmmu: Add basic PMB support
From: Damian Hobson-Garcia @ 2013-01-18 6:35 UTC (permalink / raw)
To: linux-arm-kernel
The PMB can be used to remap 16, 64, 128 or 512 MiB pages from
the 0x80000000-0xffffffff address range to anywhere in the
0x00000000-0x7fffffff range.
It also has the ability to perform tiled-linear address translation,
which can be used to access a memory buffer as a series of n x m tiles,
useful for image encoding/decoding.
Currently only the userspace API via character device is supported.
All register access and hardware dependent functionality is
provided by the IPMMU driver, which is shared with the IOMMU/TLB module.
Signed-off-by: Damian Hobson-Garcia <dhobsong@igel.co.jp>
---
This patch must be applied on top of the IPMMU patch series by
Hideki EIRAKU. The code has been placed in the drivers/iommu directory for
two reasons:
1) The PMB also performs hardware address translation
2) Since the PMB shares the same register address range as the
shmobile IOMMU, the two functions are accessed through the same
platform device, the driver for which is in drivers/iommu
drivers/iommu/Kconfig | 14 ++
drivers/iommu/Makefile | 1 +
drivers/iommu/shmobile-ipmmu.c | 117 ++++++++++++-
drivers/iommu/shmobile-ipmmu.h | 28 +++-
drivers/iommu/shmobile-pmb.c | 362 ++++++++++++++++++++++++++++++++++++++++
include/linux/ipmmu.h | 29 ++++
6 files changed, 544 insertions(+), 7 deletions(-)
create mode 100644 drivers/iommu/shmobile-pmb.c
create mode 100644 include/linux/ipmmu.h
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index d364494..44af0cb 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -261,4 +261,18 @@ config SHMOBILE_IOMMU_L1SIZE
default 256 if SHMOBILE_IOMMU_ADDRSIZE_64MB
default 128 if SHMOBILE_IOMMU_ADDRSIZE_32MB
+config SHMOBILE_PMB
+ bool "IPMMU PMB driver"
+ default n
+ select SHMOBILE_IPMMU
+ help
+ This enables the PMB interface of the IPMMU hardware module.
+ The PMB can be used to remap 16, 64, 128 or 512 MiB pages from
+ the 0x80000000-0xffffffff address range to anywhere in the
+ 0x00000000-0x7fffffff range.
+ PMB support can be used either with or without SHMOBILE IOMMU
+ support.
+
+ If unsure, say N.
+
endif # IOMMU_SUPPORT
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index ef0e520..618238b 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o
obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o
obj-$(CONFIG_SHMOBILE_IOMMU) += shmobile-iommu.o
obj-$(CONFIG_SHMOBILE_IPMMU) += shmobile-ipmmu.o
+obj-$(CONFIG_SHMOBILE_PMB) += shmobile-pmb.o
diff --git a/drivers/iommu/shmobile-ipmmu.c b/drivers/iommu/shmobile-ipmmu.c
index 8321f89..db2ae78 100644
--- a/drivers/iommu/shmobile-ipmmu.c
+++ b/drivers/iommu/shmobile-ipmmu.c
@@ -14,15 +14,34 @@
#include <linux/slab.h>
#include <linux/platform_data/sh_ipmmu.h>
#include "shmobile-ipmmu.h"
+#include <linux/ipmmu.h>
-#define IMCTR1 0x000
-#define IMCTR2 0x004
-#define IMASID 0x010
-#define IMTTBR 0x014
-#define IMTTBCR 0x018
-
+#define IMCTR1 0x00
#define IMCTR1_TLBEN (1 << 0)
#define IMCTR1_FLUSH (1 << 1)
+#define IMCTR2 0x04
+#define IMCTR2_PMBEN 0x01
+#define IMASID 0x010
+#define IMTTBR 0x014
+#define IMTTBCR 0x018
+#define IMPMBA_BASE 0x80
+#define IMPBMA_V (1 << 8)
+#define IMPMBD_BASE 0xC0
+#define IMPBMD_V (1 << 8)
+#define IMPBMD_SZ_16M 0x00
+#define IMPBMD_SZ_64M 0x10
+#define IMPBMD_SZ_128M 0x80
+#define IMPBMD_SZ_512M 0x90
+#define IMPBMD_BV (1 << 9)
+#define IMPBMD_TBM_MASK (7 << 12)
+#define IMPBMD_TBM_POS 12
+#define IMPBMD_HBM_MASK (7 << 16)
+#define IMPBMD_HBM_POS 16
+#define IMPBMD_VBM_MASK (7 << 20)
+#define IMPBMD_VBM_POS 20
+
+#define IMPBMA(x) (IMPMBA_BASE + 0x4*x)
+#define IMPBMD(x) (IMPMBD_BASE + 0x4*x)
static void ipmmu_reg_write(struct shmobile_ipmmu *ipmmu, unsigned long reg_off,
unsigned long data)
@@ -88,6 +107,91 @@ void ipmmu_tlb_set(struct shmobile_ipmmu *ipmmu, unsigned long phys, int size,
mutex_unlock(&ipmmu->flush_lock);
}
+int ipmmu_pmb_enable(struct shmobile_ipmmu *ipmmu,
+ int enable)
+{
+ ipmmu_reg_write(ipmmu, IMCTR2, enable ? IMCTR2_PMBEN : 0);
+ return 0;
+
+}
+int ipmmu_pmb_set_addr(struct shmobile_ipmmu *ipmmu,
+ int index,
+ unsigned long addr,
+ int enabled)
+{
+
+ if (!enabled) {
+ ipmmu_reg_write(ipmmu, IMPBMA(index), 0);
+ return 0;
+ }
+
+ ipmmu_reg_write(ipmmu, IMPBMA(index), addr |
+ IMPBMD_V);
+ return 0;
+
+}
+
+int ipmmu_pmb_set_data(struct shmobile_ipmmu *ipmmu,
+ int index,
+ struct ipmmu_pmb_info *info,
+ struct pmb_tile_info *tile)
+{
+ int vbm, hbm, tbm;
+ int w, h;
+ unsigned long temp;
+
+ if (!info || !info->enabled) {
+ ipmmu_reg_write(ipmmu, IMPBMD(index), 0);
+ return 0;
+ }
+
+ temp = info->paddr;
+
+ switch (info->size_mb) {
+ case 16:
+ temp |= IMPBMD_SZ_16M;
+ break;
+ case 64:
+ temp |= IMPBMD_SZ_64M;
+ break;
+ case 128:
+ temp |= IMPBMD_SZ_128M;
+ break;
+ case 512:
+ temp |= IMPBMD_SZ_512M;
+ break;
+ default:
+ break;
+ }
+
+ temp |= IMPBMD_V;
+
+ if (!tile || !tile->enabled) {
+ ipmmu_reg_write(ipmmu, IMPBMD(index), temp);
+ return 0;
+ }
+
+ w = tile->tile_width;
+ h = tile->tile_height;
+
+ if (w & (w - 1) || h & (h - 1))
+ return -EINVAL;
+
+ tbm = ilog2(tile->tile_width);
+ vbm = ilog2(tile->tile_height) - 1;
+ hbm = ilog2(tile->buffer_pitch) - tbm - 1;
+ tbm -= 4;
+
+ temp |= (tbm << IMPBMD_TBM_POS) & IMPBMD_TBM_MASK;
+ temp |= (vbm << IMPBMD_VBM_POS) & IMPBMD_VBM_MASK;
+ temp |= (hbm << IMPBMD_HBM_POS) & IMPBMD_HBM_MASK;
+ temp |= IMPBMD_BV;
+ ipmmu_reg_write(ipmmu, IMPBMD(index),
+ temp);
+ ipmmu_tlb_flush(ipmmu);
+ return 0;
+}
+
static int ipmmu_probe(struct platform_device *pdev)
{
struct shmobile_ipmmu *ipmmu;
@@ -118,6 +222,7 @@ static int ipmmu_probe(struct platform_device *pdev)
ipmmu_reg_write(ipmmu, IMCTR1, 0x0); /* disable TLB */
ipmmu_reg_write(ipmmu, IMCTR2, 0x0); /* disable PMB */
ipmmu_iommu_init(ipmmu);
+ ipmmu->pmb_priv = ipmmu_pmb_init(ipmmu);
return 0;
}
diff --git a/drivers/iommu/shmobile-ipmmu.h b/drivers/iommu/shmobile-ipmmu.h
index 6270e7c..ecc4211 100644
--- a/drivers/iommu/shmobile-ipmmu.h
+++ b/drivers/iommu/shmobile-ipmmu.h
@@ -11,6 +11,8 @@
#define __SHMOBILE_IPMMU_H__
struct dma_iommu_mapping;
+struct pmb_tile_info;
+struct ipmmu_pmb_info;
struct shmobile_ipmmu {
struct device *dev;
@@ -20,10 +22,12 @@ struct shmobile_ipmmu {
struct dma_iommu_mapping *iommu_mapping;
const char * const *dev_names;
unsigned int num_dev_names;
+ void *pmb_priv;
};
-#ifdef CONFIG_SHMOBILE_IPMMU_TLB
void ipmmu_tlb_flush(struct shmobile_ipmmu *ipmmu);
+
+#ifdef CONFIG_SHMOBILE_IPMMU_TLB
void ipmmu_tlb_set(struct shmobile_ipmmu *ipmmu, unsigned long phys, int size,
int asid);
int ipmmu_iommu_init(struct shmobile_ipmmu *ipmmu);
@@ -34,4 +38,26 @@ static int ipmmu_iommu_init(struct shmobile_ipmmu *ipmmu)
}
#endif
+#ifdef CONFIG_SHMOBILE_PMB
+/* Access functions used by PMB device */
+/*void handle_free(struct device *dev, unsigned long handle, int size_mb);
+unsigned long handle_alloc(struct device *dev, int size_mb);*/
+int ipmmu_pmb_set_addr(struct shmobile_ipmmu *ipmmu,
+ int index, unsigned long addr,
+ int enabled);
+int ipmmu_pmb_set_data(struct shmobile_ipmmu *ipmmu, int index,
+ struct ipmmu_pmb_info *info,
+ struct pmb_tile_info *tile);
+int ipmmu_pmb_enable(struct shmobile_ipmmu *ipmmu, int index);
+/* PMB initialization */
+void *ipmmu_pmb_init(struct shmobile_ipmmu *ipmmu);
+void ipmmu_pmb_deinit(void *pmb_priv);
+#else
+static inline void *ipmmu_pmb_init(struct device *dev)
+{
+ return NULL;
+}
+static inline void ipmmu_pmb_deinit(void *pmb_priv) { }
+#endif
+
#endif /* __SHMOBILE_IPMMU_H__ */
diff --git a/drivers/iommu/shmobile-pmb.c b/drivers/iommu/shmobile-pmb.c
new file mode 100644
index 0000000..464af0b
--- /dev/null
+++ b/drivers/iommu/shmobile-pmb.c
@@ -0,0 +1,362 @@
+/*
+ * IPMMU-PMB driver
+ * Copyright (C) 2012 Damian Hobson-Garcia
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/cdev.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/ipmmu.h>
+#include "shmobile-ipmmu.h"
+#include <linux/uaccess.h>
+
+#define PMB_DEVICE_NAME "pmb"
+
+#define PMB_NR 16
+/* the smallest size that can be reserverd in the pmb */
+#define PMB_GRANULARITY (16 << 20)
+#define PMB_START_ADDR 0x80000000
+#define PMB_SIZE 0x40000000
+#define NUM_BITS(x) ((x) / PMB_GRANULARITY)
+#define NR_BITMAPS ((NUM_BITS(PMB_SIZE) + BITS_PER_LONG - 1) \
+ >> ilog2(BITS_PER_LONG))
+
+struct ipmmu_pmb_data {
+ struct ipmmu_pmb_priv *priv;
+ struct ipmmu_pmb_info info;
+ struct pmb_tile_info tile;
+ unsigned long handle;
+ int index;
+};
+
+struct ipmmu_pmb_priv {
+ struct shmobile_ipmmu *ipmmu;
+ struct device *ipmmu_dev;
+ struct cdev cdev;
+ struct class *pmb_class;
+ dev_t pmb_dev;
+ unsigned long busy_pmbs;
+ struct mutex pmb_lock;
+ struct ipmmu_pmb_data pmbs[PMB_NR];
+ struct mutex alloc_lock;
+ unsigned long alloc_bitmaps[NR_BITMAPS];
+ int pmb_enabled;
+};
+
+static int valid_size(int size_mb)
+{
+ switch (size_mb) {
+ case 16:
+ case 64:
+ case 128:
+ case 512:
+ return 1;
+ }
+ return 0;
+
+}
+
+static unsigned long alloc_handle(struct ipmmu_pmb_priv *priv,
+ int size_mb)
+{
+ int i;
+ int idx;
+ unsigned long tmp_bitmap;
+ unsigned long alloc_mask;
+ unsigned long align_mask;
+ int alloc_bits;
+
+ if (!valid_size(size_mb))
+ return -1;
+
+ alloc_bits = NUM_BITS(size_mb << 20);
+ alloc_mask = alloc_bits < BITS_PER_LONG ?
+ (1 << alloc_bits) - 1 : -1;
+
+
+ align_mask = alloc_mask - 1;
+ for (i = BITS_PER_LONG >> 1; i >= alloc_bits; i = i >> 1)
+ align_mask = align_mask | (align_mask << i);
+
+ mutex_lock(&priv->alloc_lock);
+ for (i = 0; i < NR_BITMAPS; i++) {
+ tmp_bitmap = priv->alloc_bitmaps[i];
+ tmp_bitmap |= align_mask;
+ idx = 0;
+ while (idx < BITS_PER_LONG) {
+ idx = find_next_zero_bit(&tmp_bitmap, BITS_PER_LONG,
+ idx);
+ if (!((alloc_mask << idx) & priv->alloc_bitmaps[i]) ||
+ (idx == BITS_PER_LONG))
+ break;
+ idx++;
+ }
+ if (idx < BITS_PER_LONG)
+ break;
+ }
+ if (i == NR_BITMAPS) {
+ mutex_unlock(&priv->alloc_lock);
+ return 0;
+ }
+
+ priv->alloc_bitmaps[i] |= (alloc_mask << idx);
+ mutex_unlock(&priv->alloc_lock);
+
+ return PMB_START_ADDR + (i * BITS_PER_LONG + idx) * PMB_GRANULARITY;
+}
+
+void free_handle(struct ipmmu_pmb_priv *priv,
+ unsigned long handle,
+ int size_mb)
+{
+ int idx;
+ unsigned long offset;
+ unsigned long alloc_bits;
+ unsigned long alloc_mask;
+
+ alloc_bits = NUM_BITS(size_mb << 20);
+ alloc_mask = alloc_bits < BITS_PER_LONG ?
+ (1 << alloc_bits) - 1 : -1;
+ offset = handle - PMB_START_ADDR;
+ offset /= PMB_GRANULARITY;
+ idx = offset & (BITS_PER_LONG - 1);
+ offset = offset / BITS_PER_LONG;
+ mutex_lock(&priv->alloc_lock);
+ priv->alloc_bitmaps[offset] &= ~(alloc_mask << idx);
+ mutex_unlock(&priv->alloc_lock);
+}
+
+static int set_pmb(struct ipmmu_pmb_data *data,
+ struct ipmmu_pmb_info *info)
+{
+ struct ipmmu_pmb_priv *priv = data->priv;
+ unsigned long data_mask;
+ int err;
+
+ if (!info->enabled) {
+ if (data->handle) {
+ free_handle(priv, data->handle,
+ data->info.size_mb);
+ data->handle = 0;
+ }
+ data->info = *info;
+ ipmmu_pmb_set_data(priv->ipmmu, data->index, NULL, NULL);
+ ipmmu_pmb_set_addr(priv->ipmmu, data->index, 0, 0);
+ ipmmu_tlb_flush(priv->ipmmu);
+ return 0;
+ }
+
+ if (data->info.enabled) {
+ err = -EBUSY;
+ goto err_out;
+ }
+
+ data_mask = ~((info->size_mb) - 1);
+
+ if (info->paddr & ~(data_mask)) {
+ err = -EINVAL;
+ goto err_out;
+ }
+
+ data->handle = alloc_handle(priv, info->size_mb);
+
+ if (!data->handle) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ data->info = *info;
+
+ ipmmu_pmb_set_addr(priv->ipmmu, data->index, data->handle, 1);
+ ipmmu_pmb_set_data(priv->ipmmu, data->index, &data->info,
+ &data->tile);
+
+ if (!data->priv->pmb_enabled) {
+ ipmmu_pmb_enable(priv->ipmmu, 1);
+ data->priv->pmb_enabled = 1;
+ }
+
+ ipmmu_tlb_flush(priv->ipmmu);
+
+ return 0;
+
+err_out:
+ info->enabled = 0;
+ return err;
+}
+
+static int set_tile(struct ipmmu_pmb_data *data,
+ struct pmb_tile_info *tile)
+{
+ struct ipmmu_pmb_priv *priv = data->priv;
+ data->tile = *tile;
+ return ipmmu_pmb_set_data(priv->ipmmu, data->index, &data->info,
+ &data->tile);
+}
+
+static int ipmmu_pmb_open(struct inode *inode, struct file *filp)
+{
+ struct ipmmu_pmb_priv *priv;
+ int idx;
+ priv = container_of(inode->i_cdev, struct ipmmu_pmb_priv,
+ cdev);
+
+ mutex_lock(&priv->pmb_lock);
+ idx = find_first_zero_bit(&priv->busy_pmbs, PMB_NR);
+ if (idx == PMB_NR)
+ return -EBUSY;
+
+ __set_bit(idx, &priv->busy_pmbs);
+ mutex_unlock(&priv->pmb_lock);
+ priv->pmbs[idx].index = idx;
+ priv->pmbs[idx].priv = priv;
+ filp->private_data = &priv->pmbs[idx];
+ return 0;
+}
+
+static int ipmmu_pmb_release(struct inode *inode, struct file *filp)
+{
+ struct ipmmu_pmb_data *pmb;
+ pmb = filp->private_data;
+ if (pmb->info.enabled) {
+ pmb->info.enabled = 0;
+ set_pmb(pmb, &pmb->info);
+ }
+
+ mutex_lock(&pmb->priv->pmb_lock);
+ __clear_bit(pmb->index, &pmb->priv->busy_pmbs);
+ mutex_unlock(&pmb->priv->pmb_lock);
+ return 0;
+}
+
+static long ipmmu_pmb_ioctl(struct file *filp, unsigned int cmd_in,
+ unsigned long arg)
+{
+ struct ipmmu_pmb_data *pmb;
+ struct ipmmu_pmb_info user_set;
+ struct pmb_tile_info user_tile;
+ long ret = -EINVAL;
+ pmb = filp->private_data;
+ switch (cmd_in) {
+ case IPMMU_GET_PMB:
+ ret = copy_to_user((char *)arg, &pmb->info, sizeof(pmb->info));
+ break;
+ case IPMMU_SET_PMB:
+ ret = copy_from_user(&user_set, (char *)arg, sizeof(user_set));
+ if (ret)
+ break;
+ ret = set_pmb(pmb, &user_set);
+ if (!ret)
+ pmb->info = user_set;
+ break;
+ case IPMMU_GET_PMB_HANDLE:
+ ret = copy_to_user((char *)arg, &pmb->handle,
+ sizeof(pmb->handle));
+ break;
+ case IPMMU_GET_PMB_TL:
+ ret = copy_to_user((char *)arg, &pmb->tile, sizeof(pmb->tile));
+ break;
+ case IPMMU_SET_PMB_TL:
+ ret = copy_from_user(&user_tile, (char *)arg,
+ sizeof(user_tile));
+ if (ret)
+ break;
+ ret = set_tile(pmb, &user_tile);
+ if (!ret)
+ pmb->tile = user_tile;
+ break;
+ }
+ return ret;
+}
+
+static const struct file_operations ipmmu_pmb_fops = {
+ .owner = THIS_MODULE,
+ .open = ipmmu_pmb_open,
+ .release = ipmmu_pmb_release,
+ .unlocked_ioctl = ipmmu_pmb_ioctl,
+};
+
+void ipmmu_pmb_deinit(void *arg)
+{
+ struct ipmmu_pmb_priv *priv = arg;
+
+ if (!priv || IS_ERR(priv))
+ return;
+
+ cdev_del(&priv->cdev);
+ device_destroy(priv->pmb_class, priv->pmb_dev);
+ unregister_chrdev_region(priv->pmb_dev, 1);
+ class_destroy(priv->pmb_class);
+ kfree(priv);
+}
+
+void *ipmmu_pmb_init(struct shmobile_ipmmu *ipmmu)
+{
+ int err = -ENOENT;
+ struct ipmmu_pmb_priv *priv;
+
+ priv = kzalloc(sizeof(struct ipmmu_pmb_priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(ipmmu->dev, "cannot allocate device data\n");
+ return ERR_PTR(-ENOMEM);
+ }
+
+ priv->ipmmu = ipmmu;
+ priv->ipmmu_dev = ipmmu->dev;
+
+ mutex_init(&priv->pmb_lock);
+ mutex_init(&priv->alloc_lock);
+
+ priv->pmb_class = class_create(THIS_MODULE, "ipmmu-pmb");
+ if (!priv->pmb_class)
+ goto free_priv;
+
+ err = alloc_chrdev_region(&priv->pmb_dev, 0, 1, PMB_DEVICE_NAME);
+ if (err) {
+ dev_err(ipmmu->dev, "cannot allocate device num\n");
+ goto destroy_class;
+ }
+
+ if (!device_create(priv->pmb_class, ipmmu->dev, priv->pmb_dev, priv,
+ "pmb"))
+ goto unregister_region;
+
+ cdev_init(&priv->cdev, &ipmmu_pmb_fops);
+ priv->cdev.owner = THIS_MODULE;
+ priv->cdev.ops = &ipmmu_pmb_fops;
+ err = cdev_add(&priv->cdev, priv->pmb_dev, 1);
+ if (err) {
+ dev_err(ipmmu->dev, "cannot add ipmmu_pmb device\n");
+ goto destroy_device;
+ }
+
+ return priv;
+
+destroy_device:
+ device_destroy(priv->pmb_class, priv->pmb_dev);
+unregister_region:
+ unregister_chrdev_region(priv->pmb_dev, 1);
+destroy_class:
+ class_destroy(priv->pmb_class);
+free_priv:
+ kfree(priv);
+ return ERR_PTR(err);
+}
diff --git a/include/linux/ipmmu.h b/include/linux/ipmmu.h
new file mode 100644
index 0000000..4d31122
--- /dev/null
+++ b/include/linux/ipmmu.h
@@ -0,0 +1,29 @@
+#ifndef __LINUX_IPMMU_PMB_H__
+#define __LINUX_IPMMU_PMB_H__
+
+struct ipmmu_pmb_info {
+ int enabled;
+ unsigned long paddr;
+ int size_mb;
+};
+
+struct pmb_tile_info {
+ int tile_width;
+ int tile_height;
+ int buffer_pitch;
+ int enabled;
+};
+
+/* IOCTL commands. */
+
+#define IPMMU_SET_PMB _IOW('S', 37, struct ipmmu_pmb_phys *)
+#define IPMMU_GET_PMB _IOR('S', 38, struct ipmmu_pmb_phys *)
+#define IPMMU_GET_PMB_HANDLE _IOR('S', 39, unsigned long *)
+#define IPMMU_SET_PMB_TL _IOW('S', 41, struct ipmmu_pmb_tile_info *)
+#define IPMMU_GET_PMB_TL _IOR('S', 42, struct ipmmu_pmb_tile_info *)
+
+#ifdef __kernel
+
+#endif /* __kernel */
+
+#endif /* __LINUX_IPMMU_PMB_H__ */
--
1.7.5.4
^ permalink raw reply related
* [PATCH 0/3] Add device tree support for NAND flash in am335x-evm
From: Philip Avinash @ 2013-01-18 6:41 UTC (permalink / raw)
To: linux-arm-kernel
This patch series adds device tree support for NAND flash in am335x-evm.
Also ELM node is populated in device tree and been used for BCH error
correction in NAND flash part. Also this patch series ensures RBL ecc
layout maintained in Linux kernel with BCH8 ecc scheme.
This patch series based on [1] and depends on [2] & [3].
1. http://git.kernel.org/?p=linux/kernel/git/bcousson/linux-omap-dt.git;a=tree;h=refs/heads/for_3.9/dts;hb=refs/heads/for_3.9/dts
2. OMAP GPMC DT bindings
http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap.git;a=shortlog;h=refs/heads/omap-for-v3.9/gpmc
3. mtd: nand: OMAP: ELM error correction support for BCH ecc
http://git.infradead.org/users/dedekind/l2-mtd-2.6.git/shortlog/refs/heads/master
Philip Avinash (1):
ARM: dts: AM33XX: Add NAND flash device tree data to am335x-evm
Philip, Avinash (2):
ARM: dts: AM33XX: Add ELM node
ARM: dts: AM33XX: Add GPMC node
arch/arm/boot/dts/am335x-evm.dts | 93 +++++++++++++++++++++++++++++++++++++-
arch/arm/boot/dts/am33xx.dtsi | 18 ++++++++
2 files changed, 110 insertions(+), 1 deletion(-)
--
1.7.9.5
^ permalink raw reply
* [PATCH 1/3] ARM: dts: AM33XX: Add ELM node
From: Philip Avinash @ 2013-01-18 6:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358491295-4022-1-git-send-email-avinashphilip@ti.com>
From: "Philip, Avinash" <avinashphilip@ti.com>
Add ELM data node to AM33XX device tree file.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
---
arch/arm/boot/dts/am33xx.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index c2f14e8..eaef5e7 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -385,5 +385,13 @@
mac-address = [ 00 00 00 00 00 00 ];
};
};
+
+ elm: elm at 48080000 {
+ compatible = "ti,am33xx-elm";
+ reg = <0x48080000 0x2000>;
+ interrupts = <4>;
+ ti,hwmods = "elm";
+ status = "disabled";
+ };
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/3] ARM: dts: AM33XX: Add GPMC node
From: Philip Avinash @ 2013-01-18 6:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358491295-4022-1-git-send-email-avinashphilip@ti.com>
From: "Philip, Avinash" <avinashphilip@ti.com>
Add GPMC data node to AM33XX device tree file.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
---
arch/arm/boot/dts/am33xx.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index eaef5e7..f4209d8 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -393,5 +393,17 @@
ti,hwmods = "elm";
status = "disabled";
};
+
+ gpmc: gpmc at 50000000 {
+ compatible = "ti,am3352-gpmc";
+ ti,hwmods = "gpmc";
+ reg = <0x50000000 0x2000>;
+ interrupts = <100>;
+ num-cs = <8>;
+ num-waitpins = <2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to am335x-evm
From: Philip Avinash @ 2013-01-18 6:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358491295-4022-1-git-send-email-avinashphilip@ti.com>
NAND flash connected in am335x-evm on GPMC controller. This patch adds
device tree node in am335x-evm with GPMC controller timing for NAND flash
interface, NAND partition table, ECC scheme, elm handle id, pin-mux
setup.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
---
arch/arm/boot/dts/am335x-evm.dts | 98 +++++++++++++++++++++++++++++++++++++-
1 file changed, 97 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d649644..1c6b1a8 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -26,7 +26,8 @@
am33xx_pinmux: pinmux at 44e10800 {
pinctrl-names = "default";
- pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
+ pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0
+ &nandflash_pins_s0>;
matrix_keypad_s0: matrix_keypad_s0 {
pinctrl-single,pins = <
@@ -44,6 +45,26 @@
0x154 0x27 /* spi0_d0.gpio0_3, INPUT | MODE7 */
>;
};
+
+ nandflash_pins_s0: nandflash_pins_s0 {
+ pinctrl-single,pins = <
+ 0x0 0x30 /* gpmc_ad0.gpmc_ad0, INPUT | PULLUP | MODE0 */
+ 0x4 0x30 /* gpmc_ad1.gpmc_ad1, INPUT | PULLUP | MODE0 */
+ 0x8 0x30 /* gpmc_ad2.gpmc_ad2, INPUT | PULLUP | MODE0 */
+ 0xc 0x30 /* gpmc_ad3.gpmc_ad3, INPUT | PULLUP | MODE0 */
+ 0x10 0x30 /* gpmc_ad4.gpmc_ad4, INPUT | PULLUP | MODE0 */
+ 0x14 0x30 /* gpmc_ad5.gpmc_ad5, INPUT | PULLUP | MODE0 */
+ 0x18 0x30 /* gpmc_ad6.gpmc_ad6, INPUT | PULLUP | MODE0 */
+ 0x1c 0x30 /* gpmc_ad7.gpmc_ad7, INPUT | PULLUP | MODE0 */
+ 0x70 0x30 /* gpmc_wait0.gpmc_wait0, INPUT | PULLUP | MODE0 */
+ 0x74 0x37 /* gpmc_wpn.gpio0_30, INPUT | PULLUP | MODE7 */
+ 0x7c 0x8 /* gpmc_csn0.gpmc_csn0, PULL DISA */
+ 0x90 0x8 /* gpmc_advn_ale.gpmc_advn_ale, PULL DISA */
+ 0x94 0x8 /* gpmc_oen_ren.gpmc_oen_ren, PULL DISA */
+ 0x98 0x8 /* gpmc_wen.gpmc_wen, PULL DISA */
+ 0x9c 0x8 /* gpmc_be0n_cle.gpmc_be0n_cle, PULL DISA */
+ >;
+ };
};
ocp {
@@ -102,6 +123,81 @@
reg = <0x48>;
};
};
+
+ elm: elm at 48080000 {
+ status = "okay";
+ };
+
+ gpmc: gpmc at 50000000 {
+ status = "okay";
+ ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
+
+ nand at 0,0 {
+ reg = <0 0 0>; /* CS0, offset 0 */
+ nand-bus-width = <8>;
+ ti,nand-ecc-opt = "bch8";
+
+ gpmc,sync-clk = <0>;
+ gpmc,cs-on = <0>;
+ gpmc,cs-rd-off = <44>;
+ gpmc,cs-wr-off = <44>;
+ gpmc,adv-on = <6>;
+ gpmc,adv-rd-off = <34>;
+ gpmc,adv-wr-off = <44>;
+ gpmc,we-off = <40>;
+ gpmc,oe-off = <54>;
+ gpmc,access = <64>;
+ gpmc,rd-cycle = <82>;
+ gpmc,wr-cycle = <82>;
+ gpmc,wr-access = <40>;
+ gpmc,wr-data-mux-bus = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ elm_id = <&elm>;
+
+ /* MTD partition table */
+ partition at 0 {
+ label = "SPL1";
+ reg = <0x00000000 0x000020000>;
+ };
+
+ partition at 1 {
+ label = "SPL2";
+ reg = <0x00020000 0x00020000>;
+ };
+
+ partition at 2 {
+ label = "SPL3";
+ reg = <0x00040000 0x00020000>;
+ };
+
+ partition at 3 {
+ label = "SPL4";
+ reg = <0x00060000 0x00020000>;
+ };
+
+ partition at 4 {
+ label = "U-boot";
+ reg = <0x00080000 0x001e0000>;
+ };
+
+ partition at 5 {
+ label = "environment";
+ reg = <0x00260000 0x00020000>;
+ };
+
+ partition at 6 {
+ label = "Kernel";
+ reg = <0x00280000 0x00500000>;
+ };
+
+ partition at 7 {
+ label = "File-System";
+ reg = <0x00780000 0x0F880000>;
+ };
+ };
+ };
};
vbat: fixedregulator at 0 {
--
1.7.9.5
^ permalink raw reply related
* [PATCH] ARM: shmobile: sh73a0: Use generic irqchip_init()
From: Thierry Reding @ 2013-01-18 6:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130118000517.GI16740@verge.net.au>
On Fri, Jan 18, 2013 at 09:05:17AM +0900, Simon Horman wrote:
> On Thu, Jan 17, 2013 at 01:00:13PM +0100, Thierry Reding wrote:
> > The asm/hardware/gic.h header does no longer exist and the corresponding
> > functionality was moved to linux/irqchip.h and linux/irqchip/arm-gic.h
> > respectively. gic_handle_irq() and of_irq_init() are no longer available
> > either and have been replaced by irqchip_init().
> >
> > Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
>
> Thanks.
>
> Due to the hairy upstream requirements of the arm-soc tree
> I believe this patch needs to be split in two. A 'board' patch
> for board-kzm9g-reference.c. And an 'soc' patch for the
> remaining portions.
>
> I'm happy to split the patch myself or for you to do so.
I'll resend a split patch shortly.
Thierry
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130118/1080fbf2/attachment.sig>
^ permalink raw reply
* [PATCH v2 1/2] ARM: shmobile: sh73a0: Use generic irqchip_init()
From: Thierry Reding @ 2013-01-18 7:16 UTC (permalink / raw)
To: linux-arm-kernel
The asm/hardware/gic.h header does no longer exist and the corresponding
functionality was moved to linux/irqchip.h and linux/irqchip/arm-gic.h
respectively. gic_handle_irq() and of_irq_init() are no longer available
either and have been replaced by irqchip_init().
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
---
Changes in v2:
- split off kzm9g board changes into a separate patch
arch/arm/mach-shmobile/intc-sh73a0.c | 9 ++-------
arch/arm/mach-shmobile/setup-sh73a0.c | 2 --
2 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index fc7c8da..91faba6 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -21,9 +21,9 @@
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/irq.h>
-#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
+#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic.h>
#include <mach/intc.h>
#include <mach/irqs.h>
@@ -462,14 +462,9 @@ void __init sh73a0_init_irq(void)
}
#ifdef CONFIG_OF
-static const struct of_device_id irq_of_match[] __initconst = {
- { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
- { },
-};
-
void __init sh73a0_init_irq_dt(void)
{
- of_irq_init(irq_of_match);
+ irqchip_init();
gic_arch_extn.irq_set_wake = sh73a0_set_wake;
}
#endif
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index abf1eb0..2ecd668 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -36,7 +36,6 @@
#include <mach/irqs.h>
#include <mach/sh73a0.h>
#include <mach/common.h>
-#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
@@ -892,7 +891,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
.init_early = sh73a0_add_early_devices_dt,
.nr_irqs = NR_IRQS_LEGACY,
.init_irq = sh73a0_init_irq_dt,
- .handle_irq = gic_handle_irq,
.init_machine = sh73a0_add_standard_devices_dt,
.init_time = shmobile_timer_init,
.dt_compat = sh73a0_boards_compat_dt,
--
1.8.1.1
^ permalink raw reply related
* [PATCH v2 2/2] ARM: shmobile: kzm9g: Don't use gic_handle_irq()
From: Thierry Reding @ 2013-01-18 7:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358493373-28722-1-git-send-email-thierry.reding@avionic-design.de>
This function is no longer publicly available. However, the sh73a0 setup
code now uses the generic irqchip infrastructure which will implicitly
set the IRQ handler, so it's fine to drop its initialization from the
machine definition.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
---
Changes in v2:
- new patch with kzm9g board changes
arch/arm/mach-shmobile/board-kzm9g-reference.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index 04e9ae5..08c95dd 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -90,7 +90,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
.init_early = sh73a0_add_early_devices_dt,
.nr_irqs = NR_IRQS_LEGACY,
.init_irq = sh73a0_init_irq_dt,
- .handle_irq = gic_handle_irq,
.init_machine = kzm_init,
.init_late = shmobile_init_late,
.init_time = shmobile_timer_init,
--
1.8.1.1
^ permalink raw reply related
* [PATCH 0/9] ARM: OMAP2+: AM33XX: Misc fixes/updates
From: Vaibhav Bedia @ 2013-01-18 7:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
The following patches were earlier posted as part the AM33XX
suspend-resume support series [1]. Based on the suggestion
from Santosh Shilimkar <santosh.shilimkar@ti.com> i have split
out the changes which update the various data files related
to AM33XX support.
These patches apply on top of v3.8-rc3
Regards,
Vaibhav
[1] http://marc.info/?l=linux-arm-kernel&m=135698501821074&w=2
Vaibhav Bedia (9):
ARM: OMAP2+: AM33XX: CM: Get rid of unncessary header inclusions
ARM: OMAP2+: AM33XX: CM/PRM: Use __ASSEMBLER__ macros in header files
ARM: OMAP2+: AM33XX: hwmod: Register OCMC RAM hwmod
ARM: OMAP2+: AM33XX: hwmod: Update TPTC0 hwmod with the right flags
ARM: OMAP2+: AM33XX: hwmod: Fixup cpgmac0 hwmod entry
ARM: OMAP2+: AM33XX: hwmod: Update the WKUP-M3 hwmod with reset
status bit
ARM: OMAP2+: AM33XX: Update the hardreset API
ARM: DTS: AM33XX: Add nodes for OCMC RAM and WKUP-M3
ARM: OMAP2+: AM33XX: control: Add some control module registers and
APIs
arch/arm/boot/dts/am33xx.dtsi | 11 ++++++
arch/arm/mach-omap2/cm33xx.h | 9 ++---
arch/arm/mach-omap2/control.c | 20 +++++++++++
arch/arm/mach-omap2/control.h | 41 +++++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod.c | 5 +--
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 50 ++++++++++++++++------------
arch/arm/mach-omap2/prm33xx.c | 11 ++++--
arch/arm/mach-omap2/prm33xx.h | 4 ++-
8 files changed, 115 insertions(+), 36 deletions(-)
^ permalink raw reply
* [PATCH 1/9] ARM: OMAP2+: AM33XX: CM: Get rid of unncessary header inclusions
From: Vaibhav Bedia @ 2013-01-18 7:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358493569-17142-1-git-send-email-vaibhav.bedia@ti.com>
Some of the included header files are not needed so
remove them.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
Change from RFC version:
No change
arch/arm/mach-omap2/cm33xx.h | 7 +------
1 files changed, 1 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 5fa0b62..8009e13 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -17,16 +17,11 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
#include "common.h"
#include "cm.h"
#include "cm-regbits-33xx.h"
-#include "cm33xx.h"
+#include "iomap.h"
/* CM base address */
#define AM33XX_CM_BASE 0x44e00000
--
1.7.0.4
^ permalink raw reply related
* [PATCH 2/9] ARM: OMAP2+: AM33XX: CM/PRM: Use __ASSEMBLER__ macros in header files
From: Vaibhav Bedia @ 2013-01-18 7:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358493569-17142-1-git-send-email-vaibhav.bedia@ti.com>
This is necessary to ensure that macros declared here can
be reused from assembly files.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
Change from RFC version:
Get rid of extra lines
arch/arm/mach-omap2/cm33xx.h | 2 ++
arch/arm/mach-omap2/prm33xx.h | 2 ++
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 8009e13..64f4baf 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -376,6 +376,7 @@
#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
+#ifndef __ASSEMBLER__
extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
@@ -412,4 +413,5 @@ static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
}
#endif
+#endif /* ASSEMBLER */
#endif
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 3f25c56..1c40373 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -117,6 +117,7 @@
#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004
#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
+#ifndef __ASSEMBLER__
extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
@@ -126,4 +127,5 @@ extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
u16 rstctrl_offs, u16 rstst_offs);
+#endif /* ASSEMBLER */
#endif
--
1.7.0.4
^ permalink raw reply related
* [PATCH 3/9] ARM: OMAP2+: AM33XX: hwmod: Register OCMC RAM hwmod
From: Vaibhav Bedia @ 2013-01-18 7:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358493569-17142-1-git-send-email-vaibhav.bedia@ti.com>
OCMC RAM lies in the PER power domain and this memory
support retention.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
Change from RFC version:
No change
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 47 ++++++++++++++++------------
1 files changed, 27 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 646c14d..8280f11 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -414,7 +414,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
* - cEFUSE (doesn't fall under any ocp_if)
* - clkdiv32k
* - debugss
- * - ocmc ram
* - ocp watch point
* - aes0
* - sha0
@@ -481,25 +480,6 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
},
};
-/* ocmcram */
-static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
- .name = "ocmcram",
-};
-
-static struct omap_hwmod am33xx_ocmcram_hwmod = {
- .name = "ocmcram",
- .class = &am33xx_ocmcram_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
/* ocpwp */
static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
.name = "ocpwp",
@@ -570,6 +550,25 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
#endif
+/* ocmcram */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+ .name = "ocmcram",
+};
+
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+ .name = "ocmcram",
+ .class = &am33xx_ocmcram_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "l3_gclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
/* 'smartreflex' class */
static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
.name = "smartreflex",
@@ -3328,6 +3327,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
.flags = OCPIF_SWSUP_IDLE,
};
+/* l3 main -> ocmc */
+static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_ocmcram_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_fw__emif_fw,
&am33xx_l3_main__emif,
@@ -3398,6 +3404,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__tptc0,
&am33xx_l3_main__tptc1,
&am33xx_l3_main__tptc2,
+ &am33xx_l3_main__ocmc,
&am33xx_l3_s__usbss,
&am33xx_l4_hs__cpgmac0,
&am33xx_cpgmac0__mdio,
--
1.7.0.4
^ permalink raw reply related
* [PATCH 4/9] ARM: OMAP2+: AM33XX: hwmod: Update TPTC0 hwmod with the right flags
From: Vaibhav Bedia @ 2013-01-18 7:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358493569-17142-1-git-send-email-vaibhav.bedia@ti.com>
Third Party Transfer Controller (TPTC0) needs to be idled and
put to standby under SW control. Add the appropriate flags in
the TPTC0 hwmod entry.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
Change from RFC version:
Clarify TPTC in the changelog
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 8280f11..f2f408c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -1823,6 +1823,7 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
.class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_tptc0_irqs,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
--
1.7.0.4
^ permalink raw reply related
* [PATCH 5/9] ARM: OMAP2+: AM33XX: hwmod: Fixup cpgmac0 hwmod entry
From: Vaibhav Bedia @ 2013-01-18 7:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358493569-17142-1-git-send-email-vaibhav.bedia@ti.com>
The current HWMOD code expects the memory region with
the IP's SYSCONFIG register to be marked with ADDR_TYPE_RT
flag.
CPGMAC0 hwmod entry specifies two memory regions and marks
both with the flag ADDR_TYPE_RT although only the 2nd region
has the SYSCONFIG register. This leads to the HWMOD code
accessing the wrong memory address for idle and standby
operations. Fix this by removing the ADDR_TYPE_RT flag from
the 1st memory region in CPGMAC0 hwmod entry.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
---
Change from RFC version:
No change
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index f2f408c..34a67e4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -2496,7 +2496,6 @@ static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
{
.pa_start = 0x4a100000,
.pa_end = 0x4a100000 + SZ_2K - 1,
- .flags = ADDR_TYPE_RT,
},
/* cpsw wr */
{
--
1.7.0.4
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox