* [PATCH 3/3] arm: sunxi: Add useful information about sunxi clocks
From: Emilio López @ 2013-01-22 6:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358835176-7197-1-git-send-email-emilio@elopez.com.ar>
This patch contains useful bits of information about the sunxi clocks
that may help and/or be interesting for current and future developers.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
Documentation/arm/sunxi/clocks.txt | 56 ++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 Documentation/arm/sunxi/clocks.txt
diff --git a/Documentation/arm/sunxi/clocks.txt b/Documentation/arm/sunxi/clocks.txt
new file mode 100644
index 0000000..e09a88a
--- /dev/null
+++ b/Documentation/arm/sunxi/clocks.txt
@@ -0,0 +1,56 @@
+Frequently asked questions about the sunxi clock system
+=======================================================
+
+This document contains useful bits of information that people tend to ask
+about the sunxi clock system, as well as accompanying ASCII art when adequate.
+
+Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
+ system?
+
+A: The 24MHz oscillator allows gating to save power. Indeed, if gated
+ carelessly the system would stop functioning, but with the right
+ steps, one can gate it and keep the system running. Consider this
+ simplified suspend example:
+
+ While the system is operational, you would see something like
+
+ 24MHz 32kHz
+ |
+ PLL1
+ \
+ \_ CPU Mux
+ |
+ [CPU]
+
+ When you are about to suspend, you switch the CPU Mux to the 32kHz
+ oscillator:
+
+ 24Mhz 32kHz
+ | |
+ PLL1 |
+ /
+ CPU Mux _/
+ |
+ [CPU]
+
+ Finally you can gate the main oscillator
+
+ 32kHz
+ |
+ |
+ /
+ CPU Mux _/
+ |
+ [CPU]
+
+Q: Were can I learn more about the sunxi clocks?
+
+A: The linux-sunxi wiki contains a page documenting the clock registers,
+ you can find it at
+
+ http://linux-sunxi.org/A10/CCM
+
+ The authoritative source for information at this time is the ccmu driver
+ released by Allwinner, you can find it at
+
+ https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu
--
1.8.1.1
^ permalink raw reply related
* [PATCH 2/3] arm: sunxi: Add clock definitions for the new clock driver
From: Emilio López @ 2013-01-22 6:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358835176-7197-1-git-send-email-emilio@elopez.com.ar>
This introduces proper clock definitions on sunxi.dtsi, to be used
with the new clock driver for sunxi.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
arch/arm/boot/dts/sunxi.dtsi | 55 +++++++++++++++++++++++++++++++++++++++-----
1 file changed, 49 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
index 8bbc2bf..e2cef13 100644
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ b/arch/arm/boot/dts/sunxi.dtsi
@@ -24,13 +24,56 @@
clocks {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+ ranges;
- osc: oscillator {
+ osc24M: osc24M at 01c20050 {
#clock-cells = <0>;
- compatible = "fixed-clock";
+ compatible = "allwinner,sunxi-osc-clk";
+ reg = <0x01c20050 0x4>;
clock-frequency = <24000000>;
};
+
+ osc32k: osc32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ pll1: pll1 at 01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ };
+
+ cpu: cpu at 01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-cpu-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>;
+ };
+
+ axi: axi at 01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-axi-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&cpu>;
+ };
+
+ ahb: ahb at 01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-ahb-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&axi>;
+ };
+
+ apb0: apb0 at 01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb>;
+ };
};
soc {
@@ -44,7 +87,7 @@
compatible = "allwinner,sunxi-timer";
reg = <0x01c20c00 0x90>;
interrupts = <22>;
- clocks = <&osc>;
+ clocks = <&osc24M>;
};
wdt: watchdog at 01c20c90 {
@@ -64,7 +107,7 @@
reg = <0x01c28000 0x400>;
interrupts = <1>;
reg-shift = <2>;
- clock-frequency = <24000000>;
+ clocks = <&osc24M>;
status = "disabled";
};
@@ -73,7 +116,7 @@
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
- clock-frequency = <24000000>;
+ clocks = <&osc24M>;
status = "disabled";
};
};
--
1.8.1.1
^ permalink raw reply related
* [PATCH 1/3] clk: arm: sunxi: Add a new clock driver for sunxi SOCs
From: Emilio López @ 2013-01-22 6:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358835176-7197-1-git-send-email-emilio@elopez.com.ar>
This commit implements the base CPU clocks for sunxi devices. It has
been tested using a slightly modified cpufreq driver from the
linux-sunxi 3.0 tree.
Additionally, document the new bindings introduced by this patch, and drop
the (now unused) old sunxi clock driver.
Idling:
/ # find /sys/kernel/debug/clk -name clk_rate -print -exec cat {} \;
/sys/kernel/debug/clk/osc24M/pll1/cpu/axi/ahb/apb0/clk_rate
30000000
/sys/kernel/debug/clk/osc24M/pll1/cpu/axi/ahb/clk_rate
60000000
/sys/kernel/debug/clk/osc24M/pll1/cpu/axi/clk_rate
60000000
/sys/kernel/debug/clk/osc24M/pll1/cpu/clk_rate
60000000
/sys/kernel/debug/clk/osc24M/pll1/clk_rate
60000000
/sys/kernel/debug/clk/osc24M/clk_rate
24000000
/sys/kernel/debug/clk/osc32k/clk_rate
32768
After "yes >/dev/null &":
/ # find /sys/kernel/debug/clk -name clk_rate -print -exec cat {} \;
/sys/kernel/debug/clk/osc24M/pll1/cpu/axi/ahb/apb0/clk_rate
84000000
/sys/kernel/debug/clk/osc24M/pll1/cpu/axi/ahb/clk_rate
168000000
/sys/kernel/debug/clk/osc24M/pll1/cpu/axi/clk_rate
336000000
/sys/kernel/debug/clk/osc24M/pll1/cpu/clk_rate
1008000000
/sys/kernel/debug/clk/osc24M/pll1/clk_rate
1008000000
/sys/kernel/debug/clk/osc24M/clk_rate
24000000
/sys/kernel/debug/clk/osc32k/clk_rate
32768
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 47 ++++
drivers/clk/Makefile | 2 +-
drivers/clk/clk-sunxi.c | 30 ---
drivers/clk/sunxi/Makefile | 5 +
drivers/clk/sunxi/clk-factors.c | 175 ++++++++++++++
drivers/clk/sunxi/clk-factors.h | 25 ++
drivers/clk/sunxi/clk-fixed-gate.c | 152 +++++++++++++
drivers/clk/sunxi/clk-fixed-gate.h | 13 ++
drivers/clk/sunxi/clk-sunxi.c | 265 ++++++++++++++++++++++
9 files changed, 683 insertions(+), 31 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/sunxi.txt
delete mode 100644 drivers/clk/clk-sunxi.c
create mode 100644 drivers/clk/sunxi/Makefile
create mode 100644 drivers/clk/sunxi/clk-factors.c
create mode 100644 drivers/clk/sunxi/clk-factors.h
create mode 100644 drivers/clk/sunxi/clk-fixed-gate.c
create mode 100644 drivers/clk/sunxi/clk-fixed-gate.h
create mode 100644 drivers/clk/sunxi/clk-sunxi.c
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
new file mode 100644
index 0000000..446c5ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -0,0 +1,47 @@
+Device Tree Clock bindings for arch-sunxi
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of the following:
+ "allwinner,sunxi-osc-clk" - for a gatable oscillator
+ "allwinner,sunxi-pll1-clk" - for the main PLL clock
+ "allwinner,sunxi-cpu-clk" - for the CPU multiplexer clock
+ "allwinner,sunxi-axi-clk" - for the sunxi AXI clock
+ "allwinner,sunxi-ahb-clk" - for the sunxi AHB clock
+ "allwinner,sunxi-apb0-clk" - for the sunxi APB0 clock
+
+Required properties for all clocks:
+- reg : shall be the control register address for the clock.
+- clocks : shall be the input parent clock(s) phandle for the clock, except for
+ the root gatable oscillator clock where it is not present
+- #clock-cells : from common clock binding; shall be set to 0.
+
+Additionally, the gatable oscillator clock requires:
+- clock-frequency : shall be the frequency of the oscillator.
+
+
+For example:
+
+osc24M: osc24M {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-osc-clk";
+ reg = <0x01c20050 0x4>;
+ clock-frequency = <24000000>;
+};
+
+pll1: pll1 at 01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+};
+
+cpu: cpu at 01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sunxi-cpu-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>;
+};
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ee90e87..129afed 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -20,7 +20,7 @@ endif
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
-obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o
+obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
# Chip specific
diff --git a/drivers/clk/clk-sunxi.c b/drivers/clk/clk-sunxi.c
deleted file mode 100644
index 0e831b5..0000000
--- a/drivers/clk/clk-sunxi.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright 2012 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-#include <linux/clk/sunxi.h>
-#include <linux/of.h>
-
-static const __initconst struct of_device_id clk_match[] = {
- { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
- {}
-};
-
-void __init sunxi_init_clocks(void)
-{
- of_clk_init(clk_match);
-}
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
new file mode 100644
index 0000000..8e773be
--- /dev/null
+++ b/drivers/clk/sunxi/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for sunxi specific clk
+#
+
+obj-y += clk-sunxi.o clk-factors.o clk-fixed-gate.o
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
new file mode 100644
index 0000000..428b47d
--- /dev/null
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2013 Emilio L?pez <emilio@elopez.com.ar>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Adjustable factor-based clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+#include <linux/delay.h>
+
+#include "clk-factors.h"
+
+/*
+ * DOC: basic adjustable factor-based clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is adjustable.
+ * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
+ * parent - fixed parent. No clk_set_parent support
+ */
+
+struct clk_factors {
+ struct clk_hw hw;
+ void __iomem *reg;
+ struct clk_factors_config *config;
+ void (*get_factors) (u32 *rate, u8 *n, u8 *k, u8 *m, u8 *p);
+ spinlock_t *lock;
+};
+
+#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
+
+#define SETMASK(len, pos) (((-1U) >> (31-len)) << (pos))
+#define CLRMASK(len, pos) (~(SETMASK(len, pos)))
+#define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit))
+
+#define FACTOR_SET(bit, len, reg, val) \
+ (((reg) & CLRMASK(len, bit)) | (val << (bit)))
+
+static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u8 n, k, p, m;
+ u32 reg;
+ unsigned long rate;
+ struct clk_factors *factors = to_clk_factors(hw);
+ struct clk_factors_config *config = factors->config;
+
+ /* Fetch the register value */
+ reg = readl(factors->reg);
+
+ /* Get each individual factor */
+ n = FACTOR_GET(config->nshift, config->nwidth, reg);
+ k = FACTOR_GET(config->kshift, config->kwidth, reg);
+ m = FACTOR_GET(config->mshift, config->mwidth, reg);
+ p = FACTOR_GET(config->pshift, config->pwidth, reg);
+
+ /* Calculate the rate */
+ rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
+
+ return rate;
+}
+
+static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct clk_factors *factors = to_clk_factors(hw);
+ factors->get_factors((u32 *)&rate, NULL, NULL, NULL, NULL);
+
+ return rate;
+}
+
+static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u8 n, k, m, p;
+ u32 reg;
+ struct clk_factors *factors = to_clk_factors(hw);
+ struct clk_factors_config *config = factors->config;
+ unsigned long flags = 0;
+
+ factors->get_factors((u32 *)&rate, &n, &k, &m, &p);
+
+ if (factors->lock)
+ spin_lock_irqsave(factors->lock, flags);
+
+ /* Fetch the register value */
+ reg = readl(factors->reg);
+
+ /* Set up the new factors */
+ reg = FACTOR_SET(config->nshift, config->nwidth, reg, n);
+ reg = FACTOR_SET(config->kshift, config->kwidth, reg, k);
+ reg = FACTOR_SET(config->mshift, config->mwidth, reg, m);
+ reg = FACTOR_SET(config->pshift, config->pwidth, reg, p);
+
+ /* Apply them now */
+ writel(reg, factors->reg);
+
+ /* delay 500us so pll stabilizes */
+ __delay((rate >> 20) * 500 / 2);
+
+ if (factors->lock)
+ spin_unlock_irqrestore(factors->lock, flags);
+
+ return 0;
+}
+
+static const struct clk_ops clk_factors_ops = {
+ .recalc_rate = clk_factors_recalc_rate,
+ .round_rate = clk_factors_round_rate,
+ .set_rate = clk_factors_set_rate,
+};
+
+/**
+ * clk_register_factors - register a factors clock with
+ * the clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust factors
+ * @config: shift and width of factors n, k, m and p
+ * @get_factors: function to calculate the factors for a given frequency
+ * @lock: shared register lock for this clock
+ */
+struct clk *clk_register_factors(struct device *dev, const char *name,
+ const char *parent_name,
+ unsigned long flags, void __iomem *reg,
+ struct clk_factors_config *config,
+ void (*get_factors) (u32 *rate, u8 *n, u8 *k,
+ u8 *m, u8 *p),
+ spinlock_t *lock)
+{
+ struct clk_factors *factors;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ /* allocate the factors */
+ factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
+ if (!factors) {
+ pr_err("%s: could not allocate factors clk\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = name;
+ init.ops = &clk_factors_ops;
+ init.flags = flags;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ /* struct clk_factors assignments */
+ factors->reg = reg;
+ factors->config = config;
+ factors->lock = lock;
+ factors->hw.init = &init;
+ factors->get_factors = get_factors;
+
+ /* register the clock */
+ clk = clk_register(dev, &factors->hw);
+
+ if (IS_ERR(clk))
+ kfree(factors);
+
+ return clk;
+}
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
new file mode 100644
index 0000000..a24c889
--- /dev/null
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -0,0 +1,25 @@
+#ifndef __MACH_SUNXI_CLK_FACTORS_H
+#define __MACH_SUNXI_CLK_FACTORS_H
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+
+struct clk_factors_config {
+ u8 nshift;
+ u8 nwidth;
+ u8 kshift;
+ u8 kwidth;
+ u8 mshift;
+ u8 mwidth;
+ u8 pshift;
+ u8 pwidth;
+};
+
+struct clk *clk_register_factors(struct device *dev, const char *name,
+ const char *parent_name,
+ unsigned long flags, void __iomem *reg,
+ struct clk_factors_config *config,
+ void (*get_factors) (u32 *rate, u8 *n, u8 *k,
+ u8 *m, u8 *p),
+ spinlock_t *lock);
+#endif
diff --git a/drivers/clk/sunxi/clk-fixed-gate.c b/drivers/clk/sunxi/clk-fixed-gate.c
new file mode 100644
index 0000000..b16eda5
--- /dev/null
+++ b/drivers/clk/sunxi/clk-fixed-gate.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2013 Emilio L?pez <emilio@elopez.com.ar>
+ *
+ * Based on drivers/clk/clk-gate.c,
+ *
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Fixed rate, gated clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+#include "clk-fixed-gate.h"
+
+/**
+ * DOC: fixed rate clock which can gate and ungate it's ouput
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent is (un)prepared
+ * enable - clk_enable and clk_disable are functional & control gating
+ * rate - rate is always a fixed value. No clk_set_rate support
+ * parent - fixed parent. No clk_set_parent support
+ */
+
+struct clk_fixed_gate {
+ struct clk_hw hw;
+ u8 bit_idx;
+ u8 flags;
+ unsigned long fixed_rate;
+ void __iomem *reg;
+ spinlock_t *lock;
+};
+
+#define to_clk_fixed_gate(_hw) container_of(_hw, struct clk_fixed_gate, hw)
+
+static void clk_fixed_gate_endisable(struct clk_hw *hw, int enable)
+{
+ struct clk_fixed_gate *gate = to_clk_fixed_gate(hw);
+ unsigned long flags = 0;
+ u32 reg;
+
+ if (gate->lock)
+ spin_lock_irqsave(gate->lock, flags);
+
+ reg = readl(gate->reg);
+
+ if (enable)
+ reg |= BIT(gate->bit_idx);
+ else
+ reg &= ~BIT(gate->bit_idx);
+
+ writel(reg, gate->reg);
+
+ if (gate->lock)
+ spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int clk_fixed_gate_enable(struct clk_hw *hw)
+{
+ clk_fixed_gate_endisable(hw, 1);
+
+ return 0;
+}
+
+static void clk_fixed_gate_disable(struct clk_hw *hw)
+{
+ clk_fixed_gate_endisable(hw, 0);
+}
+
+static int clk_fixed_gate_is_enabled(struct clk_hw *hw)
+{
+ u32 reg;
+ struct clk_fixed_gate *gate = to_clk_fixed_gate(hw);
+
+ reg = readl(gate->reg);
+
+ reg &= BIT(gate->bit_idx);
+
+ return reg ? 1 : 0;
+}
+
+static unsigned long clk_fixed_gate_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return to_clk_fixed_gate(hw)->fixed_rate;
+}
+
+static const struct clk_ops clk_fixed_gate_ops = {
+ .enable = clk_fixed_gate_enable,
+ .disable = clk_fixed_gate_disable,
+ .is_enabled = clk_fixed_gate_is_enabled,
+ .recalc_rate = clk_fixed_gate_recalc_rate,
+};
+
+/**
+ * clk_register_fixed_gate - register a fixed rate,
+ * gate clock with the clock framework
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_name: name of this clock's parent
+ * @flags: framework-specific flags for this clock
+ * @reg: register address to control gating of this clock
+ * @bit_idx: which bit in the register controls gating of this clock
+ * @lock: shared register lock for this clock
+ */
+struct clk *clk_register_fixed_gate(struct device *dev, const char *name,
+ const char *parent_name,
+ unsigned long flags, void __iomem *reg,
+ u8 bit_idx, unsigned long fixed_rate,
+ spinlock_t *lock)
+{
+ struct clk_fixed_gate *gate;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ /* allocate the gate */
+ gate = kzalloc(sizeof(struct clk_fixed_gate), GFP_KERNEL);
+ if (!gate) {
+ pr_err("%s: could not allocate fixed gated clk\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = name;
+ init.ops = &clk_fixed_gate_ops;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ /* struct clk_fixed_gate assignments */
+ gate->fixed_rate = fixed_rate;
+ gate->reg = reg;
+ gate->bit_idx = bit_idx;
+ gate->lock = lock;
+ gate->hw.init = &init;
+
+ clk = clk_register(dev, &gate->hw);
+
+ if (IS_ERR(clk))
+ kfree(gate);
+
+ return clk;
+}
diff --git a/drivers/clk/sunxi/clk-fixed-gate.h b/drivers/clk/sunxi/clk-fixed-gate.h
new file mode 100644
index 0000000..29d9ed3
--- /dev/null
+++ b/drivers/clk/sunxi/clk-fixed-gate.h
@@ -0,0 +1,13 @@
+#ifndef __MACH_SUNXI_CLK_FIXED_GATE_H
+#define __MACH_SUNXI_CLK_FIXED_GATE_H
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+
+struct clk *clk_register_fixed_gate(struct device *dev, const char *name,
+ const char *parent_name,
+ unsigned long flags, void __iomem *reg,
+ u8 bit_idx, unsigned long fixed_rate,
+ spinlock_t *lock);
+
+#endif
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
new file mode 100644
index 0000000..cb587a0
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright 2013 Emilio L?pez
+ *
+ * Emilio L?pez <emilio@elopez.com.ar>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/sunxi.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk-factors.h"
+#include "clk-fixed-gate.h"
+
+static DEFINE_SPINLOCK(clk_lock);
+
+/**
+ * sunxi_osc_clk_setup() - Setup function for gatable oscillator
+ */
+
+#define SUNXI_OSC24M_GATE 0
+
+static void __init sunxi_osc_clk_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ void *reg;
+ u32 rate;
+
+ reg = of_iomap(node, 0);
+
+ if (of_property_read_u32(node, "clock-frequency", &rate))
+ return;
+
+ clk = clk_register_fixed_gate(NULL, clk_name, NULL,
+ CLK_IS_ROOT | CLK_IGNORE_UNUSED,
+ reg, SUNXI_OSC24M_GATE, rate, &clk_lock);
+
+ if (clk) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ clk_register_clkdev(clk, clk_name, NULL);
+ }
+}
+
+
+
+/**
+ * sunxi_get_pll1_factors() - calculates n, k, m, p factors for PLL1
+ * PLL1 rate is calculated as follows
+ * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
+ * parent_rate is always 24Mhz
+ */
+
+static void sunxi_get_pll1_factors(u32 *freq, u8 *n, u8 *k, u8 *m, u8 *p)
+{
+ u8 div;
+
+ /* Normalize value to a 6M multiple */
+ div = *freq / 6000000;
+ *freq = 6000000 * div;
+
+ /* we were called to round the frequency, we can now return */
+ if (n == NULL)
+ return;
+
+ /* m is always zero for pll1 */
+ *m = 0;
+
+ /* k is 1 only on these cases */
+ if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
+ *k = 1;
+ else
+ *k = 0;
+
+ /* p will be 3 for divs under 10 */
+ if (div < 10)
+ *p = 3;
+
+ /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
+ else if (div < 20 || (div < 32 && (div & 1)))
+ *p = 2;
+
+ /* p will be 1 for even divs under 32, divs under 40 and odd pairs
+ * of divs between 40-62 */
+ else if (div < 40 || (div < 64 && (div & 2)))
+ *p = 1;
+
+ /* any other entries have p = 0 */
+ else
+ *p = 0;
+
+ /* calculate a suitable n based on k and p */
+ div <<= *p;
+ div /= (*k + 1);
+ *n = div / 4;
+}
+
+/**
+ * sunxi_pll1_clk_setup() - Setup function for PLL1 clock
+ */
+
+struct clk_factors_config pll1_config = {
+ .nshift = 8,
+ .nwidth = 5,
+ .kshift = 4,
+ .kwidth = 2,
+ .mshift = 0,
+ .mwidth = 2,
+ .pshift = 16,
+ .pwidth = 2,
+};
+
+static void __init sunxi_pll1_clk_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ const char *parent;
+ void *reg;
+
+ reg = of_iomap(node, 0);
+
+ parent = of_clk_get_parent_name(node, 0);
+
+ clk = clk_register_factors(NULL, clk_name, parent, CLK_IGNORE_UNUSED,
+ reg, &pll1_config, sunxi_get_pll1_factors,
+ &clk_lock);
+
+ if (clk) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ clk_register_clkdev(clk, clk_name, NULL);
+ }
+}
+
+
+
+/**
+ * sunxi_cpu_clk_setup() - Setup function for CPU mux
+ */
+
+#define SUNXI_CPU_GATE 16
+#define SUNXI_CPU_GATE_WIDTH 2
+
+static void __init sunxi_cpu_clk_setup(struct device_node *node)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ const char **parents = kmalloc(sizeof(char *) * 5, GFP_KERNEL);
+ void *reg;
+ int i = 0;
+
+ reg = of_iomap(node, 0);
+
+ while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
+ i++;
+
+ clk = clk_register_mux(NULL, clk_name, parents, i, 0, reg,
+ SUNXI_CPU_GATE, SUNXI_CPU_GATE_WIDTH,
+ 0, &clk_lock);
+
+ if (clk) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ clk_register_clkdev(clk, clk_name, NULL);
+ }
+}
+
+
+
+/**
+ * sunxi_divider_clk_setup() - Setup function for simple divider clocks
+ */
+
+#define SUNXI_DIVISOR_WIDTH 2
+
+struct div_data {
+ u8 div;
+ u8 pow;
+};
+
+static const __initconst struct div_data axi_data = {
+ .div = 0,
+ .pow = 0,
+};
+
+static const __initconst struct div_data ahb_data = {
+ .div = 4,
+ .pow = 1,
+};
+
+static const __initconst struct div_data apb0_data = {
+ .div = 8,
+ .pow = 1,
+};
+
+static void __init sunxi_divider_clk_setup(struct device_node *node, u8 shift,
+ u8 power_of_two)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ const char *clk_parent;
+ void *reg;
+
+ reg = of_iomap(node, 0);
+
+ clk_parent = of_clk_get_parent_name(node, 0);
+
+ clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
+ reg, shift, SUNXI_DIVISOR_WIDTH,
+ power_of_two ? CLK_DIVIDER_POWER_OF_TWO : 0,
+ &clk_lock);
+ if (clk) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ clk_register_clkdev(clk, clk_name, NULL);
+ }
+}
+
+
+/* Matches for of_clk_init */
+static const __initconst struct of_device_id clk_match[] = {
+ {.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
+ {.compatible = "allwinner,sunxi-osc-clk", .data = sunxi_osc_clk_setup,},
+ {.compatible = "allwinner,sunxi-pll1-clk", .data = sunxi_pll1_clk_setup,},
+ {.compatible = "allwinner,sunxi-cpu-clk", .data = sunxi_cpu_clk_setup,},
+ {}
+};
+
+/* Matches for divider clocks */
+static const __initconst struct of_device_id clk_div_match[] = {
+ {.compatible = "allwinner,sunxi-axi-clk", .data = &axi_data,},
+ {.compatible = "allwinner,sunxi-ahb-clk", .data = &ahb_data,},
+ {.compatible = "allwinner,sunxi-apb0-clk", .data = &apb0_data,},
+ {}
+};
+
+static void __init of_sunxi_divider_clock_setup(void)
+{
+ struct device_node *np;
+ const struct div_data *data;
+ const struct of_device_id *match;
+
+ for_each_matching_node(np, clk_div_match) {
+ match = of_match_node(clk_div_match, np);
+ data = match->data;
+ sunxi_divider_clk_setup(np, data->div, data->pow);
+ }
+}
+
+void __init sunxi_init_clocks(void)
+{
+ /* Register all the simple sunxi clocks on DT */
+ of_clk_init(clk_match);
+
+ /* Register divider clocks */
+ of_sunxi_divider_clock_setup();
+}
--
1.8.1.1
^ permalink raw reply related
* [PATCH 0/3] clock driver for sunxi
From: Emilio López @ 2013-01-22 6:12 UTC (permalink / raw)
To: linux-arm-kernel
Hello everyone,
This patchset adds basic clock support for sunxi devices. Currently, it
implements support for the two oscillators, the main PLL, the CPU mux,
and its three divisor clocks. With this in place, it is possible to
write a cpufreq driver and have it work.
I have tested this driver successfully on a Cubieboard (A10, sun4i)
using the cpufreq driver from the linux-sunxi tree after minor
modifications (the clock names are not the same).
Any feedback will be highly appreciated
Thanks,
--
Emilio
Emilio L?pez (3):
clk: arm: sunxi: Add a new clock driver for sunxi SOCs
arm: sunxi: Add clock definitions for the new clock driver
arm: sunxi: Add useful information about sunxi clocks
Documentation/arm/sunxi/clocks.txt | 56 +++++
Documentation/devicetree/bindings/clock/sunxi.txt | 47 ++++
arch/arm/boot/dts/sunxi.dtsi | 55 ++++-
drivers/clk/Makefile | 2 +-
drivers/clk/clk-sunxi.c | 30 ---
drivers/clk/sunxi/Makefile | 5 +
drivers/clk/sunxi/clk-factors.c | 175 ++++++++++++++
drivers/clk/sunxi/clk-factors.h | 25 ++
drivers/clk/sunxi/clk-fixed-gate.c | 152 +++++++++++++
drivers/clk/sunxi/clk-fixed-gate.h | 13 ++
drivers/clk/sunxi/clk-sunxi.c | 265 ++++++++++++++++++++++
11 files changed, 788 insertions(+), 37 deletions(-)
create mode 100644 Documentation/arm/sunxi/clocks.txt
create mode 100644 Documentation/devicetree/bindings/clock/sunxi.txt
delete mode 100644 drivers/clk/clk-sunxi.c
create mode 100644 drivers/clk/sunxi/Makefile
create mode 100644 drivers/clk/sunxi/clk-factors.c
create mode 100644 drivers/clk/sunxi/clk-factors.h
create mode 100644 drivers/clk/sunxi/clk-fixed-gate.c
create mode 100644 drivers/clk/sunxi/clk-fixed-gate.h
create mode 100644 drivers/clk/sunxi/clk-sunxi.c
--
1.8.1.1
^ permalink raw reply
* [PATCH 13/15] USB: ehci: make orion and mxc bus glues coexist
From: Shawn Guo @ 2013-01-22 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201301212137.42611.arnd@arndb.de>
On Mon, Jan 21, 2013 at 09:37:42PM +0000, Arnd Bergmann wrote:
> > Arnd, please take a look at
> >
> > http://marc.info/?l=linux-usb&m=135843716515529&w=2
> >
> > I can't test it easily, not being set up for cross compilation. I'm
> > waiting to hear from anybody whether it works before submitting it.
> > (There's also a report of memory corruption involving a similar patch
> > for ehci-omap; it hasn't been tracked down yet.)
>
> Your patch looks good to me, but it also seems to do some other
> changes that are not required to fix the problem but could wait
> for 3.9 instead. You definitely have my Ack if you are willing
> to take it for 3.8 though.
>
> Shawn or Sascha should be able to test it.
>
Alan,
Thanks for the patch. I just gave it try. The USB Host port still
works for me with a couple of fixes on your changes integrated (one
for compiling and the other for probing). So you have my ACK with
the changes below rolled into your patch.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
---8<----
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index 177b354..a685945 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -37,7 +37,7 @@
#define DRIVER_DESC "Freescale On-Chip EHCI Host driver"
-static const char hcd_name[] = "ehci-mxc";
+static const char hcd_name[] = "mxc-ehci";
#define ULPI_VIEWPORT_OFFSET 0x170
@@ -48,7 +48,7 @@ struct ehci_mxc_priv {
static struct hc_driver __read_mostly ehci_mxc_hc_driver;
static const struct ehci_driver_overrides ehci_mxc_overrides __initdata = {
- .extra_priv_size = sizeof(struct ehci_mxc_priv);
+ .extra_priv_size = sizeof(struct ehci_mxc_priv),
};
static int ehci_mxc_drv_probe(struct platform_device *pdev)
^ permalink raw reply related
* [v3 2/2] ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9
From: Santosh Shilimkar @ 2013-01-22 6:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358833924-24535-2-git-send-email-hdoyu@nvidia.com>
On Tuesday 22 January 2013 11:22 AM, Hiroshi Doyu wrote:
> Skip scu_enable(scu_base) if CPU is not Cortex A9 with SCU.
>
> Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
> ---
Looks fine. I will also update OMAP code with the new
interface. Thanks.
For the patch,
Acked-by: Santosh Shilimkar<santosh.shilimkar@ti.com>
^ permalink raw reply
* [PATCH 3/4] ARM: mach-omap2: apply the errata at run time rather
From: Srinidhi Kasagar @ 2013-01-22 6:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130121182236.GE22517@atomide.com>
On Mon, Jan 21, 2013 at 19:22:37 +0100, Tony Lindgren wrote:
> * srinidhi kasagar <srinidhi.kasagar@stericsson.com> [130121 05:19]:
>
> Forgot to complete the subject and add the description?
No :) It has the subject, but description is intentionally skipped
because subject has all the meaning and it is a part of the series
of patches I sent..
regards/srinidhi
^ permalink raw reply
* [PATCH 4/4] ARM: apply the l2x0 Errata 769419 at run time
From: Srinidhi Kasagar @ 2013-01-22 5:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130121161202.GR23505@n2100.arm.linux.org.uk>
On Mon, Jan 21, 2013 at 17:12:02 +0100, Russell King - ARM Linux wrote:
> On Mon, Jan 21, 2013 at 06:47:12PM +0530, srinidhi kasagar wrote:
> > Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
> > ---
> > arch/arm/kernel/process.c | 9 ++++++---
> > 1 files changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> > index c6dec5f..c94d84f 100644
> > --- a/arch/arm/kernel/process.c
> > +++ b/arch/arm/kernel/process.c
> > @@ -39,6 +39,7 @@
> > #include <asm/thread_notify.h>
> > #include <asm/stacktrace.h>
> > #include <asm/mach/time.h>
> > +#include <asm/hardware/cache-l2x0.h>
> >
> > #ifdef CONFIG_CC_STACKPROTECTOR
> > #include <linux/stackprotector.h>
> > @@ -201,9 +202,11 @@ void cpu_idle(void)
> > * to ensure we don't miss a wakeup call.
> > */
> > local_irq_disable();
> > -#ifdef CONFIG_PL310_ERRATA_769419
> > - wmb();
> > -#endif
> > +
> > + /* Check for PL310 ERRATA 769419 */
> > + if (l2x0_get_rtl_release() == L2X0_CACHE_ID_RTL_R3P0)
> > + wmb();
>
> You have to be joking if you think that is suitable... two reasons:
>
> 1. It's a horrid layering violation.
> 2. l2x0_get_rtl_release() unconditionally reads from a register in the L2
> controller. What if you don't have a L2 controller?
my bad, this can be fixed. Thank you.
>
> Is it really worth this hastle, or would it just be better to keep the
> ifdef there, using the configuration symbol as a way to indicate whether
> we want this work-around included in the kernel, and always have the
> wmb() there if the symbol is enabled?
We can keep the ifdef there, my idea was to completely eliminate these
CONFIG_PL310_ERRATA_*. The problem comes when you have a single defconfig
for two platforms (ex, ST-E's 8500 and 8540) where one platform needs
this and the other don't.
regards/srinidhi
^ permalink raw reply
* [PATCH v7 14/15] pinctrl: single: support generic pinconf
From: Haojian Zhuang @ 2013-01-22 5:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130121171436.GI15361@atomide.com>
On 22 January 2013 01:14, Tony Lindgren <tony@atomide.com> wrote:
> Hi,
>
> * Haojian Zhuang <haojian.zhuang@linaro.org> [130117 23:35]:
>> +static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
>> + struct pcs_function *func,
>> + struct pinctrl_map **map)
>> +
>> +{
>> + struct pinctrl_map *m = *map;
>> + int i = 0, nconfs = 0;
>> + unsigned long *settings = NULL, *s = NULL;
>> + struct pcs_conf_vals *conf = NULL;
>> + struct pcs_conf_type prop2[] = {
>> + { "pinctrl-single,power-source", PIN_CONFIG_POWER_SOURCE, },
>> + { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
>> + { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
>> + };
>
> The PIN_CONFIG_POWER_SOURCE should be split to PIN_CONFIG_POWER_ENABLE
> and PIN_CONFIG_POWER_SOURCE. If you only have one bit for it, I guess then
> you can just use PIN_CONFIG_POWER_ENABLE and make PIN_CONFIG_POWER_SOURCE
> a NOP.
>
In Hisilicon Hi3620 SoC, 4bits are used for power source. b0000 is
2mA, b0001 is 4mA, .... b1111 is 8mA.
There's no power enable bit. In Marvell silicon, it's also same.
> I also suggest we standardize on PIN_CONFIG_*_ENABLE on the naming instead
> of PIN_CONFIG_*_DISABLE. Many of these features enable some input logic,
> and by default they should be off to save power.
>
In Hisilicon Hi3620 SoC, there's no bias enable or disable bit. They
could only configure pull up or
pull down. We can think that no-pullup and no-pulldown is bias
disable. If we define BIAS_ENABLE,
both pullup & pulldown meet the definition. It's a problem.
>> + struct pcs_conf_type prop3[] = {
>> + { "pinctrl-single,bias-disable", PIN_CONFIG_BIAS_DISABLE, },
>> + { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
>> + { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
>> + { "pinctrl-single,input-schmitt-disable",
>> + PIN_CONFIG_INPUT_SCHMITT_DISABLE, },
>> + };
>
> I'm not aware of cases where we need both INPUT_SCHMITT and INPUT_SCHMITT_DISABLE,
> so we may just want to have INPUT_SCHMITT_ENABLE if that works for you.
>
Because marvell silicon coul configure two input schmitt type (rise
edge or fall edge).
Could we always use DISABLE as our standard? It seems that this
defintion could be compatible
with most silicons.
> Other than that, looks good to me. I'll update my patches here and do
> some tests against my pinctrl-single,bits testcase.
>
> Regards,
>
> Tony
Thanks
Haojian
^ permalink raw reply
* [v3 2/2] ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9
From: Hiroshi Doyu @ 2013-01-22 5:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358833924-24535-1-git-send-email-hdoyu@nvidia.com>
Skip scu_enable(scu_base) if CPU is not Cortex A9 with SCU.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
arch/arm/mach-tegra/platsmp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 689ee4b..8853bd2 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -38,7 +38,6 @@
extern void tegra_secondary_startup(void);
static cpumask_t tegra_cpu_init_mask;
-static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
#define EVP_CPU_RESET_VECTOR \
(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
@@ -187,7 +186,8 @@ static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
/* Always mark the boot CPU (CPU0) as initialized. */
cpumask_set_cpu(0, &tegra_cpu_init_mask);
- scu_enable(scu_base);
+ if (scu_a9_has_base())
+ scu_enable(IO_ADDRESS(scu_a9_get_base()));
}
struct smp_operations tegra_smp_ops __initdata = {
--
1.7.9.5
^ permalink raw reply related
* [v3 1/2] ARM: Add API to detect SCU base address from CP15
From: Hiroshi Doyu @ 2013-01-22 5:52 UTC (permalink / raw)
To: linux-arm-kernel
Add API to detect SCU base address from CP15.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
Update: Use Russell's suggestion,
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-January/143321.html
---
arch/arm/include/asm/smp_scu.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 4eb6d00..006f026 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -6,6 +6,23 @@
#define SCU_PM_POWEROFF 3
#ifndef __ASSEMBLER__
+
+#include <asm/cputype.h>
+
+static inline bool scu_a9_has_base(void)
+{
+ return read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9;
+}
+
+static inline unsigned long scu_a9_get_base(void)
+{
+ unsigned long pa;
+
+ asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa));
+
+ return pa;
+}
+
unsigned int scu_get_core_count(void __iomem *);
void scu_enable(void __iomem *);
int scu_power_mode(void __iomem *, unsigned int);
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/4] ARM: cache-l2x0: Manage the errata at run time
From: Srinidhi Kasagar @ 2013-01-22 5:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130121160833.GQ23505@n2100.arm.linux.org.uk>
On Mon, Jan 21, 2013 at 17:08:34 +0100, Russell King - ARM Linux wrote:
> On Mon, Jan 21, 2013 at 06:44:53PM +0530, srinidhi kasagar wrote:
> > +/*
> > + * Identify ther RTL releases of l2x0 - This might help in applying
> > + * the l2x0 errata's dynamically rather compile time options
> > + */
> > +asmlinkage u32 l2x0_get_rtl_release(void)
>
> Why asmlinkage?
Because I found that TI's omap suspend code also need this.
arch/arm/mach-omap2/sleep44xx.S
>
> > +{
> > + return readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
> > + L2X0_CACHE_ID_RTL_MASK;
> > +}
> > +
> > static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
> > {
> > /* wait for cache operation by line or way to complete */
> > @@ -87,46 +97,41 @@ static inline void l2x0_inv_line(unsigned long addr)
> > writel_relaxed(addr, base + L2X0_INV_LINE_PA);
> > }
> >
> > -#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
> > -static inline void debug_writel(unsigned long val)
> > +static void debug_writel(unsigned long val)
> > {
> > - if (outer_cache.set_debug)
> > - outer_cache.set_debug(val);
> > + u32 l2x0_revision = l2x0_get_rtl_release();
> > +
> > + if (l2x0_revision == L2X0_CACHE_ID_RTL_R3P0 ||
> > + l2x0_revision == L2X0_CACHE_ID_RTL_R2P0 ||
> > + l2x0_revision == L2X0_CACHE_ID_RTL_R1P0 ||
> > + l2x0_revision == L2X0_CACHE_ID_RTL_R0P0)
> > + if (outer_cache.set_debug)
> > + outer_cache.set_debug(val);
>
> This needs comments from the TI folk. Also, change this around - if
> there's no setting for 'set_debug' there's no point reading the rtl
> release and checking it against a set of values. Added Santosh.
>
> > static inline void l2x0_flush_line(unsigned long addr)
> > {
> > void __iomem *base = l2x0_base;
> > - cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
> > - writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
> > + u32 l2x0_revision = l2x0_get_rtl_release();
> > +
> > + if (l2x0_revision == L2X0_CACHE_ID_RTL_R0P0 ||
> > + l2x0_revision == L2X0_CACHE_ID_RTL_R1P0)
> > + {
>
> Coding standards.
OK.
regards/srinidhi
^ permalink raw reply
* [PATCH 1/4] ARM: cache-l2x0: Manage the errata at run time
From: Srinidhi Kasagar @ 2013-01-22 5:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130121140344.GG18005@mudshark.cambridge.arm.com>
On Mon, Jan 21, 2013 at 15:03:44 +0100, Will Deacon wrote:
> On Mon, Jan 21, 2013 at 01:14:53PM +0000, srinidhi kasagar wrote:
> > Make it possible to manage the errata by its own by using the
> > l2x0 ID register. This relieves the platforms from choosing the
> > Errata's at compile time
> >
> > Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
> > ---
> > arch/arm/include/asm/hardware/cache-l2x0.h | 2 +
> > arch/arm/mm/cache-l2x0.c | 77 +++++++++++++++-------------
> > 2 files changed, 43 insertions(+), 36 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
> > index 3b2c40b..d5994ac 100644
> > --- a/arch/arm/include/asm/hardware/cache-l2x0.h
> > +++ b/arch/arm/include/asm/hardware/cache-l2x0.h
> > @@ -117,6 +117,8 @@ static inline int l2x0_of_init(u32 aux_val, u32 aux_mask)
> > }
> > #endif
> >
> > +asmlinkage u32 l2x0_get_rtl_release(void);
> > +
> > struct l2x0_regs {
> > unsigned long phy_base;
> > unsigned long aux_ctrl;
> > diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> > index c2f3739..49058ac 100644
> > --- a/arch/arm/mm/cache-l2x0.c
> > +++ b/arch/arm/mm/cache-l2x0.c
> > @@ -49,6 +49,16 @@ struct l2x0_of_data {
> >
> > static bool of_init = false;
> >
> > +/*
> > + * Identify ther RTL releases of l2x0 - This might help in applying
> > + * the l2x0 errata's dynamically rather compile time options
> > + */
> > +asmlinkage u32 l2x0_get_rtl_release(void)
> > +{
> > + return readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
> > + L2X0_CACHE_ID_RTL_MASK;
> > +}
>
> You're calling this function all over the place, including from the flush
> code. Can you read the RTL release during probe and stash it somewhere
> instead please?
I thought of doing that, however TI omap's suspend is the only one which needs
this API as well, So, I had to make it global. Refer my patch 3/4. I can
duplicate this for omap if you think so..
srinidhi
^ permalink raw reply
* ARM: hw_breakpoint mismatch breakpoint behaves unexpectedly like a match breakpoint on ARM_DEBUG_ARCH_V7_ECP14
From: Valentin Pistol @ 2013-01-22 4:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi Will,
I am trying to single-step each instruction in a target process by
using the hardware breakpoints with the mismatch set (bit 22) and I am
experiencing unexpected behavior: with mismatch set it behaves as a
match breakpoint.
I checked that my Debug Arch ARM_DEBUG_ARCH_V7_ECP14 has mismatch
breakpoint support.
The BCR (0x4001e5) value and DSCR (0x3070002) seem to be correct
according to the manual, so I am confused what is causing the odd
behavior.
I am testing on Pandaboard ES Rev B1 (OMAP4460) using Linux 3.0.31
with Android 4.1.1 and also on Linux 3.2.0-1424-omap4 with Ubuntu
12.04.
I checked your git repo for any updates that might be related or fix
this problem and haven't seen any but may be wrong.
I should note that I am able to set a match breakpoint using the
ptrace interface, have it trigger a SIGTRAP and capture it in my own
user space handler. When attempting to use mismatch instead, the
behavior appears to be same as a match breakpoint: breaks on the
specified PC value.
I tried setting the BVR to 0 or some short address + mismatch but that
never triggers although it should.
My own ptrace code attaches to a running test case (hello) via pid,
sets the breakpoint and detaches right after.
The hello code simply increments a value via a pointer, inside a while loop.
The hello output shows the hello handler catches the same trap for the
same PC as in BVR.
Since am not unsetting the breakpoint in the handler, it's expected
that the trap keeps triggering for a match breakpoint.
But since I am using a mistmatch, I would expect the PC value to
change across traps.
For full correctness I would still need to change the BVR on each trap
to the current PC, but that's after mismatch works in the first place.
I can provide a minicom log with full dmesg if needed.
The following logs are from Linux 3.0.31 but behavior is the same as
Linux 3.2.0-1424-omap4.
I think the multiple repeats of setting and unsetting the breakpoint
are due to context switches but I may be wrong.
ptracer log:
PTRACE_ATTACH on target pid 675
PTRACE_GETREGS for target pid:
r0 fffffffc r1 be912c48 r2 00000003 r3 00000000
r4 400484b8 r5 be912c94 r6 00000001 r7 000000a2
r8 00000000 r9 00000000 sl 00000000 fp 00000000
ip 40049ffc sp be912c40 lr 400e809d pc 400db2f0 cpsr 60000110
PTRACE_GETHBPREGS result = 0x03040105
PTRACE_GETHBPREGS debug arch = 0x3
PTRACE_GETHBPREGS max_wp_length = 4
PTRACE_GETHBPREGS wp_count = 1
PTRACE_GETHBPREGS bp_count = 5
DIDR 0x3513702a
DSCR 0x03070002
Mismatch Breakpoints Support: Yes
BVR addr = 0x400db2f0
BCR ctrl = 0x4001e5
PTRACE_DETACH ...
hello log:
SIGTRAP with TRAP code: 4 at addr: 0x400db2f0
SIGTRAP with TRAP code: 4 at addr: 0x400db2f0
SIGTRAP with TRAP code: 4 at addr: 0x400db2f0
SIGTRAP with TRAP code: 4 at addr: 0x400db2f0
[repeats]
dmesg log with additional debugging for breakpoint:
[ 65.857971] ptrace_gethbpregs entering...
[ 65.863159] ptrace_sethbpregs entering...
[ 65.867248] ptrace_hbp_create entering...
[ 65.872375] register_user_hw_breakpoint entering...
[ 65.877868] ptrace_sethbpregs setting bp_addr = 0x400db2f0
[ 65.884490] modify_user_hw_breakpoint entering...
[ 65.884490] modify_user_hw_breakpoint returning
[ 65.895263] ptrace_sethbpregs entering...
[ 65.900024] ptrace_sethbpregs setting bp_len = 4 bp_type = 4 enabled = 1
[ 65.907440] modify_user_hw_breakpoint entering...
[ 65.911193] modify_user_hw_breakpoint returning
[ 65.917724] hw_breakpoint_add entering
[ 65.922027] hw-breakpoint: arch_install_hw_breakpoint entering ...
[ 65.922027] hw-breakpoint: enable_monitor_mode entering dscr = 0x3070002...
[ 65.936035] hw-breakpoint: enable_monitor_mode setting
ARM_DSCR_MDBGEN for ARM_DEBUG_ARCH_V7_ECP14
[ 65.946685] hw-breakpoint: enable_monitor_mode leaving dscr =
0x3078002 ret = 0...
[ 65.946685] hw-breakpoint: arch_install_hw_breakpoint Setup addr +
ctrl registers
[ 65.962921] hw-breakpoint: arch_install_hw_breakpoint returning 0
[ 65.970062] hw-breakpoint: arch_uninstall_hw_breakpoint entering...
[ 65.976684] hw-breakpoint: arch_uninstall_hw_breakpoint returning
[ 65.983703] hw_breakpoint_add entering
[ 65.987945] hw-breakpoint: arch_install_hw_breakpoint entering ...
[ 65.994934] hw-breakpoint: enable_monitor_mode entering dscr = 0x3070002...
[ 66.002807] hw-breakpoint: enable_monitor_mode setting
ARM_DSCR_MDBGEN for ARM_DEBUG_ARCH_V7_ECP14
[ 66.012573] hw-breakpoint: enable_monitor_mode leaving dscr =
0x3078002 ret = 0...
[ 66.020874] hw-breakpoint: arch_install_hw_breakpoint Setup addr +
ctrl registers
[ 66.028747] hw-breakpoint: arch_install_hw_breakpoint returning 0
[ 66.035888] hw-breakpoint: arch_uninstall_hw_breakpoint entering...
[ 66.042510] hw-breakpoint: arch_uninstall_hw_breakpoint returning
[ 66.049316] hw_breakpoint_add entering
[ 66.049377] hw-breakpoint: arch_install_hw_breakpoint entering ...
[ 66.060607] hw-breakpoint: enable_monitor_mode entering dscr = 0x3078002...
[ 66.068634] hw-breakpoint: enable_monitor_mode leaving dscr =
0x3078002 ret = 0...
[ 66.076812] hw-breakpoint: arch_install_hw_breakpoint Setup addr +
ctrl registers
[ 66.084869] hw-breakpoint: arch_install_hw_breakpoint returning 0
[ 66.091857] hw-breakpoint: arch_uninstall_hw_breakpoint entering...
[ 66.098571] hw-breakpoint: arch_uninstall_hw_breakpoint returning
[multiple repeats of above 8 lines]
[ 67.567230] hw_breakpoint_add entering
[ 67.570800] hw-breakpoint: arch_install_hw_breakpoint entering ...
[ 67.570800] hw-breakpoint: enable_monitor_mode entering dscr = 0x3078002...
[ 67.586486] hw-breakpoint: enable_monitor_mode leaving dscr =
0x3078002 ret = 0...
[ 67.586486] hw-breakpoint: arch_install_hw_breakpoint Setup addr +
ctrl registers
[ 67.586486] hw-breakpoint: arch_install_hw_breakpoint returning 0
[ 67.609802] hw-breakpoint: hw_breakpoint_pending entering...
[ 67.609802] hw-breakpoint: breakpoint fired: address = 0x400db2f0
[ 67.623016] hw-breakpoint: arch_uninstall_hw_breakpoint entering...
[ 67.625061] hw-breakpoint: arch_uninstall_hw_breakpoint returning
[...]
[ 68.909637] hw_breakpoint_add entering
[ 68.909637] hw-breakpoint: arch_install_hw_breakpoint entering ...
[ 68.920898] hw-breakpoint: enable_monitor_mode entering dscr = 0x3078006...
[ 68.920898] hw-breakpoint: enable_monitor_mode leaving dscr =
0x3078006 ret = 0...
[ 68.920898] hw-breakpoint: arch_install_hw_breakpoint Setup addr +
ctrl registers
[ 68.920898] hw-breakpoint: arch_install_hw_breakpoint returning 0
[ 68.952056] hw-breakpoint: arch_uninstall_hw_breakpoint entering...
[ 68.958801] hw-breakpoint: arch_uninstall_hw_breakpoint returning
[multiple repeats of above 8 lines]
Any comments or suggestions would be very appreciated. Thanks!
Regards,
Valentin
^ permalink raw reply
* [PATCH 13/15] USB: ehci: make orion and mxc bus glues coexist
From: Manjunath Goudar @ 2013-01-22 4:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <Pine.LNX.4.44L0.1301212227020.32663-100000@netrider.rowland.org>
On 22 January 2013 09:09, Alan Stern <stern@rowland.harvard.edu> wrote:
> On Mon, 21 Jan 2013, Arnd Bergmann wrote:
>
> > Alan, one comment about your version: You keep maintaining the
> > '#if IS_ENABLED' list in the main driver, which I think can actually
> > get removed now.
>
> I considered doing that. The benefit of keeping it is that it warns
> about configs where the main driver is built but can never be used.
>
> Still, you're right that its purpose is becoming less important. I had
> planned to remove it when all the glue driver had been converted, but
> in fact it could be removed at any time.
>
> > Since the base driver can be built independent of
> > the presence of platform glue drivers, there is no need to forbid
> > it any more, and the #if block will cause merge conflicts for each
> > patch that converts or adds another platform.
>
> If the patches are done independently. There are likely to be some
> context conflicts anyway.
>
> > I think we can actually
> > get the same results by turning the Kconfig logic around and making
> > the platform glue drivers 'select USB_EHCI_HCD' than depending on
> > it.
>
> That's a good idea. The Kconfig changes would have to be done
> carefully to make sure that the dependency on USB_ARCH_HAS_EHCI still
> applies to all the platform drivers.
>
> Manjunath, would you like to send a patch to do this?
>
> Alan Stern
>
> Ya sure,could you explain little bit briefly about the Kconfig changes.
Thanks
MAnjunath Goudar
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^ permalink raw reply
* [PATCH v2] ARM: plat-samsung: using vsnprintf instead of vsprintf for the limit buffer length 256
From: Chen Gang @ 2013-01-22 3:54 UTC (permalink / raw)
To: linux-arm-kernel
the buff is 256 limited, so need use vsnprintf instead of vsprintf
Signed-off-by: Chen Gang <gang.chen@asianux.com>
Cc: Ben Dooks <ben@fluff.org>
---
arch/arm/plat-samsung/pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 1507028..d896add 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -51,7 +51,7 @@ void s3c_pm_dbg(const char *fmt, ...)
char buff[256];
va_start(va, fmt);
- vsprintf(buff, fmt, va);
+ vsnprintf(buff, sizeof(buff), fmt, va);
va_end(va);
printascii(buff);
--
1.7.10.4
^ permalink raw reply related
* [PATCH 09/15] media: coda: don't build on multiplatform
From: Shawn Guo @ 2013-01-22 3:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358788568-11137-10-git-send-email-arnd@arndb.de>
On Mon, Jan 21, 2013 at 05:16:02PM +0000, Arnd Bergmann wrote:
> The coda video codec driver depends on a mach-imx or mach-mxs specific
> header file "mach/iram.h". This is not available when building for
> multiplatform, so let us disable this driver for v3.8 when building
> multiplatform, and hopefully find a proper fix for v3.9.
>
> drivers/media/platform/coda.c:27:23: fatal error: mach/iram.h: No such file or directory
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Cc: Javier Martin <javier.martin@vista-silicon.com>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
> Cc: Mauro Carvalho Chehab <mchehab@redhat.com>
> Cc: linux-media at vger.kernel.org
> ---
> drivers/media/platform/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> index 3dcfea6..049d2b2 100644
> --- a/drivers/media/platform/Kconfig
> +++ b/drivers/media/platform/Kconfig
> @@ -142,7 +142,7 @@ if V4L_MEM2MEM_DRIVERS
>
> config VIDEO_CODA
> tristate "Chips&Media Coda multi-standard codec IP"
> - depends on VIDEO_DEV && VIDEO_V4L2 && ARCH_MXC
> + depends on VIDEO_DEV && VIDEO_V4L2 && ARCH_MXC && !ARCH_MULTIPLATFORM
> select VIDEOBUF2_DMA_CONTIG
> select V4L2_MEM2MEM_DEV
> select IRAM_ALLOC if SOC_IMX53
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
^ permalink raw reply
* [PATCH 05/15] ASoC: fsl: fiq and dma cannot both be modules
From: Shawn Guo @ 2013-01-22 3:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358788568-11137-6-git-send-email-arnd@arndb.de>
On Mon, Jan 21, 2013 at 05:15:58PM +0000, Arnd Bergmann wrote:
> The dma and fiq portions of the imx-pcm driver both
> have a module_init() call, of which there can be only
> one in any given module. This changes Kconfig to enforce
> either the driver to be built-in in the kernel, or
> to have only one of the two when building imx-pcm as
> a module.
>
> Without this patch, we cannot build the ARM 'allmodconfig', or
> we get this error:
>
> sound/soc/fsl/imx-pcm-dma.o: In function `init_module':
> sound/soc/fsl/imx-pcm-dma.c:177: multiple definition of `init_module'
> sound/soc/fsl/imx-pcm-fiq.o:sound/soc/fsl/imx-pcm-fiq.c:334: first defined here
> sound/soc/fsl/imx-pcm-dma.o: In function `cleanup_module':
> sound/soc/fsl/imx-pcm-dma.c:177: multiple definition of `cleanup_module'
> sound/soc/fsl/imx-pcm-fiq.o:sound/soc/fsl/imx-pcm-fiq.c:334: first defined here
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Cc: Liam Girdwood <lrg@ti.com>
> Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
> Cc: Shawn Guo <shawn.guo@linaro.org>
> Cc: alsa-devel at alsa-project.org
I sent a fix [1] for that queued by Mark.
Mark,
Is the patch on the way to 3.8-rc?
Shawn
[1] http://thread.gmane.org/gmane.linux.alsa.devel/104434
^ permalink raw reply
* [PATCH 13/15] USB: ehci: make orion and mxc bus glues coexist
From: Alan Stern @ 2013-01-22 3:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201301212149.15139.arnd@arndb.de>
On Mon, 21 Jan 2013, Arnd Bergmann wrote:
> Alan, one comment about your version: You keep maintaining the
> '#if IS_ENABLED' list in the main driver, which I think can actually
> get removed now.
I considered doing that. The benefit of keeping it is that it warns
about configs where the main driver is built but can never be used.
Still, you're right that its purpose is becoming less important. I had
planned to remove it when all the glue driver had been converted, but
in fact it could be removed at any time.
> Since the base driver can be built independent of
> the presence of platform glue drivers, there is no need to forbid
> it any more, and the #if block will cause merge conflicts for each
> patch that converts or adds another platform.
If the patches are done independently. There are likely to be some
context conflicts anyway.
> I think we can actually
> get the same results by turning the Kconfig logic around and making
> the platform glue drivers 'select USB_EHCI_HCD' than depending on
> it.
That's a good idea. The Kconfig changes would have to be done
carefully to make sure that the dependency on USB_ARCH_HAS_EHCI still
applies to all the platform drivers.
Manjunath, would you like to send a patch to do this?
Alan Stern
^ permalink raw reply
* [PATCH 06/14] mfd: omap-usb-host: update nports in platform_data
From: Samuel Ortiz @ 2013-01-22 3:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357836694-30788-7-git-send-email-rogerq@ti.com>
Hi Roger,
On Thu, Jan 10, 2013 at 06:51:26PM +0200, Roger Quadros wrote:
> EHCI driver would need to know the number of ports available
> on the platform. We set the nports parameter of platform_data
> based on IP version if it was not already provided.
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* [PATCH 08/14] mfd: omap-usb-host: Remove PHY reset handling code
From: Samuel Ortiz @ 2013-01-22 3:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357836694-30788-9-git-send-email-rogerq@ti.com>
HI Roger,
On Thu, Jan 10, 2013 at 06:51:28PM +0200, Roger Quadros wrote:
> PHY reset GPIO handling will be done in the PHY driver
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* [PATCH 3/4] watchdog: add support for ux500_wdt watchdog
From: Samuel Ortiz @ 2013-01-22 3:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358509214-22407-4-git-send-email-fabio.baltieri@linaro.org>
Hi Fabio, Wim,
On Fri, Jan 18, 2013 at 12:40:13PM +0100, Fabio Baltieri wrote:
> This patch adds support for the ux500_wdt watchdog that is found in
> ST-Ericsson Ux500 platform. The driver is based on PRCMU APIs.
>
> Acked-by: Lee Jones <lee.jones@linaro.org>
> Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org>
> ---
> drivers/watchdog/Kconfig | 12 +++
> drivers/watchdog/Makefile | 1 +
> drivers/watchdog/ux500_wdt.c | 171 ++++++++++++++++++++++++++++++++
> include/linux/platform_data/ux500_wdt.h | 19 ++++
> 4 files changed, 203 insertions(+)
> create mode 100644 drivers/watchdog/ux500_wdt.c
> create mode 100644 include/linux/platform_data/ux500_wdt.h
There is a dependency between this one an the first patch.
Wim, would you like me to carry this patch through the MFD tree ?
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* [PATCH 3/4] pinctrl: add abx500 pinctrl driver core
From: Samuel Ortiz @ 2013-01-22 3:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358242984-5160-1-git-send-email-linus.walleij@stericsson.com>
Hi Linus,
On Tue, Jan 15, 2013 at 10:43:04AM +0100, Linus Walleij wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> This adds the AB8500 core driver, which will be utilized by
> the follow-on drivers for different ABx500 variants.
> Sselect the driver from the DBX500_SOC, as this chip is
> powering and clocking that SoC.
>
> Cc: Samuel Ortiz <sameo@linux.intel.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Hi Sam, it'd be great if you could ACK this so we could proceed
> with rewriting the GPIO driver.
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* [PATCH 1/3] mfd: Fix compile errors and warnings when !CONFIG_AB8500_BM
From: Samuel Ortiz @ 2013-01-22 3:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357725965-27342-1-git-send-email-lee.jones@linaro.org>
Hi Lee,
On Wed, Jan 09, 2013 at 10:06:03AM +0000, Lee Jones wrote:
> drivers/mfd/ab8500-core.c:1015:21: error: ?ab8500_bm_data? undeclared here
>
> include/linux/mfd/abx500/ab8500-bm.h:445:13: warning: ?ab8500_fg_reinit? defined but not used
> include/linux/mfd/abx500/ab8500-bm.h:448:13: warning: ?ab8500_charger_usb_state_changed? defined but not used
> include/linux/mfd/abx500/ab8500-bm.h:451:29: warning: ?ab8500_btemp_get? defined but not used
> include/linux/mfd/abx500/ab8500-bm.h:455:12: warning: ?ab8500_btemp_get_batctrl_temp? defined but not used
> include/linux/mfd/abx500/ab8500-bm.h:463:12: warning: ?ab8500_fg_inst_curr_blocking? defined but not used
> include/linux/mfd/abx500/ab8500-bm.h:442:12: warning: ?ab8500_fg_inst_curr_done? defined but not used
> include/linux/mfd/abx500/ab8500-bm.h:447:26: warning: ?ab8500_fg_get? defined but not used
>
> Signed-off-by: Lee Jones <lee.jones@linaro.org>
> ---
> drivers/mfd/ab8500-core.c | 1 +
> include/linux/mfd/abx500.h | 2 --
> include/linux/mfd/abx500/ab8500-bm.h | 29 ++++-------------------------
> 3 files changed, 5 insertions(+), 27 deletions(-)
Applied to my for-linus branch, thanks.
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* [PATCH] ARM: ux500: de-globalize <mach/id.h>
From: Samuel Ortiz @ 2013-01-22 3:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357546827-10154-1-git-send-email-linus.walleij@stericsson.com>
Hi Linus,
On Mon, Jan 07, 2013 at 09:20:27AM +0100, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij@linaro.org>
>
> This removes the file <mach/id.h> from the global kernel include
> scope, making it a pure mach-ux500 detail. All ASIC specifics
> needed by drivers shall henceforth be passed from either platform
> data or the device tree.
>
> Cc: Samuel Ortiz <sameo@linux.intel.com>
> Cc: Rafael J. Wysocki <rjw@sisk.pl>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> I'm sending this as a preview, collecting ACKs for the next
> merge window.
>
> Sam, Rafael, could you ACK this?
>
> Linus Walleij
> ---
> arch/arm/mach-ux500/board-mop500-uib.c | 1 +
> arch/arm/mach-ux500/cache-l2x0.c | 3 +-
> arch/arm/mach-ux500/cpu-db8500.c | 2 +
> arch/arm/mach-ux500/cpu.c | 1 +
> arch/arm/mach-ux500/id.c | 2 +
> arch/arm/mach-ux500/id.h | 144 ++++++++++++++++++++++++++++
> arch/arm/mach-ux500/include/mach/hardware.h | 1 -
> arch/arm/mach-ux500/include/mach/id.h | 144 ----------------------------
> arch/arm/mach-ux500/platsmp.c | 3 +
> arch/arm/mach-ux500/timer.c | 2 +
> drivers/cpufreq/db8500-cpufreq.c | 3 -
> drivers/mfd/db8500-prcmu.c | 17 ++--
> include/linux/mfd/dbx500-prcmu.h | 2 -
For the MFD bits:
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
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