* [PATCH 3/6] arm: kconfig: don't select TWD with local timer for Armada 370/XP
From: Arnd Bergmann @ 2013-01-22 17:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130122171817.GM23505@n2100.arm.linux.org.uk>
On Tuesday 22 January 2013, Russell King - ARM Linux wrote:
> >
> > > > default y
> > > I am not a kconfig expert, but won't this line set HAVE_ARM_TWD to 'y' whatever
> > > the result of the previous line?
> >
> > Yes, that was a mistake on my side.
>
> Sigh. No. Wrong.
>
> config HAVE_ARM_TWD
> depends on LOCAL_TIMERS
> default ARCH_MULTIPLATFORM || (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT && !ARMADA_370_XP_TIMER)
> default y
>
> This takes the value of the first enabled default. The first enabled
> default is the first default (it's unconditional). So, the default y
> will never be used.
Right. I actually know how it works, but didn't think through it this
time. The 'default y' was a mistake on my side and should not have
been in there. I was also missing a 'bool' statement in there, which
makes the whole thing a syntax error.
> Given the above, it's far from clear what the actual behaviour being
> asked for is - it looks totally and utterly screwed to me - and the
> wrong thing to be doing.
>
> If the desire is to have it enabled if ARCH_MULTIPLATFORM is set, then
> it's easy, and requires just a single line addition:
>
> config LOCAL_TIMERS
> bool "Use local timer interrupts"
> depends on SMP
> default y
> select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
> + select HAVE_ARM_TWD if ARCH_MULTIPLATFORM
Right. The effect would be the same as what I intended to write:
config LOCAL_TIMERS
bool "Use local timer interrupts"
depends on SMP
default y
config HAVE_ARM_TWD
def_bool ARCH_MULTIPLATFORM || (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
depends on LOCAL_TIMERS
but your patch is simpler.
Arnd
^ permalink raw reply
* [PATCH] arm: kconfig: always select TWD with local timer for multiplatform
From: Gregory CLEMENT @ 2013-01-22 17:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50FEBF96.6020001@free-electrons.com>
When we enable multiplatform and local timers we should not disable
the build of the TWD driver even if there is support for MSM and/or
EXYNOS (those SoCs don't use TWD for their local timers). Indeed most
of the other SoCs will need it.
If multiplatform is not enable we keep the possibility to not add
support for TWD as we only built a kernel for MSM or for EXYNOS.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 67874b8..482ee23 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1625,6 +1625,7 @@ config LOCAL_TIMERS
depends on SMP
default y
select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
+ select HAVE_ARM_TWD if ARCH_MULTIPLATFORM
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system
--
1.7.9.5
^ permalink raw reply related
* [PATCH v4] drivers/pinctrl: grab default handles from device core
From: Stephen Warren @ 2013-01-22 17:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358795855-21064-1-git-send-email-linus.walleij@stericsson.com>
On 01/21/2013 12:17 PM, Linus Walleij wrote:
> This makes the device core auto-grab the pinctrl handle and set
> the "default" (PINCTRL_STATE_DEFAULT) state for every device
> that is present in the device model right before probe. This will
> account for the lion's share of embedded silicon devcies.
> diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
> @@ -1144,6 +1156,12 @@ PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
>
> This gives the exact same result as the above construction.
>
> +This should not be used for any kind of device which is represented in
> +the device model, as the pinctrl core will attempt to do the equal of
> +pinctrl_get_select_default() for these devices right before their device
> +drivers are probed, so hogging these will just make the model look
> +strange. Instead put in proper map entries.
This is a policy change unrelated to this change. There are good reasons
to use pinctrl hogs for everything except where dynamic changes are
required by drivers. As such, I think the wording above is overly
strong. Preferably, that paragraph should simply not be added.
> diff --git a/drivers/base/pinctrl.c b/drivers/base/pinctrl.c
> +int pinctrl_bind_pins(struct device *dev)
> +{
> + struct dev_pin_info *dpi;
> + int ret;
> +
> + /* Allocate a pin state container on-the-fly */
> + if (!dev->pins) {
This path is guaranteed to be take unless there is a bug. The first time
through, this field will be NULL. If probe fails, the code below
attempts to ensure this field is set back to NULL. As such, we should
simply remove this if condition and always allocate dpi. This would also
remove the requirement to set dev->pins back to NULL below, this
simplifying the code all around, although perhaps it'd be a good idea to
clear out any invalid pointers for clarity either way.
> + dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
> + if (!dpi)
> + return -ENOMEM;
> + } else
> + dpi = dev->pins;
> + /*
> + * Check if we already have a pinctrl handle, as we may arrive here
> + * after a deferral in the state selection below
> + */
> + if (!dpi->p) {
...
> + /*
> + * We may have looked up the state earlier as well.
> + */
> + if (!dpi->default_state) {
The same argument applies to both those if conditions too.
Following on from this, I thought that the code looked OK; all the error
paths set dev->pins=NULL when expected, although I think that the
pinctrl_lookup_state() short-exit path should have cleared dpi->p and
dpi->default_state, so I thought this patch would test out OK. However,
pinctrl_bind_pins() is not the only source of errors during probe(); the
driver itself could fail to probe() due to -EPROBE_DEFER, and that would
then require clearing dev->pins. So in fact, this patch still doesn't
work. Again, this can all be solved simply by removing all the
conditionals in the code that I mention above.
I'll send an updated/tested patch in a minute.
^ permalink raw reply
* [PATCH 02/33] ARM: Convert to devm_ioremap_resource()
From: Greg Kroah-Hartman @ 2013-01-22 17:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130121161611.GS23505@n2100.arm.linux.org.uk>
On Mon, Jan 21, 2013 at 04:16:11PM +0000, Russell King - ARM Linux wrote:
> On Mon, Jan 21, 2013 at 05:05:47PM +0100, Thierry Reding wrote:
> > On Mon, Jan 21, 2013 at 03:58:46PM +0000, Russell King - ARM Linux wrote:
> > > On Mon, Jan 21, 2013 at 11:08:55AM +0100, Thierry Reding wrote:
> > > > Convert all uses of devm_request_and_ioremap() to the newly introduced
> > > > devm_ioremap_resource() which provides more consistent error handling.
> > >
> > > Does this include the resource part of the handling too?
> >
> > I'm not sure I understand your question. devm_ioremap_resource() does a
> > devm_request_mem_region() internally if that's what you were asking.
>
> Ah, that's fine then. The function name is a little misleading, and as
> it doesn't exist in mainline at present, it is not something I know about.
Can I assume this is an Acked-by: from you for this patch so that I can
take this through my driver-core tree?
thanks,
greg k-h
^ permalink raw reply
* One of these things (CONFIG_HZ) is not like the others..
From: Arnd Bergmann @ 2013-01-22 17:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130122145113.GK23505@n2100.arm.linux.org.uk>
On Tuesday 22 January 2013, Russell King - ARM Linux wrote:
> On Tue, Jan 22, 2013 at 03:44:03PM +0530, Santosh Shilimkar wrote:
> > Sorry for not being clear enough. On OMAP, 32KHz is the only clock which
> > is always running(even during low power states) and hence the clock
> > source and clock event have been clocked using 32KHz clock. As mentioned
> > by RMK, with 32768 Hz clock and HZ = 100, there will be always an
> > error of 0.1 %. This accuracy also impacts the timer tick interval.
> > This was the reason, OMAP has been using the HZ = 128.
>
> Ok. Let's look at this. As far as time-of-day is concerned, this
> shouldn't really matter with the clocksource/clockevent based system
> that we now have (where *important point* platforms have been converted
> over.)
>
> Any platform providing a clocksource will override the jiffy-based
> clocksource. The measurement of time-of-day passing is now based on
> the difference in values read from the clocksource, not from the actual
> tick rate.
Ok, that was my reading as well.
> - if the interrupt rate is slightly faster than HZ, then you can end up
> with updates being delayed by 2x interrupt rate.
> - if the interrupt rate is slightly slower than HZ, you can occasionally
> end up with jiffies incrementing by two.
> - if your interrupt rate is dead on HZ, then other system noise can come
> into effect and you may get maybe zero, one or two jiffy increments per
> interrupt.
>
> (You have to think about time passing in NS, where jiffy updates should
> be vs where the timer interrupts happen.) See tick_do_update_jiffies64()
> for the details.
Ah, right. I forgot about this case. So when we have an accurate clocksource,
rather than relying on the timer tick as the sole source for timekeeping,
the jiffies64 variable may be less accurate (up to almost two jiffies
diff, rather than almost one jiffy).
> The timer infrastructure is jiffy based - which includes scheduling where
> the scheduler does not use hrtimers. That means a slight discrepency
> between HZ and the actual interrupt rate can cause around 1/HZ jitter.
> That's a matter of fact due to how the code works.
Yes, the two jiffies accuracy I mentioned above would be the result of
the 1 jiffy jitter plus 1 jiffy from the limited resolution.
> So, actually, I think the accuracy of HZ has much overall effect _provided_
> a platform provides a clocksource to the accuracy of jiffy based timers
> nor timekeeping. For those which don't, the accuracy of the timer
> interrupt to HZ is very important.
This is where I don't see the same problem that you are seeing. Shouldn't
the old ACT_HZ calculation based on CLOCK_TICK_RATE have prevented this?
Note that all PC-like systems traditionally have a CLOCK_TICK_RATE of
1193182 Hz, which does not accurately divide into any of the normal
HZ values, the jiffies clocksource used to have code in it to make
up for this problem. Nowadays, since John's b3c869d35 "jiffies: Remove
compile time assumptions about CLOCK_TICK_RATE" patch in 3.7, the
logic in part of the refined_jiffies clock source that is used currently
only on x86.
I do agree that any platform that is using neither a platform specific
clocksource nor the refined_jiffies would suffer from the drift as
you describe. OMAP was in fact using CLOCK_TICK_RATE correctly, but
is not using the refined_jiffies clocksource now because it has
its own clocksource implementation.
> And I think further discussion is pointless until such research has been
> done (or someone who _really_ knows the time keeping/timer/sched code
> inside out comments.)
Maybe John has some more insights here, he seems to be the one that
understands it better than any of us.
Arnd
^ permalink raw reply
* [PATCH 15/15] staging/omapdrm: don't build on multiplatform
From: Greg Kroah-Hartman @ 2013-01-22 17:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50FEC508.50004@ti.com>
On Tue, Jan 22, 2013 at 10:57:44AM -0600, Rob Clark wrote:
> On 01/22/2013 10:53 AM, Greg Kroah-Hartman wrote:
> >On Mon, Jan 21, 2013 at 12:39:31PM -0600, Rob Clark wrote:
> >>On 01/21/2013 11:41 AM, Arnd Bergmann wrote:
> >>>On Monday 21 January 2013, Rob Clark wrote:
> >>>>Are you sure OMAP2_DSS requires ARCH_OMAP2PLUS? I don't see this, and
> >>>>it at least used to not depend on ARCH_OMAP2PLUS. If it does now, I
> >>>>think the correct fix would be to remove the dependency in OMAP2_DSS. I
> >>>>don't think removing ARCH_MULTIPLATFORM support in omapdrm is the
> >>>>correct solution.
> >>>At least it says so in drivers/video/omap2/Kconfig, which contains
> >>>
> >>>if ARCH_OMAP2PLUS
> >>>source drivers/video/omap2/dss/Kconfig
> >>>endif
> >>ahh, ok, I see.. the if ARCH_OMAP2PLUS bit looks like it came in
> >>recently (770b6cb)
> >>
> >>what about changing this to 'if ARCH_OMAP2PLUS || ARCH_MULTIPLATFORM'?
> >That's what Arnd's patch did.
>
> sorry, I was talking about in drivers/video/omap2/Kconfig
Ah, ok.
> Ie. I'd prefer to re-enable omapdss on multi-plat rather than
> disabling omapdrm. With changes in drm core, it is a bit of a pain
> to compile test all the arm drivers by doing N different builds, so
> we've been trying to get to the point of all arm drm drivers
> supporting multi-plat
Ok, I'll let you and Arnd fight it out and drop this patch from my
to-apply queue for now...
greg k-h
^ permalink raw reply
* [PATCH 3/6] arm: kconfig: don't select TWD with local timer for Armada 370/XP
From: Russell King - ARM Linux @ 2013-01-22 17:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201301221557.02976.arnd@arndb.de>
On Tue, Jan 22, 2013 at 03:57:02PM +0000, Arnd Bergmann wrote:
> On Monday 21 January 2013, Gregory CLEMENT wrote:
> > I don't see a strong reason to not enable it if we don't use it. My concern
> > was that I don't need it so I didn't want to include it and generating extra
> > code for nothing. Then just after having sent this patch set, I received your
> > patch set about build regression in 3.8 and especially the part about
> > CONFIG_MULTIPLATFORM made me realized that it could be a problem.
>
> Ok.
>
> > > Maybe it can be written as
> > >
> > > config LOCAL_TIMERS
> > > bool "Use local timer interrupts"
> > > depends on SMP
> > > default y
> > >
> > > config HAVE_ARM_TWD
> > > depends on LOCAL_TIMERS
> > > default ARCH_MULTIPLATFORM || (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
> >
> > So in this case why not written something like this:
> > default ARCH_MULTIPLATFORM || (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT && !ARMADA_370_XP_TIMER)
>
> That does not change anything, because ARMADA_370_XP_TIMER is only ever enabled
> when ARCH_MULTIPLATFORM is enabled as well.
>
> > > default y
> > I am not a kconfig expert, but won't this line set HAVE_ARM_TWD to 'y' whatever
> > the result of the previous line?
>
> Yes, that was a mistake on my side.
Sigh. No. Wrong.
config HAVE_ARM_TWD
depends on LOCAL_TIMERS
default ARCH_MULTIPLATFORM || (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT && !ARMADA_370_XP_TIMER)
default y
This takes the value of the first enabled default. The first enabled
default is the first default (it's unconditional). So, the default y
will never be used.
Given the above, it's far from clear what the actual behaviour being
asked for is - it looks totally and utterly screwed to me - and the
wrong thing to be doing.
If the desire is to have it enabled if ARCH_MULTIPLATFORM is set, then
it's easy, and requires just a _single_ line addition:
config LOCAL_TIMERS
bool "Use local timer interrupts"
depends on SMP
default y
select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
+ select HAVE_ARM_TWD if ARCH_MULTIPLATFORM
^ permalink raw reply
* [PATCH 3/6] arm: kconfig: don't select TWD with local timer for Armada 370/XP
From: Russell King - ARM Linux @ 2013-01-22 17:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201301212044.41865.arnd@arndb.de>
On Mon, Jan 21, 2013 at 08:44:41PM +0000, Arnd Bergmann wrote:
> Documentation is generally considered a good thing, but few people
> can be bothered to write it, and few of the other people that should
> read it actually do.
Actually _that_ is just one of the problems with documentation. The
whole thing is full of problems:
1. People don't write documentation.
2. People don't bother to update correct documentation when the code
changes in a way that the documentation should be updated for.
3. People don't bother to read documentation which is provided.
(2) is about as bad as it gets - because the small percentage of people
who do read the documentation rather than the code now are lead down
paths which are no longer true.
And (2) educates people to behave like (3). And (3) educates people to
behave like (1) - why should they bother if they're just going to have
to waste time in an email explaining it time and time again (even when
documentation does exist.)
^ permalink raw reply
* ARM: hw_breakpoint mismatch breakpoint behaves unexpectedly like a match breakpoint on ARM_DEBUG_ARCH_V7_ECP14
From: Valentin Pistol @ 2013-01-22 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130122093102.GC12295@mudshark.cambridge.arm.com>
> The ptrace interface doesn't support mismatch breakpoints, and ignores those
> bits in the user request, hence why you see a normal breakpoint being
> created. Note that mismatch breakpoints are used internally for stepping
> over breakpoints set by perf.
>
> If you wanted to add single-step using mismatch breakpoints, I think we'd be
> better off re-introducing the SINGLESTEP ptrace request for ARM to use
> hw_breakpoints.
I noticed your old Feb 2011 post on SINGLESTEP being removed:
http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February/041408.html
So it was managing its own breakpoints and instruction decoding (like
gdb would) but didn't take advantage of either mismatch support or
hw_breakpoints?
Such support seems really useful and yet much more simple if mismatch
is supported.
I definitely would like to use the ptrace and hw-breakpoints interface
instead of avoiding and writing it from scratch, as it takes care of a
lot of details, for instance SMP and context switches, uninstalling
and installing the breakpoints as required.
I'm wondering how pervasive the required changes are to support
SINGLESTEP with mismatch breakpoints.
If you think it's a good idea I'm very willing to try and add-in such support.
Please let me know if there's some obvious issues about going forward
with this that you may be aware of.
Thanks so much!
Valentin
^ permalink raw reply
* [PATCH 1/4] ARM: cache-l2x0: Manage the errata at run time
From: Will Deacon @ 2013-01-22 17:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130122054227.GA5594@bnru10>
On Tue, Jan 22, 2013 at 05:42:29AM +0000, Srinidhi Kasagar wrote:
> On Mon, Jan 21, 2013 at 15:03:44 +0100, Will Deacon wrote:
> > On Mon, Jan 21, 2013 at 01:14:53PM +0000, srinidhi kasagar wrote:
> > > +asmlinkage u32 l2x0_get_rtl_release(void)
> > > +{
> > > + return readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
> > > + L2X0_CACHE_ID_RTL_MASK;
> > > +}
> >
> > You're calling this function all over the place, including from the flush
> > code. Can you read the RTL release during probe and stash it somewhere
> > instead please?
>
> I thought of doing that, however TI omap's suspend is the only one which needs
> this API as well, So, I had to make it global. Refer my patch 3/4. I can
> duplicate this for omap if you think so..
Just make the get_rtl_release_function return the stashed value if it's been
probed and get the driver to use the stashed value directly.
Will
^ permalink raw reply
* [v3 2/2] ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9
From: Olof Johansson @ 2013-01-22 17:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50FEC503.2080602@wwwdotorg.org>
On Tue, Jan 22, 2013 at 8:57 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 01/21/2013 11:07 PM, Santosh Shilimkar wrote:
>> On Tuesday 22 January 2013 11:22 AM, Hiroshi Doyu wrote:
>>> Skip scu_enable(scu_base) if CPU is not Cortex A9 with SCU.
>>>
>>> Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
>>> ---
>> Looks fine. I will also update OMAP code with the new
>> interface. Thanks.
>
> OK, so patch 1/2 at least needs to get into a stable arm-soc branch
> then. Unless there are violent objections, I'll forward patch 1/2 to
> arm-soc and request it be added into a branch so that Tegra and OMAP can
> both merge it into their branches as a dependency. I guess patch 2/2
> could also be included; I don't think it has any complex dependencies
> that'd prevent that, and would help to show how patch 1/2 gets used.
>
> Hiroshi, is this series the only dependency you need for your Tegra114
> series? So, I could merge your Tegra114 series once this series is applied?
For something like this, it might make more sense for us to just apply
the patches for OMAP on top, i.e. we'll pull the short branch from
you, and then we can just apply patches (with maintainer acks) on top,
instead of doing a bunch of single-patch pulls.
Since Russell had comments on it earlier, I'd like him to give a nod
that he's happy with it too.
-Olof
^ permalink raw reply
* [PATCH v1 0/6] USB: Add support for multiple PHYs of same type
From: Koen Kooi @ 2013-01-22 17:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50FEBB61.9000707@ti.com>
Op 22 jan. 2013, om 17:16 heeft kishon <kishon@ti.com> het volgende geschreven:
> Hi,
>
> On Tuesday 22 January 2013 09:15 PM, kishon wrote:
>> On Tuesday 22 January 2013 09:11 PM, Koen Kooi wrote:
>>>
>>> Op 22 jan. 2013, om 10:58 heeft Kishon Vijay Abraham I <kishon@ti.com>
>>> het volgende geschreven:
>>>
>>>> This patch series adds support for adding multiple PHY's (of same type).
>>>> The binding information has to be present in the PHY library (otg.c) in
>>>> order for it to return the appropriate PHY whenever the USB controller
>>>> request for the PHY. So added a new API usb_bind_phy() to pass the
>>>> binding
>>>> information. This API should be called by platform specific
>>>> initialization
>>>> code.
>>>>
>>>> So the binding should be done something like
>>>> usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto"); specifying
>>>> the USB
>>>> controller device name, index, and the PHY device name.
>>>> I have done this binding for OMAP platforms, but it should be done for
>>>> all the platforms.
>>>>
>>>> After this design, the phy can be got by passing the USB controller
>>>> device
>>>> pointer and the index.
>>>>
>>>> Developed this patch series on
>>>> git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git xceiv
>>>> after applying "usb: musb: add driver for control module" patch series
>>>> and "ARM: dts: omap: add dt data for MUSB"
>>>>
>>>> Did basic enumeration testing in omap4 panda and omap3 beagle.
>>>
>>> With this patchset USB completely breaks on am33xx beaglebone, is that
>>> intended?
>> Not really.
>> Does am33xx makes use of omap2430.c? Which PHY does am33xx uses?
>
> I figured out it uses drivers/usb/musb/musb_dsps.c (So it doesn't use omap2430.c). I think it uses TWL4030_USB (TPS659x0) as PHY.
Actually it uses nop-phy as a phy, which is missing from arch/arm/boot/dts/am33xx.dtsi, so mainline is already broken. But adding the nop-phy to the DT is easy enough to patch in locally.
regards,
Koen
^ permalink raw reply
* [PATCH 15/15] staging/omapdrm: don't build on multiplatform
From: Rob Clark @ 2013-01-22 16:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130122165330.GA28152@kroah.com>
On 01/22/2013 10:53 AM, Greg Kroah-Hartman wrote:
> On Mon, Jan 21, 2013 at 12:39:31PM -0600, Rob Clark wrote:
>> On 01/21/2013 11:41 AM, Arnd Bergmann wrote:
>>> On Monday 21 January 2013, Rob Clark wrote:
>>>> Are you sure OMAP2_DSS requires ARCH_OMAP2PLUS? I don't see this, and
>>>> it at least used to not depend on ARCH_OMAP2PLUS. If it does now, I
>>>> think the correct fix would be to remove the dependency in OMAP2_DSS. I
>>>> don't think removing ARCH_MULTIPLATFORM support in omapdrm is the
>>>> correct solution.
>>> At least it says so in drivers/video/omap2/Kconfig, which contains
>>>
>>> if ARCH_OMAP2PLUS
>>> source drivers/video/omap2/dss/Kconfig
>>> endif
>> ahh, ok, I see.. the if ARCH_OMAP2PLUS bit looks like it came in
>> recently (770b6cb)
>>
>> what about changing this to 'if ARCH_OMAP2PLUS || ARCH_MULTIPLATFORM'?
> That's what Arnd's patch did.
sorry, I was talking about in drivers/video/omap2/Kconfig
Ie. I'd prefer to re-enable omapdss on multi-plat rather than disabling
omapdrm. With changes in drm core, it is a bit of a pain to compile
test all the arm drivers by doing N different builds, so we've been
trying to get to the point of all arm drm drivers supporting multi-plat
BR,
-R
> totally confused,
>
> greg k-h
^ permalink raw reply
* [v3 2/2] ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9
From: Stephen Warren @ 2013-01-22 16:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50FE2CA8.20100@ti.com>
On 01/21/2013 11:07 PM, Santosh Shilimkar wrote:
> On Tuesday 22 January 2013 11:22 AM, Hiroshi Doyu wrote:
>> Skip scu_enable(scu_base) if CPU is not Cortex A9 with SCU.
>>
>> Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
>> ---
> Looks fine. I will also update OMAP code with the new
> interface. Thanks.
OK, so patch 1/2 at least needs to get into a stable arm-soc branch
then. Unless there are violent objections, I'll forward patch 1/2 to
arm-soc and request it be added into a branch so that Tegra and OMAP can
both merge it into their branches as a dependency. I guess patch 2/2
could also be included; I don't think it has any complex dependencies
that'd prevent that, and would help to show how patch 1/2 gets used.
Hiroshi, is this series the only dependency you need for your Tegra114
series? So, I could merge your Tegra114 series once this series is applied?
> For the patch,
> Acked-by: Santosh Shilimkar<santosh.shilimkar@ti.com>
Thanks.
^ permalink raw reply
* [PATCH 1/6] arm: mvebu: Add support for local interrupt
From: Thomas Petazzoni @ 2013-01-22 16:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50FE572F.4090402@free-electrons.com>
Dear Gregory CLEMENT,
On Tue, 22 Jan 2013 10:09:03 +0100, Gregory CLEMENT wrote:
> You're right!
> I would have liked to say I have done it on purpose, but in fact these
> braces are here only because during development I had had multiples lines
> inside the else.
> However, as you pointed it, I will keep it.
ACK, fine. Didn't know about this specific point of the CodingStyle.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 15/15] staging/omapdrm: don't build on multiplatform
From: Greg Kroah-Hartman @ 2013-01-22 16:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50FD8B63.1060506@ti.com>
On Mon, Jan 21, 2013 at 12:39:31PM -0600, Rob Clark wrote:
> On 01/21/2013 11:41 AM, Arnd Bergmann wrote:
> >On Monday 21 January 2013, Rob Clark wrote:
> >>Are you sure OMAP2_DSS requires ARCH_OMAP2PLUS? I don't see this, and
> >>it at least used to not depend on ARCH_OMAP2PLUS. If it does now, I
> >>think the correct fix would be to remove the dependency in OMAP2_DSS. I
> >>don't think removing ARCH_MULTIPLATFORM support in omapdrm is the
> >>correct solution.
> >At least it says so in drivers/video/omap2/Kconfig, which contains
> >
> >if ARCH_OMAP2PLUS
> >source drivers/video/omap2/dss/Kconfig
> >endif
>
> ahh, ok, I see.. the if ARCH_OMAP2PLUS bit looks like it came in
> recently (770b6cb)
>
> what about changing this to 'if ARCH_OMAP2PLUS || ARCH_MULTIPLATFORM'?
That's what Arnd's patch did.
totally confused,
greg k-h
^ permalink raw reply
* [PATCH 4/4] ARM: AM33XX: clock: SET_RATE_PARENT in lcd path
From: Afzal Mohammed @ 2013-01-22 16:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1358871018.git.afzal@ti.com>
LCDC clock node is a one that does not have set rate capability. It
just passes on the rate that is sent downstream by it's parent. While
lcdc clock parent and it's grand parent - dpll_disp_m2_ck and
dpll_disp_ck has the capability to configure rate.
And the default rates provided by LCDC clock's ancestors are not
sufficient to obtain pixel clock for current LCDC use cases, hence
currently display would not work on AM335x SoC's (with driver
modifications in platfrom independent way).
Hence inform clock framework to propogate set rate for LCDC clock as
well as it's parent - dpll_disp_m2_ck. With this change, set rate on
LCDC clock would get propogated till dpll_disp_ck via dpll_disp_m2_ck,
hence allowing the driver (same driver is used in DaVinci too) to set
rates using LCDC clock without worrying about platform dependent clock
details.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/cclock33xx_data.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 8f7c60d..0519e91 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -286,10 +286,10 @@ DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
* TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
* and ALT_CLK1/2)
*/
-DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0,
- AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
- CLK_DIVIDER_ONE_BASED, NULL);
+DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
+ CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
+ AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
/* DPLL_PER */
static struct dpll_data dpll_per_dd = {
@@ -726,7 +726,8 @@ static struct clk_hw_omap lcd_gclk_hw = {
.clksel_mask = AM33XX_CLKSEL_0_1_MASK,
};
-DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops);
+DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
+ gpio_fck_ops, CLK_SET_RATE_PARENT);
DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
--
1.7.12
^ permalink raw reply related
* [PATCH 3/4] ARM: OMAP2+: clock: DEFINE_STRUCT_CLK_FLAGS helper
From: Afzal Mohammed @ 2013-01-22 16:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1358871018.git.afzal@ti.com>
DEFINE_STRUCT_CLK does not have the capability to set flags, define
DEFINE_STRUCT_CLK_FLAGS to handle flags. This is needed to add
SET_RATE_PARENT flag in statically defined lcd clock in am335x.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/clock.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b402048..60ddd86 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,17 @@ struct clockdomain;
.ops = &_clkops_name, \
};
+#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
+ _clkops_name, _flags) \
+ static struct clk _name = { \
+ .name = #_name, \
+ .hw = &_name##_hw.hw, \
+ .parent_names = _parent_array_name, \
+ .num_parents = ARRAY_SIZE(_parent_array_name), \
+ .ops = &_clkops_name, \
+ .flags = _flags, \
+ };
+
#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
static struct clk_hw_omap _name##_hw = { \
.hw = { \
--
1.7.12
^ permalink raw reply related
* [PATCH 2/4] ARM: OMAP2+: dpll: am335x - avoid freqsel
From: Afzal Mohammed @ 2013-01-22 16:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1358871018.git.afzal@ti.com>
am335x does not have freqsel, avoid it.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/dpll3xxx.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 0a02aab5..3aed4b0 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -500,8 +500,9 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
if (dd->last_rounded_rate == 0)
return -EINVAL;
- /* No freqsel on OMAP4 and OMAP3630 */
- if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+ /* No freqsel on AM335x, OMAP4 and OMAP3630 */
+ if (!soc_is_am33xx() && !cpu_is_omap44xx() &&
+ !cpu_is_omap3630()) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n);
WARN_ON(!freqsel);
--
1.7.12
^ permalink raw reply related
* [PATCH 1/4] ARM: OMAP2+: dpll: round rate to closest value
From: Afzal Mohammed @ 2013-01-22 16:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1358871018.git.afzal@ti.com>
Currently round rate function would return proper rate iff requested
rate exactly matches the PLL lockable rate. This causes set_rate to
fail if exact rate could not be set. Instead round rate may return
closest rate possible (less than the requested). And if any user is
badly in need of exact rate, then return value of round rate could
be used to decide whether to invoke set rate or not.
Modify round rate so that it return closest possible rate.
This was required to get display working on am335x. Without this
display rate could not be set (taking help of SET_RATE_PARENT). Couple
of the downstream clocks of display PLL are basic clock dividers and
they do MULT_ROUND_UP before requesting rate on PLL causing values
that mostly could not be locked by PLL. And even otherwise, if
requested rate for a particular pixel clock could not be satisfied by
PLL, display would not work. This change will resolve the issue.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/clkt_dpll.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 924c230..15e6d41 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -345,20 +345,22 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
clk_name, m, n, new_rate);
- if (target_rate == new_rate) {
+ if ((new_rate <= target_rate) &&
+ (new_rate > dd->last_rounded_rate)) {
dd->last_rounded_m = m;
dd->last_rounded_n = n;
- dd->last_rounded_rate = target_rate;
- break;
+ dd->last_rounded_rate = new_rate;
+ if (new_rate == target_rate)
+ break;
}
}
- if (target_rate != new_rate) {
+ if (!dd->last_rounded_rate) {
pr_debug("clock: %s: cannot round to rate %ld\n",
clk_name, target_rate);
return ~0;
}
- return target_rate;
+ return dd->last_rounded_rate;
}
--
1.7.12
^ permalink raw reply related
* [PATCH 0/4] ARM: AM335x: LCDC platform support
From: Afzal Mohammed @ 2013-01-22 16:44 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This series make am335x lcdc capable of providing display.
Certain changes were required in generic OMAP clock handling
to attain it. Clock nodes in LCDC path is marked such that
rate can get propogated to upstream clocks till display PLL.
Based on 3.8-rc3.
Tested on AM335x EVM.
To test on AM335x based boards, tree
@ git://gitorious.org/x0148406-public/linux-kernel.git tags/da8xx-fb-dt-v3
Regards
Afzal
Afzal Mohammed (4):
ARM: OMAP2+: dpll: round rate to closest value
ARM: OMAP2+: dpll: am335x - avoid freqsel
ARM: OMAP2+: clock: DEFINE_STRUCT_CLK_FLAGS helper
ARM: AM33XX: clock: SET_RATE_PARENT in lcd path
arch/arm/mach-omap2/cclock33xx_data.c | 11 ++++++-----
arch/arm/mach-omap2/clkt_dpll.c | 12 +++++++-----
arch/arm/mach-omap2/clock.h | 11 +++++++++++
arch/arm/mach-omap2/dpll3xxx.c | 5 +++--
4 files changed, 27 insertions(+), 12 deletions(-)
--
1.7.12
^ permalink raw reply
* [PATCH 2/2] clk: divider: handle minimum divider
From: Afzal Mohammed @ 2013-01-22 16:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d20165dfc67970c3429b9d95ac9631015f8b2396.1358870920.git.afzal@ti.com>
Some of clocks can have a limit on minimum divider value that can be
programmed. Modify basic clock divider to take care of this aspect.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
drivers/clk/clk-divider.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 0b34992..2de9ff5 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -32,6 +32,11 @@
#define div_mask(d) ((1 << (d->width)) - 1)
#define is_power_of_two(i) !(i & ~i)
+static unsigned int _get_mindiv(struct clk_divider *divider)
+{
+ return divider->min_div;
+}
+
static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
{
unsigned int maxdiv = 0;
@@ -148,17 +153,18 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
{
struct clk_divider *divider = to_clk_divider(hw);
int i, bestdiv = 0;
- unsigned long parent_rate, best = 0, now, maxdiv;
+ unsigned long parent_rate, best = 0, now, maxdiv, mindiv;
if (!rate)
rate = 1;
maxdiv = _get_maxdiv(divider);
+ mindiv = _get_mindiv(divider);
if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
parent_rate = *best_parent_rate;
bestdiv = DIV_ROUND_UP(parent_rate, rate);
- bestdiv = bestdiv == 0 ? 1 : bestdiv;
+ bestdiv = bestdiv == 0 ? mindiv : bestdiv;
bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
return bestdiv;
}
@@ -169,7 +175,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
*/
maxdiv = min(ULONG_MAX / rate, maxdiv);
- for (i = 1; i <= maxdiv; i++) {
+ for (i = mindiv; i <= maxdiv; i++) {
if (!_is_valid_div(divider, i))
continue;
parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
--
1.7.12
^ permalink raw reply related
* [PATCH 1/2] clk: divider: prepare for minimum divider
From: Afzal Mohammed @ 2013-01-22 16:39 UTC (permalink / raw)
To: linux-arm-kernel
Some of clocks can have a limit on minimum divider value that can be
programmed, prepare for such a support.
Add a new field min_div for the basic divider clock. Enhance runtime
registration and static definition helper of basic clock divider so
that minimum divider value can be specified and modify all call sites.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
---
Based on v3.8-rc3, tested on am335x evm.
arch/arm/mach-imx/clk-imx6q.c | 4 +-
arch/arm/mach-imx/clk.h | 4 +-
arch/arm/mach-omap2/cclock2420_data.c | 12 +++---
arch/arm/mach-omap2/cclock2430_data.c | 9 ++--
arch/arm/mach-omap2/cclock33xx_data.c | 25 ++++++-----
arch/arm/mach-omap2/cclock3xxx_data.c | 49 +++++++++++----------
arch/arm/mach-omap2/cclock44xx_data.c | 81 +++++++++++++++++++++--------------
drivers/clk/clk-divider.c | 13 +++---
drivers/clk/clk-ls1x.c | 9 ++--
drivers/clk/mmp/clk-mmp2.c | 24 +++++++----
drivers/clk/mmp/clk-pxa168.c | 3 +-
drivers/clk/mmp/clk-pxa910.c | 3 +-
drivers/clk/spear/spear3xx_clock.c | 6 ++-
include/linux/clk-private.h | 16 ++++---
include/linux/clk-provider.h | 7 ++-
15 files changed, 159 insertions(+), 106 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 7f2c10c..aa901b2 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -218,8 +218,8 @@ int __init mx6q_clocks_init(void)
clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
- base + 0xe0, 0, 2, 0, clk_enet_ref_table,
- &imx_ccm_lock);
+ base + 0xe0, 0, 2, CLK_DIVIDER_MIN_DIV_DEFAULT, 0,
+ clk_enet_ref_table, &imx_ccm_lock);
/* name parent_name reg idx */
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 9d1f3b9..d09e821 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -56,7 +56,9 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
void __iomem *reg, u8 shift, u8 width)
{
return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
- reg, shift, width, 0, &imx_ccm_lock);
+ reg, shift, width,
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0,
+ &imx_ccm_lock);
}
static inline struct clk *imx_clk_gate(const char *name, const char *parent,
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
index 7e5febe..2a3d030 100644
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -146,12 +146,12 @@ DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk aes_ick;
@@ -1226,7 +1226,7 @@ DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops);
DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk mpu_wdt_fck;
@@ -1470,7 +1470,8 @@ DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
- OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+ OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL,
@@ -1480,7 +1481,8 @@ DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0,
OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT,
- OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+ OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
static struct clk uart1_fck;
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index eda079b..4b94eff 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -146,12 +146,12 @@ DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk aes_ick;
@@ -1402,7 +1402,7 @@ DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops);
DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk mpu_wdt_fck;
@@ -1645,7 +1645,8 @@ DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
- OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+ OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
static struct clk uart1_fck;
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index ea64ad6..8f7c60d 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -137,20 +137,21 @@ DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
- AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
+ AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH,
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED,
NULL);
DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
/* DPLL_MPU */
@@ -198,7 +199,8 @@ DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
*/
DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+ AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, NULL);
/* DPLL_DDR */
static struct dpll_data dpll_ddr_dd = {
@@ -244,7 +246,7 @@ DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
/* emif_fck functional clock */
DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
@@ -286,7 +288,8 @@ DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
*/
DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0,
AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+ AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, NULL);
/* DPLL_PER */
static struct dpll_data dpll_per_dd = {
@@ -322,8 +325,8 @@ DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
/* CLKOUT: fdpll/M2 */
DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
- NULL);
+ AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
&dpll_per_m2_ck, 0x0, 1, 4);
@@ -759,7 +762,8 @@ static const struct clk_div_table div_1_0_2_1_rates[] = {
DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
&gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
- 0x0, div_1_0_2_1_rates, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0x0,
+ div_1_0_2_1_rates, NULL);
static const char *sysclkout_ck_parents[] = {
"clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
@@ -803,7 +807,8 @@ static const struct clk_div_table div8_rates[] = {
DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
- AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
+ AM33XX_CLKOUT2DIV_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0x0, div8_rates, NULL);
DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 6ef8758..c04ce02 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -84,7 +84,8 @@ DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
- OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+ OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, NULL);
static struct dpll_data dpll3_dd = {
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -135,7 +136,7 @@ DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk core_ck;
@@ -151,12 +152,12 @@ DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk security_l4_ick2;
@@ -277,7 +278,7 @@ DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk mpu_ck;
@@ -291,7 +292,7 @@ DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
- 0x0, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0x0, NULL);
static struct clk cam_ick;
@@ -384,7 +385,7 @@ DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dpll4_m5x2_ck;
@@ -463,7 +464,7 @@ static const struct clksel_rate clkout2_src_96m_rates[] = {
DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dpll4_m2x2_ck;
@@ -519,7 +520,7 @@ static const struct clksel_rate clkout2_src_54m_rates[] = {
DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dpll4_m3x2_ck;
@@ -754,7 +755,7 @@ DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dpll2_fck;
@@ -797,18 +798,18 @@ DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dpll3_m3x2_ck;
@@ -842,7 +843,7 @@ DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dpll4_m4x2_ck;
@@ -874,7 +875,7 @@ static struct clk dpll4_m4x2_ck_3630 = {
DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dpll4_m6x2_ck;
@@ -943,7 +944,7 @@ DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dss1_alwon_fck_3430es1;
@@ -1188,7 +1189,7 @@ DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk fac_ick;
@@ -1239,7 +1240,7 @@ DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk gfx_cg1_ck;
@@ -2462,12 +2463,12 @@ DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk per_48m_fck;
@@ -2499,7 +2500,7 @@ DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
- CLK_DIVIDER_ONE_BASED, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk rng_ick;
@@ -2780,7 +2781,8 @@ DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
- OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+ OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
@@ -2790,7 +2792,8 @@ DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_CLKSEL_TRACECLK_SHIFT,
- OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+ OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, NULL);
static struct clk ts_fck;
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 5789a5e..69dd52e 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -201,13 +201,14 @@ DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
- OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+ OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
OMAP4430_CM1_ABE_AESS_CLKCTRL,
OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
- 0x0, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0x0, NULL);
DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
@@ -294,15 +295,18 @@ DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
- OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
+ OMAP4430_CLKSEL_CORE_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0x0, NULL);
DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
- OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+ OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
- OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+ OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
&dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
@@ -313,7 +317,8 @@ DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
- OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+ OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, NULL);
static const struct clk_ops dmic_fck_ops = {
.enable = &omap2_dflt_clk_enable,
@@ -509,7 +514,8 @@ DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
- OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+ OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, NULL);
static const char *dpll_per_x2_ck_parents[] = {
"dpll_per_ck",
@@ -653,8 +659,8 @@ static const struct clk_div_table func_48m_fclk_rates[] = {
};
DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
- NULL);
+ OMAP4430_SCALE_FCLK_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0x0, func_48m_fclk_rates, NULL);
DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
0x0, 1, 4);
@@ -666,8 +672,8 @@ static const struct clk_div_table func_64m_fclk_rates[] = {
};
DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
- NULL);
+ OMAP4430_SCALE_FCLK_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0x0, func_64m_fclk_rates, NULL);
static const struct clk_div_table func_96m_fclk_rates[] = {
{ .div = 2, .val = 0 },
@@ -676,8 +682,8 @@ static const struct clk_div_table func_96m_fclk_rates[] = {
};
DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
- NULL);
+ OMAP4430_SCALE_FCLK_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0x0, func_96m_fclk_rates, NULL);
static const struct clk_div_table init_60m_fclk_rates[] = {
{ .div = 1, .val = 0 },
@@ -687,15 +693,18 @@ static const struct clk_div_table init_60m_fclk_rates[] = {
DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
- 0x0, init_60m_fclk_rates, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0x0,
+ init_60m_fclk_rates, NULL);
DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
- OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
+ OMAP4430_CLKSEL_L3_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0x0, NULL);
DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
- OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
+ OMAP4430_CLKSEL_L4_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0x0, NULL);
DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
0x0, 1, 16);
@@ -717,18 +726,21 @@ DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
OMAP4430_CM1_ABE_AESS_CLKCTRL,
OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
- 0x0, ocp_abe_iclk_rates, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0x0,
+ ocp_abe_iclk_rates, NULL);
DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
0x0, 1, 4);
DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
- OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
+ OMAP4430_SCALE_FCLK_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0x0, NULL);
DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
- OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
+ OMAP4430_CLKSEL_0_0_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0x0, NULL);
static const char *dbgclk_mux_ck_parents[] = {
"sys_clkin_ck"
@@ -766,8 +778,9 @@ static const struct clk_div_table div_ts_ck_rates[] = {
DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
OMAP4430_CLKSEL_24_25_SHIFT,
- OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
- NULL);
+ OMAP4430_CLKSEL_24_25_WIDTH,
+ CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0x0, div_ts_ck_rates, NULL);
DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
@@ -847,7 +860,8 @@ DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
- OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+ OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0,
OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
@@ -929,8 +943,8 @@ DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0,
DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
- OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
+ OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
OMAP4430_CM_L4PER_I2C1_CLKCTRL,
@@ -1506,7 +1520,7 @@ static const struct clk_div_table usim_ck_rates[] = {
DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
OMAP4430_CM_WKUP_USIM_CLKCTRL,
OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
- 0x0, usim_ck_rates, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0x0, usim_ck_rates, NULL);
DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
@@ -1541,8 +1555,9 @@ DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
&pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
- OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
- NULL);
+ OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH,
+ CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
static const char *trace_clk_div_ck_parents[] = {
"pmd_trace_clk_mux_ck",
@@ -1605,7 +1620,7 @@ DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0x0, NULL);
DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
@@ -1614,7 +1629,7 @@ DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0x0, NULL);
DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
@@ -1623,7 +1638,7 @@ DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0x0, NULL);
DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
@@ -1632,7 +1647,7 @@ DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0x0, NULL);
DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
@@ -1641,7 +1656,7 @@ DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0x0, NULL);
DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
@@ -1650,7 +1665,7 @@ DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
- 0x0, NULL);
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0x0, NULL);
static const char *auxclkreq_ck_parents[] = {
"auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index a9204c6..0b34992 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -236,7 +236,7 @@ EXPORT_SYMBOL_GPL(clk_divider_ops);
static struct clk *_register_divider(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
- void __iomem *reg, u8 shift, u8 width,
+ void __iomem *reg, u8 shift, u8 width, u8 min_div,
u8 clk_divider_flags, const struct clk_div_table *table,
spinlock_t *lock)
{
@@ -261,6 +261,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
div->reg = reg;
div->shift = shift;
div->width = width;
+ div->min_div = min_div;
div->flags = clk_divider_flags;
div->lock = lock;
div->hw.init = &init;
@@ -284,16 +285,17 @@ static struct clk *_register_divider(struct device *dev, const char *name,
* @reg: register address to adjust divider
* @shift: number of bits to shift the bitfield
* @width: width of the bitfield
+ * @min_div: minimum allowable divider value
* @clk_divider_flags: divider-specific flags for this clock
* @lock: shared register lock for this clock
*/
struct clk *clk_register_divider(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
- void __iomem *reg, u8 shift, u8 width,
+ void __iomem *reg, u8 shift, u8 width, u8 min_div,
u8 clk_divider_flags, spinlock_t *lock)
{
return _register_divider(dev, name, parent_name, flags, reg, shift,
- width, clk_divider_flags, NULL, lock);
+ width, min_div, clk_divider_flags, NULL, lock);
}
/**
@@ -306,16 +308,17 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
* @reg: register address to adjust divider
* @shift: number of bits to shift the bitfield
* @width: width of the bitfield
+ * @min_div: minimum allowable divider value
* @clk_divider_flags: divider-specific flags for this clock
* @table: array of divider/value pairs ending with a div set to 0
* @lock: shared register lock for this clock
*/
struct clk *clk_register_divider_table(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
- void __iomem *reg, u8 shift, u8 width,
+ void __iomem *reg, u8 shift, u8 width, u8 min_div,
u8 clk_divider_flags, const struct clk_div_table *table,
spinlock_t *lock)
{
return _register_divider(dev, name, parent_name, flags, reg, shift,
- width, clk_divider_flags, table, lock);
+ width, min_div, clk_divider_flags, table, lock);
}
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
index f20b750..ee844aa 100644
--- a/drivers/clk/clk-ls1x.c
+++ b/drivers/clk/clk-ls1x.c
@@ -87,19 +87,22 @@ void __init ls1x_clk_init(void)
clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
- DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+ DIV_CPU_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, &_lock);
clk_prepare_enable(clk);
clk_register_clkdev(clk, "cpu", NULL);
clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
- DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+ DIV_DC_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, &_lock);
clk_prepare_enable(clk);
clk_register_clkdev(clk, "dc", NULL);
clk = clk_register_divider(NULL, "ahb_clk", "pll_clk",
CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
- DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+ DIV_DDR_WIDTH, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, &_lock);
clk_prepare_enable(clk);
clk_register_clkdev(clk, "ahb", NULL);
clk_register_clkdev(clk, "stmmaceth", NULL);
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
index ade4358..4f34ca6 100644
--- a/drivers/clk/mmp/clk-mmp2.c
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -330,7 +330,8 @@ void __init mmp2_clk_init(void)
clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
- 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+ 10, 4, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, &clk_lock);
clk_register_clkdev(clk, "sdh_div", NULL);
clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
@@ -360,7 +361,8 @@ void __init mmp2_clk_init(void)
clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
- 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+ 8, 4, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, &clk_lock);
clk_register_clkdev(clk, "disp_div.0", NULL);
clk = mmp_clk_register_apmu("disp0", "disp0_div",
@@ -368,7 +370,8 @@ void __init mmp2_clk_init(void)
clk_register_clkdev(clk, NULL, "mmp-disp.0");
clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
- apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
+ apmu_base + APMU_DISP0, 15, 5,
+ CLK_DIVIDER_MIN_DIV_DEFAULT, 0, &clk_lock);
clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
@@ -382,7 +385,8 @@ void __init mmp2_clk_init(void)
clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
- 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+ 8, 4, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, &clk_lock);
clk_register_clkdev(clk, "disp_div.1", NULL);
clk = mmp_clk_register_apmu("disp1", "disp1_div",
@@ -400,7 +404,8 @@ void __init mmp2_clk_init(void)
clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
- 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+ 17, 4, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, &clk_lock);
clk_register_clkdev(clk, "ccic_div.0", NULL);
clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
@@ -413,7 +418,8 @@ void __init mmp2_clk_init(void)
clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
- 10, 5, 0, &clk_lock);
+ 10, 5, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0, &clk_lock);
clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
@@ -427,7 +433,8 @@ void __init mmp2_clk_init(void)
clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
- 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+ 16, 4, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ CLK_DIVIDER_ONE_BASED, &clk_lock);
clk_register_clkdev(clk, "ccic_div.1", NULL);
clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
@@ -440,7 +447,8 @@ void __init mmp2_clk_init(void)
clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
- 10, 5, 0, &clk_lock);
+ 10, 5, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0, &clk_lock);
clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
index e8d036c..95ea167 100644
--- a/drivers/clk/mmp/clk-pxa168.c
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -337,7 +337,8 @@ void __init pxa168_clk_init(void)
clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
- 10, 5, 0, &clk_lock);
+ 10, 5, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0, &clk_lock);
clk_register_clkdev(clk, "sphyclk_div", NULL);
clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
index 7048c31..367cc1a 100644
--- a/drivers/clk/mmp/clk-pxa910.c
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -311,7 +311,8 @@ void __init pxa910_clk_init(void)
clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
- 10, 5, 0, &clk_lock);
+ 10, 5, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0, &clk_lock);
clk_register_clkdev(clk, "sphyclk_div", NULL);
clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index 33d3ac5..bee26ce 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -407,7 +407,8 @@ void __init spear3xx_clk_init(void)
clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
- HCLK_RATIO_MASK, 0, &_lock);
+ HCLK_RATIO_MASK, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0, &_lock);
clk_register_clkdev(clk, "ahb_clk", NULL);
clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
@@ -536,7 +537,8 @@ void __init spear3xx_clk_init(void)
clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
- PCLK_RATIO_MASK, 0, &_lock);
+ PCLK_RATIO_MASK, CLK_DIVIDER_MIN_DIV_DEFAULT,
+ 0, &_lock);
clk_register_clkdev(clk, "apb_clk", NULL);
clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 9c7f580..8370b81 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -105,7 +105,8 @@ struct clk {
#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
_flags, _reg, _shift, _width, \
- _divider_flags, _table, _lock) \
+ _min_div, _divider_flags, \
+ _table, _lock) \
static struct clk _name; \
static const char *_name##_parent_names[] = { \
_parent_name, \
@@ -120,6 +121,7 @@ struct clk {
.reg = _reg, \
.shift = _shift, \
.width = _width, \
+ .min_div = _min_div, \
.flags = _divider_flags, \
.table = _table, \
.lock = _lock, \
@@ -129,18 +131,20 @@ struct clk {
#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
_flags, _reg, _shift, _width, \
- _divider_flags, _lock) \
+ _min_div, _divider_flags, _lock)\
_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
_flags, _reg, _shift, _width, \
- _divider_flags, NULL, _lock)
+ _min_div, _divider_flags, \
+ NULL, _lock)
#define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name, \
_parent_ptr, _flags, _reg, \
- _shift, _width, _divider_flags, \
- _table, _lock) \
+ _shift, _width, _min_div, \
+ _divider_flags, _table, _lock) \
_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
_flags, _reg, _shift, _width, \
- _divider_flags, _table, _lock) \
+ _min_div, _divider_flags, \
+ _table, _lock)
#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
_reg, _shift, _width, \
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 4989b8a..655dc2b 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -248,22 +248,25 @@ struct clk_divider {
void __iomem *reg;
u8 shift;
u8 width;
+ u8 min_div;
u8 flags;
const struct clk_div_table *table;
spinlock_t *lock;
};
+#define CLK_DIVIDER_MIN_DIV_DEFAULT 1
+
#define CLK_DIVIDER_ONE_BASED BIT(0)
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
extern const struct clk_ops clk_divider_ops;
struct clk *clk_register_divider(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
- void __iomem *reg, u8 shift, u8 width,
+ void __iomem *reg, u8 shift, u8 width, u8 min_div,
u8 clk_divider_flags, spinlock_t *lock);
struct clk *clk_register_divider_table(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
- void __iomem *reg, u8 shift, u8 width,
+ void __iomem *reg, u8 shift, u8 width, u8 min_div,
u8 clk_divider_flags, const struct clk_div_table *table,
spinlock_t *lock);
--
1.7.12
^ permalink raw reply related
* [PATCH] clk: Deduplicate exit code in clk_set_rate
From: Mike Turquette @ 2013-01-22 16:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358525259-7979-1-git-send-email-novroy@riseup.net>
Quoting Nestor Ovroy (2013-01-18 08:07:39)
> On non-out case 'return ret;' is equivalent to 'return 0;' as the ret
> variable is initialized at 0 and never changed.
>
> Signed-off-by: Nestor Ovroy <novroy@riseup.net>
Nestor,
Thanks for the fix. Taken into clk-next.
Regards,
Mike
> ---
> drivers/clk/clk.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 251e45d..0e21d7a 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -948,13 +948,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
> }
>
> /* change the rates */
> clk_change_rate(top);
>
> - mutex_unlock(&prepare_lock);
> -
> - return 0;
> out:
> mutex_unlock(&prepare_lock);
>
> return ret;
> }
> --
> 1.7.10.4
^ permalink raw reply
* [PATCH] ARM: mxs: dt: Add Crystalfontz CFA-10037 device tree support
From: Maxime Ripard @ 2013-01-22 16:35 UTC (permalink / raw)
To: linux-arm-kernel
The CFA-10037 is another expansion board for the CFA-10036 module, with
only a USB Host, a Ethernet device and a lot of gpios.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/imx28-cfa10037.dts | 77 ++++++++++++++++++++++++++++++++++
arch/arm/mach-mxs/mach-mxs.c | 8 ++++
2 files changed, 85 insertions(+)
create mode 100644 arch/arm/boot/dts/imx28-cfa10037.dts
diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts
new file mode 100644
index 0000000..c2ef3a3
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10037.dts
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ "imx28-cfa10036.dts"
+
+/ {
+ model = "Crystalfontz CFA-10037 Board";
+ compatible = "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28";
+
+ apb at 80000000 {
+ apbh at 80000000 {
+ pinctrl at 80018000 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&hog_pins_cfa10037>;
+
+ hog_pins_cfa10037: hog-10037 at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
+ 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+ };
+ };
+
+ apbx at 80040000 {
+ usbphy1: usbphy at 8007e000 {
+ status = "okay";
+ };
+ };
+ };
+
+ ahb at 80080000 {
+ usb1: usb at 80090000 {
+ vbus-supply = <®_usb1_vbus>;
+ pinctrl-0 = <&usbphy1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ mac0: ethernet at 800f0000 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>;
+ phy-reset-gpios = <&gpio2 21 0>;
+ phy-reset-duration = <100>;
+ status = "okay";
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ reg_usb1_vbus: usb1_vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio0 7 1>;
+ };
+ };
+};
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 4668cf7..622c45a 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -417,6 +417,12 @@ static void __init cfa10049_init(void)
mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
}
+static void __init cfa10037_init(void)
+{
+ enable_clk_enet_out();
+ update_fec_mac_prop(OUI_CRYSTALFONTZ);
+}
+
static void __init apf28_init(void)
{
enable_clk_enet_out();
@@ -437,6 +443,8 @@ static void __init mxs_machine_init(void)
m28evk_init();
else if (of_machine_is_compatible("bluegiga,apx4devkit"))
apx4devkit_init();
+ else if (of_machine_is_compatible("crystalfontz,cfa10037"))
+ cfa10037_init();
else if (of_machine_is_compatible("crystalfontz,cfa10049"))
cfa10049_init();
else if (of_machine_is_compatible("armadeus,imx28-apf28"))
--
1.7.10.4
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox