* [GIT PULL V2 0/4] ARM: mvebu: changes for v3.9
From: Jason Cooper @ 2013-01-23 2:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <pull-1358033364-983365>
The following changes since commit 4b53ab9cb853e446f628e561ce6fcc527df30a76:
Merge branch 'mvebu/fixes' into mvebu/drivers (2013-01-23 01:42:14 +0000)
are available in the git repository at:
git://git.infradead.org/users/jcooper/linux.git mvebu/for-next
for you to fetch changes up to bf70a4aed75cdcfc765f896916cec73d3f94f3ec:
Merge branch 'mvebu/dt' into mvebu/for-next (2013-01-23 02:42:39 +0000)
----------------------------------------------------------------
Andrew Lunn (1):
ARM: Kirkwood: Cleanup unneeded include files
Gregory CLEMENT (2):
arm: mvebu: Update defconfig with Marvell RTC support
arm: mvebu: Add RTC support for Armada 370 and Armada XP
Jason Cooper (4):
Merge branch 'mvebu/cleanup' into mvebu/for-next
Merge branch 'mvebu/drivers' into mvebu/for-next
Merge branch 'mvebu/boards' into mvebu/for-next
Merge branch 'mvebu/dt' into mvebu/for-next
Nobuhiro Iwamatsu (3):
ARM: Kirkwood: Add pinctrl of TWSI1 to 88f6282
ARM: Kirkwood: Add pinctrl of NAND to 88f6282
ARM: Kirkwood: Convert openblocks A6 board to pinctrl
Sebastian Hesselbarth (2):
ARM: Dove: move CuBox led pinctrl to gpio-leds node
ARM: Dove: add fixed regulator for CuBox USB power
Thomas Petazzoni (18):
arm: kirkwood: dockstar: remove useless include of SDIO header
mmc: mvsdio: use slot-gpio infrastructure for write protect gpio
mmc: mvsdio: use slot-gpio for card detect gpio
mmc: mvsdio: implement a Device Tree binding
mmc: mvsdio: add pinctrl integration
arm: mvebu: enable SDIO support in mvebu_defconfig
arm: mvebu: enable mwifiex driver in mvebu_defconfig
arm: mvebu: enable btmrvl driver in mvebu_defconfig
arm: mvebu: add DT information for the SDIO interface of Armada 370/XP
arm: mvebu: add pin muxing options for the SDIO interface on Armada 370
arm: mvebu: add pin muxing options for the SDIO interface on Armada XP
arm: mvebu: enable the SD card slot on Armada XP DB board
arm: mvebu: enable the SD card slot on Armada 370 DB board
arm: mvebu: enable the SDIO interface on the Globalscale Mirabox
arm: kirkwood: add Device Tree informations for the SDIO controller
arm: kirkwood: dreamplug: use Device Tree to probe SDIO
arm: kirkwood: mplcec4: use Device Tree to probe SDIO
arm: kirkwood: add pinmux option for the SDIO interface on 88F6282
.../devicetree/bindings/mmc/orion-sdio.txt | 17 +++
arch/arm/boot/dts/armada-370-db.dts | 15 +++
arch/arm/boot/dts/armada-370-mirabox.dts | 10 ++
arch/arm/boot/dts/armada-370-xp.dtsi | 14 +++
arch/arm/boot/dts/armada-370.dtsi | 12 ++
arch/arm/boot/dts/armada-xp-db.dts | 7 ++
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 6 +
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 6 +
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 6 +
arch/arm/boot/dts/dove-cubox.dts | 28 ++++-
arch/arm/boot/dts/kirkwood-6282.dtsi | 17 +++
arch/arm/boot/dts/kirkwood-dreamplug.dts | 7 ++
arch/arm/boot/dts/kirkwood-mplcec4.dts | 11 +-
arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 116 ++++++++++++++++++
arch/arm/boot/dts/kirkwood.dtsi | 8 ++
arch/arm/configs/mvebu_defconfig | 9 ++
arch/arm/mach-dove/Kconfig | 2 +
arch/arm/mach-kirkwood/board-dreamplug.c | 6 -
arch/arm/mach-kirkwood/board-ib62x0.c | 1 -
arch/arm/mach-kirkwood/board-mplcec4.c | 8 --
arch/arm/mach-kirkwood/board-openblocks_a6.c | 44 -------
arch/arm/mach-kirkwood/dockstar-setup.c | 1 -
drivers/mmc/host/mvsdio.c | 129 ++++++++++-----------
23 files changed, 351 insertions(+), 129 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/orion-sdio.txt
^ permalink raw reply
* [GIT PULL V2 1/4] ARM: mvebu: cleanup for v3.9
From: Jason Cooper @ 2013-01-23 2:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358909281.35276e0.21555@triton>
The following changes since commit d1c3ed669a2d452cacfb48c2d171a1f364dae2ed:
Linux 3.8-rc2 (2013-01-02 18:13:21 -0800)
are available in the git repository at:
git://git.infradead.org/users/jcooper/linux.git tags/cleanup_for_v3.9
for you to fetch changes up to b96e1b1c3c5319294edb0970b6d5bf099c0e85eb:
ARM: Kirkwood: Cleanup unneeded include files (2013-01-12 21:50:10 +0000)
----------------------------------------------------------------
mvebu cleanup for v3.9
- remove unneeded includes due to DT conversion
----------------------------------------------------------------
Andrew Lunn (1):
ARM: Kirkwood: Cleanup unneeded include files
Thomas Petazzoni (1):
arm: kirkwood: dockstar: remove useless include of SDIO header
arch/arm/mach-kirkwood/board-ib62x0.c | 1 -
arch/arm/mach-kirkwood/board-mplcec4.c | 1 -
arch/arm/mach-kirkwood/dockstar-setup.c | 1 -
3 files changed, 3 deletions(-)
^ permalink raw reply
* [GIT PULL V2 2/4] ARM: mvebu: drivers for v3.9
From: Jason Cooper @ 2013-01-23 2:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358909281.35276e0.21555@triton>
The following changes since commit 4b53ab9cb853e446f628e561ce6fcc527df30a76:
Merge branch 'mvebu/fixes' into mvebu/drivers (2013-01-23 01:42:14 +0000)
are available in the git repository at:
git://git.infradead.org/users/jcooper/linux.git tags/drivers_for_v3.9
for you to fetch changes up to 43076a4c4e5fb92721bedc5d05b93468d6d76b2c:
mmc: mvsdio: add pinctrl integration (2013-01-23 01:42:29 +0000)
----------------------------------------------------------------
mvebu drivers for v3.9
- mvsdio
- use slot-gpio for card detect and write protect
- add DT binding
- add pinctrl integration
- use rtc-mv in mvebu armv7 SoCs
- add pci-e hotplug for kirkwood
depends on:
- mvebu/fixes
----------------------------------------------------------------
Thomas Petazzoni (4):
mmc: mvsdio: use slot-gpio infrastructure for write protect gpio
mmc: mvsdio: use slot-gpio for card detect gpio
mmc: mvsdio: implement a Device Tree binding
mmc: mvsdio: add pinctrl integration
.../devicetree/bindings/mmc/orion-sdio.txt | 17 +++
drivers/mmc/host/mvsdio.c | 129 ++++++++++-----------
2 files changed, 80 insertions(+), 66 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/orion-sdio.txt
^ permalink raw reply
* [GIT PULL V2 3/4] ARM: mvebu: boards for v3.9
From: Jason Cooper @ 2013-01-23 2:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358909281.35276e0.21555@triton>
The following changes since commit 43076a4c4e5fb92721bedc5d05b93468d6d76b2c:
mmc: mvsdio: add pinctrl integration (2013-01-23 01:42:29 +0000)
are available in the git repository at:
git://git.infradead.org/users/jcooper/linux.git tags/boards_for_v3.9
for you to fetch changes up to 6c00ce51dd26ffcd978c657533a71af32dbf2793:
arm: mvebu: enable btmrvl driver in mvebu_defconfig (2013-01-23 01:57:37 +0000)
----------------------------------------------------------------
mvebu boards for v3.9
- Guruplug Server Plus DT board
- mvebu improved SMP support in interrupt controller
- update mvebu_defconfig
depends on:
- mvebu/fixes
- mvebu/drivers
----------------------------------------------------------------
Gregory CLEMENT (1):
arm: mvebu: Update defconfig with Marvell RTC support
Thomas Petazzoni (3):
arm: mvebu: enable SDIO support in mvebu_defconfig
arm: mvebu: enable mwifiex driver in mvebu_defconfig
arm: mvebu: enable btmrvl driver in mvebu_defconfig
arch/arm/configs/mvebu_defconfig | 9 +++++++++
1 file changed, 9 insertions(+)
^ permalink raw reply
* [GIT PULL V2 4/4] ARM: mvebu: dt for v3.9
From: Jason Cooper @ 2013-01-23 2:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358909281.35276e0.21555@triton>
The following changes since commit 6c00ce51dd26ffcd978c657533a71af32dbf2793:
arm: mvebu: enable btmrvl driver in mvebu_defconfig (2013-01-23 01:57:37 +0000)
are available in the git repository at:
git://git.infradead.org/users/jcooper/linux.git tags/dt_for_v3.9
for you to fetch changes up to 68f4d9ecc4512aa5680f897187d607be91a3f95b:
ARM: Dove: add fixed regulator for CuBox USB power (2013-01-23 02:07:09 +0000)
----------------------------------------------------------------
mvebu dt changes for v3.9
- mvebu
- add rtc support
- add sdio support
- kirkwood
- add sdio support
- add twsi1 and nand to 88f6282
- convert openblocks A6 to pinctrl
- dove
- move led pinctrl to gpio-leds node
- use fixed regulator for usb power
depends on:
- mvebu/fixes
- mvebu/drivers
- mvebu/boards
----------------------------------------------------------------
Gregory CLEMENT (1):
arm: mvebu: Add RTC support for Armada 370 and Armada XP
Nobuhiro Iwamatsu (3):
ARM: Kirkwood: Add pinctrl of TWSI1 to 88f6282
ARM: Kirkwood: Add pinctrl of NAND to 88f6282
ARM: Kirkwood: Convert openblocks A6 board to pinctrl
Sebastian Hesselbarth (2):
ARM: Dove: move CuBox led pinctrl to gpio-leds node
ARM: Dove: add fixed regulator for CuBox USB power
Thomas Petazzoni (10):
arm: mvebu: add DT information for the SDIO interface of Armada 370/XP
arm: mvebu: add pin muxing options for the SDIO interface on Armada 370
arm: mvebu: add pin muxing options for the SDIO interface on Armada XP
arm: mvebu: enable the SD card slot on Armada XP DB board
arm: mvebu: enable the SD card slot on Armada 370 DB board
arm: mvebu: enable the SDIO interface on the Globalscale Mirabox
arm: kirkwood: add Device Tree informations for the SDIO controller
arm: kirkwood: dreamplug: use Device Tree to probe SDIO
arm: kirkwood: mplcec4: use Device Tree to probe SDIO
arm: kirkwood: add pinmux option for the SDIO interface on 88F6282
arch/arm/boot/dts/armada-370-db.dts | 15 ++++
arch/arm/boot/dts/armada-370-mirabox.dts | 10 +++
arch/arm/boot/dts/armada-370-xp.dtsi | 14 ++++
arch/arm/boot/dts/armada-370.dtsi | 12 +++
arch/arm/boot/dts/armada-xp-db.dts | 7 ++
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 6 ++
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 6 ++
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 6 ++
arch/arm/boot/dts/dove-cubox.dts | 28 ++++++-
arch/arm/boot/dts/kirkwood-6282.dtsi | 17 ++++
arch/arm/boot/dts/kirkwood-dreamplug.dts | 7 ++
arch/arm/boot/dts/kirkwood-mplcec4.dts | 11 ++-
arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 116 +++++++++++++++++++++++++++
arch/arm/boot/dts/kirkwood.dtsi | 8 ++
arch/arm/mach-dove/Kconfig | 2 +
arch/arm/mach-kirkwood/board-dreamplug.c | 6 --
arch/arm/mach-kirkwood/board-mplcec4.c | 7 --
arch/arm/mach-kirkwood/board-openblocks_a6.c | 44 ----------
18 files changed, 262 insertions(+), 60 deletions(-)
^ permalink raw reply
* [PATCH 1/2 net-next] net: fec: add napi support to improve proformance
From: Frank Li @ 2013-01-23 4:12 UTC (permalink / raw)
To: linux-arm-kernel
Add napi support
Before this patch
iperf -s -i 1
------------------------------------------------------------
Server listening on TCP port 5001
TCP window size: 85.3 KByte (default)
------------------------------------------------------------
[ 4] local 10.192.242.153 port 5001 connected with 10.192.242.138 port 50004
[ ID] Interval Transfer Bandwidth
[ 4] 0.0- 1.0 sec 41.2 MBytes 345 Mbits/sec
[ 4] 1.0- 2.0 sec 43.7 MBytes 367 Mbits/sec
[ 4] 2.0- 3.0 sec 42.8 MBytes 359 Mbits/sec
[ 4] 3.0- 4.0 sec 43.7 MBytes 367 Mbits/sec
[ 4] 4.0- 5.0 sec 42.7 MBytes 359 Mbits/sec
[ 4] 5.0- 6.0 sec 43.8 MBytes 367 Mbits/sec
[ 4] 6.0- 7.0 sec 43.0 MBytes 361 Mbits/sec
After this patch
[ 4] 2.0- 3.0 sec 51.6 MBytes 433 Mbits/sec
[ 4] 3.0- 4.0 sec 51.8 MBytes 435 Mbits/sec
[ 4] 4.0- 5.0 sec 52.2 MBytes 438 Mbits/sec
[ 4] 5.0- 6.0 sec 52.1 MBytes 437 Mbits/sec
[ 4] 6.0- 7.0 sec 52.1 MBytes 437 Mbits/sec
[ 4] 7.0- 8.0 sec 52.3 MBytes 439 Mbits/sec
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
---
drivers/net/ethernet/freescale/fec.c | 68 ++++++++++++++++++++++++++++++---
drivers/net/ethernet/freescale/fec.h | 4 ++
2 files changed, 65 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index f52ba33..8fa420c 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -67,6 +67,8 @@
#endif
#define DRIVER_NAME "fec"
+#define FEC_NAPI_WEIGHT 64
+#define INT32_MAX 0x7FFFFFFF
/* Pause frame feild and FIFO threshold */
#define FEC_ENET_FCE (1 << 5)
@@ -565,6 +567,20 @@ fec_timeout(struct net_device *ndev)
}
static void
+fec_enet_rx_int_is_enabled(struct net_device *ndev, bool enabled)
+{
+ struct fec_enet_private *fep = netdev_priv(ndev);
+ uint int_events;
+
+ int_events = readl(fep->hwp + FEC_IMASK);
+ if (enabled)
+ int_events |= FEC_ENET_RXF;
+ else
+ int_events &= ~FEC_ENET_RXF;
+ writel(int_events, fep->hwp + FEC_IMASK);
+}
+
+static void
fec_enet_tx(struct net_device *ndev)
{
struct fec_enet_private *fep;
@@ -656,8 +672,8 @@ fec_enet_tx(struct net_device *ndev)
* not been given to the system, we just set the empty indicator,
* effectively tossing the packet.
*/
-static void
-fec_enet_rx(struct net_device *ndev)
+static int
+fec_enet_rx(struct net_device *ndev, int budget)
{
struct fec_enet_private *fep = netdev_priv(ndev);
const struct platform_device_id *id_entry =
@@ -667,13 +683,12 @@ fec_enet_rx(struct net_device *ndev)
struct sk_buff *skb;
ushort pkt_len;
__u8 *data;
+ int pkt_received = 0;
#ifdef CONFIG_M532x
flush_cache_all();
#endif
- spin_lock(&fep->hw_lock);
-
/* First, grab all of the stats for the incoming packet.
* These get messed up if we get called due to a busy condition.
*/
@@ -681,6 +696,10 @@ fec_enet_rx(struct net_device *ndev)
while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
+ if (pkt_received >= budget)
+ break;
+ pkt_received++;
+
/* Since we have allocated space to hold a complete frame,
* the last indicator should be set.
*/
@@ -796,7 +815,7 @@ rx_processing_done:
}
fep->cur_rx = bdp;
- spin_unlock(&fep->hw_lock);
+ return pkt_received;
}
static irqreturn_t
@@ -805,6 +824,7 @@ fec_enet_interrupt(int irq, void *dev_id)
struct net_device *ndev = dev_id;
struct fec_enet_private *fep = netdev_priv(ndev);
uint int_events;
+ ulong flags;
irqreturn_t ret = IRQ_NONE;
do {
@@ -813,7 +833,18 @@ fec_enet_interrupt(int irq, void *dev_id)
if (int_events & FEC_ENET_RXF) {
ret = IRQ_HANDLED;
- fec_enet_rx(ndev);
+ spin_lock_irqsave(&fep->hw_lock, flags);
+
+ if (fep->use_napi) {
+ /* Disable the RX interrupt */
+ if (napi_schedule_prep(&fep->napi)) {
+ fec_enet_rx_int_is_enabled(ndev, false);
+ __napi_schedule(&fep->napi);
+ }
+ } else
+ fec_enet_rx(ndev, INT32_MAX);
+
+ spin_unlock_irqrestore(&fep->hw_lock, flags);
}
/* Transmit OK, or non-fatal error. Update the buffer
@@ -834,7 +865,16 @@ fec_enet_interrupt(int irq, void *dev_id)
return ret;
}
-
+static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
+{
+ struct net_device *ndev = napi->dev;
+ int pkgs = fec_enet_rx(ndev, budget);
+ if (pkgs < budget) {
+ napi_complete(napi);
+ fec_enet_rx_int_is_enabled(ndev, true);
+ }
+ return pkgs;
+}
/* ------------------------------------------------------------------------- */
static void fec_get_mac(struct net_device *ndev)
@@ -1392,6 +1432,9 @@ fec_enet_open(struct net_device *ndev)
struct fec_enet_private *fep = netdev_priv(ndev);
int ret;
+ if (fep->use_napi)
+ napi_enable(&fep->napi);
+
/* I should reset the ring buffers here, but I don't yet know
* a simple way to do that.
*/
@@ -1604,6 +1647,11 @@ static int fec_enet_init(struct net_device *ndev)
ndev->netdev_ops = &fec_netdev_ops;
ndev->ethtool_ops = &fec_enet_ethtool_ops;
+ if (fep->use_napi) {
+ fec_enet_rx_int_is_enabled(ndev, false);
+ netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, fep->napi_weight);
+ }
+
/* Initialize the receive buffer descriptors. */
bdp = fep->rx_bd_base;
for (i = 0; i < RX_RING_SIZE; i++) {
@@ -1698,6 +1746,7 @@ fec_probe(struct platform_device *pdev)
static int dev_id;
struct pinctrl *pinctrl;
struct regulator *reg_phy;
+ struct device_node *np = pdev->dev.of_node;
of_id = of_match_device(fec_dt_ids, &pdev->dev);
if (of_id)
@@ -1811,6 +1860,11 @@ fec_probe(struct platform_device *pdev)
}
}
+ fep->use_napi = !of_property_read_bool(np, "disable_napi");
+
+ if (of_property_read_u32(np, "napi_weight", &fep->napi_weight))
+ fep->napi_weight = FEC_NAPI_WEIGHT; /*using default value*/
+
fec_reset_phy(pdev);
ret = fec_enet_init(ndev);
diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
index 2ebedaf..31fcdd0 100644
--- a/drivers/net/ethernet/freescale/fec.h
+++ b/drivers/net/ethernet/freescale/fec.h
@@ -249,6 +249,10 @@ struct fec_enet_private {
int bufdesc_ex;
int pause_flag;
+ struct napi_struct napi;
+ int napi_weight;
+ bool use_napi;
+
struct ptp_clock *ptp_clock;
struct ptp_clock_info ptp_caps;
unsigned long last_overflow_check;
--
1.7.1
^ permalink raw reply related
* [PATCH 2/2 net-next] doc: dt: fsl: fec: add napi optional properties
From: Frank Li @ 2013-01-23 4:12 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Frank Li <Frank.Li@freescale.com>
---
Documentation/devicetree/bindings/net/fsl-fec.txt | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
index d536392..4a94090 100644
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@@ -15,6 +15,8 @@ Optional properties:
only if property "phy-reset-gpios" is available. Missing the property
will have the duration be 1 millisecond. Numbers greater than 1000 are
invalid and 1 millisecond will be used instead.
+- disable_napi : disable napi support
+- napi_weight : napi weight number, default value is 64
Example:
--
1.7.1
^ permalink raw reply related
* [PATCH] ab8500: btemp: demote initcall sequence
From: Rajanikanth H.V @ 2013-01-23 4:26 UTC (permalink / raw)
To: linux-arm-kernel
From: "Rajanikanth H.V" <rajanikanth.hv@stericsson.com>
Power supply subsystem creates thermal zone device for
the property 'POWER_SUPPLY_PROP_TEMP' which requires
thermal subsystem to be ready before 'ab8500 battery temperature monitor'
driver is initialized.
ab8500 btemp driver is initialized with subsys_initcall whereas thermal
subsystem is initialized with fs_initcall which causes
thermal_zone_device_register(...) to crash since the required structure
'thermal_class' is not initialized yet.
crash log:
===================================================================
Unable to handle kernel NULL pointer dereference at virtual address 000000a4
pgd = c0004000
[000000a4] *pgd=00000000
Internal error: Oops: 5 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 Tainted: G W (3.8.0-rc4-00001-g632fda8-dirty #1)
PC is at _raw_spin_lock+0x18/0x54
LR is at get_device_parent+0x50/0x1b8
pc : [<c02f1dd0>] lr : [<c01cb248>] psr: 60000013
sp : ef04bdc8 ip : 00000000 fp : c0446180
r10: ef216e38 r9 : c03af5d0 r8 : ef275c18
r7 : 00000000 r6 : c0476c14 r5 : ef275c18 r4 : ef095840
r3 : ef04a000 r2 : 00000001 r1 : 00000000 r0 : 000000a4
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c5787d Table: 0000404a DAC: 00000015
Process swapper/0 (pid: 1, stack limit = 0xef04a238)
Stack: (0xef04bdc8 to 0xef04c000)
bdc0: ef275c18 00000000 00000000 c01cb8d8 00000000 ef275c18
bde0: ef275c80 00000000 c0446180 c01d3edc ef275c18 ef275c00 00000000 00000000
be00: c03af5d0 ef275c18 c03af5d0 ef216e38 c0446180 c020b91c 00000000 ef275c04
be20: ef04be48 ef1ad000 ef216e38 ef1ad000 ef216e38 00000000 ef1b9010 00000002
be40: c03af5d0 00000000 c0446058 c0202030 c0445400 00000000 00000000 00000000
be60: ef216e10 ef1b9000 c04457f4 c02055ec 00000000 c01d57ac ef216e38 ef037a00
be80: ef181fc0 00000000 ef1b9010 c0476c38 ef1b9010 ef1b9044 c0446008 c041bbb0
bea0: c044d940 ef04a000 c0414b68 c01cf0dc c01cf0c8 c01cde70 00000000 ef1b9010
bec0: c0446008 ef1b9044 00000000 c01ce094 00000000 c0446008 c01ce008 c01cc640
bee0: ef032258 ef180334 ef222f00 c0446008 c0441778 c01cd6b4 c03ab170 c0446008
bf00: c0446008 c041bbd0 00000005 c044d940 c041bbb0 c01ce54c 00000000 c0422988
bf20: c041bbd0 00000005 c044d940 c041bbb0 ef04a000 c00086ac 00000049 c00360cc
bf40: ef04bf6c 00000000 c0388c34 c03e1a78 00000004 00000004 c0436998 c0422988
bf60: c041bbd0 00000005 c044d940 c041bbb0 c040027c 00000049 00000000 c02e89c8
bf80: 00000004 00000004 c040027c c0c88340 00000000 c02e88a8 00000000 00000000
bfa0: 00000000 00000000 00000000 c000e358 00000000 00000000 00000000 00000000
bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
bfe0: 00000000 00000000 00000000 00000000 00000013 00000000 80800004 00304600
[<c02f1dd0>] (_raw_spin_lock+0x18/0x54) from [<c01cb248>] (get_device_parent+0x50/0x1b8)
[<c01cb248>] (get_device_parent+0x50/0x1b8) from [<c01cb8d8>] (device_add+0xa4/0x574)
[<c01cb8d8>] (device_add+0xa4/0x574) from [<c020b91c>] (thermal_zone_device_register+0x118/0x938)
[<c020b91c>] (thermal_zone_device_register+0x118/0x938) from [<c0202030>] (power_supply_register+0x170/0x1f8)
[<c0202030>] (power_supply_register+0x170/0x1f8) from [<c02055ec>] (ab8500_btemp_probe+0x208/0x47c)
[<c02055ec>] (ab8500_btemp_probe+0x208/0x47c) from [<c01cf0dc>] (platform_drv_probe+0x14/0x18)
[<c01cf0dc>] (platform_drv_probe+0x14/0x18) from [<c01cde70>] (driver_probe_device+0x74/0x20c)
[<c01cde70>] (driver_probe_device+0x74/0x20c) from [<c01ce094>] (__driver_attach+0x8c/0x90)
[<c01ce094>] (__driver_attach+0x8c/0x90) from [<c01cc640>] (bus_for_each_dev+0x4c/0x80)
[<c01cc640>] (bus_for_each_dev+0x4c/0x80) from [<c01cd6b4>] (bus_add_driver+0x16c/0x23c)
[<c01cd6b4>] (bus_add_driver+0x16c/0x23c) from [<c01ce54c>] (driver_register+0x78/0x14c)
[<c01ce54c>] (driver_register+0x78/0x14c) from [<c00086ac>] (do_one_initcall+0xfc/0x164)
[<c00086ac>] (do_one_initcall+0xfc/0x164) from [<c02e89c8>] (kernel_init+0x120/0x2b8)
[<c02e89c8>] (kernel_init+0x120/0x2b8) from [<c000e358>] (ret_from_fork+0x14/0x3c)
Code: e3c3303f e5932004 e2822001 e5832004 (e1903f9f)
---[ end trace ed9df72941b5bada ]---
===================================================================
Signed-off-by: Rajanikanth H.V <rajanikanth.hv@stericsson.com>
---
drivers/power/ab8500_btemp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/power/ab8500_btemp.c b/drivers/power/ab8500_btemp.c
index 20e2a7d..056222e 100644
--- a/drivers/power/ab8500_btemp.c
+++ b/drivers/power/ab8500_btemp.c
@@ -1123,7 +1123,7 @@ static void __exit ab8500_btemp_exit(void)
platform_driver_unregister(&ab8500_btemp_driver);
}
-subsys_initcall_sync(ab8500_btemp_init);
+device_initcall(ab8500_btemp_init);
module_exit(ab8500_btemp_exit);
MODULE_LICENSE("GPL v2");
--
1.7.10.4
^ permalink raw reply related
* Boot ARM (Cortex A-9) target without device tree support
From: naveen yadav @ 2013-01-23 5:05 UTC (permalink / raw)
To: linux-arm-kernel
Dear All,
We want to run our embedded target on 3.8-rc4 without using device
tree support. Is it possible.
If yes then is it controlled by .config or I need to revert some patches.
Thanks
^ permalink raw reply
* [PATCH v3] i2c: exynos5: add High Speed I2C controller driver
From: Naveen Krishna Ch @ 2013-01-23 5:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1356694023-32470-1-git-send-email-ch.naveen@samsung.com>
On 28 December 2012 16:57, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> Adds support for High Speed I2C driver found in Exynos5 and later
> SoCs from Samsung. This driver currently supports Auto mode.
>
> Driver only supports Device Tree method of passing platform data.
> Note: Added debugfs support for registers view, not tested.
>
> Signed-off-by: Taekgyun Ko <taeggyun.ko@samsung.com>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> Changes since v2: fixed comments from Felipe Balbi.
> And minor fixes for the return values in exynos5_i2c_doxfer()
>
> drivers/i2c/busses/Kconfig | 7 +
> drivers/i2c/busses/Makefile | 1 +
> drivers/i2c/busses/i2c-exynos5.c | 736 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 744 insertions(+)
> create mode 100644 drivers/i2c/busses/i2c-exynos5.c
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index bdca511..4caea76 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -618,6 +618,13 @@ config I2C_S3C2410
> Say Y here to include support for I2C controller in the
> Samsung SoCs.
>
> +config I2C_EXYNOS5
> + tristate "Exynos5 high-speed I2C driver"
> + depends on ARCH_EXYNOS5
> + help
> + Say Y here to include support for High-speed I2C controller in the
> + Exynos5 based Samsung SoCs.
> +
> config I2C_S6000
> tristate "S6000 I2C support"
> depends on XTENSA_VARIANT_S6000
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 6181f3f..4b1548c 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -61,6 +61,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
> obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
> obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
> obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o
> +obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o
> obj-$(CONFIG_I2C_S6000) += i2c-s6000.o
> obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
> obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
> diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
> new file mode 100644
> index 0000000..a5eb959
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-exynos5.c
> @@ -0,0 +1,736 @@
> +/**
> + * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
> + *
> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/debugfs.h>
> +
> +#include <linux/i2c.h>
> +#include <linux/init.h>
> +#include <linux/time.h>
> +#include <linux/interrupt.h>
> +#include <linux/delay.h>
> +#include <linux/errno.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/clk.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/of_address.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_i2c.h>
> +
> +/* Register Map */
> +#define HSI2C_CTL 0x00
> +#define HSI2C_FIFO_CTL 0x04
> +#define HSI2C_TRAILIG_CTL 0x08
> +#define HSI2C_CLK_CTL 0x0C
> +#define HSI2C_CLK_SLOT 0x10
> +#define HSI2C_INT_ENABLE 0x20
> +#define HSI2C_INT_STATUS 0x24
> +#define HSI2C_ERR_STATUS 0x2C
> +#define HSI2C_FIFO_STATUS 0x30
> +#define HSI2C_TX_DATA 0x34
> +#define HSI2C_RX_DATA 0x38
> +#define HSI2C_CONF 0x40
> +#define HSI2C_AUTO_CONF 0x44
> +#define HSI2C_TIMEOUT 0x48
> +#define HSI2C_MANUAL_CMD 0x4C
> +#define HSI2C_TRANS_STATUS 0x50
> +#define HSI2C_TIMING_HS1 0x54
> +#define HSI2C_TIMING_HS2 0x58
> +#define HSI2C_TIMING_HS3 0x5C
> +#define HSI2C_TIMING_FS1 0x60
> +#define HSI2C_TIMING_FS2 0x64
> +#define HSI2C_TIMING_FS3 0x68
> +#define HSI2C_TIMING_SLA 0x6C
> +#define HSI2C_ADDR 0x70
> +
> +/* I2C_CTL Register bits */
> +#define HSI2C_FUNC_MODE_I2C (1u << 0)
> +#define HSI2C_MASTER (1u << 3)
> +#define HSI2C_RXCHON (1u << 6)
> +#define HSI2C_TXCHON (1u << 7)
> +#define HSI2C_SW_RST (1u << 31)
> +
> +/* I2C_FIFO_CTL Register bits */
> +#define HSI2C_RXFIFO_EN (1u << 0)
> +#define HSI2C_TXFIFO_EN (1u << 1)
> +#define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)
> +#define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)
> +
> +/* I2C_TRAILING_CTL Register bits */
> +#define HSI2C_TRAILING_COUNT (0xf)
> +
> +/* I2C_INT_EN Register bits */
> +#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
> +#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
> +#define HSI2C_INT_TRAILING_EN (1u << 6)
> +#define HSI2C_INT_I2C_EN (1u << 9)
> +
> +/* I2C_FIFO_STAT Register bits */
> +#define HSI2C_RX_FIFO_EMPTY (1u << 24)
> +#define HSI2C_RX_FIFO_FULL (1u << 23)
> +#define HSI2C_RX_FIFO_LEVEL_MASK (0x7 << 16)
> +#define HSI2C_TX_FIFO_EMPTY (1u << 8)
> +#define HSI2C_TX_FIFO_FULL (1u << 7)
> +#define HSI2C_TX_FIFO_LEVEL_MASK (0x7 << 7)
> +#define HSI2C_FIFO_EMPTY (0x1000100)
> +
> +/* I2C_CONF Register bits */
> +#define HSI2C_AUTO_MODE (1u << 31)
> +#define HSI2C_10BIT_ADDR_MODE (1u << 30)
> +#define HSI2C_HS_MODE (1u << 29)
> +
> +/* I2C_AUTO_CONF Register bits */
> +#define HSI2C_READ_WRITE (1u << 16)
> +#define HSI2C_STOP_AFTER_TRANS (1u << 17)
> +#define HSI2C_MASTER_RUN (1u << 31)
> +
> +/* I2C_TIMEOUT Register bits */
> +#define HSI2C_TIMEOUT_EN (1u << 31)
> +
> +/* I2C_TRANS_STATUS register bits */
> +#define HSI2C_MASTER_BUSY (1u << 17)
> +#define HSI2C_SLAVE_BUSY (1u << 16)
> +#define HSI2C_NO_DEV (1u << 3)
> +#define HSI2C_NO_DEV_ACK (1u << 2)
> +#define HSI2C_TRANS_ABORT (1u << 1)
> +#define HSI2C_TRANS_DONE (1u << 0)
> +
> +/**
> + * Although exynos5 supports max HS-IIC speed of 3.4Mhz,
> + * but currently we are facing booting issues beyond 1Mhz
> + * So limiting HS-IIC bus speed to 1Mhz
> +*/
> +#define HSI2C_HS_TX_CLOCK 1000000
> +#define HSI2C_FS_TX_CLOCK 400000
> +
> +#define HSI2C_FAST_SPD 0
> +#define HSI2C_HIGH_SPD 1
> +
> +#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
> +
> +/* timeout for pm runtime autosuspend */
> +#define EXYNOS5_I2C_PM_TIMEOUT 1000 /* ms */
> +
> +struct exynos5_i2c {
> + struct i2c_adapter adap;
> + unsigned int suspended:1;
> +
> + struct i2c_msg *msg;
> + unsigned int msg_idx;
> + struct completion msg_complete;
> + unsigned int msg_ptr;
> +
> + unsigned int irq;
> +
> + void __iomem *regs;
> + struct clk *clk;
> + struct device *dev;
> + int gpios[2];
> +
> + int bus_num;
> + int speed_mode;
> + struct dentry *debugfs_root;
> +};
> +
> +static const struct of_device_id exynos5_i2c_match[] = {
> + { .compatible = "samsung,exynos5-hsi2c" },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
> +
> +static void exynos5_i2c_stop(struct exynos5_i2c *i2c, int err)
> +{
> + dev_vdbg(i2c->dev, "STOP\n");
> +
> + i2c->msg_idx++;
> + if (err)
> + i2c->msg_idx = err;
> +
> + /* Disable interrrupts */
> + writel(0, i2c->regs + HSI2C_INT_ENABLE);
> + complete(&i2c->msg_complete);
> +}
> +
> +static void exynos5_i2c_en_timeout(struct exynos5_i2c *i2c)
> +{
> + unsigned long i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
> +
> + /* Clear to enable Timeout */
> + i2c_timeout &= ~HSI2C_TIMEOUT_EN;
> + writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
> +}
> +
> +static void exynos5_i2c_master_run(struct exynos5_i2c *i2c)
> +{
> + /* Start data transfer in Master mode */
> + u32 i2c_auto_conf = readl(i2c->regs + HSI2C_AUTO_CONF);
> + i2c_auto_conf |= HSI2C_MASTER_RUN;
> + writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
> +}
> +
> +/**
> + * exynos5_i2c_set_bus: get the i2c bus for a master transaction
> +*/
> +static int exynos5_i2c_set_master(struct exynos5_i2c *i2c)
> +{
> + unsigned long t_status;
> + int timeout = 400;
> +
> + while (timeout-- > 0) {
> + t_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
> +
> + if (!(t_status & HSI2C_MASTER_BUSY))
> + return 0;
> +
> + msleep(20);
> + }
> +
> + return -ETIMEDOUT;
> +}
> +
> +/**
> + * exynos5_i2c_irq: top level IRQ servicing routine
> +*/
> +static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
> +{
> + struct exynos5_i2c *i2c = dev_id;
> + unsigned long t_stat;
> + unsigned char byte;
> +
> + t_stat = readl(i2c->regs + HSI2C_TRANS_STATUS);
> +
> + if (t_stat & HSI2C_TRANS_ABORT) {
> + /* deal with arbitration loss */
> + dev_err(i2c->dev, "deal with arbitration loss\n");
> + goto out;
> + }
> + if (i2c->msg->flags & I2C_M_RD) {
> + if (t_stat & HSI2C_TRANS_DONE) {
> + dev_dbg(i2c->dev, "Device found.");
> + while ((readl(i2c->regs + HSI2C_FIFO_STATUS) &
> + HSI2C_RX_FIFO_EMPTY) == 0) {
> + byte = readl(i2c->regs + HSI2C_RX_DATA);
> + dev_dbg(i2c->dev, "read rx_data = %x", byte);
> + i2c->msg->buf[i2c->msg_ptr++] = byte;
> + }
> +
> + if (i2c->msg_ptr >= i2c->msg->len)
> + exynos5_i2c_stop(i2c, 0);
> +
> + } else if (t_stat & HSI2C_NO_DEV) {
> + dev_dbg(i2c->dev, "No device found.");
> + exynos5_i2c_stop(i2c, -ENXIO);
> + } else if (t_stat & HSI2C_NO_DEV_ACK &&
> + !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
> + dev_dbg(i2c->dev, "No device Ack.");
> + exynos5_i2c_stop(i2c, -ENXIO);
> + }
> + } else {
> + byte = i2c->msg->buf[i2c->msg_ptr++];
> + dev_dbg(i2c->dev, "write tx_data = %x ", byte);
> + writel(byte, i2c->regs + HSI2C_TX_DATA);
> +
> + if (i2c->msg_ptr >= i2c->msg->len)
> + exynos5_i2c_stop(i2c, 0);
> + }
> +
> + out:
> + /* Set those bits to clear them */
> + writel(readl(i2c->regs + HSI2C_INT_STATUS),
> + i2c->regs + HSI2C_INT_STATUS);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void exynos5_i2c_message_start(struct exynos5_i2c *i2c,
> + struct i2c_msg *msgs)
> +{
> + unsigned long usi_ctl = HSI2C_FUNC_MODE_I2C | HSI2C_MASTER;
> + unsigned long i2c_auto_conf;
> + unsigned long i2c_addr = ((msgs->addr & 0x7f) << 10);
> + unsigned long usi_int_en = 0;
> +
> + exynos5_i2c_en_timeout(i2c);
> +
> + if (msgs->flags & I2C_M_RD) {
> + usi_ctl &= ~HSI2C_TXCHON;
> + usi_ctl |= HSI2C_RXCHON;
> +
> + i2c_auto_conf |= HSI2C_READ_WRITE;
> +
> + usi_int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
> + HSI2C_INT_TRAILING_EN);
> + } else {
> + usi_ctl &= ~HSI2C_RXCHON;
> + usi_ctl |= HSI2C_TXCHON;
> +
> + i2c_auto_conf &= ~HSI2C_READ_WRITE;
> +
> + usi_int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
> + }
> +
> + writel(i2c_addr, i2c->regs + HSI2C_ADDR);
> + writel(usi_ctl, i2c->regs + HSI2C_CTL);
> +
> + i2c_auto_conf |= i2c->msg->len;
> + i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
> + writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
> +
> + exynos5_i2c_master_run(i2c);
> +
> + /* Enable appropriate interrupts */
> + writel(usi_int_en, i2c->regs + HSI2C_INT_ENABLE);
> +}
> +
> +static int exynos5_i2c_doxfer(struct exynos5_i2c *i2c, struct i2c_msg *msgs)
> +{
> + unsigned long timeout;
> + int ret;
> +
> + if (i2c->suspended) {
> + dev_err(i2c->dev, "HS-I2C is not initialzed.\n");
> + return -EIO;
> + }
> +
> + if (exynos5_i2c_set_master(i2c)) {
> + dev_err(i2c->dev, "cannot get bus, Master busy.\n");
> + return -EAGAIN;
> + }
> +
> + i2c->msg = msgs;
> + i2c->msg_ptr = 0;
> + i2c->msg_idx = 0;
> +
> + INIT_COMPLETION(i2c->msg_complete);
> +
> + exynos5_i2c_message_start(i2c, msgs);
> +
> + timeout = wait_for_completion_timeout(&i2c->msg_complete,
> + EXYNOS5_I2C_TIMEOUT);
> +
> + ret = i2c->msg_idx;
> +
> + if (timeout == 0)
> + dev_dbg(i2c->dev, "timeout\n");
> + else if ((ret != msgs->len) && (ret < 0))
> + dev_dbg(i2c->dev, "incomplete xfer (%d)\n", i2c->msg_idx);
> +
> + return ret;
> +}
> +
> +static int exynos5_i2c_xfer(struct i2c_adapter *adap,
> + struct i2c_msg *msgs, int num)
> +{
> + struct exynos5_i2c *i2c = (struct exynos5_i2c *)adap->algo_data;
> + int retry, i;
> + int ret;
> +
> + ret = pm_runtime_get_sync(i2c->dev);
> + if (IS_ERR_VALUE(ret))
> + goto out;
> +
> + clk_prepare_enable(i2c->clk);
> +
> + for (retry = 0; retry < adap->retries; retry++) {
> + for (i = 0; i < num; i++) {
> + ret = exynos5_i2c_doxfer(i2c, msgs);
> + msgs++;
> +
> + if (ret == -EAGAIN)
> + break;
> + }
> + if (i == num) {
> + clk_disable_unprepare(i2c->clk);
> +
> + if (i2c->msg_idx == -ENXIO)
> + ret = i2c->msg_idx;
> + else
> + ret = num;
> + goto out;
> + }
> +
> + dev_dbg(i2c->dev, "retrying transfer (%d)\n", retry);
> +
> + udelay(100);
> + }
> +
> + ret = -EREMOTEIO;
> + clk_disable_unprepare(i2c->clk);
> + out:
> + pm_runtime_mark_last_busy(i2c->dev);
> + pm_runtime_put_autosuspend(i2c->dev);
> + return ret;
> +}
> +
> +static u32 exynos5_i2c_func(struct i2c_adapter *adap)
> +{
> + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> +}
> +
> +static const struct i2c_algorithm exynos5_i2c_algorithm = {
> + .master_xfer = exynos5_i2c_xfer,
> + .functionality = exynos5_i2c_func,
> +};
> +
> +static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int speed_mode)
> +{
> + unsigned long i2c_timing_s1;
> + unsigned long i2c_timing_s2;
> + unsigned long i2c_timing_s3;
> + unsigned long i2c_timing_sla;
> + unsigned int op_clk;
> + unsigned int clkin = clk_get_rate(i2c->clk);
> + unsigned int n_clkdiv;
> + unsigned int t_start_su, t_start_hd;
> + unsigned int t_stop_su;
> + unsigned int t_data_su, t_data_hd;
> + unsigned int t_scl_l, t_scl_h;
> + unsigned int t_sr_release;
> + unsigned int t_ftl_cycle;
> + unsigned int i = 0, utemp0 = 0, utemp1 = 0, utemp2 = 0;
> +
> + if (speed_mode == HSI2C_HIGH_SPD)
> + op_clk = HSI2C_HS_TX_CLOCK;
> + else
> + op_clk = HSI2C_FS_TX_CLOCK;
> +
> + /* FPCLK / FI2C =
> + * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
> + * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
> + * uTemp1 = (TSCLK_L + TSCLK_H + 2)
> + * uTemp2 = TSCLK_L + TSCLK_H
> + */
> + t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
> + utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
> +
> + /* CLK_DIV max is 256 */
> + for (i = 0; i < 256; i++) {
> + utemp1 = utemp0 / (i + 1);
> + /* SCLK_L/H max is 255
> + * so sclk_l + sclk_h has max value of 510
> + */
> + if (utemp1 < 511) {
> + utemp2 = utemp1 - 2;
> + break;
> + }
> + }
> +
> + n_clkdiv = i;
> + t_scl_l = utemp2 / 2;
> + t_scl_h = utemp2 / 2;
> + t_start_su = t_scl_l;
> + t_start_hd = t_scl_l;
> + t_stop_su = t_scl_l;
> + t_data_su = t_scl_l / 2;
> + t_data_hd = t_scl_l / 2;
> + t_sr_release = utemp2;
> +
> + i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
> + i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
> + i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
> + i2c_timing_sla = t_data_hd << 0;
> +
> + dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
> + t_start_su, t_start_hd, t_stop_su);
> + dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
> + t_data_su, t_scl_l, t_scl_h);
> + dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
> + n_clkdiv, t_sr_release);
> + dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
> +
> + if (speed_mode == HSI2C_HIGH_SPD) {
> + writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
> + writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
> + writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
> + } else {
> + writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
> + writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
> + writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
> + }
> + writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
> +
> + return 0;
> +}
> +
> +/**
> + * Parse a list of GPIOs from a node property and request each one
> + *
> + * @param i2c i2c driver data
> + * @return 0 on success, -EINVAL on error, in which case no GPIOs requested
> +*/
> +static int exynos5_i2c_parse_dt_gpio(struct exynos5_i2c *i2c)
> +{
> + int idx, gpio, ret;
> +
> + for (idx = 0; idx < 2; idx++) {
> + gpio = of_get_gpio(i2c->dev->of_node, idx);
> + if (!gpio_is_valid(gpio)) {
> + dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
> + return -EINVAL;
> + }
> + i2c->gpios[idx] = gpio;
> +
> + ret = devm_gpio_request(i2c->dev, gpio, "i2c-bus");
> + if (ret) {
> + dev_err(i2c->dev, "gpio [%d] request failed\n", gpio);
> + return -EINVAL;
> + }
> + }
> + return 0;
> +}
> +
> +static void exynos5_i2c_init(struct exynos5_i2c *i2c)
> +{
> + unsigned long usi_trailing_ctl = HSI2C_TRAILING_COUNT;
> + unsigned long i2c_conf = HSI2C_AUTO_MODE;
> + unsigned long usi_fifo_ctl;
> +
> + writel(usi_trailing_ctl, i2c->regs + HSI2C_TRAILIG_CTL);
> +
> + /* Set default trigger level for TXFIFO and RXFIFO */
> + usi_fifo_ctl = HSI2C_TXFIFO_TRIGGER_LEVEL | HSI2C_RXFIFO_TRIGGER_LEVEL;
> +
> + /* Enable RXFIFO and TXFIFO */
> + usi_fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
> + writel(usi_fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
> +
> + if (i2c->speed_mode == HSI2C_HIGH_SPD) {
> + exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD);
> + /* Configure I2C controller in High speed mode */
> + i2c_conf |= HSI2C_HS_MODE;
> + writel(i2c_conf, i2c->regs + HSI2C_CONF);
> + } else {
> + /* Configure I2C controller in Fast speed mode */
> + exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD);
> + }
> +}
> +
> +#define HSI2C_REG(regname) {.name = #regname, .offset = regname}
> +static struct debugfs_reg32 exynos5_hsi2c_regs[] = {
> + HSI2C_REG(HSI2C_CTL), HSI2C_REG(HSI2C_FIFO_CTL),
> + HSI2C_REG(HSI2C_TRAILIG_CTL), HSI2C_REG(HSI2C_CLK_CTL),
> + HSI2C_REG(HSI2C_CLK_SLOT), HSI2C_REG(HSI2C_INT_ENABLE),
> + HSI2C_REG(HSI2C_INT_STATUS), HSI2C_REG(HSI2C_ERR_STATUS),
> + HSI2C_REG(HSI2C_FIFO_STATUS), HSI2C_REG(HSI2C_TX_DATA),
> + HSI2C_REG(HSI2C_RX_DATA), HSI2C_REG(HSI2C_CONF),
> + HSI2C_REG(HSI2C_AUTO_CONF), HSI2C_REG(HSI2C_TIMEOUT),
> + HSI2C_REG(HSI2C_MANUAL_CMD), HSI2C_REG(HSI2C_TRANS_STATUS),
> + HSI2C_REG(HSI2C_TIMING_HS1), HSI2C_REG(HSI2C_TIMING_HS2),
> + HSI2C_REG(HSI2C_TIMING_HS3), HSI2C_REG(HSI2C_TIMING_FS1),
> + HSI2C_REG(HSI2C_TIMING_FS2), HSI2C_REG(HSI2C_TIMING_FS3),
> + HSI2C_REG(HSI2C_TIMING_SLA), HSI2C_REG(HSI2C_ADDR),
> +};
> +
> +static struct debugfs_regset32 exynos5_hsi2c_regset = {
> + .regs = exynos5_hsi2c_regs,
> + .nregs = ARRAY_SIZE(exynos5_hsi2c_regs),
> +};
> +
> +static struct dentry *exynos5_hsi2c_reg_debugfs;
> +
> +static int exynos5_i2c_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct exynos5_i2c *i2c;
> + int ret;
> +
> + if (!np) {
> + dev_err(&pdev->dev, "no device node\n");
> + return -ENOENT;
> + }
> +
> + i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
> + if (!i2c) {
> + dev_err(&pdev->dev, "no memory for state\n");
> + return -ENOMEM;
> + }
> +
> + i2c->bus_num = -1;
> + /* Mode of operation High/Fast Speed mode */
> + of_property_read_u32(np, "samsung,hs-mode", &i2c->speed_mode);
> +
> + strlcpy(i2c->adap.name, "exynos5-hsi2c", sizeof(i2c->adap.name));
> + i2c->adap.owner = THIS_MODULE;
> + i2c->adap.algo = &exynos5_i2c_algorithm;
> + i2c->adap.retries = 2;
> + i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
> +
> + i2c->dev = &pdev->dev;
> + i2c->clk = clk_get(&pdev->dev, "hsi2c");
> + if (IS_ERR(i2c->clk)) {
> + dev_err(&pdev->dev, "cannot get clock\n");
> + ret = -ENOENT;
> + goto err_noclk;
> + }
> +
> + dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
> +
> + clk_prepare_enable(i2c->clk);
> +
> + i2c->regs = of_iomap(np, 0);
> + if (!i2c->regs) {
> + dev_err(&pdev->dev, "cannot map HS-I2C IO\n");
> + ret = -ENXIO;
> + goto err_clk;
> + }
> +
> + /* inititalise the gpio */
> + if (exynos5_i2c_parse_dt_gpio(i2c))
> + return -EINVAL;
> +
> + i2c->irq = irq_of_parse_and_map(np, 0);
> + if (i2c->irq) {
> + ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
> + 0, dev_name(&pdev->dev), i2c);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n",
> + i2c->irq);
> + goto err_iomap;
> + }
> + }
> +
> + /*
> + * TODO: Use private lock to avoid race conditions as
> + * mentioned in pm_runtime.txt
> + */
> + pm_runtime_enable(i2c->dev);
> + pm_runtime_set_autosuspend_delay(i2c->dev, EXYNOS5_I2C_PM_TIMEOUT);
> + pm_runtime_use_autosuspend(i2c->dev);
> +
> + ret = pm_runtime_get_sync(i2c->dev);
> + if (IS_ERR_VALUE(ret))
> + goto err_iomap;
> +
> + exynos5_i2c_init(i2c);
> +
> + i2c->adap.algo_data = i2c;
> + i2c->adap.dev.parent = &pdev->dev;
> + i2c->adap.nr = i2c->bus_num;
> + i2c->adap.dev.of_node = pdev->dev.of_node;
> +
> + ret = i2c_add_numbered_adapter(&i2c->adap);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "failed to add bus to i2c core\n");
> + goto err_pm;
> + }
> +
> + init_completion(&i2c->msg_complete);
> + of_i2c_register_devices(&i2c->adap);
> + platform_set_drvdata(pdev, i2c);
> +
> + dev_info(&pdev->dev, "%s: Exynos5 HS-I2C adapter\n",
> + dev_name(&i2c->adap.dev));
> +
> + exynos5_hsi2c_reg_debugfs = debugfs_create_regset32("exynos5-hsi2c",
> + S_IFREG | S_IRUGO,
> + NULL, &exynos5_hsi2c_regset);
> + clk_disable_unprepare(i2c->clk);
> + pm_runtime_mark_last_busy(i2c->dev);
> + pm_runtime_put_autosuspend(i2c->dev);
> + return 0;
> +
> + err_pm:
> + pm_runtime_put(i2c->dev);
> + pm_runtime_disable(&pdev->dev);
> + err_iomap:
> + iounmap(i2c->regs);
> + err_clk:
> + clk_disable_unprepare(i2c->clk);
> + err_noclk:
> + return ret;
> +}
> +
> +static int exynos5_i2c_remove(struct platform_device *pdev)
> +{
> + struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
> + int ret;
> +
> + ret = pm_runtime_get_sync(&pdev->dev);
> + if (IS_ERR_VALUE(ret))
> + return ret;
> +
> + clk_disable_unprepare(i2c->clk);
> + pm_runtime_put(&pdev->dev);
> + pm_runtime_disable(&pdev->dev);
> +
> + i2c_del_adapter(&i2c->adap);
> +
> + iounmap(i2c->regs);
> + platform_set_drvdata(pdev, NULL);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int exynos5_i2c_suspend_noirq(struct device *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
> +
> + i2c->suspended = 1;
> +
> + return 0;
> +}
> +
> +static int exynos5_i2c_resume_noirq(struct device *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
> +
> + clk_prepare_enable(i2c->clk);
> + exynos5_i2c_init(i2c);
> + clk_disable_unprepare(i2c->clk);
> + i2c->suspended = 0;
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
> + .suspend_noirq = exynos5_i2c_suspend_noirq,
> + .resume_noirq = exynos5_i2c_resume_noirq,
> +};
> +
> +#define EXYNOS5_DEV_PM_OPS (&exynos5_i2c_dev_pm_ops)
> +#else
> +#define EXYNOS5_DEV_PM_OPS NULL
> +#endif
> +
> +static struct platform_driver exynos5_i2c_driver = {
> + .probe = exynos5_i2c_probe,
> + .remove = exynos5_i2c_remove,
> + .driver = {
> + .owner = THIS_MODULE,
> + .name = "exynos5-hsi2c",
> + .pm = EXYNOS5_DEV_PM_OPS,
> + .of_match_table = exynos5_i2c_match,
> + },
> +};
> +
> +static int __init i2c_adap_exynos5_init(void)
> +{
> + return platform_driver_register(&exynos5_i2c_driver);
> +}
> +subsys_initcall(i2c_adap_exynos5_init);
> +
> +static void __exit i2c_adap_exynos5_exit(void)
> +{
> + platform_driver_unregister(&exynos5_i2c_driver);
> +}
> +module_exit(i2c_adap_exynos5_exit);
> +
> +MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
> +MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>");
> +MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>");
> +MODULE_LICENSE("GPL");
> --
> 1.7.9.5
>
Any comments please.
Or shall i re base and resent
--
Shine bright,
(: Nav :)
^ permalink raw reply
* One of these things (CONFIG_HZ) is not like the others..
From: Santosh Shilimkar @ 2013-01-23 5:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130122215257.GU22517@atomide.com>
On Wednesday 23 January 2013 03:22 AM, Tony Lindgren wrote:
> * John Stultz <john.stultz@linaro.org> [130122 11:02]:
>>
>> Correct, with HRT, we actually trigger the HZ-frequency timer tick
>> from an hrtimer (which expires based on the system time driven by
>> the clocksource). Thus even if there is a theoretical error between
>> the ideal HZ and what the hardware can do, that error will not
>> propagate forward.
>
> If there's no cumulative error, sounds like the way to go is to select
> HRT for ARM multiplatform builds and set the HZ to 100 then.
>
HIGH_RES_TIMERS are always enabled by default for OMAP as well as
multi-platform build.
Regards,
Santosh
^ permalink raw reply
* [PATCH v1 0/6] USB: Add support for multiple PHYs of same type
From: kishon @ 2013-01-23 5:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <B9531499-0746-44DA-BDBB-999D4CA31E63@dominion.thruhere.net>
On Tuesday 22 January 2013 10:32 PM, Koen Kooi wrote:
>
> Op 22 jan. 2013, om 17:16 heeft kishon <kishon@ti.com> het volgende geschreven:
>
>> Hi,
>>
>> On Tuesday 22 January 2013 09:15 PM, kishon wrote:
>>> On Tuesday 22 January 2013 09:11 PM, Koen Kooi wrote:
>>>>
>>>> Op 22 jan. 2013, om 10:58 heeft Kishon Vijay Abraham I <kishon@ti.com>
>>>> het volgende geschreven:
>>>>
>>>>> This patch series adds support for adding multiple PHY's (of same type).
>>>>> The binding information has to be present in the PHY library (otg.c) in
>>>>> order for it to return the appropriate PHY whenever the USB controller
>>>>> request for the PHY. So added a new API usb_bind_phy() to pass the
>>>>> binding
>>>>> information. This API should be called by platform specific
>>>>> initialization
>>>>> code.
>>>>>
>>>>> So the binding should be done something like
>>>>> usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto"); specifying
>>>>> the USB
>>>>> controller device name, index, and the PHY device name.
>>>>> I have done this binding for OMAP platforms, but it should be done for
>>>>> all the platforms.
>>>>>
>>>>> After this design, the phy can be got by passing the USB controller
>>>>> device
>>>>> pointer and the index.
>>>>>
>>>>> Developed this patch series on
>>>>> git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git xceiv
>>>>> after applying "usb: musb: add driver for control module" patch series
>>>>> and "ARM: dts: omap: add dt data for MUSB"
>>>>>
>>>>> Did basic enumeration testing in omap4 panda and omap3 beagle.
>>>>
>>>> With this patchset USB completely breaks on am33xx beaglebone, is that
>>>> intended?
>>> Not really.
>>> Does am33xx makes use of omap2430.c? Which PHY does am33xx uses?
>>
>> I figured out it uses drivers/usb/musb/musb_dsps.c (So it doesn't use omap2430.c). I think it uses TWL4030_USB (TPS659x0) as PHY.
>
> Actually it uses nop-phy as a phy, which is missing from arch/arm/boot/dts/am33xx.dtsi, so mainline is already broken. But adding the nop-phy to the DT is easy enough to patch in locally.
Cool. You can add your patch after applying this series then. (I'll post
a new version addressing the comments in this series.)
Thanks
Kishon
^ permalink raw reply
* [PATCH] ARM: dts: add mshc controller node for Exynos4x12 SoCs
From: Dongjin Kim @ 2013-01-23 5:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJuYYwTT+e5e6S7GtK+=PRS_C-3XqARwrb2bqhmehScN3DRT9A@mail.gmail.com>
Hello Thomas,
Thank you. I will submit the change soon.
Thanks again.
Dongjin.
On Wed, Jan 23, 2013 at 8:25 AM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> Hi Dongjin,
>
> On 22 January 2013 10:15, Dongjin Kim <tobetter@gmail.com> wrote:
>> Hi Thomas,
>>
>> Good to see your patch, actually I had sent similar one before but no
>> one care my patch. And now I feel it seems to be wrong.
>>
>> But I have a couple of question if I use your patch to enable MSHC
>> controller work properly on Exynos4412.
>>
>> What's the exact form of ".compatible" on board file?
>> With your patch, MSHC is not probed at all in my board. The
>> ".compatible" has to be 'samsung,exynos5250-dw-mshc' and it works.
>>
>> I also tried '.compatible = "samsung,exynos5250-dw-mshc",
>> "samsung,exynos4412-dw-mshc"', it probes the driver but in the
>> function 'dw_mci_exynos_priv_init', priv->ctrl_type always becomes
>> DW_MCI_TYPE_EXYNOS5250. Because there is a loop and returns each
>> compatible strings in alphanumeric order whatever it is ordered in the
>> board file.
>>
>> I also tried below patch to add a compatible for Exynos4412 to
>> 'dw_mci_exynos_match' with its specific data, and it works. What's the
>> right direction? If I am missing something or wrong, please correct
>> me. :)
>
> Yes, your below patch is the correct thing to do. The dt patches for
> dwmmc controller driver were only tested on Exynos5250 based board. So
> I had not added the compatible string for Exynos4412 in
> 'of_match_table' of the driver. Please submit the below change as a
> patch (minor comment below).
>
>>
>> Many thanks,
>> Dongjin.
>>
>> @@ -184,6 +186,25 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
>> return 0;
>> }
>>
>> +/* Exynos4412 controller specific capabilities */
>> +static unsigned long exynos4412_dwmmc_caps[4] = {
>> + MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
>> + MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
>> + MMC_CAP_CMD23,
>> + MMC_CAP_CMD23,
>> + MMC_CAP_CMD23,
>> +};
>
> Since this is same as the 'exynos5250_dwmmc_caps', it can be reused
> for 4412 as well, avoiding duplicate copy 'exynos4412_dwmmc_caps'.
>
>> +
>> +static const struct dw_mci_drv_data exynos4412_drv_data = {
>> + .caps = exynos4412_dwmmc_caps,
>> + .init = dw_mci_exynos_priv_init,
>> + .setup_clock = dw_mci_exynos_setup_clock,
>> + .prepare_command = dw_mci_exynos_prepare_command,
>> + .set_ios = dw_mci_exynos_set_ios,
>> + .parse_dt = dw_mci_exynos_parse_dt,
>> + .setup_bus = dw_mci_exynos_setup_bus,
>> +};
>
> If the above change is done, 'exynos4412_drv_data ' also could be avoided.
>
>> +
>> /* Exynos5250 controller specific capabilities */
>> static unsigned long exynos5250_dwmmc_caps[4] = {
>> MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
>> @@ -204,6 +225,8 @@ static const struct dw_mci_drv_data exynos5250_drv_data = {
>> };
>>
>> static const struct of_device_id dw_mci_exynos_match[] = {
>> + { .compatible = "samsung,exynos4412-dw-mshc",
>> + .data = &exynos4412_drv_data, },
>> { .compatible = "samsung,exynos5250-dw-mshc",
>> .data = &exynos5250_drv_data, },
>> {},
>
> Thanks,
> Thomas.
>
>>
>>
>> On Mon, Jan 21, 2013 at 7:39 PM, Thomas Abraham
>> <thomas.abraham@linaro.org> wrote:
>>> Commit cea0f256 ("ARM: dts: Add board dts file for ODROID-X") includes a node
>>> to describe the board level properties for mshc controller. But the mshc
>>> controller node was not added in the Exynos4x12 dtsi file which resulted
>>> in the following warning when compiling the dtb files.
>>>
>>> Warning (reg_format): "reg" property in /mshc at 12550000/slot at 0 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
>>> Warning (avoid_default_addr_size): Relying on default #address-cells value for /mshc at 12550000/slot at 0
>>> Warning (avoid_default_addr_size): Relying on default #size-cells value for /mshc at 12550000/slot at 0
>>>
>>> Fix this by adding the mshc controller node for Exynos4x12 SoCs.
>>>
>>> Cc: Dongjin Kim <tobetter@gmail.com>
>>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>>> ---
>>> arch/arm/boot/dts/exynos4412.dtsi | 8 ++++++++
>>> 1 files changed, 8 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
>>> index 78ed377..96f5b66 100644
>>> --- a/arch/arm/boot/dts/exynos4412.dtsi
>>> +++ b/arch/arm/boot/dts/exynos4412.dtsi
>>> @@ -32,4 +32,12 @@
>>> interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
>>> <1 12 0>, <1 12 0>, <1 12 0>, <1 12 0>;
>>> };
>>> +
>>> + mshc at 12550000 {
>>> + compatible = "samsung,exynos4412-dw-mshc";
>>> + reg = <0x12550000 0x1000>;
>>> + interrupts = <0 77 0>;
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + };
>>> };
>>> --
>>> 1.7.5.4
>>>
^ permalink raw reply
* linux-next: manual merge of the tegra tree with the arm-soc tree
From: Stephen Rothwell @ 2013-01-23 5:25 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
Today's linux-next merge of the tegra tree got a conflict in
arch/arm/mach-tegra/common.c between commit 0529e315bbda ("ARM: use
common irqchip_init for GIC init") from the arm-soc tree and commit
567f70da22d2 ("ARM: tegra: migrate to new clock code") from the tegra
tree.
I fixed it up (see below) and can carry the fix as necessary (no action
is required).
--
Cheers,
Stephen Rothwell sfr at canb.auug.org.au
diff --cc arch/arm/mach-tegra/common.c
index 3599959,87dd69c..0000000
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@@ -21,9 -21,11 +21,10 @@@
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/delay.h>
-#include <linux/of_irq.h>
+#include <linux/irqchip.h>
+ #include <linux/clk/tegra.h>
#include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
#include <mach/powergate.h>
@@@ -56,10 -58,16 +57,11 @@@ u32 tegra_uart_config[4] =
};
#ifdef CONFIG_OF
-static const struct of_device_id tegra_dt_irq_match[] __initconst = {
- { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
- { }
-};
-
void __init tegra_dt_init_irq(void)
{
+ tegra_clocks_init();
tegra_init_irq();
- of_irq_init(tegra_dt_irq_match);
+ irqchip_init();
}
#endif
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^ permalink raw reply
* linux-next: manual merge of the tegra tree with the arm-soc tree
From: Stephen Rothwell @ 2013-01-23 5:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
Today's linux-next merge of the tegra tree got a conflict in
arch/arm/mach-tegra/platsmp.c between commit 520f7bd73354 ("irqchip: Move
ARM gic.h to include/linux/irqchip/arm-gic.h") from the arm-soc tree and
commit 4c6e1ff5b5fe ("ARM: tegra: move tegra_cpu_car.h to
linux/clk/tegra.h") from the tegra tree.
I fixed it up (see below) and can carry the fix as necessary (no action
is required).
--
Cheers,
Stephen Rothwell sfr at canb.auug.org.au
diff --cc arch/arm/mach-tegra/platsmp.c
index 18d7290,3ec7fc4..0000000
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@@ -18,11 -18,13 +18,13 @@@
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
+ #include <linux/clk/tegra.h>
#include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
+ #include <asm/smp_plat.h>
#include <mach/powergate.h>
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^ permalink raw reply
* [PATCH] ARM: mach-shmobile: armadillo: defconfig: Enable CEU
From: Simon Horman @ 2013-01-23 5:49 UTC (permalink / raw)
To: linux-arm-kernel
Update the defconfig to enable the CEU camera.
It appears that it was previously enabled but an
update is required for Kconfig changes.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/configs/armadillo800eva_defconfig | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index f9e2701..0b98100 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -90,14 +90,11 @@ CONFIG_I2C_SH_MOBILE=y
# CONFIG_HWMON is not set
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
-# CONFIG_RC_CORE is not set
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-# CONFIG_V4L_USB_DRIVERS is not set
+CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_MT9T112=y
CONFIG_VIDEO_SH_MOBILE_CEU=y
-# CONFIG_RADIO_ADAPTERS is not set
CONFIG_FB=y
CONFIG_FB_SH_MOBILE_LCDC=y
CONFIG_FB_SH_MOBILE_HDMI=y
--
1.7.10.4
^ permalink raw reply related
* [PATCH] ARM: mach-shmobile: mackerel: enable VFP in defconfig
From: Simon Horman @ 2013-01-23 6:00 UTC (permalink / raw)
To: linux-arm-kernel
CONFIG_VFP appears to be required to use the
Debian armhf userspace. Enabling this is consistent
with many other shmobile boards.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/configs/mackerel_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index e6881ac..7594b3a 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -25,6 +25,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_KEXEC=y
+CONFIG_VFP=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_PM=y
CONFIG_PM_RUNTIME=y
--
1.7.10.4
^ permalink raw reply related
* [v3 2/2] ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9
From: Hiroshi Doyu @ 2013-01-23 6:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50FEC503.2080602@wwwdotorg.org>
Stephen Warren <swarren@wwwdotorg.org> wrote @ Tue, 22 Jan 2013 17:57:39 +0100:
> Hiroshi, is this series the only dependency you need for your
> Tegra114
Basically yes.
> series? So, I could merge your Tegra114 series once this series is applied?
But now "CCF" seems to be in. Then, the HACK(*1) needs to be replaced
with "Tegra114 CCF". But "Tegra114 CCF" doesn't seem ready yet. I'll check
if this Tegra114 series would work without "Tegra114 CCF".
*1: http://patchwork.ozlabs.org/patch/212010/
^ permalink raw reply
* [PATCH 1/2 net-next] net: fec: add napi support to improve proformance
From: Eric Dumazet @ 2013-01-23 6:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358914330-3768-1-git-send-email-Frank.Li@freescale.com>
On Wed, 2013-01-23 at 12:12 +0800, Frank Li wrote:
> Add napi support
>
> Before this patch
>
> iperf -s -i 1
> ------------------------------------------------------------
> Server listening on TCP port 5001
> TCP window size: 85.3 KByte (default)
> ------------------------------------------------------------
> [ 4] local 10.192.242.153 port 5001 connected with 10.192.242.138 port 50004
> [ ID] Interval Transfer Bandwidth
> [ 4] 0.0- 1.0 sec 41.2 MBytes 345 Mbits/sec
> [ 4] 1.0- 2.0 sec 43.7 MBytes 367 Mbits/sec
> [ 4] 2.0- 3.0 sec 42.8 MBytes 359 Mbits/sec
> [ 4] 3.0- 4.0 sec 43.7 MBytes 367 Mbits/sec
> [ 4] 4.0- 5.0 sec 42.7 MBytes 359 Mbits/sec
> [ 4] 5.0- 6.0 sec 43.8 MBytes 367 Mbits/sec
> [ 4] 6.0- 7.0 sec 43.0 MBytes 361 Mbits/sec
>
> After this patch
> [ 4] 2.0- 3.0 sec 51.6 MBytes 433 Mbits/sec
> [ 4] 3.0- 4.0 sec 51.8 MBytes 435 Mbits/sec
> [ 4] 4.0- 5.0 sec 52.2 MBytes 438 Mbits/sec
> [ 4] 5.0- 6.0 sec 52.1 MBytes 437 Mbits/sec
> [ 4] 6.0- 7.0 sec 52.1 MBytes 437 Mbits/sec
> [ 4] 7.0- 8.0 sec 52.3 MBytes 439 Mbits/sec
Strange, as you still call netif_rx()
NAPI should call netif_receive_skb() instead
^ permalink raw reply
* [PATCH 23/24] ab8500-bm: Fix minor niggles experienced during testing
From: Anton Vorontsov @ 2013-01-23 6:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130122092717.GI6857@gmail.com>
On Tue, Jan 22, 2013 at 09:27:17AM +0000, Lee Jones wrote:
> On Mon, 21 Jan 2013, Anton Vorontsov wrote:
>
> > On Mon, Jan 21, 2013 at 12:03:59PM +0000, Lee Jones wrote:
> > > When compile testing the new AB8500 Battery Management changes
> > > due for inclusion into upstream, there were a few minor niggles
> > > which required repairing, or adapting for use against the
> > > Mainline kernel. This patch is a collection of them all.
> >
> > No. This is the third time I'm saying it: the last time I checked, this is
> > not how we do development in the mainline.
>
> Okay, all of these changes have now been fixed-up into the patches
> which caused the issues. I have also added Stable to the patch you
> requested it on.
>
> How would you like to proceed? Do you want a pull-request, or for me
> to send the patches to the list again?
Either way will work.
Thanks!
Anton
p.s. I took another look at the patches, and noticed one issue that is
constantly there: you place your signed-off-by line on top of everyones',
but that's wrong. Sign offs are going downwards, not upwards. This is
quite important since the lines encode how the code "travels" between
companies and submitters. Currently, one might assume that the origin of
the code is always Linaro, which is not quite true. (And 'From:' doesn't
always mean the author, fwiw.)
^ permalink raw reply
* [PATCH 2/3] ARM: dts: AM33XX: Add GPMC node
From: Philip, Avinash @ 2013-01-23 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8738xu9rni.fsf@dell.be.48ers.dk>
On Tue, Jan 22, 2013 at 02:31:53, Peter Korsgaard wrote:
> >>>>> "Philip" == Philip Avinash <avinashphilip@ti.com> writes:
>
> Philip> From: "Philip, Avinash" <avinashphilip@ti.com>
> Philip> Add GPMC data node to AM33XX device tree file.
>
> Philip> Signed-off-by: Philip Avinash <avinashphilip@ti.com>
> Philip> ---
> Philip> arch/arm/boot/dts/am33xx.dtsi | 12 ++++++++++++
> Philip> 1 file changed, 12 insertions(+)
>
> Philip> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> Philip> index eaef5e7..f4209d8 100644
> Philip> --- a/arch/arm/boot/dts/am33xx.dtsi
> Philip> +++ b/arch/arm/boot/dts/am33xx.dtsi
> Philip> @@ -393,5 +393,17 @@
> Philip> ti,hwmods = "elm";
> Philip> status = "disabled";
> Philip> };
> Philip> +
> Philip> + gpmc: gpmc at 50000000 {
> Philip> + compatible = "ti,am3352-gpmc";
> Philip> + ti,hwmods = "gpmc";
> Philip> + reg = <0x50000000 0x2000>;
> Philip> + interrupts = <100>;
> Philip> + num-cs = <8>;
>
> Next to Jan's comment about am335x having 7 cs signals, I just realized
> the difference in compatible string between the gpmc and elm. The gpmc
> refers to a real device (which is afaik how it should be done), but the
> elm compatible is simply ti,am33xx-elm.
>
> Presumably it should have been ti,am3352-elm in the binding instead?
I thought of following the file name convention. I will correct to "ti,am3352-elm"
>
> Other than that it looks fine.
>
> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Thanks
Avinash
>
> --
> Bye, Peter Korsgaard
>
^ permalink raw reply
* [PATCH 1/3] ARM: dts: AM33XX: Add ELM node
From: Philip, Avinash @ 2013-01-23 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <877gn69sb9.fsf@dell.be.48ers.dk>
On Tue, Jan 22, 2013 at 02:17:38, Peter Korsgaard wrote:
> >>>>> "Philip" == Philip Avinash <avinashphilip@ti.com> writes:
>
> Philip> From: "Philip, Avinash" <avinashphilip@ti.com>
> Philip> Add ELM data node to AM33XX device tree file.
>
> Philip> Signed-off-by: Philip Avinash <avinashphilip@ti.com>
> Philip> ---
> Philip> arch/arm/boot/dts/am33xx.dtsi | 8 ++++++++
> Philip> 1 file changed, 8 insertions(+)
>
> Philip> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> Philip> index c2f14e8..eaef5e7 100644
> Philip> --- a/arch/arm/boot/dts/am33xx.dtsi
> Philip> +++ b/arch/arm/boot/dts/am33xx.dtsi
> Philip> @@ -385,5 +385,13 @@
> Philip> mac-address = [ 00 00 00 00 00 00 ];
> Philip> };
> Philip> };
> Philip> +
> Philip> + elm: elm at 48080000 {
> Philip> + compatible = "ti,am33xx-elm";
>
> Please drop the <tab> after compatible.
I will replace with space and submit another version
>
> Other than that it looks goood.
>
> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Thanks
Avinash
>
> --
> Bye, Peter Korsgaard
>
^ permalink raw reply
* [PATCH 1/2] misc/at24: Add at24c512b eeprom support
From: Liu Ying @ 2013-01-23 6:32 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds at24c512b eeprom support.
The datasheet of at24c512b can be found at:
http://www.alldatasheet.com/datasheet-pdf/pdf/
256958/ATMEL/AT24C512B-TH-B.html
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
---
Documentation/devicetree/bindings/eeprom.txt | 2 +-
drivers/misc/eeprom/at24.c | 1 +
2 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/bindings/eeprom.txt b/Documentation/devicetree/bindings/eeprom.txt
index 4342c10..fcea214 100644
--- a/Documentation/devicetree/bindings/eeprom.txt
+++ b/Documentation/devicetree/bindings/eeprom.txt
@@ -6,7 +6,7 @@ Required properties:
If there is no specific driver for <manufacturer>, a generic
driver based on <type> is selected. Possible types are:
24c00, 24c01, 24c02, 24c04, 24c08, 24c16, 24c32, 24c64,
- 24c128, 24c256, 24c512, 24c1024, spd
+ 24c128, 24c256, 24c512, 24c512b, 24c1024, spd
- reg : the I2C address of the EEPROM
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index 2baeec5..0df4cb0 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -124,6 +124,7 @@ static const struct i2c_device_id at24_ids[] = {
{ "24c128", AT24_DEVICE_MAGIC(131072 / 8, AT24_FLAG_ADDR16) },
{ "24c256", AT24_DEVICE_MAGIC(262144 / 8, AT24_FLAG_ADDR16) },
{ "24c512", AT24_DEVICE_MAGIC(524288 / 8, AT24_FLAG_ADDR16) },
+ { "24c512b", AT24_DEVICE_MAGIC(524288 / 8, AT24_FLAG_ADDR16) },
{ "24c1024", AT24_DEVICE_MAGIC(1048576 / 8, AT24_FLAG_ADDR16) },
{ "at24", 0 },
{ /* END OF LIST */ }
--
1.7.1
^ permalink raw reply related
* [PATCH 2/2] ARM: dts: imx51-babbage: Add at24c512b eeprom support
From: Liu Ying @ 2013-01-23 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358922764-31654-1-git-send-email-Ying.Liu@freescale.com>
This patch adds at24c512b i2c device to the device tree
along with the necessary i2c device node and pinctrl
settings for i2c bus.
The eeprom chip is populated on the accessory board of
the imx51-babbage board.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
---
arch/arm/boot/dts/imx51-babbage.dts | 12 ++++++++++++
arch/arm/boot/dts/imx51.dtsi | 9 +++++++++
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 567e7ee..4f0fc75 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -241,6 +241,18 @@
};
};
+ i2c at 83fc8000 { /* I2C1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_1>;
+ status = "okay";
+
+ at24 at 50 {
+ compatible = "at24,24c512b";
+ pagesize = <128>;
+ reg = <0x50>;
+ };
+ };
+
audmux at 83fd0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 1f5d45e..6495c69 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -311,6 +311,15 @@
};
};
+ i2c1 {
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ 4 0x400001ed /* MX51_PAD_EIM_D16__I2C1_SDA */
+ 23 0x400001ed /* MX51_PAD_EIM_D19__I2C1_SCL */
+ >;
+ };
+ };
+
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
--
1.7.1
^ permalink raw reply related
* [PATCH 1/2 net-next] net: fec: add napi support to improve proformance
From: Waskiewicz Jr, Peter P @ 2013-01-23 6:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358914330-3768-1-git-send-email-Frank.Li@freescale.com>
On Wed, Jan 23, 2013 at 12:12:10PM +0800, Frank Li wrote:
[...]
> diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
> index f52ba33..8fa420c 100644
> --- a/drivers/net/ethernet/freescale/fec.c
> +++ b/drivers/net/ethernet/freescale/fec.c
> @@ -67,6 +67,8 @@
> #endif
>
> #define DRIVER_NAME "fec"
> +#define FEC_NAPI_WEIGHT 64
> +#define INT32_MAX 0x7FFFFFFF
This seems awfully big as an upper-limit to your ISR processing. See below
for more comments.
>
> /* Pause frame feild and FIFO threshold */
> #define FEC_ENET_FCE (1 << 5)
> @@ -565,6 +567,20 @@ fec_timeout(struct net_device *ndev)
> }
>
> static void
> +fec_enet_rx_int_is_enabled(struct net_device *ndev, bool enabled)
> +{
> + struct fec_enet_private *fep = netdev_priv(ndev);
> + uint int_events;
> +
> + int_events = readl(fep->hwp + FEC_IMASK);
> + if (enabled)
> + int_events |= FEC_ENET_RXF;
> + else
> + int_events &= ~FEC_ENET_RXF;
> + writel(int_events, fep->hwp + FEC_IMASK);
> +}
> +
> +static void
> fec_enet_tx(struct net_device *ndev)
> {
> struct fec_enet_private *fep;
> @@ -656,8 +672,8 @@ fec_enet_tx(struct net_device *ndev)
> * not been given to the system, we just set the empty indicator,
> * effectively tossing the packet.
> */
> -static void
> -fec_enet_rx(struct net_device *ndev)
> +static int
> +fec_enet_rx(struct net_device *ndev, int budget)
> {
> struct fec_enet_private *fep = netdev_priv(ndev);
> const struct platform_device_id *id_entry =
> @@ -667,13 +683,12 @@ fec_enet_rx(struct net_device *ndev)
> struct sk_buff *skb;
> ushort pkt_len;
> __u8 *data;
> + int pkt_received = 0;
>
> #ifdef CONFIG_M532x
> flush_cache_all();
> #endif
>
> - spin_lock(&fep->hw_lock);
> -
> /* First, grab all of the stats for the incoming packet.
> * These get messed up if we get called due to a busy condition.
> */
> @@ -681,6 +696,10 @@ fec_enet_rx(struct net_device *ndev)
>
> while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
>
> + if (pkt_received >= budget)
> + break;
> + pkt_received++;
> +
This seems wrong given how it's called from the ISR when NAPI isn't being
used. If you have continuous packets coming in, you won't exit your ISR
and release your spin_lock until you hit INT32_MAX.
> /* Since we have allocated space to hold a complete frame,
> * the last indicator should be set.
> */
> @@ -796,7 +815,7 @@ rx_processing_done:
> }
> fep->cur_rx = bdp;
>
> - spin_unlock(&fep->hw_lock);
> + return pkt_received;
> }
>
> static irqreturn_t
> @@ -805,6 +824,7 @@ fec_enet_interrupt(int irq, void *dev_id)
> struct net_device *ndev = dev_id;
> struct fec_enet_private *fep = netdev_priv(ndev);
> uint int_events;
> + ulong flags;
> irqreturn_t ret = IRQ_NONE;
>
> do {
> @@ -813,7 +833,18 @@ fec_enet_interrupt(int irq, void *dev_id)
>
> if (int_events & FEC_ENET_RXF) {
> ret = IRQ_HANDLED;
> - fec_enet_rx(ndev);
> + spin_lock_irqsave(&fep->hw_lock, flags);
> +
> + if (fep->use_napi) {
> + /* Disable the RX interrupt */
> + if (napi_schedule_prep(&fep->napi)) {
> + fec_enet_rx_int_is_enabled(ndev, false);
> + __napi_schedule(&fep->napi);
> + }
> + } else
> + fec_enet_rx(ndev, INT32_MAX);
As mentioned above, you may want to check this a bit closer since this
can run for a very, very long time if you have constant packets flowing
when not using NAPI.
Also, the code formatting here should also have braces around the else
clause since the if clause has them.
> +
> + spin_unlock_irqrestore(&fep->hw_lock, flags);
> }
>
> /* Transmit OK, or non-fatal error. Update the buffer
> @@ -834,7 +865,16 @@ fec_enet_interrupt(int irq, void *dev_id)
> return ret;
> }
>
> -
> +static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
> +{
> + struct net_device *ndev = napi->dev;
> + int pkgs = fec_enet_rx(ndev, budget);
> + if (pkgs < budget) {
> + napi_complete(napi);
> + fec_enet_rx_int_is_enabled(ndev, true);
> + }
> + return pkgs;
> +}
>
> /* ------------------------------------------------------------------------- */
> static void fec_get_mac(struct net_device *ndev)
> @@ -1392,6 +1432,9 @@ fec_enet_open(struct net_device *ndev)
> struct fec_enet_private *fep = netdev_priv(ndev);
> int ret;
>
> + if (fep->use_napi)
> + napi_enable(&fep->napi);
> +
> /* I should reset the ring buffers here, but I don't yet know
> * a simple way to do that.
> */
> @@ -1604,6 +1647,11 @@ static int fec_enet_init(struct net_device *ndev)
> ndev->netdev_ops = &fec_netdev_ops;
> ndev->ethtool_ops = &fec_enet_ethtool_ops;
>
> + if (fep->use_napi) {
> + fec_enet_rx_int_is_enabled(ndev, false);
> + netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, fep->napi_weight);
Make sure not to exceed 80 characters here.
> + }
> +
> /* Initialize the receive buffer descriptors. */
> bdp = fep->rx_bd_base;
> for (i = 0; i < RX_RING_SIZE; i++) {
> @@ -1698,6 +1746,7 @@ fec_probe(struct platform_device *pdev)
> static int dev_id;
> struct pinctrl *pinctrl;
> struct regulator *reg_phy;
> + struct device_node *np = pdev->dev.of_node;
>
> of_id = of_match_device(fec_dt_ids, &pdev->dev);
> if (of_id)
> @@ -1811,6 +1860,11 @@ fec_probe(struct platform_device *pdev)
> }
> }
>
> + fep->use_napi = !of_property_read_bool(np, "disable_napi");
> +
> + if (of_property_read_u32(np, "napi_weight", &fep->napi_weight))
> + fep->napi_weight = FEC_NAPI_WEIGHT; /*using default value*/
> +
> fec_reset_phy(pdev);
>
> ret = fec_enet_init(ndev);
> diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
> index 2ebedaf..31fcdd0 100644
> --- a/drivers/net/ethernet/freescale/fec.h
> +++ b/drivers/net/ethernet/freescale/fec.h
> @@ -249,6 +249,10 @@ struct fec_enet_private {
> int bufdesc_ex;
> int pause_flag;
>
> + struct napi_struct napi;
> + int napi_weight;
> + bool use_napi;
> +
> struct ptp_clock *ptp_clock;
> struct ptp_clock_info ptp_caps;
> unsigned long last_overflow_check;
> --
> 1.7.1
>
>
> --
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