* [PATCH v2 1/2] clk: divider: prepare for minimum divider
From: Afzal Mohammed @ 2013-01-23 11:38 UTC (permalink / raw)
To: linux-arm-kernel
Some of clocks can have a limit on minimum divider value that can be
programmed, prepare for such a support.
Add a new field min_div for the basic divider clock and a new dynamic
clock divider registration function where minimum divider value can
be specified. Keep behaviour of existing divider clock registration
functions, static initialization helpers as was earlier.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
v2: create a new registration function for those that needs to
constrain minimum divider value instead of modifying existing
registration functions and hence remove modification in other
clock files.
drivers/clk/clk-divider.c | 37 ++++++++++++++++++++++++++++++++++---
include/linux/clk-private.h | 6 +++++-
include/linux/clk-provider.h | 7 +++++++
3 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index a9204c6..4025c5a 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -236,7 +236,7 @@ EXPORT_SYMBOL_GPL(clk_divider_ops);
static struct clk *_register_divider(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
- void __iomem *reg, u8 shift, u8 width,
+ void __iomem *reg, u8 shift, u8 width, u8 min_div,
u8 clk_divider_flags, const struct clk_div_table *table,
spinlock_t *lock)
{
@@ -244,6 +244,11 @@ static struct clk *_register_divider(struct device *dev, const char *name,
struct clk *clk;
struct clk_init_data init;
+ if (!min_div) {
+ pr_err("%s: minimum divider cannot be zero\n", __func__);
+ return ERR_PTR(-EINVAL);
+ }
+
/* allocate the divider */
div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
if (!div) {
@@ -261,6 +266,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
div->reg = reg;
div->shift = shift;
div->width = width;
+ div->min_div = min_div;
div->flags = clk_divider_flags;
div->lock = lock;
div->hw.init = &init;
@@ -276,6 +282,29 @@ static struct clk *_register_divider(struct device *dev, const char *name,
}
/**
+ * clk_register_min_divider - register a divider clock having minimum divider
+ * constraints with clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust divider
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @min_div: minimum allowable divider
+ * @clk_divider_flags: divider-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
+struct clk *clk_register_min_divider(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width, u8 min_div,
+ u8 clk_divider_flags, spinlock_t *lock)
+{
+ return _register_divider(dev, name, parent_name, flags, reg, shift,
+ width, min_div, clk_divider_flags, NULL, lock);
+}
+
+/**
* clk_register_divider - register a divider clock with the clock framework
* @dev: device registering this clock
* @name: name of this clock
@@ -293,7 +322,8 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
u8 clk_divider_flags, spinlock_t *lock)
{
return _register_divider(dev, name, parent_name, flags, reg, shift,
- width, clk_divider_flags, NULL, lock);
+ width, CLK_DIVIDER_MIN_DIV_DEFAULT, clk_divider_flags,
+ NULL, lock);
}
/**
@@ -317,5 +347,6 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
spinlock_t *lock)
{
return _register_divider(dev, name, parent_name, flags, reg, shift,
- width, clk_divider_flags, table, lock);
+ width, CLK_DIVIDER_MIN_DIV_DEFAULT, clk_divider_flags,
+ table, lock);
}
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 9c7f580..942a1be 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -105,7 +105,8 @@ struct clk {
#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
_flags, _reg, _shift, _width, \
- _divider_flags, _table, _lock) \
+ _min_div, _divider_flags, \
+ _table, _lock) \
static struct clk _name; \
static const char *_name##_parent_names[] = { \
_parent_name, \
@@ -120,6 +121,7 @@ struct clk {
.reg = _reg, \
.shift = _shift, \
.width = _width, \
+ .min_div = _min_div, \
.flags = _divider_flags, \
.table = _table, \
.lock = _lock, \
@@ -132,6 +134,7 @@ struct clk {
_divider_flags, _lock) \
_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
_flags, _reg, _shift, _width, \
+ CLK_DIVIDER_MIN_DIV_DEFAULT, \
_divider_flags, NULL, _lock)
#define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name, \
@@ -140,6 +143,7 @@ struct clk {
_table, _lock) \
_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
_flags, _reg, _shift, _width, \
+ CLK_DIVIDER_MIN_DIV_DEFAULT, \
_divider_flags, _table, _lock) \
#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 4989b8a..1c09481 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -248,15 +248,22 @@ struct clk_divider {
void __iomem *reg;
u8 shift;
u8 width;
+ u8 min_div;
u8 flags;
const struct clk_div_table *table;
spinlock_t *lock;
};
+#define CLK_DIVIDER_MIN_DIV_DEFAULT 1
+
#define CLK_DIVIDER_ONE_BASED BIT(0)
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
extern const struct clk_ops clk_divider_ops;
+struct clk *clk_register_min_divider(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width, u8 min_div,
+ u8 clk_divider_flags, spinlock_t *lock);
struct clk *clk_register_divider(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 shift, u8 width,
--
1.7.12
^ permalink raw reply related
* [GIT PULL] power: ab8500-bm: Latest Mainline<->STE delta reduction patch-set
From: Lee Jones @ 2013-01-23 11:38 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 8fd526fd18233887ba652079a369f4eee0de9d9d:
qnap-poweroff: Fix license string (2013-01-19 18:04:04 -0800)
are available in the git repository at:
git://git.linaro.org/people/ljones/linux-3.0-ux500.git tb-power-2
for you to fetch changes up to 19db37d598705c273f6b5ab261b9115d065ffb5b:
u8500-charger: Delay for USB enumeration (2013-01-23 11:33:17 +0000)
----------------------------------------------------------------
Hakan Berg (1):
ab8500-fg: Adjust for RF bursts voltage drops
Henrik S?lver (1):
ab8500-charger: AB workaround for invalid charger
Jonas Aaberg (2):
ab8500-bm: Flush all work queues before suspending
ab8500-charger: Do not touch VBUSOVV bits
Lee Jones (5):
ab8500-charger: Kick watchdog
ab8500-chargalg: Update battery health on safety timer exp
ab8500-chargalg: Only root should have write permission on sysfs
file
abx500-chargalg: Add new sysfs interface to get current charge
status
ab8500-bm: Remove individual [charger|btemp|fg|chargalg] pdata
structures
Loic Pallardy (3):
pm2301: Add deep debug
pm2301: Remove volt_now & curr_now properties
pm2301: Update watchdog for pm2xxx support
Martin Bergstr?m (1):
ab8500-fg: Go to INIT_RECOVERY when charger removed
Michel JAOUEN (4):
pm2301: Provide u9540 support for the pm2301 charger
ab8500-btemp: Adaptation to AB8505 and AB9540 platforms
ab8500-fg: Add test interface for u9540
ab8500-fg-deepdebug: Create Deep Debug interface
Nicolas Guion (1):
ab8500-charger: Add support for autopower on AB8505 and AB9540
Olivier Clergeaud (1):
pm2301: Clean-up PM2301 interrupt management
Paer-Olof Haakansson (1):
u8500-charger: Delay for USB enumeration
Rajkumar Kasirajan (2):
pm2301: Enable vbat low monitoring
ab8500-fg: Use correct battery charge full design
Rupesh Kumar (1):
pm2301: LPN mode control support
drivers/mfd/ab8500-core.c | 6 +
drivers/power/Kconfig | 26 +
drivers/power/Makefile | 3 +
drivers/power/ab8500_btemp.c | 67 +-
drivers/power/ab8500_charger.c | 629 ++++++++---
drivers/power/ab8500_fg.c | 316 ++----
drivers/power/ab8500_fg.h | 244 +++++
drivers/power/ab8500_fg_deepdebug.c | 1692 +++++++++++++++++++++++++++++
drivers/power/abx500_chargalg.c | 43 +-
drivers/power/pm2301_charger.c | 1097 +++++++++++++++++++
drivers/power/pm2301_charger.h | 535 +++++++++
drivers/power/pm2301_deepdebug.c | 131 +++
include/linux/mfd/abx500.h | 3 +
include/linux/mfd/abx500/ab8500-bm.h | 186 +++-
include/linux/mfd/abx500/ab8500.h | 19 +
include/linux/mfd/abx500/ux500_chargalg.h | 5 +
include/linux/pm2301_charger.h | 61 ++
17 files changed, 4655 insertions(+), 408 deletions(-)
create mode 100644 drivers/power/ab8500_fg.h
create mode 100644 drivers/power/ab8500_fg_deepdebug.c
create mode 100644 drivers/power/pm2301_charger.c
create mode 100644 drivers/power/pm2301_charger.h
create mode 100644 drivers/power/pm2301_deepdebug.c
create mode 100644 include/linux/pm2301_charger.h
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v2 2/2] clk: divider: handle minimum divider
From: Afzal Mohammed @ 2013-01-23 11:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6dc1c48cac5b2646a55da3079afb72f88e40c3bc.1358937138.git.afzal@ti.com>
Some of clocks can have a limit on minimum divider value that can be
programmed. Modify basic clock divider to take care of this aspect.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
drivers/clk/clk-divider.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 4025c5a..ee648dc 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -32,6 +32,11 @@
#define div_mask(d) ((1 << (d->width)) - 1)
#define is_power_of_two(i) !(i & ~i)
+static unsigned int _get_mindiv(struct clk_divider *divider)
+{
+ return divider->min_div;
+}
+
static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
{
unsigned int maxdiv = 0;
@@ -148,17 +153,18 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
{
struct clk_divider *divider = to_clk_divider(hw);
int i, bestdiv = 0;
- unsigned long parent_rate, best = 0, now, maxdiv;
+ unsigned long parent_rate, best = 0, now, maxdiv, mindiv;
if (!rate)
rate = 1;
maxdiv = _get_maxdiv(divider);
+ mindiv = _get_mindiv(divider);
if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
parent_rate = *best_parent_rate;
bestdiv = DIV_ROUND_UP(parent_rate, rate);
- bestdiv = bestdiv == 0 ? 1 : bestdiv;
+ bestdiv = bestdiv == 0 ? mindiv : bestdiv;
bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
return bestdiv;
}
@@ -169,7 +175,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
*/
maxdiv = min(ULONG_MAX / rate, maxdiv);
- for (i = 1; i <= maxdiv; i++) {
+ for (i = mindiv; i <= maxdiv; i++) {
if (!_is_valid_div(divider, i))
continue;
parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
--
1.7.12
^ permalink raw reply related
* [PATCH v2 0/4] ARM: AM335x: LCDC platform support
From: Afzal Mohammed @ 2013-01-23 11:41 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This series make am335x lcdc capable of providing display.
Certain changes were required in generic OMAP clock handling
to attain it. Clock nodes in LCDC path is marked such that
rate can get propogated to upstream clocks till display PLL.
Based on 3.8-rc3.
Tested on AM335x EVM.
To test on AM335x based boards, tree
@ git://gitorious.org/x0148406-public/linux-kernel.git tags/da8xx-fb-dt-v4
Regards
Afzal
v2: As DEFINE_CLK_DIVIDER args has no change, make it's usage as reqd.
Afzal Mohammed (4):
ARM: OMAP2+: dpll: round rate to closest value
ARM: OMAP2+: dpll: am335x - avoid freqsel
ARM: OMAP2+: clock: DEFINE_STRUCT_CLK_FLAGS helper
ARM: AM33XX: clock: SET_RATE_PARENT in lcd path
arch/arm/mach-omap2/cclock33xx_data.c | 10 ++++++----
arch/arm/mach-omap2/clkt_dpll.c | 12 +++++++-----
arch/arm/mach-omap2/clock.h | 11 +++++++++++
arch/arm/mach-omap2/dpll3xxx.c | 5 +++--
4 files changed, 27 insertions(+), 11 deletions(-)
--
1.7.12
^ permalink raw reply
* [PATCH v2 1/4] ARM: OMAP2+: dpll: round rate to closest value
From: Afzal Mohammed @ 2013-01-23 11:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1358937533.git.afzal@ti.com>
Currently round rate function would return proper rate iff requested
rate exactly matches the PLL lockable rate. This causes set_rate to
fail if exact rate could not be set. Instead round rate may return
closest rate possible (less than the requested). And if any user is
badly in need of exact rate, then return value of round rate could
be used to decide whether to invoke set rate or not.
Modify round rate so that it return closest possible rate.
This was required to get display working on am335x. Without this
display rate could not be set (taking help of SET_RATE_PARENT). Couple
of the downstream clocks of display PLL are basic clock dividers and
they do MULT_ROUND_UP before requesting rate on PLL causing values
that mostly could not be locked by PLL. And even otherwise, if
requested rate for a particular pixel clock could not be satisfied by
PLL, display would not work. This change will resolve the issue.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/clkt_dpll.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 924c230..15e6d41 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -345,20 +345,22 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
clk_name, m, n, new_rate);
- if (target_rate == new_rate) {
+ if ((new_rate <= target_rate) &&
+ (new_rate > dd->last_rounded_rate)) {
dd->last_rounded_m = m;
dd->last_rounded_n = n;
- dd->last_rounded_rate = target_rate;
- break;
+ dd->last_rounded_rate = new_rate;
+ if (new_rate == target_rate)
+ break;
}
}
- if (target_rate != new_rate) {
+ if (!dd->last_rounded_rate) {
pr_debug("clock: %s: cannot round to rate %ld\n",
clk_name, target_rate);
return ~0;
}
- return target_rate;
+ return dd->last_rounded_rate;
}
--
1.7.12
^ permalink raw reply related
* [PATCH v2 2/4] ARM: OMAP2+: dpll: am335x - avoid freqsel
From: Afzal Mohammed @ 2013-01-23 11:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1358937533.git.afzal@ti.com>
am335x does not have freqsel, avoid it.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/dpll3xxx.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 0a02aab5..3aed4b0 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -500,8 +500,9 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
if (dd->last_rounded_rate == 0)
return -EINVAL;
- /* No freqsel on OMAP4 and OMAP3630 */
- if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+ /* No freqsel on AM335x, OMAP4 and OMAP3630 */
+ if (!soc_is_am33xx() && !cpu_is_omap44xx() &&
+ !cpu_is_omap3630()) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n);
WARN_ON(!freqsel);
--
1.7.12
^ permalink raw reply related
* [PATCH v2 3/4] ARM: OMAP2+: clock: DEFINE_STRUCT_CLK_FLAGS helper
From: Afzal Mohammed @ 2013-01-23 11:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1358937533.git.afzal@ti.com>
DEFINE_STRUCT_CLK does not have the capability to set flags, define
DEFINE_STRUCT_CLK_FLAGS to handle flags. This is needed to add
SET_RATE_PARENT flag in statically defined lcd clock in am335x.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
arch/arm/mach-omap2/clock.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b402048..60ddd86 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,17 @@ struct clockdomain;
.ops = &_clkops_name, \
};
+#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
+ _clkops_name, _flags) \
+ static struct clk _name = { \
+ .name = #_name, \
+ .hw = &_name##_hw.hw, \
+ .parent_names = _parent_array_name, \
+ .num_parents = ARRAY_SIZE(_parent_array_name), \
+ .ops = &_clkops_name, \
+ .flags = _flags, \
+ };
+
#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
static struct clk_hw_omap _name##_hw = { \
.hw = { \
--
1.7.12
^ permalink raw reply related
* [PATCH 7/9] ARM: at91/at91_dt_defconfig: remove memory specification to cmdline
From: Nicolas Ferre @ 2013-01-23 11:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130123102057.GJ7360@game.jcrosoft.org>
On 01/23/2013 11:20 AM, Jean-Christophe PLAGNIOL-VILLARD :
> On 10:48 Wed 23 Jan , Nicolas Ferre wrote:
>> No need for this cmdline option as we are using DT.
>> Moreover this defconfig is targeted to multiple SoC/boards: this option
>> was nonsense.
> just keep the console the rest is a nonsense too
>
> as on 9g45 the initrd will be at 0x7xxxxxxx
BTW, how do you mix 9g45 with other sam9's in this defconfig: it is not
possible due to this difference in address rage, it not it?
In this case, should we remove the
CONFIG_SOC_AT91SAM9G45=y
from this at91_dt_defconfig?
> the console too but as the patch serie to support via DT is not yet mainline
> we can keep it
>
> Best Regards,
> J.
>>
>> Reported-by: Josh Wu <josh.wu@atmel.com>
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>> ---
>> arch/arm/configs/at91_dt_defconfig | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
>> index b175577..a353ff6 100644
>> --- a/arch/arm/configs/at91_dt_defconfig
>> +++ b/arch/arm/configs/at91_dt_defconfig
>> @@ -31,7 +31,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
>> CONFIG_ZBOOT_ROM_BSS=0x0
>> CONFIG_ARM_APPENDED_DTB=y
>> CONFIG_ARM_ATAG_DTB_COMPAT=y
>> -CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
>> +CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
>> CONFIG_KEXEC=y
>> CONFIG_AUTO_ZRELADDR=y
>> # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
Bye,
--
Nicolas Ferre
^ permalink raw reply
* [PATCH v2 4/4] ARM: AM33XX: clock: SET_RATE_PARENT in lcd path
From: Afzal Mohammed @ 2013-01-23 11:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1358937533.git.afzal@ti.com>
LCDC clock node is a one that does not have set rate capability. It
just passes on the rate that is sent downstream by it's parent. While
lcdc clock parent and it's grand parent - dpll_disp_m2_ck and
dpll_disp_ck has the capability to configure rate.
And the default rates provided by LCDC clock's ancestors are not
sufficient to obtain pixel clock for current LCDC use cases, hence
currently display would not work on AM335x SoC's (with driver
modifications in platfrom independent way).
Hence inform clock framework to propogate set rate for LCDC clock as
well as it's parent - dpll_disp_m2_ck. With this change, set rate on
LCDC clock would get propogated till dpll_disp_ck via dpll_disp_m2_ck,
hence allowing the driver (same driver is used in DaVinci too) to set
rates using LCDC clock without worrying about platform dependent clock
details.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
v2: As DEFINE_CLK_DIVIDER args has no change, make it's usage as reqd.
arch/arm/mach-omap2/cclock33xx_data.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index ea64ad6..476b820 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -284,9 +284,10 @@ DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
* TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
* and ALT_CLK1/2)
*/
-DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0,
- AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
- AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
+ CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
+ AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
+ CLK_DIVIDER_ONE_BASED, NULL);
/* DPLL_PER */
static struct dpll_data dpll_per_dd = {
@@ -723,7 +724,8 @@ static struct clk_hw_omap lcd_gclk_hw = {
.clksel_mask = AM33XX_CLKSEL_0_1_MASK,
};
-DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops);
+DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
+ gpio_fck_ops, CLK_SET_RATE_PARENT);
DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
--
1.7.12
^ permalink raw reply related
* [V4 PATCH 18/26] usb: phy: mv_usb2_phy: add externel chip support
From: Felipe Balbi @ 2013-01-23 11:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CADApbeghH7EdQaz7PP-pPK4huhxJ0OrLDEGTHBg4s0+3SQbRoA@mail.gmail.com>
Hi,
On Tue, Jan 22, 2013 at 10:51:32AM +0800, Chao Xie wrote:
> On Mon, Jan 21, 2013 at 11:51 PM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
> > On Mon, Jan 21, 2013 at 05:07:36AM -0500, Chao Xie wrote:
> >> + mv_phy->extern_chip.head = devm_kzalloc(&pdev->dev,
> >> + sizeof(*mv_phy->extern_chip.head),
> >> + GFP_KERNEL);
> >> + if (mv_phy->extern_chip.head == NULL)
> >> + return -ENOMEM;
> >> + ATOMIC_INIT_NOTIFIER_HEAD(mv_phy->extern_chip.head);
> >
> > Why do you need to allocate an atomic notifier list head as an entirely
> > separate data structure?
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
>
> Th reason is that the original code seperate the extern_chip and phy
> support. So it depends
> on the ->head to detect whether extern_chip is initialized or not.
> Now it is combined with phy, the ->phy pointer can do the job.
does that need to be dynamically allocated ?
--
balbi
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* [V4 PATCH 00/26] mv-usb fix and enhancement patches
From: Felipe Balbi @ 2013-01-23 11:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358762864-9249-1-git-send-email-chao.xie@marvell.com>
Hi,
On Mon, Jan 21, 2013 at 05:07:18AM -0500, Chao Xie wrote:
> The patches are divied into 4 parts
> 1. bug fixes
> usb: gadget: mv_udc: use udc_start and udc_stop functions
> usb: gadget: mv_udc: use devm_xxx for probe
> usb: gadget: mv_udc: fix the warning of mv_udc_remove
> usb: otg: mv_otg: use devm_xxx for probe
> usb: host: ehci-mv: remove unused variable
> usb: gadget: mv_udc: fix the value of tranceiver
> usb: gadget: mv_udc: make mv_udc depends on ARCH_MMP or ARCH_PXA
> Above patches are bug fixes.
>
> 2. PHY driver
> To remove the callbacks in the platform data, a usb PHY driver
> for marvell udc/otg/ehci is written.
> For device tree support, it is not good to pass the callback
> pointers by platform data. The PHY driver also removes the
> block.
>
> usb: phy: mv_usb2: add PHY driver for marvell usb2 controller
> usb: gadget: mv_udc: use PHY driver for udc
> usb: ehci: ehci-mv: use PHY driver for ehci
> usb: otg: mv_otg: use PHY driver for otg
> Above patches are marvell usb PHY driver support.
>
> arm: mmp2: change the defintion of usb devices
> arm: pxa910: change the defintion of usb devices
> arm: brownstone: add usb support for the board
> arm: ttc_dkb: add usb support
> arm: mmp: remove the usb phy setting
> arm: mmp: remove usb devices from pxa168
> Above patches are for SOC/board support for marvell usb PHY
> driver.
>
> 3. external chip support
> The marvell usb controller can detect the vbus/idpin, but it
> need PHY and usb clocks to be enabled.
> Based on measurement it will import 15mA current, and increase
> the power when the usb is not used.
> Using a external chip to detect vbus/idpin changes will save
> the power.
> In fact the marvell PMIC 88pm860x and 88pm80x can do it. The
> drivers are located at drivers/mfd.
> So add a middle layer in the marvell usb PHY driver.
> PMIC call the APIs in middle driver to registers the callback
> for vbus/idpin detection/query
> udc/otg/ehci driver will call the APIs to get vbus/idpin changes
> and query the states of the vbus/idpin.
> usb: phy: mv_usb2_phy: add externel chip support
> usb: gadget: mv_udc: add extern chip support
> usb: ehci: ehci-mv: add extern chip support
> usb: otg: mv_otg: add extern chip support
> Above patches are the middle layer suppor for udc/otg/ehci
>
> arm: mmp: add extern chip support for brownstone
> arm: mmp: add extern chip support for ttc_dkb
> Above patches are corresponding board file changes
>
> 4. device tree support
> After removing the callbacks in platform data, and the not
> constant variables in platform data. All the information needed
> by udc/otg/ehci driver are constant.
>
> usb: gadget: mv_udc: add device tree support
> usb: otg: mv_otg: add device tree support
> usb: ehci: ehci-mv: add device tree support
> Above patches are device tree support for udc/otg/ehci driver.
this series will be delayed for v3.10. Sorry
--
balbi
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* [PATCH] ARM: mach-ux500: enable 128KB way L2 cache on DB8540
From: Linus Walleij @ 2013-01-23 12:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358936878-29806-1-git-send-email-fabio.baltieri@linaro.org>
On Wed, Jan 23, 2013 at 11:27 AM, Fabio Baltieri
<fabio.baltieri@linaro.org> wrote:
> From: Maxime Coquelin <maxime.coquelin@stericsson.com>
>
> DB8540 L2 was configured with 64KB way size, but it has 128KB as AP9540.
>
> Fix this by modifying ux500_l2x0_init() to use 128KB way size for all
> cpus in the x540 family.
>
> Signed-off-by: Maxime Coquelin <maxime.coquelin@stericsson.com>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org>
Applied to my ux500-core branch.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 1/2] misc/at24: Add at24c512b eeprom support
From: Linus Walleij @ 2013-01-23 12:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358922764-31654-1-git-send-email-Ying.Liu@freescale.com>
On Wed, Jan 23, 2013 at 7:32 AM, Liu Ying <Ying.Liu@freescale.com> wrote:
> This patch adds at24c512b eeprom support.
> The datasheet of at24c512b can be found at:
> http://www.alldatasheet.com/datasheet-pdf/pdf/
> 256958/ATMEL/AT24C512B-TH-B.html
>
> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Arnd Bergmann is the misc maintainer, route this by him.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] Implements DMA on mmci driver for LPC3250 plateform
From: Ezequiel Garcia @ 2013-01-23 12:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AB1CB712-43B0-4E47-9752-91447BD749B9@precidata.com>
Gabriele,
On Wed, Jan 23, 2013 at 7:11 AM, Gabriele Mondada
<gabriele@precidata.com> wrote:
> Signed-off-by: Gabriele Mondada <gabriele@precidata.com>
>
> UPDATE: Here is the patch cleaned up and validated with scripts/checkpatch.pl. I also add a check to prevent crashing when DMA is disabled.
>
> ORIGINAL POST:
> Hi,
> Currently, LPC32xx plateform do not enable DMA on the mmci driver. This makes the driver useless because getting out data from a 64 bytes FIFO by interrupt is not fast enough (at standard SD-card data rate).
>
> DMA is not enabled because LPC32xx has a bug that prevent DMA to work properly with the MMC controller (silicon bug, I guess). NXP did a patch to workaround this, but it has not been commited on the main branch. The patch is for linux 2.6.39.2 and does not use dmaengine.
>
> So, I reworked this patch to make it compatible with the last kernel (3.7). Here it is. Have I any chance to see this patch be commited on the main branch?
>
You can add this sort of description, that's not intended as part of the
commit message after the "---" line and before the diff stat (*).
It's typically used to add a changelog.
See here:
http://permalink.gmane.org/gmane.linux.ports.arm.omap/92215
Also, given you seem to be having some problems preparing the patch
I suggest you to watch Greg's talk on submitting first patch:
http://www.youtube.com/watch?v=LLBrBBImJt4
>
> ---
(*) here!
> drivers/dma/amba-pl08x.c | 20 ++++++
> drivers/mmc/host/mmci.c | 159 +++++++++++++++++++++++++++++++++++++++++-----
> drivers/mmc/host/mmci.h | 12 +++-
> 3 files changed, 174 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> index d1cc579..728f65f 100644
> --- a/drivers/dma/amba-pl08x.c
> +++ b/drivers/dma/amba-pl08x.c
> @@ -1758,6 +1758,26 @@ static void pl08x_free_virtual_channels(struct dma_device *dmadev)
> }
> }
[...]
--
Ezequiel
^ permalink raw reply
* [PATCH 00/10] rework gpio pxa driver for pinctrl
From: Linus Walleij @ 2013-01-23 12:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358929554-32265-1-git-send-email-haojian.zhuang@linaro.org>
On Wed, Jan 23, 2013 at 9:25 AM, Haojian Zhuang
<haojian.zhuang@linaro.org> wrote:
> Remove all cpu depend macro. Bind gpio pxa driver with pinctrl driver.
Please route this patch series by Mika so he can test it on his
funny hardware too.
Can we have this based on top of Mika's patches of these work
out fine on the PXA?
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2] Dove: activate GPIO interrupts in DT
From: Jason Cooper @ 2013-01-23 12:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130123093816.5cb73df1@armhf>
On Wed, Jan 23, 2013 at 09:38:16AM +0100, Jean-Francois Moine wrote:
> In a DT, the interrupts of an interrupt-controller are not usable when
> #interrupt-cells is missing.
>
> This patch activates the interrupts of the GPIOs 0 and 1 for the Marvell
> Dove SoC.
>
> Signed-off-by: Jean-Fran?ois Moine <moinejf@free.fr>
> ---
> v2
> - gpio-mvebu asks for 2 cells
> ---
> arch/arm/boot/dts/dove.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
Applied to mvebu/fixes
thx,
Jason.
^ permalink raw reply
* [alsa-devel] [PATCH V2 2/2] ASoC: Davinci: machine: Add device tree binding
From: Hebbar, Gururaja @ 2013-01-23 12:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130104122612.GM4627@opensource.wolfsonmicro.com>
On Fri, Jan 04, 2013 at 17:56:12, Mark Brown wrote:
> On Fri, Jan 04, 2013 at 03:24:37PM +0530, Hebbar Gururaja wrote:
>
> > + "MIC3L", "Mic Bias 2V",
> > + "MIC3R", "Mic Bias 2V",
> > + "Mic Bias 2V", "Mic Jack",
>
> The CODEC driver biases should be changed over to be supplies, this
> makes the above much more natural - the routing there is a hack for
> older versions of ASoc. Otherwise this looks fine.
ON TLV320AIC3x Codec, MIC Bias power on/off share the same register bits
with Bias voltage output.
Page 0 / Register 25: MICBIAS Control Register
BIT READ/WRITE RESET VALUE DESCRIPTION
D7?D6 R/W 00 MICBIAS Level Control
00: MICBIAS output is powered down
01: MICBIAS output is powered to 2.0V
10: MICBIAS output is powered to 2.5V
11: MICBIAS output is connected to AVDD
Because of this, I find it difficult to use SND_SOC_DAPM_SUPPLY macro.
I found a similar implementation (MIC BIAS enable + Bias voltage selection)
in 2 other platform (WM8900 & SGTL5000).
WM8900 --> Different registers for MIC BIAS enable & Bias voltage selection.
However both are implemented using different macros
static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
static const struct soc_enum mic_bias_level =
SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
...
static const struct snd_kcontrol_new wm8900_snd_controls[] = {
SOC_ENUM("Mic Bias Level", mic_bias_level),
...
SND_SOC_DAPM_SUPPLY("Mic Bias", WM8900_REG_POWER1, 4, 0, NULL, 0),
SGTL5000 --> Single register for MIC BIAS enable & output impedance of MIC
Bias. The driver uses SND_SOC_DAPM_POST_PMU & SND_SOC_DAPM_PRE_PMD macro to
handle the MIC Bias enable & disable event.
static int mic_bias_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
...
static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
...
SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
mic_bias_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
Since TLV320AIC3x Codec uses single register bit-set to indicate BIA state
& Voltage level, I am not able to able to change existing code to
SND_SOC_DAPM_SUPPLY macro.
Could you please show some pointers on how to handle/implement
SND_SOC_DAPM_SUPPLY in above scenario?
Thanks & Regards,
Gururaja
^ permalink raw reply
* [PATCH 7/9] ARM: at91/at91_dt_defconfig: remove memory specification to cmdline
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-01-23 12:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50FFCC92.2080906@atmel.com>
On 12:42 Wed 23 Jan , Nicolas Ferre wrote:
> On 01/23/2013 11:20 AM, Jean-Christophe PLAGNIOL-VILLARD :
> > On 10:48 Wed 23 Jan , Nicolas Ferre wrote:
> >> No need for this cmdline option as we are using DT.
> >> Moreover this defconfig is targeted to multiple SoC/boards: this option
> >> was nonsense.
> > just keep the console the rest is a nonsense too
> >
> > as on 9g45 the initrd will be at 0x7xxxxxxx
>
> BTW, how do you mix 9g45 with other sam9's in this defconfig: it is not
> possible due to this difference in address rage, it not it?
>
> In this case, should we remove the
> CONFIG_SOC_AT91SAM9G45=y
> from this at91_dt_defconfig?
no you just need to boot the zImage from barebox
barebox handle automaticaly where the kernel is supposed to run
and the kernel found his running/decompressing address at runtime too
Best Regards,
J.
^ permalink raw reply
* [PATCH 0/5 v3] at91: PMECC: enable PMECC in dt for at91sam9x5ek, at91sam9n12ek
From: Josh Wu @ 2013-01-23 12:47 UTC (permalink / raw)
To: linux-arm-kernel
Those patches will enable PMECC in dt parameters for at91sam9x5ek and
at91sam9n12ek.
The PMECC driver will check minimum required ecc on ONFI parameter from NAND
flash.
If pmecc-cap, pmecc-sector-size in dts file is specified, use those two.
otherwise, set those according to NAND flash ONFI parameters.
If the pmecc-cap, pmecc-sector-size in dts are different with ecc requirement
in ONFI, print out a warning.
For the following compile error:
ERROR (phandle_references): Reference to non-existent node or label "pinctrl_ssc0_tx"
ERROR: Input tree has errors, aborting (use -f to force output)
make[2]: *** [arch/arm/boot/dts/at91sam9g20ek.dtb] Error 2
the fixes are already merged in Linux mainline in v3.8-rc4.
you can find in:
544ae6b2e676c3c37fb8c93ef9327932fc2e5bc2 (ARM: at91/dts: add pinctrl support for SSC peripheral)
ea03c81521bde526570e1dec96eaa21fe5ac84a2 (ASoC: atmel-ssc: add pinctrl selection to driver)
Change logs:
v2: rebase to v3.8-rc3. And wrapped the commit message.
v3: big chages:
1. reduce the PMECC lookup table mapping. Just the lookup table not whole
ROM code according to J.C's suggestion.
2. use simpler strategy to handle pmecc-cap, pmecc-sector-size:
* make pmecc-cap, pmecc-sector-size optional.
* If pmecc-cap, pmecc-sector-size are not set, use ONFI ecc parameters.
otherwise, use those in DTS file.
* print out a warning if PMECC use different ecc bits or sector size
from ONFI ecc parameters.
Josh Wu (5):
MTD: atmel_nand: avoid to report an error when lookup table offset is
0.
ARM: at91: at91sam9x5: add DT parameters to enable PMECC
ARM: at91: at91sam9n12: add DT parameters to enable PMECC
MTD: atmel_nand: make pmecc-cap, pmecc-sector-size in dts is
optional.
MTD: at91: atmel_nand: for PMECC, add code to check the ONFI
parameter ECC requirement.
arch/arm/boot/dts/at91sam9n12.dtsi | 3 +-
arch/arm/boot/dts/at91sam9n12ek.dts | 5 +-
arch/arm/boot/dts/at91sam9x5.dtsi | 4 +
arch/arm/boot/dts/at91sam9x5cm.dtsi | 5 +-
drivers/mtd/nand/atmel_nand.c | 141 +++++++++++++++++++++++++++++------
5 files changed, 131 insertions(+), 27 deletions(-)
--
1.7.9.5
^ permalink raw reply
* [PATCH 1/5] MTD: atmel_nand: avoid to report an error when lookup table offset is 0.
From: Josh Wu @ 2013-01-23 12:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358945232-2282-1-git-send-email-josh.wu@atmel.com>
Before this patch, we assume the whole ROM code are mapping to memory. So
it is wrong if the lookup table offset is 0.
After this patch, we can map only the lookup table of ROM code to memory
intead of the whole ROM code (about 1M). In this case, one lookup table
offset can be 0.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
---
drivers/mtd/nand/atmel_nand.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index c516a94..1d989db 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1215,7 +1215,7 @@ static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
static int atmel_of_init_port(struct atmel_nand_host *host,
struct device_node *np)
{
- u32 val, table_offset;
+ u32 val;
u32 offset[2];
int ecc_mode;
struct atmel_nand_data *board = &host->board;
@@ -1288,13 +1288,12 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
return -EINVAL;
}
- table_offset = host->pmecc_sector_size == 512 ? offset[0] : offset[1];
-
- if (!table_offset) {
+ if (!offset[0] && !offset[1]) {
dev_err(host->dev, "Invalid PMECC lookup table offset\n");
return -EINVAL;
}
- host->pmecc_lookup_table_offset = table_offset;
+ host->pmecc_lookup_table_offset =
+ (host->pmecc_sector_size == 512) ? offset[0] : offset[1];
return 0;
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/5] ARM: at91: at91sam9x5: add DT parameters to enable PMECC
From: Josh Wu @ 2013-01-23 12:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358945232-2282-1-git-send-email-josh.wu@atmel.com>
Default ecc correctable setting is 2bits in 512 bytes.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
---
arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++++
arch/arm/boot/dts/at91sam9x5cm.dtsi | 5 ++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 3a47cf9..ecfafcf 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -498,7 +498,11 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x10000000
+ 0xffffe000 0x600 /* PMECC Registers */
+ 0xffffe600 0x200 /* PMECC Error Location Registers */
+ 0x00108000 0x18000 /* PMECC looup table in ROM code */
>;
+ atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 31e7be2..4027ac7 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -26,7 +26,10 @@
ahb {
nand0: nand at 40000000 {
nand-bus-width = <8>;
- nand-ecc-mode = "soft";
+ nand-ecc-mode = "hw";
+ atmel,has-pmecc; /* Enable PMECC */
+ atmel,pmecc-cap = <2>;
+ atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
--
1.7.9.5
^ permalink raw reply related
* [PATCH 3/5] ARM: at91: at91sam9n12: add DT parameters to enable PMECC
From: Josh Wu @ 2013-01-23 12:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358945232-2282-1-git-send-email-josh.wu@atmel.com>
Default ecc correctable setting is 2bits in 512 bytes.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
---
arch/arm/boot/dts/at91sam9n12.dtsi | 3 ++-
arch/arm/boot/dts/at91sam9n12ek.dts | 5 ++++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 80e29c6..a3a3fdb 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -390,8 +390,9 @@
reg = < 0x40000000 0x10000000
0xffffe000 0x00000600
0xffffe600 0x00000200
- 0x00100000 0x00100000
+ 0x00108000 0x00018000
>;
+ atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 0376bf4..d400f8d 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -71,7 +71,10 @@
nand0: nand at 40000000 {
nand-bus-width = <8>;
- nand-ecc-mode = "soft";
+ nand-ecc-mode = "hw";
+ atmel,has-pmecc;
+ atmel,pmecc-cap = <2>;
+ atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 4/5] MTD: atmel_nand: make pmecc-cap, pmecc-sector-size in dts is optional.
From: Josh Wu @ 2013-01-23 12:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358945232-2282-1-git-send-email-josh.wu@atmel.com>
If those two are not specified in dts file, driver will report an error.
TODO: in this case, driver will find ecc requirement in NAND ONFI parameters.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
---
drivers/mtd/nand/atmel_nand.c | 52 ++++++++++++++++++++++++-----------------
1 file changed, 31 insertions(+), 21 deletions(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 1d989db..f186a37 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -101,6 +101,8 @@ struct atmel_nand_host {
u8 pmecc_corr_cap;
u16 pmecc_sector_size;
u32 pmecc_lookup_table_offset;
+ u32 pmecc_lookup_table_offset_512;
+ u32 pmecc_lookup_table_offset_1024;
int pmecc_bytes_per_sector;
int pmecc_sector_number;
@@ -916,8 +918,16 @@ static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
struct resource *regs, *regs_pmerr, *regs_rom;
int cap, sector_size, err_no;
+ if (host->pmecc_corr_cap == 0 || host->pmecc_sector_size == 0)
+ /* TODO: Should use ONFI ecc parameters. */
+ return -EINVAL;
+
cap = host->pmecc_corr_cap;
sector_size = host->pmecc_sector_size;
+ host->pmecc_lookup_table_offset = (sector_size == 512) ?
+ host->pmecc_lookup_table_offset_512 :
+ host->pmecc_lookup_table_offset_1024;
+
dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
cap, sector_size);
@@ -1259,29 +1269,29 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
/* use PMECC, get correction capability, sector size and lookup
* table offset.
+ * If correction bits and sector size are not specified, then find
+ * them from NAND ONFI parameters.
*/
- if (of_property_read_u32(np, "atmel,pmecc-cap", &val) != 0) {
- dev_err(host->dev, "Cannot decide PMECC Capability\n");
- return -EINVAL;
- } else if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
- (val != 24)) {
- dev_err(host->dev,
- "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
- val);
- return -EINVAL;
+ if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
+ if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
+ (val != 24)) {
+ dev_err(host->dev,
+ "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
+ val);
+ return -EINVAL;
+ }
+ host->pmecc_corr_cap = (u8)val;
}
- host->pmecc_corr_cap = (u8)val;
- if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) != 0) {
- dev_err(host->dev, "Cannot decide PMECC Sector Size\n");
- return -EINVAL;
- } else if ((val != 512) && (val != 1024)) {
- dev_err(host->dev,
- "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
- val);
- return -EINVAL;
+ if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
+ if ((val != 512) && (val != 1024)) {
+ dev_err(host->dev,
+ "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
+ val);
+ return -EINVAL;
+ }
+ host->pmecc_sector_size = (u16)val;
}
- host->pmecc_sector_size = (u16)val;
if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
offset, 2) != 0) {
@@ -1292,8 +1302,8 @@ static int atmel_of_init_port(struct atmel_nand_host *host,
dev_err(host->dev, "Invalid PMECC lookup table offset\n");
return -EINVAL;
}
- host->pmecc_lookup_table_offset =
- (host->pmecc_sector_size == 512) ? offset[0] : offset[1];
+ host->pmecc_lookup_table_offset_512 = offset[0];
+ host->pmecc_lookup_table_offset_1024 = offset[1];
return 0;
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH 5/5] MTD: at91: atmel_nand: for PMECC, add code to check the ONFI parameter ECC requirement.
From: Josh Wu @ 2013-01-23 12:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358945232-2282-1-git-send-email-josh.wu@atmel.com>
This patch will check NAND flash's ecc minimum requirement in ONFI parameter.
1. if pmecc-cap, pmecc-sector-size is set in dts. then use it. Driver will
print out a WARNING if the values are different from ONFI parameters.
2. if pmecc-cap, pmecc-sector-size is not set in dts, then use the value
from ONFI parameters.
* If ONFI ECC parameters are in ONFI extended parameter page, since we are
not support it, so assume the minimum ecc requirement is 2 bits in 512
bytes.
* For non-ONFI support nand flash, also assume the minimum ecc requirement is
2 bits in 512 bytes.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
---
drivers/mtd/nand/atmel_nand.c | 90 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 87 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index f186a37..ffcbcca 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -910,6 +910,84 @@ static void atmel_pmecc_core_init(struct mtd_info *mtd)
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
}
+/*
+ * Get ECC requirement in ONFI parameters, returns -1 if ONFI
+ * parameters is not supported.
+ * return 0 if success to get the ECC requirement.
+ */
+static int get_onfi_ecc_param(struct nand_chip *chip,
+ int *ecc_bits, int *sector_size)
+{
+ *ecc_bits = *sector_size = 0;
+
+ if (chip->onfi_params.ecc_bits == 0xff)
+ /* TODO: the sector_size and ecc_bits need to be find in
+ * extended ecc parameter, currently we don't support it.
+ */
+ return -1;
+
+ *ecc_bits = chip->onfi_params.ecc_bits;
+
+ /* The default sector size (ecc codeword size) is 512 */
+ *sector_size = 512;
+
+ return 0;
+}
+
+/*
+ * Get ecc requirement from ONFI parameters ecc requirement.
+ * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
+ * will set them according to ONFI ecc requirement. Otherwise, use the
+ * value in DTS file.
+ * return 0 if success. otherwise return error code.
+ */
+static int pmecc_choose_ecc(struct atmel_nand_host *host,
+ int *cap, int *sector_size)
+{
+ /* Get ECC requirement from ONFI parameters */
+ *cap = *sector_size = 0;
+ if (host->nand_chip.onfi_version) {
+ if (!get_onfi_ecc_param(&host->nand_chip, cap, sector_size))
+ dev_info(host->dev, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
+ *cap, *sector_size);
+ else
+ dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
+ } else {
+ dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
+ }
+ if (*cap == 0 && *sector_size == 0) {
+ *cap = 2;
+ *sector_size = 512;
+ }
+
+ /* If dts file doesn't specify then use the one in ONFI parameters */
+ if (host->pmecc_corr_cap == 0) {
+ /* use the most fitable ecc bits (the near bigger one ) */
+ if (*cap <= 2)
+ host->pmecc_corr_cap = 2;
+ else if (*cap <= 4)
+ host->pmecc_corr_cap = 4;
+ else if (*cap < 8)
+ host->pmecc_corr_cap = 8;
+ else if (*cap < 12)
+ host->pmecc_corr_cap = 12;
+ else if (*cap < 24)
+ host->pmecc_corr_cap = 24;
+ else
+ return -EINVAL;
+ }
+ if (host->pmecc_sector_size == 0) {
+ /* use the most fitable sector size (the near smaller one ) */
+ if (*sector_size >= 1024)
+ host->pmecc_sector_size = 1024;
+ else if (*sector_size >= 512)
+ host->pmecc_sector_size = 512;
+ else
+ return -EINVAL;
+ }
+ return 0;
+}
+
static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
struct atmel_nand_host *host)
{
@@ -918,9 +996,15 @@ static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
struct resource *regs, *regs_pmerr, *regs_rom;
int cap, sector_size, err_no;
- if (host->pmecc_corr_cap == 0 || host->pmecc_sector_size == 0)
- /* TODO: Should use ONFI ecc parameters. */
- return -EINVAL;
+ err_no = pmecc_choose_ecc(host, &cap, §or_size);
+ if (err_no) {
+ dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
+ return err_no;
+ }
+
+ if (cap != host->pmecc_corr_cap ||
+ sector_size != host->pmecc_sector_size)
+ dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
cap = host->pmecc_corr_cap;
sector_size = host->pmecc_sector_size;
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/2] misc/at24: Add at24c512b eeprom support
From: Wolfram Sang @ 2013-01-23 12:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdbQcyO82Z7+v61VmJBOHuPVT2ZphQQT7OpZ9edYbho5YQ@mail.gmail.com>
On Wed, Jan 23, 2013 at 01:24:52PM +0100, Linus Walleij wrote:
> On Wed, Jan 23, 2013 at 7:32 AM, Liu Ying <Ying.Liu@freescale.com> wrote:
>
> > This patch adds at24c512b eeprom support.
> > The datasheet of at24c512b can be found at:
> > http://www.alldatasheet.com/datasheet-pdf/pdf/
> > 256958/ATMEL/AT24C512B-TH-B.html
> >
> > Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
>
> Arnd Bergmann is the misc maintainer, route this by him.
I usually take at24 patches via my I2C tree.
But not this one, though. The 512b can equally use the 512 entry. The
devicetree should contain both entries, the 512 one as a fallback. (And
the vendor is not "at24"!)
Regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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