* [PATCH] ARM: dts: add mshc controller node for Exynos4x12 SoCs
From: Dongjin Kim @ 2013-01-23 15:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CADoNuNcF3oVEN3y-j4cxu2YLK0+YXLfCOAs1mU9jL2-Gbi98RA@mail.gmail.com>
Tested-by: Dongjin Kim <tobetter@gmail.com>
This patch had been tested on v3.8-rc4 with ODROID-X hardware.
On Wed, Jan 23, 2013 at 2:21 PM, Dongjin Kim <tobetter@gmail.com> wrote:
> Hello Thomas,
>
> Thank you. I will submit the change soon.
>
> Thanks again.
> Dongjin.
>
> On Wed, Jan 23, 2013 at 8:25 AM, Thomas Abraham
> <thomas.abraham@linaro.org> wrote:
>> Hi Dongjin,
>>
>> On 22 January 2013 10:15, Dongjin Kim <tobetter@gmail.com> wrote:
>>> Hi Thomas,
>>>
>>> Good to see your patch, actually I had sent similar one before but no
>>> one care my patch. And now I feel it seems to be wrong.
>>>
>>> But I have a couple of question if I use your patch to enable MSHC
>>> controller work properly on Exynos4412.
>>>
>>> What's the exact form of ".compatible" on board file?
>>> With your patch, MSHC is not probed at all in my board. The
>>> ".compatible" has to be 'samsung,exynos5250-dw-mshc' and it works.
>>>
>>> I also tried '.compatible = "samsung,exynos5250-dw-mshc",
>>> "samsung,exynos4412-dw-mshc"', it probes the driver but in the
>>> function 'dw_mci_exynos_priv_init', priv->ctrl_type always becomes
>>> DW_MCI_TYPE_EXYNOS5250. Because there is a loop and returns each
>>> compatible strings in alphanumeric order whatever it is ordered in the
>>> board file.
>>>
>>> I also tried below patch to add a compatible for Exynos4412 to
>>> 'dw_mci_exynos_match' with its specific data, and it works. What's the
>>> right direction? If I am missing something or wrong, please correct
>>> me. :)
>>
>> Yes, your below patch is the correct thing to do. The dt patches for
>> dwmmc controller driver were only tested on Exynos5250 based board. So
>> I had not added the compatible string for Exynos4412 in
>> 'of_match_table' of the driver. Please submit the below change as a
>> patch (minor comment below).
>>
>>>
>>> Many thanks,
>>> Dongjin.
>>>
>>> @@ -184,6 +186,25 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
>>> return 0;
>>> }
>>>
>>> +/* Exynos4412 controller specific capabilities */
>>> +static unsigned long exynos4412_dwmmc_caps[4] = {
>>> + MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
>>> + MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
>>> + MMC_CAP_CMD23,
>>> + MMC_CAP_CMD23,
>>> + MMC_CAP_CMD23,
>>> +};
>>
>> Since this is same as the 'exynos5250_dwmmc_caps', it can be reused
>> for 4412 as well, avoiding duplicate copy 'exynos4412_dwmmc_caps'.
>>
>>> +
>>> +static const struct dw_mci_drv_data exynos4412_drv_data = {
>>> + .caps = exynos4412_dwmmc_caps,
>>> + .init = dw_mci_exynos_priv_init,
>>> + .setup_clock = dw_mci_exynos_setup_clock,
>>> + .prepare_command = dw_mci_exynos_prepare_command,
>>> + .set_ios = dw_mci_exynos_set_ios,
>>> + .parse_dt = dw_mci_exynos_parse_dt,
>>> + .setup_bus = dw_mci_exynos_setup_bus,
>>> +};
>>
>> If the above change is done, 'exynos4412_drv_data ' also could be avoided.
>>
>>> +
>>> /* Exynos5250 controller specific capabilities */
>>> static unsigned long exynos5250_dwmmc_caps[4] = {
>>> MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
>>> @@ -204,6 +225,8 @@ static const struct dw_mci_drv_data exynos5250_drv_data = {
>>> };
>>>
>>> static const struct of_device_id dw_mci_exynos_match[] = {
>>> + { .compatible = "samsung,exynos4412-dw-mshc",
>>> + .data = &exynos4412_drv_data, },
>>> { .compatible = "samsung,exynos5250-dw-mshc",
>>> .data = &exynos5250_drv_data, },
>>> {},
>>
>> Thanks,
>> Thomas.
>>
>>>
>>>
>>> On Mon, Jan 21, 2013 at 7:39 PM, Thomas Abraham
>>> <thomas.abraham@linaro.org> wrote:
>>>> Commit cea0f256 ("ARM: dts: Add board dts file for ODROID-X") includes a node
>>>> to describe the board level properties for mshc controller. But the mshc
>>>> controller node was not added in the Exynos4x12 dtsi file which resulted
>>>> in the following warning when compiling the dtb files.
>>>>
>>>> Warning (reg_format): "reg" property in /mshc at 12550000/slot at 0 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
>>>> Warning (avoid_default_addr_size): Relying on default #address-cells value for /mshc at 12550000/slot at 0
>>>> Warning (avoid_default_addr_size): Relying on default #size-cells value for /mshc at 12550000/slot at 0
>>>>
>>>> Fix this by adding the mshc controller node for Exynos4x12 SoCs.
>>>>
>>>> Cc: Dongjin Kim <tobetter@gmail.com>
>>>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>>>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>>>> ---
>>>> arch/arm/boot/dts/exynos4412.dtsi | 8 ++++++++
>>>> 1 files changed, 8 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
>>>> index 78ed377..96f5b66 100644
>>>> --- a/arch/arm/boot/dts/exynos4412.dtsi
>>>> +++ b/arch/arm/boot/dts/exynos4412.dtsi
>>>> @@ -32,4 +32,12 @@
>>>> interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
>>>> <1 12 0>, <1 12 0>, <1 12 0>, <1 12 0>;
>>>> };
>>>> +
>>>> + mshc at 12550000 {
>>>> + compatible = "samsung,exynos4412-dw-mshc";
>>>> + reg = <0x12550000 0x1000>;
>>>> + interrupts = <0 77 0>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + };
>>>> };
>>>> --
>>>> 1.7.5.4
>>>>
^ permalink raw reply
* [PATCH] ARM: sunxi: gpio: Add Allwinner SoCs GPIO drivers
From: Linus Walleij @ 2013-01-23 15:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358933646-12681-2-git-send-email-maxime.ripard@free-electrons.com>
On Wed, Jan 23, 2013 at 10:34 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The IP responsible for the muxing on the Allwinner SoCs are also
> handling the GPIOs on the system. This patch adds the needed driver that
> relies on the pinctrl driver for most of its operations.
>
> The number of pins available for GPIOs operations are already declared
> in the pinctrl driver, we only need to probe a generic driver to handle
> the banks available for each SoC.
>
> This driver has been tested on a A13-Olinuxino.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Overall this is VERY NICE!
> + char *func, *pin_name;
(...)
> + pin_name = kzalloc(5, GFP_KERNEL);
> + if (!pin_name)
> + return -ENOMEM;
> +
> + ret = sprintf(pin_name, "P%c%d", 'A' + bank, pin);
> + if (!ret)
> + goto error;
(...)
> +error:
> + kfree(pin_name);
Isn't this a bit awkward?
Can't you either use something like a local
static char foo[MAX_SIZE]; or atleast try to use
one of the static string print functions from <linux/kernel.h>:
/* lib/printf utilities */
extern __printf(2, 3) int sprintf(char *buf, const char * fmt, ...);
extern __printf(2, 0) int vsprintf(char *buf, const char *, va_list);
extern __printf(3, 4)
int snprintf(char *buf, size_t size, const char *fmt, ...);
extern __printf(3, 0)
int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
extern __printf(3, 4)
int scnprintf(char *buf, size_t size, const char *fmt, ...);
extern __printf(3, 0)
int vscnprintf(char *buf, size_t size, const char *fmt, va_list args);
extern __printf(2, 3)
char *kasprintf(gfp_t gfp, const char *fmt, ...);
extern char *kvasprintf(gfp_t gfp, const char *fmt, va_list args);
Yours,
Linus Walleij
^ permalink raw reply
* [alsa-devel] [PATCH V2 2/2] ASoC: Davinci: machine: Add device tree binding
From: Mark Brown @ 2013-01-23 15:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1BAFE6F6C881BF42822005164F1491C33EB50DCF@DBDE01.ent.ti.com>
On Wed, Jan 23, 2013 at 12:39:35PM +0000, Hebbar, Gururaja wrote:
> On Fri, Jan 04, 2013 at 17:56:12, Mark Brown wrote:
> > The CODEC driver biases should be changed over to be supplies, this
> > makes the above much more natural - the routing there is a hack for
> > older versions of ASoc. Otherwise this looks fine.
> ON TLV320AIC3x Codec, MIC Bias power on/off share the same register bits
> with Bias voltage output.
So you need to use an event to write the actual enable bit.
> SGTL5000 --> Single register for MIC BIAS enable & output impedance of MIC
> Bias. The driver uses SND_SOC_DAPM_POST_PMU & SND_SOC_DAPM_PRE_PMD macro to
> handle the MIC Bias enable & disable event.
This is the way these things should be handled.
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^ permalink raw reply
* [PATCH 1/2] usb: host: tegra: don't touch EMC clock
From: Stephen Warren @ 2013-01-23 16:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358934326.1540.32.camel@tellur>
On 01/23/2013 02:45 AM, Lucas Stach wrote:
> Am Mittwoch, den 23.01.2013, 12:25 +0530 schrieb Venu Byravarasu:
>>> -----Original Message-----
>>> From: linux-tegra-owner at vger.kernel.org [mailto:linux-tegra-
>>> owner at vger.kernel.org] On Behalf Of Stephen Warren
>>> Sent: Wednesday, January 23, 2013 5:58 AM
>>> To: Alan Stern; Greg Kroah-Hartman; Stephen Warren
>>> Cc: Venu Byravarasu; linux-tegra at vger.kernel.org; linux-arm-
>>> kernel at lists.infradead.org; linux-usb at vger.kernel.org; Stephen Warren
>>> Subject: [PATCH 1/2] usb: host: tegra: don't touch EMC clock
>>>
>>> From: Stephen Warren <swarren@nvidia.com>
>>>
>>> Clock "emc" is for the External Memory Controller. The USB driver has no
>>> business touching this clock directly. Remove the code that does so.
>>
>> Stephen,
>> This was primarily done to make sure that EMC is set to a minimum
>> frequency, below which data errors may occur during USB transfers.
>> If we plan to remove this, how should we make sure that the EMC
>> is programmed for the required frequency during USB transfers?
>
> You could use something like the API I added in "ARM: tegra: add EMC
> clock scaling API". This needs some rework and I looked into integrating
> this with the DEVFREQ framework, but I don't think it fits too well.
>
> Bandwidth requirements should always be communicated to the EMC driver
> and not described by clock rates.
I agree.
Besides, on some boards there's an EMC scaling table defined already, so
the EMC driver is simply overriding the value the USB driver selects anyway.
^ permalink raw reply
* [PATCH 5/8] ARM: shmobile: add a GPIO controller DT node for sh7372
From: Guennadi Liakhovetski @ 2013-01-23 16:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4209290.uCBdrcvT3q@avalon>
Hi Laurent
Thanks for your comments. All will be addressed except for this one:
On Mon, 21 Jan 2013, Laurent Pinchart wrote:
> Hi Guennadi,
>
> Thanks for the patch.
>
> On Wednesday 16 January 2013 18:08:14 Guennadi Liakhovetski wrote:
> > Add a missing GPIO controller node to sh7372.
> >
> > Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
> > ---
> > arch/arm/boot/dts/sh7372.dtsi | 8 ++++++++
> > 1 files changed, 8 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
> > index 582fdec..7ca9322 100644
> > --- a/arch/arm/boot/dts/sh7372.dtsi
> > +++ b/arch/arm/boot/dts/sh7372.dtsi
> > @@ -19,6 +19,14 @@
> > };
> > };
> >
> > + gpio: pfc at e6050000 {
> > + compatible = "renesas,pfc-sh7372";
> > + reg = <0xe6050000 0x8000>,
> > + <0xe605800c 0x20>;
>
> Shouldn't the second one be
>
> <0xe605800c 0x1c>;
>
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + };
> > +
>
> I haven't checked the board files, have you made sure that the PFC device
> won't be instantiated twice, once from DT and once from board code ?
Don't think so. board-mackerel.c uses DT in a really dull way - it doesn't
call of_platform_populate(). It also initialises interrupts by calling
sh7372_init_irq(), which would conflict with intc instances in sh7372.dtsi
too, if the latter were used. And board-mackerel-reference.c doesn't
register PFC internally.
Thanks
Guennadi
>
> > soc {
> > compatible = "simple-bus";
> > #address-cells = <1>;
>
> --
> Regards,
>
> Laurent Pinchart
>
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
^ permalink raw reply
* [v4 PATCH 06/12] spi/atmel_spi: add dmaengine support
From: Richard Genoud @ 2013-01-23 16:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358148877-18679-7-git-send-email-wenyou.yang@atmel.com>
2013/1/14 Wenyou Yang <wenyou.yang@atmel.com>:
> From: Nicolas Ferre <nicolas.ferre@atmel.com>
>
> Add dmaengine support.
>
> For different SoC, the "has_dma_support" is used to select
> the transfer mode: dmaengine or PDC.
>
> For the dmaengine transfer mode, if it fails to config dmaengine,
> or if the message len less than 16 bytes, it will use the PIO transfer mode.
>
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> [wenyou.yang at atmel.com: using "has_dma_support" to select DMA as the spi xfer mode]
> [wenyou.yang at atmel.com: add support NPCS1,2,3 chip select other than NPCS0]
> [wenyou.yang at atmel.com: fix DMA: OOPS if buffer > 4096 bytes]
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> Cc: grant.likely at secretlab.ca
> Cc: spi-devel-general at lists.sourceforge.net
> Cc: richard.genoud at gmail.com
> ---
> This patch is based on the original patch from Nicolas
> [PATCH] spi/atmel_spi: add dmaengine support
> and merge the patches from Richard Genoud <richard.genoud@gmail.com>
> [PATCH] spi-atmel: update with dmaengine interface
> [PATCH] spi-atmel: fix __init/__devinit sections mismatch
> and Wenyou Yang add the code to support selecting the spi transfer mode,
> add support NPCS1,2,3 chip select other than NPCS0.
> fix DMA: OOPS if buffer > 4096 bytes.
>
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index 43c1f63..0d242dc 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -15,11 +15,13 @@
> #include <linux/platform_device.h>
> #include <linux/delay.h>
> #include <linux/dma-mapping.h>
> +#include <linux/dmaengine.h>
> #include <linux/err.h>
> #include <linux/interrupt.h>
> #include <linux/spi/spi.h>
> #include <linux/slab.h>
> #include <linux/platform_data/atmel.h>
> +#include <linux/platform_data/dma-atmel.h>
> #include <linux/of.h>
>
> #include <asm/io.h>
> @@ -182,6 +184,19 @@
> #define spi_writel(port,reg,value) \
> __raw_writel((value), (port)->regs + SPI_##reg)
>
> +/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
> + * cache operations; better heuristics consider wordsize and bitrate.
> + */
> +#define DMA_MIN_BYTES 16
> +
> +struct atmel_spi_dma {
> + struct dma_chan *chan_rx;
> + struct dma_chan *chan_tx;
> + struct scatterlist sgrx;
> + struct scatterlist sgtx;
> + struct dma_async_tx_descriptor *data_desc_rx;
> + struct dma_async_tx_descriptor *data_desc_tx;
> +};
>
> /*
> * The core SPI transfer engine just talks to a register bank to set up
> @@ -192,6 +207,7 @@ struct atmel_spi_pdata {
> u8 version;
> bool has_dma_support;
> bool has_wdrbt;
> + struct at_dma_slave dma_slave;
> };
>
> struct atmel_spi {
> @@ -207,6 +223,7 @@ struct atmel_spi {
>
> u8 stopping;
> struct list_head queue;
> + struct tasklet_struct tasklet;
> struct spi_transfer *current_transfer;
> unsigned long current_remaining_bytes;
> struct spi_transfer *next_transfer;
> @@ -214,8 +231,15 @@ struct atmel_spi {
> int done_status;
> struct atmel_spi_pdata *pdata;
>
> + bool use_dma;
> + bool use_pdc;
> +
> + /* scratch buffer */
> void *buffer;
> dma_addr_t buffer_dma;
> +
> + /* dmaengine data */
> + struct atmel_spi_dma dma;
> };
>
> /* Controller-specific per-slave state */
> @@ -328,9 +352,7 @@ static bool atmel_spi_is_v2(struct atmel_spi *as)
> * and (c) will trigger that first erratum in some cases.
> *
> * TODO: Test if the atmel_spi_is_v2() branch below works on
> - * AT91RM9200 if we use some other register than CSR0. However, don't
> - * do this unconditionally since AP7000 has an errata where the BITS
> - * field in CSR0 overrides all other CSRs.
> + * AT91RM9200 if we use some other register than CSR0.
> */
>
> static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
> @@ -340,18 +362,16 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
> u32 mr;
>
> if (atmel_spi_is_v2(as)) {
> - /*
> - * Always use CSR0. This ensures that the clock
> - * switches to the correct idle polarity before we
> - * toggle the CS.
> - */
> - spi_writel(as, CSR0, asd->csr);
> + spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
>
> if (as->pdata->has_wdrbt)
> - spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MSTR)
> - | SPI_BIT(MODFDIS) | SPI_BIT(WDRBT));
> + spi_writel(as, MR,
> + SPI_BF(PCS, ~(0x01 << spi->chip_select))
> + | SPI_BIT(MSTR) | SPI_BIT(MODFDIS)
> + | SPI_BIT(WDRBT));
> else
> - spi_writel(as, MR, SPI_BF(PCS, 0x0e)
> + spi_writel(as, MR,
> + SPI_BF(PCS, ~(0x01 << spi->chip_select))
> | SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
>
> mr = spi_readl(as, MR);
> @@ -414,6 +434,12 @@ static void atmel_spi_unlock(struct atmel_spi *as)
> spin_unlock_irqrestore(&as->lock, as->flags);
> }
>
> +static inline bool atmel_spi_use_dma(struct atmel_spi *as,
> + struct spi_transfer *xfer)
> +{
> + return as->use_dma && xfer->len >= DMA_MIN_BYTES;
> +}
> +
> static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
> struct spi_transfer *xfer)
> {
> @@ -425,6 +451,220 @@ static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
> return xfer->delay_usecs == 0 && !xfer->cs_change;
> }
>
> +static bool filter(struct dma_chan *chan, void *slave)
> +{
> + struct at_dma_slave *sl = slave;
> +
> + if (sl->dma_dev == chan->device->dev) {
> + chan->private = sl;
> + return true;
> + } else {
> + return false;
> + }
> +}
> +
> +static int __devinit atmel_spi_configure_dma(struct atmel_spi *as)
> +{
> + struct at_dma_slave *sdata
> + = (struct at_dma_slave *)&as->pdata->dma_slave;
> +
> + if (sdata && sdata->dma_dev) {
> + dma_cap_mask_t mask;
> +
> + /* setup DMA addresses */
> + sdata->rx_reg = (dma_addr_t)as->phybase + SPI_RDR;
> + sdata->tx_reg = (dma_addr_t)as->phybase + SPI_TDR;
> +
> + /* Try to grab two DMA channels */
> + dma_cap_zero(mask);
> + dma_cap_set(DMA_SLAVE, mask);
> + as->dma.chan_tx = dma_request_channel(mask, filter, sdata);
> + if (as->dma.chan_tx)
> + as->dma.chan_rx =
> + dma_request_channel(mask, filter, sdata);
> + }
> + if (!as->dma.chan_rx || !as->dma.chan_tx) {
> + if (as->dma.chan_rx)
> + dma_release_channel(as->dma.chan_rx);
> + if (as->dma.chan_tx)
> + dma_release_channel(as->dma.chan_tx);
> + dev_err(&as->pdev->dev,
> + "DMA channel not available, unable to use SPI\n");
> + return -EBUSY;
> + }
> +
> + dev_info(&as->pdev->dev,
> + "Using %s (tx) and %s (rx) for DMA transfers\n",
> + dma_chan_name(as->dma.chan_tx),
> + dma_chan_name(as->dma.chan_rx));
> +
> + return 0;
> +}
> +
> +static void atmel_spi_stop_dma(struct atmel_spi *as)
> +{
> + if (as->dma.chan_rx)
> + as->dma.chan_rx->device->device_control(as->dma.chan_rx,
> + DMA_TERMINATE_ALL, 0);
> + if (as->dma.chan_tx)
> + as->dma.chan_tx->device->device_control(as->dma.chan_tx,
> + DMA_TERMINATE_ALL, 0);
> +}
> +
> +static void atmel_spi_release_dma(struct atmel_spi *as)
> +{
> + if (as->dma.chan_rx)
> + dma_release_channel(as->dma.chan_rx);
> + if (as->dma.chan_tx)
> + dma_release_channel(as->dma.chan_tx);
> +}
> +
> +/* This function is called by the DMA driver from tasklet context */
> +static void dma_callback(void *data)
> +{
> + struct spi_master *master = data;
> + struct atmel_spi *as = spi_master_get_devdata(master);
> +
> + /* trigger SPI tasklet */
> + tasklet_schedule(&as->tasklet);
> +}
> +
> +/*
> + * Next transfer using PIO.
> + * lock is held, spi tasklet is blocked
> + */
> +static void atmel_spi_next_xfer_pio(struct spi_master *master,
> + struct spi_transfer *xfer)
> +{
> + struct atmel_spi *as = spi_master_get_devdata(master);
> +
> + dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
> +
> + as->current_remaining_bytes = xfer->len;
> +
> + /* Make sure data is not remaining in RDR */
> + spi_readl(as, RDR);
> + while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
> + spi_readl(as, RDR);
> + cpu_relax();
> + }
> +
> + if (xfer->tx_buf)
> + spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
> + else
> + spi_writel(as, TDR, 0);
> +
> + dev_dbg(master->dev.parent,
> + " start pio xfer %p: len %u tx %p rx %p\n",
> + xfer, xfer->len, xfer->tx_buf, xfer->rx_buf);
> +
> + /* Enable relevant interrupts */
> + spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
> +}
> +
> +/*
> + * Submit next transfer for DMA.
> + * lock is held, spi tasklet is blocked
> + */
> +static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
> + struct spi_transfer *xfer,
> + u32 *plen)
> +{
> + struct atmel_spi *as = spi_master_get_devdata(master);
> + struct dma_chan *rxchan = as->dma.chan_rx;
> + struct dma_chan *txchan = as->dma.chan_tx;
> + struct dma_async_tx_descriptor *rxdesc;
> + struct dma_async_tx_descriptor *txdesc;
> + dma_cookie_t cookie;
> + u32 len = *plen;
> +
> + dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
> +
> + /* Check that the channels are available */
> + if (!rxchan || !txchan)
> + return -ENODEV;
> +
> + /* release lock for DMA operations */
> + atmel_spi_unlock(as);
> +
> + /* prepare the RX dma transfer */
> + sg_init_table(&as->dma.sgrx, 1);
> + if (xfer->rx_buf)
> + as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
> + else {
> + as->dma.sgrx.dma_address = as->buffer_dma;
> + if (len > BUFFER_SIZE)
> + len = BUFFER_SIZE;
> + }
You should use brackets before the "else" also.
cf Documentation/CodingStyle line 169 :
This does not apply if only one branch of a conditional statement is a single
statement; in the latter case use braces in both branches:
if (condition) {
do_this();
do_that();
} else {
otherwise();
}
> +
> + /* prepare the TX dma transfer */
> + sg_init_table(&as->dma.sgtx, 1);
> + if (xfer->tx_buf) {
> + as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
> + } else {
> + as->dma.sgtx.dma_address = as->buffer_dma;
> + if (len > BUFFER_SIZE)
> + len = BUFFER_SIZE;
> + memset(as->buffer, 0, len);
> + }
> +
> + sg_dma_len(&as->dma.sgtx) = len;
> + sg_dma_len(&as->dma.sgrx) = len;
> +
> + *plen = len;
> +
> + /* Send both scatterlists */
> + rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
> + &as->dma.sgrx,
> + 1,
> + DMA_FROM_DEVICE,
> + DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
> + NULL);
> + if (!rxdesc)
> + goto err_dma;
> +
> + txdesc = txchan->device->device_prep_slave_sg(txchan,
> + &as->dma.sgtx,
> + 1,
> + DMA_TO_DEVICE,
> + DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
> + NULL);
> + if (!txdesc)
> + goto err_dma;
> +
> + dev_dbg(master->dev.parent,
> + " start dma xfer %p: len %u tx %p/%08x rx %p/%08x\n",
> + xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
> + xfer->rx_buf, xfer->rx_dma);
> +
> + /* Enable relevant interrupts */
> + spi_writel(as, IER, SPI_BIT(OVRES));
> +
> + /* Put the callback on the RX transfer only, that should finish last */
> + rxdesc->callback = dma_callback;
> + rxdesc->callback_param = master;
> +
> + /* Submit and fire RX and TX with TX last so we're ready to read! */
> + cookie = rxdesc->tx_submit(rxdesc);
> + if (dma_submit_error(cookie))
> + goto err_dma;
> + cookie = txdesc->tx_submit(txdesc);
> + if (dma_submit_error(cookie))
> + goto err_dma;
> + rxchan->device->device_issue_pending(rxchan);
> + txchan->device->device_issue_pending(txchan);
> +
> + /* take back lock */
> + atmel_spi_lock(as);
> + return 0;
> +
> +err_dma:
> + spi_writel(as, IDR, SPI_BIT(OVRES));
> + atmel_spi_stop_dma(as);
> + atmel_spi_lock(as);
> + return -ENOMEM;
> +}
> +
> static void atmel_spi_next_xfer_data(struct spi_master *master,
> struct spi_transfer *xfer,
> dma_addr_t *tx_dma,
> @@ -457,10 +697,10 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
> }
>
> /*
> - * Submit next transfer for DMA.
> + * Submit next transfer for PDC.
> * lock is held, spi irq is blocked
> */
> -static void atmel_spi_next_xfer(struct spi_master *master,
> +static void atmel_spi_next_xfer_pdc(struct spi_master *master,
> struct spi_message *msg)
> {
> struct atmel_spi *as = spi_master_get_devdata(master);
> @@ -557,6 +797,49 @@ static void atmel_spi_next_xfer(struct spi_master *master,
> spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
> }
>
> +/*
> + * Choose way to submit next transfer and start it.
> + * lock is held, spi tasklet is blocked
> + */
> +static void atmel_spi_next_xfer_dma(struct spi_master *master,
> + struct spi_message *msg)
> +{
> + struct atmel_spi *as = spi_master_get_devdata(master);
> + struct spi_transfer *xfer;
> + u32 remaining, len;
> +
> + dev_vdbg(&msg->spi->dev, "atmel_spi_next_xfer\n");
> +
> + remaining = as->current_remaining_bytes;
> + if (remaining) {
> + xfer = as->current_transfer;
> + len = remaining;
> + } else {
> + if (!as->current_transfer)
> + xfer = list_entry(msg->transfers.next,
> + struct spi_transfer, transfer_list);
> + else
> + xfer = list_entry(
> + as->current_transfer->transfer_list.next,
> + struct spi_transfer, transfer_list);
> +
> + as->current_transfer = xfer;
> + len = xfer->len;
> + }
> +
> + if (atmel_spi_use_dma(as, xfer)) {
> + u32 total = len;
> + if (!atmel_spi_next_xfer_dma_submit(master, xfer, &len)) {
> + as->current_remaining_bytes = total - len;
> + return;
> + } else
> + dev_err(&msg->spi->dev, "unable to use DMA, fallback to PIO\n");
same here.
> + }
> +
> + /* use PIO if error appened using DMA */
> + atmel_spi_next_xfer_pio(master, xfer);
> +}
> +
> static void atmel_spi_next_message(struct spi_master *master)
> {
> struct atmel_spi *as = spi_master_get_devdata(master);
> @@ -581,7 +864,10 @@ static void atmel_spi_next_message(struct spi_master *master)
> } else
> cs_activate(as, spi);
>
> - atmel_spi_next_xfer(master, msg);
> + if (as->use_pdc)
> + atmel_spi_next_xfer_pdc(master, msg);
> + else
> + atmel_spi_next_xfer_dma(master, msg);
> }
>
> /*
> @@ -634,6 +920,11 @@ static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
> xfer->len, DMA_FROM_DEVICE);
> }
>
> +static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
> +{
> + spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
> +}
> +
> static void
> atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
> struct spi_message *msg, int stay)
> @@ -659,19 +950,175 @@ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
> as->done_status = 0;
>
> /* continue if needed */
> - if (list_empty(&as->queue) || as->stopping)
> - spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
> - else
> + if (list_empty(&as->queue) || as->stopping) {
> + if (as->use_pdc)
> + atmel_spi_disable_pdc_transfer(as);
> + } else
> atmel_spi_next_message(master);
same.
> }
>
> -static irqreturn_t
> -atmel_spi_interrupt(int irq, void *dev_id)
> +/* Called from IRQ
> + * lock is held
> + *
> + * Must update "current_remaining_bytes" to keep track of data
> + * to transfer.
> + */
> +static void
> +atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
> {
> - struct spi_master *master = dev_id;
> + u8 *txp;
> + u8 *rxp;
> + unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
> +
> + if (xfer->rx_buf) {
> + rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
> + *rxp = spi_readl(as, RDR);
> + } else {
> + spi_readl(as, RDR);
> + }
> +
> + as->current_remaining_bytes--;
> +
> + if (as->current_remaining_bytes) {
> + if (xfer->tx_buf) {
> + txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
> + spi_writel(as, TDR, *txp);
> + } else {
> + spi_writel(as, TDR, 0);
> + }
> + }
> +}
> +
> +/* Tasklet
> + * Called from DMA callback + pio transfer and overrun IRQ.
> + */
> +static void atmel_spi_tasklet_func(unsigned long data)
> +{
> + struct spi_master *master = (struct spi_master *)data;
> struct atmel_spi *as = spi_master_get_devdata(master);
> struct spi_message *msg;
> struct spi_transfer *xfer;
> +
> + dev_vdbg(master->dev.parent, "atmel_spi_tasklet_func\n");
> +
> + atmel_spi_lock(as);
> +
> + xfer = as->current_transfer;
> +
> + if (xfer == NULL)
> + /* already been there */
> + goto tasklet_out;
> +
> + msg = list_entry(as->queue.next, struct spi_message, queue);
> +
> + if (as->current_remaining_bytes == 0) {
> + if (as->done_status < 0) {
> + /* error happened (overrun) */
> + if (atmel_spi_use_dma(as, xfer))
> + atmel_spi_stop_dma(as);
> + } else
> + /* only update length if no error */
> + msg->actual_length += xfer->len;
same
> +
> + if (atmel_spi_use_dma(as, xfer))
> + if (!msg->is_dma_mapped)
> + atmel_spi_dma_unmap_xfer(master, xfer);
> +
> + if (xfer->delay_usecs)
> + udelay(xfer->delay_usecs);
> +
> + if (atmel_spi_xfer_is_last(msg, xfer) || as->done_status < 0)
> + /* report completed (or erroneous) message */
> + atmel_spi_msg_done(master, as, msg, xfer->cs_change);
> + else {
same
> + if (xfer->cs_change) {
> + cs_deactivate(as, msg->spi);
> + udelay(1);
> + cs_activate(as, msg->spi);
> + }
> +
> + /*
> + * Not done yet. Submit the next transfer.
> + *
> + * FIXME handle protocol options for xfer
> + */
> + atmel_spi_next_xfer_dma(master, msg);
> + }
> + } else
same
> + /*
> + * Keep going, we still have data to send in
> + * the current transfer.
> + */
> + atmel_spi_next_xfer_dma(master, msg);
> +
> +tasklet_out:
> + atmel_spi_unlock(as);
> +}
> +
> +static int atmel_spi_interrupt_dma(struct atmel_spi *as,
> + struct spi_master *master)
> +{
> + u32 status, pending, imr;
> + struct spi_transfer *xfer;
> + int ret = IRQ_NONE;
> +
> + imr = spi_readl(as, IMR);
> + status = spi_readl(as, SR);
> + pending = status & imr;
> +
> + if (pending & SPI_BIT(OVRES)) {
> + ret = IRQ_HANDLED;
> + spi_writel(as, IDR, SPI_BIT(OVRES));
> + dev_warn(master->dev.parent, "overrun\n");
> +
> + /*
> + * When we get an overrun, we disregard the current
> + * transfer. Data will not be copied back from any
> + * bounce buffer and msg->actual_len will not be
> + * updated with the last xfer.
> + *
> + * We will also not process any remaning transfers in
> + * the message.
> + *
> + * All actions are done in tasklet with done_status indication
> + */
> + as->done_status = -EIO;
> + smp_wmb();
> +
> + /* Clear any overrun happening while cleaning up */
> + spi_readl(as, SR);
> +
> + tasklet_schedule(&as->tasklet);
> +
> + } else if (pending & SPI_BIT(RDRF)) {
> + atmel_spi_lock(as);
> +
> + if (as->current_remaining_bytes) {
> + ret = IRQ_HANDLED;
> + xfer = as->current_transfer;
> + atmel_spi_pump_pio_data(as, xfer);
> + if (!as->current_remaining_bytes) {
> + /* no more data to xfer, kick tasklet */
> + spi_writel(as, IDR, pending);
> + tasklet_schedule(&as->tasklet);
> + }
> + }
> +
> + atmel_spi_unlock(as);
> + } else {
> + WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
> + ret = IRQ_HANDLED;
> + spi_writel(as, IDR, pending);
> + }
> +
> + return ret;
> +}
> +
> +static int atmel_spi_interrupt_pdc(struct atmel_spi *as,
> + struct spi_master *master)
> +{
> + struct spi_message *msg;
> + struct spi_transfer *xfer;
> u32 status, pending, imr;
> int ret = IRQ_NONE;
>
> @@ -767,14 +1214,14 @@ atmel_spi_interrupt(int irq, void *dev_id)
> *
> * FIXME handle protocol options for xfer
> */
> - atmel_spi_next_xfer(master, msg);
> + atmel_spi_next_xfer_pdc(master, msg);
> }
> } else {
> /*
> * Keep going, we still have data to send in
> * the current transfer.
> */
> - atmel_spi_next_xfer(master, msg);
> + atmel_spi_next_xfer_pdc(master, msg);
> }
> }
>
> @@ -783,6 +1230,27 @@ atmel_spi_interrupt(int irq, void *dev_id)
> return ret;
> }
>
> +/* Interrupt
> + *
> + * No need for locking in this Interrupt handler: done_status is the
> + * only information modified. What we need is the update of this field
> + * before tasklet runs. This is ensured by using barrier.
> + */
> +static irqreturn_t
> +atmel_spi_interrupt(int irq, void *dev_id)
> +{
> + struct spi_master *master = dev_id;
> + struct atmel_spi *as = spi_master_get_devdata(master);
> + int ret;
> +
> + if (as->use_pdc)
> + ret = atmel_spi_interrupt_pdc(as, master);
> + else
> + ret = atmel_spi_interrupt_dma(as, master);
> +
> + return ret;
> +}
> +
> static int atmel_spi_setup(struct spi_device *spi)
> {
> struct atmel_spi *as;
> @@ -945,13 +1413,10 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
>
> /*
> * DMA map early, for performance (empties dcache ASAP) and
> - * better fault reporting. This is a DMA-only driver.
> - *
> - * NOTE that if dma_unmap_single() ever starts to do work on
> - * platforms supported by this driver, we would need to clean
> - * up mappings for previously-mapped transfers.
> + * better fault reporting.
> */
> - if (!msg->is_dma_mapped) {
> + if ((!msg->is_dma_mapped) && (atmel_spi_use_dma(as, xfer)
> + || as->use_pdc)) {
> if (atmel_spi_dma_map_xfer(as, xfer) < 0)
> return -ENOMEM;
> }
> @@ -1068,6 +1533,8 @@ static int atmel_spi_probe(struct platform_device *pdev)
>
> spin_lock_init(&as->lock);
> INIT_LIST_HEAD(&as->queue);
> + tasklet_init(&as->tasklet, atmel_spi_tasklet_func,
> + (unsigned long)master);
> as->pdev = pdev;
> as->regs = ioremap(regs->start, resource_size(regs));
> if (!as->regs)
> @@ -1096,7 +1563,15 @@ static int atmel_spi_probe(struct platform_device *pdev)
> else
> spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
>
> - spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
> + as->use_dma = false;
> + as->use_pdc = false;
> +
> + if (as->pdata->has_dma_support) {
> + if (atmel_spi_configure_dma(as) == 0)
> + as->use_dma = true;
> + } else
> + as->use_pdc = true;
same.
Maybe you should add a little dev_info in case both use_dma and
use_pcd are null:
if (!as->use_dma && !as->use_pdc)
dev_info(&pdev->dev, "Atmel SPI Controller: Using PIO only for transferts");
I tested it on sam9g35.
It's working *almost* all right.
I've got a problem with the ioctl SPI_IOC_MESSAGE().
(cf Documentation/spi/spidev_fdx.c)
I'm reading on spidev something like that :
struct spi_ioc_transfer xfer[3];
memset(xfer, 0, sizeof(xfer));
xfer[0].tx_buf = (unsigned long)&tx_header;
xer[0].rx_buf = (unsigned long)&rx_header;
xfer[0].len = 2;
xfer[1].rx_buf = (unsigned long)rx_buf;
xfer[1].len = 124;
xfer[2].tx_buf = (unsigned long)&tx_footer;
xfer[2].rx_buf = (unsigned long)&rx_footer;
xfer[2].len = 2;
nb = ioctl(spi_data->fd, SPI_IOC_MESSAGE(3), xfer);
If I force DMA all the time with
#define DMA_MIN_BYTES 1
I haven't got any problem, all works ok.
If I for PIO all the time with
#define DMA_MIN_BYTES 1000
I'ts woking also without any problem.
BUT
When the DMA_MIN_BYTES are at 16 (so, xfer[0] is transfered by PIO,
xfer[1] by DMA and xfer[2] by PIO), I've got a lot of errors in my
rx_buffer.
ie, I'm not receiving what I should.
Did you experience anything like that ?
Regards,
Richard
^ permalink raw reply
* [PATCH v2] mm: dmapool: use provided gfp flags for all dma_alloc_coherent() calls
From: Andrew Lunn @ 2013-01-23 16:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5100022D.9050106@web.de>
On Wed, Jan 23, 2013 at 04:30:53PM +0100, Soeren Moch wrote:
> On 19.01.2013 19:59, Andrew Lunn wrote:
> >>Please find attached a debug log generated with your patch.
> >>
> >>I used the sata disk and two em28xx dvb sticks, no other usb devices,
> >>no ethernet cable connected, tuners on saa716x-based card not used.
> >>
> >>What I can see in the log: a lot of coherent mappings from sata_mv
> >>and orion_ehci, a few from mv643xx_eth, no other coherent mappings.
> >>All coherent mappings are page aligned, some of them (from orion_ehci)
> >>are not really small (as claimed in __alloc_from_pool).
> >>
> >>I don't believe in a memory leak. When I restart vdr (the application
> >>utilizing the dvb sticks) then there is enough dma memory available
> >>again.
> >
> >Hi Soeren
> >
> >We should be able to rule out a leak. Mount debugfg and then:
> >
> >while [ /bin/true ] ; do cat /debug/dma-api/num_free_entries ; sleep 60 ; done
> >
> >while you are capturing. See if the number goes down.
> >
> > Andrew
>
> Now I built a kernel with debugfs enabled.
> It is not clear to me what I can see from the
> dma-api/num_free_entries output. After reboot (vdr running) I see
> decreasing numbers (3453 3452 3445 3430...), min_free_entries is
> lower (3390). Sometimes the output is constant for several minutes (
> 3396 3396 3396 3396 3396,...)
We are interesting in the long term behavior. Does it gradually go
down? Or is it stable? If it goes down over time, its clearly a leak
somewhere.
Andrew
^ permalink raw reply
* [PATCH 2/2] ARM: tegra: add clocks properties to USB PHY nodes
From: Stephen Warren @ 2013-01-23 16:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <D958900912E20642BCBC71664EFECE3E6E1B13B847@BGMAIL02.nvidia.com>
On 01/22/2013 11:43 PM, Venu Byravarasu wrote:
> Stephen Warren wrote at Wednesday, January 23, 2013 6:03 AM:
>> On 01/22/2013 05:28 PM, Stephen Warren wrote:
>>> The patch to add USB PHY nodes to device tree was written before Tegra
>>> supported the clocks property in device tree. Now that it does, add the
>>> required clocks properties to these nodes.
>>>
>>> This will allow all clk_get_sys() calls in tegra_usb_phy.c to be replaced
>>> by clk_get(phy->dev, clock_name), as part of converting the PHY driver to
>>> a platform driver.
>>
>>> diff --git a/arch/arm/boot/dts/tegra20.dtsi
>> b/arch/arm/boot/dts/tegra20.dtsi
>>
>>> + clocks = <&tegra_car 22>, <&tegra_car 127>;
>>> + clock-names = "utmi", "pll_u";
>> ...
>>> + clocks = <&tegra_car 94>, <&tegra_car 127>;
>>> + clock-names = "ulpi", "pll_u";
>>
>> Hmmm. Thinking about that first clock more, if we name it just "phy" in
>> both the UTMI and ULPI PHY nodes, we could make tegra_phy_init() perform
>> the clk_get() for all PHY types, and use the same clock name everywhere,
>> and hence remove the type-specific clk_get()s from tegra_phy_init() and
>> utmip_pad_open().
>>
>> Venu, will this work for other chips such as Tegra30/Tegra114 and so on
>> into the future, or do chips after Tegra20 introduce any new clocks, and
>> hence break this scheme?
>
> Should be fine, as same clocks are used across all chips.
> Acked-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Thanks. I've applied both patches to Tegra's for-3.9/soc branch, with
patch 2/2 modified to name the first clock "phy" rather than "utmi" or
"ulpi".
^ permalink raw reply
* [v3 2/2] ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9
From: Stephen Warren @ 2013-01-23 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130123.112745.1104072242042163713.hdoyu@nvidia.com>
On 01/23/2013 02:27 AM, Hiroshi Doyu wrote:
> Hiroshi Doyu <hdoyu@nvidia.com> wrote @ Wed, 23 Jan 2013 08:04:57 +0200 (EET):
>
>> Stephen Warren <swarren@wwwdotorg.org> wrote @ Tue, 22 Jan 2013 17:57:39 +0100:
>>
>>> Hiroshi, is this series the only dependency you need for your
>>> Tegra114
>>
>> Basically yes.
>>
>>> series? So, I could merge your Tegra114 series once this series is applied?
>>
>> But now "CCF" seems to be in. Then, the HACK(*1) needs to be replaced
>> with "Tegra114 CCF". But "Tegra114 CCF" doesn't seem ready yet. I'll check
>> if this Tegra114 series would work without "Tegra114 CCF".
>>
>> *1: http://patchwork.ozlabs.org/patch/212010/
>
> Stephen,
>
> Verified "Tegra114 series" worked with "for-3.9/soc" branch(inc CCF)
> with a little tweak.
Good news.
> I can post Tegra114 series again. If you want them rebased onto
> another branch, let me know.
Yes please. I will apply them to for-3.9/soc. Please assume that
for-3.9/soc will already contain "ARM: Define CPU part numbers and
implementors", and your two SCU-related patches. Include your "ARM:
tegra: Use DT /cpu node to detect number of CPU core" as the first patch
in the series. I assume that is all of the dependencies; if I've
forgotten anything, please point it out. Thanks.
^ permalink raw reply
* [PATCH v3 0/8] ARM: shmobile: pinctrl and DT extensions
From: Guennadi Liakhovetski @ 2013-01-23 16:37 UTC (permalink / raw)
To: linux-arm-kernel
This is v3 of the patch series [1], addressing minor issues in 3 out of 8
patches.
[1] http://thread.gmane.org/gmane.linux.ports.sh.devel/18729
Guennadi Liakhovetski (8):
pinctrl: add SDHI and MMCIF pin groups to r8a7740
pinctrl: add SDHI and MMCIF pin groups to sh7372
ARM: shmobile: simplify armadillo800eva and kzm9g Kconfig
dependencies
ARM: shmobile: add MMCIF and SDHI DT clock aliases to sh73a0 and
r8a7740
ARM: shmobile: add a GPIO controller DT node for sh7372
ARM: shmobile: use GPIO SD-card detection on armadillo800eva
ARM: shmobile: completely switch MMC interfaces on mackerel-reference
to DT
ARM: shmobile: completely switch MMC interfaces on
armadillo800eva-reference to DT
.../boot/dts/r8a7740-armadillo800eva-reference.dts | 107 +++++++++
arch/arm/boot/dts/sh7372-mackerel-reference.dts | 42 +++-
arch/arm/boot/dts/sh7372.dtsi | 8 +
arch/arm/mach-shmobile/Kconfig | 12 +-
.../board-armadillo800eva-reference.c | 5 +-
arch/arm/mach-shmobile/board-armadillo800eva.c | 10 +-
arch/arm/mach-shmobile/board-mackerel-reference.c | 46 ----
arch/arm/mach-shmobile/clock-r8a7740.c | 4 +
arch/arm/mach-shmobile/clock-sh73a0.c | 3 +
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 248 ++++++++++++++++++++
drivers/pinctrl/sh-pfc/pfc-sh7372.c | 205 ++++++++++++++++
11 files changed, 626 insertions(+), 64 deletions(-)
--
1.7.2.5
Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
^ permalink raw reply
* [PATCH v3 1/8] pinctrl: add SDHI and MMCIF pin groups to r8a7740
From: Guennadi Liakhovetski @ 2013-01-23 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358959071-2873-1-git-send-email-g.liakhovetski@gmx.de>
Add pin groups for the first two SDHI interfaces and two alternative pin
groups for the MMCIF interface on the r8a7740 SoC.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
v3: swapped two pin numbers for MMCIF, as spotted by Laurent, thanks.
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 248 ++++++++++++++++++++++++++++++++++
1 files changed, 248 insertions(+), 0 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index d0b7165..4c92af8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1870,6 +1870,188 @@ static const unsigned int lcd1_sys_mux[] = {
LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
};
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ 77,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SDHI0_D0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ 77, 78, 79, 80,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CMD, CLK */
+ 76, 82,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SDHI0_CMD_MARK, SDHI0_CLK_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ 81,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SDHI0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ 83,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SDHI0_WP_MARK,
+};
+
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ 68,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SDHI1_D0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ 68, 69, 70, 71,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CMD, CLK */
+ 67, 66,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SDHI1_CMD_MARK, SDHI1_CLK_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+ /* CD */
+ 72,
+};
+static const unsigned int sdhi1_cd_mux[] = {
+ SDHI1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+ /* WP */
+ 73,
+};
+static const unsigned int sdhi1_wp_mux[] = {
+ SDHI1_WP_MARK,
+};
+
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ 205,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SDHI2_D0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ 205, 206, 207, 208,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CMD, CLK */
+ 204, 203,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SDHI2_CMD_MARK, SDHI2_CLK_MARK,
+};
+static const unsigned int sdhi2_cd_0_pins[] = {
+ /* CD */
+ 202,
+};
+static const unsigned int sdhi2_cd_0_mux[] = {
+ SDHI2_CD_PORT202_MARK,
+};
+static const unsigned int sdhi2_wp_0_pins[] = {
+ /* WP */
+ 177,
+};
+static const unsigned int sdhi2_wp_0_mux[] = {
+ SDHI2_WP_PORT177_MARK,
+};
+static const unsigned int sdhi2_cd_1_pins[] = {
+ /* CD */
+ 24,
+};
+static const unsigned int sdhi2_cd_1_mux[] = {
+ SDHI2_CD_PORT24_MARK,
+};
+static const unsigned int sdhi2_wp_1_pins[] = {
+ /* WP */
+ 25,
+};
+static const unsigned int sdhi2_wp_1_mux[] = {
+ SDHI2_WP_PORT25_MARK,
+};
+
+static const unsigned int mmc0_data1_0_pins[] = {
+ /* D[0] */
+ 68,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+ MMC0_D0_PORT68_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+ /* D[0:3] */
+ 68, 69, 70, 71,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+ MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+ /* D[0:7] */
+ 68, 69, 70, 71, 72, 73, 74, 75,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+ MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
+ MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+ /* CMD, CLK */
+ 67, 66,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+ MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
+};
+
+static const unsigned int mmc0_data1_1_pins[] = {
+ /* D[0] */
+ 149,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+ MMC1_D0_PORT149_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+ /* D[0:3] */
+ 149, 148, 147, 146,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+ MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+ /* D[0:7] */
+ 149, 148, 147, 146, 145, 144, 143, 142,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+ MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
+ MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+ /* CMD, CLK */
+ 104, 103,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+ MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
+};
+
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(lcd0_data8),
SH_PFC_PIN_GROUP(lcd0_data9),
@@ -1893,6 +2075,31 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(lcd1_lclk),
SH_PFC_PIN_GROUP(lcd1_sync),
SH_PFC_PIN_GROUP(lcd1_sys),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd_0),
+ SH_PFC_PIN_GROUP(sdhi2_wp_0),
+ SH_PFC_PIN_GROUP(sdhi2_cd_1),
+ SH_PFC_PIN_GROUP(sdhi2_wp_1),
+ SH_PFC_PIN_GROUP(mmc0_data1_0),
+ SH_PFC_PIN_GROUP(mmc0_data4_0),
+ SH_PFC_PIN_GROUP(mmc0_data8_0),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+ SH_PFC_PIN_GROUP(mmc0_data1_1),
+ SH_PFC_PIN_GROUP(mmc0_data4_1),
+ SH_PFC_PIN_GROUP(mmc0_data8_1),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_1),
};
static const char * const lcd0_groups[] = {
@@ -1923,9 +2130,50 @@ static const char * const lcd1_groups[] = {
"lcd1_sys",
};
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+ "sdhi1_cd",
+ "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+ "sdhi2_cd_0",
+ "sdhi2_wp_0",
+ "sdhi2_cd_1",
+ "sdhi2_wp_1",
+};
+
+static const char * const mmc0_groups[] = {
+ "mmc0_data1_0",
+ "mmc0_data4_0",
+ "mmc0_data8_0",
+ "mmc0_ctrl_0",
+ "mmc0_data1_1",
+ "mmc0_data4_1",
+ "mmc0_data8_1",
+ "mmc0_ctrl_1",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(lcd0),
SH_PFC_FUNCTION(lcd1),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(mmc0),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
--
1.7.2.5
^ permalink raw reply related
* [PATCH v3 2/8] pinctrl: add SDHI and MMCIF pin groups to sh7372
From: Guennadi Liakhovetski @ 2013-01-23 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358959071-2873-1-git-send-email-g.liakhovetski@gmx.de>
Add pin groups for all three SDHI interfaces and two alternative pin
groups for the MMCIF interface on the sh7372 SoC.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
v3: fixed indentation.
drivers/pinctrl/sh-pfc/pfc-sh7372.c | 205 +++++++++++++++++++++++++++++++++++
1 files changed, 205 insertions(+), 0 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 847e0cd..b4b54a0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -933,6 +933,206 @@ static struct sh_pfc_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
};
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ 173,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SDHID0_0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ 173, 174, 175, 176,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CMD, CLK */
+ 177, 171,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SDHICMD0_MARK, SDHICLK0_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ 172,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SDHICD0_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ 178,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SDHIWP0_MARK,
+};
+
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ 180,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SDHID1_0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ 180, 181, 182, 183,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CMD, CLK */
+ 184, 179,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SDHICMD1_MARK, SDHICLK1_MARK,
+};
+
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ 186,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SDHID2_0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ 186, 187, 188, 189,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CMD, CLK */
+ 190, 185,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SDHICMD2_MARK, SDHICLK2_MARK,
+};
+
+static const unsigned int mmc0_data1_0_pins[] = {
+ /* D[0] */
+ 84,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+ MMCD0_0_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+ /* D[0:3] */
+ 84, 85, 86, 87,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+ MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+ /* D[0:7] */
+ 84, 85, 86, 87, 88, 89, 90, 91,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+ MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+ MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+ /* CMD, CLK */
+ 92, 99,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+ MMCCMD0_MARK, MMCCLK0_MARK,
+};
+
+static const unsigned int mmc0_data1_1_pins[] = {
+ /* D[0] */
+ 54,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+ MMCD1_0_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+ /* D[0:3] */
+ 54, 55, 56, 57,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+ MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+ /* D[0:7] */
+ 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+ MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+ MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+ /* CMD, CLK */
+ 67, 66,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+ MMCCMD1_MARK, MMCCLK1_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(mmc0_data1_0),
+ SH_PFC_PIN_GROUP(mmc0_data4_0),
+ SH_PFC_PIN_GROUP(mmc0_data8_0),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+ SH_PFC_PIN_GROUP(mmc0_data1_1),
+ SH_PFC_PIN_GROUP(mmc0_data4_1),
+ SH_PFC_PIN_GROUP(mmc0_data8_1),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+};
+
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+};
+
+static const char * const mmc0_groups[] = {
+ "mmc0_data1_0",
+ "mmc0_data4_0",
+ "mmc0_data8_0",
+ "mmc0_ctrl_0",
+ "mmc0_data1_1",
+ "mmc0_data4_1",
+ "mmc0_data8_1",
+ "mmc0_ctrl_1",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(mmc0),
+};
+
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static struct pinmux_func pinmux_func_gpios[] = {
@@ -1644,6 +1844,11 @@ struct sh_pfc_soc_info sh7372_pinmux_info = {
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
--
1.7.2.5
^ permalink raw reply related
* [PATCH v3 3/8] ARM: shmobile: simplify armadillo800eva and kzm9g Kconfig dependencies
From: Guennadi Liakhovetski @ 2013-01-23 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358959071-2873-1-git-send-email-g.liakhovetski@gmx.de>
Reference kernel configurations for armadillo800eva and kzm9g boards do not
have to depend on their respective "legacy" configurations, doing device
instantiation in .c, they can be configured and built independently.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
arch/arm/mach-shmobile/Kconfig | 12 ++++++++++--
1 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 5f61e8f..927eecc 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -106,7 +106,11 @@ config MACH_ARMADILLO800EVA
config MACH_ARMADILLO800EVA_REFERENCE
bool "Armadillo-800 EVA board - Reference Device Tree Implementation"
- depends on MACH_ARMADILLO800EVA
+ depends on ARCH_R8A7740
+ select ARCH_REQUIRE_GPIOLIB
+ select REGULATOR_FIXED_VOLTAGE if REGULATOR
+ select SND_SOC_WM8978 if SND_SIMPLE_CARD
+ select USE_OF
---help---
Use reference implementation of Aramdillo800 EVA board support
which makes a greater use of device tree at the expense
@@ -136,7 +140,11 @@ config MACH_KZM9G
config MACH_KZM9G_REFERENCE
bool "KZM-A9-GT board - Reference Device Tree Implementation"
- depends on MACH_KZM9G
+ depends on ARCH_SH73A0
+ select ARCH_REQUIRE_GPIOLIB
+ select REGULATOR_FIXED_VOLTAGE if REGULATOR
+ select SND_SOC_AK4642 if SND_SIMPLE_CARD
+ select USE_OF
---help---
Use reference implementation of KZM-A9-GT board support
which makes as greater use of device tree at the expense
--
1.7.2.5
^ permalink raw reply related
* [PATCH v3 4/8] ARM: shmobile: add MMCIF and SDHI DT clock aliases to sh73a0 and r8a7740
From: Guennadi Liakhovetski @ 2013-01-23 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358959071-2873-1-git-send-email-g.liakhovetski@gmx.de>
Add clock lookup entries for SDHI and MMCIF device names, for the FDT case.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
arch/arm/mach-shmobile/clock-r8a7740.c | 4 ++++
arch/arm/mach-shmobile/clock-sh73a0.c | 3 +++
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 8765a76..83209bf 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -611,12 +611,16 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
+ CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]),
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
+ CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]),
CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]),
+ CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]),
CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]),
CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]),
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
+ CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]),
/* ICK */
CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]),
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index afa5423..5fa106b 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -581,10 +581,13 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+ CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+ CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
+ CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
--
1.7.2.5
^ permalink raw reply related
* [PATCH v3 5/8] ARM: shmobile: add a GPIO controller DT node for sh7372
From: Guennadi Liakhovetski @ 2013-01-23 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358959071-2873-1-git-send-email-g.liakhovetski@gmx.de>
Add a missing GPIO controller node to sh7372.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
v3: fix second memory area size.
arch/arm/boot/dts/sh7372.dtsi | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 582fdec..3598e57 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -19,6 +19,14 @@
};
};
+ gpio: pfc at e6050000 {
+ compatible = "renesas,pfc-sh7372";
+ reg = <0xe6050000 0x8000>,
+ <0xe605800c 0x1c>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
--
1.7.2.5
^ permalink raw reply related
* [PATCH v3 6/8] ARM: shmobile: use GPIO SD-card detection on armadillo800eva
From: Guennadi Liakhovetski @ 2013-01-23 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358959071-2873-1-git-send-email-g.liakhovetski@gmx.de>
Switch SDHI0 and SDHI1 SD-card interfaces on armadillo800eva to using GPIO
card detection, which provides maximum power saving and automatically
selects IRQ or polling mode, depending on the CD GPIO capability.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
arch/arm/mach-shmobile/board-armadillo800eva.c | 10 ++++++----
1 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index e657a7a..1cf1157 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -580,10 +580,10 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] =
static struct sh_mobile_sdhi_info sdhi0_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
- .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |\
- MMC_CAP_NEEDS_POLL,
+ .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
.tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
- .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
+ .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
+ .cd_gpio = GPIO_PORT167,
};
static struct resource sdhi0_resources[] = {
@@ -624,7 +624,9 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
.dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
.tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
- .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
+ .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
+ /* Port72 cannot generate IRQs, will be used in polling mode. */
+ .cd_gpio = GPIO_PORT72,
};
static struct resource sdhi1_resources[] = {
--
1.7.2.5
^ permalink raw reply related
* [PATCH v3 7/8] ARM: shmobile: completely switch MMC interfaces on mackerel-reference to DT
From: Guennadi Liakhovetski @ 2013-01-23 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358959071-2873-1-git-send-email-g.liakhovetski@gmx.de>
Switch MMCIF, SDHI0 and SDHI2 to complete DT initialisation: use DT
bindings to configure interface pins, card-detect GPIOs, various
interface configuration parameters. Notice, since MMCIF and SDHI1 share
the same card slot, both devices cannot be successfully probed
simultaneously: they both would try to get the card-detection GPIO and only
one would succeed. Ideally it should be possible to let the user decide
which device to enable by, possibly, patching the DT at run-time. As long as
this is unsupported, we choose to enable MMCIF and remove SDHI1 from DT
completely.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
arch/arm/boot/dts/sh7372-mackerel-reference.dts | 42 +++++++++++++++----
arch/arm/mach-shmobile/board-mackerel-reference.c | 46 ---------------------
2 files changed, 33 insertions(+), 55 deletions(-)
diff --git a/arch/arm/boot/dts/sh7372-mackerel-reference.dts b/arch/arm/boot/dts/sh7372-mackerel-reference.dts
index 2fd1eff..aa72309 100644
--- a/arch/arm/boot/dts/sh7372-mackerel-reference.dts
+++ b/arch/arm/boot/dts/sh7372-mackerel-reference.dts
@@ -75,6 +75,11 @@
interrupt-parent = <&intca>;
interrupts = <0x1ac0 0x1ae0>;
vmmc-supply = <®_1p8v>;
+ bus-width = <8>;
+ cd-gpios = <&gpio 41 1>;
+ broken-cd;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
};
sdhi0: sdhi at 0xe6850000 {
@@ -83,22 +88,26 @@
interrupt-parent = <&intca>;
interrupts = <0x0e00 0x0e20 0x0e40>;
vmmc-supply = <®_3p3v>;
- };
-
- sdhi1: sdhi at 0xe6860000 {
- compatible = "renesas,shmobile-sdhi";
- reg = <0xe6860000 0x100>;
- interrupt-parent = <&intca>;
- interrupts = <0x0e80 0x0ea0 0x0ec0>;
- vmmc-supply = <®_1p8v>;
+ bus-width = <4>;
+ cd-gpios = <&gpio 172 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhi0_pins>;
+ toshiba,mmc-cap-sdio-irq;
};
sdhi2: sdhi at 0xe6870000 {
compatible = "renesas,shmobile-sdhi";
reg = <0xe6870000 0x100>;
interrupt-parent = <&intca>;
- interrupts = <0x1200 0x1220 0x1240>;
+ interrupts = <0x1220 0x1240>;
vmmc-supply = <®_3p3v>;
+ bus-width = <4>;
+ cd-gpios = <&gpio 162 1>;
+ broken-cd;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhi2_pins>;
+ toshiba,mmc-wrprotect-disable;
+ toshiba,mmc-cap-sdio-irq;
};
flash at 2000000 {
@@ -129,3 +138,18 @@
};
};
};
+
+&gpio {
+ sdhi0_pins: pfc_sdhi0_pins {
+ renesas,pins = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
+ renesas,function = "sdhi0";
+ };
+ sdhi2_pins: pfc_sdhi2_pins {
+ renesas,pins = "sdhi2_data4", "sdhi2_ctrl";
+ renesas,function = "sdhi2";
+ };
+ mmc0_pins: pfc_mmc0_pins {
+ renesas,pins = "mmc0_data8_0", "mmc0_ctrl_0";
+ renesas,function = "mmc0";
+ };
+};
diff --git a/arch/arm/mach-shmobile/board-mackerel-reference.c b/arch/arm/mach-shmobile/board-mackerel-reference.c
index 1d83653..323a812 100644
--- a/arch/arm/mach-shmobile/board-mackerel-reference.c
+++ b/arch/arm/mach-shmobile/board-mackerel-reference.c
@@ -42,8 +42,6 @@ static void __init mackerel_init(void)
/* External clock source */
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
- sh7372_pinmux_init();
-
/* enable SCIFA0 */
gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
@@ -59,50 +57,6 @@ static void __init mackerel_init(void)
/* enable Accelerometer */
gpio_request(GPIO_FN_IRQ21, NULL);
irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
-
- /* enable SDHI0 */
- gpio_request(GPIO_FN_SDHIWP0, NULL);
- gpio_request(GPIO_FN_SDHICMD0, NULL);
- gpio_request(GPIO_FN_SDHICLK0, NULL);
- gpio_request(GPIO_FN_SDHID0_3, NULL);
- gpio_request(GPIO_FN_SDHID0_2, NULL);
- gpio_request(GPIO_FN_SDHID0_1, NULL);
- gpio_request(GPIO_FN_SDHID0_0, NULL);
-
- /* SDHI0 PORT172 card-detect IRQ26 */
- gpio_request(GPIO_FN_IRQ26_172, NULL);
-
- /* enable SDHI1 */
- gpio_request(GPIO_FN_SDHICMD1, NULL);
- gpio_request(GPIO_FN_SDHICLK1, NULL);
- gpio_request(GPIO_FN_SDHID1_3, NULL);
- gpio_request(GPIO_FN_SDHID1_2, NULL);
- gpio_request(GPIO_FN_SDHID1_1, NULL);
- gpio_request(GPIO_FN_SDHID1_0, NULL);
-
- /* enable SDHI2 */
- gpio_request(GPIO_FN_SDHICMD2, NULL);
- gpio_request(GPIO_FN_SDHICLK2, NULL);
- gpio_request(GPIO_FN_SDHID2_3, NULL);
- gpio_request(GPIO_FN_SDHID2_2, NULL);
- gpio_request(GPIO_FN_SDHID2_1, NULL);
- gpio_request(GPIO_FN_SDHID2_0, NULL);
-
- /* card detect pin for microSD slot (CN23) */
- gpio_request(GPIO_PORT162, NULL);
- gpio_direction_input(GPIO_PORT162);
-
- /* MMCIF */
- gpio_request(GPIO_FN_MMCD0_0, NULL);
- gpio_request(GPIO_FN_MMCD0_1, NULL);
- gpio_request(GPIO_FN_MMCD0_2, NULL);
- gpio_request(GPIO_FN_MMCD0_3, NULL);
- gpio_request(GPIO_FN_MMCD0_4, NULL);
- gpio_request(GPIO_FN_MMCD0_5, NULL);
- gpio_request(GPIO_FN_MMCD0_6, NULL);
- gpio_request(GPIO_FN_MMCD0_7, NULL);
- gpio_request(GPIO_FN_MMCCMD0, NULL);
- gpio_request(GPIO_FN_MMCCLK0, NULL);
}
static const char *mackerel_compat_dt[] __initdata = {
--
1.7.2.5
^ permalink raw reply related
* [PATCH v3 8/8] ARM: shmobile: completely switch MMC interfaces on armadillo800eva-reference to DT
From: Guennadi Liakhovetski @ 2013-01-23 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358959071-2873-1-git-send-email-g.liakhovetski@gmx.de>
Switch MMCIF, SDHI0 and SDHI1 to complete DT initialisation: use DT
bindings to configure regulators, interface pins, card-detect GPIOs,
various interface configuration parameters.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
v3: add missing regulator and SDHI properties
.../boot/dts/r8a7740-armadillo800eva-reference.dts | 107 ++++++++++++++++++++
.../board-armadillo800eva-reference.c | 5 +-
2 files changed, 109 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index 319af9b..11cb0f9 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -30,4 +30,111 @@
sh-eth,register-type = "gigabit";
sh-eth,phy-id = <0>;
};
+
+ reg_3p3v: regulator at 0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mmcif0: mmcif at 0xe6bd0000 {
+ compatible = "renesas,sh-mmcif", "renesas,sh7372-mmcif";
+ reg = <0xe6bd0000 0x100>;
+ interrupt-parent = <&intca>;
+ interrupts = <0x1ac0 0x1ae0>;
+ vmmc-supply = <®_3p3v>;
+ bus-width = <8>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ };
+
+ vcc_sdhi0: regulator at 1 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vcc-sdhi0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio 75 0>;
+ enable-active-high;
+ };
+
+ vcc_sdhi1: regulator at 2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vcc-sdhi1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio 16 0>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: gpio-regulator at 0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "vccq-sdhi0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sdhi0>;
+
+ enable-gpio = <&gpio 74 0>;
+ gpios = <&gpio 17 0>;
+ states = <3300000 0
+ 1800000 1>;
+
+ enable-active-high;
+ };
+
+ sdhi0: sdhi at 0xe6850000 {
+ compatible = "renesas,shmobile-sdhi";
+ reg = <0xe6850000 0x100>;
+ interrupt-parent = <&intca>;
+ interrupts = <0xe20 0xe40>;
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ bus-width = <4>;
+ cd-gpios = <&gpio 167 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhi0_pins>;
+ cap-sd-highspeed;
+ cap-power-off-card;
+ toshiba,mmc-has-idle-wait;
+ toshiba,mmc-cap-sdio-irq;
+ };
+
+ sdhi1: sdhi at 0xe6860000 {
+ compatible = "renesas,shmobile-sdhi";
+ reg = <0xe6860000 0x100>;
+ interrupt-parent = <&intca>;
+ interrupts = <0xea0 0xec0>;
+ vmmc-supply = <&vcc_sdhi1>;
+ bus-width = <4>;
+ cd-gpios = <&gpio 72 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhi1_pins>;
+ cap-sd-highspeed;
+ cap-power-off-card;
+ toshiba,mmc-has-idle-wait;
+ toshiba,mmc-cap-sdio-irq;
+ };
+};
+
+&gpio {
+ sdhi0_pins: pfc_sdhi0_pins {
+ renesas,pins = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
+ renesas,function = "sdhi0";
+ };
+ sdhi1_pins: pfc_sdhi1_pins {
+ renesas,pins = "sdhi1_data4", "sdhi1_ctrl", "sdhi1_wp";
+ renesas,function = "sdhi1";
+ };
+ mmc0_pins: pfc_mmc0_pins {
+ renesas,pins = "mmc0_data8_1", "mmc0_ctrl_1";
+ renesas,function = "mmc0";
+ };
};
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
index c206612..f929931 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -107,9 +107,10 @@
*/
static void __init eva_init(void)
{
- r8a7740_pinmux_init();
r8a7740_meram_workaround();
+ r8a7740_add_standard_devices_dt();
+
/* SCIFA1 */
gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
@@ -142,8 +143,6 @@ static void __init eva_init(void)
/* Early BRESP enable, Shared attribute override enable, 32K*8way */
l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
#endif
-
- r8a7740_add_standard_devices_dt();
}
#define RESCNT2 IOMEM(0xe6188020)
--
1.7.2.5
^ permalink raw reply related
* Kernel API for SGI usage
From: loody @ 2013-01-23 16:39 UTC (permalink / raw)
To: linux-arm-kernel
hi all:
The other cores on my Soc need SGI to be waken up from reset state.
Could any one header and functions I need to include and used for?
--
Regards,
^ permalink raw reply
* [PATCH] ARM: dts: Fix MSHC property and add RTC node
From: Dongjin Kim @ 2013-01-23 16:40 UTC (permalink / raw)
To: linux-arm-kernel
This fixes the property of dw-mshc-sdr-timing and dw-mshc-ddr-timing as per
its current binding, it only has two cells.
And also RTC node is added new.
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
---
arch/arm/boot/dts/exynos4412-odroidx.dts | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index f41a84e..1c1d5ec 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -49,8 +49,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <2 3 3>;
- samsung,dw-mshc-ddr-timing = <1 2 3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
slot at 0 {
reg = <0>;
@@ -90,4 +90,8 @@
serial at 13830000 {
status = "okay";
};
+
+ rtc at 10070000 {
+ status = "okay";
+ };
};
--
1.7.10.4
^ permalink raw reply related
* Kernel API for SGI usage
From: Russell King - ARM Linux @ 2013-01-23 16:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANudz+tDzfU1xJgsjeuQBL7r5cwosvSEH6tct5aO8c+LvAm4pA@mail.gmail.com>
On Thu, Jan 24, 2013 at 12:39:54AM +0800, loody wrote:
> hi all:
> The other cores on my Soc need SGI to be waken up from reset state.
> Could any one header and functions I need to include and used for?
That's almost what every platform does. Plenty of examples in the
platform SMP code for you to look at.
^ permalink raw reply
* [PATCH v2 1/3] ARM: DT: tegra: move serial clock-frequency attr into the SoC dtsi
From: Stephen Warren @ 2013-01-23 16:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358891169-5939-1-git-send-email-dev@lynxeye.de>
On 01/22/2013 02:46 PM, Lucas Stach wrote:
> No Tegra Platform is running PLL_P at another rate than 216MHz, nor is
> any using an other PLL as UART source clock. Move attribute into SoC
> level dtsi file to slim down board DT files.
I've applied the series to Tegra's for-3.9/dt branch.
^ permalink raw reply
* Kernel API for SGI usage
From: loody @ 2013-01-23 16:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130123164620.GR23505@n2100.arm.linux.org.uk>
hi Russell:
2013/1/24 Russell King - ARM Linux <linux@arm.linux.org.uk>:
> On Thu, Jan 24, 2013 at 12:39:54AM +0800, loody wrote:
>> hi all:
>> The other cores on my Soc need SGI to be waken up from reset state.
>> Could any one header and functions I need to include and used for?
>
> That's almost what every platform does. Plenty of examples in the
> platform SMP code for you to look at.
Nice to meet you
Would you please show me a hint or function name for reference?
Appreciate your help, @_@
^ permalink raw reply
* [PATCH] ARM: shmobile: fix armadillo800eva clock initialisation in reference DT set up
From: Guennadi Liakhovetski @ 2013-01-23 16:53 UTC (permalink / raw)
To: linux-arm-kernel
Clock configuration on armadillo800eva in reference DT set up must be the
same, as in the board-code case: the clock tree and oscillator frequencies
have to be fixed.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
This goes on top of my DT/mmc/pinctrl patch-series from today, which in
turn is based on Simon's (no longer existing) pfc4 branch.
.../board-armadillo800eva-reference.c | 56 +++++++++++++++++++-
arch/arm/mach-shmobile/setup-r8a7740.c | 13 +++--
2 files changed, 64 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
index f929931..92d7106 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -25,11 +25,13 @@
*/
#include <linux/kernel.h>
+#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <mach/common.h>
#include <mach/r8a7740.h>
+#include <asm/mach/time.h>
#include <asm/mach/arch.h>
#include <asm/hardware/cache-l2x0.h>
@@ -102,6 +104,41 @@
* # amixer set "Headphone" 50
*/
+static void __init eva_clock_init(void)
+{
+ struct clk *system = clk_get(NULL, "system_clk");
+ struct clk *xtal1 = clk_get(NULL, "extal1");
+ struct clk *usb24s = clk_get(NULL, "usb24s");
+ struct clk *fsibck = clk_get(NULL, "fsibck");
+
+ if (IS_ERR(system) ||
+ IS_ERR(xtal1) ||
+ IS_ERR(usb24s) ||
+ IS_ERR(fsibck)) {
+ pr_err("armadillo800eva board clock init failed\n");
+ goto clock_error;
+ }
+
+ /* armadillo 800 eva extal1 is 24MHz */
+ clk_set_rate(xtal1, 24000000);
+
+ /* usb24s use extal1 (= system) clock (= 24MHz) */
+ clk_set_parent(usb24s, system);
+
+ /* FSIBCK is 12.288MHz, and it is parent of FSI-B */
+ clk_set_rate(fsibck, 12288000);
+
+clock_error:
+ if (!IS_ERR(system))
+ clk_put(system);
+ if (!IS_ERR(xtal1))
+ clk_put(xtal1);
+ if (!IS_ERR(usb24s))
+ clk_put(usb24s);
+ if (!IS_ERR(fsibck))
+ clk_put(fsibck);
+}
+
/*
* board init
*/
@@ -145,6 +182,23 @@ static void __init eva_init(void)
#endif
}
+static void __init eva_earlytimer_init(void)
+{
+ r8a7740_clock_init(MD_CK0 | MD_CK2);
+ shmobile_earlytimer_init();
+
+ /* the rate of extal1 clock must be set before late_time_init */
+ eva_clock_init();
+}
+
+static void __init eva_add_early_devices(void)
+{
+ r8a7740_add_early_devices_dt();
+
+ /* override timer setup with board-specific code */
+ shmobile_timer.init = eva_earlytimer_init;
+}
+
#define RESCNT2 IOMEM(0xe6188020)
static void eva_restart(char mode, const char *cmd)
{
@@ -159,7 +213,7 @@ static const char *eva_boards_compat_dt[] __initdata = {
DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva-reference")
.map_io = r8a7740_map_io,
- .init_early = r8a7740_add_early_devices_dt,
+ .init_early = eva_add_early_devices,
.init_irq = r8a7740_init_irq_of,
.nr_irqs = NR_IRQS_LEGACY,
.handle_irq = shmobile_handle_irq_intc,
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 9fe7ca8..cb5aa31 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -861,9 +861,6 @@ static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
void __init r8a7740_add_standard_devices_dt(void)
{
- /* clocks are setup late during boot in the case of DT */
- r8a7740_clock_init(0);
-
platform_add_devices(r8a7740_early_devices,
ARRAY_SIZE(r8a7740_early_devices));
@@ -871,6 +868,14 @@ void __init r8a7740_add_standard_devices_dt(void)
r8a7740_auxdata_lookup, NULL);
}
+static void __init add_standard_devices(void)
+{
+ /* clocks are setup late during boot in the case of DT */
+ r8a7740_clock_init(0);
+
+ r8a7740_add_standard_devices_dt();
+}
+
static const char *r8a7740_boards_compat_dt[] __initdata = {
"renesas,r8a7740",
NULL,
@@ -881,7 +886,7 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
.init_early = r8a7740_add_early_devices_dt,
.init_irq = r8a7740_init_irq_of,
.handle_irq = shmobile_handle_irq_intc,
- .init_machine = r8a7740_add_standard_devices_dt,
+ .init_machine = add_standard_devices,
.timer = &shmobile_timer,
.dt_compat = r8a7740_boards_compat_dt,
MACHINE_END
--
1.7.2.5
^ permalink raw reply related
* [PATCH] ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi
From: Stephen Warren @ 2013-01-23 16:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Stephen Warren <swarren@nvidia.com>
No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/boot/dts/tegra30-beaver.dts | 1 -
arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 --
arch/arm/boot/dts/tegra30.dtsi | 5 +++++
3 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 0f296a4..8ff2ff2 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -90,7 +90,6 @@
serial at 70006000 {
status = "okay";
- clock-frequency = <408000000>;
};
i2c at 7000c000 {
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index ff6b68f..1749927 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -120,13 +120,11 @@
serial at 70006000 {
status = "okay";
- clock-frequency = <408000000>;
};
serial at 70006200 {
compatible = "nvidia,tegra30-hsuart";
status = "okay";
- clock-frequency = <408000000>;
};
i2c at 7000c000 {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index ff4a0ca..313fa71 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -234,6 +234,7 @@
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
+ clock-frequency = <408000000>;
nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>;
status = "disabled";
@@ -243,6 +244,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
+ clock-frequency = <408000000>;
interrupts = <0 37 0x04>;
nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 160>;
@@ -253,6 +255,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
+ clock-frequency = <408000000>;
interrupts = <0 46 0x04>;
nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>;
@@ -263,6 +266,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
+ clock-frequency = <408000000>;
interrupts = <0 90 0x04>;
nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>;
@@ -273,6 +277,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006400 0x100>;
reg-shift = <2>;
+ clock-frequency = <408000000>;
interrupts = <0 91 0x04>;
nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>;
--
1.7.10.4
^ permalink raw reply related
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