* Fwd: [PATCH v3 6/7] DT: Convert all kirkwood boards with mv643xx that use DT
From: Jason Cooper @ 2013-01-24 18:43 UTC (permalink / raw)
To: linux-arm-kernel
All,
Here's the patch converting all the kirkwood DT boards to Ian's
mv643xx_eth binding. Unfortunately, what I don't like is that the call
to kirkwood_ge00_init() remains, but with a NULL argument.
thx,
Jason.
----- Forwarded message from Ian Molton <ian.molton@codethink.co.uk> -----
Date: Tue, 7 Aug 2012 15:34:51 +0100
From: Ian Molton <ian.molton@codethink.co.uk>
To: linux-arm-kernel at lists.infradead.org
Cc: thomas.petazzoni at free-electrons.com, andrew at lunn.ch,
ben.dooks at codethink.co.uk, arnd at arndb.de, netdev at vger.kernel.org
Subject: [PATCH v3 6/7] DT: Convert all kirkwood boards with mv643xx that use DT
This patch converts all present DT capable kirkwood board configurations
to use DT to configure the mv643xx ethernet controller.
Signed-off-by: Ian Molton <ian.molton@codethink.co.uk>
---
arch/arm/boot/dts/kirkwood-dnskw.dtsi | 9 +++++++++
arch/arm/boot/dts/kirkwood-dreamplug.dts | 18 ++++++++++++++++++
arch/arm/boot/dts/kirkwood-goflexnet.dts | 8 ++++++++
arch/arm/boot/dts/kirkwood-ib62x0.dts | 10 ++++++++++
arch/arm/boot/dts/kirkwood-iconnect.dts | 10 ++++++++++
arch/arm/boot/dts/kirkwood-lsxl.dtsi | 17 +++++++++++++++++
arch/arm/boot/dts/kirkwood-ts219-6281.dts | 8 +++++++-
arch/arm/boot/dts/kirkwood-ts219-6282.dts | 8 +++++++-
arch/arm/boot/dts/kirkwood-ts219.dtsi | 3 +++
arch/arm/mach-kirkwood/board-dnskw.c | 7 +------
arch/arm/mach-kirkwood/board-dreamplug.c | 13 ++-----------
arch/arm/mach-kirkwood/board-goflexnet.c | 7 +------
arch/arm/mach-kirkwood/board-ib62x0.c | 7 +------
arch/arm/mach-kirkwood/board-iconnect.c | 7 +------
arch/arm/mach-kirkwood/board-lsxl.c | 13 ++-----------
arch/arm/mach-kirkwood/board-ts219.c | 10 +---------
16 files changed, 98 insertions(+), 57 deletions(-)
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 7408655..214fe0b 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -65,5 +65,14 @@
reg = <0x7b00000 0x500000>;
};
};
+
+ smi0: mdio at 72000 {
+ status = "ok";
+ };
+
+ egiga0 {
+ phy_addr = <8>;
+ status = "ok";
+ };
};
};
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 26e281f..c27ed1c 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -53,6 +53,24 @@
status = "okay";
nr-ports = <1>;
};
+
+ smi0: mdio at 72000 {
+ status = "ok";
+ };
+
+ smi1: mdio at 76000 {
+ status = "ok";
+ };
+
+ egiga0 {
+ phy_addr = <0>;
+ status = "ok";
+ };
+
+ egiga1 {
+ phy_addr = <1>;
+ status = "ok";
+ };
};
gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index 7c8238f..f03dbd0 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -50,6 +50,14 @@
nr-ports = <2>;
};
+ smi0: mdio at 72000 {
+ status = "ok";
+ };
+
+ egiga0 {
+ phy_addr = <0>;
+ status = "ok";
+ };
};
gpio-leds {
compatible = "gpio-leds";
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 66794ed..8c462a1 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -45,6 +45,16 @@
};
};
+
+ smi0: mdio at 72000 {
+ status = "ok";
+ };
+
+ egiga0 {
+ phy_addr = <8>;
+ status = "ok";
+ };
+
};
gpio_keys {
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 52d9470..9fc82be 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -30,6 +30,16 @@
clock-frequency = <200000000>;
status = "ok";
};
+
+ smi0: mdio at 72000 {
+ status = "ok";
+ };
+
+ egiga0 {
+ phy_addr = <b>;
+ status = "ok";
+ };
+
};
gpio-leds {
compatible = "gpio-leds";
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 8ac51c0..2f47661 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -40,6 +40,23 @@
};
};
};
+ smi0: mdio at 72000 {
+ status = "ok";
+ };
+
+ smi1: mdio at 76000 {
+ status = "ok";
+ };
+
+ egiga0 {
+ phy_addr = <0>;
+ status = "ok";
+ };
+
+ egiga1 {
+ phy_addr = <8>;
+ status = "ok";
+ };
};
gpio_keys {
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index ccbf327..4ca49b5 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -3,6 +3,12 @@
/include/ "kirkwood-ts219.dtsi"
/ {
+ ocp at f1000000 {
+ egiga0 {
+ phy_addr = <8>;
+ status = "ok";
+ };
+ };
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
@@ -18,4 +24,4 @@
gpios = <&gpio0 16 1>;
};
};
-};
\ No newline at end of file
+};
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index fbe9932..40f3c61 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -3,6 +3,12 @@
/include/ "kirkwood-ts219.dtsi"
/ {
+ ocp at f1000000 {
+ egiga0 {
+ phy_addr = <0>;
+ status = "ok";
+ };
+ };
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
@@ -18,4 +24,4 @@
gpios = <&gpio1 5 1>;
};
};
-};
\ No newline at end of file
+};
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 64ea27c..06caf41 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -74,5 +74,8 @@
status = "okay";
nr-ports = <2>;
};
+ smi0: mdio at 72000 {
+ status = "ok";
+ };
};
};
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 4ab3506..4d8216b 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -15,7 +15,6 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
#include <linux/of.h>
#include <linux/gpio.h>
#include <linux/input.h>
@@ -29,10 +28,6 @@
#include "common.h"
#include "mpp.h"
-static struct mv643xx_eth_platform_data dnskw_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
static unsigned int dnskw_mpp_config[] __initdata = {
MPP13_UART1_TXD, /* Custom ... */
MPP14_UART1_RXD, /* ... Controller (DNS-320 only) */
@@ -112,7 +107,7 @@ void __init dnskw_init(void)
kirkwood_mpp_conf(dnskw_mpp_config);
kirkwood_ehci_init();
- kirkwood_ge00_init(&dnskw_ge00_data);
+ kirkwood_ge00_init(NULL);
platform_device_register(&dnskw_fan_device);
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index aeb234d..b97a112 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -15,7 +15,6 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>
@@ -34,14 +33,6 @@
#include "common.h"
#include "mpp.h"
-static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(1),
-};
-
static struct mvsdio_platform_data dreamplug_mvsdio_data = {
/* unfortunately the CD signal has not been connected */
};
@@ -65,7 +56,7 @@ void __init dreamplug_init(void)
kirkwood_mpp_conf(dreamplug_mpp_config);
kirkwood_ehci_init();
- kirkwood_ge00_init(&dreamplug_ge00_data);
- kirkwood_ge01_init(&dreamplug_ge01_data);
+ kirkwood_ge00_init(NULL);
+ kirkwood_ge01_init(NULL);
kirkwood_sdio_init(&dreamplug_mvsdio_data);
}
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
index 413e2c8..be7437d 100644
--- a/arch/arm/mach-kirkwood/board-goflexnet.c
+++ b/arch/arm/mach-kirkwood/board-goflexnet.c
@@ -20,7 +20,6 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>
@@ -36,10 +35,6 @@
#include "common.h"
#include "mpp.h"
-static struct mv643xx_eth_platform_data goflexnet_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(0),
-};
-
static unsigned int goflexnet_mpp_config[] __initdata = {
MPP29_GPIO, /* USB Power Enable */
MPP47_GPIO, /* LED Orange */
@@ -67,5 +62,5 @@ void __init goflexnet_init(void)
pr_err("can't setup GPIO 29 (USB Power Enable)\n");
kirkwood_ehci_init();
- kirkwood_ge00_init(&goflexnet_ge00_data);
+ kirkwood_ge00_init(NULL);
}
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
index cfc47f8..0a29183 100644
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ b/arch/arm/mach-kirkwood/board-ib62x0.c
@@ -16,7 +16,6 @@
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <asm/mach-types.h>
@@ -27,10 +26,6 @@
#define IB62X0_GPIO_POWER_OFF 24
-static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
static unsigned int ib62x0_mpp_config[] __initdata = {
MPP0_NF_IO2,
MPP1_NF_IO3,
@@ -62,7 +57,7 @@ void __init ib62x0_init(void)
kirkwood_mpp_conf(ib62x0_mpp_config);
kirkwood_ehci_init();
- kirkwood_ge00_init(&ib62x0_ge00_data);
+ kirkwood_ge00_init(NULL);
if (gpio_request(IB62X0_GPIO_POWER_OFF, "ib62x0:power:off") == 0 &&
gpio_direction_output(IB62X0_GPIO_POWER_OFF, 0) == 0)
pm_power_off = ib62x0_power_off;
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index d7a9198..220f0d4 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -17,7 +17,6 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/mtd/partitions.h>
-#include <linux/mv643xx_eth.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
@@ -26,10 +25,6 @@
#include "common.h"
#include "mpp.h"
-static struct mv643xx_eth_platform_data iconnect_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(11),
-};
-
static unsigned int iconnect_mpp_config[] __initdata = {
MPP12_GPIO,
MPP35_GPIO,
@@ -92,7 +87,7 @@ void __init iconnect_init(void)
kirkwood_nand_init(ARRAY_AND_SIZE(iconnect_nand_parts), 25);
kirkwood_ehci_init();
- kirkwood_ge00_init(&iconnect_ge00_data);
+ kirkwood_ge00_init(NULL);
platform_device_register(&iconnect_button_device);
}
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 83d8975..60331d1 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -18,7 +18,6 @@
#include <linux/ata_platform.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
-#include <linux/mv643xx_eth.h>
#include <linux/gpio.h>
#include <linux/gpio-fan.h>
#include <linux/input.h>
@@ -28,14 +27,6 @@
#include "common.h"
#include "mpp.h"
-static struct mv643xx_eth_platform_data lsxl_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data lsxl_ge01_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
static unsigned int lsxl_mpp_config[] __initdata = {
MPP10_GPO, /* HDD Power Enable */
MPP11_GPIO, /* USB Vbus Enable */
@@ -126,8 +117,8 @@ void __init lsxl_init(void)
gpio_set_value(LSXL_GPIO_HDD_POWER, 1);
kirkwood_ehci_init();
- kirkwood_ge00_init(&lsxl_ge00_data);
- kirkwood_ge01_init(&lsxl_ge01_data);
+ kirkwood_ge00_init(NULL);
+ kirkwood_ge01_init(NULL);
platform_device_register(&lsxl_fan_device);
/* register power-off method */
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index 1750e68..7e7fe6c 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -18,7 +18,6 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
#include <linux/ata_platform.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
@@ -29,10 +28,6 @@
#include "mpp.h"
#include "tsx1x-common.h"
-static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
static unsigned int qnap_ts219_mpp_config[] __initdata = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
@@ -62,10 +57,7 @@ void __init qnap_dt_ts219_init(void)
kirkwood_mpp_conf(qnap_ts219_mpp_config);
kirkwood_pcie_id(&dev, &rev);
- if (dev == MV88F6282_DEV_ID)
- qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
-
- kirkwood_ge00_init(&qnap_ts219_ge00_data);
+ kirkwood_ge00_init(NULL);
kirkwood_ehci_init();
pm_power_off = qnap_tsx1x_power_off;
--
1.7.9.5
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
----- End forwarded message -----
^ permalink raw reply related
* [PATCH] arm/dts: Add basic support for gta04 (Openmoko next generation) board.
From: Marek Belisko @ 2013-01-24 18:34 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Marek Belisko <marek.belisko@open-nandra.com>
---
arch/arm/boot/dts/omap3-gta04.dts | 94 +++++++++++++++++++++++++++++++++++++
1 file changed, 94 insertions(+)
create mode 100644 arch/arm/boot/dts/omap3-gta04.dts
diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts
new file mode 100644
index 0000000..9e7e3ec
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04.dts
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2013 Marek Belisko <marek.belisko@open-nandra.com>
+ *
+ * Based on omap3-beagle-xm.dts
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+ model = "OMAP3 GTA04";
+ compatible = "ti,omap3-gta04", "ti,omap3";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512 MB */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ aux-button {
+ label = "AUX";
+ linux,code = <169>;
+ gpios = <&gpio1 7 1>;
+ gpio-key,wakeup;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <2600000>;
+
+ twl: twl at 48 {
+ reg = <0x48>;
+ interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+ interrupt-parent = <&intc>;
+ };
+};
+
+/include/ "twl4030.dtsi"
+
+&i2c2 {
+ clock-frequency = <400000>;
+ /* Pressure Sensor */
+ bmp085 at 77 {
+ compatible = "bosch,bmp085";
+ reg = <0x77>;
+ };
+
+ /* leds */
+ tca6507 at 45 {
+ compatible = "ti,tca6507";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x45>;
+
+ gta04_led0: red_aux at 0 {
+ label = "gta04:red:aux";
+ reg = <0x0>;
+ };
+
+ gta04_led1: green_aux at 1 {
+ label = "gta04:green:aux";
+ reg = <0x1>;
+ };
+
+ gta04_led3: red_power at 3 {
+ label = "gta04:red:power";
+ reg = <0x3>;
+ linux,default-trigger = "default-on";
+ };
+
+ gta04_led4: green_power at 4 {
+ label = "gta04:green:power";
+ reg = <0x4>;
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmc1>;
+ bus-width = <4>;
+};
+
--
1.7.10.4
^ permalink raw reply related
* [PATCH] arm: omap: make wakeupgen_lock raw
From: Felipe Balbi @ 2013-01-24 18:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1354891787-24119-1-git-send-email-balbi@ti.com>
Hi,
On Fri, Dec 07, 2012 at 04:49:47PM +0200, Felipe Balbi wrote:
> From: Thomas Gleixner <tglx@linutronix.de>
>
> When applying RT patch on top of Linux, spinlocks are
> implemented as RT-mutexes, which means they are preemptable.
>
> Current GIC implementation on OMAP is using a spinlock
> to protect against preemption. As it turns out, we need
> to convert that lock into a raw_spinlock so that OMAP's
> interrupt controller works as expected after RT-patch
> is applied.
>
> This patch is simply to decrease the amount of changes
> RT-team needs to carry out of tree. It doesn't cause any
> changes in behavior.
>
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> Signed-off-by: Felipe Balbi <balbi@ti.com>
ping
--
balbi
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^ permalink raw reply
* [PATCH v8 3/3] Cortex-M3: Add support for exception handling
From: Jonathan Austin @ 2013-01-24 18:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358413196-5609-4-git-send-email-u.kleine-koenig@pengutronix.de>
Hi Uwe,
Here's the next bunch of comments on this series...
This patch, like the other one, introduces another lot of magic
constants that I'd really rather have #defined as it is much cleaner to
read.
Culprits for this are things in the 0xe000XXXX range, as well as
bitmasks for certain parts of special registers.
Do we need something like arch/arm/include/asm/cp15.h for M?
The second major comment that arises from this patch is that the FP
stuff looks untested/incomplete for M. I would prefer that there was no
FP stuff (for example in this patch the optional skipping of the extra
space in the FP stack-frame) and we added something later. For example,
I imagine that when we come to implement FP for v7-M we might well find
we don't want to use the larger stack-frame every anyway!
These comments, as well as a few related to the idea from the previous
patch of deriving EXC_RETURN rather than storing it in pt_regs.
The final thing that I would like to think a bit more about is whether
we can align our fast and slow exception exits better with what happens
for A-class. At the moment we're quite different (and for good reason,
too), but is there a way to map the M-case more closely on to the
existing code?
On 17/01/13 08:59, Uwe Kleine-K?nig wrote:
> This patch implements the exception handling for the ARMv7-M
> architecture (pretty different from the A or R profiles).
>
> It bases on work done earlier by Catalin for 2.6.33 but was nearly
> completely rewritten to use a pt_regs layout compatible to the A
> profile.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
> ---
> arch/arm/kernel/entry-common.S | 4 ++
> arch/arm/kernel/entry-header.S | 148 ++++++++++++++++++++++++++++++++++++++++
> arch/arm/kernel/entry-v7m.S | 134 ++++++++++++++++++++++++++++++++++++
> arch/arm/kernel/process.c | 4 ++
> arch/arm/kernel/ptrace.c | 3 +
> 5 files changed, 293 insertions(+)
> create mode 100644 arch/arm/kernel/entry-v7m.S
>
> diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
> index 3471175..48d8dc0 100644
> --- a/arch/arm/kernel/entry-common.S
> +++ b/arch/arm/kernel/entry-common.S
> @@ -339,6 +339,9 @@ ENDPROC(ftrace_stub)
>
> .align 5
> ENTRY(vector_swi)
> +#ifdef CONFIG_CPU_V7M
> + v7m_exception_entry
> +#else
> sub sp, sp, #S_FRAME_SIZE
> stmia sp, {r0 - r12} @ Calling r0 - r12
> ARM( add r8, sp, #S_PC )
> @@ -349,6 +352,7 @@ ENTRY(vector_swi)
> str lr, [sp, #S_PC] @ Save calling PC
> str r8, [sp, #S_PSR] @ Save CPSR
> str r0, [sp, #S_OLD_R0] @ Save OLD_R0
> +#endif
> zero_fp
>
> /*
> diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
> index 9a8531e..33d9900 100644
> --- a/arch/arm/kernel/entry-header.S
> +++ b/arch/arm/kernel/entry-header.S
> @@ -44,6 +44,145 @@
> #endif
> .endm
>
> +#ifdef CONFIG_CPU_V7M
> +/*
> + * ARMv7-M exception entry/exit macros.
> + *
> + * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
> + * automatically saved on the current stack (32 words) before
> + * switching to the exception stack (SP_main).
> + *
> + * If exception is taken while in user mode, SP_main is
> + * empty. Otherwise, SP_main is aligned to 64 bit automatically
> + * (CCR.STKALIGN set).
> + *
> + * Linux assumes that the interrupts are disabled when entering an
> + * exception handler and it may BUG if this is not the case. Interrupts
> + * are disabled during entry and reenabled in the exit macro.
> + *
> + * v7m_exception_fast_exit is used when returning from interrupts.
> + *
> + * v7m_exception_slow_exit is used when returning from SVC or PendSV.
> + * When returning to kernel mode, we don't return from exception.
> + */
> + .macro v7m_exception_entry
> + @ determine the location of the registers saved by the core during
> + @ exception entry. Depending on the mode the cpu was in when the
> + @ exception happend that is either on the main or the process stack.
> + @ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
> + @ was used.
> + tst lr, #0x4
> + mrsne r12, psp
> + moveq r12, sp
> +
> + @ we cannot rely on r0-r3 and r12 matching the value saved in the
> + @ exception frame because of tail-chaining. So these have to be
> + @ reloaded.
> + ldmia r12!, {r0-r3}
> +
> + @ Linux expects to have irqs off. Do it here before taking stack space
> + cpsid i
> +
> + sub sp, #S_FRAME_SIZE-S_IP
> + stmdb sp!, {r0-r11}
> +
> + @ load saved r12, lr, return address and xPSR.
> + @ r0-r7 are used for signals and never touched from now on. Clobbering
> + @ r8-r12 is OK.
> + mov r9, r12
> + ldmia r9!, {r8, r10-r12}
> +
> + @ calculate the original stack pointer value.
> + @ r9 currently points to the memory location just above the auto saved
> + @ xPSR. If the FP extension is implemented and bit 4 of EXC_RETURN is 0
> + @ then space was allocated for FP state. That is space for 18 32-bit
> + @ values. (If FP extension is unimplemented, bit 4 is 1.)
> + @ Additionally the cpu might automatically 8-byte align the stack. Bit 9
> + @ of the saved xPSR specifies if stack aligning took place. In this case
> + @ another 32-bit value is included in the stack.
> +
> + tst lr, #0x10
Can we name these constants please as the bitmasks are architecturally
defined. I think if we name the constants the code is more 'self
documenting' ;)
> + addeq r9, r9, #576
Okay, this looks weird, and I don't think it gets tested in the code
path for efm32 as there's not FP support there, correct?
Do we want to add 576 to r9? It looks more like we should be adding
4*18, not 32*18...
I think I probably don't need to go on about them in this patch too, but
this is another bit of magic that I'd like to see #defined. If this was
32*FP_STACK_SIZE
then this would be clearer.
> +
> + tst r12, 0x100
> + addne r9, r9, #4
> +
> + @ store saved r12 using str to have a register to hold the base for stm
> + str r8, [sp, #S_IP]
> + add r8, sp, #S_SP
> + @ store r13-r15, xPSR
> + stmia r8!, {r9-r12}
> + @ store r0 once more and EXC_RETURN
> + stmia r8, {r0, lr}
> + .endm
> +
> + .macro v7m_exception_fast_exit
> + @ registers r0-r3 and r12 are automatically restored on exception
> + @ return. r4-r7 were not clobbered in v7m_exception_entry so for
> + @ correctness they don't need to be restored. So only r8-r11 must be
> + @ restored here. The easiest way to do so is to restore r0-r7, too.
> + ldmia sp!, {r0-r11}
> + add sp, #S_FRAME_SIZE-S_IP
> + cpsie i
> + bx lr
> + .endm
We don't set lr here - we seem to rely on whatever is calling
v7m_fast_exit to do that.
Is that safe? So far it works because we only do a fast exit from a few
locations, but as the port grows I worry about that being always true...
Secondly, I think we need a clrex somewhere in this path:
The ARM ARM states that if a strex is performed to any address other
than the last one from which a ldrex was done AND the exclusive monitor
is exclusive access state then it is implementation defined whether the
store succeeds. In ARMv7-M this must be treated as a programming error.
I think without a clrex here we can provoke this:
(A) (b)
... ...
ldrex(a)
...
-------context switch--------
...
ldrex(b)
...
-------context switch--------
strex(a)
And I believe the same is required in the slow path, as this could be
required after returning from a pend_sv or even when switching between
kernel threads if we've got a pre-emptable kernel
And that leads me to think perhaps we should have some unified part of
the exception return path?
> +
> + .macro v7m_exception_slow_exit ret_r0
> + cpsid i
> + ldr lr, [sp, #S_EXC_RET] @ read exception LR0.11.22
So, if we chose to remove ARM_EXC_RET from pt_regs we could instead load
S_PSR, and check if the IPSR part of this is zero to decide whether
we're going back to handler or thread mode. Put the appropriate EXC_RET
in to lr and carry on as usual...
(typed in editor/intended for explanation not compilation)
ldr lr, [sp, #S_PSR]
ands lr, lr, #IPSR_MASK
ldreq lr, #ER_THREAD_PROCESS_BASIC
ldrne lr, #ER_THREAD_HANDLER_BASIC
Where IPSR_MASK is 0x1FF (bits 0-8 of the xPSR)
> + tst lr, #0x8
> + bne 1f @ go to thread mode using exception return
> +
> + /*
> + * return to kernel thread
> + * sp is already set up (and might be unset in pt_regs), so only
> + * restore r0-r12 and pc
> + */
> + ldmia sp, {r0-r12}
> + ldr lr, [sp, #S_PC]
> + add sp, sp, #S_FRAME_SIZE
> + cpsie i
As I mentioned above, this path needs a clrex too (or we should have
some unified return path with a clrex)
> + bx lr
> +
> +1: /*
> + * return to userspace
> + */
> +
> + @ read original r12, sp, lr, pc and xPSR
> + add r12, sp, #S_IP
> + ldmia r12, {r1-r5}
> +
> + @ handle stack aligning
> + tst r5, #0x100
> + subne r2, r2, #4
> +
> + @ skip over stack space for fp saving
> + tst lr, #0x10
> + subeq r2, r2, #576
> +
This is another bit/byte error, I presume?
We could simplify this code quite a lot by enforcing that we only ever
use the standard (basic) exception frame size...
Given the extra overhead of saving all the FP registers, what do you
think about doing that in a lazy fashion, a bit like we do for A-class.
This way we could always disable FP on return to userspace, and we'd not
need to worry about the different size frames?
> + @ write basic exception frame
> + stmdb r2!, {r1, r3-r5}
> + ldmia sp, {r1, r3-r5}
> + .if \ret_r0
> + stmdb r2!, {r0, r3-r5}
> + .else
> + stmdb r2!, {r1, r3-r5}
> + .endif
> +
> + @ restore process sp
> + msr psp, r2
> +
> + @ restore original r4-r11
> + ldmia sp!, {r0-r11}
The comment and the code don't match here.
Didn't we just set up a stack frame so that the hardware would restore
r0-r3 for us? I guess perhaps you're doing this to save an instruction
but I had a quick chat with the hardware guys and they reckon that we're
better to fix up sp with an add first, then ldmia fewer registers.
Is there something I'm missing about why you're written back r0-r3 too?
> +
> + @ restore main sp
> + add sp, sp, #S_FRAME_SIZE-S_IP
> +
> + cpsie i
> + bx lr
> + .endm
> +#endif /* CONFIG_CPU_V7M */
> +
> @
> @ Store/load the USER SP and LR registers by switching to the SYS
> @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
> @@ -131,6 +270,14 @@
> rfeia sp!
> .endm
>
> +#ifdef CONFIG_CPU_V7M
> + .macro restore_user_regs, fast = 0, offset = 0
> + .if \offset
> + add sp, #\offset
> + .endif
> + v7m_exception_slow_exit ret_r0 = \fast
> + .endm
> +#else /* !CONFIG_CPU_V7M */
> .macro restore_user_regs, fast = 0, offset = 0
> clrex @ clear the exclusive monitor
> mov r2, sp
> @@ -147,6 +294,7 @@
> add sp, sp, #S_FRAME_SIZE - S_SP
> movs pc, lr @ return & move spsr_svc into cpsr
> .endm
> +#endif /* CONFIG_CPU_V7M */
>
> .macro get_thread_info, rd
> mov \rd, sp
> diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
> new file mode 100644
> index 0000000..842394c
> --- /dev/null
> +++ b/arch/arm/kernel/entry-v7m.S
> @@ -0,0 +1,134 @@
> +/*
> + * linux/arch/arm/kernel/entry-v7m.S
> + *
> + * Copyright (C) 2008 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Low-level vector interface routines for the ARMv7-M architecture
> + */
> +#include <asm/memory.h>
> +#include <asm/glue.h>
> +#include <asm/thread_notify.h>
> +
> +#include <mach/entry-macro.S>
> +
> +#include "entry-header.S"
> +
> +#ifdef CONFIG_PREEMPT
> +#error "CONFIG_PREEMPT not supported on the current ARMv7M implementation"
> +#endif
> +#ifdef CONFIG_TRACE_IRQFLAGS
> +#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation"
> +#endif
> +
> +__invalid_entry:
> + v7m_exception_entry
> + adr r0, strerr
> + mrs r1, ipsr
> + mov r2, lr
> + bl printk
> + mov r0, sp
> + bl show_regs
> +1: b 1b
> +ENDPROC(__invalid_entry)
> +
> +strerr: .asciz "\nUnhandled exception: IPSR = %08lx LR = %08lx\n"
> +
> + .align 2
> +__irq_entry:
> + v7m_exception_entry
> +
> + @
> + @ Invoke the IRQ handler
> + @
> + mrs r0, ipsr
> + and r0, #0xff
> + sub r0, #16 @ IRQ number
> + mov r1, sp
> + @ routine called with r0 = irq number, r1 = struct pt_regs *
> + bl asm_do_IRQ
> +
> + @
> + @ Check for any pending work if returning to user
> + @
> + ldr lr, [sp, #S_EXC_RET]
Same kind of change as I describe above might work here, too.
It also struck me as a bit weird that we do this in the __irq_entry
*not* in the fast exit path. What's the reasoning behind that. I know at
the moment that the only user of the fast_exit is the irq handler, but
is that always going to be true?
> + tst lr, #0x8 @ check the return stack
> + beq 2f @ returning to handler mode
> + get_thread_info tsk
> + ldr r1, [tsk, #TI_FLAGS]
> + tst r1, #_TIF_WORK_MASK
> + beq 2f @ no work pending
> + ldr r1, =0xe000ed04 @ ICSR
> + mov r0, #1 << 28 @ ICSR.PENDSVSET
> + str r0, [r1] @ raise PendSV
> +
> +2:
> + v7m_exception_fast_exit
At the moment this is the only place that we use fast_exit, and I wonder
if there is scope to inline *some* of fast_exit here and split the rest
of it off in to a common exit path.
For example
fast_exit becomes
* new stuff at the end of __irq_entry
* common_exit
slow_exit becomes
* slow_exit
* common_exit
But if you have plans to use v7m_exception_fast_exit more broadly in the
future then disregard this...
> +ENDPROC(__irq_entry)
> +
> +__pendsv_entry:
> + v7m_exception_entry
> +
> + ldr r1, =0xe000ed04 @ ICSR
> + mov r0, #1 << 27 @ ICSR.PENDSVCLR
> + str r0, [r1] @ clear PendSV
> +
> + @ execute the pending work, including reschedule
> + get_thread_info tsk
> + mov why, #0
> + b ret_to_user
> +ENDPROC(__pendsv_entry)
> +
> +/*
> + * Register switch for ARMv7-M processors.
> + * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
> + * previous and next are guaranteed not to be the same.
> + */
> +ENTRY(__switch_to)
> + .fnstart
> + .cantunwind
> + add ip, r1, #TI_CPU_SAVE
Out of curiosity, why ip here not r12 as later in the code?
> + stmia ip!, {r4 - r11} @ Store most regs on stack
> + str sp, [ip], #4
> + str lr, [ip], #4
> + mov r5, r0
> + add r4, r2, #TI_CPU_SAVE
> + ldr r0, =thread_notify_head
> + mov r1, #THREAD_NOTIFY_SWITCH
> + bl atomic_notifier_call_chain
> + mov ip, r4
> + mov r0, r5
> + ldmia ip!, {r4 - r11} @ Load all regs saved previously
> + ldr sp, [ip]
> + ldr pc, [ip, #4]!
> + .fnend
> +ENDPROC(__switch_to)
> +
> + .data
> + .align 8
> +/*
> + * Vector table (64 words => 256 bytes natural alignment)
> + */
> +ENTRY(vector_table)
> + .long 0 @ 0 - Reset stack pointer
> + .long __invalid_entry @ 1 - Reset
> + .long __invalid_entry @ 2 - NMI
> + .long __invalid_entry @ 3 - HardFault
> + .long __invalid_entry @ 4 - MemManage
> + .long __invalid_entry @ 5 - BusFault
> + .long __invalid_entry @ 6 - UsageFault
> + .long __invalid_entry @ 7 - Reserved
> + .long __invalid_entry @ 8 - Reserved
> + .long __invalid_entry @ 9 - Reserved
> + .long __invalid_entry @ 10 - Reserved
> + .long vector_swi @ 11 - SVCall
> + .long __invalid_entry @ 12 - Debug Monitor
> + .long __invalid_entry @ 13 - Reserved
> + .long __pendsv_entry @ 14 - PendSV
> + .long __invalid_entry @ 15 - SysTick
> + .rept 64 - 16
> + .long __irq_entry @ 16..64 - External Interrupts
> + .endr
> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> index 90084a6..3d745d4 100644
> --- a/arch/arm/kernel/process.c
> +++ b/arch/arm/kernel/process.c
> @@ -387,6 +387,10 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
> *childregs = *regs;
> childregs->ARM_r0 = 0;
> childregs->ARM_sp = stack_start;
> +#if defined CONFIG_CPU_V7M
> + /* Return to Thread mode with Process stack */
> + childregs->ARM_EXC_RET = 0xfffffffdUL;
> +#endif
Another justification for deriving this instead of
saving/storing/copying it - we could remove another #ifdef block.
> } else {
> memset(childregs, 0, sizeof(struct pt_regs));
> thread->cpu_context.r4 = stk_sz;
> diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
> index 739db3a..55df1d5 100644
> --- a/arch/arm/kernel/ptrace.c
> +++ b/arch/arm/kernel/ptrace.c
> @@ -87,6 +87,9 @@ static const struct pt_regs_offset regoffset_table[] = {
> REG_OFFSET_NAME(pc),
> REG_OFFSET_NAME(cpsr),
> REG_OFFSET_NAME(ORIG_r0),
> +#ifdef CONFIG_CPU_V7M
> + REG_OFFSET_NAME(EXC_RET),
> +#endif
> REG_OFFSET_END,
> };
>
>
Hope you find these comments useful!
Jonny
^ permalink raw reply
* [RFC PATCH 6/6] ARM: kirkwood: consolidate mv643xx_eth init for DT
From: Jason Cooper @ 2013-01-24 18:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <510174AF.4020503@openwrt.org>
On Thu, Jan 24, 2013 at 06:51:43PM +0100, Florian Fainelli wrote:
> On 01/24/2013 05:13 PM, Jason Cooper wrote:
> >On Thu, Jan 24, 2013 at 03:54:27PM +0000, Arnd Bergmann wrote:
> >>On Thursday 24 January 2013, Jason Cooper wrote:
> >>>I agree, however, there is a long history with that patch. That driver
> >>>has been in use by powerpc for many years. We need to be mindful not to
> >>>break existing installations. I don't think it'll be ready in time for
> >>>v3.9. So, I'd like to do the cleanup now.
> >>>
> >>>>[1]: http://patchwork.ozlabs.org/patch/175652/
> >>>
> >>I actually think we can take that patch.
> >
> >Woot!
> >
> >>The result of the discussion back then was after all that we won't try
> >>to keep the bindings compatible, and the powerpc version just uses the
> >>platform_device part of the driver by fabricating platform_data from
> >>the arch code.
> >>
> >>It should not have any impact on this, as long as you ensure that the
> >>platform_data is still supported.
> >
> >Ian's patch appears to do so. I'll respin this series using it vice my
> >lookup table.
> >
> Sounds good, while at it, I wonder if we could not simplify Ian's
> patch to be limited to the actual Ethernet MAC driver and use
> Thomas's mvdio device tree binding for the MDIO bits of mv643xx_eth.
> What do you think?
It sounds like you just volunteered ;-) Do you think you have the time
to knock it out for v3.9?
I'd like to drop most of these board-*.c files for v3.9. They've been
bugging me since I added the first one (board-dreamplug.c).
thx,
Jason.
^ permalink raw reply
* [PATCH 1/4] clk: Introduce optional is_prepared callback
From: Mike Turquette @ 2013-01-24 18:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359045956-30741-2-git-send-email-ulf.hansson@stericsson.com>
Quoting Ulf Hansson (2013-01-24 08:45:53)
> From: Ulf Hansson <ulf.hansson@linaro.org>
>
> To reflect whether a clk_hw is prepared the clk_hw may implement
> the optional is_prepared callback. If not implemented we fall back
> to use the software prepare counter.
>
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> drivers/clk/clk.c | 21 +++++++++++++++++++++
> include/linux/clk-provider.h | 6 ++++++
> 2 files changed, 27 insertions(+)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 593a2e4..deb259a 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -458,6 +458,27 @@ unsigned long __clk_get_flags(struct clk *clk)
> return !clk ? 0 : clk->flags;
> }
>
> +bool __clk_is_prepared(struct clk *clk)
> +{
> + int ret;
> +
> + if (!clk)
> + return false;
> +
> + /*
> + * .is_prepared is optional for clocks that can prepare
> + * fall back to software usage counter if it is missing
> + */
Why not make it mandatory? This could be as simple as saying "it is
mandatory", or we could even enforce a check in clk_init, though the
latter suggestion would be noisy until existing clock providers were
updated.
Note that .is_enabled is technically mandatory for any clock that
implements .enable/.disable but there is no check for compliance. It is
only in Documentation/clk.txt and the kerneldoc.
Regards,
Mike
^ permalink raw reply
* [PATCH v2 1/1 net-next] net: fec: add napi support to improve proformance
From: Troy Kisky @ 2013-01-24 17:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359014309-8636-1-git-send-email-Frank.Li@freescale.com>
On 1/24/2013 12:58 AM, Frank Li wrote:
> diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
> index f52ba33..39be2ab 100644
> --- a/drivers/net/ethernet/freescale/fec.c
> +++ b/drivers/net/ethernet/freescale/fec.c
> @@ -67,6 +67,7 @@
> #endif
>
> #define DRIVER_NAME "fec"
> +#define FEC_NAPI_WEIGHT 64
>
> /* Pause frame feild and FIFO threshold */
> #define FEC_ENET_FCE (1 << 5)
> @@ -565,6 +566,20 @@ fec_timeout(struct net_device *ndev)
> }
>
> static void
> +fec_enet_rx_int_is_enabled(struct net_device *ndev, bool enabled)
> +{
> + struct fec_enet_private *fep = netdev_priv(ndev);
> + uint int_events;
> +
> + int_events = readl(fep->hwp + FEC_IMASK);
> + if (enabled)
> + int_events |= FEC_ENET_RXF;
> + else
> + int_events &= ~FEC_ENET_RXF;
> + writel(int_events, fep->hwp + FEC_IMASK);
> +}
fec_enet_rx_int_is_enabled looks like a question.
fec_enet_rx_int_enable would be a better name
^ permalink raw reply
* [RFC PATCH 6/6] ARM: kirkwood: consolidate mv643xx_eth init for DT
From: Florian Fainelli @ 2013-01-24 17:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130124161349.GC1758@titan.lakedaemon.net>
On 01/24/2013 05:13 PM, Jason Cooper wrote:
> On Thu, Jan 24, 2013 at 03:54:27PM +0000, Arnd Bergmann wrote:
>> On Thursday 24 January 2013, Jason Cooper wrote:
>>> I agree, however, there is a long history with that patch. That driver
>>> has been in use by powerpc for many years. We need to be mindful not to
>>> break existing installations. I don't think it'll be ready in time for
>>> v3.9. So, I'd like to do the cleanup now.
>>>
>>>> [1]: http://patchwork.ozlabs.org/patch/175652/
>> I actually think we can take that patch.
> Woot!
>
>> The result of the discussion back then was after all that we won't try
>> to keep the bindings compatible, and the powerpc version just uses the
>> platform_device part of the driver by fabricating platform_data from
>> the arch code.
>>
>> It should not have any impact on this, as long as you ensure that the
>> platform_data is still supported.
> Ian's patch appears to do so. I'll respin this series using it vice my
> lookup table.
Sounds good, while at it, I wonder if we could not simplify Ian's patch
to be limited to the actual Ethernet MAC driver and use Thomas's mvdio
device tree binding for the MDIO bits of mv643xx_eth. What do you think?
--
Florian
^ permalink raw reply
* [PATCH 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
From: Rob Herring @ 2013-01-24 17:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358963974-5496-5-git-send-email-catalin.marinas@arm.com>
On 01/23/2013 11:59 AM, Catalin Marinas wrote:
> All the calls to gic_secondary_init() pass 0 as the first argument.
> Since this function is called on each CPU when starting, it can be done
> in a platform-independent way via a CPU notifier registered by the GIC
> code.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: David Brown <davidb@codeaurora.org>
> Cc: Daniel Walker <dwalker@fifo99.com>
> Cc: Bryan Huntsman <bryanh@codeaurora.org>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Simon Horman <horms@verge.net.au>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Shiraz Hashim <shiraz.hashim@st.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
Acked-by: Rob Herring <rob.herring@calxeda.com>
>
> Randomly chosen CPU notifier priority. I can add a definition somewhere
> though they don't seem to be used much and cause conflicts.
>
> arch/arm/mach-exynos/platsmp.c | 8 --------
> arch/arm/mach-highbank/platsmp.c | 7 -------
> arch/arm/mach-imx/platsmp.c | 12 ------------
> arch/arm/mach-msm/platsmp.c | 8 --------
> arch/arm/mach-omap2/omap-smp.c | 7 -------
> arch/arm/mach-shmobile/smp-emev2.c | 7 -------
> arch/arm/mach-shmobile/smp-r8a7779.c | 7 -------
> arch/arm/mach-shmobile/smp-sh73a0.c | 7 -------
> arch/arm/mach-socfpga/platsmp.c | 12 ------------
> arch/arm/mach-spear13xx/platsmp.c | 8 --------
> arch/arm/mach-tegra/platsmp.c | 8 --------
> arch/arm/mach-ux500/platsmp.c | 8 --------
> arch/arm/plat-versatile/platsmp.c | 8 --------
> drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++-------
> include/linux/irqchip/arm-gic.h | 1 -
> 15 files changed, 21 insertions(+), 115 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index a083e05..a0e8ff7 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -20,7 +20,6 @@
> #include <linux/jiffies.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/smp_plat.h>
> @@ -77,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock);
> static void __cpuinit exynos_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
> index 8797a70..a984573 100644
> --- a/arch/arm/mach-highbank/platsmp.c
> +++ b/arch/arm/mach-highbank/platsmp.c
> @@ -17,7 +17,6 @@
> #include <linux/init.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/smp_scu.h>
>
> @@ -25,11 +24,6 @@
>
> extern void secondary_startup(void);
>
> -static void __cpuinit highbank_secondary_init(unsigned int cpu)
> -{
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> highbank_set_cpu_jump(cpu, secondary_startup);
> @@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
> struct smp_operations highbank_smp_ops __initdata = {
> .smp_init_cpus = highbank_smp_init_cpus,
> .smp_prepare_cpus = highbank_smp_prepare_cpus,
> - .smp_secondary_init = highbank_secondary_init,
> .smp_boot_secondary = highbank_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_die = highbank_cpu_die,
> diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
> index b2872ec..7f63dda 100644
> --- a/arch/arm/mach-imx/platsmp.c
> +++ b/arch/arm/mach-imx/platsmp.c
> @@ -12,7 +12,6 @@
>
> #include <linux/init.h>
> #include <linux/smp.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <asm/page.h>
> #include <asm/smp_scu.h>
> #include <asm/mach/map.h>
> @@ -42,16 +41,6 @@ void __init imx_scu_map_io(void)
> scu_base = IMX_IO_ADDRESS(base);
> }
>
> -static void __cpuinit imx_secondary_init(unsigned int cpu)
> -{
> - /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> imx_set_cpu_jump(cpu, v7_secondary_startup);
> @@ -86,7 +75,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
> struct smp_operations imx_smp_ops __initdata = {
> .smp_init_cpus = imx_smp_init_cpus,
> .smp_prepare_cpus = imx_smp_prepare_cpus,
> - .smp_secondary_init = imx_secondary_init,
> .smp_boot_secondary = imx_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_die = imx_cpu_die,
> diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
> index 42932865..00cdb0a 100644
> --- a/arch/arm/mach-msm/platsmp.c
> +++ b/arch/arm/mach-msm/platsmp.c
> @@ -15,7 +15,6 @@
> #include <linux/jiffies.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/cputype.h>
> @@ -42,13 +41,6 @@ static inline int get_core_count(void)
> static void __cpuinit msm_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
> index 3616779..c6ce880 100644
> --- a/arch/arm/mach-omap2/omap-smp.c
> +++ b/arch/arm/mach-omap2/omap-smp.c
> @@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
> 4, 0, 0, 0, 0, 0);
>
> /*
> - * If any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * Synchronise with the boot thread.
> */
> spin_lock(&boot_lock);
> diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
> index 953eb1f..384e27d 100644
> --- a/arch/arm/mach-shmobile/smp-emev2.c
> +++ b/arch/arm/mach-shmobile/smp-emev2.c
> @@ -23,7 +23,6 @@
> #include <linux/spinlock.h>
> #include <linux/io.h>
> #include <linux/delay.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <mach/common.h>
> #include <mach/emev2.h>
> #include <asm/smp_plat.h>
> @@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
> }
>
>
> -static void __cpuinit emev2_secondary_init(unsigned int cpu)
> -{
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> cpu = cpu_logical_map(cpu);
> @@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)
> struct smp_operations emev2_smp_ops __initdata = {
> .smp_init_cpus = emev2_smp_init_cpus,
> .smp_prepare_cpus = emev2_smp_prepare_cpus,
> - .smp_secondary_init = emev2_secondary_init,
> .smp_boot_secondary = emev2_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_kill = emev2_cpu_kill,
> diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
> index 3a4acf2..9949065 100644
> --- a/arch/arm/mach-shmobile/smp-r8a7779.c
> +++ b/arch/arm/mach-shmobile/smp-r8a7779.c
> @@ -23,7 +23,6 @@
> #include <linux/spinlock.h>
> #include <linux/io.h>
> #include <linux/delay.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <mach/common.h>
> #include <mach/r8a7779.h>
> #include <asm/smp_plat.h>
> @@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
> }
>
>
> -static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
> -{
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> struct r8a7779_pm_ch *ch = NULL;
> @@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)
> struct smp_operations r8a7779_smp_ops __initdata = {
> .smp_init_cpus = r8a7779_smp_init_cpus,
> .smp_prepare_cpus = r8a7779_smp_prepare_cpus,
> - .smp_secondary_init = r8a7779_secondary_init,
> .smp_boot_secondary = r8a7779_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_kill = r8a7779_cpu_kill,
> diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
> index 9812ea3..f3b4912 100644
> --- a/arch/arm/mach-shmobile/smp-sh73a0.c
> +++ b/arch/arm/mach-shmobile/smp-sh73a0.c
> @@ -23,7 +23,6 @@
> #include <linux/spinlock.h>
> #include <linux/io.h>
> #include <linux/delay.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <mach/common.h>
> #include <asm/cacheflush.h>
> #include <asm/smp_plat.h>
> @@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)
> return scu_get_core_count(scu_base);
> }
>
> -static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
> -{
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> cpu = cpu_logical_map(cpu);
> @@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)
> struct smp_operations sh73a0_smp_ops __initdata = {
> .smp_init_cpus = sh73a0_smp_init_cpus,
> .smp_prepare_cpus = sh73a0_smp_prepare_cpus,
> - .smp_secondary_init = sh73a0_secondary_init,
> .smp_boot_secondary = sh73a0_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_kill = sh73a0_cpu_kill,
> diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
> index 4e9e69d..4b468ef 100644
> --- a/arch/arm/mach-socfpga/platsmp.c
> +++ b/arch/arm/mach-socfpga/platsmp.c
> @@ -22,7 +22,6 @@
> #include <linux/io.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/smp_scu.h>
> @@ -33,16 +32,6 @@
> extern void __iomem *sys_manager_base_addr;
> extern void __iomem *rst_manager_base_addr;
>
> -static void __cpuinit socfpga_secondary_init(unsigned int cpu)
> -{
> - /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -}
> -
> static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
> @@ -106,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu)
> struct smp_operations socfpga_smp_ops __initdata = {
> .smp_init_cpus = socfpga_smp_init_cpus,
> .smp_prepare_cpus = socfpga_smp_prepare_cpus,
> - .smp_secondary_init = socfpga_secondary_init,
> .smp_boot_secondary = socfpga_boot_secondary,
> #ifdef CONFIG_HOTPLUG_CPU
> .cpu_die = socfpga_cpu_die,
> diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
> index af4ade6..551c69c 100644
> --- a/arch/arm/mach-spear13xx/platsmp.c
> +++ b/arch/arm/mach-spear13xx/platsmp.c
> @@ -15,7 +15,6 @@
> #include <linux/jiffies.h>
> #include <linux/io.h>
> #include <linux/smp.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <asm/cacheflush.h>
> #include <asm/smp_scu.h>
> #include <mach/spear.h>
> @@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
> static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
> index c72e249..dea94d2 100644
> --- a/arch/arm/mach-tegra/platsmp.c
> +++ b/arch/arm/mach-tegra/platsmp.c
> @@ -18,7 +18,6 @@
> #include <linux/jiffies.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
> #include <linux/clk/tegra.h>
>
> #include <asm/cacheflush.h>
> @@ -45,13 +44,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
>
> static void __cpuinit tegra_secondary_init(unsigned int cpu)
> {
> - /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
> }
>
> diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
> index b8adac9..b4d0735 100644
> --- a/arch/arm/mach-ux500/platsmp.c
> +++ b/arch/arm/mach-ux500/platsmp.c
> @@ -16,7 +16,6 @@
> #include <linux/device.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/smp_plat.h>
> @@ -55,13 +54,6 @@ static DEFINE_SPINLOCK(boot_lock);
> static void __cpuinit ux500_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
> index f2ac155..1e1b2d7 100644
> --- a/arch/arm/plat-versatile/platsmp.c
> +++ b/arch/arm/plat-versatile/platsmp.c
> @@ -14,7 +14,6 @@
> #include <linux/device.h>
> #include <linux/jiffies.h>
> #include <linux/smp.h>
> -#include <linux/irqchip/arm-gic.h>
>
> #include <asm/cacheflush.h>
> #include <asm/smp_plat.h>
> @@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);
> void __cpuinit versatile_secondary_init(unsigned int cpu)
> {
> /*
> - * if any interrupts are already enabled for the primary
> - * core (e.g. timer irq), then they will not have been enabled
> - * for us: do so
> - */
> - gic_secondary_init(0);
> -
> - /*
> * let the primary processor know we're out of the
> * pen, then head off into the C entry point
> */
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index ef1429a..f103cb8 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -28,6 +28,7 @@
> #include <linux/module.h>
> #include <linux/list.h>
> #include <linux/smp.h>
> +#include <linux/cpu.h>
> #include <linux/cpu_pm.h>
> #include <linux/cpumask.h>
> #include <linux/io.h>
> @@ -678,6 +679,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
> return 0;
> }
>
> +#ifdef CONFIG_SMP
> +static int __cpuinit gic_secondary_init(struct notifier_block *nfb,
> + unsigned long action, void *hcpu)
> +{
> + if (action == CPU_STARTING)
> + gic_cpu_init(&gic_data[0]);
> + return NOTIFY_OK;
> +}
> +
> +/*
> + * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
> + * priority because the GIC needs to be up before the ARM generic timers.
> + */
> +static struct notifier_block __cpuinitdata gic_cpu_notifier = {
> + .notifier_call = gic_secondary_init,
> + .priority = 100,
> +};
> +#endif
> +
> const struct irq_domain_ops gic_irq_domain_ops = {
> .map = gic_irq_domain_map,
> .xlate = gic_irq_domain_xlate,
> @@ -768,6 +788,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
>
> #ifdef CONFIG_SMP
> set_smp_cross_call(gic_raise_softirq);
> + register_cpu_notifier(&gic_cpu_notifier);
> #endif
>
> set_handle_irq(gic_handle_irq);
> @@ -778,13 +799,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
> gic_pm_init(gic);
> }
>
> -void __cpuinit gic_secondary_init(unsigned int gic_nr)
> -{
> - BUG_ON(gic_nr >= MAX_GIC_NR);
> -
> - gic_cpu_init(&gic_data[gic_nr]);
> -}
> -
> #ifdef CONFIG_OF
> static int gic_cnt __initdata = 0;
>
> diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
> index a67ca55..59e59b3 100644
> --- a/include/linux/irqchip/arm-gic.h
> +++ b/include/linux/irqchip/arm-gic.h
> @@ -36,7 +36,6 @@ extern struct irq_chip gic_arch_extn;
>
> void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
> u32 offset, struct device_node *);
> -void gic_secondary_init(unsigned int);
> void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
>
> static inline void gic_init(unsigned int nr, int start,
>
^ permalink raw reply
* [PATCH 1/7] clk: add common of_clk_init() function
From: Rob Herring @ 2013-01-24 17:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357282858-2112-1-git-send-email-pgaikwad@nvidia.com>
On 01/04/2013 01:00 AM, Prashant Gaikwad wrote:
> Modify of_clk_init function so that it will determine which
> driver to initialize based on device tree instead of each driver
> registering to it.
>
> Based on a similar patch for drivers/irqchip by Thomas Petazzoni and
> drivers/clocksource by Stephen Warren.
>
> Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
> ---
For this and highbank:
Tested-by: Rob Herring <rob.herring@calxeda.com>
> drivers/clk/clk-fixed-rate.c | 1 +
> drivers/clk/clk.c | 9 +++++++++
> include/asm-generic/vmlinux.lds.h | 10 ++++++++++
> include/linux/clk-provider.h | 6 ++++++
> 4 files changed, 26 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
> index af78ed6..f2104df 100644
> --- a/drivers/clk/clk-fixed-rate.c
> +++ b/drivers/clk/clk-fixed-rate.c
> @@ -101,4 +101,5 @@ void __init of_fixed_clk_setup(struct device_node *node)
> of_clk_add_provider(node, of_clk_src_simple_get, clk);
> }
> EXPORT_SYMBOL_GPL(of_fixed_clk_setup);
> +CLK_OF_DECLARE(fixed_clk, "fixed-clock", of_fixed_clk_setup);
> #endif
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 037b48a..fb38dd8 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -18,6 +18,7 @@
> #include <linux/slab.h>
> #include <linux/of.h>
> #include <linux/device.h>
> +#include <linux/init.h>
>
> static DEFINE_SPINLOCK(enable_lock);
> static DEFINE_MUTEX(prepare_lock);
> @@ -1805,6 +1806,11 @@ struct of_clk_provider {
> void *data;
> };
>
> +extern struct of_device_id __clk_of_table[];
> +
> +static const struct of_device_id __clk_of_table_sentinel
> + __used __section(__clk_of_table_end);
> +
> static LIST_HEAD(of_clk_providers);
> static DEFINE_MUTEX(of_clk_lock);
>
> @@ -1933,6 +1939,9 @@ void __init of_clk_init(const struct of_device_id *matches)
> {
> struct device_node *np;
>
> + if (!matches)
> + matches = __clk_of_table;
> +
> for_each_matching_node(np, matches) {
> const struct of_device_id *match = of_match_node(matches, np);
> of_clk_init_cb_t clk_init_cb = match->data;
> diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
> index 1e744c5..8282f7c 100644
> --- a/include/asm-generic/vmlinux.lds.h
> +++ b/include/asm-generic/vmlinux.lds.h
> @@ -158,6 +158,15 @@
> #define CLKSRC_OF_TABLES()
> #endif
>
> +#ifdef CONFIG_COMMON_CLK
> +#define CLK_OF_TABLES() . = ALIGN(8); \
> + VMLINUX_SYMBOL(__clk_of_table) = .; \
> + *(__clk_of_table) \
> + *(__clk_of_table_end)
> +#else
> +#define CLK_OF_TABLES()
> +#endif
> +
> #define KERNEL_DTB() \
> STRUCT_ALIGN(); \
> VMLINUX_SYMBOL(__dtb_start) = .; \
> @@ -502,6 +511,7 @@
> CPU_DISCARD(init.rodata) \
> MEM_DISCARD(init.rodata) \
> CLKSRC_OF_TABLES() \
> + CLK_OF_TABLES() \
> KERNEL_DTB()
>
> #define INIT_TEXT \
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 4989b8a..7f197d7 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -379,7 +379,13 @@ struct clk_onecell_data {
> };
> struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
> const char *of_clk_get_parent_name(struct device_node *np, int index);
> +
> void of_clk_init(const struct of_device_id *matches);
>
> +#define CLK_OF_DECLARE(name, compat, fn) \
> + static const struct of_device_id __clk_of_table_##name \
> + __used __section(__clk_of_table) \
> + = { .compatible = compat, .data = fn };
> +
> #endif /* CONFIG_COMMON_CLK */
> #endif /* CLK_PROVIDER_H */
>
^ permalink raw reply
* [PATCH 2/4] arm: Move chained_irq_(enter|exit) to a generic file
From: Catalin Marinas @ 2013-01-24 17:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5100C759.4070503@ti.com>
On Thu, Jan 24, 2013 at 05:32:09AM +0000, Santosh Shilimkar wrote:
> On Wednesday 23 January 2013 11:29 PM, Catalin Marinas wrote:
> > diff --git a/include/linux/irqchip/chained_irq.h b/include/linux/irqchip/chained_irq.h
> > new file mode 100644
> > index 0000000..adf4c30
> > --- /dev/null
> > +++ b/include/linux/irqchip/chained_irq.h
> > @@ -0,0 +1,52 @@
> > +/*
> > + * Chained IRQ handlers support.
> > + *
> > + * Copyright (C) 2011 ARM Ltd.
>
> 2013 now ;)
I thought about this but decided to keep the year when the chained IRQ
functions were contributed by Will (still ARM's copyright).
--
Catalin
^ permalink raw reply
* OMAP4 randconfig failure: Zynq
From: Rob Herring @ 2013-01-24 17:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130124170803.GA1036@beefymiracle.amer.corp.natinst.com>
On 01/24/2013 11:08 AM, Josh Cartwright wrote:
> On Thu, Jan 24, 2013 at 04:12:11PM +0000, Russell King - ARM Linux wrote:
>> On Thu, Jan 24, 2013 at 04:06:09PM +0000, Russell King - ARM Linux wrote:
>>> On Thu, Jan 24, 2013 at 09:57:04AM -0600, Josh Cartwright wrote:
>>>> On Thu, Jan 24, 2013 at 11:11:17AM +0000, Russell King - ARM Linux wrote:
>>>>> The OMAP4 randconfig build last night failed with this error:
>>>>>
>>>>> arch/arm/mach-zynq/common.c:99:14: error: 'irqchip_init' undeclared here (not in a function)
>>>>>
>>>>> Full details at the usual place -
>>>>> http://www.arm.linux.org.uk/developer/build/
>>>>
>>>> Curious. This doesn't look like a valid config to me.
>>>
>>> I think you're wrong.
>
> Yes, indeed. I was running my tests using the wrong tree. I can see
> this issue in today's linux-next. Sorry for the noise.
>
> [..]
>>
>> And what's missing is _specific_ to Zynq. Let's look at the error again:
>>
>> arch/arm/mach-zynq/common.c:99:14: error: 'irqchip_init' undeclared here (not in a function)
>>
>> What it means is that the "irqchip_init" identifier was not declared by
>> anything before it has been used. That means arch/arm/mach-zynq/common.c
>> is missing a required #include statement.
>>
>> irqchip_init can be found in linux/irqchip.h. Does arch/arm/mach-zynq/common.c
>> include this required include? No. Therefore, the build fails with the
>> above error.
>>
>> You need to add this include file...
>
> Agreed, thanks. Looks like this was introduced with "ARM: use common
> irqchip_init for GIC init". Here's a patch to fix it up, it probably
> makes sense to be pulled into Rob's irqchip/gic-vic-move branch.
Can you also add zynq to multi_v7_defconfig if that is not already
queued up.
Rob
^ permalink raw reply
* [PATCH v6 01/15] ARM: Add page table and page defines needed by KVM
From: Christoffer Dall @ 2013-01-24 17:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130124171349.GH18233@arm.com>
On Thu, Jan 24, 2013 at 12:13 PM, Catalin Marinas
<catalin.marinas@arm.com> wrote:
> On Thu, Jan 24, 2013 at 05:04:32PM +0000, Christoffer Dall wrote:
>> On Thu, Jan 24, 2013 at 12:02 PM, Catalin Marinas
>> <catalin.marinas@arm.com> wrote:
>> > On Thu, Jan 24, 2013 at 04:05:33PM +0000, Christoffer Dall wrote:
>> >> On Thu, Jan 24, 2013 at 6:39 AM, Catalin Marinas
>> >> <catalin.marinas@arm.com> wrote:
>> >> > On Wed, Jan 16, 2013 at 05:57:26PM +0000, Christoffer Dall wrote:
>> >> >> @@ -82,6 +85,10 @@ extern pgprot_t pgprot_kernel;
>> >> >> #define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
>> >> >> #define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN)
>> >> >> #define PAGE_KERNEL_EXEC pgprot_kernel
>> >> >> +#define PAGE_HYP _MOD_PROT(pgprot_kernel, L_PTE_HYP)
>> >> >> +#define PAGE_HYP_DEVICE _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
>> >> >> +#define PAGE_S2 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
>> >> >> +#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
>> >> >
>> >> > Are these S2 read-only by default?
>> >>
>> >> not sure I understand what you're asking here?
>> >
>> > Why do you pass L_PTE_S2_RDONLY? Do you need to restrict guest writes
>> > via the stage 2 attributes?
>> >
>> yes, for example when KSM merges two pages, then it must be mapped
>> read-only to the guest so that we catch writes and perform COW.
>
> OK, so you want the default to be read-only unless write access is
> required and you perform an 'or' with L_PTE_S2_RDWR. Sounds fine.
>
exactly, the specific pointer to the code is in line ~562 in arch/arm/kvm/mmu.c.
-Christoffer
^ permalink raw reply
* [BUG] snowball board locks up on boot
From: Steven Rostedt @ 2013-01-24 17:14 UTC (permalink / raw)
To: linux-arm-kernel
I tried to get my snowball board working on the latest kernel, but it
locks up hard very early on boot up.
I bisected it down to this commit:
commit ebc96db7632f987e0b9bffcb782cf5cfb8afb0dd
Author: Ulf Hansson <ulf.hansson@linaro.org>
Date: Mon Aug 27 15:45:53 2012 +0200
ARM: ux500: Switch to use common clock framework
Remove machine specific clock implementation and switch to use
new common clock framework.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
I reverted the change (tweaking it to get it to compile again), and sure
enough, I'm able to boot the board again.
I'm not sure what to do about this, but I wanted to let you know that
the common clock framework does not support my snowball board.
Below is the changes I made to get the board working on 3.8-rc4.
-- Steve
---
arch/arm/mach-ux500/Kconfig | 1
arch/arm/mach-ux500/Makefile | 2
arch/arm/mach-ux500/clock.c | 715 +++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-ux500/clock.h | 164 +++++++++
arch/arm/mach-ux500/cpu.c | 15
drivers/clk/Makefile | 1
6 files changed, 886 insertions(+), 12 deletions(-)
Index: arm-test.git/arch/arm/mach-ux500/Kconfig
===================================================================
--- arm-test.git.orig/arch/arm/mach-ux500/Kconfig 2013-01-24 11:29:36.000000000 -0500
+++ arm-test.git/arch/arm/mach-ux500/Kconfig 2013-01-24 11:30:28.574250603 -0500
@@ -8,7 +8,6 @@ config UX500_SOC_COMMON
select ARM_GIC
select CACHE_L2X0
select CLKSRC_NOMADIK_MTU
- select COMMON_CLK
select PINCTRL
select PINCTRL_NOMADIK
select PL310_ERRATA_753970 if CACHE_PL310
Index: arm-test.git/arch/arm/mach-ux500/Makefile
===================================================================
--- arm-test.git.orig/arch/arm/mach-ux500/Makefile 2013-01-24 10:33:45.000000000 -0500
+++ arm-test.git/arch/arm/mach-ux500/Makefile 2013-01-24 11:30:19.402046175 -0500
@@ -2,7 +2,7 @@
# Makefile for the linux kernel, U8500 machine.
#
-obj-y := cpu.o devices.o devices-common.o \
+obj-y := clock.o cpu.o devices.o devices-common.o \
id.o usb.o timer.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
Index: arm-test.git/arch/arm/mach-ux500/clock.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ arm-test.git/arch/arm/mach-ux500/clock.c 2013-01-24 11:52:41.083970656 -0500
@@ -0,0 +1,715 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ * Copyright (C) 2009 STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/cpufreq.h>
+
+//#include <plat/mtu.h>
+#include <mach/hardware.h>
+#include "clock.h"
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#include <linux/uaccess.h> /* for copy_from_user */
+static LIST_HEAD(clk_list);
+#endif
+
+#define PRCC_PCKEN 0x00
+#define PRCC_PCKDIS 0x04
+#define PRCC_KCKEN 0x08
+#define PRCC_KCKDIS 0x0C
+
+#define PRCM_YYCLKEN0_MGT_SET 0x510
+#define PRCM_YYCLKEN1_MGT_SET 0x514
+#define PRCM_YYCLKEN0_MGT_CLR 0x518
+#define PRCM_YYCLKEN1_MGT_CLR 0x51C
+#define PRCM_YYCLKEN0_MGT_VAL 0x520
+#define PRCM_YYCLKEN1_MGT_VAL 0x524
+
+#define PRCM_SVAMMDSPCLK_MGT 0x008
+#define PRCM_SIAMMDSPCLK_MGT 0x00C
+#define PRCM_SGACLK_MGT 0x014
+#define PRCM_UARTCLK_MGT 0x018
+#define PRCM_MSP02CLK_MGT 0x01C
+#define PRCM_MSP1CLK_MGT 0x288
+#define PRCM_I2CCLK_MGT 0x020
+#define PRCM_SDMMCCLK_MGT 0x024
+#define PRCM_SLIMCLK_MGT 0x028
+#define PRCM_PER1CLK_MGT 0x02C
+#define PRCM_PER2CLK_MGT 0x030
+#define PRCM_PER3CLK_MGT 0x034
+#define PRCM_PER5CLK_MGT 0x038
+#define PRCM_PER6CLK_MGT 0x03C
+#define PRCM_PER7CLK_MGT 0x040
+#define PRCM_LCDCLK_MGT 0x044
+#define PRCM_BMLCLK_MGT 0x04C
+#define PRCM_HSITXCLK_MGT 0x050
+#define PRCM_HSIRXCLK_MGT 0x054
+#define PRCM_HDMICLK_MGT 0x058
+#define PRCM_APEATCLK_MGT 0x05C
+#define PRCM_APETRACECLK_MGT 0x060
+#define PRCM_MCDECLK_MGT 0x064
+#define PRCM_IPI2CCLK_MGT 0x068
+#define PRCM_DSIALTCLK_MGT 0x06C
+#define PRCM_DMACLK_MGT 0x074
+#define PRCM_B2R2CLK_MGT 0x078
+#define PRCM_TVCLK_MGT 0x07C
+#define PRCM_TCR 0x1C8
+#define PRCM_TCR_STOPPED (1 << 16)
+#define PRCM_TCR_DOZE_MODE (1 << 17)
+#define PRCM_UNIPROCLK_MGT 0x278
+#define PRCM_SSPCLK_MGT 0x280
+#define PRCM_RNGCLK_MGT 0x284
+#define PRCM_UICCCLK_MGT 0x27C
+
+#define PRCM_MGT_ENABLE (1 << 8)
+
+static DEFINE_SPINLOCK(clocks_lock);
+
+static void __clk_enable(struct clk *clk)
+{
+ if (clk->enabled++ == 0) {
+ if (clk->parent_cluster)
+ __clk_enable(clk->parent_cluster);
+
+ if (clk->parent_periph)
+ __clk_enable(clk->parent_periph);
+
+ if (clk->ops && clk->ops->enable)
+ clk->ops->enable(clk);
+ }
+}
+
+int clk_enable(struct clk *clk)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ __clk_enable(clk);
+ spin_unlock_irqrestore(&clocks_lock, flags);
+
+ return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+static void __clk_disable(struct clk *clk)
+{
+ if (--clk->enabled == 0) {
+ if (clk->ops && clk->ops->disable)
+ clk->ops->disable(clk);
+
+ if (clk->parent_periph)
+ __clk_disable(clk->parent_periph);
+
+ if (clk->parent_cluster)
+ __clk_disable(clk->parent_cluster);
+ }
+}
+
+void clk_disable(struct clk *clk)
+{
+ unsigned long flags;
+
+ WARN_ON(!clk->enabled);
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ __clk_disable(clk);
+ spin_unlock_irqrestore(&clocks_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+/*
+ * The MTU has a separate, rather complex muxing setup
+ * with alternative parents (peripheral cluster or
+ * ULP or fixed 32768 Hz) depending on settings
+ */
+static unsigned long clk_mtu_get_rate(struct clk *clk)
+{
+ void __iomem *addr;
+ u32 tcr;
+ int mtu = (int) clk->data;
+ /*
+ * One of these is selected eventually
+ * TODO: Replace the constant with a reference
+ * to the ULP source once this is modeled.
+ */
+ unsigned long clk32k = 32768;
+ unsigned long mturate;
+ unsigned long retclk;
+
+ if (cpu_is_u8500_family())
+ addr = __io_address(U8500_PRCMU_BASE);
+ else
+ ux500_unknown_soc();
+
+ /*
+ * On a startup, always conifgure the TCR to the doze mode;
+ * bootloaders do it for us. Do this in the kernel too.
+ */
+ writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR);
+
+ tcr = readl(addr + PRCM_TCR);
+
+ /* Get the rate from the parent as a default */
+ if (clk->parent_periph)
+ mturate = clk_get_rate(clk->parent_periph);
+ else if (clk->parent_cluster)
+ mturate = clk_get_rate(clk->parent_cluster);
+ else
+ /* We need to be connected SOMEWHERE */
+ BUG();
+
+ /* Return the clock selected for this MTU */
+ if (tcr & (1 << mtu))
+ retclk = clk32k;
+ else
+ retclk = mturate;
+
+ pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
+ return retclk;
+}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ unsigned long rate;
+
+ /*
+ * If there is a custom getrate callback for this clock,
+ * it will take precedence.
+ */
+ if (clk->get_rate)
+ return clk->get_rate(clk);
+
+ if (clk->ops && clk->ops->get_rate)
+ return clk->ops->get_rate(clk);
+
+ rate = clk->rate;
+ if (!rate) {
+ if (clk->parent_periph)
+ rate = clk_get_rate(clk->parent_periph);
+ else if (clk->parent_cluster)
+ rate = clk_get_rate(clk->parent_cluster);
+ }
+
+ return rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+ /*TODO*/
+ return rate;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ clk->rate = rate;
+ return 0;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ /*TODO*/
+ return -ENOSYS;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+static void clk_prcmu_enable(struct clk *clk)
+{
+ void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
+ + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
+
+ writel(1 << clk->prcmu_cg_bit, cg_set_reg);
+}
+
+static void clk_prcmu_disable(struct clk *clk)
+{
+ void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
+ + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
+
+ writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
+}
+
+static struct clkops clk_prcmu_ops = {
+ .enable = clk_prcmu_enable,
+ .disable = clk_prcmu_disable,
+};
+
+static unsigned int clkrst_base[] = {
+ [1] = U8500_CLKRST1_BASE,
+ [2] = U8500_CLKRST2_BASE,
+ [3] = U8500_CLKRST3_BASE,
+ [5] = U8500_CLKRST5_BASE,
+ [6] = U8500_CLKRST6_BASE,
+};
+
+static void clk_prcc_enable(struct clk *clk)
+{
+ void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
+
+ if (clk->prcc_kernel != -1)
+ writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
+
+ if (clk->prcc_bus != -1)
+ writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
+}
+
+static void clk_prcc_disable(struct clk *clk)
+{
+ void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
+
+ if (clk->prcc_bus != -1)
+ writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
+
+ if (clk->prcc_kernel != -1)
+ writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
+}
+
+static struct clkops clk_prcc_ops = {
+ .enable = clk_prcc_enable,
+ .disable = clk_prcc_disable,
+};
+
+static struct clk clk_32khz = {
+ .name = "clk_32khz",
+ .rate = 32000,
+};
+
+/*
+ * PRCMU level clock gating
+ */
+
+/* Bank 0 */
+static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK);
+static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK);
+static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK);
+static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000);
+static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK);
+static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */
+static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000);
+static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 100000000);
+static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK);
+static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK);
+static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
+static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK);
+static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK);
+static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000);
+static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK);
+static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK);
+static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK);
+static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK);
+static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK);
+static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK);
+static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK);
+static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK);
+static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK);
+static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */
+static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK);
+static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK);
+static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK);
+static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */
+static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */
+
+/* Bank 1 */
+static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */
+static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
+
+/*
+ * PRCC level clock gating
+ * Format: per#, clk, PCKEN bit, KCKEN bit, parent
+ */
+
+/* Peripheral Cluster #1 */
+static DEFINE_PRCC_CLK(1, msp3, 11, 10, &clk_msp1clk);
+static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
+static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
+static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
+static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL);
+static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk);
+static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk);
+static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk);
+static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk);
+static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk);
+static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk);
+
+/* Peripheral Cluster #2 */
+static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL);
+static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL);
+static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL);
+static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL);
+static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk);
+static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL);
+static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL);
+static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL);
+static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk);
+
+/* Peripheral Cluster #3 */
+static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL);
+static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk);
+static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz);
+static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk);
+static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk);
+static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk);
+static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL);
+
+/* Peripheral Cluster #4 is in the always on domain */
+
+/* Peripheral Cluster #5 */
+static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL);
+static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL);
+
+/* Peripheral Cluster #6 */
+
+/* MTU ID in data */
+static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1);
+static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0);
+static DEFINE_PRCC_CLK(6, cfgreg, 7, 7, NULL);
+static DEFINE_PRCC_CLK(6, hash1, 6, -1, NULL);
+static DEFINE_PRCC_CLK(6, unipro, 5, 1, &clk_uniproclk);
+static DEFINE_PRCC_CLK(6, pka, 4, -1, NULL);
+static DEFINE_PRCC_CLK(6, hash0, 3, -1, NULL);
+static DEFINE_PRCC_CLK(6, cryp0, 2, -1, NULL);
+static DEFINE_PRCC_CLK(6, cryp1, 1, -1, NULL);
+static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk);
+
+static struct clk clk_dummy_apb_pclk = {
+ .name = "apb_pclk",
+};
+
+static struct clk_lookup u8500_clks[] = {
+ CLK(dummy_apb_pclk, NULL, "apb_pclk"),
+
+ /* Peripheral Cluster #1 */
+ CLK(gpio0, "gpio.0", NULL),
+ CLK(gpio0, "gpio.1", NULL),
+ CLK(slimbus0, "slimbus0", NULL),
+ CLK(i2c2, "nmk-i2c.2", NULL),
+ CLK(sdi0, "sdi0", NULL),
+ CLK(msp0, "ux500-msp-i2s.0", NULL),
+ CLK(i2c1, "nmk-i2c.1", NULL),
+ CLK(uart1, "uart1", NULL),
+ CLK(uart0, "uart0", NULL),
+
+ /* Peripheral Cluster #3 */
+ CLK(gpio2, "gpio.2", NULL),
+ CLK(gpio2, "gpio.3", NULL),
+ CLK(gpio2, "gpio.4", NULL),
+ CLK(gpio2, "gpio.5", NULL),
+ CLK(sdi5, "sdi5", NULL),
+ CLK(uart2, "uart2", NULL),
+ CLK(ske, "ske", NULL),
+ CLK(ske, "nmk-ske-keypad", NULL),
+ CLK(sdi2, "sdi2", NULL),
+ CLK(i2c0, "nmk-i2c.0", NULL),
+ CLK(fsmc, "fsmc", NULL),
+
+ /* Peripheral Cluster #5 */
+ CLK(gpio3, "gpio.8", NULL),
+
+ /* Peripheral Cluster #6 */
+ CLK(hash1, "hash1", NULL),
+ CLK(pka, "pka", NULL),
+ CLK(hash0, "hash0", NULL),
+ CLK(cryp0, "cryp0", NULL),
+ CLK(cryp1, "cryp1", NULL),
+
+ /* PRCMU level clock gating */
+
+ /* Bank 0 */
+ CLK(svaclk, "sva", NULL),
+ CLK(siaclk, "sia", NULL),
+ CLK(sgaclk, "sga", NULL),
+ CLK(slimclk, "slim", NULL),
+ CLK(lcdclk, "lcd", NULL),
+ CLK(bmlclk, "bml", NULL),
+ CLK(hsitxclk, "stm-hsi.0", NULL),
+ CLK(hsirxclk, "stm-hsi.1", NULL),
+ CLK(hdmiclk, "hdmi", NULL),
+ CLK(apeatclk, "apeat", NULL),
+ CLK(apetraceclk, "apetrace", NULL),
+ CLK(mcdeclk, "mcde", NULL),
+ CLK(ipi2clk, "ipi2", NULL),
+ CLK(dmaclk, "dma40.0", NULL),
+ CLK(b2r2clk, "b2r2", NULL),
+ CLK(tvclk, "tv", NULL),
+
+ /* Peripheral Cluster #1 */
+ CLK(i2c4, "nmk-i2c.4", NULL),
+ CLK(spi3, "spi3", NULL),
+ CLK(msp1, "ux500-msp-i2s.1", NULL),
+ CLK(msp3, "ux500-msp-i2s.3", NULL),
+
+ /* Peripheral Cluster #2 */
+ CLK(gpio1, "gpio.6", NULL),
+ CLK(gpio1, "gpio.7", NULL),
+ CLK(ssitx, "ssitx", NULL),
+ CLK(ssirx, "ssirx", NULL),
+ CLK(spi0, "spi0", NULL),
+ CLK(sdi3, "sdi3", NULL),
+ CLK(sdi1, "sdi1", NULL),
+ CLK(msp2, "ux500-msp-i2s.2", NULL),
+ CLK(sdi4, "sdi4", NULL),
+ CLK(pwl, "pwl", NULL),
+ CLK(spi1, "spi1", NULL),
+ CLK(spi2, "spi2", NULL),
+ CLK(i2c3, "nmk-i2c.3", NULL),
+
+ /* Peripheral Cluster #3 */
+ CLK(ssp1, "ssp1", NULL),
+ CLK(ssp0, "ssp0", NULL),
+
+ /* Peripheral Cluster #5 */
+ CLK(usb, "musb-ux500.0", "usb"),
+
+ /* Peripheral Cluster #6 */
+ CLK(mtu1, "mtu1", NULL),
+ CLK(mtu0, "mtu0", NULL),
+ CLK(cfgreg, "cfgreg", NULL),
+ CLK(hash1, "hash1", NULL),
+ CLK(unipro, "unipro", NULL),
+ CLK(rng, "rng", NULL),
+
+ /* PRCMU level clock gating */
+
+ /* Bank 0 */
+ CLK(uniproclk, "uniproclk", NULL),
+ CLK(dsialtclk, "dsialt", NULL),
+
+ /* Bank 1 */
+ CLK(rngclk, "rng", NULL),
+ CLK(uiccclk, "uicc", NULL),
+};
+
+#ifdef CONFIG_DEBUG_FS
+/*
+ * debugfs support to trace clock tree hierarchy and attributes with
+ * powerdebug
+ */
+static struct dentry *clk_debugfs_root;
+
+void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num)
+{
+ while (num--) {
+ /* Check that the clock has not been already registered */
+ if (!(cl->clk->list.prev != cl->clk->list.next))
+ list_add_tail(&cl->clk->list, &clk_list);
+
+ cl++;
+ }
+}
+
+static ssize_t usecount_dbg_read(struct file *file, char __user *buf,
+ size_t size, loff_t *off)
+{
+ struct clk *clk = file->f_dentry->d_inode->i_private;
+ char cusecount[128];
+ unsigned int len;
+
+ len = sprintf(cusecount, "%u\n", clk->enabled);
+ return simple_read_from_buffer(buf, size, off, cusecount, len);
+}
+
+static ssize_t rate_dbg_read(struct file *file, char __user *buf,
+ size_t size, loff_t *off)
+{
+ struct clk *clk = file->f_dentry->d_inode->i_private;
+ char crate[128];
+ unsigned int rate;
+ unsigned int len;
+
+ rate = clk_get_rate(clk);
+ len = sprintf(crate, "%u\n", rate);
+ return simple_read_from_buffer(buf, size, off, crate, len);
+}
+
+static const struct file_operations usecount_fops = {
+ .read = usecount_dbg_read,
+};
+
+static const struct file_operations set_rate_fops = {
+ .read = rate_dbg_read,
+};
+
+static struct dentry *clk_debugfs_register_dir(struct clk *c,
+ struct dentry *p_dentry)
+{
+ struct dentry *d, *clk_d;
+ const char *p = c->name;
+
+ if (!p)
+ p = "BUG";
+
+ clk_d = debugfs_create_dir(p, p_dentry);
+ if (!clk_d)
+ return NULL;
+
+ d = debugfs_create_file("usecount", S_IRUGO,
+ clk_d, c, &usecount_fops);
+ if (!d)
+ goto err_out;
+ d = debugfs_create_file("rate", S_IRUGO,
+ clk_d, c, &set_rate_fops);
+ if (!d)
+ goto err_out;
+ /*
+ * TODO : not currently available in ux500
+ * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags);
+ * if (!d)
+ * goto err_out;
+ */
+
+ return clk_d;
+
+err_out:
+ debugfs_remove_recursive(clk_d);
+ return NULL;
+}
+
+static int clk_debugfs_register_one(struct clk *c)
+{
+ struct clk *pa = c->parent_periph;
+ struct clk *bpa = c->parent_cluster;
+
+ if (!(bpa && !pa)) {
+ c->dent = clk_debugfs_register_dir(c,
+ pa ? pa->dent : clk_debugfs_root);
+ if (!c->dent)
+ return -ENOMEM;
+ }
+
+ if (bpa) {
+ c->dent_bus = clk_debugfs_register_dir(c,
+ bpa->dent_bus ? bpa->dent_bus : bpa->dent);
+ if ((!c->dent_bus) && (c->dent)) {
+ debugfs_remove_recursive(c->dent);
+ c->dent = NULL;
+ return -ENOMEM;
+ }
+ }
+ return 0;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+ int err;
+ struct clk *pa = c->parent_periph;
+ struct clk *bpa = c->parent_cluster;
+
+ if (pa && (!pa->dent && !pa->dent_bus)) {
+ err = clk_debugfs_register(pa);
+ if (err)
+ return err;
+ }
+
+ if (bpa && (!bpa->dent && !bpa->dent_bus)) {
+ err = clk_debugfs_register(bpa);
+ if (err)
+ return err;
+ }
+
+ if ((!c->dent) && (!c->dent_bus)) {
+ err = clk_debugfs_register_one(c);
+ if (err)
+ return err;
+ }
+ return 0;
+}
+
+int __init clk_debugfs_init(void)
+{
+ struct clk *c;
+ struct dentry *d;
+ int err;
+
+ d = debugfs_create_dir("clock", NULL);
+ if (!d)
+ return -ENOMEM;
+ clk_debugfs_root = d;
+
+ list_for_each_entry(c, &clk_list, list) {
+ err = clk_debugfs_register(c);
+ if (err)
+ goto err_out;
+ }
+ return 0;
+err_out:
+ debugfs_remove_recursive(clk_debugfs_root);
+ return err;
+}
+
+#endif /* defined(CONFIG_DEBUG_FS) */
+
+unsigned long clk_smp_twd_rate = 500000000;
+
+unsigned long clk_smp_twd_get_rate(struct clk *clk)
+{
+ return clk_smp_twd_rate;
+}
+
+static struct clk clk_smp_twd = {
+ .get_rate = clk_smp_twd_get_rate,
+ .name = "smp_twd",
+};
+
+static struct clk_lookup clk_smp_twd_lookup = {
+ .dev_id = "smp_twd",
+ .clk = &clk_smp_twd,
+};
+
+#ifdef CONFIG_CPU_FREQ
+
+static int clk_twd_cpufreq_transition(struct notifier_block *nb,
+ unsigned long state, void *data)
+{
+ struct cpufreq_freqs *f = data;
+
+ if (state == CPUFREQ_PRECHANGE) {
+ /* Save frequency in simple Hz */
+ clk_smp_twd_rate = (f->new * 1000) / 2;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block clk_twd_cpufreq_nb = {
+ .notifier_call = clk_twd_cpufreq_transition,
+};
+
+int clk_init_smp_twd_cpufreq(void)
+{
+ return cpufreq_register_notifier(&clk_twd_cpufreq_nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+#endif
+
+int __init clk_init(void)
+{
+ clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
+ clkdev_add(&clk_smp_twd_lookup);
+
+#ifdef CONFIG_DEBUG_FS
+ clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
+#endif
+ return 0;
+}
Index: arm-test.git/arch/arm/mach-ux500/clock.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ arm-test.git/arch/arm/mach-ux500/clock.h 2013-01-24 11:30:19.402046175 -0500
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson
+ * Copyright (C) 2009 STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/**
+ * struct clkops - ux500 clock operations
+ * @enable: function to enable the clock
+ * @disable: function to disable the clock
+ * @get_rate: function to get the current clock rate
+ *
+ * This structure contains function pointers to functions that will be used to
+ * control the clock. All of these functions are optional. If get_rate is
+ * NULL, the rate in the struct clk will be used.
+ */
+struct clkops {
+ void (*enable) (struct clk *);
+ void (*disable) (struct clk *);
+ unsigned long (*get_rate) (struct clk *);
+ int (*set_parent)(struct clk *, struct clk *);
+};
+
+/**
+ * struct clk - ux500 clock structure
+ * @ops: pointer to clkops struct used to control this clock
+ * @name: name, for debugging
+ * @enabled: refcount. positive if enabled, zero if disabled
+ * @get_rate: custom callback for getting the clock rate
+ * @data: custom per-clock data for example for the get_rate
+ * callback
+ * @rate: fixed rate for clocks which don't implement
+ * ops->getrate
+ * @prcmu_cg_off: address offset of the combined enable/disable register
+ * (used on u8500v1)
+ * @prcmu_cg_bit: bit in the combined enable/disable register (used on
+ * u8500v1)
+ * @prcmu_cg_mgt: address of the enable/disable register (used on
+ * u8500ed)
+ * @cluster: peripheral cluster number
+ * @prcc_bus: bit for the bus clock in the peripheral's CLKRST
+ * @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST.
+ * -1 if no kernel clock exists.
+ * @parent_cluster: pointer to parent's cluster clk struct
+ * @parent_periph: pointer to parent's peripheral clk struct
+ *
+ * Peripherals are organised into clusters, and each cluster has an associated
+ * bus clock. Some peripherals also have a parent peripheral clock.
+ *
+ * In order to enable a clock for a peripheral, we need to enable:
+ * (1) the parent cluster (bus) clock at the PRCMU level
+ * (2) the parent peripheral clock (if any) at the PRCMU level
+ * (3) the peripheral's bus & kernel clock at the PRCC level
+ *
+ * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each
+ * of the cluster and peripheral clocks, and hooking these as the parents of
+ * the individual peripheral clocks.
+ *
+ * (3) is handled by specifying the bits in the PRCC control registers required
+ * to enable these clocks and modifying them in the ->enable and
+ * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK).
+ *
+ * This structure describes both the PRCMU-level clocks and PRCC-level clocks.
+ * The prcmu_* fields are only used for the PRCMU clocks, and the cluster,
+ * prcc, and parent pointers are only used for the PRCC-level clocks.
+ */
+struct clk {
+ const struct clkops *ops;
+ const char *name;
+ unsigned int enabled;
+ unsigned long (*get_rate)(struct clk *);
+ void *data;
+
+ unsigned long rate;
+ struct list_head list;
+
+ /* These three are only for PRCMU clks */
+
+ unsigned int prcmu_cg_off;
+ unsigned int prcmu_cg_bit;
+ unsigned int prcmu_cg_mgt;
+
+ /* The rest are only for PRCC clks */
+
+ int cluster;
+ unsigned int prcc_bus;
+ unsigned int prcc_kernel;
+
+ struct clk *parent_cluster;
+ struct clk *parent_periph;
+#if defined(CONFIG_DEBUG_FS)
+ struct dentry *dent; /* For visible tree hierarchy */
+ struct dentry *dent_bus; /* For visible tree hierarchy */
+#endif
+};
+
+#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \
+struct clk clk_##_name = { \
+ .name = #_name, \
+ .ops = &clk_prcmu_ops, \
+ .prcmu_cg_off = _cg_off, \
+ .prcmu_cg_bit = _cg_bit, \
+ .prcmu_cg_mgt = PRCM_##_reg##_MGT \
+ }
+
+#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \
+struct clk clk_##_name = { \
+ .name = #_name, \
+ .ops = &clk_prcmu_ops, \
+ .prcmu_cg_off = _cg_off, \
+ .prcmu_cg_bit = _cg_bit, \
+ .rate = _rate, \
+ .prcmu_cg_mgt = PRCM_##_reg##_MGT \
+ }
+
+#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \
+struct clk clk_##_name = { \
+ .name = #_name, \
+ .ops = &clk_prcc_ops, \
+ .cluster = _pclust, \
+ .prcc_bus = _bus_en, \
+ .prcc_kernel = _kernel_en, \
+ .parent_cluster = &clk_per##_pclust##clk, \
+ .parent_periph = _kernclk \
+ }
+
+#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \
+struct clk clk_##_name = { \
+ .name = #_name, \
+ .ops = &clk_prcc_ops, \
+ .cluster = _pclust, \
+ .prcc_bus = _bus_en, \
+ .prcc_kernel = _kernel_en, \
+ .parent_cluster = &clk_per##_pclust##clk, \
+ .parent_periph = _kernclk, \
+ .get_rate = _callback, \
+ .data = (void *) _data \
+ }
+
+
+#define CLK(_clk, _devname, _conname) \
+ { \
+ .clk = &clk_##_clk, \
+ .dev_id = _devname, \
+ .con_id = _conname, \
+ }
+
+int __init clk_db8500_ed_fixup(void);
+int __init clk_init(void);
+
+#ifdef CONFIG_DEBUG_FS
+int clk_debugfs_init(void);
+#else
+static inline int clk_debugfs_init(void) { return 0; }
+#endif
+
+#ifdef CONFIG_CPU_FREQ
+int clk_init_smp_twd_cpufreq(void);
+#else
+static inline int clk_init_smp_twd_cpufreq(void) { return 0; }
+#endif
Index: arm-test.git/arch/arm/mach-ux500/cpu.c
===================================================================
--- arm-test.git.orig/arch/arm/mach-ux500/cpu.c 2013-01-24 11:26:15.000000000 -0500
+++ arm-test.git/arch/arm/mach-ux500/cpu.c 2013-01-24 11:40:20.547446502 -0500
@@ -8,6 +8,7 @@
#include <linux/platform_device.h>
#include <linux/io.h>
+#include <linux/clk.h>
#include <linux/mfd/db8500-prcmu.h>
#include <linux/clksrc-dbx500-prcmu.h>
#include <linux/sys_soc.h>
@@ -17,7 +18,6 @@
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/irq.h>
-#include <linux/platform_data/clk-ux500.h>
#include <asm/hardware/gic.h>
#include <asm/mach/map.h>
@@ -28,6 +28,8 @@
#include "board-mop500.h"
+#include "clock.h"
+
void __iomem *_PRCMU_BASE;
/*
@@ -73,18 +75,13 @@ void __init ux500_init_irq(void)
*/
if (cpu_is_u8500_family())
db8500_prcmu_early_init();
-
- if (cpu_is_u8500_family())
- u8500_clk_init();
- else if (cpu_is_u9540())
- u9540_clk_init();
- else if (cpu_is_u8540())
- u8540_clk_init();
+ clk_init();
}
void __init ux500_init_late(void)
{
- mop500_uib_init();
+ clk_debugfs_init();
+ clk_init_smp_twd_cpufreq();
}
static const char * __init ux500_get_machine(void)
Index: arm-test.git/drivers/clk/Makefile
===================================================================
--- arm-test.git.orig/drivers/clk/Makefile 2013-01-24 11:29:36.000000000 -0500
+++ arm-test.git/drivers/clk/Makefile 2013-01-24 11:32:35.297073843 -0500
@@ -18,7 +18,6 @@ ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP) += mmp/
endif
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
-obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o
obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
^ permalink raw reply
* [PATCH v6 00/15] KVM/ARM Implementation
From: Gleb Natapov @ 2013-01-24 17:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130124162627.GE18233@arm.com>
On Thu, Jan 24, 2013 at 04:26:28PM +0000, Catalin Marinas wrote:
> Hi Christoffer,
>
> On Wed, Jan 16, 2013 at 05:57:19PM +0000, Christoffer Dall wrote:
> > The following series implements KVM support for ARM processors,
> > specifically on the Cortex A-15 platform.
>
> I went through the KVM patches (just this series, not the vgic or
> timers) and apart from a few minor clean-up issues (which can be done
> later as an additional patch) they look fine to me.
>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Same here. Reviewed the patch series from KVM perspective. There are
improvements that can be done to vcpu run loop, but nothing that should
prevent this series from going in.
Reviewed-by: Gleb Natapov <gleb@redhat.com>
--
Gleb.
^ permalink raw reply
* [PATCH v6 01/15] ARM: Add page table and page defines needed by KVM
From: Catalin Marinas @ 2013-01-24 17:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANM98q+mmU4R1yQ7mnp_QynhX4mbBiViP96FMjSob=fzAHLp6Q@mail.gmail.com>
On Thu, Jan 24, 2013 at 05:04:32PM +0000, Christoffer Dall wrote:
> On Thu, Jan 24, 2013 at 12:02 PM, Catalin Marinas
> <catalin.marinas@arm.com> wrote:
> > On Thu, Jan 24, 2013 at 04:05:33PM +0000, Christoffer Dall wrote:
> >> On Thu, Jan 24, 2013 at 6:39 AM, Catalin Marinas
> >> <catalin.marinas@arm.com> wrote:
> >> > On Wed, Jan 16, 2013 at 05:57:26PM +0000, Christoffer Dall wrote:
> >> >> @@ -82,6 +85,10 @@ extern pgprot_t pgprot_kernel;
> >> >> #define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
> >> >> #define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN)
> >> >> #define PAGE_KERNEL_EXEC pgprot_kernel
> >> >> +#define PAGE_HYP _MOD_PROT(pgprot_kernel, L_PTE_HYP)
> >> >> +#define PAGE_HYP_DEVICE _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
> >> >> +#define PAGE_S2 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
> >> >> +#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
> >> >
> >> > Are these S2 read-only by default?
> >>
> >> not sure I understand what you're asking here?
> >
> > Why do you pass L_PTE_S2_RDONLY? Do you need to restrict guest writes
> > via the stage 2 attributes?
> >
> yes, for example when KSM merges two pages, then it must be mapped
> read-only to the guest so that we catch writes and perform COW.
OK, so you want the default to be read-only unless write access is
required and you perform an 'or' with L_PTE_S2_RDWR. Sounds fine.
--
Catalin
^ permalink raw reply
* [PATCH v6 02/15] ARM: Section based HYP idmap
From: Christoffer Dall @ 2013-01-24 17:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130124170520.GG18233@arm.com>
On Thu, Jan 24, 2013 at 12:05 PM, Catalin Marinas
<catalin.marinas@arm.com> wrote:
> On Thu, Jan 24, 2013 at 04:36:09PM +0000, Christoffer Dall wrote:
>> On Thu, Jan 24, 2013 at 9:32 AM, Catalin Marinas
>> <catalin.marinas@arm.com> wrote:
>> > On Wed, Jan 16, 2013 at 05:57:34PM +0000, Christoffer Dall wrote:
>> >> --- a/arch/arm/mm/idmap.c
>> >> +++ b/arch/arm/mm/idmap.c
>> >> @@ -1,4 +1,6 @@
>> >> +#include <linux/module.h>
>> >
>> > Minor thing - do you need to include linux/module.h here?
>> >
>>
>> there was once a time when kvm/arm could be compiled as a module; my
>> best guess is that it's a leftover from that.
>>
>> >> + identity_mapping_add(hyp_pgd, __hyp_idmap_text_start,
>> >> + __hyp_idmap_text_end, PMD_SECT_AP1);
>> >
>> > It would be more consistent if you define PMD_SECT_HYP or something like
>> > that. I think you have a L_PTE_HYP bit as well.
>> >
>> Is this along the lines of what you had in mind?
>>
>> diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h
>> b/arch/arm/include/asm/pgtable-3level-hwdef.h
>> index 18f5cef..432fa12 100644
>> --- a/arch/arm/include/asm/pgtable-3level-hwdef.h
>> +++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
>> @@ -50,6 +50,7 @@
>> #define PMD_SECT_AP_READ (_AT(pmdval_t, 0))
>> #define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6)
>> #define PMD_SECT_TEX(x) (_AT(pmdval_t, 0))
>> +#define PMD_SECT_HYP PMD_SECT_AP1
>>
>> /*
>> * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
>> diff --git a/arch/arm/include/asm/pgtable-3level.h
>> b/arch/arm/include/asm/pgtable-3level.h
>> index 6ef8afd..a7e6532 100644
>> --- a/arch/arm/include/asm/pgtable-3level.h
>> +++ b/arch/arm/include/asm/pgtable-3level.h
>> @@ -116,6 +116,7 @@
>> /*
>> * Hyp-mode PL2 PTE definitions for LPAE.
>> */
>> +#define PMD_HYP PMD_SECT_AP1
>
> Yes, but only one definition in is probably enough (PMD_SECT_HYP?).
>
yeah, that one was not supposed to be included in my git add command, whoops:
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h
b/arch/arm/include/asm/pgtable-3level-hwdef.h
index 18f5cef..432fa12 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -50,6 +50,7 @@
#define PMD_SECT_AP_READ (_AT(pmdval_t, 0))
#define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6)
#define PMD_SECT_TEX(x) (_AT(pmdval_t, 0))
+#define PMD_SECT_HYP PMD_SECT_AP1
/*
* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index 2dffc01..bf1ee20 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -1,4 +1,3 @@
-#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
@@ -97,7 +96,7 @@ static int __init init_static_idmap_hyp(void)
pr_info("Setting up static HYP identity map for 0x%p - 0x%p\n",
__hyp_idmap_text_start, __hyp_idmap_text_end);
identity_mapping_add(hyp_pgd, __hyp_idmap_text_start,
- __hyp_idmap_text_end, PMD_SECT_AP1);
+ __hyp_idmap_text_end, PMD_SECT_HYP);
return 0;
}
--
Thanks, I'll queue these and send them after the other patch series
has been merged.
-Christoffer
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: omap3-overo: Add support for pwm-leds
From: Peter Ujfalusi @ 2013-01-24 17:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5101663C.7020301@epfl.ch>
On 01/24/2013 05:50 PM, Florian Vaussard wrote:
>>> I did it at first, but the led API executes in atomic context, where the
>>> pwm-twl-led driver uses i2c communication. Setting a trigger will result in a
>>> kernel panic.
>>
>> Now that you mentioned it, this might be true.
>>
>
> [<c0013204>] (unwind_backtrace+0x0/0xec) from [<c00348ac>]
> (warn_slowpath_common+0x4c/0x64)
> [<c00348ac>] (warn_slowpath_common+0x4c/0x64) from [<c00348e0>]
> (warn_slowpath_null+0x1c/0x24)
> [<c00348e0>] (warn_slowpath_null+0x1c/0x24) from [<c054d384>]
> (__mutex_lock_slowpath+0x6c/0x26c)
> [<c054d384>] (__mutex_lock_slowpath+0x6c/0x26c) from [<c054d590>]
> (mutex_lock+0xc/0x20)
> [<c054d590>] (mutex_lock+0xc/0x20) from [<c02d740c>]
> (regmap_bulk_write+0x48/0x138)
> [<c02d740c>] (regmap_bulk_write+0x48/0x138) from [<c02de2c0>]
> (twl_i2c_write+0xa4/0xf0)
> [<c02de2c0>] (twl_i2c_write+0xa4/0xf0) from [<c0299e34>]
> (twl4030_pwmled_config+0x70/0x9c)
> [<c0299e34>] (twl4030_pwmled_config+0x70/0x9c) from [<c029875c>]
> (pwm_config+0x5c/0x6c)
> [<c029875c>] (pwm_config+0x5c/0x6c) from [<c039dc04>] (led_pwm_set+0x28/0x64)
> [<c039dc04>] (led_pwm_set+0x28/0x64) from [<c039e27c>]
> (led_heartbeat_function+0x10c/0x134)
> [<c039e27c>] (led_heartbeat_function+0x10c/0x134) from [<c004359c>]
> (call_timer_fn+0x90/0x178)
> [<c004359c>] (call_timer_fn+0x90/0x178) from [<c0043994>]
> (run_timer_softirq+0x250/0x2c8)
> [<c0043994>] (run_timer_softirq+0x250/0x2c8) from [<c003cf78>]
> (__do_softirq+0xf8/0x248)
> [<c003cf78>] (__do_softirq+0xf8/0x248) from [<c003d154>] (irq_exit+0x44/0x98)
> [<c003d154>] (irq_exit+0x44/0x98) from [<c000e338>] (handle_IRQ+0x68/0x8c)
> [<c000e338>] (handle_IRQ+0x68/0x8c) from [<c000870c>]
> (omap3_intc_handle_irq+0x58/0x70)
> [<c000870c>] (omap3_intc_handle_irq+0x58/0x70) from [<c054f8c0>]
> (__irq_svc+0x40/0x70)
> Exception stack(0xc077df60 to 0xc077dfa8)
>
> :-)
>
>>> I am working on a patch for pwm-twl-led to defer using a workqueue right now.
>>
>> Great!
>> The only thing I worry about is the latency we are going to get with the
>> workqueue.
>>
>
> If the latency becomes critical, we can create our own workqueue.
Hrm, when we handled the led via gpio-leds it was also going through the same
path at the end, via i2c to twl4030.
I think the fix for this is going to be needed in the pwm core level. Just
need to look at the gpio code to have similar handling of might_sleep interfaces.
> Do we merge anyway this patchset, or do we wait until the trigger has been fixed?
I think it can go and later when we have the fix for the slow path you can add
the default trigger.
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
^ permalink raw reply
* OMAP4 randconfig failure: Zynq
From: Josh Cartwright @ 2013-01-24 17:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130124161211.GX23505@n2100.arm.linux.org.uk>
On Thu, Jan 24, 2013 at 04:12:11PM +0000, Russell King - ARM Linux wrote:
> On Thu, Jan 24, 2013 at 04:06:09PM +0000, Russell King - ARM Linux wrote:
> > On Thu, Jan 24, 2013 at 09:57:04AM -0600, Josh Cartwright wrote:
> > > On Thu, Jan 24, 2013 at 11:11:17AM +0000, Russell King - ARM Linux wrote:
> > > > The OMAP4 randconfig build last night failed with this error:
> > > >
> > > > arch/arm/mach-zynq/common.c:99:14: error: 'irqchip_init' undeclared here (not in a function)
> > > >
> > > > Full details at the usual place -
> > > > http://www.arm.linux.org.uk/developer/build/
> > >
> > > Curious. This doesn't look like a valid config to me.
> >
> > I think you're wrong.
Yes, indeed. I was running my tests using the wrong tree. I can see
this issue in today's linux-next. Sorry for the noise.
[..]
>
> And what's missing is _specific_ to Zynq. Let's look at the error again:
>
> arch/arm/mach-zynq/common.c:99:14: error: 'irqchip_init' undeclared here (not in a function)
>
> What it means is that the "irqchip_init" identifier was not declared by
> anything before it has been used. That means arch/arm/mach-zynq/common.c
> is missing a required #include statement.
>
> irqchip_init can be found in linux/irqchip.h. Does arch/arm/mach-zynq/common.c
> include this required include? No. Therefore, the build fails with the
> above error.
>
> You need to add this include file...
Agreed, thanks. Looks like this was introduced with "ARM: use common
irqchip_init for GIC init". Here's a patch to fix it up, it probably
makes sense to be pulled into Rob's irqchip/gic-vic-move branch.
-- 8< --
Subject: [PATCH] ARM: zynq: include irqchip.h to prevent build failure
Commit 0529e315bbda5d502c93df2cfafba9bb337fbdf4 ("ARM: use common irqchip_init
for GIC init") converts Zynq to make use of irqchip_init, but fails to
include linux/irqchip.h. Fixes this build error:
arch/arm/mach-zynq/common.c:99:14: error: 'irqchip_init' undeclared here (not in a function)
Reported-by: Russell King <linux@arm.linux.org.uk>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
---
arch/arm/mach-zynq/common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 8513b16..8a0b8ab 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -20,6 +20,7 @@
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/clk/zynq.h>
+#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
--
1.8.1.1
^ permalink raw reply related
* [PATCH v2 1/2] clk: divider: prepare for minimum divider
From: Mike Turquette @ 2013-01-24 17:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A93EA92ABC@DBDE01.ent.ti.com>
Quoting Mohammed, Afzal (2013-01-24 03:29:15)
> Hi Mike,
>
> On Thu, Jan 24, 2013 at 03:10:53, Mike Turquette wrote:
> > Quoting Afzal Mohammed (2013-01-23 03:38:52)
>
> > > Some of clocks can have a limit on minimum divider value that can be
> > > programmed, prepare for such a support.
>
> > > Add a new field min_div for the basic divider clock and a new dynamic
> > > clock divider registration function where minimum divider value can
> > > be specified. Keep behaviour of existing divider clock registration
> > > functions, static initialization helpers as was earlier.
>
> > My first question is whether the minimum divider you plan to use is an
> > actual constraint of the hardware (e.g. the clock controller ip only
> > lets program two bits which divide by 4, 5, 6 or 7, where 4 is the
> > minimum divider) or if this is a functional constraint (e.g. the clock
> > hardware can divide by a lower value, but you never want that since it
> > results in non-functional video/audio/whatever). If this is more of a
> > functional constraint then perhaps a new api like clk_set_min_rate makes
> > more sense.
>
> It is a functional constraint: divider has 8 bits and it can have
> all possible values (0 to 255) and divider value corresponds to
> value set in the 8 bits. But depending on the modes the minimum
> value that can be configured (to get display working) varies.
> Eg. For raster mode (which the driver is presently supporting), it
> can take a minimum value of 2, while in LIDD (LCD interface display
> driver) mode it can take a min value of 1.
>
> Here min rate is not a constraint w.r.t divider in LCDC IP, but
> rather min divider.
>
Just so I understand correctly... you are saying that the functional
constraint is not caused by the clock rate, but instead by the divider
value? For the different modes (raster vs LIDD) is the clock rate the
same, or is the clock rate different?
What is the clock output rate of the divider in raster mode? What is
the clock output rate of the divider in LIDD mode?
Thanks,
Mike
> As it is the case, you prefer a clk_divider_set_min_div()?
>
> >
> > Secondly, have you looked into using the rate-table option provided by
> > the basic divider clock? Can you explain how this is not a good fit for
> > your needs? Perhaps there are too many divisor values so the table
> > would be large?
>
> Divider values can range from 2-255 (254 possible values), so I believe
> it is not a suitable candidate here (also divider to values have 1-to-1
> mapping)
>
> Regards
> Afzal
^ permalink raw reply
* [PATCH v6 02/15] ARM: Section based HYP idmap
From: Catalin Marinas @ 2013-01-24 17:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANM98qJfxsXtQwjpMw5m8FEM2awtkCg-hZXa_Qrk7=jb3pqFAQ@mail.gmail.com>
On Thu, Jan 24, 2013 at 04:36:09PM +0000, Christoffer Dall wrote:
> On Thu, Jan 24, 2013 at 9:32 AM, Catalin Marinas
> <catalin.marinas@arm.com> wrote:
> > On Wed, Jan 16, 2013 at 05:57:34PM +0000, Christoffer Dall wrote:
> >> --- a/arch/arm/mm/idmap.c
> >> +++ b/arch/arm/mm/idmap.c
> >> @@ -1,4 +1,6 @@
> >> +#include <linux/module.h>
> >
> > Minor thing - do you need to include linux/module.h here?
> >
>
> there was once a time when kvm/arm could be compiled as a module; my
> best guess is that it's a leftover from that.
>
> >> + identity_mapping_add(hyp_pgd, __hyp_idmap_text_start,
> >> + __hyp_idmap_text_end, PMD_SECT_AP1);
> >
> > It would be more consistent if you define PMD_SECT_HYP or something like
> > that. I think you have a L_PTE_HYP bit as well.
> >
> Is this along the lines of what you had in mind?
>
> diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h
> b/arch/arm/include/asm/pgtable-3level-hwdef.h
> index 18f5cef..432fa12 100644
> --- a/arch/arm/include/asm/pgtable-3level-hwdef.h
> +++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
> @@ -50,6 +50,7 @@
> #define PMD_SECT_AP_READ (_AT(pmdval_t, 0))
> #define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6)
> #define PMD_SECT_TEX(x) (_AT(pmdval_t, 0))
> +#define PMD_SECT_HYP PMD_SECT_AP1
>
> /*
> * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
> diff --git a/arch/arm/include/asm/pgtable-3level.h
> b/arch/arm/include/asm/pgtable-3level.h
> index 6ef8afd..a7e6532 100644
> --- a/arch/arm/include/asm/pgtable-3level.h
> +++ b/arch/arm/include/asm/pgtable-3level.h
> @@ -116,6 +116,7 @@
> /*
> * Hyp-mode PL2 PTE definitions for LPAE.
> */
> +#define PMD_HYP PMD_SECT_AP1
Yes, but only one definition in is probably enough (PMD_SECT_HYP?).
--
Catalin
^ permalink raw reply
* [PATCH v6 01/15] ARM: Add page table and page defines needed by KVM
From: Christoffer Dall @ 2013-01-24 17:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130124170220.GF18233@arm.com>
On Thu, Jan 24, 2013 at 12:02 PM, Catalin Marinas
<catalin.marinas@arm.com> wrote:
> On Thu, Jan 24, 2013 at 04:05:33PM +0000, Christoffer Dall wrote:
>> On Thu, Jan 24, 2013 at 6:39 AM, Catalin Marinas
>> <catalin.marinas@arm.com> wrote:
>> > On Wed, Jan 16, 2013 at 05:57:26PM +0000, Christoffer Dall wrote:
>> >> diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
>> >> index a3f3792..6ef8afd 100644
>> >> --- a/arch/arm/include/asm/pgtable-3level.h
>> >> +++ b/arch/arm/include/asm/pgtable-3level.h
>> >> @@ -104,11 +104,29 @@
>> >> */
>> >> #define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
>> >>
>> >> +/*
>> >> + * 2nd stage PTE definitions for LPAE.
>> >> + */
>> >> +#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
>> >> +#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
>> >> +#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
>> >> +#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
>> >> +#define L_PTE_S2_RDWR (_AT(pteval_t, 2) << 6) /* HAP[2:1] */
>> >
>> > Why is this called L_PTE_S2_RDWR? The ARM ARM shows HAP[2:1] as 0b11 for
>> > read/write and 0b10 for WRONLY.
>>
>> it should be
>>
>> +#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
>
> OK.
>
>>
>> >> --- a/arch/arm/include/asm/pgtable.h
>> >> +++ b/arch/arm/include/asm/pgtable.h
>> >> @@ -70,6 +70,9 @@ extern void __pgd_error(const char *file, int line, pgd_t);
>> >>
>> >> extern pgprot_t pgprot_user;
>> >> extern pgprot_t pgprot_kernel;
>> >> +extern pgprot_t pgprot_hyp_device;
>> >> +extern pgprot_t pgprot_s2;
>> >> +extern pgprot_t pgprot_s2_device;
>> >>
>> >> #define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
>> >>
>> >> @@ -82,6 +85,10 @@ extern pgprot_t pgprot_kernel;
>> >> #define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
>> >> #define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN)
>> >> #define PAGE_KERNEL_EXEC pgprot_kernel
>> >> +#define PAGE_HYP _MOD_PROT(pgprot_kernel, L_PTE_HYP)
>> >> +#define PAGE_HYP_DEVICE _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
>> >> +#define PAGE_S2 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
>> >> +#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
>> >
>> > Are these S2 read-only by default?
>>
>> not sure I understand what you're asking here?
>
> Why do you pass L_PTE_S2_RDONLY? Do you need to restrict guest writes
> via the stage 2 attributes?
>
yes, for example when KSM merges two pages, then it must be mapped
read-only to the guest so that we catch writes and perform COW.
^ permalink raw reply
* [PATCH v6 01/15] ARM: Add page table and page defines needed by KVM
From: Catalin Marinas @ 2013-01-24 17:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANM98qKYhvb6YVUr_jF0iYrgcmoMqtom+9tsZw1PkWFabRKVNQ@mail.gmail.com>
On Thu, Jan 24, 2013 at 04:05:33PM +0000, Christoffer Dall wrote:
> On Thu, Jan 24, 2013 at 6:39 AM, Catalin Marinas
> <catalin.marinas@arm.com> wrote:
> > On Wed, Jan 16, 2013 at 05:57:26PM +0000, Christoffer Dall wrote:
> >> diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
> >> index a3f3792..6ef8afd 100644
> >> --- a/arch/arm/include/asm/pgtable-3level.h
> >> +++ b/arch/arm/include/asm/pgtable-3level.h
> >> @@ -104,11 +104,29 @@
> >> */
> >> #define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
> >>
> >> +/*
> >> + * 2nd stage PTE definitions for LPAE.
> >> + */
> >> +#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
> >> +#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
> >> +#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
> >> +#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
> >> +#define L_PTE_S2_RDWR (_AT(pteval_t, 2) << 6) /* HAP[2:1] */
> >
> > Why is this called L_PTE_S2_RDWR? The ARM ARM shows HAP[2:1] as 0b11 for
> > read/write and 0b10 for WRONLY.
>
> it should be
>
> +#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
OK.
>
> >> --- a/arch/arm/include/asm/pgtable.h
> >> +++ b/arch/arm/include/asm/pgtable.h
> >> @@ -70,6 +70,9 @@ extern void __pgd_error(const char *file, int line, pgd_t);
> >>
> >> extern pgprot_t pgprot_user;
> >> extern pgprot_t pgprot_kernel;
> >> +extern pgprot_t pgprot_hyp_device;
> >> +extern pgprot_t pgprot_s2;
> >> +extern pgprot_t pgprot_s2_device;
> >>
> >> #define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
> >>
> >> @@ -82,6 +85,10 @@ extern pgprot_t pgprot_kernel;
> >> #define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
> >> #define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN)
> >> #define PAGE_KERNEL_EXEC pgprot_kernel
> >> +#define PAGE_HYP _MOD_PROT(pgprot_kernel, L_PTE_HYP)
> >> +#define PAGE_HYP_DEVICE _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
> >> +#define PAGE_S2 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
> >> +#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
> >
> > Are these S2 read-only by default?
>
> not sure I understand what you're asking here?
Why do you pass L_PTE_S2_RDONLY? Do you need to restrict guest writes
via the stage 2 attributes?
--
Catalin
^ permalink raw reply
* [PATCH v6 04/15] KVM: ARM: Hypervisor initialization
From: Christoffer Dall @ 2013-01-24 16:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130124154535.GD18233@arm.com>
On Thu, Jan 24, 2013 at 10:45 AM, Catalin Marinas
<catalin.marinas@arm.com> wrote:
> On Wed, Jan 16, 2013 at 05:57:48PM +0000, Christoffer Dall wrote:
>> --- a/arch/arm/include/asm/pgtable-3level-hwdef.h
>> +++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
>> @@ -32,6 +32,9 @@
>> #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
>> #define PMD_BIT4 (_AT(pmdval_t, 0))
>> #define PMD_DOMAIN(x) (_AT(pmdval_t, 0))
>> +#define PMD_APTABLE_SHIFT (61)
>> +#define PMD_APTABLE (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT)
>> +#define PMD_PXNTABLE (_AT(pgdval_t, 1) << 59)
>
> Are these used anywhere? I grep'ed but couldn't find. While I'm fine
> with keeping some hardware definitions for future use, I think here you
> need to qualify these bits with some suffix to PMD_APTABLE. The APTable
> are just a group of bits with different meaning (no write access etc.).
> If you want to keep them as group of bits, you can add a _MASK suffix.
>
>> +static int init_hyp_mode(void)
>> +{
>> + phys_addr_t init_phys_addr;
>> + int cpu;
>> + int err = 0;
>> +
>> + /*
>> + * Allocate Hyp PGD and setup Hyp identity mapping
>> + */
>> + err = kvm_mmu_init();
>> + if (err)
>> + goto out_err;
>
> The comment is a bit misleading since kvm_mmu_init() simply checks
> whether hyp_pgd has been initialised. The actual initialisation is done
> by the idmap code.
>
This should fix it, thanks:
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h
b/arch/arm/include/asm/pgtable-3level-hwdef.h
index 432fa12..30fb12a 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -33,7 +33,7 @@
#define PMD_BIT4 (_AT(pmdval_t, 0))
#define PMD_DOMAIN(x) (_AT(pmdval_t, 0))
#define PMD_APTABLE_SHIFT (61)
-#define PMD_APTABLE (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT)
+#define PMD_APTABLE_MASK (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT)
#define PMD_PXNTABLE (_AT(pgdval_t, 1) << 59)
/*
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 2d30e3a..8354a6f 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -871,7 +871,7 @@ static int init_hyp_mode(void)
int err = 0;
/*
- * Allocate Hyp PGD and setup Hyp identity mapping
+ * Make sure the Hyp identity map is ready for us.
*/
err = kvm_mmu_init();
if (err)
--
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: omap3-overo: Add support for pwm-leds
From: Florian Vaussard @ 2013-01-24 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5101570A.1030303@ti.com>
>> I did it at first, but the led API executes in atomic context, where the
>> pwm-twl-led driver uses i2c communication. Setting a trigger will result in a
>> kernel panic.
>
> Now that you mentioned it, this might be true.
>
[<c0013204>] (unwind_backtrace+0x0/0xec) from [<c00348ac>]
(warn_slowpath_common+0x4c/0x64)
[<c00348ac>] (warn_slowpath_common+0x4c/0x64) from [<c00348e0>]
(warn_slowpath_null+0x1c/0x24)
[<c00348e0>] (warn_slowpath_null+0x1c/0x24) from [<c054d384>]
(__mutex_lock_slowpath+0x6c/0x26c)
[<c054d384>] (__mutex_lock_slowpath+0x6c/0x26c) from [<c054d590>]
(mutex_lock+0xc/0x20)
[<c054d590>] (mutex_lock+0xc/0x20) from [<c02d740c>]
(regmap_bulk_write+0x48/0x138)
[<c02d740c>] (regmap_bulk_write+0x48/0x138) from [<c02de2c0>]
(twl_i2c_write+0xa4/0xf0)
[<c02de2c0>] (twl_i2c_write+0xa4/0xf0) from [<c0299e34>]
(twl4030_pwmled_config+0x70/0x9c)
[<c0299e34>] (twl4030_pwmled_config+0x70/0x9c) from [<c029875c>]
(pwm_config+0x5c/0x6c)
[<c029875c>] (pwm_config+0x5c/0x6c) from [<c039dc04>]
(led_pwm_set+0x28/0x64)
[<c039dc04>] (led_pwm_set+0x28/0x64) from [<c039e27c>]
(led_heartbeat_function+0x10c/0x134)
[<c039e27c>] (led_heartbeat_function+0x10c/0x134) from [<c004359c>]
(call_timer_fn+0x90/0x178)
[<c004359c>] (call_timer_fn+0x90/0x178) from [<c0043994>]
(run_timer_softirq+0x250/0x2c8)
[<c0043994>] (run_timer_softirq+0x250/0x2c8) from [<c003cf78>]
(__do_softirq+0xf8/0x248)
[<c003cf78>] (__do_softirq+0xf8/0x248) from [<c003d154>]
(irq_exit+0x44/0x98)
[<c003d154>] (irq_exit+0x44/0x98) from [<c000e338>] (handle_IRQ+0x68/0x8c)
[<c000e338>] (handle_IRQ+0x68/0x8c) from [<c000870c>]
(omap3_intc_handle_irq+0x58/0x70)
[<c000870c>] (omap3_intc_handle_irq+0x58/0x70) from [<c054f8c0>]
(__irq_svc+0x40/0x70)
Exception stack(0xc077df60 to 0xc077dfa8)
:-)
>> I am working on a patch for pwm-twl-led to defer using a workqueue right now.
>
> Great!
> The only thing I worry about is the latency we are going to get with the
> workqueue.
>
If the latency becomes critical, we can create our own workqueue.
Do we merge anyway this patchset, or do we wait until the trigger has
been fixed?
Florian
^ permalink raw reply
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