* [PATCH 05/15] ARM: sh7372: add clock lookup entries for DT-based devices
From: Simon Horman @ 2013-01-25 2:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359080013-29189-1-git-send-email-horms+renesas@verge.net.au>
From: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
When booting with DT, devices are named differently. To get their clocks
additional entries have to be added to the lookup table.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
arch/arm/mach-shmobile/clock-sh7372.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 3ca6757b..45d21fe 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -544,6 +544,7 @@ static struct clk_lookup lookups[] = {
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
+ CLKDEV_DEV_ID("fff30000.i2c", &mstp_clks[MSTP001]), /* IIC2 */
CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
@@ -556,6 +557,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
+ CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), /* IIC0 */
CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */
CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
@@ -577,18 +579,25 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
+ CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), /* IIC1 */
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
CLKDEV_DEV_ID("sh_flctl.0", &mstp_clks[MSTP315]), /* FLCTL */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+ CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+ CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
+ CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMC */
CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
+ CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), /* SDHI2 */
CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
+ CLKDEV_DEV_ID("e6d20000.i2c", &mstp_clks[MSTP411]), /* IIC3 */
CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
+ CLKDEV_DEV_ID("e6d30000.i2c", &mstp_clks[MSTP410]), /* IIC4 */
CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */
CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
--
1.7.10.4
^ permalink raw reply related
* [PATCH 04/15] ARM: mach-shmobile: sh73a0 external IRQ wake update
From: Simon Horman @ 2013-01-25 2:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359080013-29189-1-git-send-email-horms+renesas@verge.net.au>
From: Magnus Damm <damm@opensource.se>
Use sh73a0_set_wake() for external IRQ signals on sh73a0.
The sh73a0 IRQ hardware for external IRQ pins consists of
the INTCA interrupt controller and the GIC together doing
their best to limp along. These external IRQ pins are
treated as a special case where interrupts need to be
managed in both interrupt controllers in parallel.
The ->irq_set_wake() callback for the external IRQ pins
can be dealt with in the same way as INTCA-only without
involving the GIC. So this patch updates the external
IRQ pin code for sh73a0 to no longer involve the GIC.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/intc-sh73a0.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 9783699..45973b5 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -315,11 +315,6 @@ static int intca_gic_set_type(struct irq_data *data, unsigned int type)
return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
}
-static int intca_gic_set_wake(struct irq_data *data, unsigned int on)
-{
- return irq_cbp(irq_set_wake, to_intca_reloc_irq(data), on);
-}
-
#ifdef CONFIG_SMP
static int intca_gic_set_affinity(struct irq_data *data,
const struct cpumask *cpumask,
@@ -339,7 +334,7 @@ struct irq_chip intca_gic_irq_chip = {
.irq_disable = intca_gic_disable,
.irq_shutdown = intca_gic_disable,
.irq_set_type = intca_gic_set_type,
- .irq_set_wake = intca_gic_set_wake,
+ .irq_set_wake = sh73a0_set_wake,
#ifdef CONFIG_SMP
.irq_set_affinity = intca_gic_set_affinity,
#endif
--
1.7.10.4
^ permalink raw reply related
* [PATCH 03/15] ARM: shmobile: sh73a0: fixup div4_clks bitmap
From: Simon Horman @ 2013-01-25 2:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359080013-29189-1-git-send-email-horms+renesas@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
div4_clks's bitmap of sh73a0 was wrong.
This patch is based on v2.0 datasheet.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/clock-sh73a0.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 516ff7f..5f57701 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -264,17 +264,17 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
static struct clk div4_clks[DIV4_NR] = {
- [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
- [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
- [DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
- [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
- [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
- [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
- [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
- [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
- [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
- [DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
- [DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
+ [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
+ [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
+ [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
+ [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
+ [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
+ [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
+ [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
+ [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
+ [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
+ [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
+ [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
};
enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
--
1.7.10.4
^ permalink raw reply related
* [PATCH 02/15] ARM: shmobile: r8a7740: add TMU timer support
From: Simon Horman @ 2013-01-25 2:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359080013-29189-1-git-send-email-horms+renesas@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch enabled TMU0 timer on r8a7740.
But TMU1 timer is not supported yet
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/clock-r8a7740.c | 6 +-
arch/arm/mach-shmobile/setup-r8a7740.c | 94 ++++++++++++++++++++++++++++++++
2 files changed, 99 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index eac49d5..19ce885 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -581,10 +581,14 @@ static struct clk_lookup lookups[] = {
/* MSTP32 clocks */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
- CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
+ CLKDEV_DEV_ID("sh_tmu.3", &mstp_clks[MSTP111]),
+ CLKDEV_DEV_ID("sh_tmu.4", &mstp_clks[MSTP111]),
+ CLKDEV_DEV_ID("sh_tmu.5", &mstp_clks[MSTP111]),
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
+ CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]),
+ CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP125]),
CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]),
CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]),
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 9ef397d..847567d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -261,6 +261,97 @@ static struct platform_device cmt10_device = {
.num_resources = ARRAY_SIZE(cmt10_resources),
};
+/* TMU */
+static struct sh_timer_config tmu00_platform_data = {
+ .name = "TMU00",
+ .channel_offset = 0x4,
+ .timer_bit = 0,
+ .clockevent_rating = 200,
+};
+
+static struct resource tmu00_resources[] = {
+ [0] = {
+ .name = "TMU00",
+ .start = 0xfff80008,
+ .end = 0xfff80014 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = intcs_evt2irq(0xe80),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device tmu00_device = {
+ .name = "sh_tmu",
+ .id = 0,
+ .dev = {
+ .platform_data = &tmu00_platform_data,
+ },
+ .resource = tmu00_resources,
+ .num_resources = ARRAY_SIZE(tmu00_resources),
+};
+
+static struct sh_timer_config tmu01_platform_data = {
+ .name = "TMU01",
+ .channel_offset = 0x10,
+ .timer_bit = 1,
+ .clocksource_rating = 200,
+};
+
+static struct resource tmu01_resources[] = {
+ [0] = {
+ .name = "TMU01",
+ .start = 0xfff80014,
+ .end = 0xfff80020 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = intcs_evt2irq(0xea0),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device tmu01_device = {
+ .name = "sh_tmu",
+ .id = 1,
+ .dev = {
+ .platform_data = &tmu01_platform_data,
+ },
+ .resource = tmu01_resources,
+ .num_resources = ARRAY_SIZE(tmu01_resources),
+};
+
+static struct sh_timer_config tmu02_platform_data = {
+ .name = "TMU02",
+ .channel_offset = 0x1C,
+ .timer_bit = 2,
+ .clocksource_rating = 200,
+};
+
+static struct resource tmu02_resources[] = {
+ [0] = {
+ .name = "TMU02",
+ .start = 0xfff80020,
+ .end = 0xfff8002C - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = intcs_evt2irq(0xec0),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device tmu02_device = {
+ .name = "sh_tmu",
+ .id = 2,
+ .dev = {
+ .platform_data = &tmu02_platform_data,
+ },
+ .resource = tmu02_resources,
+ .num_resources = ARRAY_SIZE(tmu02_resources),
+};
+
static struct platform_device *r8a7740_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
@@ -272,6 +363,9 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
&scif7_device,
&scifb_device,
&cmt10_device,
+ &tmu00_device,
+ &tmu01_device,
+ &tmu02_device,
};
/* DMA */
--
1.7.10.4
^ permalink raw reply related
* [PATCH 01/15] ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in setup-r8a7740.c
From: Simon Horman @ 2013-01-25 2:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359080013-29189-1-git-send-email-horms+renesas@verge.net.au>
linux/dma-mapping.h was included twice.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/setup-r8a7740.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 03c69f9..9ef397d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -27,7 +27,6 @@
#include <linux/serial_sci.h>
#include <linux/sh_dma.h>
#include <linux/sh_timer.h>
-#include <linux/dma-mapping.h>
#include <mach/dma-register.h>
#include <mach/r8a7740.h>
#include <mach/pm-rmobile.h>
--
1.7.10.4
^ permalink raw reply related
* [GIT PULL] Renesas ARM-based SoC for v3.9
From: Simon Horman @ 2013-01-25 2:13 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Arnd,
please consider the following soc enhancements for 3.9.
This series is based on a merge of the irqchip/gic-vic-move and
timer/cleanup branches in the arm-soc tree. There were a number of
conflicts in this merge, as indicated by the merge commit
6265b0f325eed54558b35769aecb1d79423295c7. In each case I took care to
match the merge made in the arm-soc tree which is evident in the for-next
branch.
----------------------------------------------------------------
The following changes since commit 6265b0f325eed54558b35769aecb1d79423295c7:
Merge remote-tracking branches 'arm-soc/irqchip/gic-vic-move' and 'arm-soc/timer/cleanup' into soc (2013-01-24 17:57:20 +0900)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git soc
for you to fetch changes up to 977b5564fc613d662a346abfce05104ea5080a46:
ARM: shmobile: r8a7779: scif .irqs used SCIx_IRQ_MUXED() (2013-01-25 09:10:45 +0900)
----------------------------------------------------------------
Bastian Hecht (4):
ARM: shmobile: sh73a0: Add CPU sleep suspend
ARM: shmobile: r8a7740: Add CPU sleep suspend
ARM: SH-Mobile: sh73a0: Secondary CPUs handle own SCU flags
ARM: SH-Mobile: sh73a0: Add CPU Hotplug
Guennadi Liakhovetski (3):
ARM: sh7372: add clock lookup entries for DT-based devices
ARM: sh7372: fix cache clean / invalidate order
ARM: shmobile: add function declarations for sh7372 DT helper functions
Kuninori Morimoto (3):
ARM: shmobile: r8a7740: add TMU timer support
ARM: shmobile: sh73a0: fixup div4_clks bitmap
ARM: shmobile: r8a7779: scif .irqs used SCIx_IRQ_MUXED()
Magnus Damm (1):
ARM: mach-shmobile: sh73a0 external IRQ wake update
Simon Horman (4):
ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in setup-r8a7740.c
ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT
ARM: mach-shmobile: sh73a0: Minimal setup using DT
ARM: mach-shmobile: sh73a0: Initialise MMCIF using DT
arch/arm/boot/dts/sh73a0-reference.dtsi | 24 ++++++
arch/arm/boot/dts/sh73a0.dtsi | 93 +++++++++++++++++++++++
arch/arm/mach-shmobile/Makefile | 3 +-
arch/arm/mach-shmobile/board-armadillo800eva.c | 2 +
arch/arm/mach-shmobile/board-kzm9g.c | 2 +
arch/arm/mach-shmobile/clock-r8a7740.c | 6 +-
arch/arm/mach-shmobile/clock-sh7372.c | 9 +++
arch/arm/mach-shmobile/clock-sh73a0.c | 35 ++++++---
arch/arm/mach-shmobile/headsmp-sh73a0.S | 50 +++++++++++++
arch/arm/mach-shmobile/include/mach/common.h | 8 ++
arch/arm/mach-shmobile/intc-sh73a0.c | 16 ++--
arch/arm/mach-shmobile/pm-r8a7740.c | 22 ++++++
arch/arm/mach-shmobile/pm-sh73a0.c | 32 ++++++++
arch/arm/mach-shmobile/setup-r8a7740.c | 95 +++++++++++++++++++++++-
arch/arm/mach-shmobile/setup-r8a7779.c | 18 ++---
arch/arm/mach-shmobile/setup-sh73a0.c | 62 +++++++++++++++-
arch/arm/mach-shmobile/sleep-sh7372.S | 12 +--
arch/arm/mach-shmobile/smp-sh73a0.c | 66 ++++++++--------
18 files changed, 485 insertions(+), 70 deletions(-)
create mode 100644 arch/arm/boot/dts/sh73a0-reference.dtsi
create mode 100644 arch/arm/boot/dts/sh73a0.dtsi
create mode 100644 arch/arm/mach-shmobile/headsmp-sh73a0.S
create mode 100644 arch/arm/mach-shmobile/pm-sh73a0.c
^ permalink raw reply
* [PATCH 2/2] ARM: mach-shmobile: mackerel: enable VFP in defconfig
From: Simon Horman @ 2013-01-25 2:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359079374-25032-1-git-send-email-horms+renesas@verge.net.au>
CONFIG_VFP appears to be required to use the
Debian armhf userspace. Enabling this is consistent
with many other shmobile boards.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/configs/mackerel_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index e6881ac..7594b3a 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -25,6 +25,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_KEXEC=y
+CONFIG_VFP=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_PM=y
CONFIG_PM_RUNTIME=y
--
1.7.10.4
^ permalink raw reply related
* [PATCH 1/2] ARM: mach-shmobile: armadillo: defconfig: Enable CEU
From: Simon Horman @ 2013-01-25 2:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359079374-25032-1-git-send-email-horms+renesas@verge.net.au>
Update the defconfig to enable the CEU camera.
It appears that it was previously enabled but an
update is required for Kconfig changes.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/configs/armadillo800eva_defconfig | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index f9e2701..0b98100 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -90,14 +90,11 @@ CONFIG_I2C_SH_MOBILE=y
# CONFIG_HWMON is not set
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
-# CONFIG_RC_CORE is not set
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-# CONFIG_V4L_USB_DRIVERS is not set
+CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_MT9T112=y
CONFIG_VIDEO_SH_MOBILE_CEU=y
-# CONFIG_RADIO_ADAPTERS is not set
CONFIG_FB=y
CONFIG_FB_SH_MOBILE_LCDC=y
CONFIG_FB_SH_MOBILE_HDMI=y
--
1.7.10.4
^ permalink raw reply related
* [GIT PULL] Renesas ARM-based SoC defconfig for v3.9 #2
From: Simon Horman @ 2013-01-25 2:02 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Arnd,
please consider the following defconfig enhancements for 3.9.
This series is based on the renesas/defconfig branch in the arm-soc tree.
----------------------------------------------------------------
The following changes since commit 8098df15c26b2bf16924df5a134d1a649692ab62:
ARM: mach-shmobile: kzm9d: update defconfig (2013-01-15 08:57:09 +0900)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git defconfig2
for you to fetch changes up to 46bbd43fa44fe083188f3e4846ba5b8d3c89bae6:
ARM: mach-shmobile: mackerel: enable VFP in defconfig (2013-01-23 14:59:37 +0900)
----------------------------------------------------------------
Simon Horman (2):
ARM: mach-shmobile: armadillo: defconfig: Enable CEU
ARM: mach-shmobile: mackerel: enable VFP in defconfig
arch/arm/configs/armadillo800eva_defconfig | 5 +----
arch/arm/configs/mackerel_defconfig | 1 +
2 files changed, 2 insertions(+), 4 deletions(-)
^ permalink raw reply
* [PATCH v2 1/1 net-next] net: fec: add napi support to improve proformance
From: Frank Li @ 2013-01-25 2:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359035768.12374.2083.camel@edumazet-glaptop>
2013/1/24 Eric Dumazet <eric.dumazet@gmail.com>:
> On Thu, 2013-01-24 at 15:58 +0800, Frank Li wrote:
>>
>> static irqreturn_t
>> @@ -805,6 +823,7 @@ fec_enet_interrupt(int irq, void *dev_id)
>> struct net_device *ndev = dev_id;
>> struct fec_enet_private *fep = netdev_priv(ndev);
>> uint int_events;
>> + ulong flags;
>> irqreturn_t ret = IRQ_NONE;
>>
>> do {
>> @@ -813,7 +832,14 @@ fec_enet_interrupt(int irq, void *dev_id)
>>
>> if (int_events & FEC_ENET_RXF) {
>> ret = IRQ_HANDLED;
>> - fec_enet_rx(ndev);
>> +
>> + spin_lock_irqsave(&fep->hw_lock, flags);
>
> You already are in a irq safe context, spin_lock() should be ok
Okay, I will fix it.
>
>> + /* Disable the RX interrupt */
>> + if (napi_schedule_prep(&fep->napi)) {
>> + fec_enet_rx_int_is_enabled(ndev, false);
>> + __napi_schedule(&fep->napi);
>> + }
>> + spin_unlock_irqrestore(&fep->hw_lock, flags);
>
> spin_unlock();
>
>> }
>>
>
>
> Same remark for the spin_lock_irqsave(&fep->tmreg_lock, flags) in
> fec_enet_tx()
>
Okay, but it is not related with NAPI support.
Need new patch for that.
>
>
^ permalink raw reply
* [V5 PATCH 07/26] usb: gadget: mv_udc: make mv_udc depends on ARCH_MMP or ARCH_PXA
From: chao xie @ 2013-01-25 1:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130124090849.GE27304@arwen.pp.htv.fi>
2013/1/24 Felipe Balbi <balbi@ti.com>:
> Hi,
>
> On Thu, Jan 24, 2013 at 01:38:31AM -0500, Chao Xie wrote:
>> Only ARCH_PXA and ARCH_MMP will use mv_udc.
>>
>> Signed-off-by: Chao Xie <chao.xie@marvell.com>
>
> NAK, you should fix your transceiver dependency. I want these gadget
> drivers to compile cleanly on all arches so we make proper use of
> linux-next. I have applied up to previous patch in this series and I
> won't go any further. The rest will be delayed for v3.10
>
> sorry
>
> --
> balbi
I see. I will remove this patch. In fact, I have modified the dependency, so
without this patch, the reset of patches can still be compiled successully.
So when is the next merge? Need i re-send the rest of patches?
There are some feedbacks about device tree, and I will seperate the
device tree part from the
patche series. i do not want to post a big set of patches only with
modification to device tree part.
Thanks.
Chao
^ permalink raw reply
* [PATCH v3 1/1 net-next] net: fec: enable pause frame to improve rx prefomance for 1G network
From: Frank Li @ 2013-01-25 1:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359046173.2736.2.camel@bwh-desktop.uk.solarflarecom.com>
2013/1/25 Ben Hutchings <bhutchings@solarflare.com>:
> On Thu, 2013-01-24 at 10:16 +0800, Frank Li wrote:
>> 2013/1/24 Ben Hutchings <bhutchings@solarflare.com>:
>> > On Thu, 2013-01-17 at 10:55 +0800, Frank Li wrote:
>> >> The limition of imx6 internal bus cause fec can't achieve 1G perfomance.
>> >> There will be many packages lost because FIFO over run.
>> >>
>> >> This patch enable pause frame flow control.
>> > [...]
>> >> --- a/drivers/net/ethernet/freescale/fec.c
>> >> +++ b/drivers/net/ethernet/freescale/fec.c
>> > [...]
>> >> +static int fec_enet_set_pauseparam(struct net_device *ndev,
>> >> + struct ethtool_pauseparam *pause)
>> >> +{
>> >> + struct fec_enet_private *fep = netdev_priv(ndev);
>> >> +
>> >> + if (pause->tx_pause != pause->rx_pause) {
>> >> + netdev_info(ndev,
>> >> + "hardware only support enable/disable both tx and rx");
>> >> + return -EINVAL;
>> >> + }
>> >> +
>> >> + fep->pause_flag = 0;
>> >> +
>> >> + /* tx pause must be same as rx pause */
>> >> + fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
>> >> + fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
>> >> +
>> >> + if (pause->rx_pause || pause->autoneg) {
>> >> + fep->phy_dev->supported |= ADVERTISED_Pause;
>> >> + fep->phy_dev->advertising |= ADVERTISED_Pause;
>> >> + } else {
>> >> + fep->phy_dev->supported &= ~ADVERTISED_Pause;
>> >> + fep->phy_dev->advertising &= ~ADVERTISED_Pause;
>> >> + }
>> > [...]
>> >
>> > Why is this changing the supported flags, i.e. device capabilities? You
>> > need to leave those flags alone and reject an attempt to enable pause
>> > frames on a device that doesn't support them.
>>
>> I go through phylib, I have not found good place set ADVERTISED_Pause
>> capabilities.
>> genphy_config_init never check Pause capabilities.
>
> I agree that phylib can't initialise pause capabilities because those
> depend on the MAC. But look at which function I'm quoting: this is the
> ethtool operation, which shouldn't change capabilities.
Where is good place do you think? in probe function?
>
> Ben.
>
> --
> Ben Hutchings, Staff Engineer, Solarflare
> Not speaking for my employer; that's the marketing department's job.
> They asked us to note that Solarflare product names are trademarked.
>
^ permalink raw reply
* [PATCH 2/2 net-next] doc: dt: fsl: fec: add napi optional properties
From: Frank Li @ 2013-01-25 1:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130124.181800.580308569081621879.davem@davemloft.net>
2013/1/25 David Miller <davem@davemloft.net>:
> From: Frank Li <Frank.Li@freescale.com>
> Date: Thu, 24 Jan 2013 15:06:59 +0800
>
>> Signed-off-by: Frank Li <Frank.Li@freescale.com>
>
> For the thousandth time, you should not make NAPI run time
> selectable, this is non-negotable.
Sorry, this patch send by accident.
Please forget it.
Best regards
Frank Li
^ permalink raw reply
* [PATCH v3 1/1 net-next] net: fec: add napi support to improve proformance
From: Frank Li @ 2013-01-25 1:29 UTC (permalink / raw)
To: linux-arm-kernel
Add napi support
Before this patch
iperf -s -i 1
------------------------------------------------------------
Server listening on TCP port 5001
TCP window size: 85.3 KByte (default)
------------------------------------------------------------
[ 4] local 10.192.242.153 port 5001 connected with 10.192.242.138 port 50004
[ ID] Interval Transfer Bandwidth
[ 4] 0.0- 1.0 sec 41.2 MBytes 345 Mbits/sec
[ 4] 1.0- 2.0 sec 43.7 MBytes 367 Mbits/sec
[ 4] 2.0- 3.0 sec 42.8 MBytes 359 Mbits/sec
[ 4] 3.0- 4.0 sec 43.7 MBytes 367 Mbits/sec
[ 4] 4.0- 5.0 sec 42.7 MBytes 359 Mbits/sec
[ 4] 5.0- 6.0 sec 43.8 MBytes 367 Mbits/sec
[ 4] 6.0- 7.0 sec 43.0 MBytes 361 Mbits/sec
After this patch
[ 4] 2.0- 3.0 sec 51.6 MBytes 433 Mbits/sec
[ 4] 3.0- 4.0 sec 51.8 MBytes 435 Mbits/sec
[ 4] 4.0- 5.0 sec 52.2 MBytes 438 Mbits/sec
[ 4] 5.0- 6.0 sec 52.1 MBytes 437 Mbits/sec
[ 4] 6.0- 7.0 sec 52.1 MBytes 437 Mbits/sec
[ 4] 7.0- 8.0 sec 52.3 MBytes 439 Mbits/sec
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
---
Change from v2 to v3
* replace fec_enet_rx_int_is_enabled with fec_enet_rx_int_enable
* replace spin_lock_saveirq with spin_lock in irq handle
Change from v1 to v2
* Remove use_napi and napi_weight config. Support NAPI only.
* using napi_gro_receive replace netif_rx
drivers/net/ethernet/freescale/fec.c | 55 +++++++++++++++++++++++++++++-----
drivers/net/ethernet/freescale/fec.h | 2 +
2 files changed, 49 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index f52ba33..1d9e019 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -67,6 +67,7 @@
#endif
#define DRIVER_NAME "fec"
+#define FEC_NAPI_WEIGHT 64
/* Pause frame feild and FIFO threshold */
#define FEC_ENET_FCE (1 << 5)
@@ -565,6 +566,20 @@ fec_timeout(struct net_device *ndev)
}
static void
+fec_enet_rx_int_enable(struct net_device *ndev, bool enabled)
+{
+ struct fec_enet_private *fep = netdev_priv(ndev);
+ uint int_events;
+
+ int_events = readl(fep->hwp + FEC_IMASK);
+ if (enabled)
+ int_events |= FEC_ENET_RXF;
+ else
+ int_events &= ~FEC_ENET_RXF;
+ writel(int_events, fep->hwp + FEC_IMASK);
+}
+
+static void
fec_enet_tx(struct net_device *ndev)
{
struct fec_enet_private *fep;
@@ -656,8 +671,8 @@ fec_enet_tx(struct net_device *ndev)
* not been given to the system, we just set the empty indicator,
* effectively tossing the packet.
*/
-static void
-fec_enet_rx(struct net_device *ndev)
+static int
+fec_enet_rx(struct net_device *ndev, int budget)
{
struct fec_enet_private *fep = netdev_priv(ndev);
const struct platform_device_id *id_entry =
@@ -667,13 +682,12 @@ fec_enet_rx(struct net_device *ndev)
struct sk_buff *skb;
ushort pkt_len;
__u8 *data;
+ int pkt_received = 0;
#ifdef CONFIG_M532x
flush_cache_all();
#endif
- spin_lock(&fep->hw_lock);
-
/* First, grab all of the stats for the incoming packet.
* These get messed up if we get called due to a busy condition.
*/
@@ -681,6 +695,10 @@ fec_enet_rx(struct net_device *ndev)
while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
+ if (pkt_received >= budget)
+ break;
+ pkt_received++;
+
/* Since we have allocated space to hold a complete frame,
* the last indicator should be set.
*/
@@ -762,7 +780,7 @@ fec_enet_rx(struct net_device *ndev)
}
if (!skb_defer_rx_timestamp(skb))
- netif_rx(skb);
+ napi_gro_receive(&fep->napi, skb);
}
bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
@@ -796,7 +814,7 @@ rx_processing_done:
}
fep->cur_rx = bdp;
- spin_unlock(&fep->hw_lock);
+ return pkt_received;
}
static irqreturn_t
@@ -813,7 +831,14 @@ fec_enet_interrupt(int irq, void *dev_id)
if (int_events & FEC_ENET_RXF) {
ret = IRQ_HANDLED;
- fec_enet_rx(ndev);
+
+ spin_lock(&fep->hw_lock);
+ /* Disable the RX interrupt */
+ if (napi_schedule_prep(&fep->napi)) {
+ fec_enet_rx_int_enable(ndev, false);
+ __napi_schedule(&fep->napi);
+ }
+ spin_unlock(&fep->hw_lock);
}
/* Transmit OK, or non-fatal error. Update the buffer
@@ -834,7 +859,16 @@ fec_enet_interrupt(int irq, void *dev_id)
return ret;
}
-
+static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
+{
+ struct net_device *ndev = napi->dev;
+ int pkgs = fec_enet_rx(ndev, budget);
+ if (pkgs < budget) {
+ napi_complete(napi);
+ fec_enet_rx_int_enable(ndev, true);
+ }
+ return pkgs;
+}
/* ------------------------------------------------------------------------- */
static void fec_get_mac(struct net_device *ndev)
@@ -1392,6 +1426,8 @@ fec_enet_open(struct net_device *ndev)
struct fec_enet_private *fep = netdev_priv(ndev);
int ret;
+ napi_enable(&fep->napi);
+
/* I should reset the ring buffers here, but I don't yet know
* a simple way to do that.
*/
@@ -1604,6 +1640,9 @@ static int fec_enet_init(struct net_device *ndev)
ndev->netdev_ops = &fec_netdev_ops;
ndev->ethtool_ops = &fec_enet_ethtool_ops;
+ fec_enet_rx_int_enable(ndev, false);
+ netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
+
/* Initialize the receive buffer descriptors. */
bdp = fep->rx_bd_base;
for (i = 0; i < RX_RING_SIZE; i++) {
diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
index 2ebedaf..01579b8 100644
--- a/drivers/net/ethernet/freescale/fec.h
+++ b/drivers/net/ethernet/freescale/fec.h
@@ -249,6 +249,8 @@ struct fec_enet_private {
int bufdesc_ex;
int pause_flag;
+ struct napi_struct napi;
+
struct ptp_clock *ptp_clock;
struct ptp_clock_info ptp_caps;
unsigned long last_overflow_check;
--
1.7.1
^ permalink raw reply related
* [PATCHv1 for soc 5/5] arm: socfpga: Add SMP support for actual socfpga harware
From: dinguyen at altera.com @ 2013-01-25 1:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359075633-13502-1-git-send-email-dinguyen@altera.com>
From: Dinh Nguyen <dinguyen@altera.com>
Because the CPU1 start address is different for socfpga-vt and
socfpga-cyclone5, we add code to use the correct CPU1 start addr.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
---
arch/arm/configs/socfpga_defconfig | 1 +
arch/arm/mach-socfpga/core.h | 4 +++-
arch/arm/mach-socfpga/headsmp.S | 14 ++++++++++----
arch/arm/mach-socfpga/platsmp.c | 3 ++-
arch/arm/mach-socfpga/socfpga.c | 16 ++++++++++++++++
5 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 4e1ce21..480ab64 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -21,6 +21,7 @@ CONFIG_ARM_THUMBEE=y
# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
# CONFIG_CACHE_L2X0 is not set
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_VMSPLIT_2G=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_AEABI=y
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 9941caa..5b76dd4 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -20,7 +20,7 @@
#ifndef __MACH_CORE_H
#define __MACH_CORE_H
-extern void secondary_startup(void);
+extern void v7_secondary_startup(void);
extern void __iomem *socfpga_scu_base_addr;
extern void socfpga_init_clocks(void);
@@ -29,6 +29,8 @@ extern void socfpga_sysmgr_init(void);
extern struct smp_operations socfpga_smp_ops;
extern char secondary_trampoline, secondary_trampoline_end;
+extern unsigned long cpu1start_addr;
+
#define SOCFPGA_SCU_VIRT_BASE 0xfffec000
#endif
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index f09b128..01911e8 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -13,13 +13,19 @@
__CPUINIT
.arch armv7-a
-#define CPU1_START_ADDR 0xffd08010
-
ENTRY(secondary_trampoline)
- movw r0, #:lower16:CPU1_START_ADDR
- movt r0, #:upper16:CPU1_START_ADDR
+ movw r2, #:lower16:cpu1start_addr
+ movt r2, #:upper16:cpu1start_addr
+ ldr r0, [r2]
ldr r1, [r0]
bx r1
ENTRY(secondary_trampoline_end)
+
+#ifdef CONFIG_SMP
+ENTRY(v7_secondary_startup)
+ bl v7_invalidate_l1
+ b secondary_startup
+ENDPROC(v7_secondary_startup)
+#endif
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 68dd1b6..c428519 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -49,7 +49,8 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct
memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
- __raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
+ __raw_writel(virt_to_phys(v7_secondary_startup),
+ (sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
flush_cache_all();
smp_wmb();
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 198f491..317f4c3 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -29,6 +29,7 @@
void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
void __iomem *sys_manager_base_addr;
void __iomem *rst_manager_base_addr;
+unsigned long cpu1start_addr;
static struct map_desc scu_io_desc __initdata = {
.virtual = SOCFPGA_SCU_VIRT_BASE,
@@ -55,6 +56,16 @@ static void __init socfpga_scu_map_io(void)
iotable_init(&scu_io_desc, 1);
}
+static void __init init_socfpga_vt(void)
+{
+ cpu1start_addr = 0xffd08010;
+}
+
+static void __init init_socfpga(void)
+{
+ cpu1start_addr = 0xffd080c4;
+}
+
static void __init socfpga_map_io(void)
{
socfpga_scu_map_io();
@@ -82,6 +93,11 @@ static void __init gic_init_irq(void)
{
of_irq_init(irq_match);
socfpga_sysmgr_init();
+
+ if (of_machine_is_compatible("altr,socfpga-vt"))
+ init_socfpga_vt();
+ else
+ init_socfpga();
}
static void socfpga_cyclone5_restart(char mode, const char *cmd)
--
1.7.9.5
^ permalink raw reply related
* [PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S
From: dinguyen at altera.com @ 2013-01-25 1:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359075633-13502-1-git-send-email-dinguyen@altera.com>
From: Dinh Nguyen <dinguyen@altera.com>
mach-socfpga is another platform that needs to use
v7_invalidate_l1 to bringup additional cores. There was a comment that
the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Olof Johansson <olof@lixom.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Simon Horman <horms@verge.net.au>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Pavel Machek <pavel@denx.de>
---
arch/arm/mach-imx/headsmp.S | 47 -------------------------------------
arch/arm/mach-shmobile/headsmp.S | 48 --------------------------------------
arch/arm/mach-tegra/headsmp.S | 43 ----------------------------------
arch/arm/mm/cache-v7.S | 47 +++++++++++++++++++++++++++++++++++++
4 files changed, 47 insertions(+), 138 deletions(-)
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 7e49deb..921fc15 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -17,53 +17,6 @@
.section ".text.head", "ax"
-/*
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor. We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- *
- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
- * to be called for both secondary cores startup and primary core resume
- * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
- */
-ENTRY(v7_invalidate_l1)
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
- mcr p15, 2, r0, c0, c0, 0
- mrc p15, 1, r0, c0, c0, 0
-
- ldr r1, =0x7fff
- and r2, r1, r0, lsr #13
-
- ldr r1, =0x3ff
-
- and r3, r1, r0, lsr #3 @ NumWays - 1
- add r2, r2, #1 @ NumSets
-
- and r0, r0, #0x7
- add r0, r0, #4 @ SetShift
-
- clz r1, r3 @ WayShift
- add r4, r3, #1 @ NumWays
-1: sub r2, r2, #1 @ NumSets--
- mov r3, r4 @ Temp = NumWays
-2: subs r3, r3, #1 @ Temp--
- mov r5, r3, lsl r1
- mov r6, r2, lsl r0
- orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
- mcr p15, 0, r5, c7, c6, 2
- bgt 2b
- cmp r2, #0
- bgt 1b
- dsb
- isb
- mov pc, lr
-ENDPROC(v7_invalidate_l1)
-
#ifdef CONFIG_SMP
ENTRY(v7_secondary_startup)
bl v7_invalidate_l1
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index b202c12..96001fd 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -16,54 +16,6 @@
__CPUINIT
-/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks!
- *
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor. We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- *
- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
- * to be called for both secondary cores startup and primary core resume
- * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
- */
-ENTRY(v7_invalidate_l1)
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
- mcr p15, 2, r0, c0, c0, 0
- mrc p15, 1, r0, c0, c0, 0
-
- ldr r1, =0x7fff
- and r2, r1, r0, lsr #13
-
- ldr r1, =0x3ff
-
- and r3, r1, r0, lsr #3 @ NumWays - 1
- add r2, r2, #1 @ NumSets
-
- and r0, r0, #0x7
- add r0, r0, #4 @ SetShift
-
- clz r1, r3 @ WayShift
- add r4, r3, #1 @ NumWays
-1: sub r2, r2, #1 @ NumSets--
- mov r3, r4 @ Temp = NumWays
-2: subs r3, r3, #1 @ Temp--
- mov r5, r3, lsl r1
- mov r6, r2, lsl r0
- orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
- mcr p15, 0, r5, c7, c6, 2
- bgt 2b
- cmp r2, #0
- bgt 1b
- dsb
- isb
- mov pc, lr
-ENDPROC(v7_invalidate_l1)
-
ENTRY(shmobile_invalidate_start)
bl v7_invalidate_l1
b secondary_startup
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 4a317fa..fb082c4 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -18,49 +18,6 @@
.section ".text.head", "ax"
__CPUINIT
-/*
- * Tegra specific entry point for secondary CPUs.
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor. We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- */
-ENTRY(v7_invalidate_l1)
- mov r0, #0
- mcr p15, 2, r0, c0, c0, 0
- mrc p15, 1, r0, c0, c0, 0
-
- ldr r1, =0x7fff
- and r2, r1, r0, lsr #13
-
- ldr r1, =0x3ff
-
- and r3, r1, r0, lsr #3 @ NumWays - 1
- add r2, r2, #1 @ NumSets
-
- and r0, r0, #0x7
- add r0, r0, #4 @ SetShift
-
- clz r1, r3 @ WayShift
- add r4, r3, #1 @ NumWays
-1: sub r2, r2, #1 @ NumSets--
- mov r3, r4 @ Temp = NumWays
-2: subs r3, r3, #1 @ Temp--
- mov r5, r3, lsl r1
- mov r6, r2, lsl r0
- orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
- mcr p15, 0, r5, c7, c6, 2
- bgt 2b
- cmp r2, #0
- bgt 1b
- dsb
- isb
- mov pc, lr
-ENDPROC(v7_invalidate_l1)
-
ENTRY(tegra_secondary_startup)
bl v7_invalidate_l1
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 7539ec2..a7f7893 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -19,6 +19,53 @@
#include "proc-macros.S"
/*
+ * The secondary kernel init calls v7_flush_dcache_all before it enables
+ * the L1; however, the L1 comes out of reset in an undefined state, so
+ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ * of cache lines with uninitialized data and uninitialized tags to get
+ * written out to memory, which does really unpleasant things to the main
+ * processor. We fix this by performing an invalidate, rather than a
+ * clean + invalidate, before jumping into the kernel.
+ *
+ * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
+ * to be called for both secondary cores startup and primary core resume
+ * procedures.
+ */
+ENTRY(v7_invalidate_l1)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mcr p15, 2, r0, c0, c0, 0
+ mrc p15, 1, r0, c0, c0, 0
+
+ ldr r1, =0x7fff
+ and r2, r1, r0, lsr #13
+
+ ldr r1, =0x3ff
+
+ and r3, r1, r0, lsr #3 @ NumWays - 1
+ add r2, r2, #1 @ NumSets
+
+ and r0, r0, #0x7
+ add r0, r0, #4 @ SetShift
+
+ clz r1, r3 @ WayShift
+ add r4, r3, #1 @ NumWays
+1: sub r2, r2, #1 @ NumSets--
+ mov r3, r4 @ Temp = NumWays
+2: subs r3, r3, #1 @ Temp--
+ mov r5, r3, lsl r1
+ mov r6, r2, lsl r0
+ orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+ mcr p15, 0, r5, c7, c6, 2
+ bgt 2b
+ cmp r2, #0
+ bgt 1b
+ dsb
+ isb
+ mov pc, lr
+ENDPROC(v7_invalidate_l1)
+
+/*
* v7_flush_icache_all()
*
* Flush the whole I-cache.
--
1.7.9.5
^ permalink raw reply related
* [PATCHv1 for soc 3/5] arm: socfpga: Add entries to enable make dtbs socfpga
From: dinguyen at altera.com @ 2013-01-25 1:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359075633-13502-1-git-send-email-dinguyen@altera.com>
From: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
---
arch/arm/boot/dts/Makefile | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5ebb44f..1b8276c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
r8a7740-armadillo800eva.dtb \
sh73a0-kzm9g.dtb \
sh7372-mackerel.dtb
+dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
+ socfpga_vt.dtb
dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
spear1340-evb.dtb
dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
--
1.7.9.5
^ permalink raw reply related
* [PATCHv1 for soc 2/5] arm: socfpga: Add clock entries to socfpga.dtsi
From: dinguyen at altera.com @ 2013-01-25 1:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359075633-13502-1-git-send-email-dinguyen@altera.com>
From: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
---
arch/arm/boot/dts/socfpga.dtsi | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 936d230..688729f 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -78,6 +78,43 @@
};
};
+ clkmgr at ffd04000 {
+ compatible = "altr, clk-mgr";
+ reg = <0xffd04000 0x1000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc1: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ mainpll: mainpll {
+ #clock-cells = <0>;
+ compatible = "altr,main-pll-clock";
+ clocks = <&osc1>;
+ reg = <0x40>;
+ };
+
+ perpll: perpll {
+ #clock-cells = <0>;
+ compatible = "altr,per-pll-clock";
+ clocks = <&osc1>;
+ reg = <0x80>;
+ };
+
+ sdrampll: sdrampll {
+ #clock-cells = <0>;
+ compatible = "altr,sdram-pll-clock";
+ clocks = <&osc1>;
+ reg = <0xC0>;
+ };
+ };
+ };
+
gmac0: stmmac at ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
reg = <0xff700000 0x2000>;
--
1.7.9.5
^ permalink raw reply related
* [PATCHv1 for soc 1/5] arm: socfpga: Add new device tree source for actual socfpga HW
From: dinguyen at altera.com @ 2013-01-25 1:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359075633-13502-1-git-send-email-dinguyen@altera.com>
From: Dinh Nguyen <dinguyen@altera.com>
Up to this point, support for socfpga has only been on a virtual
platform. Now that actual hardware is available, we add the appropriate
device tree source files.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
---
arch/arm/boot/dts/socfpga.dtsi | 22 ++++++------
arch/arm/boot/dts/socfpga_cyclone5.dts | 28 ++++++++++++++-
arch/arm/boot/dts/socfpga_vt.dts | 60 ++++++++++++++++++++++++++++++++
arch/arm/mach-socfpga/socfpga.c | 1 +
4 files changed, 98 insertions(+), 13 deletions(-)
create mode 100644 arch/arm/boot/dts/socfpga_vt.dts
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 19aec42..936d230 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -25,6 +25,10 @@
ethernet0 = &gmac0;
serial0 = &uart0;
serial1 = &uart1;
+ timer0 = &timer0;
+ timer1 = &timer1;
+ timer2 = &timer2;
+ timer3 = &timer3;
};
cpus {
@@ -98,47 +102,41 @@
interrupts = <1 13 0xf04>;
};
- timer0: timer at ffc08000 {
+ timer0: timer0 at ffc08000 {
compatible = "snps,dw-apb-timer-sp";
interrupts = <0 167 4>;
- clock-frequency = <200000000>;
reg = <0xffc08000 0x1000>;
};
- timer1: timer at ffc09000 {
+ timer1: timer1 at ffc09000 {
compatible = "snps,dw-apb-timer-sp";
interrupts = <0 168 4>;
- clock-frequency = <200000000>;
reg = <0xffc09000 0x1000>;
};
- timer2: timer at ffd00000 {
+ timer2: timer2 at ffd00000 {
compatible = "snps,dw-apb-timer-osc";
interrupts = <0 169 4>;
- clock-frequency = <200000000>;
reg = <0xffd00000 0x1000>;
};
- timer3: timer at ffd01000 {
+ timer3: timer3 at ffd01000 {
compatible = "snps,dw-apb-timer-osc";
interrupts = <0 170 4>;
- clock-frequency = <200000000>;
reg = <0xffd01000 0x1000>;
};
- uart0: uart at ffc02000 {
+ uart0: serial0 at ffc02000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x1000>;
- clock-frequency = <7372800>;
interrupts = <0 162 4>;
reg-shift = <2>;
reg-io-width = <4>;
};
- uart1: uart at ffc03000 {
+ uart1: serial1 at ffc03000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc03000 0x1000>;
- clock-frequency = <7372800>;
interrupts = <0 163 4>;
reg-shift = <2>;
reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index ab7e4a9..1a6d088 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -29,6 +29,32 @@
memory {
name = "memory";
device_type = "memory";
- reg = <0x0 0x10000000>; /* 256MB */
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ soc {
+ timer0 at ffc08000 {
+ clock-frequency = <100000000>;
+ };
+
+ timer1 at ffc09000 {
+ clock-frequency = <100000000>;
+ };
+
+ timer2 at ffd00000 {
+ clock-frequency = <25000000>;
+ };
+
+ timer3 at ffd01000 {
+ clock-frequency = <25000000>;
+ };
+
+ serial0 at ffc02000 {
+ clock-frequency = <100000000>;
+ };
+
+ serial1 at ffc03000 {
+ clock-frequency = <100000000>;
+ };
};
};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
new file mode 100644
index 0000000..df3551f
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/include/ "socfpga.dtsi"
+
+/ {
+ model = "Altera SOCFPGA VT";
+ compatible = "altr,socfpga-vt";
+
+ chosen {
+ bootargs = "console=ttyS0,57600";
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1 GB */
+ };
+
+ soc {
+ timer0 at ffc08000 {
+ clock-frequency = <7000000>;
+ };
+
+ timer1 at ffc09000 {
+ clock-frequency = <7000000>;
+ };
+
+ timer2 at ffd00000 {
+ clock-frequency = <7000000>;
+ };
+
+ timer3 at ffd01000 {
+ clock-frequency = <7000000>;
+ };
+
+ serial0 at ffc02000 {
+ clock-frequency = <7372800>;
+ };
+
+ serial1 at ffc03000 {
+ clock-frequency = <7372800>;
+ };
+ };
+};
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 6732924..198f491 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -99,6 +99,7 @@ static void __init socfpga_cyclone5_init(void)
static const char *altera_dt_match[] = {
"altr,socfpga",
"altr,socfpga-cyclone5",
+ "altr,socfpga-vt",
NULL
};
--
1.7.9.5
^ permalink raw reply related
* [PATCHv1 for soc 0/5] Enabling socfpga on hardware
From: dinguyen at altera.com @ 2013-01-25 1:00 UTC (permalink / raw)
To: linux-arm-kernel
From: Dinh Nguyen <dinguyen@altera.com>
Hi,
Up until this point, support for socfpga has only been for a virtual target environment.
Here are a set of patches that enables socfpga on actual hardware.
patch: arm: Add v7_invalidate_l1 to cache-v7.S should be of some interest.
When enabling SMP on ARMv7 hardware on socfpga, the call to v7_flush_dcache_all was
making the main CPU lost. On socfpga, as well as IMX, SHMOBILE, and TEGRA the call
to v7_invalidate_l1 was required.
Thanks,
Dinh
Dinh Nguyen (5):
arm: socfpga: Add new device tree source for actual socfpga HW
arm: socfpga: Add clock entries to socfpga.dtsi
arm: socfpga: Add entries to enable make dtbs socfpga
arm: Add v7_invalidate_l1 to cache-v7.S
arm: socfpga: Add SMP support for actual socfpga harware
arch/arm/boot/dts/Makefile | 2 ++
arch/arm/boot/dts/socfpga.dtsi | 59 ++++++++++++++++++++++++-------
arch/arm/boot/dts/socfpga_cyclone5.dts | 28 ++++++++++++++-
arch/arm/boot/dts/socfpga_vt.dts | 60 ++++++++++++++++++++++++++++++++
arch/arm/configs/socfpga_defconfig | 1 +
arch/arm/mach-imx/headsmp.S | 47 -------------------------
arch/arm/mach-shmobile/headsmp.S | 48 -------------------------
arch/arm/mach-socfpga/core.h | 4 ++-
arch/arm/mach-socfpga/headsmp.S | 14 +++++---
arch/arm/mach-socfpga/platsmp.c | 3 +-
arch/arm/mach-socfpga/socfpga.c | 17 +++++++++
arch/arm/mach-tegra/headsmp.S | 43 -----------------------
arch/arm/mm/cache-v7.S | 47 +++++++++++++++++++++++++
13 files changed, 216 insertions(+), 157 deletions(-)
create mode 100644 arch/arm/boot/dts/socfpga_vt.dts
--
1.7.9.5
^ permalink raw reply
* [PATCH 2/2 net-next] doc: dt: fsl: fec: add napi optional properties
From: David Miller @ 2013-01-24 23:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359011219-8343-1-git-send-email-Frank.Li@freescale.com>
From: Frank Li <Frank.Li@freescale.com>
Date: Thu, 24 Jan 2013 15:06:59 +0800
> Signed-off-by: Frank Li <Frank.Li@freescale.com>
For the thousandth time, you should not make NAPI run time
selectable, this is non-negotable.
^ permalink raw reply
* [PATCH v2 1/3] ARM: stacktrace: harden FP stacktraces against invalid stacks
From: Colin Cross @ 2013-01-24 22:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5101A2A3.8000608@codeaurora.org>
On Thu, Jan 24, 2013 at 1:07 PM, Laura Abbott <lauraa@codeaurora.org> wrote:
> On 11/29/2012 3:00 PM, Colin Cross wrote:
>
>> +bool sp_addr_valid(unsigned long sp)
>> +{
>> + unsigned long high;
>> + unsigned long offset;
>> + unsigned int pfn;
>> + unsigned int start_pfn;
>> + unsigned int end_pfn;
>> +
>> + if (!IS_ALIGNED(sp, 4))
>> + return false;
>> +
>> + offset = sp & (THREAD_SIZE - 1);
>> +
>> + if (offset > THREAD_START_SP)
>> + return false;
>> +
>> + if (offset < sizeof(struct thread_info))
>> + return false;
>> +
>> + high = STACK_MAX(sp);
>> +
>> + if (!virt_addr_valid(sp) || !virt_addr_valid(high))
>> + return false;
>> +
>> + start_pfn = page_to_pfn(virt_to_page(sp));
>> + end_pfn = page_to_pfn(virt_to_page(high));
>> + for (pfn = start_pfn; pfn <= end_pfn; pfn++)
>> + if (!pfn_valid(pfn))
>> + return false;
>> +
>> + return true;
>> +}
>
>
> I get crashes on bootup with CONFIG_SPARSEMEM enabled if a stacktrace needs
> to be saved before the sections are setup:
>
> <1>[ 0.000000] Unable to handle kernel NULL pointer dereference at
> virtual address 00000000
> <1>[ 0.000000] pgd = c0004000
> <1>[ 0.000000] [00000000] *pgd=00000000
> <0>[ 0.000000] Internal error: Oops: 5 [#1] PREEMPT SMP ARM
> <4>[ 0.000000] Modules linked in:
> <4>[ 0.000000] CPU: 0 Not tainted (3.4.0-ga472ec0-00007-g6479b9e-dirty
> #10)
> <4>[ 0.000000] PC is at sp_addr_valid+0xb0/0x1bc
> <4>[ 0.000000] LR is at unwind_frame+0x4c/0x5b0
> ...
> <1>[ 0.000000] Unable to handle kernel NULL pointer dereference at
> virtual address 00000000
> <1>[ 0.000000] pgd = c0004000
> <1>[ 0.000000] [00000000] *pgd=00000000
> <0>[ 0.000000] BUG: spinlock lockup on CPU#0, swapper/0
> <0>[ 0.000000] lock: die_lock+0x0/0x10, .magic: dead4ead, .owner:
> swapper/0, .owner_cpu: 0
> <1>[ 0.000000] Unable to handle kernel NULL pointer dereference at
> virtual address 00000000
> <1>[ 0.000000] pgd = c0004000
> <1>[ 0.000000] [00000000] *pgd=00000000
> <0>[ 0.000000] BUG: spinlock lockup on CPU#0, swapper/0
> <0>[ 0.000000] lock: die_lock+0x0/0x10, .magic: dead4ead, .owner:
> swapper/0, .owner_cpu: 0
> [repeat several more times]
>
> In this case, the stacktrace is being saved via a call to kmemleak_free in
> free_bootmem. The sections have not yet been initialized so there is a crash
> in virt_to_page when accessing the section data.
>
> I don't see an easy workaround for this right now unless we want to restrict
> sp_addr_valid until later in bootup.
Thanks for testing, I was able to reproduce the problem. It is easily
fixed by replacing page_to_pfn(virt_to_page(x)) with
__phys_to_pfn(__virt_to_phys(x)) to avoid touching the page structs at
all.
^ permalink raw reply
* [RFC v2 13/18] ARM: OMAP2+: AM33XX: timer: Interchance clkevt and clksrc timers
From: Jon Hunter @ 2013-01-24 22:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1356959231-17335-14-git-send-email-vaibhav.bedia@ti.com>
Hi Vaibhav,
On 12/31/2012 07:07 AM, Vaibhav Bedia wrote:
> AM33XX has two timers (DTIMER0/1) in the WKUP domain.
> On GP devices the source of DMTIMER0 is fixed to an
> inaccurate internal 32k RC oscillator and this makes
> the DMTIMER0 practically either as a clocksource or
> as clockevent.
>
> Currently the timer instance in WKUP domain is used
> as the clockevent and the timer in non-WKUP domain
> as the clocksource. DMTIMER1 in WKUP domain can keep
> running in suspend from a 32K clock fed from external
> OSC and can serve as the persistent clock for the kernel.
> To enable this, interchange the timers used as clocksource
> and clockevent for AM33XX.
I have been thinking about this some more. In the case where we are
using gptimers for both clock-events and clock-source (on both AM33xx
and OMAP) and I am wondering if it makes sense to switch the timers so
that we use the always-on timer for clock-source and a different one
from clock-events.
For OMAP, if we are not using the 32k-sync for clock-source, then we are
never going to achieve low power states during idle as we will always
have one gptimer running. And in this case, to your point below, it
would be better to use the always-on for clock-source so that in suspend
we can at least hit low power states and maintain time.
> For now a new DT property has been added to allow the timer code
> to select the timer with the right property.
>
> It has been pointed out by Santosh Shilimkar and Kevin Hilman
> that such a change will result in soc-idle never being achieved
> on AM33XX. There are other reasons why soc-idle does not look
> feasible on AM33XX so for now we go ahead with the interchange
> of the the timers. If at a later point of time we do come up
> with an approach which makes soc-idle possible on AM33XX, this
> can be revisited.
Right, but this would also be true for OMAP if we don't use the 32k-sync
as we only have one gptimer in the wake-up domain.
Cheers
Jon
^ permalink raw reply
* [PATCH] ARM: OMAP1: fix USB host on 1710
From: Aaro Koskinen @ 2013-01-24 22:24 UTC (permalink / raw)
To: linux-arm-kernel
There is a long-standing bug that OHCI USB host controller does
not respond on 1710, because of wrong clock definitions. See e.g.
http://marc.info/?l=linux-omap&m=119634441229321&w=2. All register reads
return just zeroes:
[ 1.896606] ohci ohci: OMAP OHCI
[ 1.912597] ohci ohci: new USB bus registered, assigned bus number 1
[ 1.933776] ohci ohci: irq 38, io mem 0xfffba000
[ 2.012573] ohci ohci: init err (00000000 0000)
[ 2.030334] ohci ohci: can't start
[ 2.046661] ohci ohci: startup error -75
[ 2.063201] ohci ohci: USB bus 1 deregistered
After some experiments, it seems that when changing the usb_dc_ck /
SOFT_REQ enable bit from USB_REQ_EN_SHIFT to SOFT_USB_OTG_DPLL_REQ_SHIFT
(like done also on 7XX), the USB appears to work:
[ 2.183959] ohci ohci: OMAP OHCI
[ 2.198242] ohci ohci: new USB bus registered, assigned bus number 1
[ 2.215820] ohci ohci: irq 38, io mem 0xfffba000
[ 2.324798] hub 1-0:1.0: USB hub found
[ 2.361267] hub 1-0:1.0: 3 ports detected
The patch is tested on Nokia 770.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
---
arch/arm/mach-omap1/clock_data.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index cb7c6ae..6c4f766 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -543,15 +543,6 @@ static struct clk usb_dc_ck = {
/* Direct from ULPD, no parent */
.rate = 48000000,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
- .enable_bit = USB_REQ_EN_SHIFT,
-};
-
-static struct clk usb_dc_ck7xx = {
- .name = "usb_dc_ck",
- .ops = &clkops_generic,
- /* Direct from ULPD, no parent */
- .rate = 48000000,
- .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
};
@@ -727,8 +718,7 @@ static struct omap_clk omap_clks[] = {
CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
- CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
- CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
+ CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
--
1.7.10.4
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: omap3-overo: Add support for pwm-leds
From: Florian Vaussard @ 2013-01-24 21:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <51016A84.20703@ti.com>
Hi
>>
>>>> I am working on a patch for pwm-twl-led to defer using a workqueue right now.
>>>
>>> Great!
>>> The only thing I worry about is the latency we are going to get with the
>>> workqueue.
>>>
>>
>> If the latency becomes critical, we can create our own workqueue.
>
> Hrm, when we handled the led via gpio-leds it was also going through the same
> path at the end, via i2c to twl4030.
> I think the fix for this is going to be needed in the pwm core level. Just
> need to look at the gpio code to have similar handling of might_sleep interfaces.
>
You are right. But then the pwm core must provide a way to know if the
pwm access function are callable
from atomic context or not (the gpio framework provides gpio_cansleep()).
This implies a good amount of changes to the pwm framework, and
currently we are the only driver using
non-atomic access.
I will take a closer look to the complexity of this solution tomorrow.
Florian
^ permalink raw reply
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